AT90USBKey Hardware User Guide - Atmel Corporation - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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AT90USBKey
.............................................................................................
Hardware User Guide
AT90USBKey Hardware User Guide User Guide 1
7627A–AVR–04/06
Section 1
Introduction ........................................................................................... 1-3
1.1 Overview ...................................................................................................1-3
1.2 AT90USBKey Features............................................................................1-4
Section 2
Using the AT90USBKey ....................................................................... 2-5
2.1 Overview ...................................................................................................2-5
2.2 Power Supply ............................................................................................2-6
2.3 Reset.........................................................................................................2-8
2.4 On-board Resources.................................................................................2-9
2.5 In-System Programming .........................................................................2-13
2.6 Debugging...............................................................................................2-14
Section 3
Troubleshooting Guide ....................................................................... 3-15
Section 4
Technical Specifications ..................................................................... 4-16
Section 5
Technical Support............................................................................... 5-17
Section 6
Complete Schematics......................................................................... 6-18
AT90USBKey Hardware User Guide 1-3
7627A–AVR–04/06
Section 1
Introduction
Congratulations on acquiring the AVR® AT90USBKey. This kit is designed to give
designers a quick start to develop code on the AVR® and for prototyping and testing of
new designs with the AT90USB microcontroller family.
1.1 Overview
This document describes the AT90USBKey dedicated to the AT90USB AVR
microcontroller. This board is designed to allow an easy evaluation of the product using
demonstration software.
To increase its demonstrative capabilities, this stand alone board has numerous onboard
resources: USB, joystick, data-flash and temperature sensor.
Figure 1-1 . AT90USBKey
Introduction
1-4 AT90USBKey Hardware User Guide
7627A–AVR–04/06
1.2 AT90USBKey Features
The AT90USBKey provides the following features:
AT90USB QFN64
AVR Studio® software interface (1)
USB software interface for Device Firmware Upgrade (DFU bootloader) (2)
Power supply flagged by “VCC-ON” LED:
– regulated 3.3V
– from an external battery connector (for reduced host or OTG operation)
– from the USB interface (USB device bus powered application)
JTAG interface (connector not mounted):
– for on-chip ISP
– for on-chip debugging using JTAG ICE
Serial interfaces:
– 1 USB full/low speed device/host/OTG interface
On-board resources:
– 4+1-ways joystick
– 2 Bi-Color LEDs
– temperature sensor
– serial dataflash memories
– all microcontroller I/O ports access on 2x8pin headers (not mounted)
On-board RESET button
On-board HWB button to force bootloader section execution at reset.
System clock:
– 8 MHz crystal
Notes: 1. The AVRUSBKey is supported by AVR Studio®, version 4.12 or higher. For up-todate
information on this and other AVR tool products, please consult our web site.
The most recent version of AVR Studio®, AVR tools and this User Guide can be
found in the AVR section of the Atmel web site, http://www.atmel.com.
2. ATMEL Flip®, In System Programming Version 3 or Higher shall be used for Device
Firmware Upgrade. Please consult Atmel web site to retrieve the latex version of Flip
and the DFU bootloader Hex file if needed.
AT90USBKey Hardware User Guide 2-5
7627A–AVR–04/06
Section 2
Using the AT90USBKey
This chapter describes the AVRUSBKey and all its resources.
2.1 Overview
Figure 2-1 . AT90USBKey Overview
Using the AT90USBKey
2-6 AT90USBKey Hardware User Guide
7627A–AVR–04/06
2.2 Power Supply
2.2.1 Power Supply Sources
The on-board power supply circuitry allows two power supply configurations:
from USB connector
from battery connector
USB powered When used as a USB device bus powered application, the AVRUSBKey can be directly
powered via the USB VBUS power supply line.
Battery powered The external battery connector should be used when the AT90USBKey is used as a
USB host. This mode allows the AT90USBKey to provide a 5V power supply from its
VBUS pin.
– Need of a female battery clip
– Input supply from 8 up to 15V DC (min. 100mA)
Figure 2-2 . Power supply schematic
VCC3
IN
1
GND
2
OUT
3
U5
LM340
VBUS
VBAT
D4
LL4148
-
C16
4.7uF
R19
124k 1%
U3out=1.25*(1+(R15+R18)/R19)
100k 1% R18
D3
LL4148
C17
220nF
VCC3
5V
R15
100k 1%
MTA
Ext power supply
1 2
J8
C18
100nF
OUT
1
IN
2
GND
3
OUT
4
FAULT
SHDN 8
7
CC
6
SET
5
U4
LP3982
C15
33nF
D6
LL4148
Using the AT90USBKey
AT90USBKey Hardware User Guide 2-7
7627A–AVR–04/06
2.2.2 VBUS Generator
When using the AT90USB microcontroller in USB host mode, the AT90USBKey should
provide a 5V power supply over the VBUS pin of its USB mini AB connector.
A couple of transistors allows the UVCON pin of the AT90USB to control the VBUS
generation (See Figure 2-3). In this mode the AT90USBKey is powered by external
battery power supply source.
Figure 2-3 . VBUS generator schematic
2.2.3 “POWER-ON“ LED
The POWER-ON LED (“D1”) is always lit when power is applied to AVRUSBKey
regardless of the power supply source.
R25
100k
Q1
BC847B -
C19
4.7uF
R24
10k
M1
FDV304P/FAI
UVCON
5V VBUS
Using the AT90USBKey
2-8 AT90USBKey Hardware User Guide
7627A–AVR–04/06
2.3 Reset
Although the AT90USB has its on-chip RESET circuitry (c.f. AT90USB Datasheet,
section “System Control and Reset), the AVRUSBKey provides to the AT90USB a
RESET signal witch can come from two different sources:
Figure 2-4 . Reset Implementation
2.3.1 Power-on RESET
The on-board RC network acts as power-on RESET.
2.3.2 RESET Push Button
By pressing the RESET push button on the AVRUSBKey, a warm RESET of the
AT90USB is performed.
2.3.3 Main Clock XTAL
To use the USB interface of the AT90USB, the clock source should always be a crystal
or external clock oscillator (the internal 8MHz RC oscillator can not be used to operate
with the USB interface). Only the following crystal frequency allows proper USB
operations: 2MHz, 4MHz, 6MHz, 8MHz, 12MHz, 16MHz. The AT90USBKey comes with
a default 8MHz crystal oscillator.
RST
VCC
R6
47k C8
220nF
RESET
Using the AT90USBKey
AT90USBKey Hardware User Guide 2-9
7627A–AVR–04/06
2.4 On-board Resources
2.4.1 USB
The AVRUSBKey is supplied with a standard USB mini A-B receptacle. The mini AB
receptacle allows to connect both a mini A plug or a mini B plug connectors.
Figure 2-5 . USB mini A-B Receptacle
When connected to a mini B plug, the AT90USB operates as an “USB device” (the ID
pin of the plug is unconnected) and when connected to a mini A plug, the AT90USB
operates as a “USB host” (the ID pin of the A plug is tied to ground).
2.4.2 Joystick
The 4+1 ways joystick offers an easy user interface implementation for a USB
application (it can emulate mouse movements, keyboard inputs...).
Pushing the push-button causes the corresponding signal to be pulled low, while
releasing (not pressed) causes an H.Z state on the signal. The user must enable
internal pull-ups on the microcontroller input pins, removing the need for an external
pull-up resistors on the push-button.
Figure 2-6 . Joystick Schematic
C7
1uF
VBUS
R4 0
GND
VBUS
1-V_BUS
3-D+
2-D-
4-ID
5-GND
SHIELD
USB_MiniAB
J3
VBUS
VBUS
GND
R3 22
R2 22
D+
DUID
CR1 CR2
UCAP
Select
5
Lef t
7
Up
3
Right
6
Down
4
Com1
1
Com2
2
SW3
TPA511G
PE[7..0]
PB[7..0]
PB5
PB6
PB7
PE4
PE5
Using the AT90USBKey
2-10 AT90USBKey Hardware User Guide
7627A–AVR–04/06
2.4.3 LEDs
The AT90USBKey includes 2 bi-color LEDs (green/red) implemented on one line. They
are connected to the high nibble of “Port D” of AT90USB (PORTD[4..7]).
To light on a LED, the corresponding port pin must drive a high level. To light off a LED,
the corresponding port pin must drive a low level.
Figure 2-7 . LEDs Implementation schematic
Table 2-1 . Leds references
2.4.4 Temperature Sensor
The temperature sensor uses a thermistor (R29), or temperature-sensitive resistor. This
thermistor have a negative temperature coefficient (NTC), meaning the resistance goes
up as temperature goes down. Of all passive temperature measurement sensors,
thermistors have the highest sensitivity (resistance change per degree of temperature
change). Thermistors do not have a linear temperature/resistance curve.
The voltage over the NTC can be found using the A/D converter (connected to channel
0). See the AT90USB Datasheet for how to use the ADC. The thermistor value (RT) is
calculate with the following expression:
Where: RT = Thermistor value (Ω) at T temperature (°Kelvin)
RH = Second resistor of the bridge -100 KΩ ±10% at 25°C
VADC0 = Voltage value on ADC-0 input (V)
VCC = Board power supply
LED Reference AT90USB Connection Color
D2 PORTD.4 Red
PORTD.5 Green
D5 PORTD.6 Green
PORTD.7 Red
D2
D5
1k R14
1k R17
LEDs In-line Grouped LEDs
PD4
PD5
PD7
PD[7..0]
PD6
1k R22
1k R23
RT (RH ⋅ VADC0) VCC VADC0 – = ⁄ ( )
Using the AT90USBKey
AT90USBKey Hardware User Guide 2-11
7627A–AVR–04/06
The NTC thermistor used in AT90USBKey has a resistance of 100 KΩ ±5% at 25°C (T0)
and a beta-value of 4250 ±3%. By the use of the following equation, the temperature (T)
can be calculated:
Where: RT = Thermistor value (Ω) at T temperature (°Kelvin)
ß = 4250 ±3%
R0 = 100 KΩ ±5% at 25°C
T0 = 298 °K (273 °K + 25°K)
The following cross table also can be used. It is based on the above equation.
Table 2-2 . Thermistor Values versus Temperature
Temp.
(°C)
RT
(KΩ)
Temp.
(°C)
RT
(KΩ)
Temp.
(°C)
RT
(KΩ)
Temp.
(°C)
RT
(KΩ)
-20 1263,757 10 212,958 40 50,486 70 15,396
-19 1182,881 11 201,989 41 48,350 71 14,851
-18 1107,756 12 191,657 42 46,316 72 14,329
-17 1037,934 13 181,920 43 44,380 73 13,828
-16 973,006 14 172,740 44 42,537 74 13,347
-15 912,596 15 164,083 45 40,781 75 12,885
-14 856,361 16 155,914 46 39,107 76 12,442
-13 803,984 17 148,205 47 37,513 77 12,017
-12 755,175 18 140,926 48 35,992 78 11,608
-11 709,669 19 134,051 49 34,542 79 11,215
-10 667,221 20 127,555 50 33,159 80 10,838
-9 627,604 21 121,414 51 31,840 81 10,476
-8 590,613 22 115,608 52 30,580 82 10,128
-7 556,056 23 110,116 53 29,378 83 9,793
-6 523,757 24 104,919 54 28,229 84 9,471
-5 493,555 25 100,000 55 27,133 85 9,161
-4 465,300 26 95,342 56 26,085 86 8,863
-3 438,854 27 90,930 57 25,084 87 8,576
-2 414,089 28 86,750 58 24,126 88 8,300
-1 390,890 29 82,787 59 23,211 89 8,035
0 369,145 30 79,030 60 22,336 90 7,779
1 348,757 31 75,466 61 21,498 91 7,533
2 329,630 32 72,085 62 20,697 92 7,296
3 311,680 33 68,876 63 19,930 93 7,067
4 294,826 34 65,830 64 19,196 94 6,847
T β
RT
R0
⎝ ln-------⎠
⎛ ⎞ β
T0
+ ------
= -------------------------------
Using the AT90USBKey
2-12 AT90USBKey Hardware User Guide
7627A–AVR–04/06
Figure 2-8 . Thermistor Schematic
2.4.5 Data Flash memory
For mass-storage class demonstration purpose, the AT90USBKey provides two on-chip
serial Flash memories (AT45DB642D) connected to the AT90USB Serial Port Interface
(SPI).
The data-flash chip select signals are connected to PortE bit 0 and bit 1 of the AT90USB
(See Figure 2-9).
Figure 2-9 . On-board data flash schematic
5 278,995 35 62,937 65 18,493 95 6,635
6 264,119 36 60,188 66 17,820 96 6,430
7 250,134 37 57,576 67 17,174 97 6,233
8 236,981 38 55,093 68 16,556 98 6,043
9 224,606 39 52,732 69 15,964 99 5,860
Temp.
(°C)
RT
(KΩ)
Temp.
(°C)
RT
(KΩ)
Temp.
(°C)
RT
(KΩ)
Temp.
(°C)
RT
(KΩ)
PF[7..0]
R29
R27
100k
PF0
VCC
PE0
VCC3
VCC3
PB[7..0]
PB1
R9
100k
RESET
PB3
PB2
SI
1
SCK
2
RESET
3
CS
4
WP
VCC 5
GND 6
SO 7
8
U2
AT45DB642D CASON8
PE1
VCC3
VCC3
RESET
PB1
R10
100k
PB3
PB2
SI
1
SCK
2
RESET
3
CS
4
WP
VCC 5
GND 6
SO 7
8
U3
AT45DB642D CASON8
R12
100k
R11
100k
Using the AT90USBKey
AT90USBKey Hardware User Guide 2-13
7627A–AVR–04/06
2.5 In-System Programming
2.5.1 Programming with USB bootloader: DFU (Device Firmware Upgrade)
AT90USB part comes with a default factory pre-programmed USB bootloader located in
the on-chip boot section of the AT90USB. This is the easiest and fastest way to
reprogram the device directly over the USB interface. The “Flip” PC side application, is
available from the Atmel website, offers a flexible an user friendly interface to reprogram
the application over the USB bus.
The HWB pin of the AT90USB allows to force the bootloader section execution after
reset. (Refer to AT90USB datasheet section “boot loader support”). To force bootloader
execution, operate as follow:
Press both “RST” and “HWB” push buttons
First release the “RST” push button
Release the “HWB” push button
For more information about the USB bootloader and “Flip” application, please refer to
the “USB bootloader datasheet document” and “Flip’s user manual”.
Note: The HWB pin is active only if the HWBE fuse is set (default factory configuration).
2.5.2 Programming with AVR JTAGICEmKII
The AT90USB can be programmed using specific JTAG link. To use the AVR
JTAGICEmkII with an AT90USBKey an optional HE10 connector should be soldered to
J9 footprint. Then the JTAG probe can be connected to the AT90USBKey as shown in
Figure 2-10.
Note: When the JTAGEN Fuse is unprogrammed, the four TAP pins are normal port pins, and
the TAP controller is in reset. When programmed, the input TAP signals are internally
pulled high and the JTAG is enabled for Boundary-scan and programming. The
AT90USB device is shipped with this fuse programmed.
Using the AT90USBKey
2-14 AT90USBKey Hardware User Guide
7627A–AVR–04/06
Figure 2-10 . Connecting AVR JTAG ICE to AVRUSBKey
The Flash, EEPROM and all Fuse and Lock Bit options ISP-programmable can be
programmed individually or with the sequential automatic programming option.
Note: See AVR Studio® on-line Help for information.
2.6 Debugging
2.6.1 Debugging with AVR JTAG ICE mkII
The AT90USBKey can be used for debugging with JTAG ICE MK II.
Connect the JTAG ICE mkII as shown in Figure 2-10, for debugging, please refer to
AVR Studio® Help information.
When using JTAG ICE MK II for debugging, and as AT90USB parts are factory
configured with the higher security level set, a chip erase operation will be performed on
the part before debugging. Thus the on-chip flash bootloader will be erased. It can be
restored after the debug session using the bootloader hex file available from ATMEL
website.
AT90USBKey Hardware User Guide 3-15
7627A–AVR–04/06
Section 3
Troubleshooting Guide
Figure 3-1 . Troubleshooting Guide
Problem Reason Solution
The Green “VCC-ON”
LED is not on
No power supply
Verify the power supply source (check
AVRUSBKey does not battery charge or USB connection).
work
The AT90USB cannot be
programmed
The AVR JTAG ICE
probe is not
connected
Connect the JTAG ICE 10-PIN header to
the correct AVRUSBKey JTAG header
(page 13)
The memory lock bits
are programmed
Erase the memory before programming
with JTAG ICE.
The fuse bits are
wrongly programmed
Check the fuse bits with JTAG ICE
Can not connect to
USB bootloader
Force bootloader execution with HWB
under reset.
USB bootloader erased after a JTAG
debugging session: reprogram the USB
bootloader with JTAG.
AVR Studio does not
detect the AVR JTAG
ICE.
Serial/USB cable is
not connected, or
power is off
Connect serial cable to RS232 (STK500 -
AVR ISP) and check power connections
Connect serial cable to USB (JATG ICE
MKII, AVR ISPmkIIl) and check power
connections
PC COM port is in
use
Disable other programs that are using
PC COM port.
Change PC COM port
AVR Studio does not
detect COM port.
Disable COM port auto-detection in AVR
Studio file menu. Force COM port to
correct COM port
AT90USBKey Hardware User Guide 4-16
7627A–AVR–04/06
Section 4
Technical Specifications
System Unit
– Physical Dimensions.....................................................L=90 x W=30 x H=8 mm
– Weight ...........................................................................................................12 g
Operating Conditions
– Internal Voltage Supply ............................................................................... 3.3V
– External Voltage Supply .........................................................................8V -15V
Connections
– USB Connector ......................................................................Mini AB receptacle
– USB Communications .......................................................Full speed/low speed
– JTAG Connector.................................................... Footprint for HE10 connector
– All ports connectors.............................................................J1, J2, J4, J5, J6, J7
– Battery connector ....................................................................... MTA right angle
AT90USBKey Hardware User Guide 5-17
7627A–AVR–04/06
Section 5
Technical Support
For Technical support, please contact avr@atmel.com. When requesting technical
support, please include the following information:
Which target AVR device is used (complete part number)
Target voltage and speed
Clock source and fuse setting of the AVR
Programming method (ISP, JTAG or specific Boot-Loader)
Hardware revisions of the AVR tools, found on the PCB
Version number of AVR Studio. This can be found in the AVR Studio help menu.
PC operating system and version/build
PC processor type and speed
A detailed description of the problem
AT90USBKey Hardware User Guide 6-18
7627A–AVR–04/06
Section 6
Complete Schematics
On the next pages, the following documents of AT90USBKey are shown:
Complete schematics,
Bill of materials.
Complete Schematics
AT90USBKey Hardware User Guide 6-19
7627A–AVR–04/06
Figure 6-1 . Schematics, 1 of 2
C7
1uF
C3216-A
VBUS
RST
RST
DTSM-3
AVCC
PD[7..0] PD[7..0]
PA0
UCAP Capacitor
Closed to the MCU
VCC
PA1
R4 0
R0603
PE0
PF7
PE2
PE1
PE4
PE3
PE6
PE[7..0]
PE5
1
1
2
2 3
3
4
4 5
5
6
6 7
7
8
8 9
9
10
10
J2
1.27 mm Dual
H1.27-10
PE7
PA3
UGND
(not mounted)
PE2
VCC
PA[7..0]
PF0
PA2
RESET
PA4
PF2
Reset Circuit
UVCON
VBUS
PA5
HWB
HWB
DTSM-3
R1 0
R0603
PF4
RESET
UGND
R8 0
R0603
PA6
AGND
C1
100nF
C0603
PF1
UCAP
PA7
(not mounted)
(not mounted)
(not mounted)
PF3
PE2
PF[7..0]
PC7
R5 0
R0603
VCC
C9
220nF
C0603
(not mounted)
PE4
VCC
PB[7..0] PB[7..0]
PE5
PC6
VCC AVCC
C2
100nF
C0603
GND
Title
Size Document Number Rev
Date: Sheet of
1.0.0
CPU
A4
Monday , January 09, 2006 1 2
PE6
PF6
PC5
PD0
PD2
PD1
PD4
PD3
PD6
PD[7..0]
PD5
(not mounted)
1
1
2
2 3
3
4
4 5
5
6
6 7
7
8
8 9
9
10
10
J4
1.27 mm Dual
H1.27-10
PD7
PC4
QFN64
VCC
PB0
VCC
Ferrite & capacitors
closed to the MCU
PB0
PB2
PB1
PB4
PB1 PB3
PB6
PB[7..0]
PB5
1
1
2
2 3
3
4
4 5
5
6
6 7
7
8
8 9
9
10
10
J6
1.27 mm Dual
H1.27-10
PB7
PA0
1-V_BUS
3-D+
2-D-
4-ID
5-GND
SHIELD
USB_MiniABF
J3
MINI_USBC
PA2
PA1
PA4
PA3
PA6
PA[7..0]
PB2
PA5
PC3
PF[7..0]
1
1
2
2 3
3
4
4 5
5
6
6 7
7
8
8 9
9
10
10
J7
1.27 mm Dual
H1.27-10
PA7
R6
47k
R0603
PE7
2
UVcc
3
D-
4
D+
5
UGND
6
UCAP
7
VBUS
8
PE3
9
PB0
10
PB1
11
PB2
12
PB3
13
PB4
14
PB5
15
PB6
16
PB7
17
PD0
25
PD1
26
PD2
27
PD3
28
PD4
29
PD5
30
PD6
31
PD7
32
PE4
18
PE5
19
AREF
62
RESET
20
GND
53
GND
63
GND
22
XTAL2
23
XTAL1
24
PE0
PE1 33
34
PE6
1
PE2
43
PC0
PC1 35
PC2 36
PC3 37
PC4 38
PC5 39
PC6 40
PC7 41
42
PA7
PA6 44
PA5 45
PA4 46
PA3 47
48
PA2
PA1 49
PA0 50
51
PF7
PF6 54
PF5 55
PF4 56
PF3 57
PF2 58
PF1 59
PF0 60
61
VCC
52
VCC
21
AVCC
64
AT90USB128
U1
QFN64
PB3
UVCON PE7
C5
100nF
C0603
VCC
DECOUPLING CAPACITORS
CLOSED TO THE DEVICE
VBUS MCU Pin3
PC2
PB4
Y1 8MHz CRYSTAL
8MHz
49US
C11
15pF
C0603
C10
15pF
C0603
PC1
PB5
PC0
PC2
PC1
PC4
PC3
PC6
PC[7..0]
PC5
1
1
2
2 3
3
4
4 5
5
6
6 7
7
8
8 9
9
10
10
J5
1.27 mm Dual
H1.27-10
PC7
VBUS
AREF
PC0
PB6
PE[7..0]
PE1
PB7
VCC
PF0
PE0
C8
220nF
C0603
UGND UGND
PC[7..0] PC[7..0]
C3
100nF
C0603
GND
PF1
R3 22
R0603
R7
47k
R0603
R2 22
R0603
RESET
D+
C4
100nF
C0603
DUID
PE3
PF2
A90USB Key
VCC
GND
PD0
XTAL2
PD1
PD2
PF5
PF3
PD3
AGND
CR1
PGB0010603
R0603
CR2
PGB0010603
R0603
PD4
XTAL1
VCC
PD5
1
1
2
2 3
3
4
4 5
5
6
6 7
7
8
8 9
9
10
10
J1
1.27 mm Dual
H1.27-10
PD6
DECOUPLING CAPACITORS
CLOSED TO THE DEVICE
MCU Pin52
RESISTORS
CLOSED TO THE DEVICE
PD7
PF4
VCC
XTAL2
VCC
UCAP
PF7
UVCC
D+ D- RESISTORS
Closed to the MCU
PF5
Bootloader Activation
C6
100nF
C0603
VCC
PA[7..0]
VCC
AREF
DECOUPLING CAPACITORS
CLOSED TO THE DEVICE
MCU Pin21
PF6
XTAL1
Complete Schematics
6-20 AT90USBKey Hardware User Guide
7627A–AVR–04/06
Figure 6-2 . Schematics, 2 of 2
PE0
VCC3
!!! R21 not mounted
D2
IN
1
GND
2
OUT
3
U5
LM340
-
C14
4.7uF
VCC3
When mounting R21:
R20 not mounted
U4 not mounted
Allows to generate 3.3V
from U1 internal regulator
CAUTION: R21 default not mounted !!!
VBUS generator f or OTG/HOST mode
1 F 1.0.0
Power & Interf aces
A4
Saturday , February 18, 2006 2 2
1k R17
LEDs In-line Grouped LEDs
PD4
PD5
PD7
PD[7..0]
PD6
1k R22
C17
220nF
VBat Mon.
VCC
1k R23
VCC3
-
C19
4.7uF
5V
PE1
VCC3
VCC3
VCC3
DECOUPLING CAPACITOR
CLOSE TO THE DEVICE
C13
100nF
RESET
PB1
R10
100k
PB3
PB2
SI
1
SCK
2
RESET
3
CS
4
WP
VCC 5
GND 6
SO 7
8
U3
AT45DB642D CASON8
R12
100k
R24
10k
R15
100k 1%
MTA
Ext power supply
1 2
J8
C18
100nF
VCC
OUT
1
IN
2
GND
3
OUT
4
FAULT
SHDN 8
7
CC
6
SET
5
U4
LP3982
C15
33nF
R11
100k
(not mounted)
M1
D6 FDV304P/FAI
LL4148
R16
0 R20
0
UCAP
UVCON
R21
0
VCC
VBUS
Complete Schematics
AT90USBKey Hardware User Guide 6-21
7627A–AVR–04/06
Table 6-1 . Bill of material
Item Q.ty Reference Part
Tech.
Characteristics Package
1 2 CR1,CR2 ESD protection (PGB0010603)
2 10 C1,C2,C3,C4,C5,C6,C12,
C13, C18, C20
100nF 50V-10% Ceramic CASE 0603
3 1 C7 1uF 10Vmin ±10% EIA/IECQ 3216
4 3 C8,C9, C17 220nF 50V-10% Ceramic CASE 0603
5 2 C10, C11 15pF 50V-5% Ceramic CASE 0603
6 3 C14, C16, C19 4.7uF 10Vmin ±10% EIA/IECQ 3216
7 1 C15 33nF 50V-5% Ceramic CASE 0603
8 2 D2,D5 LED BI-COLOUR/ LSGT670 I=10 mA_ PLCC-4
9 1 D1 TOPLED/ LPM676-K2M1 I=10 mA_ PLCC-2
10 2 D3,D4 DII LL4148-7 i=200mA max LL-34
11 1 J3 USB mini AB receptacle Surface mount
12 0 J9 CON 2x5 (2.54mm) (Not Mounted)
13 0 J1,J2,J4,J5,J6,J7 1.27 mm Dual header (Not Mounted)
14 1 J8 Connector MTA 2 cts right angle
15 1 M1 FDV304P/FAI SOT23
16 1 Q1 BC847B IC peak=200mA SOT23
17 2 R2,R3 22 1/16W-5% SMD CASE 0603
18 1 R5 68k 1/16W-5% SMD CASE 0603
19 2 R6,R7 47k 1/16W-5% SMD CASE 0603
20 7 R1,R4,R5,R8,R16,R20, R26 0 CASE 0603
21 0 R21 0 (Not Mounted) CASE 0603
22 1 R28 220k 1/16W-5% SMD CASE 0603
23 7 R9,R10,R11,R12,R25,R27,R3
0
100k 1/16W-5% SMD CASE 0603
24 5 R13,R14,R17,R22,R23 1k 1/16W-5% SMD CASE 0603
25 2 R24,R28 10k 1/16W-5% SMD CASE 0603
26 1 R29 NCP18WF104J03RB 100K - ß=4250 CASE 0603
27 2 R15,R18 100k 1% 1/16W-1% SMD CASE 0603
28 1 R19 120k 1% 1/16W-1% SMD CASE 0603
29 2 SW1,SW2 PUSH-BUTTON / DTSM31N 6x3.5mm - 1.6N See DS
30 1 SW3 TPA511G 4 ways joystick + center CMS mount
31 1 U1 AT90USB1287 QFN64
32 2 U2,U3 AT45DB642D CASON8
33 1 U4 LP3982IMM-ADJ Vin Max 6V, 300mA MSOP8
34 1 U6 LM340MP5.0
35 1 Y1 8MHz CRYSTAL H=4mm HC49/4H
Printed on recycled paper.
7627A–AVR–04/06 /xM
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SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
Dependable Texas Instruments Quality and
Reliability
description/ordering information
These devices contain six independent inverters.
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
SN5404 . . . J PACKAGE
SN54LS04, SN54S04 . . . J OR W PACKAGE
SN7404, SN74S04 . . . D, N, OR NS PACKAGE
SN74LS04 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
2Y
2A
VCC
3A
3Y
4A
1Y
6A
6Y
GND
5Y
5A
4Y
SN5404 . . . W PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
6Y
NC
5A
NC
5Y
2A
NC
2Y
NC
3A
SN54LS04, SN54S04 . . . FK PACKAGE
(TOP VIEW)
1Y
1A
NC
4Y
4A 6A
3Y
GND
NC
NC − No internal connection
VCC
!" #!$% & "'
&! #" #" (" " ") !"
& & * +' &! # " , &" " " %+ %!&"
" , %% # " " '
#&! #% - ./.010 %% # " " " " "&
!%" ("* " "&' %% (" #&! #&!
# " , &" " " %+ %!&" " , %% # " " '
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TA PACKAGE† ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tube SN7404N SN7404N
PDIP − N Tube SN74LS04N SN74LS04N
Tube SN74S04N SN74S04N
Tube SN7404D
7404
Tape and reel SN7404DR
SOIC − D
Tube SN74LS04D
LS04
0°C to 70°C
Tape and reel SN74LS04DR
0 70 Tube SN74S04D
S04
Tape and reel SN74S04DR
Tape and reel SN7404NSR SN7404
SOP − NS Tape and reel SN74LS04NSR 74LS04
Tape and reel SN74S04NSR 74S04
SSOP − DB Tape and reel SN74LS04DBR LS04
Tube SN5404J SN5404J
Tube SNJ5404J SNJ5404J
CDIP − J
Tube SN54LS04J SN54LS04J
Tube SN54S04J SN54S04J
Tube SNJ54LS04J SNJ54LS04J
−55°C to 125°C Tube SNJ54S04J SNJ54S04J
Tube SNJ5404W SNJ5404W
CFP − W Tube SNJ54LS04W SNJ54LS04W
Tube SNJ54S04W SNJ54S04W
LCCC − FK
Tube SNJ54LS04FK SNJ54LS04FK
Tube SNJ54S04FK SNJ54S04FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H L
L H
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
logic diagram (positive logic)
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
Y = A
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics (each gate)
Input A
VCC
Output Y
GND
130 Ω
1 kΩ
1.6 kΩ
’04
4 kΩ
Input
A
VCC
Output
Y
GND
20 kΩ 120 Ω
’LS04
8 kΩ
12 kΩ
1.5 kΩ
3 kΩ
4 kΩ
Input
A
VCC
Output
Y
GND
2.8 kΩ 900 Ω
’S04
50 Ω
3.5 kΩ
250 Ω
500 Ω
Resistor values shown are nominal.
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN5404 SN7404
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 16 16 mA
TA Operating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST SN5404 SN7404
CONDITIONS‡
UNIT
MIN TYP§ MAX MIN TYP§ MAX
VIK VCC = MIN, II = − 12 mA −1.5 −1.5 V
VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V
II VCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VI = 2.4 V 40 40 μA
IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA
IOS¶ VCC = MAX −20 −55 −18 −55 mA
ICCH VCC = MAX, VI = 0 V 6 12 6 12 mA
ICCL VCC = MAX, VI = 4.5 V 18 33 18 33 mA
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC = 5 V, TA = 25°C.
¶ Not more than one output should be shorted at a time.
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
FROM
TO
SN5404
PARAMETER
SN7404 (INPUT)
(OUTPUT) TEST CONDITIONS
MIN TYP MAX
UNIT
tPLH
A Y RL = 400 Ω, CL = 15 pF
12 22
ns
tPHL
8 15
recommended operating conditions (see Note 3)
SN54LS04 SN74LS04
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 4 8 mA
TA Operating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS†
SN54LS04 SN74LS04
UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIK VCC = MIN, II = − 18 mA −1.5 −1.5 V
VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V
VOL VCC = MIN, VIH = 2 V
IOL = 4 mA 0.25 0.4 0.4
V
IOL = 8 mA 0.25 0.5
II VCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 20 μA
IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA
IOS§ VCC = MAX −20 −100 −20 −100 mA
ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA
ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)
FROM
TO
SN54LS04
PARAMETER
SN74LS04 (INPUT)
(OUTPUT) TEST CONDITIONS
MIN TYP MAX
UNIT
tPLH
A Y RL = 2 kΩ, CL = 15 pF
9 15
ns
tPHL
10 15
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
recommended operating conditions (see Note 3)
SN54S04 SN74S04
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −1 −1 mA
IOL Low-level output current 20 20 mA
TA Operating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS†
SN54S04 SN74S04
UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIK VCC = MIN, II = − 18 mA −1.2 −1.2 V
VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V
II VCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VI = 2.7 V 50 50 μA
IIL VCC = MAX, VI = 0.5 V −2 −2 mA
IOS§ VCC = MAX −40 −100 −40 −100 mA
ICCH VCC = MAX, VI = 0 V 15 24 15 24 mA
ICCL VCC = MAX, VI = 4.5 V 30 54 30 54 mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
FROM
TO
SN54S04
PARAMETER
SN74S04 (INPUT)
(OUTPUT) TEST CONDITIONS
MIN TYP MAX
UNIT
tPLH
A Y RL = 280 Ω, CL = 15 pF
3 4.5
ns
tPHL
3 5
tPLH
A Y RL = 280 Ω, CL = 50 pF
4.5
ns
tPHL
5
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 AND 54S/74S DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time, with one input transition per measurement.
S1
S2
tPHZ
tPZL tPLZ
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D)
≈1.5 V
VOH − 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
tw
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOH
VOL
Figure 1. Load Circuits and Voltage Waveforms
SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time, with one input transition per measurement.
S1
S2
tPHZ
tPZL tPLZ
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D) ≈1.5 V
VOH − 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tw
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOL
VOH
Figure 2. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
JM38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00105BCA
JM38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00105BDA
JM38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07003BCA
JM38510/07003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07003BDA
JM38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
30003B2A
JM38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003BCA
JM38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003BDA
JM38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003SCA
JM38510/30003SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003SDA
M38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00105BCA
M38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00105BDA
M38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07003BCA
M38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
30003B2A
M38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003BCA
M38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003BDA
M38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003SCA
M38510/30003SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003SDA
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2014
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5404J
SN54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS04J
SN54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S04J
SN7404D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404N ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N
SN7404N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70
SN7404NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N
SN74LS04D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04J OBSOLETE CDIP J 14 TBD Call TI Call TI 0 to 70
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2014
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LS04N ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N
SN74LS04N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70
SN74LS04NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N
SN74LS04NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04
SN74LS04NSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04
SN74S04D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04
SN74S04DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04
SN74S04DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04
SN74S04DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04
SN74S04DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04
SN74S04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04
SN74S04N ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N
SN74S04N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70
SN74S04NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N
SN74S04NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04
SN74S04NSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04
SN74S04NSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04
SNJ5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404J
SNJ5404W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404W
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2014
Addendum-Page 4
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SNJ54LS04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS
04FK
SNJ54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04J
SNJ54LS04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04W
SNJ54S04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S
04FK
SNJ54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04J
SNJ54S04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2014
Addendum-Page 5
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5404, SN54LS04, SN54LS04-SP, SN54S04, SN7404, SN74LS04, SN74S04 :
• Catalog: SN7404, SN74LS04, SN54LS04, SN74S04
• Military: SN5404, SN54LS04, SN54S04
• Space: SN54LS04-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
SN7404DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74S04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74S04NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN7404DR SOIC D 14 2500 367.0 367.0 38.0
SN74LS04DR SOIC D 14 2500 367.0 367.0 38.0
SN74S04DR SOIC D 14 2500 367.0 367.0 38.0
SN74S04NSR SO NS 14 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
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TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
1FEATURES
1
2
3
4 5
6
7
8
2IN+
2IN–
2OUT
V
CC+
V
CC–
1IN+
1IN–
1OUT
NE5532, NE5532A . . . D, P, OR PS PACKAGE
SA5532, SA5532A . . . D OR P PACKAGE
(TOP VIEW)
DESCRIPTION/ORDERING INFORMATION
NE5532, NE5532A
SA5532, SA5532A
www.ti.com................................................................................................................................................... SLOS075I–NOVEMBER 1979–REVISED APRIL 2009
DUAL LOW-NOISE OPERATIONAL AMPLIFIERS
· Equivalent Input Noise Voltage:
5 nV/√Hz Typ at 1 kHz
· Unity-Gain Bandwidth: 10 MHz Typ
· Common-Mode Rejection Ratio: 100 dB Typ
· High DC Voltage Gain: 100 V/mV Typ
· Peak-to-Peak Output Voltage Swing 26 V Typ
With VCC± = ±15 V and RL = 600 Ω
· High Slew Rate: 9 V/ms Typ
The NE5532, NE5532A, SA5532, and SA5532A are high-performance operational amplifiers combining excellent
dc and ac characteristics. They feature very low noise, high output-drive capability, high unity-gain and
maximum-output-swing bandwidths, low distortion, high slew rate, input-protection diodes, and output
short-circuit protection. These operational amplifiers are compensated internally for unity-gain operation. These
devices have specified maximum limits for equivalent input noise voltage.
ORDERING INFORMATION(1)
TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING
NE5532P NE5532P
PDIP – P Tube of 50
NE5532AP NE5532AP
Tube of 75 NE5532D
N5532
Reel of 2500 NE5532DR
0°C to 70°C SOIC – D
Tube of 75 NE5532AD
N5532A
Reel of 2500 NE5532ADR
NE5532PSR N5532
SOP – PS Reel of 2000
NE5532APSR N5532A
SA5532P SA5532P
PDIP – P Tube of 50
SA5532AP SA5532AP
Tube of 75 SA5532D
–40°C to 85°C SA5532
Reel of 2500 SA5532DR
SOIC – D
Tube of 75 SA5532AD
SA5532A
Reel of 2500 SA5532ADR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1979–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OUT
VCC–
VCC+
36 pF
37 pF
14 pF
7 pF
15 W
460 W
15 W
IN+
IN–
Component values shown are nominal.
ABSOLUTE MAXIMUM RATINGS(1)
NE5532, NE5532A
SA5532, SA5532A
SLOS075I–NOVEMBER 1979–REVISED APRIL 2009................................................................................................................................................... www.ti.com
SCHEMATIC (EACH AMPLIFIER)
over operating free-air temperature range (unless otherwise noted)
VCC+ 22 V
VCC Supply voltage(2)
VCC– –22 V
Input voltage, either input(2) (3) VCC±
Input current(4) ±10 mA
Duration of output short circuit(5) Unlimited
D package 97°C/W
qJA Package thermal impedance(6) (7) P package 85°C/W
PS package 95°C/W
TJ Operating virtual-junction temperature 150°C
Tstg Storage temperature range –65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
(3) The magnitude of the input voltage must never exceed the magnitude of the supply voltage.
(4) Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless
some limiting resistance is used.
(5) The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the
maximum dissipation rating is not exceeded.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
(7) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) - TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
2 Submit Documentation Feedback Copyright © 1979–2009, Texas Instruments Incorporated
Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
NE5532, NE5532A
SA5532, SA5532A
www.ti.com................................................................................................................................................... SLOS075I–NOVEMBER 1979–REVISED APRIL 2009
MIN MAX UNIT
VCC+ Supply voltage 5 15 V
VCC– Supply voltage –5 –15 V
NE5532, NE5532A 0 70
TA Operating free-air temperature °C
SA5532, SA5532A –40 85
VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
TA = 25°C 0.5 4
VIO Input offset voltage VO = 0 mV
TA = Full range(2) 5
TA = 25°C 10 150
IIO Input offset current nA
TA = Full range(2) 200
TA = 25°C 200 800
IIB Input bias current nA
TA = Full range(2) 1000
VICR Common-mode input-voltage range ±12 ±13 V
V Maximum peak-to-peak output-voltage OPP swing RL ≥ 600 Ω, VCC± = ±15 V 24 26 V
TA = 25°C 15 50
RL ≥ 600 Ω, VO = ±10 V
Large-signal differential-voltage TA = Full range(2) 10 AVD amplification V/mV TA = 25°C 25 100
RL ≥ 2 kΩ, VO±10 V
TA = Full range(2) 15
A Small-signal differential-voltage vd amplification f = 10 kHz 2.2 V/mV
BOM Maximum output-swing bandwidth RL = 600 Ω, VO = ±10 V 140 kHz
B1 Unity-gain bandwidth RL = 600 Ω, CL = 100 pF 10 MHz
ri Input resistance 30 300 kΩ
zo Output impedance AVD = 30 dB, RL = 600 Ω, f = 10 kHz 0.3 Ω
CMRR Common-mode rejection ratio VIC = VICR min 70 100 dB
k Supply-voltage rejection ratio SVR (ΔV VCC± = ±9 V to ±15 V, VO = 0 80 100 dB CC±/ΔVIO)
IOS Output short-circuit current 10 38 60 mA
ICC Total supply curent VO = 0, No load 8 16 mA
Crosstalk attenuation (VO1/VO2) V01 = 10 V peak, f = 1 kHz 110 dB
(1) All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified.
(2) Full temperature ranges are: –40°C to 85°C for the SA5532 and SA5532A, and 0°C to 70°C for the NE5532 and NE5532A.
Copyright © 1979–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A
OPERATING CHARACTERISTICS
NE5532, NE5532A
SA5532, SA5532A
SLOS075I–NOVEMBER 1979–REVISED APRIL 2009................................................................................................................................................... www.ti.com
VCC± = ±15 V, TA = 25°C (unless otherwise noted)
NE5532, SA5532 NE5532A, SA5532A
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
SR Slew rate at unity gain 9 9 V/ms
Overshoot factor VI = 100 mV, RL = 600 Ω, 10 10 % AVD = 1, CL = 100 pF
f = 30 Hz 8 8 10
Vn Equivalent input noise voltage nV/√Hz
f = 1 kHz 5 5 6
f = 30 Hz 2.7 2.7
In Equivalent input noise current pA/√Hz
f = 1 kHz 0.7 0.7
4 Submit Documentation Feedback Copyright © 1979–2009, Texas Instruments Incorporated
Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A
PACKAGE OPTION ADDENDUM
www.ti.com 17-May-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
NE5532AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A
NE5532ADE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A
NE5532ADG4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70
NE5532ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A
NE5532ADRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A
NE5532ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A
NE5532AIP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85
NE5532AP ACTIVE PDIP P 8 50 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 NE5532AP
NE5532APE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 NE5532AP
NE5532APSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A
NE5532APSRE4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A
NE5532APSRG4 ACTIVE SO PS 8 TBD Call TI Call TI 0 to 70
NE5532D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532
NE5532DE4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70
NE5532DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532
NE5532DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 N5532
NE5532DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532
NE5532DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532
PACKAGE OPTION ADDENDUM
www.ti.com 17-May-2014
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
NE5532IP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85
NE5532P ACTIVE PDIP P 8 50 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 NE5532P
NE5532PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 NE5532P
NE5532PSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532
NE5532PSRE4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532
NE5532PSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532
SA5532AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A
SA5532ADE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85
SA5532ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A
SA5532ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A
SA5532ADRE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85
SA5532ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A
SA5532AP ACTIVE PDIP P 8 50 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 85 SA5532AP
SA5532APE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 85 SA5532AP
SA5532D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532
SA5532DE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85
SA5532DG4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85
SA5532DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532
SA5532DRE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85
PACKAGE OPTION ADDENDUM
www.ti.com 17-May-2014
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SA5532DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532
SA5532P ACTIVE PDIP P 8 50 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 85 SA5532P
SA5532PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 85 SA5532P
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 17-May-2014
Addendum-Page 4
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
NE5532ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE5532APSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
NE5532DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
NE5532DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE5532DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
NE5532PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SA5532ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SA5532DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
NE5532ADR SOIC D 8 2500 340.5 338.1 20.6
NE5532APSR SO PS 8 2000 367.0 367.0 38.0
NE5532DR SOIC D 8 2500 364.0 364.0 27.0
NE5532DR SOIC D 8 2500 340.5 338.1 20.6
NE5532DRG4 SOIC D 8 2500 340.5 338.1 20.6
NE5532PSR SO PS 8 2000 367.0 367.0 38.0
SA5532ADR SOIC D 8 2500 340.5 338.1 20.6
SA5532DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Oct-2013
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
LM386
LM386 Low Voltage Audio Power Amplifier
Literature Number: SNAS545A
LM386
Low Voltage Audio Power Amplifier
General Description
The LM386 is a power amplifier designed for use in low voltage
consumer applications. The gain is internally set to 20 to
keep external part count low, but the addition of an external
resistor and capacitor between pins 1 and 8 will increase the
gain to any value from 20 to 200.
The inputs are ground referenced while the output automatically
biases to one-half the supply voltage. The quiescent
power drain is only 24 milliwatts when operating from a 6 volt
supply, making the LM386 ideal for battery operation.
Features
n Battery operation
n Minimum external parts
n Wide supply voltage range: 4V–12V or 5V–18V
n Low quiescent current drain: 4mA
n Voltage gains from 20 to 200
n Ground referenced input
n Self-centering output quiescent voltage
n Low distortion: 0.2% (AV = 20, VS = 6V, RL = 8W, PO =
125mW, f = 1kHz)
n Available in 8 pin MSOP package
Applications
n AM-FM radio amplifiers
n Portable tape player amplifiers
n Intercoms
n TV sound systems
n Line drivers
n Ultrasonic drivers
n Small servo drivers
n Power converters
Equivalent Schematic and Connection Diagrams
DS006976-1
Small Outline,
Molded Mini Small Outline,
and Dual-In-Line Packages
DS006976-2
Top View
Order Number LM386M-1,
LM386MM-1, LM386N-1,
LM386N-3 or LM386N-4
See NS Package Number
M08A, MUA08A or N08E
August 2000
LM386 Low Voltage Audio Power Amplifier
© 2000 National Semiconductor Corporation DS006976 www.national.com
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
(LM386N-1, -3, LM386M-1) 15V
Supply Voltage (LM386N-4) 22V
Package Dissipation (Note 3)
(LM386N) 1.25W
(LM386M) 0.73W
(LM386MM-1) 0.595W
Input Voltage ±0.4V
Storage Temperature −65°C to +150°C
Operating Temperature 0°C to +70°C
Junction Temperature +150°C
Soldering Information
Dual-In-Line Package
Soldering (10 sec) +260°C
Small Outline Package
(SOIC and MSOP)
Vapor Phase (60 sec) +215°C
Infrared (15 sec) +220°C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
Thermal Resistance
qJC (DIP) 37°C/W
qJA (DIP) 107°C/W
qJC (SO Package) 35°C/W
qJA (SO Package) 172°C/W
qJA (MSOP) 210°C/W
qJC (MSOP) 56°C/W
Electrical Characteristics (Notes 1, 2)
TA = 25°C
Parameter Conditions Min Typ Max Units
Operating Supply Voltage (VS)
LM386N-1, -3, LM386M-1, LM386MM-1 4 12 V
LM386N-4 5 18 V
Quiescent Current (IQ) VS = 6V, VIN = 0 4 8 mA
Output Power (POUT)
LM386N-1, LM386M-1, LM386MM-1 VS = 6V, RL = 8W, THD = 10% 250 325 mW
LM386N-3 VS = 9V, RL = 8W, THD = 10% 500 700 mW
LM386N-4 VS = 16V, RL = 32W, THD = 10% 700 1000 mW
Voltage Gain (AV) VS = 6V, f = 1 kHz 26 dB
10 μF from Pin 1 to 8 46 dB
Bandwidth (BW) VS = 6V, Pins 1 and 8 Open 300 kHz
Total Harmonic Distortion (THD) VS = 6V, RL = 8W, POUT = 125 mW 0.2 %
f = 1 kHz, Pins 1 and 8 Open
Power Supply Rejection Ratio (PSRR) VS = 6V, f = 1 kHz, CBYPASS = 10 μF 50 dB
Pins 1 and 8 Open, Referred to Output
Input Resistance (RIN) 50 kW
Input Bias Current (IBIAS) VS = 6V, Pins 2 and 3 Open 250 nA
Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee
specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is
given, however, the typical value is a good indication of device performance.
Note 3: For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and 1) a thermal resistance
of 107°C/W junction to ambient for the dual-in-line package and 2) a thermal resistance of 170°C/W for the small outline package.
LM386
www.national.com 2
Application Hints
GAIN CONTROL
To make the LM386 a more versatile amplifier, two pins (1
and 8) are provided for gain control. With pins 1 and 8 open
the 1.35 kW resistor sets the gain at 20 (26 dB). If a capacitor
is put from pin 1 to 8, bypassing the 1.35 kW resistor, the
gain will go up to 200 (46 dB). If a resistor is placed in series
with the capacitor, the gain can be set to any value from 20
to 200. Gain control can also be done by capacitively coupling
a resistor (or FET) from pin 1 to ground.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and frequency
response for individual applications. For example,
we can compensate poor speaker bass response by frequency
shaping the feedback path. This is done with a series
RC from pin 1 to 5 (paralleling the internal 15 kW resistor).
For 6 dB effective bass boost: R . 15 kW, the lowest value
for good stable operation is R = 10 kW if pin 8 is open. If pins
1 and 8 are bypassed then R as low as 2 kW can be used.
This restriction is because the amplifier is only compensated
for closed-loop gains greater than 9.
INPUT BIASING
The schematic shows that both inputs are biased to ground
with a 50 kW resistor. The base current of the input transistors
is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the LM386
is higher than 250 kW it will contribute very little additional
offset (about 2.5 mV at the input, 50 mV at the output). If the
dc source resistance is less than 10 kW, then shorting the
unused input to ground will keep the offset low (about 2.5 mV
at the input, 50 mV at the output). For dc source resistances
between these values we can eliminate excess offset by putting
a resistor from the unused input to ground, equal in
value to the dc source resistance. Of course all offset problems
are eliminated if the input is capacitively coupled.
When using the LM386 with higher gains (bypassing the
1.35 kW resistor between pins 1 and 8) it is necessary to bypass
the unused input, preventing degradation of gain and
possible instabilities. This is done with a 0.1 μF capacitor or
a short to ground depending on the dc source resistance on
the driven input.
LM386
3 www.national.com
Typical Performance Characteristics
Quiescent Supply Current
vs Supply Voltage
DS006976-5
Power Supply Rejection Ratio
(Referred to the Output)
vs Frequency
DS006976-12
Peak-to-Peak Output Voltage
Swing vs Supply Voltage
DS006976-13
Voltage Gain vs Frequency
DS006976-14
Distortion vs Frequency
DS006976-15
Distortion vs Output Power
DS006976-16
Device Dissipation vs Output
Power—4W Load
DS006976-17
Device Dissipation vs Output
Power—8W Load
DS006976-18
Device Dissipation vs Output
Power—16W Load
DS006976-19
LM386
www.national.com 4
Typical Applications
Amplifier with Gain = 20
Minimum Parts
DS006976-3
Amplifier with Gain = 200
DS006976-4
Amplifier with Gain = 50
DS006976-6
Low Distortion Power Wienbridge Oscillator
DS006976-7
Amplifier with Bass Boost
DS006976-8
Square Wave Oscillator
DS006976-9
LM386
5 www.national.com
Typical Applications (Continued)
Note 4: Twist Supply lead and supply ground very tightly.
Note 5: Twist speaker lead and ground very tightly.
Note 6: Ferrite bead in Ferroxcube K5-001-001/3B with 3 turns of wire.
Note 7: R1C1 band limits input signals.
Note 8: All components must be spaced very closely to IC.
Frequency Response with Bass Boost
DS006976-10
AM Radio Power Amplifier
DS006976-11
LM386
www.national.com 6
Physical Dimensions inches (millimeters) unless otherwise noted
SO Package (M)
Order Number LM386M-1
NS Package Number M08A
LM386
7 www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead (0.118” Wide) Molded Mini Small Outline Package
Order Number LM386MM-1
NS Package Number MUA08A
LM386
www.national.com 8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
Dual-In-Line Package (N)
Order Number LM386N-1, LM386N-3 or LM386N-4
NS Package Number N08E
LM386 Low Voltage Audio Power Amplifier
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
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Interface interface.ti.com Security www.ti.com/security
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Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
2-kV ESD Protection for:
− LM224K, LM224KA
− LM324K, LM324KA
− LM2902K, LM2902KV, LM2902KAV
Wide Supply Ranges
− Single Supply . . . 3 V to 32 V
(26 V for LM2902)
− Dual Supplies . . . 1.5 V to 16 V
(13 V for LM2902)
Low Supply-Current Drain Independent of
Supply Voltage . . . 0.8 mA Typ
Common-Mode Input Voltage Range
Includes Ground, Allowing Direct Sensing
Near Ground
Low Input Bias and Offset Parameters
− Input Offset Voltage . . . 3 mV Typ
A Versions . . . 2 mV Typ
− Input Offset Current . . . 2 nA Typ
− Input Bias Current . . . 20 nA Typ
A Versions . . . 15 nA Typ
Differential Input Voltage Range Equal to
Maximum-Rated Supply Voltage . . . 32 V
(26 V for LM2902)
Open-Loop Differential Voltage
Amplification . . . 100 V/mV Typ
Internal Frequency Compensation
description/ordering information
These devices consist of four independent
high-gain frequency-compensated operational
amplifiers that are designed specifically to operate
from a single supply over a wide range of voltages.
Operation from split supplies also is possible if the
difference between the two supplies is 3 V to 32 V
(3 V to 26 V for the LM2902), and VCC is at least
1.5 V more positive than the input common-mode
voltage. The low supply-current drain is
independent of the magnitude of the supply
voltage.
Applications include transducer amplifiers, dc amplification blocks, and all the conventional
operational-amplifier circuits that now can be more easily implemented in single-supply-voltage systems. For
example, the LM124 can be operated directly from the standard 5-V supply that is used in digital systems and
provides the required interface electronics, without requiring additional ±15-V supplies.
PRODUCTION DATA information is current as of publication date. Copyright 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VCC
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
LM124 . . . D, J, OR W PACKAGE
LM124A . . . J OR W PACKAGE
LM224, LM224A, LM224K, LM224KA . . . D OR N PACKAGE
LM324, LM324K . . . D, N, NS, OR PW PACKAGE
LM324A . . . D, DB, N, NS, OR PW PACKAGE
LM324KA . . . D, N, NS, OR PW PACKAGE
LM2902 . . . D, N, NS, OR PW PACKAGE
LM2902K . . . D, DB, N, NS, OR PW PACKAGE
LM2902KV, LM2902KAV . . . D OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4IN+
NC
GND
NC
3IN+
1IN+
NC
VCC
NC
2IN+
LM124, LM124A . . . FK PACKAGE
(TOP VIEW)
1IN−
1OUT
NC
3IN− 4IN−
2IN−
2OUT
NC
NC − No internal connection
3OUT 4OUT
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products,
production processing does not necessarily include testing
of all parameters.
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
VIOmax
AT 25°C
MAX
TESTED
VCC
PACKAGE ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP (N) Tube of 25
LM324N LM324N
LM324KN LM324KN
Tube of 50 LM324D
Reel of 2500 LM324DR LM324
SOIC (D)
Reel of 2500 LM324DRG3
Tube of 50 LM324KD
LM324K
7 mV 30 V
Reel of 2500 LM324KDR
Reel of 2000 LM324NSR LM324
SOP (NS)
Tube of 50 LM324KNS
LM324K
Reel of 2000 LM324KNSR
Tube of 90 LM324PW
L324
TSSOP (PW)
Reel of 2000 LM324PWR
Tube of 90 LM324KPW
L324K
0°C to 70°C
Reel of 2000 LM324KPWR
PDIP (N)
Tube of 25 LM324AN LM324AN
Tube of 25 LM324KAN LM324KAN
Tube of 50 LM324AD
LM324A
SOIC (D)
Reel of 2500 LM324ADR
Tube of 50 LM324KAD
LM324KA
Reel of 2500 LM324KADR
3 mV 30 V
Reel of 2000 LM324ANSR LM324A
SOP (NS)
Tube of 50 LM324KANS
LM324KA
Reel of 2000 LM324KANSR
SSOP (DB) Reel of 2000 LM324ADBR LM324A
Tube of 90 LM324APW
L324A
TSSOP (PW)
Reel of 2000 LM324APWR
Tube of 90 LM324KAPW
L324KA
Reel of 2000 LM324KAPWR
PDIP (N) Tube of 25
LM224N LM224N
LM224KN LM224KN
5 mV 30 V
Tube of 50 LM224D
LM224
SOIC (D)
Reel of 2500 LM224DR
Tube of 50 LM224KD
LM224K
25°C to 85°C
Reel of 2500 LM224KDR
−PDIP (N)
Tube of 25 LM224AN LM224AN
Tube of 25 LM224KAN LM224KAN
3 mV 30 V
Tube of 50 LM224AD
LM224A
SOIC (D)
Reel of 2500 LM224ADR
Tube of 50 LM224KAD
LM224KA
Reel of 2500 LM224KADR
† For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
ORDERING INFORMATION (CONTINUED)
TA
VIOmax
AT 25°C
MAX
TESTED
VCC
PACKAGE† ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP (N)
Tube of 25 LM2902N LM2902N
Tube of 25 LM2902KN LM2902KN
Tube of 50 LM2902D
LM2902
SOIC (D)
Reel of 2500 LM2902DR
Tube of 50 LM2902KD
LM2902K
Reel of 2500 LM2902KDR
Reel of 2000 LM2902NSR LM2902
26 V SOP (NS)
Tube of 50 LM2902KNS
LM2902K
7 mV
Reel of 2000 LM2902KNSR
−40°C to 125°C
SSOP (DB)
Tube of 80 LM2902KDB
L2902K
40 125 Reel of 2000 LM2902KDBR
Tube of 90 LM2902PW
L2902
TSSOP (PW)
Reel of 2000 LM2902PWR
Tube of 90 LM2902KPW
L2902K
Reel of 2000 LM2902KPWR
32 V
SOIC (D) Reel of 2500 LM2902KVQDR L2902KV
TSSOP (PW) Reel of 2000 LM2902KVQPWR L2902KV
2 mV 32 V
SOIC (D) Reel of 2500 LM2902KAVQDR L2902KA
TSSOP (PW) Reel of 2000 LM2902KAVQPWR L2902KA
CDIP (J) Tube of 25 LM124J LM124J
CFP (W) Tube of 25 LM124W LM124W
5 mV 30 V
LCCC (FK) Tube of 55 LM124FK LM124FK
55°C to 125°C
SOIC (D)
Tube of 50 LM124D
−LM124
Reel of 2500 LM124DR
CDIP (J) Tube of 25 LM124AJ LM124AJ
2 mV 30 V CFP (W) Tube of 25 LM124AW LM124AW
LCCC (FK) Tube of 55 LM124AFK LM124AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
symbol (each amplifier)
−
+
IN−
IN+
OUT
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic (each amplifier)
To Other
Amplifiers
≈6-μA
Current
Regulator
VCC
OUT
GND
IN−
IN+
≈100-μA
Current
Regulator
≈50-μA
Current
Regulator
COMPONENT COUNT
(total device)
Epi-FET
Transistors
Diodes
Resistors
Capacitors
1
95
4
11
4
≈6-μA
Current
Regulator
† ESD protection cells - available on LM324K and LM324KA only
†
†
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
LM2902
ALL OTHER
DEVICES UNIT
Supply voltage, VCC (see Note 1) ±13 or 26 ±16 or 32 V
Differential input voltage, VID (see Note 2) ±26 ±32 V
Input voltage, VI (either input) −0.3 to 26 −0.3 to 32 V
Duration of output short circuit (one amplifier) to ground at (or below) TA = 25°C,
VCC ≤ 15 V (see Note 3)
Unlimited Unlimited
D package 86 86
DB package 96 96
Package thermal impedance, θJA (see Notes 4 and 5) N package 80 80 °C/W
NS package 76 76
PW package 113 113
FK package 5.61
Package thermal impedance, JC (see Notes 6 and 7) J package 15.05 °C/W
W package 14.65
Operating virtual junction temperature, TJ 150 150 °C
Case temperature for 60 seconds FK package 260 °C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J or W package 300 300 °C
Storage temperature range, Tstg −65 to 150 −65 to 150 °C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND.
2. Differential voltages are at IN+, with respect to IN−.
3. Short circuits from outputs to VCC can cause excessive heating and eventual destruction.
4. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/JA. Operating at the absolute maximum TJ of 150°C can affect reliability.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) − TC)/JC. Operating at the absolute maximum TJ of 150°C can affect reliability.
7. The package thermal impedance is calculated in accordance with MIL-STD-883.
ESD protection
TEST CONDITIONS TYP UNIT
Human-Body Model LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV ±2 kV
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS† TA
LM124
LM224
LM324
LM324K UNIT
‡
MIN TYP§ MAX MIN TYP§ MAX
V Input offset voltage VCC = 5 V to MAX, 25°C 3 5 3 7
VIO mV
VIC = VICRmin, VO = 1.4 V Full range 7 9
I Input offset current V 1 4 V
25°C 2 30 2 50
IIO VO = 1.4 nA
Full range 100 150
I Input bias current V 1 4 V
25°C −20 −150 −20 −250
IIB VO = 1.4 nA
Full range −300 −500
25°C 0 to
0 to
V Common-mode
V 5 V to MAX
VCC − 1.5
VCC − 1.5
VICR V
input voltage range
VCC = Full range 0 to
0 to
VCC − 2
VCC − 2
RL = 2 kΩ 25°C VCC − 1.5 VCC − 1.5
V High-level
RL = 10 kΩ 25°C
VOH V
output voltage
V MAX
RL = 2 kΩ Full range 26 26
p g
VCC = RL ≥ 10 kΩ Full range 27 28 27 28
VOL
Low-level
output voltage
RL ≤ 10 kΩ Full range 5 20 5 20 mV
A
Large-signal
differential voltage VCC = 15 V, VO = 1 V to 11 V,
25°C 50 100 25 100
AVD V/mV
amplification
RL ≥ 2 kΩ Full range 25 15
CMRR
Common-mode
rejection ratio
VIC = VICRmin 25°C 70 80 65 80 dB
k
Supply-voltage
kSVR rejection ratio 25°C 65 100 65 100 dB
(ΔVCC /ΔVIO)
VO1/VO2
Crosstalk
attenuation
f = 1 kHz to 20 kHz 25°C 120 120 dB
VCC = 15 V,
V 1 V Source
CC 25°C −20 −30 −60 −20 −30 −60
VID = V,
VO = 0
Full range −10 −10
mA
IO Output current VCC = 15 V,
V 1 V Sink
25°C 10 20 10 20
O p CC
VID = −V,
VO = 15 V
Full range 5 5
VID = −1 V, VO = 200 mV 25°C 12 30 12 30 μA
IOS
Short-circuit
output current
VCC at 5 V,
GND at −5 V
VO = 0,
25°C ±40 ±60 ±40 ±60 mA
Supply current
VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2
ICC
(four amplifiers) VCC = MAX,
VO = 0.5 VCC, No load Full range 1.4 3 1.4 3
mA
† All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. MAX VCC for
testing purposes is 26 V for LM2902 and 30 V for the others.
‡ Full range is −55°C to 125°C for LM124, −25°C to 85°C for LM224, and 0°C to 70°C for LM324.
§ All typical values are at TA = 25°C.
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS† T ‡
LM2902 LM2902V
TA UNIT
MIN TYP§ MAX MIN TYP§ MAX
V 5 V t
Non-A-suffix
25°C 3 7 3 7
V Input offset voltage
VCC = to
devices Full range 10 10
VIO MAX,
mV
VIC = VICRmin,
V 1 4 V A-suffix
25°C 1 2
IC ICR
VO = 1.4 devices Full range 4
ΔVIO/ΔT
Input offset voltage
temperature drift
RS = 0 Ω Full range 7 μV/°C
I Input offset current V 1 4 V
25°C 2 50 2 50
IIO VO = 1.4 nA
Full range 300 150
ΔIIO/ΔT
Input offset current
temperature drift
Full range 10 pA/°C
I Input bias current V 1 4 V
25°C −20 −250 −20 −250
IIB VO = 1.4 nA
Full range −500 −500
25°C 0 to
0 to
V Common-mode
V 5 V to MAX
VCC − 1.5
VCC − 1.5
VICR V
input voltage range
VCC = Full range 0 to
0 to
VCC − 2
VCC − 2
RL = 2 kΩ 25°C
V High-level
RL = 10 kΩ 25°C VCC − 1.5 VCC − 1.5
VOH V
output voltage
V MAX
RL = 2 kΩ Full range 22 26
p g
VCC = RL ≥ 10 kΩ Full range 23 24 27
VOL
Low-level
output voltage
RL ≤ 10 kΩ Full range 5 20 5 20 mV
A
Large-signal
differential voltage VCC = 15 V, VO = 1 V to 11 V,
25°C 25 100 25 100
AVD V/mV
amplification
RL ≥ 2 kΩ Full range 15 15
CMRR
Common-mode
rejection ratio
VIC = VICRmin 25°C 50 80 60 80 dB
k
Supply-voltage
kSVR rejection ratio 25°C 50 100 60 100 dB
(ΔVCC /ΔVIO)
VO1/VO2
Crosstalk
attenuation
f = 1 kHz to 20 kHz 25°C 120 120 dB
VCC = 15 V,
V 1 V S
CC 25°C −20 −30 −60 −20 −30 −60
VID = V,
VO = 0
Source
Full range −10 −10
mA
IO Output current VCC = 15 V,
V 1 V Sink
25°C 10 20 10 20
CC
VID = −V,
VO = 15 V
Full range 5 5
VID = −1 V, VO = 200 mV 25°C 30 12 40 μA
IOS
Short-circuit
output current
VCC at 5 V,
GND at −5 V
VO = 0,
25°C ±40 ±60 ±40 ±60 mA
Supply current
VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2
ICC
(four amplifiers) VCC = MAX,
VO = 0.5 VCC, No load Full range 1.4 3 1.4 3
mA
† All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. MAX VCC for
testing purposes is 26 V for LM2902 and 32 V for LM2902V.
‡ Full range is −40°C to 125°C for LM2902.
§ All typical values are at TA = 25°C.
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − MARCH 2010
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS† TA
‡
LM124A LM224A
LM324A,
T LM324KA UNIT
A
MIN TYP§ MAX MIN TYP§ MAX MIN TYP § MAX
V Input offset voltage
VCC = 5 V to 30 V,
25°C 2 2 3 2 3
VIO mV
VIC = VICRmin, VO = 1.4 V Full range 4 4 5
I Input offset current V 1 4 V
25°C 10 2 15 2 30
IIO VO = 1.4 nA
Full range 30 30 75
I Input bias current V 1 4 V
25°C −50 −15 −80 −15 −100
IIB VO = 1.4 nA
Full range −100 −100 −200
V
Common-mode input
V 30 V
25°C
0 to
VCC − 1.5
0 to
VCC − 1.5
0 to
VCC − 1.5
VICR V
voltage range
VCC = Full range
0 to
VCC − 2
0 to
VCC − 2
0 to
VCC − 2
RL = 2 kΩ 25°C VCC − 1.5 VCC − 1.5 VCC − 1.5
VOH High-level output voltage
V 30 V
High RL = 2 kΩ Full range 26 26 26 V
VCC = RL ≥ 10 kΩ Full range 27 27 28 27 28
VOL Low-level output voltage RL ≤ 10 kΩ Full range 20 5 20 5 20 mV
A
Large-signal differential
VCC = 15 V, VO = 1 V to 11 V,
25°C 50 100 50 100 25 100
AVD V/mV
voltage amplification
RL ≥ 2 kΩ Full range 25 25 15
CMRR Common-mode rejection ratio VIC = VICRmin 25°C 70 70 80 65 80 dB
kSVR
Supply-voltage rejection ratio
(ΔVCC /ΔVIO)
25°C 65 65 100 65 100 dB
VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 120 dB
VCC = 15 V,
V 1 V
Source
25°C −20 −20 −30 −60 −20 −30 −60
VID = V,
VO = 0
Full range −10 −10 −10
mA
IO Output current VCC = 15 V,
V 1 V Sink
25°C 10 10 20 10 20
VID = −V,
VO = 15 V
Full range 5 5 5
VID = −1 V, VO = 200 mV 25°C 12 12 30 12 30 μA
IOS Short-circuit output current
VCC at 5 V, GND at −5 V,
VO = 0
25°C ±40 ±60 ±40 ±60 ±40 ±60 mA
Supply current
VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 0.7 1.2
ICC
(four amplifiers) VCC = 30 V, VO = 15 V,
No load
Full range 1.4 3 1.4 3 1.4 3
mA
† All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified.
‡ Full range is −55°C to 125°C for LM124A, −25°C to 85°C for LM224A, and 0°C to 70°C for LM324A.
§ All typical values are at TA = 25°C.
LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V,
LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV
QUADRUPLE OPERATIONAL AMPLIFIERS
SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
operating conditions, VCC = ±15 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
SR Slew rate at unity gain RL = 1 MΩ, CL = 30 pF, VI = ±10 V (see Figure 1) 0.5 V/μs
B1 Unity-gain bandwidth RL = 1 MΩ, CL = 20 pF (see Figure 1) 1.2 MHz
Vn Equivalent input noise voltage RS = 100 Ω, VI = 0 V, f = 1 kHz (see Figure 2) 35 nV/√Hz
VO
−
+
RL CL
VI
VCC+
VCC−
Figure 1. Unity-Gain Amplifier
VO
−
+
100 Ω
VCC+
VCC−
RS
900 Ω
VI = 0 V
Figure 2. Noise-Test Circuit
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-7704301VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7704301VC
A
LM124JQMLV
5962-9950403V9B ACTIVE XCEPT KGD 0 100 TBD Call TI N / A for Pkg Type -55 to 125
5962-9950403VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9950403VC
A
LM124AJQMLV
77043012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043012A
LM124FKB
7704301CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301CA
LM124JB
7704301DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301DA
LM124WB
77043022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043022A
LM124AFKB
7704302CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302CA
LM124AJB
7704302DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302DA
LM124AWB
JM38510/11005BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/11005BCA
LM124ADR OBSOLETE SOIC D 14 TBD Call TI Call TI -55 to 125
LM124AFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043022A
LM124AFKB
LM124AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124AJ
LM124AJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302CA
LM124AJB
LM124AWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302DA
LM124AWB
LM124D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124
LM124DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM124DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124
LM124DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124
LM124FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043012A
LM124FKB
LM124J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124J
LM124JB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301CA
LM124JB
LM124N OBSOLETE PDIP N 14 TBD Call TI Call TI -55 to 125
LM124W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124W
LM124WB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301DA
LM124WB
LM224AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A
LM224ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A
LM224ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A
LM224ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -25 to 85 LM224A
LM224ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A
LM224ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A
LM224AN ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -25 to 85 LM224AN
LM224ANE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -25 to 85 LM224AN
LM224D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224
LM224DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224
LM224DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM224DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -25 to 85 LM224
LM224DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224
LM224DRG3 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM -25 to 85 LM224
LM224DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224
LM224KAD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA
LM224KADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA
LM224KADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA
LM224KADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA
LM224KADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA
LM224KADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA
LM224KAN ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -25 to 85 LM224KAN
LM224KANE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -25 to 85 LM224KAN
LM224KDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K
LM224KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K
LM224KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K
LM224KN ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -25 to 85 LM224KN
LM224KNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -25 to 85 LM224KN
LM224N ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -25 to 85 LM224N
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 4
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM224NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -25 to 85 LM224N
LM2902D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902
LM2902DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902
LM2902DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902
LM2902DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LM2902
LM2902DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902
LM2902DRG3 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM -40 to 125 LM2902
LM2902DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902
LM2902KAVQDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA
LM2902KAVQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA
LM2902KAVQPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA
LM2902KAVQPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA
LM2902KD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
LM2902KDB ACTIVE SSOP DB 14 80 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KDBE4 ACTIVE SSOP DB 14 80 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KDBG4 ACTIVE SSOP DB 14 80 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KDE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
LM2902KDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 5
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM2902KDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
LM2902KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
LM2902KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
LM2902KN ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 125 LM2902KN
LM2902KNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 125 LM2902KN
LM2902KNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
LM2902KNSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
LM2902KNSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K
LM2902KPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K
LM2902KVQDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV
LM2902KVQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV
LM2902KVQPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV
LM2902KVQPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 6
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM2902N ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 125 LM2902N
LM2902NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 125 LM2902N
LM2902NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902
LM2902NSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902
LM2902PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902
LM2902PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902
LM2902PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902
LM2902PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 125
LM2902PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L2902
LM2902PWRE4 ACTIVE TSSOP PW 14 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902
LM2902PWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM -40 to 125 L2902
LM2902PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902
LM2902QN OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 125
LM324AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
LM324ADBR ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 7
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM324ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM324A
LM324ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324AN ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 LM324AN
LM324ANE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 LM324AN
LM324ANSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A
LM324APW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A
LM324APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A
LM324APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A
LM324APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
LM324APWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 L324A
LM324APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A
LM324APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A
LM324D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324
LM324DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 8
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM324DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324
LM324DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM324
LM324DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324
LM324DRG3 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM 0 to 70 LM324
LM324DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324
LM324KAD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KAN ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 LM324KAN
LM324KANE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 LM324KAN
LM324KANSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KANSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KANSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA
LM324KAPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA
LM324KAPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 9
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM324KAPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA
LM324KAPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA
LM324KAPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA
LM324KAPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA
LM324KD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KDE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KN ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 LM324KN
LM324KNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 LM324KN
LM324KNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KNSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KNSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K
LM324KPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K
LM324KPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K
LM324KPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 10
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM324KPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K
LM324KPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K
LM324KPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K
LM324N ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 LM324N
LM324NE3 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU SN N / A for Pkg Type 0 to 70 LM324N
LM324NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type 0 to 70 LM324N
LM324NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324
LM324NSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324
LM324NSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324
LM324PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324
LM324PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324
LM324PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324
LM324PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI 0 to 70
LM324PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 L324
LM324PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324
LM324PWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM 0 to 70 L324
LM324PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324
LM324Y OBSOLETE DIESALE Y 0 TBD Call TI Call TI
M38510/11005BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/11005BCA
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 11
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM124, LM124-SP, LM124M, LM2902 :
• Catalog: LM124, LM124
• Automotive: LM2902-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 12
• Enhanced Product: LM2902-EP
• Military: LM124M, LM124M
• Space: LM124-SP, LM124-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LM124DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM224ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
LM224ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM224ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM224ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM224DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM224DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
LM224KADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM224KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM2902DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM2902DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM2902DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
LM2902DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM2902KAVQPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM2902KAVQPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM2902KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM2902KNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
LM2902KPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Oct-2013
Pack Materials-Page 1
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LM2902KVQPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM2902KVQPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM2902NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
LM2902PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM2902PWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
LM2902PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM324ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
LM324ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
LM324ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM324ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM324ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
LM324APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
LM324APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM324APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM324DR SOIC D 14 2500 330.0 16.4 6.55 9.05 2.1 8.0 16.0 Q1
LM324DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
LM324DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM324DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
LM324DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM324KADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM324KANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
LM324KAPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM324KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM324KNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
LM324KPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM324PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM324PWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
LM324PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Oct-2013
Pack Materials-Page 2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM124DR SOIC D 14 2500 367.0 367.0 38.0
LM224ADR SOIC D 14 2500 364.0 364.0 27.0
LM224ADR SOIC D 14 2500 333.2 345.9 28.6
LM224ADRG4 SOIC D 14 2500 333.2 345.9 28.6
LM224ADRG4 SOIC D 14 2500 367.0 367.0 38.0
LM224DR SOIC D 14 2500 367.0 367.0 38.0
LM224DRG3 SOIC D 14 2500 364.0 364.0 27.0
LM224KADR SOIC D 14 2500 367.0 367.0 38.0
LM224KDR SOIC D 14 2500 367.0 367.0 38.0
LM2902DR SOIC D 14 2500 333.2 345.9 28.6
LM2902DR SOIC D 14 2500 367.0 367.0 38.0
LM2902DRG3 SOIC D 14 2500 364.0 364.0 27.0
LM2902DRG4 SOIC D 14 2500 333.2 345.9 28.6
LM2902KAVQPWR TSSOP PW 14 2000 367.0 367.0 35.0
LM2902KAVQPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
LM2902KDR SOIC D 14 2500 367.0 367.0 38.0
LM2902KNSR SO NS 14 2000 367.0 367.0 38.0
LM2902KPWR TSSOP PW 14 2000 367.0 367.0 35.0
LM2902KVQPWR TSSOP PW 14 2000 367.0 367.0 35.0
LM2902KVQPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Oct-2013
Pack Materials-Page 3
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM2902NSR SO NS 14 2000 367.0 367.0 38.0
LM2902PWR TSSOP PW 14 2000 367.0 367.0 35.0
LM2902PWRG3 TSSOP PW 14 2000 364.0 364.0 27.0
LM2902PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
LM324ADBR SSOP DB 14 2000 367.0 367.0 38.0
LM324ADR SOIC D 14 2500 364.0 364.0 27.0
LM324ADR SOIC D 14 2500 367.0 367.0 38.0
LM324ADRG4 SOIC D 14 2500 367.0 367.0 38.0
LM324ANSR SO NS 14 2000 367.0 367.0 38.0
LM324APWR TSSOP PW 14 2000 364.0 364.0 27.0
LM324APWR TSSOP PW 14 2000 367.0 367.0 35.0
LM324APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
LM324DR SOIC D 14 2500 385.0 388.0 194.0
LM324DR SOIC D 14 2500 364.0 364.0 27.0
LM324DR SOIC D 14 2500 333.2 345.9 28.6
LM324DRG3 SOIC D 14 2500 364.0 364.0 27.0
LM324DRG4 SOIC D 14 2500 333.2 345.9 28.6
LM324KADR SOIC D 14 2500 367.0 367.0 38.0
LM324KANSR SO NS 14 2000 367.0 367.0 38.0
LM324KAPWR TSSOP PW 14 2000 367.0 367.0 35.0
LM324KDR SOIC D 14 2500 367.0 367.0 38.0
LM324KNSR SO NS 14 2000 367.0 367.0 38.0
LM324KPWR TSSOP PW 14 2000 367.0 367.0 35.0
LM324PWR TSSOP PW 14 2000 367.0 367.0 35.0
LM324PWRG3 TSSOP PW 14 2000 364.0 364.0 27.0
LM324PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Oct-2013
Pack Materials-Page 4
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
7,90 9,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
16 20
6,50 6,50
14
0,05 MIN
5,90 5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 0,15 M
0°–8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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User's Guide
SLAU295A–September 2009–Revised October 2012
TLV320AIC3254EVM-U
This User’s Guide describes the operation, use, features and characteristics of the TLV320AIC3254EVMU.
This small form factor evaluation module (EVM) is a programmable USB audio device that features the
TLV320AIC3254 Audio Codec with miniDSP.
Figure 1. TLV321AIC3254EVM-U Angle View
The following related documents are available through the Texas Instruments Web site at www.ti.com.
EVM-Compatible Device Data Sheets
Device Literature Number
TLV320AIC3254 SLAS549
TAS1020B SLES025
Contents
1 EVM Overview ............................................................................................................... 3
2 EVM Description and Basics .............................................................................................. 4
3 AIC3254EVM-U Control Software ........................................................................................ 7
Appendix A TLV320AIC3254EVM Schematic ............................................................................... 15
Appendix B TLV320AIC3254EVM Bill of Materials ......................................................................... 16
Appendix C Writing Scripts ..................................................................................................... 18
List of Figures
1 TLV321AIC3254EVM-U Angle View ..................................................................................... 1
2 Bottom and Top Views ..................................................................................................... 4
3 Default Input and Output Signals ......................................................................................... 5
4 Sounds and Audio Devices Properties................................................................................... 6
5 Main Panel Window ........................................................................................................ 8
6 Compatibility Tab............................................................................................................ 9
7 Playback Configurations and Controls.................................................................................. 10
8 Associated Script and Description ...................................................................................... 10
9 Tip Strip Example.......................................................................................................... 11
10 Status Flags Panel ........................................................................................................ 12
11 Register Tables Panel .................................................................................................... 13
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 1
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12 Command Line interface Panel.......................................................................................... 14
List of Tables
1 TLV320AIC3254EVM Bill of Materials .................................................................................. 16
2 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012
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www.ti.com EVM Overview
1 EVM Overview
1.1 Features
• Small USB Stick form factor EVM for the TLV320AIC3254 Audio Codec.
• USB connection to the PC provides power, control and streaming audio for easy evaluation.
• Pre-programmed EEPROM boots the TLV320AIC3254 as a fully functional USB Audio Device when
connected to a PC.
• Easy to use AIC3254 Control Software (CS) configures and controls the TLV320AIC3254.
The TLV320AIC3254EVM-U is a universal serial bus (USB)-based audio device for use with a personal
computer running the Microsoft Windows™ XP operating system
1.2 Introduction
The TLV320AIC3254EVM-U is a USB Audio Device with programmable inputs and outputs, effects and
extensive routing capabilities. It is a simple platform to evaluate the TLV320AIC3254 miniDSP Audio
Codec.
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 3
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EVM Description and Basics www.ti.com
2 EVM Description and Basics
This section provides information on the analog input and output, digital control, power, and general
connection of the TLV320AIC3254EVM-U.
2.1 TLV320AIC3254EVM-U Hardware Description
The TLV320AIC3254EVM-U has 2 stereo analog input connectors (Line-in and Mic-in) and 2 stereo
analog output connectors (Line-Out and Headphone-Out) that are routed to the TLV320AIC3254. Digital
audio as well as control data communicated between the PC and the EVM are interpreted by the
TAS1020B USB Streaming Controller. Control data is communicated to the TLV320AIC3254 via the I2C
protocol; audio data is communicated via the I2S protocol.
An on-board 32KB EEPROM is capable of storing TLV320AIC3254 commands (scripts) as well as the
TAS1020B firmware. A push button is provided to cycle between scripts along with an LED that provides
the user feedback regarding the script that is currently loaded. The EEPROM Manager in the AIC3254 CS
is used to write new scripts into the EEPROM.
Figure 2. Bottom and Top Views
4 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012
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The table below summarizes the audio jacks available to connect analog inputs and outputs to the
TLV320AIC3254, as well as a switch.
Designator Label Associated Pin Description
J1 L IN (LINE IN) IN2_L / IN2_R Line Input.
External electric
microphone input.
J2 MIC IN (MIC IN) IN3_L / IN3_R MICBIAS is connected to
both tip and ring through
resistors.
Line output. Only high
impedance loads should
J3 L OUT (LINE OUT) LOL / LOR be connected to this
output (e.g. external
Class-D amplifier).
J4 HP OUT (HEADPHONE) HPL / HPR Headphone output.
Cycles through scripts
SW1 SW1 N/A loaded in the on-board
EEPROM.
2.2 Getting Started
Evaluation can start right out of the box. Simply connect the TLV320AIC3254EVM-U to an available USB
port, connect stereo headphones to HP OUT and start playing audio with any media player. By default,
when the TLV320AIC3254EVM-U is connected, the TLV320AIC3254 is automatically configured to play
and record stereo audio through all four jacks, as shown below.
Figure 3. Default Input and Output Signals
To adjust playback volume, open “Sounds and Audio Devices” in the “Control Panel” and click the
“Volume” button of the “Sound playback” section of the “Audio” tab. Ensure USB-miniEVM is selected as
the default playback and recording device.
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 5
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Figure 4. Sounds and Audio Devices Properties
Pressing SW1 on the EVM once will set a flat response at the outputs (LED D1 blinks once). Pressing
SW1 again will switch to bass and treble boost (LED D1 blinks twice).
The following section explains the software installation procedure which allows programming of the audio
device.
6 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012
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www.ti.com AIC3254EVM-U Control Software
3 AIC3254EVM-U Control Software
The AIC3254 Control Software (CS) is an intuitive, easy-to-use, powerful tool to learn, evaluate, and
control the TLV320AIC3254. This tool was specifically designed to make learning the TLV320AIC3254
software easy. The following sections describe the operation and installation of this software
NOTE: For configuration of the codec, the TLV320AIC3254 block diagram located in SLAS549 is a
good reference to help determine the signal routing.
3.1 AIC3254EVM-U CS Setup
This section provides setup instructions for the AIC3254EVM-U CS.
To install the AIC3254EVM-U software:
1. Download the latest version of the AIC3254EVM-U Control Software (CS) located in the
TLV320AIC3254EVM-U Product Folder.
2. Open the self-extracting installation file.
3. Extract the software to a known folder.
4. Install the EVM software by double-clicking the Setup executable, and follow the directions. The user
may be prompted to restart their computer.
This installs all the AIC3254EVM-U software and required drivers onto the PC.
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 7
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3.2 AIC3254EVM-U CS Usage
The following sections describe the AIC3254EVM-U CS usage.
3.2.1 Main Panel Window The Firmware Name and Version boxes provide
The Main Panel window, shown in the figure below, information about the firmware loaded into the EVM's
provides easy access to all the features of the EEPROM.
AIC3254 CS. The USB-MODEVM Interface drop-down menu allows
the user to select which communication protocol the
TAS1020B USB Controller uses to communicate with
the TLV320AIC3254.
The TLV320AIC3254 supports I2C Standard, I2C Fast,
and 8-bit register SPI. However, this EVM only
supports I2C. The USB Interface selection is global to
all panels, including the Command-Line Interface.
The Panel Selection Tree provides access to typical
configurations, features, and other panels that allow
the user to control the TLV320AIC3254.
The tree is divided into several categories which
contain items that pop up panels. A panel can be
opened by double-clicking any item inside a category
in the Panel Selection Tree.
Below the Panel Selection Tree are three buttons that
pop up the following:
• Status Flags - Allows the user to monitor the
TLV320AIC3254 status flags.
• Register Tables - A tool to monitor register pages.
• Command-Line Interface - A tool to
execute/generate scripts and monitor register
activity.
The USB LED indicates if the EVM is recognized by
the software and the ACTIVITY LED illuminates every
time a command request is sent.
The dialog box at the bottom of the Main Panel
provides feedback of the current status of the
software.
Figure 5. Main Panel Window
8 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012
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If running the software in Windows Vista or Windows 7, right-click the AIC3254EVM-U CS shortcut and select
Properties. Configure the Compatibility tab as shown in Figure 6
Figure 6. Compatibility Tab
3.2.2 Typical Configurations
This category can help users to quickly become familiar with the TLV320AIC3254. Each of the panels that
can be accessed through this menu have controls relevant to the selected configuration; a tab shows the
script that will be loaded for that particular configuration. Each script includes a brief description of the
selected configuration.
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 9
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Figure 7. Playback Configurations and Controls
Figure 8. Associated Script and Description
3.2.3 Control Categories
The Digital Settings, Analog Settings, and Signal Processing categories provide control of many registers
and other features of the TLV320AIC3254 . These categories are intended for the advanced user.
Hovering the mouse cursor on top of a control displays a tip strip that contains page, register, and bit
information. As an example, hovering on top of IN1_R of the Audio Inputs panel, as shown in Figure 9
displays p1_r55_b7-6 which means that this control writes to Page 1/Register 55/Bits D7 to D6.
10 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012
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Figure 9. Tip Strip Example
Before changing a control, see the data sheet to ensure that a particular control is compatible with the
current state of the codec. As an example, some controls in the Analog Setup panel must be modified in a
particular order as described in the data sheet. Other controls must only be modified with a specific
hardware setup, such as powering up the AVDD LDO.
All controls update their status with respect to the register contents in the following conditions:
• A panel is opened.
• The Execute Command Buffer button in the Command-Line Interface is pressed (if enabled).
• The Refresh button at the bottom right of a panel is pressed
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 11
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3.2.4 Status Flags Panel
The TLV320AIC3254 status flags can monitored in the Status Flags panel (Figure 10) which is located
below in the Panel Selection Tree . Pressing the POLL button continuously reads all the registers relevant
to each flag and updates those flags accordingly. The rate at which the registers are read can be modified
by changing the value in the Polling Interval numeric control. Note that a smaller interval reduces
responsiveness of other controls, especially volume sliders, due to bandwidth limitations. By default, the
polling interval is 200 ms and can be set to a minimum of 20 ms. The Sticky Flags tab contains indicators
whose corresponding register contents clear every time a read is performed to that register. To read all
the sticky flags, click the Read Sticky Flags button.
Figure 10. Status Flags Panel
12 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012
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3.2.5 Register Tables Panel
The contents of configuration and coefficient pages of the TLV320AIC3254 can be accessed through the
Register Tables panel (Figure 11). The Page Number control changes to the page to be displayed in the
register table. The register table contains page information such as the register name, reset value, current
value, and a bitmap of the current value. The contents of the selected page can be exported into a
spreadsheet by clicking the Dump to Spreadsheet button.
Figure 11. Register Tables Panel
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 13
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3.2.6 Command-line Interface Panel
The Command-Line Interface panel provides a means to communicate with the TLV320AIC3254 using a
simple scripting language (described in Appendix C). The TAS1020B USB Controller handles all
communication between the PC and the TLV320AIC3254. A script is loaded into the command buffer,
either by loading a script file using the File menu or by pasting text from the clipboard using the Ctrl-V key
combination (Figure 12). When the command buffer is executed, the return data packets which result from
each individual command are displayed in the Command History control. This control is an array (with a
maximum size of 100 elements) that contains information about each command as well as status. The
Interface box displays the interface used for a particular command in the Command History array. The
Command box displays the type of command executed (i.e., write, read) for a particular interface. The
Flag Retries box displays the number of read iterations performed by a Wait for Flag command (see
Appendix C for details). The Register Data array displays the register number and data bytes that
correspond to a particular command. The Information tab provides additional information related to the
Command History as well as additional settings. The Syntax and Examples tabs provide useful information
related to the scripting language.
The File menu provides some options for working with scripts. The first option, Open Script File..., loads a
command file script into the command buffer. This script can then be executed by pressing the Execute
Command Buffer button. The contents of the Command Buffer can be saved using the Save Script File...
option.
Both the Command Buffer and Command History can be cleared by clicking their corresponding Clear
buttons
Figure 12. Command Line interface Panel
14 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012
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www.ti.com
Appendix A TLV320AIC3254EVM Schematic
The schematic diagram for the TLV320AIC3254EVM is provided as a reference.
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM Schematic 15
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
DOUT
DIN
WCLK
BCLK
MCLK
SCLK
SDA
SCL
RESET~
DESIGN LEAD: EDGE #:
DATE:
FILENAME:
SCH REV:
PCB REV:
SHEET: OF:
LEAD # DRAWN BY:
PAGE INFO: TI
FILENAME
DATE OF
BY
SHEET
REV
REV
C12
0402
0.1ufd/6.3V
C16
0603
10ufd/6.3V
GND
TLV320AIC3254RHB
U1
QFN32-RHB
25 26 27 28 29 30 31 32
6
8
4
1
2
3
5
7
16 15 14 13 12 11 10 9
21
24
22
23
19
20
18
17
C15
0805
22ufd/6.3V
C11
0402
0.1ufd/6.3V
GND
GND
GND
C5
0603
0.47ufd/16V
C6
0603
0.47ufd/16V
GND
C13
0603
.047ufd/25V
C9
0603
1.0ufd/16V
C14
0603
.047ufd/25V
C8
0603
1.0ufd/16V
GND
GND GND
C10
0805
22ufd/6.3V
C7
0402
0.1ufd/6.3V
GND
GND
GND
C1
0603
0.47ufd/16V
C2
0603
0.47ufd/16V
C3
0603
10ufd/6.3V
GND
R4
0603
4.7K
+3.3V
+3.3V
+3.3V
J1
LEFT
RIGHT
Shield
2
4
1
3
6
5
J2
LEFT
RIGHT
Shield
2
4
1
3
6
5
J3
LEFT
RIGHT
Shield
2
4
1
3
6
5
J4
LEFT
RIGHT
Shield
2
4
1
3
6
5
C17
1210
100ufd/6.3V
C18
1210
100ufd/6.3V
R1
0603
1.2K
R2
0603
1.2K
C4
0402
0.1ufd/6.3V
TLV320AIC3254RHB
U1
41
40
39
38
37
36
35
34
33
QFN32-RHB
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C35
0603
10ufd/6.3V
R3
100
0603
R5
100
0603
TLV320AIC3254_RHB_USB_EVM
TLV320AIC3254_RHB_USB_EVM
STEVE LEGGIO
JULY 09, 2009
B
B
1 4
TLV320AIC3254_RHB_USB_EVM SL
LINE IN
MIC IN
LINE OUT
HEADPHONE
6508852
SDA
SCL
DOUT
WCLK
BCLK
DIN
MCLK
SCLK
RESET~
LEAD #
TI
FILENAME
DATE OF
DRAWN BY
SHEET
PCB REV
SCH REV
BY:
SHEET: OF:
REV:
REV:
FILENAME:
DATE:
DESIGN LEAD: EDGE #:
PAGE INFO: U2
13 14 15 17 18 19 20 22
31
30
29
27
26
25
23 24
32
34
35
36
40 39 38 37
21
8
4
28
16
33
42 41
12
11
10
9
7
6
5
45 44 43
2
1
48
3
47 46
R9
0603
1.50K
C26
0603
47pfd/50v
C27
0603
47pfd/50v
C22
0603
1000pfd/50V
1
2
3
4
5
6
7
8
J5
TYPEA_SMT-RA
NC
NC
CASE
CASE
Data+
GND
+5V
Data-
R12
0603
100K
C30
0603
1.0ufd/16V
C28
0402
0.1ufd/6.3V
C25
0402
0.1ufd/6.3V
C29
0402
0.1ufd/6.3V
C24
0402
0.1ufd/6.3V
D1
0805
Yellow
C23
0805
100pfd/50V
C19
0402
0.1ufd/6.3V
+3.3V
GND
GND
GND
GND
GND
GND GND GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
+3.3V
+3.3V
+3.3V +3.3V
+3.3V
+3.3V
+3.3V
+5V
+5V +3.3V
GND GND GND GND
C33
0603
0.1ufd/50V
C34
0805
10ufd/16V
C32
0805
10ufd/16V
1
2 3
4
Y1
SMT-8002
6MHz/3.3V
Vcc
OUT
OE
GND
GND
+3.3V
1 2
SW1
GND
C31
0603
0.1ufd/50V
R14
0603
10K
+3.3V
GND
+5V
VR1
5
3
2
1
SOT230DBV5
3.3V/400mA
4
1
2
3
4 5
6
7
8
U3
MSOP8-DGK
R13
0603
649
R8
0603
30.9K
R10
0603
27.4
R11
0603
27.4
R6
0603
2.7K/5%
R7
0603
2.7K/5%
EEPROM
USB INPUT
+5.0V USB INPUT
+3.3V OUTPUT
POWER SUPPLY
TLV320AIC3254_RHB_USB_EVM SL
2 4
B
B
JULY 09, 2009
STEVE LEGGIO
TLV320AIC3254_RHB_USB_EVM
TLV320AIC3254_RHB_USB_EVM
GPIO
6508852
www.ti.com
Appendix B TLV320AIC3254EVM Bill of Materials
The complete bill of materials for the TLV320AIC3254EVM is provided as a reference.
Table 1. TLV320AIC3254EVM Bill of Materials
PCB
Qty Value Ref Des Description Vendor Part number
1 U1 ULTRA LO PWR ST AUDIO CODEC Texas TLV320AIC3254
W/EMBEDDED MINI DSP QFN32- Instruments RHB
RHB ROHS
RESISTORS
Qty Value Ref Des Description Vendor Part number
1 1.5k R9 RESISTOR SMD0603 1.50K OHM DIGI-KEY P1.50KHCT
1% THICK FILM 1/10W ROHS
3 100k R3,R5,R12 RESISTOR SMD0603 100K OHM 1% DIGI-KEY P100KHCT
THICK FILM 1/10W ROHS
1 1.7k R4 RESISTOR SMD0603 4.7K OHMS DIGI-KEY P4.7KGCT
1% 1/10W ROHS
1 10k R14 RESISTOR SMD0603 10K 5% 1/10W DIGI-KEY P10KGCT
ROHS
2 1.2k R1,R2 RESISTOR SMD0603 1.2K OHMS DIGI-KEY P1.2KGCT
5% 1/10W ROHS
1 649 R13 RESISTOR SMD0603 THICK FILM DIGI-KEY 311-649HRCT
649 OHMS 1% 1/10W ROHS
1 30.9k R8 RESISTOR SMD0603 30.9K OHMS 541-30.9KHCT
1% 1/10W ROHS
2 27.4k R10,R11 RESISTOR SMD0603 27.4 OHMS DIGI-KEY P27.4HCT
1% 1/10W ROHS
2 2.7k R6,R7 RESISTOR SMD0603 2.7K OHMS DIGI-KEY P2.7KGCT
5% 1/10W ROHS
2 100 R3,R5 RESISTOR SMD0603 100 OHM DIGI-KEY 541-100HCT
1/10W 1% ROHS
CAPACITORS
Qty Value Ref Des Description Vendor Part number
9 0.1μF C4,C7,C11,C12,C19,C24,C25,C28,C29 CAP SMD0402 CERM 0.1UFD 6.3V DIGI-KEY 445-1266-1
10% X5R ROHS
3 10μF C3,C16, C35 CAP SMD0603 CERM 10UFD 6.3V DIGI-KEY PCC2395CT
20% X5R ROHS
2 22μF C10,C15 CAP SMD0805 CERM 22UFD 6.3V DIGI-KEY 445-1422-1
20% X5R ROHS
2 47pF C26,C27 CAP SMD0603 CERM 47PFD 50V DIGI-KEY PCC470ACVCT
5% NPO ROHS
1 1000pF C22 CAP SMD0603 CERM 1000PFD 50V DIGI-KEY 445-1293-1
5% COG ROHS
1 1μF C30 CAP SMD0603 CERM 1.0UFD 16V DIGI-KEY 445-1604-1
5% X7R ROHS
4 0.47μF C1,C2,C5,C6 CAP SMD0603 CERM 0.47UFD 16V DIGI-KEY 478-1248-1
10% X5R ROHS
2 0.47μF C13,C14 CAP SMD0603 CERM 0.47UFD 25V DIGI-KEY PCC1771CT
10% X7R ROHS
2 1μF C8,C9 CAP SMD0603 CERM 1.0UFD 16V DIGI-KEY PCC2224CT
10% X5R ROHS
1 100pF C23 CAP SMD0805 CERM 100PFD 50V DIGI-KEY 490-1615-1
5% C0G ROHS
2 0.1μF C31,C33 CAP SMD0603 CERM 0.1UFD 50V DIGI-KEY 445-1314-1
10% X7R ROHS
16 TLV320AIC3254EVM Bill of Materials SLAU295A–September 2009–Revised October 2012
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
www.ti.com Appendix B
Table 1. TLV320AIC3254EVM Bill of Materials (continued)
2 10μF C32,C34 CAP SMD0805 CERM 10UFD 16V DIGI-KEY 490-3886-1
10% X5R ROHS
2 100μF C17,C18 CAP SMD1210 CERM 100UFD 6.3V DIGI-KEY 490-3390-1
20% X5R ROHS
INTEGRATED CIRCUITS
Qty Value Ref Des Description Vendor Part number
1 U2 USB STREAMING CONTROLLER DIGI-KEY 296-13041-5
TQFP48-PFB ROHS
1 VR1 VOLT REG 3.3V 400MA LDO CAP- DIGI-KEY 296-15819-1
FREE NMOS SOT23-DBV5 ROHS
1 U3 256K I2C SERIAL EEPROM,MSOP-8 DIGI-KEY 24AA256-I/MSND
1 D1 LED, YELLOW 2.0V SMD0805 DIGI-KEY 67-1554-1
ROHS
1 Y1 OSCILLATOR SMT 6MHz 3.3V OUT- DIGI-KEY 788-
ENABLE ROHS 8002AI133E-
6.0T
MISCELLANEOUS ITEMS
Qty Value Ref Des Description Vendor Part number
1 J5 JACK-USB MALE TYPEA SMT-RA DIGI-KEY WM17118
4PIN ROHS J
4 J1,J2,J3,J4 ACK AUDIO MINI(3.5MM ,4-COND DIGI-KEY CP-43516SJCT
PCB-RA ROHS
1 SW1 SWITCH, MOM, 160G SMT 4X3MM DIGI-KEY EG4344CT
ROHS
ATTENTION: All components must be Rhos compliant. Some part numbers may be either leaded or Rhos. Verify that purchased
components are Rhos compliant.
SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM Bill of Materials 17
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
www.ti.com
Appendix C Writing Scripts
A script is simply a text file that contains data to send to the serial control buses.
Each line in a script file is one command. No provision is made for extending lines beyond one line, except
for the > command. A line is terminated by a carriage return.
The first character of a line is the command. Commands are:
I Set interface bus to use
r Read from the serial control bus
w Write to the serial control bus
> Extend repeated write commands to lines below a w
# Comment
b Break
d Delay
f Wait for Flag
The first command, I, sets the interface to use for the commands to follow. This command must be
followed by one of the following parameters:
i2cstd Standard mode I2C bus
i2cfast Fast mode I2C bus
spi8 SPI bus with 8-bit register addressing
spi16 SPI bus with 16-bit register addressing
For example, if a fast mode I2C bus is to be used, the script begins with:
I i2cfast
A double quoted string of characters following the b command can be added to provide information to the
user about each breakpoint. When the script is executed, the software's command handler halts as soon
as a breakpoint is detected and displays the string of characters within the double quotes.
The Wait for Flag command, f, reads a specified register and verifies if the bitmap provided with the
command matches the data being read. If the data does not match, the command handler retries for up to
200 times. This feature is useful when switching buffers in parts that support the adaptive filtering mode.
The command f syntax follows:
f [i2c address] [register] [D7][D6][D5][D4][D3][D2][D1][D0]
where 'i2c address' and 'register' are in hexadecimal format
and 'D7' through 'D0' are in binary format with values of 0,
1 or X for don't care.
Anything following a comment command # is ignored by the parser, provided that it is on the same line.
The delay command d allows the user to specify a time, in milliseconds, that the script pauses before
proceeding. The delay time is entered in decimal format.
A series of byte values follows either a read or write command. Each byte value is expressed in
hexadecimal, and each byte must be separated by a space. Commands are interpreted and sent to the
TAS1020B by the program.
The first byte following an r (read) or w (write) command is the I2C slave address of the device (if I2C is
used) or the first data byte to write (if SPI is usednote that SPI interfaces are not standardized on
protocols, so the meaning of this byte varies with the device being addressed on the SPI bus). The
second byte is the starting register address that data will be written to (again, with I2C; SPI varies.
Following these two bytes are data, if writing; if reading, the third byte value is the number of bytes to
read, (expressed in hexadecimal).
18 Writing Scripts SLAU295A–September 2009–Revised October 2012
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
www.ti.com Appendix C
For example, to write the values 0xAA 0x55 to an I2C device with a slave address of 0x30, starting at a
register address of 0x03, the user writes:
#example script
I i2cfast
w 30 03 AA 55
r 30 03 02
This script begins with a comment, specifies that a fast I2C bus will be used, then writes 0xAA 0x55 to the
I2C slave device at address 0x30, writing the values into registers 0x03 and 0x04. The script then reads
back two bytes from the same device starting at register address 0x03. Note that the slave device value
does not change. It is unnecessary to set the R/W bit for I2C devices in the script; the read or write
commands does that.
If extensive repeated write commands are sent and commenting is desired for a group of bytes, the >
command can be used to extend the bytes to other lines that follow. A usage example for the > command
follows:
#example script for '>' command
I i2cfast
# Write AA and BB to registers 3 and 4, respectively
w 30 03 AA BB
# Write CC, DD, EE and FF to registers 5, 6, 7 and 8, respectively
> CC DD EE FF
# Place a commented breakpoint
b "AA BB CC DD EE FF was written, starting at register 3"
# Read back all six registers, starting at register 3
r 30 03 06
The following example demonstrates usage of the Wait for Flag command, f:
#example script for 'wait for flag' command
I i2cfast
# Switch to Page 44
w 30 00 2C
# Switch buffers
w 30 01 05
# Wait for bit D0 to clear. 'x' denotes a don't care.
f 30 01 xxxxxxx0
Any text editor can be used to write these scripts; Jedit is an editor that is highly recommended for general
usage. For more information, go to: http://www.jedit.org.
Once the script is written, it can be used in the command window by running the program, and then
selecting Open Script File... from the File menu. Locate the script and open it. The script is then displayed
in the command buffer. The user can also edit the script once it is in the buffer and save it by selecting
Save Script File... from the File menu.
SLAU295A–September 2009–Revised October 2012 Writing Scripts 19
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
Appendix C www.ti.com
Once the script is in the command buffer, it can be executed by pressing the Execute Command Buffer
button. If there are breakpoints in the script, the script executes to that point, and the user is presented
with a dialog box with a button to press to continue executing the script. When ready to proceed, push that
button and the script continues.
20 Writing Scripts SLAU295A–September 2009–Revised October 2012
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
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EVM WARNINGS AND RESTRICTIONS
It is important to operate the EVM daughterboard within the input voltage range specified in Table A-4 and the EVM motherboard within the
input voltage range of 6 Vdc to 10 Vdc when using an external ac/dc power source. See the USB-MODEVM Interface Power section of this
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Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 85°C. The EVM is designed to operate
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please be aware that these devices may be very warm to the touch.
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Copyright © 2008, Texas Instruments Incorporated
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Copyright © 2012, Texas Instruments Incorporated
SLLS025A − JULY 1986
Copyright 1986, Texas Instruments Incorporated
Revision Information
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
• Dual Circuits Capable of Driving
High-Capacitance Loads at High Speeds
• Output Supply Voltage Range up to 24 V
• Low Standby Power Dissipation
description
The SN75372 is a dual NAND gate interface
circuit designed to drive power MOSFETs from
TTL inputs. It provides high current and voltage
levels necessary to drive large capacitive loads at
high speeds. The device operates from a VCC1 of
5 V and a VCC2 of up to 24 V.
The SN75372 is characterized for operation from
0°C to 70°C.
schematic (each driver)
VCC1 VCC2
To Other
Driver
To Other
Driver
Output Y
GND
Input A
Enable E
1Y
7
2Y
6
E
2
EN
1A
1
2A
3
logic symbol†
TTL/MOS
1
2
3
4
8
7
6
5
1A
E
2A
GND
VCC1
1Y
2Y
VCC2
D OR P PACKAGE
(TOP VIEW)
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
!"# $"%&! ' #(
'"! ! $#!! $# )# # #* " #
' ' + ,( '"! $!# - '# #!# &, !&"'#
# - && $ # # (
SLLS025A − JULY 1986
3−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 25 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Peak output current, VO (tw < 10 ms, duty cycle < 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to network GND.
DISSIPATION RATING TABLE
PACKAGE
TA = 25°C
DERATING FACTOR
TA = 70°C
25 POWER RATING
ABOVE TA = 25°C
70 POWER RATING
D 725 mW 5.8 mW/°C 464 mW
P 1000 mW 8.0 mW/°C 640 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC1 4.75 5 5.25 V
Supply voltage, VCC2 4.75 20 24 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
High-level output current, IOH −10 mA
Low-level output current, IOL 40 mA
Operating free-air temperature, TA 0 70 °C
SLLS025A − JULY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of VCC1, VCC2, and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK Input clamp voltage II = − 12 mA −1.5 V
VOH High-level output voltage
VIL = 0.8 V, IOH = −50 μA VCC2−1.3 VCC2−0.8
V
VIL = 0.8 V, IOH = − 10 mA VCC2−2.5 VCC2−1.8
VIH = 2 V, IOL = 10 mA 0.15 0.3
VOL Low-level output voltage VCC2 = 15 V to 24 V,
IOL = 40 mA
VIH = 2 V,
0.25 0.5
V
VF Output clamp-diode forward voltage VI = 0, IF = 20 mA 1.5 V
II
Input current at maximum input
VI = 5.5 V 1 mA
voltage IIH High-level input current
Any A
VI = 2.4 V
40
A
Any E
80
μA
IIL Low-level input current
Any A
VI = 0.4 V
−1 −1.6
mA
Any E
−2 −3.2
ICC1(H)
Supply current from VCC1, both
outputs high 2 4 mA
ICC2(H)
Supply current from VCC2, both
outputs high
VCC1 = 5.25 V,
All inputs at 0 V,
VCC2 = 24 V,
No load
0.5 mA
ICC1(L)
Supply current from VCC1, both
outputs low 16 24 mA
ICC2(L)
Supply current from VCC2, both
outputs low
VCC1 = 5.25 V,
All inputs at 5 V,
VCC2 = 24 V,
No load
7 13 mA
ICC2(S)
Supply current from VCC2, standby
condition
VCC1 = 0,
All inputs at 5 V,
VCC2 = 24 V,
No load
0.5 mA
† All typical values are at VCC1 = 5 V, VCC2 = 20 V, and TA = 25°C.
switching characteristics, VCC1 = 5 V, VCC2 = 20 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDLH Delay time, low-to-high-level output 20 35 ns
tDHL Delay time, high-to-low-level output 10 20 ns
tTLH Transition time, low-to-high-level output
CL = 390 pF, RD = 10 Ω, See Figure 1
20 30 ns
tTHL Transition time, high-to-low-level output
20 30 ns
tPLH Propagation delay time, low-to-high-level output 10 40 65 ns
tPHL Propagation delay time, high-to-low-level output 10 30 50 ns
SLLS025A − JULY 1986
3−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
10%
5 V
2.4 V
VCC1
TEST CIRCUIT
Input
GND
VCC2
Pulse
Generator
(see Note A) Output
CL = 390 pF
(see Note B)
20 V
RD
Input
Output
VOLTAGE WAVEFORMS
≤ 10 ns
90%
1.5 V
0.5 μs
tDHL tTLH
VCC2−3 V
2 V
0 V
VOH
≤ 10 ns
90%
1.5 V 10%
tPHL tPHL
tDLH
tTHL
VCC2−3 V
2 V
VOL
3 V
NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Test Circuit and Voltage Waveforms, Each Driver
TYPICAL CHARACTERISTICS
−1
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
−10 −100
0.3
0.2
0.1
0
0 20 40 60
0.4
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.5
80 100
VCC2−0.5
VCC2−1
VCC2−1.5
VCC2−2
VCC2−2.5
VCC2−3
VCC1 = 5 V
VCC2 = 20 V
VI = 0.8 V
TA = 25°C
TA = 70°C
TA = 0°C
VVO0HH − High-Level Output Voltage − V
IOL − Low-Level Output Current − mA
VCC1 = 5 V
VCC2 = 20 V
VI = 2 V
TA = 70°C
TA = 0°C
VVOOLL − Low-Level Output Voltage − V
IOH − High-Level Output Current − mA
VCC2
− 0.01 − 0.1
Figure 2 Figure 3
SLLS025A − JULY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
10 20 40 100 400 1000
f − Frequency − kHz
POWER DISSIPATION (BOTH DRIVERS)
vs
FREQUENCY
200
400
200
0
800
1000
1200
12 600
8
4
0
0 0.5 1 1.5
16
20
VOLTAGE TRANSFER CHARACTERISTICS
24
2 2.5
VI − Input Voltage − V
VVO) − Output Voltage − V
VCC1 = 5 V
VCC2 = 20 V
No Load
TA = 25°C
VCC1 = 5 V
VCC2 = 20 V
Input: 3-V Square Wave
50% Duty Cycle
TA = 25°C
CL = 600 pF
CL = 1000 pF
CL = 2000 pF
CL = 4000 pF
CL = 400 pF
PPDT − Power Dissipation − mW
Allowable in P Package Only
Figure 4 Figure 5
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
FREE-AIR TEMPERATURE
100
80
20
0
0 10 20 30 40 50 60
High-to-Low-Level Output − ns
140
180
200
70 80
60
160
120
40
TA − Free-Air Temperature − °C
tkPSLVHR − Propagation Delay Time,
Low-to-High-Level Output − ns
ktSPVHRL − Propagation Delay Time,
TA − Free-Air Temperature − °C
100
80
20
0
140
180
200
60
160
120
40
0 10 20 30 40 50 60 70 80
CL = 50 pF
CL = 200 pF
CL = 1000 pF
CL = 2000 pF
CL = 4000 pF
VCC1 = 5 V
VCC2 = 20 V
RD = 10 Ω
See Figure 1
CL = 4000 pF
CL = 2000 pF
CL = 1000 pF
VCC1 = 5 V
VCC2 = 20 V
RD = 10 Ω
See Figure 1
CL = 200 pF CL = 390 pF
CL = 50 pF
CL = 390 pF
Figure 6 Figure 7
SLLS025A − JULY 1986
3−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
0 5 10 15
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
VCC2 SUPPLY VOLTAGE
20 25
100
80
20
0
140
180
200
60
160
120
40
Low-to-High-Level Output − ns
VCC2 − Supply Voltage − V
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
VCC2 SUPPLY VOLTAGE
100
80
20
0
140
180
200
60
160
120
40
0 5 10 15 20 25
VCC2 − Supply Voltage − V
tPLH − Propagation Delay Time,
VCC1 = 5 V
RD = 10 Ω
TA = 25°C
See Figure 1
CL = 2000 pF
CL = 1000 pF
CL = 200 pF CL = 390 pF
CL = 50 pF
VCC1 = 5 V
RD = 10 Ω
TA = 25°C
See Figure 1
CL = 4000 pF
CL = 2000 pF
CL = 1000 pF
CL = 390 pF
CL = 200 pF
CL = 50 pF
CL = 4000 pF
High-to-Low-Level Output − ns
tPLH − Propagation Delay Time,
Figure 8 Figure 9
0 1000 2000 3000 4000
VCC1 = 5 V
VCC2 = 20 V
TA = 25°C
See Figure 1
Low-to-High-Level Output − ns
100
80
20
0
140
180
200
60
160
120
40
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
RD = 10 Ω
RD = 0
RD = 24 Ω
100
80
20
0
140
180
200
60
160
120
40
0 1000 2000 3000 4000
CL − Load Capacitance − pF
VCC1 = 5 V
VCC2 = 20 V
TA = 25°C
See Figure 1
RD = 24 Ω
RD = 10 Ω
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
LOAD CAPACITANCE
RD = 0
ktSPVLRH − Propagation Delay Time,
High-to-Low-Level Output − ns
ktSPVLRH − Propagation Delay Time,
Figure 10 Figure 11
NOTE: For RD = 0, operation with CL > 2000 pF violates absolute maximum current rating.
SLLS025A − JULY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
THERMAL INFORMATION
power dissipation precautions
Significant power may be dissipated in the SN75372 driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies. Figure 5 shows the power dissipated in a typical SN75372
as a function of load capacitance and frequency. Average power dissipated by this driver is derived from the
equation
PT(AV) = PDC(AV) + PC(AV) = PS(AV)
where PDC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power level during
charging or discharging of the load capacitance, and PS(AV) is the power dissipation during switching between
the low and high levels. None of these include energy transferred to the load, and all are averaged over a full
cycle.
The power components per driver channel are
PC(AV) C V2
C
f
tHL tLH
tH
tL
T = 1/f
where the times are as defined in Figure 14. Figure 12. Output Voltage Waveform
PDC(AV) =
PHtH + PLtL
T
PS(AV) =
PLHtLH + PHLtHL
T
PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance.
VC is the voltage across the load capacitance during the charge cycle shown by the equation
VC = VOH − VOL
PS(AV) may be ignored for power calculations at low frequencies.
In the following power calculation, both channels are operating under identical conditions:
VOH =19.2 V and VOL = 0.15 V with VCC1 = 5 V, VCC2 = 20 V, VC = 19.05 V, C = 1000 pF, and the
duty cycle = 60%. At 0.5 MHz, PS(AV) is negligible and can be ignored. When the output voltage is high, ICC2
is negligible and can be ignored.
On a per-channel basis using data sheet values,
PDC(AV) (5 V) 2 mA
2 (20 V) 0 mA
2 (0.6)(5 V) 16 mA
2 (20 V) 7 mA
2 (0.4)
PDC(AV) = 47 mW per channel
Power during the charging time of the load capacitance is
PC(AV) = (1000 pF) (19.05 V)2 (0.5 MHz) = 182 mW per channel
Total power for each driver is
PT(AV) = 47 mW + 182 mW = 229 mW
and total package power is
PT(AV) = (229) (2) = 458 mW.
SLLS025A − JULY 1986
3−8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
driving power MOSFETs
The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The
input impedance of a FET consists of a reverse biased PN junction that can be described as a large capacitance
in parallel with a very high resistance. For this reason, the commonly used open-collector driver with a pullup
resistor is not satisfactory for high-speed applications. In Figure 12(a), an IRF151 power MOSFET switching
an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input
capacitance (Ciss) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time due to the
combination of Ciss and the pullup resistor is shown in Figure 12(b).
5 V
7
4 8
3
5
2 1
6
VVO0HH − − Gate Voltage − V
TLC555P
1/2 SN75447
470 Ω
48 V
M
VOL
t − Time − μs
(b)
(a)
IRF151
4
3
2
1
0
0 0.5 1 1.5 2 2.5 3
Figure 13. Power MOSFET Drive Using SN75447
SLLS025A − JULY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
A faster, more efficient drive circuit uses an active pullup as well as an active pulldown output configuration,
referred to as a totem-pole output. The SN75372 driver provides the high speed, totem-pole drive desired in
an application of this type, see Figure 13(a). The resulting faster switching speeds are shown in Figure 13(b).
5 V
TLC555P
1/2 SN75372
M
t − Time − μs
(b)
(a)
IRF151
48 V
4
3
2
1
0
0 0.5 1 1.5 2 2.5 3
VVO0HH − VVOOLL − Gate Voltage − V
7
4 8
3
5
2 1
6
Figure 14. Power MOSFET Drive Using SN75372
Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as
shown by the equation
Ipk
VC
tr
where C is the capacitive load, and tr is the desired drive time. V is the voltage that the capacitance is charged
to. In the circuit shown in Figure 13(a), V is found by the equation
V = VOH − VOL
Peak current required to maintain a rise time of 100 ns in the circuit of Figure 13(a) is
IPK
(30)4(109)
100(109) 120 mA
Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151.
With a VCC of 5 V, and assuming worst-cast conditions, the gate drive voltage is 3 V.
For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, the SN75374 quad
MOSFET driver should be used.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing
Pins Package Qty Eco Plan (2) Lead/
Ball Finish
MSL Peak Temp (3) Samples
(Requires Login)
SN75372D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN75372DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN75372DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
SN75372DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
SN75372DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
SN75372P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
SN75372PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
SN75372PSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN75372PSRE4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN75372PSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2010
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
SN75372DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75372PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75372DR SOIC D 8 2500 340.5 338.1 20.6
SN75372PSR SO PS 8 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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Copyright © 2012, Texas Instruments Incorporated
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
Meets IEEE Standard 488-1978 (GPIB)
8-Channel Bidirectional Transceivers
Power-Up/Power-Down Protection
(Glitch Free)
Designed to Implement Control Bus
Interface
SN75161B Designed for Single Controller
SN75162B Designed for Multiple
Controllers
High-Speed, Low-Power Schottky Circuitry
Low Power Dissipation . . . 72 mW Max Per
Channel
Fast Propagation Times . . . 22 ns Max
High-Impedance pnp Inputs
Receiver Hysteresis . . . 650 mV Typ
Bus-Terminating Resistors Provided on
Driver Outputs
No Loading of Bus When Device Is
Powered Down (VCC = 0)
description
The SN75161B and SN75162B eight-channel,
general-purpose interface bus transceivers are
monolithic, high-speed, low-power Schottky
devices designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is
designed to provide the bus-management and
data-transfer signals between operating units of
a single- or multiple-controller instrumentation
system. When combined with the SN75160B octal
bus transceiver, the SN75161B or SN75162B
provides the complete 16-wire interface for the
IEEE-488 bus.
The SN75161B and SN75162B feature eight
driver-receiver pairs connected in a front-to-back
configuration to form input/output (I/O) ports at
both the bus and terminal sides. A powerup/-
down disable circuit is included on all bus and
receiver outputs. This provides glitch-free operation
during VCC power up and power down.
PRODUCTION DATA information is current as of publication date. Copyright W 1995, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
DC
(TOP VIEW)
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
VCC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GPIB
I/O Ports
Terminal
I/O Ports
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
(TOP VIEW)
NC–No internal connection
SN75161B . . . DW OR N PACKAGE
SN75162B . . . DW PACKAGE
SN75162B . . . N PACKAGE
GPIB
I/O Ports
Terminal
I/O Ports
GPIB
I/O Ports
Terminal
I/O Ports
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC (on SN75162B)
enable signals. The SC input on the SN75162B allows the REN and IFC transceivers to be controlled
independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage VCC is 0. The drivers are designed to handle loads up to 48 mA of
sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV
for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal
when disabled.
The SN75161B and SN75162B are characterized for operation from 0°C to 70°C.
Function Tables
SN75161B RECEIVE/TRANSMIT
CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
DC TE ATN† ATN† SRQ REN IFC EOI DAV NDAC NRFD
(Controlled by DC) (Controlled by TE)
H H H
R T R R
T
T R R
H H L
R
L L H
T R T T
R
R T T
L L L
T
H L X R T R R R R T T
L H X T R T T T T R R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
† ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
SN75162B RECEIVE/TRANSMIT
CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
SC DC TE ATN† ATN† SRQ REN IFC EOI DAV NDAC NRFD
(Controlled by DC) (Controlled by SC) (Controlled by TE)
H H H
R T
T
T R R
H H L
R
L L H
T R
R
R T T
L L L
T
H L X R T R R T T
L H X T R T T R R
H T T
L R R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
† ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
CHANNEL-IDENTIFICATION TABLE
NAME IDENTITY CLASS
DC Direction Control
TE Talk Enable Control
SC System Control (SN75162B only)
ATN Attention
SRQ Service Request
REN Remote Enable Bus
IFC Interface Clear Management
EOI End of Identity
DAV Data Valid
NDAC Not Data Accepted Data
NRFD Not Ready for Data Transfer
SN75161B logic symbol†
EN3
1
ATN
8
1
ATN
13
1
1
EOI
7
3
EOI
14
1
3
SRQ
1
SRQ
12
1
1
REN
2
1
REN
19
1
1
IFC
3
1
IFC
18
1
1
DAV
6
2
DAV
15
1
2
NDAC
4
2
NDAC
17
1
2
2
1
16
NRFD
2
EN1/G4
EN2/G5
5
4
5
NRFD
TE
1
DC
11
This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
9
SN75161B logic diagram (positive logic)
NRFD 5 NRFD
16
NDAC 4 NDAC
17
DAV 6 DAV
15
IFC 3 IFC
18
REN 2 REN
19
SRQ 9 SRQ
12
EOI 7 EOI
14
11
DC
1
TE
13
ATN 8 ATN
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75162B logic symbol†
EN3
. 1
ATN
1
ATN
14
1
1
EOI
6
EOI
1
6
SRQ
1
SRQ
1
1
REN REN
1
3
IFC IFC
1
DAV
2
DAV
1
2
NDAC
2
NDAC
1
2
2
1
NRFD
2
EN1/G4
EN2/G5
5
4
NRFD
TE
DC
This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
EN3
12
2
1
15
SC
13
20
19
16
18
17
9
8
10
3
4
7
5
6
3
3
3
Pin numbers shown are for the N package.
SN75162B logic diagram (positive logic)
NRFD NRFD
NDAC NDAC
DAV DAV
IFC IFC
REN REN
SRQ SRQ
EOI EOI
DC
TE
ATN ATN
12
2
1
14
15
13
20
19
16
18
17
9
8
10
3
4
7
5
6
SC
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
schematics of inputs and outputs
NOM
4 kW
R(eq) 1.7 kW
NOM
10 kW
NOM
VCC
GND
Input/Output Port
Input/Output Port
GND
VCC
NOM
10 kW
NOM
4 kW
NOM
1.7 kW
NOM
9 kW
GND
Input
VCC
NOM
4 kW
EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC,
AND NRFD GPIB I/O PORTS
Driver output R(eq) = 30 W NOM
Receiver output R(eq) = 110 W NOM
Circuit inside dashed lines is on the driver outputs only.
R(eq) = equivalent resistor
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Low-level driver output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE
TA 3 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DW (20 pin) 1125 mW 9.0 mW/°C 720 mW
DW (24 pin) 1350 mW 10.8 mW/°C 864 mW
N (20 pin) 1150 mW 9.2 mW/°C 736 mW
N (22 pin) 1700 mW 13.6 mW/°C 1088 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
High level output current IOH
Bus ports with 3-state outputs –5.2 mA
High-current, Terminal ports –800 mA
Low level output current IOL
Bus ports 48
Low-current, mA
Terminal ports 16
Operating free-air temperature, TA 0 70 °C
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK Input clamp voltage II = – 18 mA –0.8 –1.5 V
Vhys
Hysteresis voltage
(VIT+ – VIT–) Bus See Figure 7 0.4 0.65 V
VOH‡ High level output voltage
Terminal IOH = – 800 mA 2.7 3.5
High-V
Bus IOH = – 5.2 mA 2.5 3.3
VOL Low level output voltage
Terminal IOL = 16 mA 0.3 0.5
Low-V
Bus IOL = 48 mA 0.35 0.5
II
Input current at maximum
Terminal VI = 5 5 V 0 2 100 mA
input voltage
5.5 0.2 IIH High-level input current Terminal and VI = 2.7 V 0.1 20 mA
IIL Low-level input current control inputs VI = 0.5 V –10 –100 mA
VI/O(b ) Voltage at bus port Driver disabled
II(bus) = 0 2.5 3.0 3.7
bus) V
II(bus) = – 12 mA –1.5
VI(bus) = – 1.5 V to 0.4 V –1.3
VI(bus) = 0.4 V to 2.5 V 0 –3.2
Power on Driver disabled VI(b ) = 2 5 V to 3 7 V
2.5
mA
II/O(bus) Current into bus port
bus) 2.5 3.7 –3.2
( )
VI(bus) = 3.7 V to 5 V 0 2.5
VI(bus) = 5 V to 5.5 V 0.7 2.5
Power off VCC = 0, VI(bus) = 0 V to 2.5 V –40 mA
IOS Short circuit output current
Terminal –15 –35 –75
Short-mA
Bus –25 –50 –125
ICC Supply current No load, TE, DE, and SC low 110 mA
CI/O(b ) Bus port capacitance
VCC = 5 V to 0,
bus) Bus-CC 16 pF
VI/O = 0 to 2 V, f = 1 MHz † All typical values are at VCC = 5 V, TA = 25°C.
‡ VOH applies for 3-state outputs only.
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS MIN TYP MAX UNIT
tPLH
Propagation delay time,
low- to high-level output
Terminal Bus
CL = 30 pF,
14 20
ns
tPHL
Propagation delay time,
high- to low-level output
L
See Figure 1
14 20
tPLH
Propagation delay time,
low- to high-level output
Terminal
Bus
(SRQ,NDAC,
NRFD)
CL = 30 pF,
See Figure 1
29 35 ns
tPLH
Propagation delay time,
low- to high-level output
Bus Terminal
CL = 30 pF,
10 20
ns
tPHL
Propagation delay time,
high- to low-level output
L
See Figure 2
15 22
tPZH Output enable time to high level
Bus (ATN
60
tPHZ Output disable time from high level TE,DC,
ATN,
EOI, REN, See Figure 3
45
ns
tPZL Output enable time to low level
or
SC
, ,
IFC, and
60
tPLZ Output disable time from low level
DAV)
55
tPZH Output enable time to high level 55
tPHZ Output disable time from high level TE,DC,
Terminal See Figure 4
50
ns
tPZL Output enable time to low level
or
SC
45
tPLZ Output disable time from low level
55
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
LOAD CIRCUIT
480 W
200 W
(see Note A)
CL = 30 pF
Test Point
5 V
Output
Bus
Input
Terminal
See Note B
VOH
VOH
0 V
3 V
tPHL
2.2 V
1.0 V
1.5 V
tPLH
1.5 V
From (Bus)
Output Under
Test
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns,
tf 3 6 ns, ZO = 50 W.
Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms
See Note B
1.5 V
tPLH
1.5 V
1.5 V 1.5 V
tPHL
3 V
0 V
VOH
VOL
Bus
Input
Output
From (Terminal)
Output Under
Test
4.3 V
Test Point
CL = 30 pF
(see Note A)
240 W
3 kW
LOAD CIRCUIT
VOLTAGE WAVEFORMS
Terminal
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns,
tf 3 6 ns, ZO = 50 W.
Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns,
tf 3 6 ns, ZO = 50 W.
S1 Open
tPHZ
1.5 V
3 V
0 V
S1 Closed
1 V
3.5 V
VOL
Input
Control
See Note B
1.5 V
tPZH
S1
VOLTAGE WAVEFORMS
2 V
tPZL
90%
0.5 V
tPLZ
VOH
0 V
Bus
Output
Bus
Output
5 V
Test Point
CL = 15 pF
(see Note A)
200 W
480 W
LOAD CIRCUIT
From (Bus)
Output Under
Test
Figure 3. Bus Enable and Disable Times Load Circuit and Voltage Waveforms
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
PARAMETER MEASUREMENT INFORMATION
Output 90%
Terminal
S1 Open
S1 Closed
Terminal
tPHZ
VOLTAGE WAVEFORMS
Output
0 V
VOH
tPLZ
0.7 V
tPZL
1.5 V
tPZH
1.5 V
See Note B
Control
Input
VOL
4 V
1 V
0 V
3 V
1.5 V
LOAD CIRCUIT
3 kW
240 W
Test Point
S1 4.3 V
CL = 15 pF
(see Note A)
From (Terminal)
Output Under
Test
NOTES: A. CL includes probe and jig capacitance.
B. The Input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle,
tr 3 6 ns, tf 3 6 ns, ZO = 50 W.
Figure 4. Terminal Enable and Disable Times Load Circuit and Voltage Waveforms
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VOH
– High-Level Output Voltage – V
TERMINAL I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3
2.5
2
1.5
1
0.5
–5 –10 –15 –20 –25 –30 –35
0
–40
4
0
TA = 25°C
VCC = 5 V
IOH – High-Level Output Current – mA
Figure 5
IOL – Low-Level Output Current – mA
– Low-Level Output Voltage – V
TERMINAL I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
0.5
0.4
0.3
0.2
0.1
10 20 30 40 50
0
60
0.6
0
VOL
Figure 6
2
– Output Voltage – V
TERMINAL I/O PORTS
OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
VIT–
TA = 25°C
No Load
VCC = 5 V
3.5
3
2.5
2
1.5
1
0.5
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0
4
VI – Bus Input Voltage – V
0
VO
VIT+
Figure 7
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13
TYPICAL CHARACTERISTICS
IOH – High-Level Output Current – mA
– High-Level Output Voltage – V
GPIB I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
3
2
1
–10 –20 –40 –30 –50
0
–60
0
0
VOH
Figure 8
IOL – Low-Level Output Current – mA
– Low-Level Output Voltage – V
GPIB I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
0.5
0.4
0.3
0.2
0.1
10 20 30 40 50 60 70 80 90
0
100
0.6
0
VOL
Figure 9
Figure 10
VI – Input Voltage – V
VO
– Output Voltage – V
GPIB I/O PORTS
OUTPUT VOLTAGE
vs
THERMAL INPUT VOLTAGE
TA = 25°C
No Load
VCC = 5 V
3
2
1
1 1.1 1.2 1.3 1.4 1.5 1.6
0
4
0.9 1.7
– Current – mA
GPIB I/O PORTS
CURRENT
vs
VOLTAGE
2
1
0
–1
–2
–3
–6
–1 0 1 2 3 4 5
–7
6
VI/O – Voltage – V
–2
TA = 25°C
VCC = 5 V
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
The Unshaded
Area Conforms to
Paragraph 3.5.3 of
IEEE Standard 488-1978
II/O
–5
–4
Figure 11
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN75161BDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75161BDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75161BDWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75161BDWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75161BDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75161BN ACTIVE PDIP N 20 20 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75161BNE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75162BDW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75162BDWE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75162BDWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75162BDWR ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75162BDWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75162BDWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75162BN OBSOLETE PDIP N 22 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
SN75161BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN75161BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1
SN75162BDWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Feb-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75161BDWR SOIC DW 20 2000 346.0 346.0 41.0
SN75161BDWR SOIC DW 20 2000 346.0 346.0 41.0
SN75162BDWR SOIC DW 24 2000 346.0 346.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Feb-2011
Pack Materials-Page 2
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Copyright © 2012, Texas Instruments Incorporated
6 O
6
(1.8639 V
2.1962 10
3.88 10
)
T 1481.96
u
u
GND NC
V+ VO
LMT88
LMT88
www.ti.com SNIS175 –MARCH 2013
LMT88 2.4V, 10μA, SC70, DSBGA Temperature Sensor
Check for Samples: LMT88
1FEATURES DESCRIPTION
The LMT88 is a precision analog output CMOS 2• Cost-Effective Alternative to Thermistors
integrated-circuit temperature sensor that operates
• Rated for full −55°C to +130°C range over a −55°C to 130°C temperature range. The
• Available in an SC70 Package power supply operating range is 2.4 V to 5.5 V. The
• Predictable Curvature Error transfer function of LMT88 is predominately linear, yet
• Suitable for Remote Applications has a slight predictable parabolic curvature. The accuracy of the LMT88 when specified to a parabolic
transfer function is ±1.5°C at an ambient temperature APPLICATIONS of 30°C. The temperature error increases linearly and
• Industrial reaches a maximum of ±2.5°C at the temperature
• HVAC range extremes. The temperature range is affected
by the power supply voltage. At a power supply
• Disk Drives voltage of 2.7 V to 5.5 V the temperature range
• Automotive extremes are 130°C and −55°C. Decreasing the
• Portable Medical Instruments power supply voltage to 2.4 V changes the negative
extreme to −30°C, while the positive remains at
• Computers 130°C.
• Battery Management
The LMT88 quiescent current is less than 10 μA.
• Printers Therefore, self-heating is less than 0.02°C in still air.
• Power Supply Modules Shutdown capability for the LMT88 is intrinsic
• FAX Machines because its inherent low power consumption allows it
to be powered directly from the output of many logic
• Mobile Phones gates or does not necessitate shutdown at all.
• Automotive
The LMT88 is a cost-competitive alternative to
thermistors.
TYPICAL APPLICATION
Full-Range Celsius (Centigrade) Temperature Sensor (−55°C TO 130°C) Operating From a Single LI-Ion
Battery Cell
space
space VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639
space
where: T is temperature, and VO is the measured output voltage of the LMT88.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMT88
GND NC
V+ VO
1
4 3
5
GND
2
LMT88
SNIS175 –MARCH 2013 www.ti.com
Figure 1. Output Voltage vs Temperature
Table 1. Output Voltage vs Temperature
TEMPERATURE (T) TYPICAL VO
130°C 303 mV
100°C 675 mV
80°C 919 mV
30°C 1515 mV
25°C 1574 mV
0°C 1863.9 mV
–30°C 2205 mV
−40°C 2318 mV
−55°C 2485 mV
CONNECTION DIAGRAMS
GND (pin 2) may be grounded or left floating. For optimum thermal conductivity to the pc board ground plane, pin 2
must be grounded.
NC (pin 1) must be left floating or grounded. Other signal traces must not be connected to this pin.
Figure 2. SC70-5 Top View
2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMT88
LMT88
www.ti.com SNIS175 –MARCH 2013
ABSOLUTE MAXIMUM RATINGS(1)
VALUES
Supply Voltage 6.5V to −0.2V
Output Voltage (V+ + 0.6 V) to −0.6 V
Output Current 10 mA
Input Current at any pin (2) 5 mA
Storage Temperature −65°C to 150°C
Maximum Junction Temperature (TJMAX) 150°C
Human Body Model 2500 V
ESD Susceptibility (3)
Machine Model 250 V
Soldering process must comply with the Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(4)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For specified specifications and test conditions, see the
ELECTRICAL CHARACTERISTICS. The specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V+), the current at that pin should be limited to 5 mA.
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin.
(4) Reflow temperature profiles are different for lead-free and non-lead-free packages.
OPERATION RATINGS
Specified Temperature Range: TMIN ≤ TA ≤ TMAX
LMT88 with 2.4 V ≤ V+≤ 2.7 V −30°C ≤ TA ≤ 130°C
LMT88 with 2.7 V ≤ V+≤ 5.5 V −55°C ≤ TA ≤ 130°C
Supply Voltage Range (V+) 2.4 V to 5.5 V
Thermal Resistance, θJA
(1)
SC70 415°C/W
(1) The junction to ambient thermal resistance (θJA) is specified without a heat sink in still air using the printed circuit board layout shown in
PCB Layouts Used For Thermal Measurements.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMT88
LMT88
SNIS175 –MARCH 2013 www.ti.com
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, these specifications apply for V+ = +2.7 VDC. Boldface limits apply for TA = TJ = TMIN to TMAX ; all
other limits TA = TJ = 25°C; Unless otherwise noted.
PARAMETER CONDITIONS TYPICAL(1) MAX(2) UNIT
(Limit)
TA = 25°C to 30°C ±1.5 ±4.0 °C (max)
TA = 130°C ±5.0 °C (max)
TA = 125°C ±5.0 °C (max)
TA = 100°C ±4.7 °C (max)
Temperature to Voltage Error TA = 85°C ±4.6 °C (max) VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639V(3)
TA = 80°C ±4.5 °C (max)
TA = 0°C ±4.4 °C (max)
TA = –30°C ±4.7 °C (min)
TA = –40°C ±4.8 °C (max)
TA = –55°C ±5.0 °C (max)
Output Voltage at 0°C 1.8639 V
Variance from Curve ±1.0 °C
Non-Linearity (4) –20°C ≤ TA ≤ 80°C ±0.4%
Sensor Gain (Temperature Sensitivity or Average Slope) –30°C ≤ T −11.0 mV/°C (min) to equation: V A ≤ 100°C −11.77 O=−11.77 mV/ °C×T+1.860V −12.6 mV/°C (max)
Output Impedance 0 μA ≤ IL ≤ 16 μA (5) (6) 160 Ω (max)
Load Regulation(7) 0 μA ≤ IL ≤ 16 μA (5) (6) −2.5 mV (max)
2.4 V ≤ V+ ≤ 5.0V 3.7 mV/V (max)
Line Regulation(8)
5.0 V ≤ V+ ≤ 5.5 V 11 mV (max)
2.4V ≤ V+ ≤ 5.0V 4.5 7 μA (max)
Quiescent Current 5.0V ≤ V+ ≤ 5.5V 4.5 9 μA (max)
2.4V ≤ V+ ≤ 5.0V 4.5 10 μA (max)
Change of Quiescent Current 2.4 V ≤ V+ ≤ 5.5V 0.7 μA
Temperature Coefficient of Quiescent Current −11 nA/°C
Shutdown Current V+ ≤ 0.8 V 0.02 μA
(1) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(2) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(3) Accuracy is defined as the error between the measured and calculated output voltage at the specified conditions of voltage, current, and
temperature (expressed in°C).
(4) Non-Linearity is defined as the deviation of the calculated output-voltage-versus-temperature curve from the best-fit straight line, over
the temperature range specified.
(5) Negative currents are flowing into the LMT88. Positive currents are flowing out of the LMT88. Using this convention the LMT88 can at
most sink −1 μA and source 16 μA.
(6) Load regulation or output impedance specifications apply over the supply voltage range of 2.4V to 5.5V.
(7) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output due to heating
effects can be computed by multiplying the internal dissipation by the thermal resistance.
(8) Line regulation is calculated by subtracting the output voltage at the highest supply input voltage from the output voltage at the lowest
supply input voltage.
4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMT88
6 O
6
(1.8639 V
2.1962 10
3.88 10
T 1481.96
u
u
LMT88
www.ti.com SNIS175 –MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS
PCB Layouts Used For Thermal Measurements
Figure 4. Layout Used For No Heat Sink Measurements
Figure 5. Layout Used For Measurements With Small Heat Sink
LMT88 TRANSFER FUNCTION
The LMT88 transfer function can be described in different ways with varying levels of precision. A simple linear
transfer function, with good accuracy near 25°C, is
VO = −11.69 mV/°C × T + 1.8663 V (1)
Over the full operating temperature range of −55°C to 130°C, best accuracy can be obtained by using the
parabolic transfer function.
VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 (2)
solving for T:
(3)
A linear transfer function can be used over a limited temperature range by calculating a slope and offset that give
best results over that range. A linear transfer function can be calculated from the parabolic transfer function of
the LMT88. The slope of the linear transfer function can be calculated using the following equation:
m = −7.76 × 10−6× T − 0.0115, (4)
where T is the middle of the temperature range of interest and m is in V/°C. For example for the temperature
range of TMIN = −30 to TMAX = +100°C:
T = 35°C (5)
and
m = −11.77 mV/°C (6)
The offset of the linear transfer function can be calculated using the following equation:
b = (VOP(TMAX) + VOP(T) − m × (TMAX+T))/2 (7)
where:
VOP(TMAX) is the calculated output voltage at TMAX using the parabolic transfer function for VO
VOP(T) is the calculated output voltage at T using the parabolic transfer function for VO.
Using this procedure the best fit linear transfer function for many popular temperature ranges was calculated in
Table 2. As shown in Table 2 the error that is introduced by the linear transfer function increases with wider
temperature ranges.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMT88
LMT88
SNIS175 –MARCH 2013 www.ti.com
Table 2. First Order Equations Optimized for Different Temperature Ranges
TEMPERATURE RANGE MAXIMUM DEVIATION OF LINEAR EQUATION
LINEAR EQUATION
Tmin (°C) Tmax (°C) FROM PARABOLIC EQUATION (°C)
−55 130 VO = −11.79 mV/°C × T + 1.8528 V ±1.41
−40 110 VO = −11.77 mV/°C × T + 1.8577 V ±0.93
−30 100 VO = −11.77 mV/°C × T + 1.8605 V ±0.70
-40 85 VO = −11.67 mV/°C × T + 1.8583 V ±0.65
−10 65 VO = −11.71 mV/°C × T + 1.8641 V ±0.23
35 45 VO = −11.81 mV/°C × T + 1.8701 V ±0.004
20 30 VO = –11.69 mV/°C × T + 1.8663 V ±0.004
MOUNTING
The LMT88 can be applied easily in the same way as other integrated-circuit temperature sensors. It can be
glued or cemented to a surface. The temperature that the LMT88 is sensing will be within about +0.02°C of the
surface temperature to which the LMT88's leads are attached to.
This presumes that the ambient air temperature is almost the same as the surface temperature; if the air
temperature were much higher or lower than the surface temperature, the actual temperature measured would
be at an intermediate temperature between the surface temperature and the air temperature.
To ensure good thermal conductivity the backside of the LMT88 die is directly attached to the pin 2 GND pin.
The tempertures of the lands and traces to the other leads of the LMT88 will also affect the temperature that is
being sensed.
Alternatively, the LMT88 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or
screwed into a threaded hole in a tank. As with any IC, the LMT88 and accompanying wiring and circuits must be
kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold
temperatures where condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy
paints or dips are often used to ensure that moisture cannot corrode the LMT88 or its connections.
The thermal resistance junction to ambient (θJA) is the parameter used to calculate the rise of a device junction
temperature due to its power dissipation. For the LMT88 the equation used to calculate the rise in the die
temperature is as follows:
TJ = TA + θJA [(V+ IQ) + (V+ − VO) IL]
where IQ is the quiescent current and ILis the load current on the output. Since the LMT88's junction temperature
is the actual temperature being measured care should be taken to minimize the load current that the LMT88 is
required to drive.
6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMT88
OUT
Heavy Capacitive Load, Wiring, Etc.
LMT88
+
d R
C
OUT
Heavy Capacitive Load, Wiring, Etc.
LMT88
+
d
R
C
0.1 μF Bypass
Optional
0.1 μF Bypass
Optional
OUT
Heavy Capacitive Load, Wiring, Etc.
LMT88
+
d
To A High-Impedance Load
LMT88
www.ti.com SNIS175 –MARCH 2013
The tables shown in Table 3 summarize the rise in die temperature of the LMT88 without any loading, and the
thermal resistance for different conditions.
Table 3. Temperature Rise of LMT88 Due to Self-Heating and Thermal Resistance (θJA)(1)
SC70-5 SC70-5
NO HEAT SINK SMALL HEAT SINK
θJA TJ − TA θJA TJ − TA
(°C/W) (°C) (°C/W) (°C)
Still air 412 0.2 350 0.19
Moving air 312 0.17 266 0.15
(1) See PCB Layouts Used For Thermal Measurements for PCB layout samples.
CAPACITIVE LOADS
The LMT88 handles capacitive loading well. Without any precautions, the LMT88 can drive any capacitive load
less than 300 pF as shown in Figure 6. Over the specified temperature range the LMT88 has a maximum output
impedance of 160 Ω. In an extremely noisy environment it may be necessary to add some filtering to minimize
noise pickup. It is recommended that 0.1 μF be added from V+ to GND to bypass the power supply voltage, as
shown in . In a noisy environment it may even be necessary to add a capacitor from the output to ground with a
series resistor as shown in . A 1 μF output capacitor with the 160 Ω maximum output impedance and a 200 Ω
series resistor will form a 442 Hz lowpass filter. Since the thermal time constant of the LMT88 is much slower,
the overall response time of the LMT88 will not be significantly affected.
Figure 6. LMT88 No Decoupling Required for Capacitive Loads Less Than 300 pF
R (Ω) C (μF)
200 1
470 0.1
680 0.01
1 k 0.001
spacer between the table and graphic
Figure 7. LMT88 with Filter for Noisy Environment and Capacitive Loading Greater Than 300 pF
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LMT88
GND
0.1 PF
V+ VO
LMT88
GND NC 0.1 PF
V+ (+5.0V)
1 k
ADCV0831
LM4040BIM3-4.1
GND
VIN
V+
6
5
4
1
3
2
3
2
1
4
5
CS
DO
CLK
470
LMT88
SHUTDOWN +VS VO
Any logic
device output
4.1V R1
R3
R2
LM4040 U3 0.1 PF
R4
VOUT
V+
VT
VTemp
+
-
U1
V+ LMT88
U2
(High = overtemp alarm)
VT1
VT2
VTEMP
VOUT
VT1 =
R1 + R2||R3
(4.1)R2
VT2 =
R2 + R1||R3
(4.1)R2||R3
LM7211
LMT88
SNIS175 –MARCH 2013 www.ti.com
NOTE
Either placement of resistor as shown above is just as effective.
APPLICATION CIRCUITS
Figure 8. Centigrade Thermostat
Figure 9. Conserving Power Dissipation with Shutdown
Figure 10. Suggested Connection to a Sampling Analog to Digital Converter Input Stage
Most CMOS ADCs found in ASICs have a sampled data comparator input structure that is notorious for causing
grief to analog output devices such as the LMT88 and many op amps. The cause of this grief is the requirement
of instantaneous charge of the input sampling capacitor in the ADC. This requirement is easily accommodated by
the addition of a capacitor. Since not all ADCs have identical input stages, the charge requirements will vary
necessitating a different value of compensating capacitor. This ADC is shown as an example only. If a digital
output temperature is required please refer to devices such as the LM74.
8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMT88
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LMT88DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM -55 to 130 T9C
LMT88DCKT ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM -55 to 130 T9C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LMT88DCKR SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMT88DCKT SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMT88DCKR SC70 DCK 5 3000 210.0 185.0 35.0
LMT88DCKT SC70 DCK 5 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
2−GBPS Differential Repeater
Evaluation Module
November 2002 High-Performance Linear/Interface Products
User’s Guide
SLLU040A
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the supply voltage range of 3 V to 3.6 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the supply range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
125°C. The EVM is designed to operate properly with certain components above 125°C as
long as the input and output ranges are maintained. These components include but are not
limited to linear regulators, switching transistors, pass transistors, and current sense
resistors. These types of devices can be identified using the EVM schematic located in the
EVM User’s Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
Information About Cautions and Warnings
v
Preface
Read This First
About This Manual
This EVM user’s guide provides information about the 2-GBPS differential
repeater evaluation module.
How to Use This Manual
This document contains the following chapters:
Chapter 1 — Introduction
Chapter2 — Setup and Equipment Required
Chapter 3 — EVM Construction
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
vi
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI document, call the Texas Instruments
Literature Response Center at (800) 477-8924 or the Product Information
Center (PIC) at (972) 644-5580. When ordering, identify this booklet by its title
and literature number. Updated documents can also be obtained through our
website at www.ti.com.
Data Sheet: Literature Number:
SN65LVDS100/101 SLLS516
SN65CML100 SLLS547
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates,
uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Contents
vii
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2 Setup and Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
3 EVM Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4 Board Layer Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Figures
1-1 EVM With SN65LVDS100 Installed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 Schematic of EVM Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1 TIA/EIA-644-A LVDS Driver Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2-2 EVM Power Connections for SN65LVDS100 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2-3 External Termination for Differential CML or LVPECL Inputs to EVM . . . . . . . . . . . . . . . . . 2-4
2-4 External Termination for Single-Ended LVPECL Inputs to EVM . . . . . . . . . . . . . . . . . . . . . . 2-5
2-5 Typical Output From SN65LVDS100 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Tables
1-1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Contents
viii
Introduction 1-1
Introduction
The 2-GBPS differential repeater evaluation module (EVM) allows evaluation
of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential
repeaters/ translators. This user’s guide gives a brief overview of the EVM,
setup and operation instructions, and typical test results that can be expected.
Topic Page
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Chapter 1
Overview
1-2
1.1 Overview
The 2-GBPS differential repeater evaluation module (EVM) is designed for
evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100
differential repeaters/ translators. The SN65LVDS100 and SN65LVDS101
devices both incorporate wide common-mode range receivers, allowing
receipt of LVDS, LVPECL, or CML input signals. The SN65LVDS100 provides
an LVDS output, the SN65LVDS101 incorporates an LVPECL output driver,
and the SN65CML100 delivers a CML output. Both devices provide a VBB
reference voltage to support receiving of single-ended LVPECL input signals,
or biasing of ac-coupled inputs. The EVM can be ordered with the
SN65LVDS100, SN65LVDS101, or SN65CML100 installed. Orderable EVM
part numbers are shown in Table 1-1.
Table 1-1. Ordering Information
EVM Part Number Installed Device
SN65LVDS100EVM SN65LVDS100DGK
SN65LVDS101EVM SN65LVDS101DGK
SN65CML100EVM SN65CML100DGK
Detailed information relating to the SN65LVDS100, SN65LVDS101, and
SN65CML100 can be found in the device data sheet, a copy of which is
shipped as part of the EVM or available from www.ti.com. A picture of the EVM,
with an SN65LVDS100 device installed, is shown in Figure 1-1.
Figure 1-1. EVM With SN65LVDS100 Installed
Signal Paths
Introduction 1-3
1.2 Signal Paths
A partial schematic of the EVM is shown in Figure 1-2 and a full
schematic is in chapter 3. Edge-mount SMA connectors (J4, J5, J6, and
J7) are provided for data input and output connections. Three power
jacks (J1, J2, and J3) are used to provide power to and a ground
reference, for the EVM. The use of these power jacks is addressed
later. Chapter 3 also provides a parts list for the EVM, as well as an
indication of which components are installed when shipped.
Figure 1-2. Schematic of EVM Signal Path
NC
A
B
Vbb
VCC
Y
Z
GND
R5
Uninstalled
JMP2
1
2
C12
.010 μF
DUT_MSOP8
DUT1
VCC01
VCC
C11
.010 μF
R2
Uninstalled
J6
GND
J7
GND
R4
Uninstalled
R3
Uninstalled
J4 R1 100 Ω
GND
J5
GND
1
1
1
2
3
4
8
7
6
5
1
1
1-4
Setup and Equipment Required 2-1
Setup and Equipment Required
This chapter examines the setup and use of the evaluation module and the results
of operation.
Topic Page
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Chapter 2
Overview
2-2
2.1 Overview
LVDS driver output characteristics are specified in the TIA/EIA-644 standard.
LVDS drivers nominally provide a 350-mV differential signal, with a 1.25-V
offset from ground. These levels are attained when driving a 100-Ω differential
line-termination test load (see Figure 2-1). In real applications, there may be
a ground potential between a driver and receiver(s). The driver must drive the
common-mode load presented by the receiver inputs and the differential load.
A TIA/EIA-644-A compliant LVDS driver is required to maintain its differential
output with up to 32 standard receivers. The receiver load is represented by
the 3.74-kΩ resistors shown in Figure 2-1.
Figure 2-1. TIA/EIA-644-A LVDS Driver Test Load
_
+
A
B
VOD 100 Ω
3.74 kΩ
3.74 kΩ
0 V ≤ Vtest ≤ 2.4 V
D
LVPECL drivers are generally loaded with 50-Ω resistors to a termination bias
voltage, VT. VT is usually 2-V below the supply voltage of the driver circuit.
When the driver operates from a 3.3-V supply, VT is set to approximately 1.3 V.
CML drivers are generally loaded with 50-Ω resistors to a termination voltage,
VTT. VTT can either be equivalent to the supply voltage of the driver circuit
(equal to VCC) or set to 2.5 V or 1.8 V, irrelevant to the supply voltage. If desired,
the SN65CML100 can be configured to drive a dual 50-Ω load. In this
configuration one 50-Ω resistor (tied to the termination voltage VTT) is placed
near the output of the SN65CML100 and a second 50-Ω resistor (also tied to
VTT) is placed near the end of the transmission line.
The EVM has been designed to support the SN65LVDS100 LVDS-output
device, the SN65LVDS101 LVPECL-output device, and the SN65CML100
CML-output device. By using the three power jacks (J1, J2, and J3), as well
as installing termination resistors (R2, R3, and R4), different methods of
termination and probing can be used to evaluate the device output
characteristics. The typical setup for the SN65LVDS100 is shown in
Figure 2-2.
Applying an Input
Setup and Equipment Required 2-3
Figure 2-2. EVM Power Connections for SN65LVDS100 Evaluation
Pattern
Generator
Oscilloscope
EVM
Power Supply 1 +
-
Power Supply 2 +
-
EVM VCC
GND
DUT
GND
1.22V
3.3V
Matched
Cables
SMA to SMA
Matched
Cables
SMA to SMA
J2
J7
J6
J5
J4
J3 J1
100 Ω
50 Ω 50 Ω
Warning
Power jacks J1, J2, and J3 are not insulated on the backside of the
EVM. Place on a nonconductive surface.
2.2 Applying an Input
LVDS inputs should be applied to SMA connectors J4 and J5, while keeping
R1 installed. The EVM comes with a 100-Ω termination resistor (R1) installed
across the differential inputs. This 100-Ω resistor represents an LVDS
termination.
When using a general-purpose signal generator with 50-Ω output impedance,
make sure that the signal levels are between 0 V to 4 V with respect to J3. A
signal generator such as the Advantest D3186 can simulate LVDS, LVPECL,
or CML inputs.
When using LVPECL or CML drivers for the input signal, termination external
to the EVM must be provided (see Figure 2-3). LVPECL drivers should be
terminated with 50-Ω pulldowns to VT, while CML drivers should be terminated
Applying an Input
2-4
with 50-Ω pullups to VTT. When using external terminations, the onboard
termination resistor R1 should be removed from the EVM. It should be noted
that the signal quality at the receiver input may be degraded when external
terminations are used, as a significant stub exists from the external termination
network to the receiver input. The user needs to verify that the transition time
of the input signal, coupled with the stub length, does not lead to reflection
problems. These concerns would be addressed in a real application where the
terminations are placed close to the receiver input.
Figure 2-3. External Termination for Differential CML or LVPECL Inputs to EVM
Select VT for LVPECL
or
Select VTT for CML
Select VT for LVPECL
or
Select VTT for CML
50 Ω
50 Ω
OUT
OUT
Signal Source EVM BOARD
NOTES: A. Locate 50-Ω resistors as close to the EVM as possible
B. Remove R1
A
B
Y
Z
Finally, as mentioned above, the SN65LVDS100, SN65LVDS101, and
SN65CML100 devices provide a VBB reference voltage output. This output
can be used with an externally terminated, single-ended, LVPECL input to
convert from a single-ended input to a differential output. The same cautions
that are mentioned above concerning signal quality and reflections apply.
When using VBB as a single-ended reference, R1 should be removed while R5
and JMP2 should be installed. The single-ended input signal is applied to J4.
This setup directly connects the VBB output to the DUT receiver B input via a
0-Ω connection (see Figure 2-4).
Observing an Output
Setup and Equipment Required 2-5
Figure 2-4. External Termination for Single-Ended LVPECL Inputs to EVM
50 Ω
OUT
Signal Source EVM BOARD
NOTES: A. Add jumper Jmp2 and 0-Ω R5
B. Remove R1
A
B
Y
Z
2.3 Observing an Output
Direct connection to an oscilloscope with 50-Ω internal terminations to ground
is accomplished without R2, R3, and R41. The outputs are available at J6 and
J7 for direct connection to oscilloscope inputs. Matched length cables must be
used when connecting the EVM to a scope to avoid inducing skew between
the noninverting (+) and inverting (-) outputs.
The three power jacks (J1, J2, and J3) are used to provide power and a ground
reference for the EVM. The power connections to the EVM determine the
common-mode load to the device. As mentioned earlier, LVDS drivers have
limited common-mode driver capability. When connecting the EVM outputs
directly to oscilloscope inputs, setting of the oscilloscope common-mode
offset voltage is required, as the oscilloscope presents low common-mode
load impedance to the device.
Returning to Figure 2-2, power supply 1 is used to provide the required 3.3 V
to the EVM. Power supply 2 is used to offset the EVM ground relative to the
DUT ground. The EVM ground is connected to the oscilloscope ground
through the returns on SMA connectors J6 and J7. With power applied as
shown in Figure 2-2, the common-mode voltage seen by the SN65LVDS100
is approximately equal to the reference voltage being used inside the device
preventing significant common-mode current to flow. Optimum device setup
can be confirmed by adjusting the voltage on power supply 2 until its current
is minimized. It is important to note that use of the dual supplies and offsetting
the EVM ground relative to the DUT ground are simply steps needed for the
test and evaluation of devices. Actual designs would include high-impedance
receivers, which would not require the setup steps outlined above.
1 As delivered R2, R3, and R4 are not installed
Typical Test Results
2-6
LVPECL drivers need a 50-Ω termination to VT. A modification of Figure 2-2
and the above instructions are used when evaluating an SN65LVDS101 with
a direct connection to a 50-Ω oscilloscope. With power supply 1 in Figure 2-2
set to 3.3 V, power supply 2 should be set to 1.3 V (2 V below VCC) to provide
the correct termination voltage.
CML drivers need a 50-Ω termination to VTT (VTT is either VCC, 2.5 V, or
1.8 V). A modification of Figure 2-2 and the instructions for the SN65LVDS100
are used when evaluating a SN65CML100 with direct connection to a 50-Ω
oscilloscope. With power supply 1 in Figure 2-2 set to 3.3 V, power supply 2
should be set to either VCC (3.3 V), 2.5 V, or 1.8 V to provide the correct
termination voltage.
Dual termination of the output can be achieved by placing 49.9-Ω resistors at
R2 and R3 and connecting to an oscilloscope as described above.
If the EVM outputs are to be evaluated with a high-impedance probe, direct
probing on the EVM is supported via installation of R2, R3, and R4. LVDS
outputs can be observed by installing R4, a 100-Ω resistor. LVPECL outputs
can be observed by installing R2 and R3 (49.9-Ω resistors), and setting power
supply 2 to 1.3 V. CML outputs can be observed by setting power supply 2 to
VTT and installing 49.9-Ω resistors at R2 and R3 for single termination, or
24.9-Ω resistors at R2 and R3 for dual termination (Note that power supply 2
must be able to sink current.)
2.4 Typical Test Results
Figure 2-5 shows a typical test result obtained with the EVM. Figure 2-5
shows the output of an SN65LVDS100 being driven directly into a 50-Ω
oscilloscope. For this figure, the SN65LVDS100 was stimulated with an HP
3-GBPS BERT. The input data was pseudorandom data at 2 GBPS and with
a random record length of 223-1. The BERT drove two electrically matched
one-meter cables with an electrical length of 3.667 ns. These cables were then
connected to the EVM inputs. The EVM outputs were connected through
another set of electrically matched one-meter cables and terminated by a
TDS8000 oscilloscope’s 50-Ω resistors to ground.
Typical Test Results
Setup and Equipment Required 2-7
Figure 2-5. Typical Output From SN65LVDS100 EVM
2-8
EVM Construction 3-1
EVM Construction
This chapter lists the EVM components and examines the construction of the
evaluation module.
Topic Page
3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4 Board Layer Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Chapter 3
Schematic
3-2
3.1 Schematic
NC
A
B
Vbb
VCC
Y
Z
GND
R5
Uninstalled
JMP2
1
2
C12
.010 μF
DUT_MSOP8
DUT1
VCC01
VCC
C11
.010 μF
R2
Uninstalled
J6
GND
J7
GND
R4
Uninstalled
R3
Uninstalled
J4 R1 100 Ω
GND
J5
GND
1
1
1
2
3
4
8
7
6
5
1
1
VCC
VCC01
+
+
+
+
C1
10 μF
C6
10 μF
C2
68 μF
C7
68 μF
C3
1 μF
C8
1 μF
C4
0.1 μF
C9
0.1 μF
C5
0.001 μF
109
0.001 μF
J1 -1
J2 -1
J3 -1
MNTH1
MNTH2
MNTH3
MNTH4
Bill of Materials
EVM Construction 3-3
3.2 Bill of Materials
ITEM QTY MFG MFG PART NO. REF.
DES.
DESCRIPTION VALUE OR
FUNCTION
NOT
INSTALLED
1 2 Sprague 293D106X0035D2W C1,C6 Capacitor, SMT,
TANT
35 V, 10%, 10 μF
2 2 AVX 12063G105ZATRA C3,C8 Capacitor, SMT1206 25 V, 80 -20%, 1.0
μF
3 2 AVX 12065C104JATMA C4,C9 Capacitor, SMT1206 50 V, 5%, 0.1 μF
4 2 Sprague 592D686X0010R2T C2,C7 Capacitor, SMT,
TANT
10 V, 20%,
68 μF, Low ESR
5 2 Murata GRM39X7R103K50V C11,
C12
Capacitor, SMT0603 50 V,±10%,
0.010 μF
6 2 AVX 06033G102JATMA C5,C10 Capacitor, SMT0603 25 V, 5%,
0.001 μF
7 3 ITT-Pomona 3267 J1, J2,
J3
Connector, banana
jack
Bannana jack
8 4 EF Johnson 142-0701-801 J4, J5,
J6, J7
Connector SMA Jack, end
launch, 0.062
9 1 Dale CRCW0603100F R1 Resistor, SMT,0603 100 Ω
10 2 R2, R3 Resistor, SMT, 0603 49.9 Ω R2, R3
11 1 R4 Resistor, SMT, 0603 100 Ω R4
12 1 R5 Resistor, SMT, 0603 0 Ω R5
13 1 AMP 4-103239-0x2 JMP2 Header Male, 2 pin,
0.100 CC
14 1 TI SN65LVDS100†
SN65LVDS101†
DUT1 IC, SMT, 8P 2-GBPS differential
repeater/translator
15 3 Screws
16 3 Nuts
17 1 User’s manual
18 1 Data sheet
† Only one is installed
Board Stackup
3-4
3.3 Board Stackup
9
Copper Foil CH A1
Copper Foil CH A1
.0062 PREPREG
.0062 PREPREG
CORE .015 C1/0 A1
.0122 PREPREG
CORE .015 C0/1 A1
SECTION A - A
NO SCALE
TOP SIDE-SIGNAL/GND FILL (LAYER 1)
INT1-GND PLANE (LAYER 2)
INT2-VCC SPLIT PLANE (LAYER 3)
9 BOTTOM SIDE-GND PLANE (LAYER 4)
Symbol Diameter (in)
0.0160
0.0320
0.0400
0.0500
0.1250
0.2720
Plated
Yes
Yes
Yes
Yes
Yes
Yes
Quantity
49
82343
Through Holes
3.000
A A
3.000
DATUM 0,0
TOP SIDE SHOWN
DRILL
0.250
0.250
NN
THIS IS AN IMPEDANCE CONTROLLED BOARD.
GENERAL NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL FABRICATION ITEMS MUST MEET OR EXCEED BEST
INDUSTRY PRACTICE. IPC-A 600C ( Commercial Std.)
2.LAMINATE MATERIAL: NELCO N4000-13 (DO NOT USE - 13SI)
3. COOPER WEIGHT:1 OZ. START INTERNAL AND 1/2 OZ. START EXTERNAL
4. FINISHED BOARD THICKNESS: .062 ±10%
5. MAXIMUM WARP AND TWIST TO BE .005 INCH PER INCH
6 MINIMUM COPPER WALL THICKNESS OF PLATED-THRU
HOLES TO BE .001 INCH
7 MINIMUM ANNULAR RING OF PLATED-THRU
HOLES TO BE .002 INCH
8. MINIMUM ALLOWABLE LINE REDUCTION TO BE
20% OR .002 WHICHEVER IS GREATER
9. 0.013 INCH SIGNAL LINES ON LAYER 1 TO BE
IMPEDANCE CONTROLLED 50 OHMS TO GND ±10%
0.010 INCH SIGNAL LINES ON LAYER 1 TO BE
IMPEDANCE CONTROLLED 100 OHMS TO EACH OTHER ±10%
10. DIELECTRIC CONSTANTS ARE:
CORE: 3.2
PREPREG:3.2
PROCESS NOTES:
1. CIRCUITRY ON OUTER LAYERS TO BE PLATED WITH TIN LEAD
2. SOLDERMASK BOTH SIDES PER ARTWORK: GREEN LPI
3. SILKSCREEN BOTH SIDE PER ARTWORK: COLOR=WHITE
4
N
6434666A PWA, BENCH, EVALUATION BOARD, SN65LVDS100/101D, EVM 10/31/01
Board Layer Patterns
EVM Construction 3-5
3.4 Board Layer Patterns
(Not to Scale)
Layer 1 - Signal/GND Fill (Top Side)
Layer 2 - GND Plane (INT1)
Board Layer Patterns
3-6
Layer 3 - VCC Split Plane (INT2)
Layer 4 - GND Plane (Bottom Side)
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
Piccolo Microcontrollers
Check for Samples: TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050
1 TMS320F2805x ( Piccolo™) MCUs
1.1 Features
123
• Highlights • Programmable Control Law Accelerator (CLA)
– High-Efficiency 32-Bit CPU ( TMS320C28x™) – 32-Bit Floating-Point Math Accelerator
– 60-MHz Device – Executes Code Independently of the Main
– Single 3.3-V Supply CPU
– Integrated Power-on and Brown-out Resets • Low Device and System Cost:
– Two Internal Zero-pin Oscillators – Single 3.3-V Supply
– Up to 42 Multiplexed GPIO Pins – No Power Sequencing Requirement
– Three 32-Bit CPU Timers – Integrated Power-on Reset and Brown-out
– On-Chip Flash, SARAM, Message RAM, OTP, Reset
CLA Data ROM, Boot ROM, Secure ROM – Low Power
Memory – No Analog Support Pins
– Dual-Zone Security Module • Clocking:
– Serial Port Peripherals (SCI/SPI/I2C/eCAN) – Two Internal Zero-pin Oscillators
– Enhanced Control Peripherals – On-Chip Crystal Oscillator/External Clock
• Enhanced Pulse Width Modulator (ePWM) Input
• Enhanced Capture (eCAP) – Dynamic PLL Ratio Changes Supported
• Enhanced Quadrature Encoder Pulse – Watchdog Timer Module
(eQEP) – Missing Clock Detection Circuitry
– Analog Peripherals • Up to 42 Individually Programmable,
• One 12-Bit Analog-to-Digital Converter Multiplexed GPIO Pins With Input Filtering
(ADC) • Peripheral Interrupt Expansion (PIE) Block That
• One On-Chip Temperature Sensor Supports All Peripheral Interrupts
• Up to Seven Comparators With up to • Three 32-Bit CPU Timers
Three Integrated Digital-to-Analog • Independent 16-Bit Timer in Each ePWM
Converters (DACs) Module
• One Buffered Reference DAC • On-Chip Memory
• Up to Four Programmable Gain – Flash, SARAM, Message RAM, OTP, CLA
Amplifiers (PGAs) Data ROM, Boot ROM, Secure ROM Available
• Up to Four Digital Filters • 128-Bit Security Key and Lock
– 80-Pin Package – Protects Secure Memory Blocks
• High-Efficiency 32-Bit CPU ( TMS320C28x™) – Prevents Firmware Reverse Engineering
– 60 MHz (16.67-ns Cycle Time) • Serial Port Peripherals
– 16 x 16 and 32 x 32 MAC Operations – Three SCI (UART) Modules
– 16 x 16 Dual MAC – One SPI Module
– Harvard Bus Architecture – One Inter-Integrated-Circuit (I2C) Bus
– Atomic Operations – One Enhanced Controller Area Network
– Fast Interrupt Response and Processing (eCAN) Bus
– Unified Memory Programming Model • Advanced Emulation Features
– Code-Efficient (in C/C++ and Assembly) – Analysis and Breakpoint Functions
• Endianness: Little Endian – Real-Time Debug via Hardware
• 80-Pin PN Low-Profile Quad Flatpack (LQFP)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510, XDS560 are trademarks of Texas
Instruments.
3All other trademarks are the property of their respective owners.
ADVANCE INFORMATION concerns new products in the sampling or preproduction Copyright © 2012, Texas Instruments Incorporated
phase of development. Characteristic data and other specifications are subject to change
without notice.
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797 –NOVEMBER 2012 www.ti.com
1.2 Description
The F2805x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law
Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family
is code-compatible with previous C28x-based code, as well as providing a high level of analog integration.
An internal voltage regulator allows for single rail operation. Analog comparators with internal 6-bit
references have been added and can be routed directly to control the PWM outputs. The ADC converts
from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The ADC
interface has been optimized for low overhead/latency.
The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to-
Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers
(PGAs), and up to four digital filters. The Programmable Gain Amplifiers (PGAs) are capable of amplifying
the input signal in three discrete gain modes. The actual gain itself depends on the resistors defined by
the user at the bipolar input end. The actual number of AFE peripherals will depend upon the 2805x
device number. See Table 2-1 for more details.
2 TMS320F2805x ( Piccolo™) MCUs Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
M0
SARAM 1Kx16
(0-wait)
16-bit Peripheral Bus
M1
SARAM 1Kx16
(0-wait)
SCI-A,
B C
(4L FIFO)
SCI- , SCI-
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
ePWM1–ePWM7
SPI-A
(4L FIFO)
I2C-A
(4L FIFO)
32-Bit
Peripheral Bus
GPIO MUX
C28x CPU
(60 MHz)
PIE
(up to 96 interrupts)
CPU Timer 0
CPU Timer 1
CPU Timer 2
TRST
TCK
TDI
TMS
TDO
OSC1,
OSC2,
Ext,
PLL,
LPM,
WD
X2
32-bit Peripheral Bus
(CLA-accessible)
EPWMxA
EPWMxB
SDAx
SCLx
SCIRXDx
GPIO
Mux
LPM Wakeup
CLA +
Message RAMs
ADC
0-wait
Result
Regs
Boot ROM
12Kx16
(0-wait)
Non-Secure
L0 SARAM (2Kx16)
(0-wait, Secure)
CLA Data RAM2
COMP
+
Digital
COMPAn Filter
COMPBn
32-bit Peripheral Bus
(CLA-accessible)
eCAN-A
(32-mbox)
eCAP
ECAPx
CANTXx
CANRXx
eQEP
EQEPxA
EQEPxB
EQEPxI
EQEPxS
SCITXDx
X1
GPIO
MUX
Program-
mable
Gain
Amps
VREG
POR/
BOR
Memory Bus
Memory Bus
TZx
Secure ROM
(A)
2Kx16
(0-wait)
Secure
L1 DPSARAM (1Kx16)
(0-wait, Secure)
CLA Data RAM0
L2 DPSARAM (1Kx16)
(0-wait, Secure)
CLA Data RAM1
L3 DPSARAM (4Kx16)
(0-wait, Secure)
CLA Program RAM
CLA Data ROM
(4Kx16)
CTRIPnOUT
ADC
3.75
MSPS
32-bit Peripheral Bus
(CLA-accessible)
CLA Bus
XRS
GPIO
Mux
XCLKIN
3 External Interrupts
Memory Bus
EPWMSYNCI
EPWMSYNCO
PSWD
Dual-
Zone
Security
Module
+
ECSL
OTP/Flash Wrapper
Z1/Z2 User OTP
Secure
PUMP
FLASH
28055, 28054: 64K x 16, 10 Sectors
28053, 28052, 28051: 32K x 16, 5 Sectors
28050: 16K x 16, 3 Sectors
Secure
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
1.3 Functional Block Diagram
A. Stores Secure Copy Code Functions on all devices.
B. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
Copyright © 2012, Texas Instruments Incorporated TMS320F2805x ( Piccolo™) MCUs 3
Submit Documentation Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797 –NOVEMBER 2012 www.ti.com
1 TMS320F2805x ( Piccolo™) MCUs .................. 1 5.1 Power Sequencing ................................. 58
1.1 Features ............................................. 1 5.2 Clocking ............................................ 60
1.2 Description ........................................... 2 5.3 Interrupts ............................................ 63
1.3 Functional Block Diagram ........................... 3 6 Peripheral Information and Timings ............... 68
2 Device Overview ........................................ 5 6.1 Parameter Information .............................. 68
2.1 Device Characteristics ............................... 5 6.2 Control Law Accelerator (CLA) ..................... 69
2.2 Memory Maps ........................................ 8 6.3 Analog Block ........................................ 72
2.3 Brief Descriptions ................................... 15 6.4 Serial Peripheral Interface (SPI) .................... 91
2.4 Register Map ....................................... 26 6.5 Serial Communications Interface (SCI) ........... 100
2.5 Device Emulation Registers ........................ 28 6.6 Enhanced Controller Area Network (eCAN) ...... 103
2.6 VREG, BOR, POR .................................. 30 6.7 Inter-Integrated Circuit (I2C) ...................... 107
2.7 System Control ..................................... 32 6.8 Enhanced Pulse Width Modulator (ePWM) ....... 110
2.8 Low-power Modes Block ........................... 40 6.9 Enhanced Capture Module (eCAP) ............... 118
2.9 Thermal Design Considerations .................... 40 6.10 Enhanced Quadrature Encoder Pulse (eQEP) .... 120
3 Device Pins ............................................. 41 6.11 JTAG Port ......................................... 123
3.1 Pin Assignments .................................... 41 6.12 General-Purpose Input/Output (GPIO) ............ 125
3.2 Terminal Functions ................................. 42 7 Device and Documentation Support ............. 136
4 Device Operating Conditions ....................... 50 7.1 Device Support .................................... 136
4.1 Absolute Maximum Ratings ........................ 50 7.2 Documentation Support ........................... 138
4.2 Recommended Operating Conditions .............. 50 7.3 Community Resources ............................ 138
4.3 Electrical Characteristics Over Recommended 8 Mechanical Packaging and Orderable
Operating Conditions (Unless Otherwise Noted) ... 51 Information ............................................ 139
4.4 Current Consumption ............................... 52 8.1 Thermal Data for Package ........................ 139
4.5 Flash Timing ........................................ 56 8.2 Packaging Information ............................ 139
5 Power, Reset, Clocking, and Interrupts ........... 58
4 Contents Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
2 Device Overview
2.1 Device Characteristics
Table 2-1 lists the features of the TMS320F2805x devices.
Copyright © 2012, Texas Instruments Incorporated Device Overview 5
Submit Documentation Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797 –NOVEMBER 2012 www.ti.com
Table 2-1. TMS320F2805x Hardware Features
FEATURE 28055 28054 28053 28052 28051 28050 (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz)
Package Type 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN LQFP LQFP LQFP LQFP LQFP LQFP
Instruction cycle 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns
Control Law Accelerator (CLA) Yes No Yes No No No
On-chip flash (16-bit word) 64K 64K 32K 32K 32K 16K
On-chip SARAM (16-bit word) 10K 10K 10K 10K 8K 6K
Dual-zone security for on-chip Flash, SARAM, OTP, Yes Yes Yes Yes Yes Yes and Secure ROM blocks
Boot ROM (12K x 16) Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM 1K 1K 1K 1K 1K 1K (16-bit word)
ePWM outputs 14 14 14 14 14 14
eCAP inputs 1 1 1 1 1 1
eQEP modules 1 1 1 1 1 1
Watchdog timer Yes Yes Yes Yes Yes Yes
MSPS 3.75 3.75 3.75 3.75 2 2
Conversion Time 267 ns 267 ns 267 ns 267 ns 500 ns 500 ns
12-Bit ADC Channels 16 16 16 16 16 16
Temperature Sensor Yes Yes Yes Yes Yes Yes
Dual Yes Yes Yes Yes Yes Yes Sample-and-Hold
Programmable Gain Amplifier (PGA) 4 4 4 4 4 3 (Gains = ~3, ~6, ~11)
Fixed Gain Amplifier 3 3 3 3 3 4 (Gain = ~3)
Comparators 7 7 7 7 7 6
Internal Comparator Reference DACs 3 3 3 3 3 2
Buffered Reference DAC 1 1 1 1 1 1
32-Bit CPU timers 3 3 3 3 3 3
Inter-integrated circuit (I2C) 1 1 1 1 1 1
Enhanced Controller Area Network (eCAN) 1 1 1 1 1 1
Serial Peripheral Interface (SPI) 1 1 1 1 1 1
Serial Communications Interface (SCI) 3 3 3 3 3 3
0-pin Oscillators 2 2 2 2 2 2
I/O pins (shared) GPIO 42 42 42 42 42 42
External interrupts 3 3 3 3 3 3
Supply voltage (nominal) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
6 Device Overview Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
Table 2-1. TMS320F2805x Hardware Features (continued)
FEATURE 28055 28054 28053 28052 28051 28050 (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz)
T: –40ºC to 105ºC Yes Yes Yes Yes Yes Yes
Temperature options
S: –40ºC to 125ºC Yes Yes Yes Yes Yes Yes
Product status(1) TMX TMX TMX TMX TMX TMX
(1) See Section 7.1.2, Device and Development Support Tool Nomenclature, for descriptions of device stages. The "TMX" product status denotes an experimental device that is not
necessarily representative of the final device's electrical specifications.
Copyright © 2012, Texas Instruments Incorporated Device Overview 7
Submit Documentation Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797 –NOVEMBER 2012 www.ti.com
2.2 Memory Maps
In Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps
are restricted to data memory only. A user program cannot access these memory maps in program
space.
• Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline
order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
8 Device Overview Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
Data Space Prog Space
Reserved
0x00 2000 Reserved
Peripheral Frame 1
(1K x 16, Protected)
0x00 6000
Peripheral Frame 3
(1.5K x 16, Protected)
0x00 6400
Peripheral Frame 1
(1.5K x 16, Protected)
0x00 6A00
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
Reserved
0x00 0800 Peripheral Frame 0
0x00 1580 Peripheral Frame 0
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 1400
0x00 0E00
0x00 1500
0x00 1480
CPU-to-CLA Message RAM
CLA-to-CPU Message RAM
CLA Registers
Peripheral Frame 0
0x00 8000
L0 DPSARAM (2K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2)
0x00 8800
L1 DPSARAM (1K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00
L2 DPSARAM (1K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)
0x00 9000
L3 DPSARAM (4K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)
0x3D 7800 User OTP, Zone 2 Passwords (512 x 16)
0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16)
0x00 F000 CLA Data ROM (4K x 16)
0x00 A000 Reserved
0x01 0000
Reserved
0x3D 7C00
Reserved
0x3D 7E00
Calibration Data
FLASH
(64K x 16, 10 Sectors, Dual Secure Zone + ECSL)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3E 8000
0x3F 7FFF
Zone 1 Secure Copy Code ROM
(1K x 16)
0x3F 8000
Zone 2 Secure Copy Code ROM
(1K x 16)
0x3F 8400
0x3D 7FCB
Configuration Data
0x3F FFC0
0x3F D000
Vector (32 Vectors, Enabled if VMAP = 1)
Boot ROM (12K x 16, 0-Wait)
0x3D 7FF0
Reserved
0x3F 8800
Reserved
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
A. CLA-specific registers and RAM apply to the 28055 device only.
Figure 2-1. 28055 and 28054 Memory Map
Copyright © 2012, Texas Instruments Incorporated Device Overview 9
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Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
Data Space Prog Space
Reserved
0x00 2000 Reserved
Peripheral Frame 1
(1K x 16, Protected)
0x00 6000
Peripheral Frame 3
(1.5K x 16, Protected)
0x00 6400
Peripheral Frame 1
(1.5K x 16, Protected)
0x00 6A00
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
Reserved
0x00 0800 Peripheral Frame 0
0x00 1580 Peripheral Frame 0
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 1400
0x00 0E00
0x00 1500
0x00 1480
CPU-to-CLA Message RAM
CLA-to-CPU Message RAM
CLA Registers
Peripheral Frame 0
0x00 8000
L0 DPSARAM (2K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2)
0x00 8800
L1 DPSARAM (1K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00
L2 DPSARAM (1K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)
0x00 9000
L3 DPSARAM (4K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)
0x3D 7800 User OTP, Zone 2 Passwords (512 x 16)
0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16)
0x00 F000 CLA Data ROM (4K x 16)
0x00 A000 Reserved
0x01 0000
Reserved
0x3D 7C00
Reserved
0x3D 7E00
Calibration Data
FLASH
(32K x 16, 5 Sectors, Dual Secure Zone + ECSL)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 0000
0x3F 7FFF
Zone 1 Secure Copy Code ROM
(1K x 16)
0x3F 8000
Zone 2 Secure Copy Code ROM
(1K x 16)
0x3F 8400
0x3D 7FCB
Configuration Data
0x3F FFC0
0x3F D000
Vector (32 Vectors, Enabled if VMAP = 1)
Boot ROM (12K x 16, 0-Wait)
0x3D 7FF0
Reserved
0x3F 8800
Reserved
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797 –NOVEMBER 2012 www.ti.com
A. CLA-specific registers and RAM apply to the 28053 device only.
Figure 2-2. 28053 and 28052 Memory Map
10 Device Overview Copyright © 2012, Texas Instruments Incorporated
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TMS320F28050
ADVANCE INFORMATION
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
Data Space Prog Space
Reserved
0x00 2000 Reserved
Peripheral Frame 1
(1K x 16, Protected)
0x00 6000
Peripheral Frame 3
(1.5K x 16, Protected)
0x00 6400
Peripheral Frame 1
(1.5K x 16, Protected)
0x00 6A00
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
Reserved
0x00 0800 Peripheral Frame 0
0x00 1580 Peripheral Frame 0
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 1400
0x00 0E00
0x00 1500
0x00 1480
CPU-to-CLA Message RAM
CLA-to-CPU Message RAM
CLA Registers
Peripheral Frame 0
0x00 8000
0x00 8800
L1 DPSARAM (1K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00
L2 DPSARAM (1K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)
0x00 9000
L3 DPSARAM (4K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)
0x3D 7800 User OTP, Zone 2 Passwords (512 x 16)
0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16)
0x00 F000 CLA Data ROM (4K x 16)
0x00 A000 Reserved
0x01 0000
Reserved
0x3D 7C00
Reserved
0x3D 7E00
Calibration Data
FLASH
(32K x 16, 5 Sectors, Dual Secure Zone + ECSL)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 0000
0x3F 7FFF
Zone 1 Secure Copy Code ROM
(1K x 16)
0x3F 8000
Zone 2 Secure Copy Code ROM
(1K x 16)
0x3F 8400
0x3D 7FCB
Configuration Data
0x3F FFC0
0x3F D000
Vector (32 Vectors, Enabled if VMAP = 1)
Boot ROM (12K x 16, 0-Wait)
0x3D 7FF0
Reserved
0x3F 8800
Reserved
Reserved
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Figure 2-3. 28051 Memory Map
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M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
Data Space Prog Space
Reserved
0x00 2000 Reserved
Peripheral Frame 1
(1K x 16, Protected)
0x00 6000
Peripheral Frame 3
(1.5K x 16, Protected)
0x00 6400
Peripheral Frame 1
(1.5K x 16, Protected)
0x00 6A00
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
Reserved
0x00 0800 Peripheral Frame 0
0x00 1580 Peripheral Frame 0
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 1400
0x00 0E00 Peripheral Frame 0
0x00 8000
L0 DPSARAM (2K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL)
0x00 8800
L1 DPSARAM (1K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL)
0x00 8C00
L2 DPSARAM (1K x 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL)
0x00 9000
0x3D 7800 User OTP, Zone 2 Passwords (512 x 16)
0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16)
0x00 F000
0x00 A000 Reserved
0x01 0000
Reserved
0x3D 7C00
Reserved
0x3D 7E00
Calibration Data
FLASH
(16K x 16, 3 Sectors, Dual Secure Zone + ECSL)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 4000
0x3F 7FFF
Zone 1 Secure Copy Code ROM
(1K x 16)
0x3F 8000
Zone 2 Secure Copy Code ROM
(1K x 16)
0x3F 8400
0x3D 7FCB
Configuration Data
0x3F FFC0
0x3F D000
Vector (32 Vectors, Enabled if VMAP = 1)
Boot ROM (12K x 16, 0-Wait)
0x3D 7FF0
Reserved
0x3F 8800
Reserved
Reserved
Reserved
Reserved
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Figure 2-4. 28050 Memory Map
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Table 2-2. Addresses of Flash Sectors in F28055 and F28054
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3E 8000 – 0x3E 8FFF Sector J (4K x 16)
0x3E 9000 – 0x3E 9FFF Sector I (4K x 16)
0x3E A000 – 0x3E BFFF Sector H (8K x 16)
0x3E C000 – 0x3E DFFF Sector G (8K x 16)
0x3E E000 – 0x3E FFFF Sector F (8K x 16)
0x3F 0000 – 0x3F 1FFF Sector E (8K x 16)
0x3F 2000 – 0x3F 3FFF Sector D (8K x 16)
0x3F 4000 – 0x3F 5FFF Sector C (8K x 16)
0x3F 6000 – 0x3F 6FFF Sector B (4K x 16)
0x3F 7000 – 0x3F 7FFF Sector A (4K x 16)
Table 2-3. Addresses of Flash Sectors in F28053, F28052, and F28051
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3F 0000 – 0x3F 1FFF Sector E (8K x 16)
0x3F 2000 – 0x3F 3FFF Sector D (8K x 16)
0x3F 4000 – 0x3F 5FFF Sector C (8K x 16)
0x3F 6000 – 0x3F 6FFF Sector B (4K x 16)
0x3F 7000 – 0x3F 7FFF Sector A (4K x 16)
Table 2-4. Addresses of Flash Sectors in F28050
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3F 4000 – 0x3F 5FFF Sector C (8K x 16)
0x3F 6000 – 0x3F 6FFF Sector B (4K x 16)
0x3F 7000 – 0x3F 7FFF Sector A (4K x 16)
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Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these
blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to
these blocks happen as written. Because of the pipeline, a write immediately followed by a read to
different memory locations will appear in reverse order on the memory bus of the CPU. This action can
cause problems in certain peripheral applications where the user expected the write to occur first (as
written). The CPU supports a block protection mode where a region of memory can be protected so that
operations occur as written (the penalty is extra cycles are added to align the operations). This mode is
programmable, and by default, it protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 2-5.
Table 2-5. Wait-States
AREA WAIT-STATES (CPU) COMMENTS
M0 and M1 SARAMs 0-wait Fixed
Peripheral Frame 0 0-wait
Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready.
2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
Peripheral Frame 3 0-wait (writes) Assumes no conflict between CPU and CLA.
2-wait (reads) Cycles can be extended by peripheral-generated ready.
L0 SARAM 0-wait data and program Assumes no CPU conflicts
L1 SARAM 0-wait data and program Assumes no CPU conflicts
L2 SARAM 0-wait data and program Assumes no CPU conflicts
L3 SARAM 0-wait data and program Assumes no CPU conflicts
OTP Programmable Programmed via the Flash registers.
1-wait minimum 1-wait is minimum number of wait states allowed.
FLASH Programmable Programmed via the Flash registers.
0-wait Paged min
1-wait Random min
Random ≥ Paged
FLASH Password 16-wait fixed Wait states of password locations are fixed.
Boot-ROM 0-wait
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2.3 Brief Descriptions
2.3.1 CPU
The 2805x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28xbased
controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. Each C28x-based
controller, including the 2805x device, is a very efficient C/C++ engine, enabling users to develop not only
their system control software in a high-level language, but also enabling development of math algorithms
using C/C++. The device is as efficient at MCU math tasks as it is at system control tasks. This efficiency
removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing
capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this
feature the fast interrupt response with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. The device has an 8-leveldeep
protected pipeline with pipelined memory accesses. This pipelining enables the device to execute at
high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.
2.3.2 Control Law Accelerator (CLA)
The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the
capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its
own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be
specified. Each task is started by software or a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU
Timer 0. The CLA executes one task at a time to completion. When a task completes the main CPU is
notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task.
The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP, and the Comparator and
DAC registers. Dedicated message RAMs provide a method to pass additional data between the main
CPU and the CLA.
2.3.3 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and
data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus
accesses can be summarized as follows:
Highest: Data Writes (Simultaneous data and program writes cannot occur on the
memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the
memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the
memory bus.)
Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the
memory bus.)
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2.3.4 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the
devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various busses that make up the processor Memory Bus into a single bus consisting of 16 address
lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are
supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports CLA access
and both 16- and 32-bit accesses (called peripheral frame 3).
2.3.5 Real-Time JTAG and Analysis
The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug.
Additionally, the devices support real-time mode of operation allowing modification of the contents of
memory, peripheral, and register locations while the processor is running and executing code and
servicing interrupts. The user can also single step through non-time-critical code while enabling timecritical
interrupts to be serviced without interference. The device implements the real-time mode in
hardware within the CPU. This feature is unique to the 28x family of devices, and requires no software
monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or
data/address watch-points and generating various user-selectable break events when a match occurs.
These devices do not support boundary scan; however, IDCODE and BYPASS features are available if
the following considerations are taken into account. The IDCODE does not come by default. The user
needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For
BYPASS instruction, the first shifted DR value would be 1.
2.3.6 Flash
The F28055 and F28054 devices contain 64K x 16 of embedded flash memory, segregated into six
8K x 16 sectors and four 4K x 16 sectors. The F28053, F28052, and F28051 devices contain 32K x 16 of
embedded flash memory, segregated into three 8K x 16 sectors and two 4K x 16 sectors. The F28050
device contains 16K x 16 of embedded flash memory, segregated into one 8K x 16 sector and two 4K x
16 sectors. The devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 –
0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other
sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash
algorithms that erase or program other sectors. Special memory pipelining is provided to enable the flash
module to achieve higher performance. The flash/OTP is mapped to both program and data space;
therefore, the flash/OTP can be used to execute code or store data information.
NOTE
The Flash and OTP wait-states can be configured by the application. This feature allows
applications running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical
Reference Manual (literature number SPRUHE5).
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
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2.3.7 M0, M1 SARAMs
All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a
unified memory map to the programmer, which makes for easier programming in high-level languages.
2.3.8 L0 SARAM, and L1, L2, and L3 DPSARAMs
The device contains up to 8K x 16 of single-access RAM. To ascertain the exact size for a given device,
see the device-specific memory map figures in Section 2.2. This block is mapped to both program and
data space. Block L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2
are both 1K in size, and together with L0, are shared with the CLA which can ultilize these blocks for its
data space. Block L3 is 4K in size and is shared with the CLA which can ultilize this block for its program
space. DPSARAM refers to the dual-port configuration of these blocks.
2.3.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math-related algorithms.
Table 2-6. Boot Mode Selection
MODE GPIO37/TDO GPIO34/COMP2OUT/ TRST MODE COMP3OUT
3 1 1 0 GetMode
2 1 0 0 Wait (see Section 2.3.10 for description)
1 0 1 0 SCI
0 0 0 0 Parallel IO
EMU x x 1 Emulation Boot
2.3.9.1 Emulation Boot
When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this
case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM
locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,
then the Wait boot option is used. All boot mode options can be accessed in emulation boot.
2.3.9.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another
boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then
boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP.
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2.3.9.3 Peripheral Pins Used by the Bootloader
Table 2-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table
to see if these conflict with any of the peripherals you would like to use in your application.
Table 2-7. Peripheral Bootload Pins
BOOTLOADER PERIPHERAL LOADER PINS
SCI SCIRXDA (GPIO28)
SCITXDA (GPIO29)
Parallel Boot Data (GPIO31,30,5:0)
28x Control (GPIO26)
Host Control (GPIO27)
SPI SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
I2C SDAA (GPIO28)
SCLA (GPIO29)
CAN CANRXA (GPIO30)
CANTXA (GPIO31)
2.3.10 Security
The TMS320F2805x device supports high levels of security with a dual-zone (Z1/Z2) feature to protect
user's firmware from being reverse-engineered. The dual-zone feature enables the user to co-develop
application software with a third-party or sub-contractor by preventing visibility into each other's software
IP. The security features a 128-bit password (hardcoded for 16 wait states) for each zone, which the user
programs into the USER-OTP. Each zone has its own dedicated USER-OTP, which needs to be
programmed by the user with the required security settings, including the 128-bit password. Since OTP
cannot be erased, in order to provide the user with the flexibility of changing security-related settings and
passwords multiple times, a 32-bit link pointer is stored at the beginning of each USER-OTP. Considering
the fact that user can only flip a ‘1’ in USER-OTP to ‘0’, the most significant bit position in the link pointer,
programmed as 0, defines the USER-OTP region (zone-select) for each zone in which security-related
settings and passwords are stored.
Table 2-8. Location of Zone-Select Block Based on Link Pointer
Zx LINK POINTER VALUE ADDRESS OFFSET FOR ZONE-SELECT
32’bxx111111111111111111111111111111 0x10
32’bxx111111111111111111111111111110 0x20
32’bxx11111111111111111111111111110x 0x30
32’bxx1111111111111111111111111110xx 0x40
32’bxx111111111111111111111111110xxx 0x50
32’bxx11111111111111111111111110xxxx 0x60
32’bxx1111111111111111111111110xxxxx 0x70
32’bxx111111111111111111111110xxxxxx 0x80
32’bxx11111111111111111111110xxxxxxx 0x90
32’bxx1111111111111111111110xxxxxxxx 0xa0
32’bxx111111111111111111110xxxxxxxxx 0xb0
32’bxx11111111111111111110xxxxxxxxxx 0xc0
32’bxx1111111111111111110xxxxxxxxxxx 0xd0
32’bxx111111111111111110xxxxxxxxxxxx 0xe0
32’bxx11111111111111110xxxxxxxxxxxxx 0xf0
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Table 2-8. Location of Zone-Select Block Based on Link Pointer (continued)
Zx LINK POINTER VALUE ADDRESS OFFSET FOR ZONE-SELECT
32’bxx1111111111111110xxxxxxxxxxxxxx 0x100
32’bxx111111111111110xxxxxxxxxxxxxxx 0x110
32’bxx11111111111110xxxxxxxxxxxxxxxx 0x120
32’bxx1111111111110xxxxxxxxxxxxxxxxx 0x130
32’bxx111111111110xxxxxxxxxxxxxxxxxx 0x140
32’bxx11111111110xxxxxxxxxxxxxxxxxxx 0x150
32’bxx1111111110xxxxxxxxxxxxxxxxxxxx 0x160
32’bxx111111110xxxxxxxxxxxxxxxxxxxxx 0x170
32’bxx11111110xxxxxxxxxxxxxxxxxxxxxx 0x180
32’bxx1111110xxxxxxxxxxxxxxxxxxxxxxx 0x190
32’bxx111110xxxxxxxxxxxxxxxxxxxxxxxx 0x1a0
32’bxx11110xxxxxxxxxxxxxxxxxxxxxxxxx 0x1b0
32’bxx1110xxxxxxxxxxxxxxxxxxxxxxxxxx 0x1c0
32’bxx110xxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1d0
32’bxx10xxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1e0
32’bxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1f0
Table 2-9. Zone-Select Block Organization in USER-OTP
16-BIT ADDRESS OFFSET (WITH RESPECT TO OFFSET OF ZONE-SELECT) CONTENT
0x0
Zx-EXEONLYRAM
0x1
0x2
Zx-EXEONLYSECT
0x3
0x4
Zx-GRABRAM
0x5
0x6
Zx-GRABSECT
0x7
0x8
Zx-CSMPSWD0
0x9
0xa
Zx-CSMPSWD1
0xb
0xc
Zx-CSMPSWD2
0xd
0xe
Zx-CSMPSWD3
0xf
The Dual Code Security Module (DCSM) is used to protect the Flash/OTP/Lx SARAM blocks/CLA/Secure
ROM content. Individual flash sectors and SARAM blocks can be attached to any of the secure zone at
start-up time. Secure ROM and the CLA are always attached to Z1. Resources attached to (owned by)
one zone do not have any access to code running in the other zone when it is secured. Individual flash
sectors, as well as SARAM blocks, can be further protected by enabling the EXEONLY protection.
EXEONLY flash sectors or SARAM blocks do not have READ/WRITE access. Only code execution is
allowed from such memory blocks.
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The security feature prevents unauthorized users from examining memory contents via the JTAG port,
executing code from external memory, or trying to boot load an undesirable software that would export the
secure memory contents. To enable access to the secure blocks of a particular zone, the user must write
a 128-bit value in the zone’s CSMKEY registers that matches the values stored in the password locations
in USER-OTP. If the 128 bits of the password locations in USER-OTP of a particular zone are all ones
(un-programmed), then the security for that zone gets UNLOCKED as soon as a dummy read is done to
the password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this
case).
In addition to the DCSM, the Emulation Code Security Logic (ECSL) has been implemented for each zone
to prevent unauthorized users from stepping through secure code. A halt inside secure code will trip the
ECSL and break the emulation connection. To allow emulation of secure code while maintaining DCSM
protection against secure memory reads, the user must write the lower 64 bits of the USER-OTP
password into the zone's CSMKEY register to disable the ECSL. Note that dummy reads of all 128 bits of
the password for that particular zone in USER-OTP must still be performed. If the lower 64 bits of the
password locations of a particular zone are all zeros, then the ECSL for that zone gets disabled as soon
as a dummy read is done to the password locations in USER-OTP (the value in the CSMKEY register
becomes "Don’t care" in this case).
When initially debugging a device with the password locations in OTP (that is, secured), the CPU will start
running and may execute an instruction that performs an access to ECSL-protected area. If the CPU
execution is halted when the program counter belongs to the secure code region, the ECSL will trip and
cause the emulator connection to be cut. The solution is to use the Wait boot option. The Wait boot option
will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping
security. The user can then exit this mode once the emulator is connected by using one of the emulation
boot options as described in the Boot ROM chapter of the TMS320x2805x Piccolo Technical Reference
Manual (literature number SPRUHE5). 2805x devices do not support hardware wait-in-reset mode.
To prevent reverse-engineering of the code in secure zone, unauthorized users are prevented from
looking at the CPU registers in the CCS Expressions Window. The values in the Expressions Window for
all of these registers, except for PC and some status bits, display false values when code is running from
a secure zone. This feature gets disabled if the zone is unlocked.
NOTE
• The USER-OTP contains security-related settings for their respective zone. Execution is
not allowed from the USER-OTP; therefore, the user should not keep any code/data in
this region.
• The 128-bit password must not be programmed to zeros. Doing so would permanently
lock the device.
• The user must try not to write into the CPU registers through the debugger watch window
when code is running/halted from/inside secure zone. This may corrupt the execution of
the actual program.
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Disclaimer
Dual Code Security Module Disclaimer
THE DUAL CODE SECURITY MODULE (DCSM) INCLUDED ON THIS DEVICE WAS
DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED
MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS
(TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM
TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE
FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE DCSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE DCSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE DCSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
2.3.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2805x devices, 54 of the possible 96
interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed
into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector
stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched
by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save
critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is
controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE
block.
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2.3.12 External Interrupts (XINT1–XINT3)
The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be
selected for negative, positive, or both negative and positive edge triggering and can also be enabled or
disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero when a
valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. There are
no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from
GPIO0–GPIO31 pins.
2.3.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a
crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling
ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating
frequency if lower power operation is desired. Refer to Section 5.2 for timing details. The PLL block can
be set in bypass mode.
2.3.14 Watchdog
Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a
missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a
certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog
can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either
generate an interrupt or a device reset.
2.3.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled or disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled
relative to the CPU clock.
2.3.16 Low-power Modes
The devices are full-static CMOS devices. Three low-power modes are provided:
IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT: This mode basically shuts down the device and places the device in the lowest
possible power consumption mode. If the internal zero-pin oscillators are used as the
clock source, the HALT mode turns them off, by default. To keep these oscillators
from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The
zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the
on-chip crystal oscillator is used as the clock source, the crystal oscillator is shut
down in this mode. A reset or an external signal (through a GPIO pin) or the CPUwatchdog
can wake the device from this mode.
The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put
the device into HALT or STANDBY.
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2.3.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash: Flash Waitstate Registers
Timers: CPU-Timers 0, 1, 2 Registers
DCSM: Dual Zone Security Module Registers
ADC: ADC Result Registers
CLA Control Law Accelrator Registers and Message RAMs
PF1: GPIO: GPIO MUX Configuration and Control Registers
eCAN: Enhanced Control Area Network Configuration and Control Registers
eCAP: Enhanced Capture Module and Registers
eQEP: Enhanced Quadrature Encoder Pulse Module and Registers
PF2: SYS: System Control Registers
SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Configuration Registers
I2C: Inter-Integrated Circuit Module and Registers
XINT: External Interrupt Registers
PF3: ePWM: Enhanced Pulse Width Modulator Module and Registers
Comparators and Comparator Modules
Digital Filters:
eCAP: Enhanced Capture Module and Registers
eQEP: Enhanced Quadrature Encoder Pulse Module and Registers
ADC: ADC Status, Control, and Configuration Registers
ADC: ADC Result Registers
DAC: DAC Control Registers
2.3.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
muxing enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset,
GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or
peripheral signal mode. For specific inputs, the user can also select the number of input qualification
cycles. This selection is to filter unwanted noise glitches. The GPIO signals can also be used to bring the
device out of specific low-power modes.
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2.3.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, the counter is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use
and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. CPU-Timer 2 is
connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLKOUT (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTSOC2)
• External clock source
2.3.20 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM: The enhanced PWM peripheral supports independent/complementary
PWM generation, adjustable dead-band generation for leading/trailing
edges, latched/cycle-by-cycle trip mechanism. The type 1 module found on
2805x devices also supports increased dead-band resolution, enhanced
SOC and interrupt generation, and advanced triggering including trip
functions based on comparator outputs.
eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up
to four programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM
signal.
eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports
low-speed measurement using capture unit and high-speed measurement
using a 32-bit unit timer. This peripheral has a watchdog timer to detect
motor stall and input error detection logic to identify simultaneous edge
transition in QEP signals.
ADC: The ADC block is a 12-bit converter. The ADC has up to 16 single-ended
channels pinned out, depending on the device. The ADC also contains two
sample-and-hold units for simultaneous sampling.
Comparator and Each comparator block consists of one analog comparator along with an
Digital Filter internal 6-bit reference for supplying one input of the comparator. The
Subsystems: comparator output signal filtering is achieved using the Digital Filter
present on each input line and qualifies the output of the COMP/DAC
subsystem. The filtered or unfiltered output of the COMP/DAC subsystem
can be configured to be an input to the Digital Compare submodule of the
ePWM peripheral. There is also a configurable option to bring the output of
the COMP/DAC subsystem onto the GPIO’s.
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2.3.21 Serial Port Peripherals
The devices support the following serial communication peripherals:
SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream
of programmed length (one to sixteen bits) to be shifted into and out of the device
at a programmable bit-transfer rate. Normally, the SPI is used for communications
between the MCU and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multi-device communications are
supported by the master/slave operation of the SPI. The SPI contains a 4-level
receive and transmit FIFO for reducing interrupt servicing overhead.
SCI: The serial communications interface is a two-wire asynchronous serial port,
commonly known as UART. The SCI contains a 4-level receive and transmit FIFO
for reducing interrupt servicing overhead.
I2C: The inter-integrated circuit (I2C) module provides an interface between an MCU
and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)
specification version 2.1 and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit and receive up to 8-bit
data to and from the MCU through the I2C module. The I2C contains a 4-level
receive and transmit FIFO for reducing interrupt servicing overhead.
eCAN: The eCAN is the enhanced version of the CAN peripheral. The eCAN supports 32
mailboxes, time stamping of messages, and is CAN 2.0B-compliant.
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2.4 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 2-10.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 2-11.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 2-12.
Peripheral Frame 3: These are peripherals that are mapped to CLA in addition to their respective
Peripheral Frame. See Table 2-13.
Table 2-10. Peripheral Frame 0 Registers(1)
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED(2)
Device Emulation Registers 0x00 0880 – 0x00 0984 261 Yes
System Power Control Registers 0x00 0985 – 0x00 0987 3 Yes
FLASH Registers(3) 0x00 0A80 – 0x00 0ADF 96 Yes
ADC registers (0 wait read only) 0x00 0B00 – 0x00 0B0F 16 No
DCSM Zone 1 Registers 0x00 0B80 – 0x00 0BBF 64 Yes
DCSM Zone 2 Registers 0x00 0BC0 – 0x00 0BEF 48 Yes
CPU-TIMER0, CPU-TIMER1, CPU-TIMER2 0x00 0C00 – 0x00 0C3F 64 No
Registers
PIE Registers 0x00 0CE0 – 0x00 0CFF 32 No
PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 No
CLA Registers 0x00 1400 – 0x00 147F 128 Yes
CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 – 0x00 14FF 128 NA
CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 – 0x00 157F 128 NA
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Dual Code Security Module (DCSM).
Table 2-11. Peripheral Frame 1 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
eCAN-A Registers 0x00 6000 – 0x00 61FF 512 (1)
eCAP1 Registers 0x00 6A00 – 0x00 6A1F 32 No
eQEP1 Registers 0x00 6B00 – 0x00 6B3F 64 (1)
GPIO Registers 0x00 6F80 – 0x00 6FFF 128 (1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
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Table 2-12. Peripheral Frame 2 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
System Control Registers 0x00 7010 – 0x00 702F 32 Yes
SPI-A Registers 0x00 7040 – 0x00 704F 16 No
SCI-A Registers 0x00 7050 – 0x00 705F 16 No
NMI Watchdog Interrupt Registers 0x00 7060 – 0x00 706F 16 Yes
External Interrupt Registers 0x00 7070 – 0x00 707F 16 Yes
ADC Registers 0x00 7100 – 0x00 717F 128 (1)
I2C-A Registers 0x00 7900 – 0x00 793F 64 (1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 2-13. Peripheral Frame 3 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
ADC registers 0x00 0B00 – 0x00 0B0F 16 No
(0 wait read only)
DAC Control Registers 0x00 6400 – 0x00 640F 16 Yes
DAC, PGA, Comparator, and Filter Enable 0x00 6410 – 0x00 641F 16 Yes
Registers
SWITCH Registers 0x00 6420 – 0x00 642F 16 Yes
Digital Filter and Comparator Control Registers 0x00 6430 – 0x00 647F 80 Yes
LOCK Registers 0x00 64F0 – 0x00 64FF 16 Yes
ePWM1 registers 0x00 6800 – 0x00 683F 64 (1)
ePWM2 registers 0x00 6840 – 0x00 687F 64 (1)
ePWM3 registers 0x00 6880 – 0x00 68BF 64 (1)
ePWM4 registers 0x00 68C0 – 0x00 68FF 64 (1)
ePWM5 registers 0x00 6900 – 0x00 693F 64 (1)
ePWM6 registers 0x00 6940 – 0x00 697F 64 (1)
ePWM7 registers 0x00 6980 – 0x00 69BF 64 (1)
eCAP1 Registers 0x00 6A00 – 0x00 6A1F 32 No
eQEP1 Registers 0x00 6B00 – 0x00 6B3F 64 (1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
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2.5 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 2-14.
Table 2-14. Device Emulation Registers
NAME ADDRESS SIZE (x16) DESCRIPTION EALLOW RANGE PROTECTED
DEVICECNF 0x0880 – 2 Device Configuration Register Yes 0x0881
PARTID 0x0882 1 PARTID Register TMS320F28055 0x0105
TMS320F28054 0x0104
TMS320F28053 0x0103
No
TMS320F28052 0x0102
TMS320F28051 0x0101
TMS320F28050 0x0100
REVID 0x0883 1 Revision ID 0x0000 - Silicon Rev. 0 - TMX No Register
DC1 0x0886 – 2 Device Capability Register 1.
0x0887 The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this
register, the module is not present. See Table 2-15.
DC2 0x0888 – 2 Device Capability Register 2.
0x0889 The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this
register, the module is not present. See Table 2-16.
DC3 0x088A – 2 Device Capability Register 3.
0x088B The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this
register, the module is not present. See Table 2-17.
Table 2-15. Device Capability Register 1 (DC1) Field Descriptions(1)
BIT FIELD TYPE DESCRIPTION
31–30 RSVD R = 0 Reserved
29–22 PARTNO R These 8 bits set the PARTNO field value in the PARTID register for the device. They
are readable in the PARTID[7:0] register bits.
21–14 RSVD R = 0 Reserved
13 CLA R CLA is present when this bit is set.
12–7 RSVD R = 0 Reserved
6 L3 R L3 is present when this bit is set.
5 L2 R L2 is present when this bit is set.
4 L1 R L1 is present when this bit is set.
3 L0 R L0 is present when this bit is set.
2 RSVD R = 0 Reserved
1–0 RSVD R = 0 Reserved
(1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same
value that is read back from the reserved bits. These bits are reserved for future enhancements.
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Table 2-16. Device Capability Register 2 (DC2) Field Descriptions(1)
BIT FIELD TYPE DESCRIPTION
31–28 RSVD R = 0 Reserved
27 eCAN-A R eCAN-A is present when this bit is set.
26–17 RSVD R = 0 Reserved
16 EQEP-1 R eQEP-1 is present when this bit is set.
15–13 RSVD R = 0 Reserved
12 ECAP-1 R eCAP-1 is present when this bit is set.
11–9 RSVD R = 0 Reserved
8 I2C-A R I2C-A is present when this bit is set.
7–5 RSVD R = 0 Reserved
4 SPI-A R SPI-A is present when this bit is set.
3 RSVD R = 0 Reserved
2 SCI-C R SCI-C is present when this bit is set.
1 SCI-B R SCI-B is present when this bit is set.
0 SCI-A R SCI-A is present when this bit is set.
(1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same
value that is read back from the reserved bits. These bits are reserved for future enhancements.
Table 2-17. Device Capability Register 3 (DC3) Field Descriptions(1)
BIT FIELD TYPE DESCRIPTION
31–20 RSVD R = 0 Reserved
19 CTRIPFIL7 R CTRIPFIL7(B7) is present when this bit is set.
18 CTRIPFIL6 R CTRIPFIL6(B6) is present when this bit is set.
17 CTRIPFIL5 R CTRIPFIL5(B4) is present when this bit is set.
16 CTRIPFIL4 R CTRIPFIL4(A6) is present when this bit is set.
15 CTRIPFIL3 R CTRIPFIL3(B1) is present when this bit is set.
14 CTRIPFIL2 R CTRIPFIL2(A3) is present when this bit is set.
13 CTRIPFIL1 R CTRIPFIL1(A1) is present when this bit is set.
12–8 RSVD R = 0 Reserved
7 RSVD R = 0 Reserved
6 ePWM7 R ePWM7 is present when this bit is set.
5 ePWM6 R ePWM6 is present when this bit is set.
4 ePWM5 R ePWM5 is present when this bit is set.
3 ePWM4 R ePWM4 is present when this bit is set.
2 ePWM3 R ePWM3 is present when this bit is set.
1 ePWM2 R ePWM2 is present when this bit is set.
0 ePWM1 R ePWM1 is present when this bit is set.
(1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same
value that is read back from the reserved bits. These bits are reserved for future enhancements.
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2.6 VREG, BOR, POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This feature eliminates the
cost and space of a second external regulator on an application board. Additionally, internal power-on
reset (POR) and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and
run mode.
2.6.1 On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors
are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
2.6.1.1 Using the On-chip VREG
To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended
operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by
the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum)
capacitance for proper regulation of the VREG. These capacitors should be located as close as possible
to the VDD pins.
2.6.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied
high.
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I/O Pin
In
Out
DIR (0 = Input, 1 = Output)
(Force Hi-Z When High)
SYSRS
C28x
Core
Sync RS
XRS
PLL
+
Clocking
Logic
MCLKRS
VREGHALT
Deglitch
Filter
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
POR/BOR
Generating
Module
XRS
Pin
SYSCLKOUT
WDRST
(A)
JTAG
TCK
Detect
Logic
PBRS
(B)
Internal
Weak PU
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2.6.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
The purpose of the POR is to create a clean reset throughout the device during the entire power-up
procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or
VDDIO rail during device operation. The POR function is present on both VDD and VDDIO rails at all times.
After initial device power-up, the BOR function is present on VDDIO at all times, and on VDD when the
internal VREG is enabled (VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the
voltages is below their respective trip point. Additionally, when the internal voltage regulator is enabled, an
over-voltage protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 4.3 for
the various trip points as well as the delay time for the device to release the XRS pin after the undervoltage
or over-voltage condition is removed. Figure 2-5 shows the VREG, POR, and BOR. To disable
both the VDD and VDDIO BOR functions, a bit is provided in the BORCFG register. See the System Control
and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number
SPRUHE5) for details.
A. WDRST is the reset signal from the CPU-watchdog.
B. PBRS is the reset signal from the POR/BOR module.
Figure 2-5. VREG + POR + BOR + Reset Signal Connectivity
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2.7 System Control
This section describes the oscillator and clocking mechanisms, the watchdog function and the low power
modes.
Table 2-18. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME ADDRESS SIZE (x16) DESCRIPTION(1)
BORCFG 0x00 0985 1 BOR Configuration Register
XCLK 0x00 7010 1 XCLKOUT Control
PLLSTS 0x00 7011 1 PLL Status Register
CLKCTL 0x00 7012 1 Clock Control Register
PLLLOCKPRD 0x00 7013 1 PLL Lock Period
INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register
INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register
LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register
PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0
PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1
LPMCR0 0x00 701E 1 Low Power Mode Control Register 0
PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3
PLLCR 0x00 7021 1 PLL Control Register
SCSR 0x00 7022 1 System Control and Status Register
WDCNTR 0x00 7023 1 Watchdog Counter Register
PCLKCR4 0x00 7024 1 Peripheral Clock Control Register 4
WDKEY 0x00 7025 1 Watchdog Reset Key Register
WDCR 0x00 7029 1 Watchdog Control Register
(1) All registers in this table are EALLOW protected.
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PCLKCR0/1/3/4
(System Ctrl Regs)
LOSPCP
(System Ctrl Regs)
I/O
Clock Enables LSPCLK
Peripheral
Registers
SPI-A, SCI-A, SCI-B, SCI-C
SYSCLKOUT
Clock Enables
Peripheral
Registers
I/O eCAP1, eQEP1
Clock Enables
Peripheral
Registers
ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6, ePWM7
I/O
Clock Enables
Peripheral
Registers
I/O I2C-A
Clock Enables
ADC
9 Ch 12-Bit ADC Registers
Clock Enables
AFE
AFE Registers
7 Ch
GPIO
Mux
Analog
C28x Core CLKIN
Peripheral
I/O eCAN-A Registers
/2
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Figure 2-6 shows the various clock domains that are discussed. Figure 2-7 shows the various clock
sources (both internal and external) that can provide a clock for device operation.
A. CLKIN is the clock into the CPU. CLKIN is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same
frequency as SYSCLKOUT).
Figure 2-6. Clock and Reset Domains
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INTOSC1TRIM Reg
(A)
Internal
OSC 1
(10 MHz)
OSCE
CLKCTL[INTOSC1OFF]
WAKEOSC
CLKCTL[INTOSC1HALT]
INTOSC2TRIM Reg
(A)
Internal
OSC 2
(10 MHz)
OSCE
CLKCTL[INTOSC2OFF]
CLKCTL[INTOSC2HALT]
1 = Turn OSC Off
1 = Ignore HALT
1 = Turn OSC Off
1 = Ignore HALT
XCLK[XCLKINSEL]
0 = GPIO38
1 = GPIO19
GPIO19
or
GPIO38
CLKCTL[XCLKINOFF]
0
0
1
(Crystal)
OSC
XCLKIN
X1
X2
CLKCTL[XTALOSCOFF]
0 = OSC on (default on reset)
1 = Turn OSC off
0
1
0
1
OSC1CLK
OSCCLKSRC1 WDCLK
OSC2CLK
0
1
CLKCTL[WDCLKSRCSEL]
(OSC1CLK on XRS reset)
CLKCTL[OSCCLKSRCSEL]
CLKCTL[TRM2CLKPRESCALE]
CLKCTL[TMR2CLKSRCSEL]
OSCCLKSRC2
11
Prescale
/1, /2, /4,
/8, /16
00
01, 10, 11
CPUTMR2CLK
SYNC
Edge
Detect
10
01
CLKCTL[OSCCLKSRC2SEL]
SYSCLKOUT
WAKEOSC
(Oscillators enabled when this signal is high)
EXTCLK
XTAL
XCLKIN
(OSC1CLK on XRS reset)
OSCCLK PLL
Missing-Clock-Detect Circuit
(B)
CPU-Watchdog
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A. Register loaded from TI OTP-based calibration function.
B. See Section 2.7.4 for details on missing clock detection.
Figure 2-7. Clock Tree
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External Clock Signal
(Toggling 0−VDDIO)
XCLKIN/GPIO19/38 X2
NC
X1
X1 X2
Crystal
XCLKIN/GPIO19/38
Turn off
XCLKIN path
in CLKCTL
register
Rd
CL1 CL2
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2.7.1 Internal Zero-Pin Oscillators
The F2805x devices contain two independent internal zero-pin oscillators. By default both oscillators are
turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings,
unused oscillators may be powered down by the user. The center frequency of these oscillators is
determined by their respective oscillator trim registers, written to in the calibration routine as part of the
boot ROM execution. See Section 5.2.1 for more information on these oscillators.
2.7.2 Crystal Oscillator Option
The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in
Table 2-19. Furthermore, ESR range = 30 to 150 Ω.
Table 2-19. Typical Specifications for External Quartz Crystal(1)
FREQUENCY (MHz) Rd (Ω) CL1 (pF) CL2 (pF)
5 2200 18 18
10 470 15 15
15 0 15 15
20 0 12 12
(1) Cshunt should be less than or equal to 5 pF.
Figure 2-8. Using the On-chip Crystal Oscillator
NOTE
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the
IC and crystal. The value is usually approximately twice the value of the crystal's load
capacitance.
2. The load capacitance of the crystal is described in the crystal specifications of the
manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the
operation of their device with the MCU chip. The resonator/crystal vendor has the
equipment and expertise to tune the tank circuit. The vendor can also advise the
customer regarding the proper tank component values that will produce proper start up
and stability over the entire operating range.
Figure 2-9. Using a 3.3-V External Oscillator
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2.7.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. The watchdog module can be re-enabled (if need be) after the PLL module has
stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that
the output frequency of the PLL (VCOCLK) is at least 50 MHz.
Table 2-20. PLL Settings
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(1) (2)
PLLSTS[DIVSEL] = 0 or 1(3) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3
0000 (PLL bypass) OSCCLK/4 (Default)(1) OSCCLK/2 OSCCLK
0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1
0010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 (OSCCLK * 2)/1
0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 (OSCCLK * 3)/1
0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 (OSCCLK * 4)/1
0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 (OSCCLK * 5)/1
0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 (OSCCLK * 6)/1
0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 (OSCCLK * 7)/1
1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 (OSCCLK * 8)/1
1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 (OSCCLK * 9)/1
1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 (OSCCLK * 10)/1
1011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 (OSCCLK * 11)/1
1100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 (OSCCLK * 12)/1
(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(2) This register is EALLOW protected. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference
Manual (literature number SPRUHE5) for more information.
(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes the PLLSTS[DIVSEL] configuration to /1.) PLLSTS[DIVSEL]
must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
Table 2-21. CLKIN Divide Options
PLLSTS [DIVSEL] CLKIN DIVIDE
0 /4
1 /4
2 /2
3 /1
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The PLL-based clock module provides four modes of operation:
• INTOSC1 (Internal Zero-pin Oscillator 1): INTOSC1 is the on-chip internal oscillator 1. INTOSC1 can
provide the clock for the Watchdog block, core and CPU-Timer 2.
• INTOSC2 (Internal Zero-pin Oscillator 2): INTOSC2 is the on-chip internal oscillator 2. INTOSC2 can
provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can
be independently chosen for the Watchdog block, core and CPU-Timer 2.
• Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external
crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to
the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 3-1 for details.
• External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows the
on-chip (crystal) oscillator to be bypassed. The device clocks are generated from an external clock
source input on the XCLKIN pin. Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The
XCLKIN input can be selected as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The
CLKCTL[XCLKINOFF] bit disables this clock input (forced low). If the clock source is not used or the
respective pins are used as GPIOs, the user should disable at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that
clock source must be disabled (using the CLKCTL register) before switching clocks.
Table 2-22. Possible PLL Configuration Modes
PLL MODE REMARKS PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. The PLL block being disabled can be useful in reducing 0, 1 OSCCLK/4
PLL Off system noise and for low-power operation. The PLLCR register must first be set to 2 OSCCLK/2
0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is 3 OSCCLK/1
derived directly from the input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external 0, 1 OSCCLK/4 PLL Bypass reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or 2 OSCCLK/2 while the PLL locks to a new frequency after the PLLCR register has been 3 OSCCLK/1 modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the 0, 1 OSCCLK * n/4 PLL Enable PLLCR the device will switch to PLL Bypass mode until the PLL locks. 2 OSCCLK * n/2 3 OSCCLK * n/1
2.7.4 Loss of Input Clock (NMI Watchdog Function)
The 2805x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1 or
INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source,
in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limpmode
clock at its output. This limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1–5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired
immediately or the NMI watchdog counter can issue a reset when the counter overflows. In addition to this
action, the Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application
to detect the input clock failure and initiate necessary corrective action such as switching over to an
alternative clock source (if available) or initiate a shut-down procedure for the system.
If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a
preprogrammed time interval. Figure 2-10 shows the interrupt mechanisms involved.
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NMIFLG[NMINT]
1
0
Generate
Interrupt
Pulse
When
Input = 1
NMINT
Latch
Clear
Set Clear
NMIFLGCLR[NMINT]
XRS
0
NMICFG[CLOCKFAIL]
Latch
Clear
Clear Set
XRS
NMIFLG[CLOCKFAIL]
NMI Watchdog
SYSCLKOUT
SYSRS
NMIRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
NMIFLGCLR[CLOCKFAIL]
SYNC?
NMIFLGFRC[CLOCKFAIL]
SYSCLKOUT
See System
Control Section
CLOCKFAIL
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Figure 2-10. NMI-watchdog
2.7.5 CPU-Watchdog Module
The CPU-watchdog module on the 2805x device is similar to the one used on the 281x, 280x, and 283xx
devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this occurrence, the user must disable
the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register
that resets the watchdog counter. Figure 2-11 shows the various functional blocks within the watchdog
module.
Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPUwatchdog
reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog
counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).
NOTE
The CPU-watchdog is different from the NMI watchdog. The CPU-watchdog is the legacy
watchdog that is present in all 28x devices.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the MCU will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent the capacitor from getting fully charged. Such a circuit would also
help in detecting failure of the flash memory.
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/512
WDCLK
WDCR (WDPS[2:0])
WDCLK
WDCNTR(7:0)
WDKEY(7:0)
Good Key
1 0 1
WDCR (WDCHK[2:0])
Bad
WDCHK
Key
WDCR (WDDIS)
Clear Counter
SCSR (WDENINT)
Watchdog
Prescaler
Generate
Output Pulse
(512 OSCCLKs)
8-Bit
Watchdog
Counter
CLR
WDRST
WDINT
Watchdog
55 + AA
Key Detector
XRS
Core-reset
WDRST(A)
Internal
Pullup
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A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 2-11. CPU-watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM
block so that the signal can wake the device from STANDBY (if enabled). See Section 2.8, Low-power
Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.
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2.8 Low-power Modes Block
Table 2-23 summarizes the various modes.
Table 2-23. Low-power Modes
MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT(1)
IDLE 00 On On On XRS, CPU-watchdog interrupt, any enabled interrupt
STANDBY 01 On Off Off XRS, CPU-watchdog interrupt, GPIO (CPU-watchdog still running) Port A signal, debugger(2)
Off
(on-chip crystal oscillator and XRS, GPIO Port A signal, debugger(2), HALT(3) 1X PLL turned off, zero-pin oscillator Off Off CPU-watchdog and CPU-watchdog state
dependent on user code.)
(1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power
mode will not be exited and the device will go back into the indicated low power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:
IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the
processor. The LPM block performs no tasks during this mode as long as
the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signals will wake the device in the
GPIOLPMSEL register. The selected signals are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.
HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake
the device from HALT mode. The user selects the signal in the
GPIOLPMSEL register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included). They
will be in whatever state the code left them in when the IDLE instruction was executed. See
the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical
Reference Manual (literature number SPRUHE5) for more details.
2.9 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require
additional thermal enhancements. Ambient temperature (TA) varies with the end application and product
design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the
ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be
measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of
the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature
number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number
SPRA963) help to understand the thermal metrics and definitions.
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20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
41
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
80
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
VSSA
VSS
VDDIO
GPIO26/SCIRXDC
TEST2
GPIO9/EPWM5B/SCITXDB
GPIO30/CANRXA/SCIRXDB/EPWM7A
GPIO31/CANTXA/SCITXDB/EPWM7B
GPIO27/SCITXDC
PFCGND
ADCINB7 (op-amp)
ADCINB0
ADCINB6 (op-amp)
ADCINB5
M2GND
ADCINB4 (op-amp)
ADCINB3
ADCINA7
ADCINA6 (op-amp)
VREFLO
GPIO23/EQEP1I/SCIRXDB
GPIO11/EPWM6B/SCIRXDB
GPIO5/EPWM3B/SPISIMOA/ECAP1
GPIO4/EPWM3A
GPIO40/EPWM7A
GPIO10/EPWM6A/ADCSOCBO
GPIO3/EPWM2B/SPISOMIA/CTRIPM2OUT (COMP2OUT)
GPIO2/EPWM2A
GPIO1/EPWM1B/CTRIPM1OUT (COMP1OUT)
GPIO0/EPWM1A
VDDIO
VREGENZ
VSS
VDD
GPIO34/CTRIPM2OUT (COMP2OUT)/CTRIPPFCOUT (COMP3OUT)
GPIO15/TZ1/CTRIPM1OUT/SCIRXDB
GPIO13/TZ2/CTRIPM2OUT
GPIO14/TZ3/CTRIPPFCOUT/SCITXDB
GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT (COMP1OUT)
GPIO21/EQEP1B/EPWM7B/CTRIPM2OUT (COMP2OUT)
VDDA
GPIO22/EQEP1S/SCITXDB
XRS
GPIO32/SDAA/EPWMSYNCI/EQEP1S
GPIO33/SCLA/EPWMSYNCO/EQEP1I
GPIO24/ECAP1/EPWM7A
GPIO42/EPWM7B/SCITXDC/CTRIPM1OUT (COMP1OUT)
VDD
VSS
TRST
ADCBGOUT/ADCINA4
ADCINA5
ADCINA3 (op-amp)
ADCINA2
ADCINA1 (op-amp)
M1GND
ADCINB2
ADCINB1 (op-amp)
ADCINA0/VREFOUT
VREFHI
GPIO29/SCITXDA/SCLA/ /CTRIPPFCOUTTZ3
GPIO36/TMS
GPIO35/TDI
GPIO37/TDO
GPIO38/TCK/XCLKIN
GPIO39/SCIRXDC/CTRIPPFCOUT
GPIO19/XCLKIN/ /SCIRXDB/ECAP1SPISTEA
VDD
VSS
X1
X2
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO7/EPWM4B/SCIRXDA
GPIO16/SPISIMOA/EQEP1S/ /CTRIPM2OUTTZ2
GPIO12/ /CTRIPM1OUT/SCITXDATZ1
GPIO25
GPIO8/EPWM5A/ADCSOCAO
GPIO17/SPISOMIA/EQEP1I/ /CTRIPPFCOUTTZ3
GPIO18/SPICLKA/SCITXDB/XCLKOUT
GPIO28/SCIRXDA/SDAA/TZ2/CTRIPM2OUT
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3 Device Pins
3.1 Pin Assignments
Figure 3-1 shows the 80-pin PN Low-Profile Quad Flatpack (LQFP) pin assignments.
Figure 3-1. 2805x 80-Pin PN LQFP (Top View)
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3.2 Terminal Functions
Table 3-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate
functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs
are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled
or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins
are not enabled at reset. The pullups on other GPIO pins are enabled upon reset.
NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38
pins could glitch during power up. If this behavior is unacceptable in an application, 1.8 V could be
supplied externally. There is no power-sequencing requirement when using an external 1.8-V supply.
However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the
1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during
power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins,
ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
Table 3-1. Terminal Functions(1)
TERMINAL
PN I/O/Z DESCRIPTION NAME PIN NO.
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control
of the operations of the device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an
active high test pin and must be maintained low at all times during normal device operation.
TRST 9 I An external pull-down resistor is required on this pin. The value of this resistor should be
based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor
generally offers adequate protection. Since the value of the resistor is application-specific, TI
recommends that each target board be validated for proper operation of the debugger and the
application. (↓)
TCK See I See GPIO38. JTAG test clock with internal pullup. (↑) GPIO38
TMS See I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is GPIO36 clocked into the TAP controller on the rising edge of TCK.. (↑)
TDI See I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected GPIO35 register (instruction or data) on a rising edge of TCK. (↑)
TDO See O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register GPIO37 (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive)
FLASH
TEST2 39 I/O Test Pin. Reserved for TI. Must be left unconnected.
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PN I/O/Z DESCRIPTION NAME PIN NO.
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same
See frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT GPIO18 O/Z XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The
mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by
the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a
clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to
See GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a
XCLKIN GPIO19 I crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. and NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal
GPIO38 device operation may need to incorporate some hooks to disable this path during debug using
the JTAG connector. This action is to prevent contention with the TCK signal, which is active
during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to
clock the device.
On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator
X1 52 I must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit
13 in the CLKCTL register. If this pin is not used, this pin must be tied to GND. (I)
X2 51 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, X2 must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out). The device has a built-in power-on-reset (POR)
and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a
reset pulse. During a power-on or brown-out condition, this pin is driven low by the device.
See Section 4.3, Electrical Characteristics, for thresholds of the POR/BOR block. This pin is
also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS
XRS 8 I/O pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, TI recommends
that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin
for noise immunity reasons. Regardless of the source, a device reset causes the device to
terminate execution. The program counter points to the address contained at the location
0x3FFFC0. When reset is deactivated, execution begins at the location designated by the
program counter. The output buffer of this pin is an open-drain with an internal pullup. (I/OD)
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PN I/O/Z DESCRIPTION NAME PIN NO.
ADC, COMPARATOR, ANALOG I/O
ADCINA7 24 I ADC Group A, Channel 7 input
ADCINA6 23 I ADC Group A, Channel 6 input (op-amp)
ADCINA5 10 I ADC Group A, Channel 5 input
ADCBGOUT 11 O
ADCINA4 I ADC Group A, Channel 4 input
ADCINA3 12 I ADC Group A, Channel 3 input (op-amp)
ADCINA2 13 I ADC Group A, Channel 2 input
ADCINA1 14 I ADC Group A, Channel 1 input (op-amp)
ADCINA0 18 I ADC Group A, Channel 0 input
VREFOUT Voltage Reference out from buffered DAC
V ADC External Reference – used when in ADC external reference mode and used as VREFOUT REFHI 19 I reference
ADCINB7 31 I ADC Group B, Channel 7 input (op-amp)
ADCINB6 29 I ADC Group B, Channel 6 input (op-amp)
ADCINB5 28 I ADC Group B, Channel 5 input
ADCINB4 26 I ADC Group B, Channel 4 input (op-amp)
ADCINB3 25 I ADC Group B, Channel 3 input
ADCINB2 16 I ADC Group B, Channel 2 input
ADCINB1 17 I ADC Group B, Channel 1 input (op-amp)
ADCINB0 30 I ADC Group B, Channel 0 input
VREFLO 22 I ADC Low Reference (always tied to ground)
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PN I/O/Z DESCRIPTION NAME PIN NO.
CPU AND I/O POWER
VDDA 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
VSSA 21 Analog Ground Pin
VDD 6 CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie
VDD 54 with 1.2 μF (minimum) ceramic capacitor (10% tolerance) to ground when using internal
V VREG. Higher value capacitors may be used, but could impact supply-rail ramp-up time. DD 73
VDDIO 38
Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled
VDDIO 70
VSS 7
VSS 37
Digital Ground Pins
VSS 53
VSS 72
M1GND 15 Ground pin for M1 channel
M2GND 27 Ground pin for M2 channel
PFCGND 32 Ground pin for PFC channel
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ 71 I Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG
GPIO AND PERIPHERAL SIGNALS (1)
GPIO0 69 I/O/Z General-purpose input/output 0
EPWM1A O Enhanced PWM1 Output A
GPIO1 68 I/O/Z General-purpose input/output 1
EPWM1B O Enhanced PWM1 Output B
CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1)
GPIO2 67 I/O/Z General-purpose input/output 2
EPWM2A O Enhanced PWM2 Output A
GPIO3 66 I/O/Z General-purpose input/output 3
EPWM2B O Enhanced PWM2 Output B
SPISOMIA I/O SPI-A slave out, master in
CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2)
GPIO4 63 I/O/Z General-purpose input/output 4
EPWM3A O Enhanced PWM3 output A
GPIO5 62 I/O/Z General-purpose input/output 5
EPWM3B O Enhanced PWM3 output B
SPISIMOA I/O SPI-A slave in, master out
ECAP1 I/O Enhanced Capture input/output 1
(1) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.
For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the
GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the
System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for
details.
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PN I/O/Z DESCRIPTION NAME PIN NO.
GPIO6 50 I/O/Z General-purpose input/output 6
EPWM4A O Enhanced PWM4 output A
EPWMSYNCI I External ePWM sync pulse input
EPWMSYNCO O External ePWM sync pulse output
GPIO7 49 I/O/Z General-purpose input/output 7
EPWM4B O Enhanced PWM4 output B
SCIRXDA I SCI-A receive data
GPIO8 45 I/O/Z General-purpose input/output 8
EPWM5A O Enhanced PWM5 output A
ADCSOCAO O ADC start-of-conversion A
GPIO9 36 I/O/Z General-purpose input/output 9
EPWM5B O Enhanced PWM5 output B
SCITXDB O SCI-B transmit data
GPIO10 65 I/O/Z General-purpose input/output 10
EPWM6A O Enhanced PWM6 output A
ADCSOCBO O ADC start-of-conversion B
GPIO11 61 I/O/Z General-purpose input/output 11
EPWM6B O Enhanced PWM6 output B
SCIRXDB I SCI-B receive data
GPIO12 48 I/O/Z General-purpose input/output 12
TZ1 I Trip Zone input 1
CTRIPM1OUT O CTRIPM1 CTRIPxx output
SCITXDA O SCI-A transmit data
GPIO13 76 I/O/Z General-purpose input/output 13
TZ2 I Trip zone input 2
CTRIPM2OUT O CTRIPM2 CTRIPxx output
GPIO14 77 I/O/Z General-purpose input/output 14
TZ3 I Trip zone input 3
CTRIPPFCOUT O CTRIPPFC output
SCITXDB O SCI-B transmit data
GPIO15 75 I/O/Z General-purpose input/output 15
TZ1 I Trip zone input 1
CTRIPM1OUT O CTRIPM1 CTRIPxx output
SCIRXDB I SCI-B receive data
GPIO16 47 I/O/Z General-purpose input/output 16
SPISIMOA I/O SPI-A slave in, master out
EQEP1S I/O Enhanced QEP1 strobe
TZ2 I Trip Zone input 2
CTRIPM2OUT O CTRIPM2 CTRIPxx output
GPIO17 44 I/O/Z General-purpose input/output 17
SPISOMIA I/O SPI-A slave out, master in
EQEP1I I/O Enhanced QEP1 index
TZ3 I Trip zone input 3
CTRIPPFCOUT O CTRIPPFC output
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PN I/O/Z DESCRIPTION NAME PIN NO.
GPIO18 43 I/O/Z General-purpose input/output 18
SPICLKA I/O SPI-A clock input/output
SCITXDB O SCI-B transmit data
XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT is controlled
by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The
XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18
must also be set to XCLKOUT for this signal to propogate to the pin.
GPIO19 55 I/O/Z General-purpose input/output 19
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux
function of this pin. Care must be taken not to enable this path for clocking if this path is being
used for the other periperhal functions
SPISTEA I/O SPI-A slave transmit enable input/output
SCIRXDB I SCI-B receive data
ECAP1 I/O Enhanced Capture input/output 1
GPIO20 78 I/O/Z General-purpose input/output 20
EQEP1A I Enhanced QEP1 input A
EPWM7A O Enhanced PWM7 output A
CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1)
GPIO21 79 I/O/Z General-purpose input/output 21
EQEP1B I Enhanced QEP1 input B
EPWM7B O Enhanced PWM7 output B
CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2)
GPIO22 1 I/O/Z General-purpose input/output 22
EQEP1S I/O Enhanced QEP1 strobe
SCITXDB O SCI-B transmit data
GPIO23 80 I/O/Z General-purpose input/output 23
EQEP1I I/O Enhanced QEP1 index
SCIRXDB I SCI-B receive data
GPIO24 4 I/O/Z General-purpose input/output 24
ECAP1 I/O Enhanced Capture input/output 1
EPWM7A O Enhanced PWM7 output A
GPIO25 46 I/O/Z General-purpose input/output 25
GPIO26 40 I/O/Z General-purpose input/output 26
SCIRXDC I SCI-C receive data
GPIO27 33 I/O/Z General-purpose input/output 27
SCITXDC O SCI-C transmit data
GPIO28 42 I/O/Z General-purpose input/output 28
SCIRXDA I SCI-A receive data
SDAA I/OD I2C data open-drain bidirectional port
TZ2 I Trip zone input 2
CTRIPM2OUT O CTRIPM2 CTRIPxx output
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PN I/O/Z DESCRIPTION NAME PIN NO.
GPIO29 41 I/O/Z General-purpose input/output 29
SCITXDA O SCI-A transmit data
SCLA I/OD I2C clock open-drain bidirectional port
TZ3 I Trip zone input 3
CTRIPPFCOUT O CTRIPPFC output
GPIO30 35 I/O/Z General-purpose input/output 30
CANRXA I CAN receive
SCIRXDB I SCI-B receive data
EPWM7A O Enhanced PWM7 output A
GPIO31 34 I/O/Z General-purpose input/output 31
CANTXA O CAN transmit
SCITXDB O SCI-B transmit data
EPWM7B O Enhanced PWM7 output B
GPIO32 2 I/O/Z General-purpose input/output 32
SDAA I/OD I2C data open-drain bidirectional port
EPWMSYNCI I Enhanced PWM external sync pulse input
EQEP1S I/O Enhanced QEP1 strobe
GPIO33 3 I/O/Z General-Purpose Input/Output 33
SCLA I/OD I2C clock open-drain bidirectional port
EPWMSYNCO O Enhanced PWM external synch pulse output
EQEP1I I/O Enhanced QEP1 index
GPIO34 74 I/O/Z General-Purpose Input/Output 34
CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2)
CTRIPPFCOUT O CTRIPPFC output (COMP3OUT) (Direct output of Comparator 3)
GPIO35 59 I/O/Z General-Purpose Input/Output 35
TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK
GPIO36 60 I/O/Z General-Purpose Input/Output 36
TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the
TAP controller on the rising edge of TCK.
GPIO37 58 I/O/Z General-Purpose Input/Output 37
TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
GPIO38 57 I/O/Z General-Purpose Input/Output 38
TCK I JTAG test clock with internal pullup
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux
function of this pin. Care must be taken to not enable this path for clocking if this path is being
used for the other functions.
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PN I/O/Z DESCRIPTION NAME PIN NO.
GPIO39 56 I/O/Z General-Purpose Input/Output 39
SCIRXDC I SCI-C receive data
CTRIPPFCOUT O CTRIPPFC output
GPIO40 64 I/O/Z General-Purpose Input/Output 40
EPWM7A O Enhanced PWM7 output A
GPIO42 5 I/O/Z General-Purpose Input/Output 42
EPWM7B O Enhanced PWM7 output B
SCITXDC O SCI-C transmit data
CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1)
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4 Device Operating Conditions
4.1 Absolute Maximum Ratings(1) (2)
Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V
Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V
Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V
Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V
Output voltage range, VO –0.3 V to 4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO)(3) ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDDIO) ±20 mA
Junction temperature range, TJ
(4) –40°C to 150°C
Storage temperature range, Tstg
(4) –65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ± 2 mA.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).
4.2 Recommended Operating Conditions
MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO
(1) 2.97 3.3 3.63 V
Device supply voltage CPU, VDD (When internal 1.71 1.8 1.995 VREG is disabled and 1.8 V is supplied externally) V
Supply ground, VSS 0 V
Analog supply voltage, VDDA
(1) 2.97 3.3 3.63 V
Analog ground, VSSA 0 V
Device clock frequency (system clock) 2 60 MHz
High-level input voltage, VIH (3.3 V) 2 VDDIO + 0.3 V
Low-level input voltage, VIL (3.3 V) VSS – 0.3 0.8 V
High-level output source current, VOH = VOH(MIN) , IOH All GPIO pins –4 mA
Group 2(2) –8 mA
Low-level output sink current, VOL = VOL(MAX), IOL All GPIO pins 4 mA
Group 2(2) 8 mA
Junction temperature, TJ T version –40 105
°C
S version –40 125
(1) VDDIO and VDDA should be maintained within approximately 0.3 V of each other.
(2) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO28, GPIO29, GPIO30, GPIO31, GPIO36, GPIO37
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4.3 Electrical Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = IOH MAX 2.4
VOH High-level output voltage V
IOH = 50 μA VDDIO – 0.2
VOL Low-level output voltage IOL = IOL MAX 0.4 V
Pin with pullup All GPIO pins –80 –140 –205 enabled VDDIO = 3.3 V, VIN = 0 V I Input current XRS pin –230 –300 –375 IL (low level) μA Pin with pulldown VDDIO = 3.3 V, VIN = 0 V ±2 enabled
Pin with pullup VDDIO = 3.3 V, VIN = VDDIO ±2 Input current enabled IIH (high level) μA Pin with pulldown VDDIO = 3.3 V, VIN = VDDIO 28 50 80 enabled
I Output current, pullup or OZ pulldown disabled VO = VDDIO or 0 V ±2 μA
CI Input capacitance 2 pF
VDDIO BOR trip point Falling VDDIO 2.78 V
VDDIO BOR hysteresis 35 mV
Supervisor reset release delay Time after BOR/POR/OVR event is removed to XRS 400 800 μs time release
VREG VDD output Internal VREG on 1.9 V
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(VDD) go out of range.
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4.4 Current Consumption
Table 4-1. TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
VREG ENABLED VREG DISABLED
MODE TEST CONDITIONS IDDIO
(1) IDDA
(2) IDD IDDIO
(1) IDDA
(2)
TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX
The following peripheral clocks are
enabled:
• ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7
• eCAP1
• eQEP1
• eCAN-A
• CLA
• SCI-A, SCI-B, SCI-C
• SPI-A
Operational • ADC 100 mA(6) 40 mA 90 mA(6) 17 mA 40 mA
(Flash)
• I2C-A
• COMPA1, COMPA3,
COMPB1, COMPA6,
COMPB4, COMPB5,
COMPB7
• CPU-TIMER0,
CPU-TIMER1,
CPU-TIMER2
All PWM pins are toggled at 60 kHz.
All I/O pins are left unconnected.(4)(5)
Code is running out of flash with
2 wait-states.
XCLKOUT is turned off.
Flash is powered down.
IDLE XCLKOUT is turned off. 13 mA 15 μA 13 mA 300 μA 15 μA
All peripheral clocks are turned off.
Flash is powered down.
STANDBY 4 mA 15 μA 4 mA 300 μA 15 μA
Peripheral clocks are off.
Flash is powered down.
HALT Peripheral clocks are off. 30 μA 15 μA 15 μA 150 μA 15 μA
Input clock is disabled.(7)
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by
writing to the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
• Data is continuously transmitted out of SPI-A, SCI-A, SCI-B, SCI-C, eCAN-A, and I2C-A ports.
• The hardware multiplier is exercised.
• Watchdog is reset.
• ADC is performing continuous conversion.
• GPIO17 is toggled.
(5) CLA is continuously performing polynomial calculations.
(6) For F2805x devices that do not have CLA, subtract the IDD current number for CLA (see Table 4-2) from the IDD (VREG disabled)/IDDIO
(VREG enabled) current numbers shown in Table 4-1 for operational mode.
(7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
NOTE
The peripheral-I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time,
although such a configuration is not useful. If the clocks to all the peripherals are turned on
at the same time, the current drawn by the device will be more than the numbers specified in
the current consumption tables.
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4.4.1 Reducing Current Consumption
The 2805x devices incorporate a method to reduce the device current consumption. Since each peripheral
unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by
turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one
of the three low-power modes could be taken advantage of to reduce the current consumption even
further. Table 4-2 indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 4-2. Typical Current Consumption by Various
Peripherals (at 60 MHz)(1)
PERIPHERAL IDD CURRENT
MODULE(2) REDUCTION (mA)
ADC 2(3)
I2C 3
ePWM 2
eCAP 2
eQEP 2
SCI 2
SPI 2
COMP/DAC 1
PGA 2
CPU-TIMER 1
Internal zero-pin oscillator 0.5
CAN 2.5
CLA 20
(1) All peripheral clocks (except CPU Timer clock) are disabled upon
reset. Writing to or reading from peripheral registers is possible only
after the peripheral clocks are turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for one
ePWM module.
(3) This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the ADC
(IDDA) as well.
NOTE
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
NOTE
The baseline IDD current (current when the core is executing a dummy loop with no
peripherals enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the
current-drawn by the peripherals (enabled by that application) must be added to the baseline
IDD current.
Following are other methods to reduce power consumption further:
• The flash module may be powered down if code is run off SARAM. This method results in a current
reduction of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
• Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
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Operational Power vs Frequency
200
250
300
350
400
450
500
0 10 20 30 40 50 60 70
SYSCLKOUT (MHz)
Operational Power (mW)
Operational Current vs Frequency
0
20
40
60
80
100
120
140
0 10 20 30 40 50 60 70
SYSCLKOUT (MHz)
Operational Current (mA)
IDDIO IDDA
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4.4.2 Current Consumption Graphs (VREG Enabled)
Figure 4-1. Typical Operational Current Versus Frequency (F2805x)
Figure 4-2. Typical Operational Power Versus Frequency (F2805x)
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Typical CLA operational current vs SYSCLKOUT
0
5
10
15
20
25
10 15 20 25 30 35 40 45 50 55 60
SYSCLKOUT (MHz)
CLA operational IDDIO current (mA)
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Figure 4-3. Typical CLA Operational Current Versus SYSCLKOUT
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4.5 Flash Timing
Table 4-3. Flash/OTP Endurance for T Temperature Material(1)
ERASE/PROGRAM TEMPERATURE MIN TYP MAX UNIT
Nf Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 4-4. Flash/OTP Endurance for S Temperature Material(1)
ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE
Nf Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 4-5. Flash Parameters at 60-MHz SYSCLKOUT
PARAMETER TEST MIN TYP MAX UNIT CONDITIONS
Program Time 16-Bit Word 50 μs
8K Sector 250 ms
4K Sector 125 ms
Erase Time(1) 8K Sector 2 s
4K Sector 2 s
IDDP
(2) VDD current consumption during Erase/Program cycle VREG disabled 80 mA
IDDIOP
(2) VDDIO current consumption during Erase/Program cycle 60
IDDIOP
(2) VDDIO current consumption during Erase/Program cycle VREG enabled 120 mA
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off.
Table 4-6. Flash/OTP Access Timing
PARAMETER MIN MAX UNIT
ta(fp) Paged Flash access time 40 ns
ta(fr) Random Flash access time 40 ns
ta(OTP) OTP access time 60 ns
Table 4-7. Flash Data Retention Duration
PARAMETER TEST CONDITIONS MIN MAX UNIT
tretention Data retention duration TJ = 55°C 15 years
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OTP Wait State 1 round up to the next highest integer, or 1, whichever is larger
ú ú
û
ù
ê ê
ë
é
-
÷ ÷
ø
ö
ç ç
è
æ
=
t
t
c(SCO)
a(OTP)
FlashRandom Wait State 1 round up to the next highest integer, or 1, whichever is larger
ú ú
û
ù
ê ê
ë
é
-
÷ ÷
ø
ö
ç ç
è
æ
= ×
t
t
c(SCO)
a(f r)
FlashPage Wait State 1 round up to the next highest integer
( )
( )
ú ú
û
ù
ê ê
ë
é
-
÷ ÷
ø
ö
ç ç
è
æ
= ·
t
t
c SCO
a f p
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Table 4-8. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT SYSCLKOUT PAGE RANDOM OTP
(MHz) (ns) WAIT-STATE(1) WAIT-STATE(1) WAIT-STATE
60 16.67 2 2 3
55 18.18 2 2 3
50 20 1 1 2
45 22.22 1 1 2
40 25 1 1 2
35 28.57 1 1 2
30 33.33 1 1 1
(1) Page and random wait-state must be ≥ 1.
The equations to compute the Flash page wait-state and random wait-state in Table 4-8 are as follows:
The equation to compute the OTP wait-state in Table 4-8 is as follows:
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tw(RSL1)
th(boot-mode)
(C)
V V
(3.3 V)
DDIO, DDA
INTOSC1
X1/X2
XRS
(D)
Boot-Mode
Pins
V (1.8 V) DD
XCLKOUT
I/O Pins
User-code dependent
User-code dependent
Boot-ROM execution starts
Peripheral/GPIO function
Based on boot code
GPIO pins as input
GPIO pins as input (state depends on internal PU/PD)
(E)
tOSCST
User-code dependent
Address/Data/
Control
(Internal)
Address/data valid, internal boot-ROM code execution phase
td(EX) User-code execution phase
tINTOSCST
(A)
(B)
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5 Power, Reset, Clocking, and Interrupts
5.1 Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset
or to prevent the I/Os from glitching during power up or power down (GPIO19, GPIO34–38 do not have
glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital
pin (for analog pins, this value is 0.7 V above VDDA) prior to powering up the device. Voltages applied to
pins on an unpowered device can bias internal p-n junctions in unintended ways and produce
unpredictable results.
A. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before SYSCLKOUT appears at XCLKOUT. XCLKOUT = OSCCLK/16
during this phase.
B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that
XCLKOUT will not be visible at the pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.
E. The internal pullup or pulldown will take effect when BOR is driven high.
Figure 5-1. Power-on Reset
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th(boot-mode)
(A)
tw(RSL2)
INTOSC1
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input Peripheral/GPIO Function
td(EX)
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Table 5-1. Reset (XRS) Timing Requirements
MIN MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1000tc(SCO) cycles
tw(RSL2) Pulse duration, XRS low on warm reset 32tc(OSCCLK) cycles
Table 5-2. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(RSL1) Pulse duration, XRS driven by device 600 μs
tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles
td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles
tINTOSCST Start up time, internal zero-pin oscillator 3 μs
tOSCST
(1) On-chip crystal-oscillator start-up time 1 10 ms
(1) Dependent on crystal/resonator and board design.
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 5-2. Warm Reset
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OSCCLK
SYSCLKOUT
Write to PLLCR
OSCCLK * 2
(Current CPU
Frequency)
OSCCLK/2
(CPU frequency while PLL is stabilizing
with the desired frequency. This period
(PLL lock-up time t ) is 1 ms long.) p
OSCCLK * 4
(Changed CPU frequency)
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Figure 5-3 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
Figure 5-3. Example of Effect of Writing Into PLLCR Register
5.2 Clocking
5.2.1 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2805x MCUs. Table 5-3 lists the cycle times of various clocks.
Table 5-3. 2805x Clock Table and Nomenclature (60-MHz Devices)
MIN NOM MAX UNIT
tc(SCO), Cycle time 16.67 500 ns
SYSCLKOUT
Frequency 2 60 MHz
tc(LCO), Cycle time 16.67 66.67(2) ns
LSPCLK(1)
Frequency 15(2) 60 MHz
tc(ADCCLK), Cycle time 16.67 ns
ADC clock
Frequency 60 MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This value is the default reset value if SYSCLKOUT = 60 MHz.
Table 5-4. Device Clocking Requirements/Characteristics
MIN NOM MAX UNIT
On-chip oscillator (X1/X2 pins) tc(OSC), Cycle time 50 200 ns
(Crystal/Resonator) Frequency 5 20 MHz
External oscillator/clock source tc(CI), Cycle time (C8) 33.3 200 ns
(XCLKIN pin) — PLL Enabled Frequency 5 30 MHz
External oscillator/clock source tc(CI), Cycle time (C8) 33.33 250 ns
(XCLKIN pin) — PLL Disabled Frequency 4 30 MHz
Limp mode SYSCLKOUT Frequency range 1 to 5 MHz (with /2 enabled)
tc(XCO), Cycle time (C1) 66.67 2000 ns
XCLKOUT
Frequency 0.5 15 MHz
PLL lock time(1) tp 1 ms
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
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Zero-Pin Oscillator Frequency Movement With Temperature
9.6
9.7
9.8
9.9
10
10.1
10.2
10.3
10.4
10.5
10.6
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature (°C)
Output Frequency (MHz)
Typical
Max
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Table 5-5. Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
PARAMETER MIN TYP MAX UNIT
Internal zero-pin oscillator 1 (INTOSC1) at 30°C(1) (2) Frequency 10.000 MHz
Internal zero-pin oscillator 2 (INTOSC2) at 30°C(1) (2) Frequency 10.000 MHz
Step size (coarse trim) 55 kHz
Step size (fine trim) 14 kHz
Temperature drift(3) 3.03 4.85 kHz/°C
Voltage (VDD) drift(3) 175 Hz/mV
(1) In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, see the Oscillator Compensation Guide Application
Report (literature number SPRAB84). Refer to Figure 5-4 for TYP and MAX values.
(2) Frequency range ensured only when VREG is enabled, VREGENZ = VSS.
(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For
example:
• Increase in temperature will cause the output frequency to increase per the temperature coefficient.
• Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient.
Figure 5-4. Zero-Pin Oscillator Frequency Movement With Temperature
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C4
C3
XCLKOUT(B)
XCLKIN(A)
C5
C9
C10
C1
C8
C6
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5.2.2 Clock Requirements and Characteristics
Table 5-6. XCLKIN Timing Requirements - PLL Enabled
NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN 6 ns
C10 tr(CI) Rise time, XCLKIN 6 ns
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 %
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 %
Table 5-7. XCLKIN Timing Requirements - PLL Disabled
NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN Up to 20 MHz 6 ns
20 MHz to 30 MHz 2
C10 tr(CI) Rise time, XCLKIN Up to 20 MHz 6 ns
20 MHz to 30 MHz 2
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 %
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 %
The possible configuration modes are shown in Table 2-22.
Table 5-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
C3 tf(XCO) Fall time, XCLKOUT 5 ns
C4 tr(XCO) Rise time, XCLKOUT 5 ns
C5 tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns
C6 tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 5-5. Clock Timing
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CPU TIMER 2
CPU TIMER 0
Watchdog
Peripherals
(SPI, SCI, ePWM, I2C,
eCAP, ADC, eQEP, CLA, eCAN)
TINT0
XINT1
Interrupt Control
XINT1
XINT1CR(15:0)
Interrupt Control
XINT2
XINT2CR(15:0)
GPIO
MUX
WDINT
INT1
to
INT12
NMI
XINT2CTR(15:0)
XINT3CTR(15:0)
CPU TIMER 1
TINT2
Low Power Modes
LPMINT
WAKEINT
Sync
SYSCLKOUT
MUX
XINT2
XINT3
ADC
XINT2SOC
GPIOXINT1SEL(4:0)
GPIOXINT2SEL(4:0)
GPIOXINT3SEL(4:0)
Interrupt Control
XINT3
XINT3CR(15:0)
XINT3CTR(15:0)
NMI interrupt with watchdog function
(See the NMI Watchdog section.) NMIRS
System Control
(See the System
Control section.)
INT14
INT13
GPIO0.int
GPIO31.int
CLOCKFAIL
CPUTMR2CLK
C28
Core
MUX MUX
TINT1
PIE
Up to 96 Interrupts
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5.3 Interrupts
Figure 5-6 shows how the various interrupt sources are multiplexed.
Figure 5-6. External and PIE Interrupt Sources
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INT12
MUX
INT11
INT2
INT1
CPU
(Flag) (Enable)
INTx
INTx.8
PIEIERx[8:1] PIEIFRx[8:1]
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals
or
External
Interrupts
(Enable) (Flag)
IFR[12:1] IER[12:1]
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. Table 5-9 shows the interrupts used by 2805x
devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
Figure 5-7. Multiplexing of Interrupts Using the PIE Block
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Table 5-9. PIE MUXed Peripheral Interrupt Vector Table(1)
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1
(LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC)
0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40
INT2.y Reserved EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
– (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50
INT3.y Reserved EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT
– (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60
INT4.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAP1_INT
– – – – – – – (eCAP1)
0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70
INT5.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved EQEP1_INT
– – – – – – – (eQEP1)
0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80
INT6.y Reserved Reserved Reserved Reserved Reserved Reserved SPITXINTA SPIRXINTA
– – – – – – (SPI-A) (SPI-A)
0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90
INT7.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
– – – – – – – –
0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0
INT8.y Reserved Reserved SCITXINTC SCIRXINTC Reserved Reserved I2CINT2A I2CINT1A
– – (SCI-C) (SCI-C) – – (I2C-A) (I2C-A)
0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0
INT9.y Reserved Reserved ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA
– – (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A)
0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0
INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1
(ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC)
(ePWM16) (ePWM15) (ePWM14) (ePWM13) (ePWM12) (ePWM11) (ePWM10) (ePWM9)
0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0
INT11.y CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1
(CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA)
(ePWM16) (ePWM15) (ePWM14) (ePWM13) (ePWM12) (ePWM11) (ePWM10) (ePWM9)
0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0
INT12.y LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3
(CLA) (CLA) – – – – – Ext. Int. 3
0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be
used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
• No peripheral within the group is asserting interrupts.
• No peripheral interrupts are assigned to the group (for example, PIE group 7).
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Table 5-10. PIE Configuration and Control Registers
NAME ADDRESS SIZE (x16) DESCRIPTION(1)
PIECTRL 0x0CE0 1 PIE, Control Register
PIEACK 0x0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register
PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register
PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register
PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register
PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register
PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register
PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register
PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register
PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register
PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register
PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register
PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register
PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register
PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register
PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register
PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register
Reserved 0x0CFA – 6 Reserved
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
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XINT1, XINT2, XINT3
tw(INT)
Interrupt Vector
td(INT)
Address bus
(internal)
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5.3.1 External Interrupts
Table 5-11. External Interrupt Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
XINT1CR 0x00 7070 1 XINT1 configuration register
XINT2CR 0x00 7071 1 XINT2 configuration register
XINT3CR 0x00 7072 1 XINT3 configuration register
XINT1CTR 0x00 7078 1 XINT1 counter register
XINT2CTR 0x00 7079 1 XINT2 counter register
XINT3CTR 0x00 707A 1 XINT3 counter register
Each external interrupt can be enabled, disabled, or qualified using positive, negative, or both positive and
negative edge. For more information, see the System Control and Interrupts chapter of the
TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5).
5.3.1.1 External Interrupt Electrical Data/Timing
Table 5-12. External Interrupt Timing Requirements(1)
TEST CONDITIONS MIN MAX UNIT
tw(INT)
(2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles
With qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 6-45.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 5-13. External Interrupt Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles
(1) For an explanation of the input qualifier parameters, see Table 6-45.
Figure 5-8. External Interrupt Timing
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Transmission Line
4.0 pF 1.85 pF
Z0 = 50 W
(A)
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
42 W 3.5 nH
Device Pin
(B)
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6 Peripheral Information and Timings
6.1 Parameter Information
6.1.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their Letters and symbols and their
meanings: meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
f fall time X Unknown, changing, or don't care level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
6.1.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-1. 3.3-V Test Load Circuit
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6.2 Control Law Accelerator (CLA)
6.2.1 Control Law Accelerator Device-Specific Information
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Timecritical
control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA
enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks
frees up the main CPU to perform other system and communication functions concurently. The following is
a list of major features of the CLA.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program address bus and program data bus
• Data address bus, data read bus, and data write bus
– Independent eight-stage pipeline.
– 12-bit program counter (MPC)
– Four 32-bit result registers (MR0–MR3)
– Two 16-bit auxillary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load and store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the CLA program memory space.
– One task is serviced at a time through to completion. There is no nesting of tasks.
– Upon task completion, a task-specific interrupt is flagged within the PIE.
– When a task finishes, the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU via the IACK instruction
– Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example:
• Task1: ADCINT1 or EPWM1_INT
• Task2: ADCINT2 or EPWM2_INT
• Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT
• Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT
– Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– The CLA has direct access to the CLA Data ROM that stores the math tables required by the
routines in the CLA Math Library.
– The CLA has direct access to the ADC Result registers, comparator and DAC registers, eCAP,
eQEP, and ePWM registers.
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CLA_INT1 to CLA_INT8
MVECT1
MIFR
MIER
MIFRC
MVECT2
MIRUN
MPERINT1
to
MPERINT8
PIE
Main
28x
CPU
CLA
Program
Memory
MMEMCFG
MIOVF
MICLR
MCTL
MICLROVF
MPISRCSEL1
MVECT3
MVECT4
MVECT5
MVECT6
MVECT7
MVECT8
PU BUS
INT11
INT12
Peripheral Interrupts
ADCINT1 to ADCINT8
EPWM1_INT to EPWM7_INT
ECAP1_INT
EQEP1_INT
CPU Timer 0
Map to CLA or
CPU Space
Main CPU Read/Write Data Bus
CLA Program Address Bus
CLA Program Data Bus
Map to CLA or
CPU Space
CLA
Data
Memory
CLA
Data
ROM
Comparator
+ DAC
Registers
ePWM
Registers
eCAP
Registers
eQEP
Registers
ADC
Result
Registers
CLA
Shared
Message
RAMs
Main CPU Bus
MR0(32)
MPC(12)
MR1(32)
MR3(32)
MAR0(32)
MSTF(32)
MR2(32)
MAR1(32)
CLA Data Read Address Bus
CLA Data Write Data Bus
CLA Data Write Address Bus
CLA Data Read Data Bus
MEALLOW
Main CPU Read Data Bus
CLA Execution
Registers
CLA Control
Registers
SYSCLKOUT
CLAENCLK
SYSRS
LVF
LUF
IACK
CLA Data Bus
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Figure 6-2. CLA Block Diagram
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6.2.2 Control Law Accelerator Register Descriptions
Table 6-1. CLA Control Registers
REGISTER NAME CLA1 SIZE (x16) EALLOW DESCRIPTION(1)
ADDRESS PROTECTED
MVECT1 0x1400 1 Yes CLA Interrupt/Task 1 Start Address
MVECT2 0x1401 1 Yes CLA Interrupt/Task 2 Start Address
MVECT3 0x1402 1 Yes CLA Interrupt/Task 3 Start Address
MVECT4 0x1403 1 Yes CLA Interrupt/Task 4 Start Address
MVECT5 0x1404 1 Yes CLA Interrupt/Task 5 Start Address
MVECT6 0x1405 1 Yes CLA Interrupt/Task 6 Start Address
MVECT7 0x1406 1 Yes CLA Interrupt/Task 7 Start Address
MVECT8 0x1407 1 Yes CLA Interrupt/Task 8 Start Address
MCTL 0x1410 1 Yes CLA Control Register
MMEMCFG 0x1411 1 Yes CLA Memory Configure Register
MPISRCSEL1 0x1414 2 Yes Peripheral Interrupt Source Select Register 1
MIFR 0x1420 1 Yes Interrupt Flag Register
MIOVF 0x1421 1 Yes Interrupt Overflow Register
MIFRC 0x1422 1 Yes Interrupt Force Register
MICLR 0x1423 1 Yes Interrupt Clear Register
MICLROVF 0x1424 1 Yes Interrupt Overflow Clear Register
MIER 0x1425 1 Yes Interrupt Enable Register
MIRUN 0x1426 1 Yes Interrupt RUN Register
MPC(2) 0x1428 1 – CLA Program Counter
MAR0(2) 0x142A 1 – CLA Aux Register 0
MAR1(2) 0x142B 1 – CLA Aux Register 1
MSTF(2) 0x142E 2 – CLA STF Register
MR0(2) 0x1430 2 – CLA R0H Register
MR1(2) 0x1434 2 – CLA R1H Register
MR2(2) 0x1438 2 – CLA R2H Register
MR3(2) 0x143C 2 – CLA R3H Register
(1) All registers in this table are DCSM protected
(2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes
to this register.
Table 6-2. CLA Message RAM
ADDRESS RANGE SIZE (x16) DESCRIPTION
0x1480 – 0x14FF 128 CLA to CPU Message RAM
0x1500 – 0x157F 128 CPU to CLA Message RAM
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Digital Value = 0, when input £ 0 V
V V
Input Analog Voltage V
Digital Value 4096
REFHI REFLO
REFLO
-
-
= ´ when 0 V input VREFHI
< <
Digital Value = 4095, when input VREFHI
³
Digital Value = 0, when input £ 0 V
3.3
Input Analog Voltage V
Digital Value 4096 REFLO
-
= ´ when 0 V < input < 3.3 V
Digital Value = 4095, when input ³ 3.3 V
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6.3 Analog Block
6.3.1 Analog-to-Digital Converter (ADC)
6.3.1.1 Analog-to-Digital Converter Device-Specific Information
The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sampleand-
hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to
16 analog input channels. The converter can be configured to run with an internal bandgap reference to
create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to
create ratiometric-based conversions.
Contrary to previous ADC types, this ADC is not sequencer-based. The user can easily create a series of
conversions from a single trigger. However, the basic principle of operation is centered around the
configurations of individual conversions, called SOCs, or Start-Of-Conversions.
Functions of the ADC module include:
• 12-bit ADC core with built-in dual sample-and-hold (S/H)
• Simultaneous sampling or sequential sampling modes
• Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input
analog voltage is derived by:
– Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or
external reference modes.)
– External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA
when using either internal or external reference modes.)
• Runs at full system clock, no prescaling required
• Up to 16-channel, multiplexed inputs
• 16 SOCs, configurable for trigger, sample window, and channel
• 16 result registers (individually addressable) to store conversion values
• Multiple trigger sources
– S/W – software immediate start
– ePWM 1–7
– GPIO XINT2
– CPU Timer 0, CPU Timer 1, CPU Timer 2
– ADCINT1, ADCINT2
• 9 flexible PIE interrupts, can configure interrupt request after any conversion
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Table 6-3. ADC Configuration and Control Registers
REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED
ADCCTL1 0x7100 1 Yes Control 1 Register
ADCCTL2 0x7101 1 Yes Control 2 Register
ADCINTFLG 0x7104 1 No Interrupt Flag Register
ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register
ADCINTOVF 0x7106 1 No Interrupt Overflow Register
ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register
INTSEL1N2 0x7108 1 Yes Interrupt 1 and 2 Selection Register
INTSEL3N4 0x7109 1 Yes Interrupt 3 and 4 Selection Register
INTSEL5N6 0x710A 1 Yes Interrupt 5 and 6 Selection Register
INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register
INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection)
SOCPRICTL 0x7110 1 Yes SOC Priority Control Register
ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register
ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels)
ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels)
ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels)
ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels)
ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels)
ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels)
ADCSOC0CTL to 0x7120 – 1 Yes SOC0 Control Register to SOC15 Control Register
ADCSOC15CTL 0x712F
ADCREFTRIM 0x7140 1 Yes Reference Trim Register
ADCOFFTRIM 0x7141 1 Yes Offset Trim Register
COMPHYSTCTL 0x714C 1 Yes Comparator Hysteresis Control Register
ADCREV 0x714F 1 No Revision Register
Table 6-4. ADC Result Registers (Mapped to PF0)
REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED
ADCRESULT0 to 0xB00 – 1 No ADC Result 0 Register to ADC Result 15 Register
ADCRESULT15 0xB0F
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PF0 (CPU)
PF2 (CPU)
SYSCLKOUT
ADCENCLK
ADC
Channels
ADC
Core
12-Bit
0-Wait
Result
Registers
ADCINT 1
ADCINT 9
ADCTRIG 1
TINT 0
PIE
CPUTIMER 0
ADCTRIG 2
TINT 1
CPUTIMER 1
ADCTRIG 3
TINT 2
CPUTIMER 2
ADCTRIG 4
XINT 2SOC
XINT 2
ADCTRIG 5
SOCA 1
EPWM 1
ADCTRIG 6
SOCB 1
ADCTRIG 7
SOCA 2
EPWM 2
ADCTRIG 8
SOCB 2
ADCTRIG 9
SOCA 3
EPWM 3
ADCTRIG 10
SOCB 3
ADCTRIG 11
SOCA 4
EPWM 4
ADCTRIG 12
SOCB 4
ADCTRIG 13
SOCA 5
EPWM 5
ADCTRIG 14
SOCB 5
ADCTRIG 15
SOCA 6
EPWM 6
ADCTRIG 16
SOCB 6
ADCTRIG 17
SOCA 7
EPWM 7
ADCTRIG 18
SOCB 7
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Figure 6-3. ADC Connections
ADC Connections if the ADC is Not Used
TI recommends that the connections for the analog power pins be kept, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:
• VDDA – Connect to VDDIO
• VSSA – Connect to VSS
• VREFLO – Connect to VSS
• ADCINAn, ADCINBn, VREFHI – Connect to VSSA
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSSA).
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.
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6.3.1.2 Analog-to-Digital Converter Electrical Data/Timing
Table 6-5. ADC Electrical Characteristics
PARAMETER MIN TYP MAX UNIT
DC SPECIFICATIONS
Resolution 12 Bits
ADC clock 0.5 60 MHz
Sample Window (see Table 6-6) 28055, 28054, 28053, 10 63 ADC
28052 Clocks
28051, 28050 24 63
ACCURACY
INL (Integral nonlinearity)(1) –4 4 LSB
DNL (Differential nonlinearity), no missing codes –1 1.5 LSB
Offset error (2) Executing a single self- –20 0 20 LSB
recalibration(3)
Executing periodic self- –4 0 4
recalibration(4)
Overall gain error with internal reference –60 60 LSB
Overall gain error with external reference –40 40 LSB
Channel-to-channel offset variation –4 4 LSB
Channel-to-channel gain variation –4 4 LSB
ADC temperature coefficient with internal reference –50 ppm/°C
ADC temperature coefficient with external reference –20 ppm/°C
VREFLO –100 μA
VREFHI 100 μA
ANALOG INPUT
Analog input voltage with internal reference 0 3.3 V
Analog input voltage with external reference VREFLO VREFHI V
VREFLO input voltage VSSA 0.66 V
VREFHI input voltage(5) 2.64 VDDA V
with VREFLO = VSSA 1.98 VDDA
Input capacitance 5 pF
Input leakage current ±2 μA
(1) INL will degrade when the ADC input voltage goes above VDDA.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) For more details, see the TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050
Piccolo MCU Silicon Errata (literature number SPRZ362).
(4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed
as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration"
section in the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature
number SPRUHE5).
(5) VREFHI must not exceed VDDA when using either internal or external reference modes.
Table 6-6. ACQPS Values(1)
OVERLAP MODE NONOVERLAP MODE
Non-PGA {9, 10, 23, 36, 49, 62} {15, 16, 28, 29, 41, 42, 54, 55}
PGA {23, 36, 49, 62} {15, 16, 28, 29, 41, 42, 54, 55}
(1) ACQPS = 6 can be used for the first sample if it is thrown away.
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ADCSOCAO
ADCSOCBO
or
tw(ADCSOCL)
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
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Table 6-7. ADC Power Modes
ADC OPERATING MODE CONDITIONS IDDA UNITS
Mode A – Operating Mode ADC Clock Enabled 13 mA
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 1)
Mode B – Quick Wake Mode ADC Clock Enabled 4 mA
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 0)
Mode C – Comparator-Only Mode ADC Clock Enabled 1.5 mA
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
Mode D – Off Mode ADC Clock Enabled 0.075 mA
Bandgap On (ADCBGPWD = 0)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
6.3.1.2.1 External ADC Start-of-Conversion Electrical Data/Timing
Table 6-8. External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO ) cycles
Figure 6-4. ADCSOCAO or ADCSOCBO Timing
6.3.1.2.2 Internal Temperature Sensor
Table 6-9. Temperature Sensor Coefficient(1)
PARAMETER(2) MIN TYP MAX UNIT
TSLOPE Degrees C of temperature movement per measured ADC LSB change 0.18(3) (4) °C/LSB
of the temperature sensor
TOFFSET ADC output at 0°C of the temperature sensor 1750 LSB
(1) The accuracy of the temperature sensor for sensing absolute temperature (temperature in degrees) is not specified. The primary use of
the temperature sensor should be to compensate the internal oscillator for temperature drift (this operation is assured as per Table 5-5).
(2) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
(3) ADC temperature coeffieicient is accounted for in this specification
(4) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
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ac
Rs ADCIN
C
5 pF
p C
1.6 pF
h
Switch
Typical Values of the Input Circuit Components:
Switch Resistance (R ): 3.4 k on
W
Sampling Capacitor (C ): 1.6 pF h
Parasitic Capacitance (C ): 5 pF p
Source Resistance (R ): 50 s
W
28x DSP
Source
Signal
3.4 kW
Ron
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE
Request for ADC
Conversion
td(PWD)
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
6.3.1.2.3 ADC Power-Up Control Bit Timing
Table 6-10. ADC Power-Up Delays
PARAMETER(1) MIN MAX UNIT
td(PWD) Delay time for the ADC to be stable after power up 1 ms
(1) Timings maintain compatibility to the ADC module. The 2805x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
Figure 6-5. ADC Conversion Timing
Figure 6-6. ADC Input Impedance Model
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SOC0
ADCCLK
ADCRESULT 0
S/H Window Pulse to Core
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCINTFLG.ADCINTx
SOC1 SOC2
0 2 9 15 22 24 37
Result 0 Latched
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
Conversion 0
13 ADC Clocks
Minimum
7 ADCCLKs
6
ADCCLKs
Conversion 1
13 ADC Clocks
Minimum
7 ADCCLKs
2 ADCCLKs
1 ADCCLK
Analog Input
SOC1 Sample
Window
SOC0 Sample
Window
SOC2 Sample
Window
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
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6.3.1.2.4 ADC Sequential and Simultaneous Timings
A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away
sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the
converter.
Figure 6-7. Timing Example for Sequential Mode / Late Interrupt Pulse
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Conversion 0
13 ADC Clocks
Minimum
7 ADCCLKs
SOC0
ADCCLK
ADCRESULT 0
S/H Window Pulse to Core
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCINTFLG.ADCINTx
SOC1 SOC2
9 15 22 24 37
6
ADCCLKs
0 2
Result 0 Latched
Conversion 1
13 ADC Clocks
Minimum
7 ADCCLKs
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
2 ADCCLKs
Analog Input
SOC1 Sample
Window
SOC0 Sample
Window
SOC2 Sample
Window
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
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A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away
sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the
converter.
Figure 6-8. Timing Example for Sequential Mode / Early Interrupt Pulse
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Conversion 0 (A)
13 ADC Clocks
Minimum
7 ADCCLKs
SOC0 (A/B)
ADCCLK
ADCRESULT 0
S/H Window Pulse to Core
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCINTFLG .ADCINTx
SOC2 (A/B)
9 22 24 37
19
ADCCLKs
0 2
Result 0 (A) Latched
Conversion 0 (B)
13 ADC Clocks
Minimum
7 ADCCLKs
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
ADCRESULT 1 Result 0 (B) Latched
Conversion 1 (A)
13 ADC Clocks
ADCRESULT 2
50
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
1 ADCCLK
2 ADCCLKs
2 ADCCLKs
Analog Input B
SOC0 Sample
B Window
SOC2 Sample
B Window
Analog Input A
SOC0 Sample
A Window
SOC2 Sample
A Window
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TMS320F28052, TMS320F28051, TMS320F28050
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A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away
sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the
converter.
Figure 6-9. Timing Example for Simultaneous Mode / Late Interrupt Pulse
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ADCCLK
0 2 9
SOC0 Sample
B Window
Analog Input B
Analog Input A
SOC0 Sample
A Window
37 50
SOC2 Sample
B Window
SOC2 Sample
A Window
22 24
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B)
ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched
ADCRESULT 1 Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
Minimum
7 ADCCLKs
Conversion 0 (A)
13 ADC Clocks
2 ADCCLKs
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
ADCINTFLG.ADCINTx
19
ADCCLKs
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away
sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the
converter.
Figure 6-10. Timing Example for Simultaneous Mode / Early Interrupt Pulse
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6.02
(SINAD 1.76)
N
-
=
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
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6.3.1.2.5 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
Zero error is the difference between the ideal input voltage and the actual input voltage that just causes a
transition from an output code of zero to an output code of one.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
it is possible to get a measure of performance expressed as N, the effective number of
bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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TMS320F28052, TMS320F28051, TMS320F28050
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6.3.2 Analog Front End (AFE)
6.3.2.1 Analog Front End Device-Specific Information
The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to-
Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers
(PGAs), and up to four digital filters. Figure 6-11 and Figure 6-12 show the AFE.
The comparator output signal filtering is achieved using the Digital Filter present on selective input line
and qualifies the output of the COMP/DAC subsystem (see Figure 6-13). The filtered or unfiltered output
of the COMP/DAC subsystem can be configured to be an input to the Digital Compare submodule of the
ePWM peripheral. Note: The Analog inputs are brought in through the AFE subsystem rather than through
an AIO Mux, which is not present.
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ADC
VREFHI
V /A0 REFOUT
B7
PGA
G~ = 3, 6, 11
_
+
Cmp1
_
+
Cmp1
V
Buffered
DAC Output
COMPB7 REFOUT
DFSS
DAC5 6-bit
DAC6 6-bit
B7
VREFHI
A0
PFCGND
B0
A2
A4
B2
A1
PGA
G~ = 3, 6, 11
M1GND
_
+
Cmp2
DAC1 6-bit
COMPA1H
DFSS
_
+
Cmp3
COMPA1L
DFSS
ADCINSWITCH
A1
A3
PGA
G~ = 3, 6, 11
M1GND
Cmp4
COMPA3H
DFSS
_
+
Cmp5
COMPA3L
DFSS
A3
B1
PGA
G~ = 3, 6, 11
M1GND
_
+
Cmp6
COMPB1H
DFSS
_
+
Cmp7
COMPB1L
DFSS
B1
DAC2 6-bit
Temp Sensor
ADCCTL1.TEMPCONV
A5
A5
ADCCTL1.REFLOCONV
B5
A7
B3
B5
VREFLO
B0
A2
A4
B2
_
+
ADCINSWITCH
VREFLO
A7
B3
A6
GAIN AMP
G~ = 3
M2GND
B4
GAIN AMP
G~ = 3
M2GND
B6
GAIN AMP
G~ = 3
M2GND
A6
B4
B6
Legend
Cmp - Comparator
DFSS - Comparator Trip/Digital Filter Subsystem Block
GAIN AMP - Fixed Gain Amplifier
PGA - Programmable Gain Amplifier
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
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Figure 6-11. 28055, 28054, 28053, 28052, and 28051 Analog Front End (AFE)
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ADC
VREFHI
V /A0 REFOUT
_
+
Cmp1
V
Buffered
DAC Output
REFOUT
DAC6 6-bit
VREFHI
A0
B0
A2
A4
B2
A1
PGA
G~ = 3, 6, 11
M1GND
_
+
Cmp2
DAC1 6-bit
COMPA1H
DFSS
_
+
Cmp3
COMPA1L
DFSS
ADCINSWITCH
A1
A3
PGA
G~ = 3, 6, 11
M1GND
Cmp4
COMPA3H
DFSS
_
+
Cmp5
COMPA3L
DFSS
A3
B1
PGA
G~ = 3, 6, 11
M1GND
_
+
Cmp6
COMPB1H
DFSS
_
+
Cmp7
COMPB1L
DFSS
B1
DAC2 6-bit
Temp Sensor
ADCCTL1.TEMPCONV
A5
A5
ADCCTL1.REFLOCONV
B5
A7
B3
B5
VREFLO
B0
A2
A4
B2
_
+
ADCINSWITCH
VREFLO
A7
B3
A6
GAIN AMP
G~ = 3
M2GND
B4
GAIN AMP
G~ = 3
M2GND
A6
B4
B6
GAIN AMP
G~ = 3
M2GND
B6
B7
GAIN AMP
G~ = 3
PFCGND
B7
Legend
Cmp - Comparator
DFSS - Comparator Trip/Digital Filter Subsystem Block
GAIN AMP - Fixed Gain Amplifier
PGA - Programmable Gain Amplifier
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
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Figure 6-12. 28050 Analog Front End (AFE)
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ePWM 1-7
DCAH
DCAL
DCBH
DCBL
D
C
T
R
I
P
S
E
L
GPIO
MUX
CTRIPOUTPOL
SYSCLK
Digital Filter
CTRIPOUTBYP 1 0 CTRIPxxOUTEN
CTRIPOUTxxSTS
CTRIPOUTxxFLG
CTRIPOUTLATEN
0
1
CTRIPFILCTRL
REGISTER
CTRIPBYP
0
1
COMPxxPOL
COMPxxH
0
1
COMPxxPOL
COMPxxL
COMPxINPEN
ENABLES
CTRIPEN
(to all ePWM modules)
CTRIPxx0CTLREGISTER
0
1
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
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Figure 6-13. Comparator Trip/Digital Filter Subsystem
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6.3.2.2 Analog Front End Register Descriptions
Table 6-11. DAC Control Registers
REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED
DAC1CTL 0x6400 1 Yes DAC1 Control Register
DAC2CTL 0x6401 1 Yes DAC2 Control Register
DAC3CTL 0x6402 1 Yes DAC3 Control Register
DAC4CTL 0x6403 1 Yes DAC4 Control Register
DAC5CTL 0x6404 1 Yes DAC5 Control Register
VREFOUTCTL 0x6405 1 Yes VREFOUT DAC Control Register
Table 6-12. DAC, PGA, Comparator, and Filter Enable Registers
REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED
DACEN 0x6410 1 Yes DAC Enables Register
VREFOUTEN 0x6411 1 Yes VREFOUT Enable Register
PGAEN 0x6412 1 Yes Programmable Gain Amplifier Enable Register
COMPEN 0x6413 1 Yes Comparator Enable Register
AMPM1_GAIN 0x6414 1 Yes Motor Unit 1 PGA Gain Controls Register
AMPM2_GAIN 0x6415 1 Yes Motor Unit 2 PGA Gain Controls Register
AMP_PFC_GAIN 0x6416 1 Yes PFC PGA Gain Controls Register
Table 6-13. SWITCH Registers
REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED
ADCINSWITCH 0x6421 1 Yes ADC Input-Select Switch Control Register
Reserved 0x6422 – 7 Yes Reserved
0x6428
COMPHYSTCTL 0x6429 1 Yes Comparator Hysteresis Control Register
Table 6-14. Digital Filter and Comparator Control Registers
REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED
CTRIPA1ICTL 0x6430 1 Yes CTRIPA1 Filter Input and Function Control Register
CTRIPA1FILCTL 0x6431 1 Yes CTRIPA1 Filter Parameters Register
CTRIPA1FILCLKCTL 0x6432 1 Yes CTRIPA1 Filter Sample Clock Control Register
Reserved 0x6433 1 Yes Reserved
CTRIPA3ICTL 0x6434 1 Yes CTRIPA3 Filter Input and Function Control Register
CTRIPA3FILCTL 0x6435 1 Yes CTRIPA3 Filter Parameters Register
CTRIPA3FILCLKCTL 0x6436 1 Yes CTRIPA3 Filter Sample Clock Control Register
Reserved 0x6437 1 Yes Reserved
CTRIPB1ICTL 0x6438 1 Yes CTRIPB1 Filter Input and Function Control Register
CTRIPB1FILCTL 0x6439 1 Yes CTRIPB1 Filter Parameters Register
CTRIPB1FILCLKCTL 0x643A 1 Yes CTRIPB1 Filter Sample Clock Control Register
Reserved 0x643B 1 Yes Reserved
Reserved 0x643C 1 Yes Reserved
CTRIPM1OCTL 0x643D 1 Yes CTRIPM1 CTRIP Filter Output Control Register
CTRIPM1STS 0x643E 1 Yes CTRIPM1 CTRIPxx Outputs Status Register
CTRIPM1FLGCLR 0x643F 1 Yes CTRIPM1 CTRIPxx Flag Clear Register
Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 87
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Table 6-14. Digital Filter and Comparator Control Registers (continued)
REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED
Reserved 0x6440 – 16 Yes Reserved
0x644F
CTRIPA6ICTL 0x6450 1 Yes CTRIPA6 Filter Input and Function Control Register
CTRIPA6FILCTL 0x6451 1 Yes CTRIPA6 Filter Parameters Register
CTRIPA6FILCLKCTL 0x6452 1 Yes CTRIPA6 Filter Sample Clock Control Register
Reserved 0x6453 1 Yes Reserved
CTRIPB4ICTL 0x6454 1 Yes CTRIPB4 Filter Input and Function Control Register
CTRIPB4FILCTL 0x6455 1 Yes CTRIPB4 Filter Parameters Register
CTRIPB4FILCLKCTL 0x6456 1 Yes CTRIPB4 Filter Sample Clock Control Register
Reserved 0x6457 1 Yes Reserved
CTRIPB6ICTL 0x6458 1 Yes CTRIPB6 Filter Input and Function Control Register
CTRIPB6FILCTL 0x6459 1 Yes CTRIPB6 Filter Parameters Register
CTRIPB6FILCLKCTL 0x645A 1 Yes CTRIPB6 Filter Sample Clock Control Register
Reserved 0x645B 1 Yes Reserved
Reserved 0x645C 1 Yes Reserved
CTRIPM2OCTL 0x645D 1 Yes CTRIPM2 CTRIP Filter Output Control Register
CTRIPM2STS 0x645E 1 Yes CTRIPM2 CTRIPxx Outputs Status Register
CTRIPM2FLGCLR 0x645F 1 Yes CTRIPM2 CTRIPxx Flag Clear Register
Reserved 0x6460 – 16 Yes Reserved
0x646F
CTRIPB7ICTL 0x6470 1 Yes CTRIPB7 Filter Input and Function Control Register
CTRIPB7FILCTL 0x6471 1 Yes CTRIPB7 Filter Parameters Register
CTRIPB7FILCLKCTL 0x6472 1 Yes CTRIPB7 Filter Sample Clock Control Register
Reserved 0x6473 – 9 Yes Reserved
0x647B
Reserved 0x647C 1 Yes Reserved
CTRIPPFCOCTL 0x647D 1 Yes CTRIPPFC CTRIPxx Outputs Status Register
CTRIPPFCSTS 0x647E 1 Yes CTRIPPFC CTRIPxx Flag Clear Register
CTRIPPFCFLGCLR 0x647F 1 Yes CTRIPPFC COMP Test Control Register
Table 6-15. LOCK Registers
REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED
LOCKCTRIP 0x64F0 1 Yes Lock Register for CTRIP Filters Register
Reserved 0x64F1 1 Yes Reserved
LOCKDAC 0x64F2 1 Yes Lock Register for DACs Register
Reserved 0x64F3 1 Yes Reserved
LOCKAMPCOMP 0x64F4 1 Yes Lock Register for Amplifiers and Comparators Register
Reserved 0x64F5 1 Yes Reserved
LOCKSWITCH 0x64F6 1 Yes Lock Register for Switches Register
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6.3.2.3 Programmable Gain Amplifier Electrical Data/Timing
Table 6-16. Op-Amp Linear Output and ADC Sampling Time Across Gain Settings
MINIMUM
INTERNAL RESISTOR RATIO EQUIVALENT GAIN FROM LINEAR OUTPUT RANGE ADC SAMPLING TIME INPUT TO OUTPUT OF OP-AMP TO ACHIEVE SETTLING
ACCURACY
10 11 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23)
5 6 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23)
2 3 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23)
Table 6-17. PGA Gain Stage: DC Accuracy Across Gain Settings
COMPENSATED COMPENSATED INPUT
INTERNAL RESISTOR RATIO EQUIVALENT GAIN FROM GAIN-ERROR DRIFT ACROSS OFFSET-ERROR ACROSS INPUT TO OUTPUT TEMPERATURE AND SUPPLY TEMPERATURE AND SUPPLY
VARIATIONS VARIATIONS IN mV
10 11 < ±2.5% < ±8 mV
5 6 < ±1.5% < ±8 mV
2 3 < ±1.0% < ±8 mV
6.3.2.4 Comparator Block Electrical Data/Timing
Table 6-18. Electrical Characteristics of the Comparator/DAC
PARAMETER MIN TYP MAX UNITS
Comparator
Comparator Input Range VSSA – VDDA V
Comparator response time to PWM Trip Zone (Async) 65 ns
Comparator large step response time to PWM Trip Zone (Async) 95 ns
Input Offset TBD mV
Input Hysteresis(1) TBD mV
DAC
DAC Output Range VDDA / 26 – VDDA V
DAC resolution 6 bits
DAC Gain –1.5 %
DAC Offset 10 mV
Monotonic Yes
INL 0.2 LSB
(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration, which results in an effective 100-kΩ feedback
resistance between the output of the comparator and the non-inverting input of the comparator. There is an option to disable the
hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x
Piccolo Technical Reference Manual (literature number SPRUHE5) for more information on this option if needed in your system.
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6.3.2.5 VREFOUT Buffered DAC Electrical Data
Table 6-19. Electrical Characteristics of VREFOUT Buffered DAC
PARAMETER MIN TYP MAX UNITS
VREFOUT Programmable Range 6 56 LSB
VREFOUT resolution 6 bits
VREFOUT Gain –1.5 %
VREFOUT Offset 10 mV
Monotonic Yes
INL ±0.2 LSB
Load 3 kΩ
100 pF
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(SPIBRR 1)
LSPCLK
Baud rate
+
= when SPIBRR = 3 to127
4
LSPCLK
Baud rate = when SPIBRR = 0,1, 2
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6.4 Serial Peripheral Interface (SPI)
6.4.1 Serial Peripheral Interface Device-Specific Information
The device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the MCU and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers, display drivers, and
ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO if the SPI module is not used.
• Two operational modes: master and slave
Baud rate: 125 different programmable rates.
• Data word length: one to sixteen data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
• Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
• 4-level transmit/receive FIFO
• Delayed transmit control
• Bi-directional 3-wire SPI mode support
• Audio data receive support via SPISTE inversion
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S
SPICTL.0
SPI INT FLAG
SPI INT
ENA
SPISTS.6
S
Clock
Polarity
Talk
LSPCLK
SPI Bit Rate
State Control
Clock
Phase
Receiver
Overrun Flag
SPICTL.4
Overrun
INT ENA
SPICCR.3 - 0
SPIBRR.6 - 0 SPICCR.6 SPICTL.3
SPIDAT.15 - 0
SPICTL.1
M
S
M
Master/Slave
SPISTS.7
SPIDAT
Data Register
M
S
SPI Char SPICTL.2
SPISIMO
SPISOMI
SPICLK
SW2
S
M
M
S
SW3
To CPU
M
SW1
RX FIFO _0
RX FIFO _1
-----
RX FIFO _3
TX FIFO Registers
TX FIFO _0
TX FIFO _1
-----
TX FIFO _3
RX FIFO Registers
16
16
16
TX Interrupt
Logic
RX Interrupt
Logic
SPIINT
SPITX
SPIFFOVF
FLAG
SPIFFRX.15
TX FIFO Interrupt
RX FIFO Interrupt
SPIRXBUF
SPITXBUF
SPIFFTX.14
SPIFFENA
SPISTE
16
3 2 1 0
6 5 4 3 2 1 0
TW
TW
TW
SPIPRI.0
TRIWIRE
SPIPRI.1
STEINV
STEINV
SPIRXBUF
Buffer Register
SPITXBUF
Buffer Register
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Figure 6-14 is a block diagram of the SPI in slave mode.
A. SPISTE is driven low by the master for a slave device.
Figure 6-14. SPI Module Block Diagram (Slave Mode)
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6.4.2 Serial Peripheral Interface Register Descriptions
The SPI port operation is configured and controlled by the registers listed in Table 6-20.
Table 6-20. SPI-A Registers
NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1)
SPICCR 0x7040 1 No SPI-A Configuration Control Register
SPICTL 0x7041 1 No SPI-A Operation Control Register
SPISTS 0x7042 1 No SPI-A Status Register
SPIBRR 0x7044 1 No SPI-A Baud Rate Register
SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register
SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register
SPIDAT 0x7049 1 No SPI-A Serial Data Register
SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register
SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register
SPIFFCT 0x704C 1 No SPI-A FIFO Control Register
SPIPRI 0x704F 1 No SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
6.4.3 Serial Peripheral Interface Master Mode Electrical Data/Timing
Table 6-21 lists the master mode timing (clock phase = 0) and Table 6-22 lists the timing (clock
phase = 1). Figure 6-15 and Figure 6-16 show the timing waveforms.
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Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5)
SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD
NO. SPIBRR = 0 OR 2 AND SPIBRR > 3 UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns
2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns
(clock polarity = 0)
tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO)
(clock polarity = 1)
3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns
(clock polarity = 0)
tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO)
(clock polarity = 1)
4 td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO 10 10 ns
valid (clock polarity = 0)
td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO 10 10
valid (clock polarity = 1)
5 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 ns
SPICLK low (clock polarity = 0)
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10
SPICLK high (clock polarity = 1)
8 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK 26 26 ns
low (clock polarity = 0)
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK 26 26
high (clock polarity = 1)
9 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 ns
SPICLK low (clock polarity = 0)
tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10
SPICLK high (clock polarity = 1)
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
SPISTE
(A)
1
2
3
5
8
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A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-15. SPI Master Mode External Timing (Clock Phase = 0)
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Table 6-22. SPI Master Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) (5)
SPI WHEN (SPIBRR + 1) IS EVEN SPI WHEN (SPIBRR + 1) IS ODD
NO. OR SPIBRR = 0 OR 2 AND SPIBRR > 3 UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns
2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns
(clock polarity = 0)
tw(SPCL))M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO
(clock polarity = 1)
3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns
(clock polarity = 0)
tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO)
(clock polarity = 1)
6 tsu(SIMO-SPCH)M Setup time, SPISIMO data valid 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns
before SPICLK high
(clock polarity = 0)
tsu(SIMO-SPCL)M Setup time, SPISIMO data valid 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10
before SPICLK low
(clock polarity = 1)
7 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns
SPICLK high (clock polarity = 0)
tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10
SPICLK low (clock polarity = 1)
10 tsu(SOMI-SPCH)M Setup time, SPISOMI before 26 26 ns
SPICLK high (clock polarity = 0)
tsu(SOMI-SPCL)M Setup time, SPISOMI before 26 26
SPICLK low (clock polarity = 1)
11 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 ns
SPICLK high (clock polarity = 0)
tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10
SPICLK low (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master in data
must be valid
Master out data Is valid
1
7
6
10
3
2
SPISTE(A)
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A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-16. SPI Master Mode External Timing (Clock Phase = 1)
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20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO data
must be valid
SPISOMI data Is valid
19
16
14
13
12
SPISTE(A)
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6.4.4 Serial Peripheral Interface Slave Mode Electrical Data/Timing
Table 6-23 lists the slave mode external timing (clock phase = 0) and Table 6-24 (clock phase = 1).
Figure 6-17 and Figure 6-18 show the timing waveforms.
Table 6-23. SPI Slave Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5)
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(LCO) ns
13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S
14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S
15 td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 21 ns
td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 21
16 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S ns
tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S
19 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 26 ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 26
20 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 ns
tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-17. SPI Slave Mode External Timing (Clock Phase = 0)
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Data Valid
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO data
must be valid
SPISOMI data is valid
21
12
18
17
14
13
SPISTE(A)
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Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3) (4)
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 8tc(LCO) ns
13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC) S
14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC) S ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S
17 tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns
tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S
18 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low 0.75tc(SPC)S ns
(clock polarity = 1)
tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high 0.75tc(SPC) S
(clock polarity = 0)
21 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 26 ns
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 26
22 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high 0.5tc(SPC)S – 10 ns
(clock polarity = 0)
tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low 0.5tc(SPC)S – 10
(clock polarity = 1)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-18. SPI Slave Mode External Timing (Clock Phase = 1)
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(BRR 1) * 8
LSPCLK
Baud rate
+
= when BRR ¹ 0
16
LSPCLK
Baud rate = when BRR = 0
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6.5 Serial Communications Interface (SCI)
6.5.1 Serial Communications Interface Device-Specific Information
The 2805x devices include three serial communications interface (SCI) modules (SCI-A, SCI-B, SCI-C).
Each SCI module supports digital communications between the CPU and other asynchronous peripherals
that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are doublebuffered,
and each has its own separate enable and interrupt bits. Both can be operated independently or
simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds
through a 16-bit baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
• Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ (non-return-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 4-level transmit/receive FIFO
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TX FIFO _0
LSPCLK
WUT
Frame Format and Mode
Even/Odd Enable
Parity
SCI RX Interrupt select logic
BRKDT
RXRDY
SCIRXST.6
SCICTL1.3
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt select logic
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
SCICCR.6 SCICCR.5
SCITXBUF.7-0
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 - 0
Transmitter-Data
Buffer Register
8 SCICTL2.6
SCICTL2.7
Baud Rate
LSbyte
Register
RXSHF
Register
TXSHF
Register
SCIRXST.5
1 TX FIFO _1
-----
TX FIFO _3
8
TX FIFO registers
TX FIFO
TX Interrupt
Logic
TXINT
SCIFFTX.14
RX FIFO _3
SCIRXBUF.7-0
Receive Data
Buffer register
SCIRXBUF.7-0
-----
RX FIFO_1
RX FIFO _0
8
RX FIFO registers
SCICTL1.0
RX Interrupt
Logic
RXINT
RX FIFO
SCIFFRX.15
RXFFOVF
RX Error
SCIRXST.7
RX Error FE OE PE
SCIRXST.4 - 2
To CPU
To CPU
AutoBaud Detect logic
SCICTL1.1
SCIFFENA
Interrupts
Interrupts
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Figure 6-19 shows the SCI module block diagram.
Figure 6-19. Serial Communications Interface (SCI) Module Block Diagram
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6.5.2 Serial Communications Interface Register Descriptions
The SCI port operation is configured and controlled by the registers listed in Table 6-25.
Table 6-25. SCI-A Registers(1)
NAME ADDRESS SIZE (x16) EALLOW DESCRIPTION PROTECTED
SCICCRA 0x7050 1 No SCI-A Communications Control Register
SCICTL1A 0x7051 1 No SCI-A Control Register 1
SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits
SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits
SCICTL2A 0x7054 1 No SCI-A Control Register 2
SCIRXSTA 0x7055 1 No SCI-A Receive Status Register
SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register
SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register
SCIFFTXA(2) 0x705A 1 No SCI-A FIFO Transmit Register
SCIFFRXA(2) 0x705B 1 No SCI-A FIFO Receive Register
SCIFFCTA(2) 0x705C 1 No SCI-A FIFO Control Register
SCIPRIA 0x705F 1 No SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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6.6 Enhanced Controller Area Network (eCAN)
6.6.1 Enhanced Controller Area Network Device-Specific Information
The CAN module (eCAN-A) has the following features:
• Fully compliant with CAN protocol, version 2.0B
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
• Low-power mode
• Programmable wake-up on bus activity
• Automatic reply to a remote request message
• Automatic retransmission of a frame in case of loss of arbitration or error
• 32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 4.6875 kbps.
The F2805x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
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Mailbox RAM
(512 Bytes)
32-Message Mailbox
of 4 x 32-Bit Words
Memory Management
Unit
CPU Interface,
Receive Control Unit,
Timer Management Unit
eCAN Memory
(512 Bytes)
Registers and
Message Objects Control
Message Controller
32 32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
Enhanced CAN Controller 32
eCAN0INT eCAN1INT Controls Address Data
32
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
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Figure 6-20. eCAN Block Diagram and Interface Circuit
Table 6-26. 3.3-V eCAN Transceivers
PART NUMBER SUPPLY LOW-POWER SLOPE VREF OTHER TVOLTAGE MODE CONTROL A
SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C
SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C
SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C
SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C
SN65HVD232 3.3 V None None None – –40°C to 85°C
SN65HVD232Q 3.3 V None None None – –40°C to 125°C
SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C
SN65HVD234 3.3 V Standby and Sleep Adjustable None – –40°C to 125°C
SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C
ISO1050 3–5.5 V None None None Built-in Isolation –55°C to 105°C
Low Prop Delay
Thermal Shutdown
Failsafe Operation
Dominant Time-Out
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Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
Master Control - CANMC
Bit-Timing Configuration - CANBTC
Error and Status - CANES
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Global Interrupt Flag 1 - CANGIF1
Time-Out Control - CANTOC
Time-Out Status - CANTOS
Reserved
eCAN-A Control and Status Registers
61E8h-61E9h Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
Message Mailbox (16 Bytes)
Control and Status Registers
6000h
603Fh
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
6040h
607Fh
6080h
60BFh
60C0h
60FFh
eCAN-A Memory (512 Bytes)
Message Object Time Stamps (MOTS)
(32 x 32-Bit RAM)
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
6100h-6107h Mailbox 0
6108h-610Fh Mailbox 1
6110h-6117h Mailbox 2
6118h-611Fh Mailbox 3
eCAN-A Memory RAM (512 Bytes)
6120h-6127h Mailbox 4
61E0h-61E7h Mailbox 28
61E8h-61EFh Mailbox 29
61F0h-61F7h Mailbox 30
61F8h-61FFh Mailbox 31
61EAh-61EBh
61ECh-61EDh
61EEh-61EFh
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Figure 6-21. eCAN-A Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO,
and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be
enabled if the eCAN RAM (LAM, MOTS, MOTO, and mailbox RAM) is used as generalpurpose
RAM.
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6.6.2 Enhanced Controller Area Network Register Descriptions
The CAN registers listed in Table 6-27 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 6-27. CAN Register Map(1)
REGISTER NAME eCAN-A SIZE (x32) DESCRIPTION ADDRESS
CANME 0x6000 1 Mailbox enable
CANMD 0x6002 1 Mailbox direction
CANTRS 0x6004 1 Transmit request set
CANTRR 0x6006 1 Transmit request reset
CANTA 0x6008 1 Transmission acknowledge
CANAA 0x600A 1 Abort acknowledge
CANRMP 0x600C 1 Receive message pending
CANRML 0x600E 1 Receive message lost
CANRFP 0x6010 1 Remote frame pending
CANGAM 0x6012 1 Global acceptance mask
CANMC 0x6014 1 Master control
CANBTC 0x6016 1 Bit-timing configuration
CANES 0x6018 1 Error and status
CANTEC 0x601A 1 Transmit error counter
CANREC 0x601C 1 Receive error counter
CANGIF0 0x601E 1 Global interrupt flag 0
CANGIM 0x6020 1 Global interrupt mask
CANGIF1 0x6022 1 Global interrupt flag 1
CANMIM 0x6024 1 Mailbox interrupt mask
CANMIL 0x6026 1 Mailbox interrupt level
CANOPC 0x6028 1 Overwrite protection control
CANTIOC 0x602A 1 TX I/O control
CANRIOC 0x602C 1 RX I/O control
CANTSC 0x602E 1 Time stamp counter (Reserved in SCC mode)
CANTOC 0x6030 1 Time-out control (Reserved in SCC mode)
CANTOS 0x6032 1 Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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6.7 Inter-Integrated Circuit (I2C)
6.7.1 Inter-Integrated Circuit Device-Specific Information
The device contains one I2C Serial Port. Figure 6-22 shows how the I2C peripheral module interfaces
within the device.
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
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I2CXSR I2CDXR
I2CRSR I2CDRR
Clock
Synchronizer
Prescaler
Noise Filters
Arbitrator
I2C INT
Peripheral Bus
Interrupt to
CPU/PIE
SDA
SCL
Control/Status
Registers CPU
I2C Module
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
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A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 6-22. I2C Peripheral Module Interfaces
6.7.2 Inter-Integrated Circuit Register Descriptions
The registers in Table 6-28 configure and control the I2C port operation.
Table 6-28. I2C-A Registers
NAME ADDRESS EALLOW DESCRIPTION PROTECTED
I2COAR 0x7900 No I2C own address register
I2CIER 0x7901 No I2C interrupt enable register
I2CSTR 0x7902 No I2C status register
I2CCLKL 0x7903 No I2C clock low-time divider register
I2CCLKH 0x7904 No I2C clock high-time divider register
I2CCNT 0x7905 No I2C data count register
I2CDRR 0x7906 No I2C data receive register
I2CSAR 0x7907 No I2C slave address register
I2CDXR 0x7908 No I2C data transmit register
I2CMDR 0x7909 No I2C mode register
I2CISRC 0x790A No I2C interrupt source register
I2CPSC 0x790C No I2C prescaler register
I2CFFTX 0x7920 No I2C FIFO transmit register
I2CFFRX 0x7921 No I2C FIFO receive register
I2CRSR – No I2C receive shift register (not accessible to the CPU)
I2CXSR – No I2C transmit shift register (not accessible to the CPU)
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6.7.3 Inter-Integrated Circuit Electrical Data/Timing
Table 6-29. I2C Timing
TEST CONDITIONS MIN MAX UNIT
fSCL SCL clock frequency I2C clock module frequency is between 400 kHz
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
vil Low level input voltage 0.3 VDDIO V
Vih High level input voltage 0.7 VDDIO V
Vhys Input hysteresis 0.05 VDDIO V
Vol Low level output voltage 3 mA sink current 0 0.4 V
tLOW Low period of SCL clock I2C clock module frequency is between 1.3 μs
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tHIGH High period of SCL clock I2C clock module frequency is between 0.6 μs
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
lI Input current with an input voltage –10 10 μA
between 0.1 VDDIO and 0.9 VDDIO MAX
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6.8 Enhanced Pulse Width Modulator (ePWM)
6.8.1 Enhanced Pulse Width Modulator Device-Specific Information
The devices contain up to seven enhanced PWM Modules (ePWM1–ePWM7). Figure 6-23 shows a block
diagram of multiple ePWM modules. Figure 6-24 shows the signal interconnections with the ePWM. See
the Enhanced Pulse Width Modulator (ePWM) Module chapter of the TMS320x2805x Piccolo Technical
Reference Manual (literature number SPRUHE5) for more details.
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EPWM1TZINT
PIE
EPWM1INT
EPWM2TZINT
EPWM2INT
EPWMxTZINT
EPWMxINT
CTRIP
Output
Subsystem
SOCA1
ADC SOCB1
SOCA2
SOCB2
SOCAx
SOCBx
EPWM1SYNCI
EPWM2SYNCI
EPWM1SYNCO
EPWM2SYNCO
EPWM1
Module
EPWM2
Module
EPWMxSYNCI
EPWMx
Module
CTRIPxx
TZ6
TZ6
TZ1 to TZ3
TZ5
CLOCKFAIL
TZ4
EQEP1ERR
EMUSTOP
TZ5
CLOCKFAIL
TZ4
EQEP1ERR
EMUSTOP
EPWM1ENCLK
TBCLKSYNC
EPWM2ENCLK
TBCLKSYNC
TZ5
TZ6
EPWMxENCLK
TBCLKSYNC
CLOCKFAIL
TZ4
EQEP1ERR
EMUSTOP
EPWM1B
C28x CPU
System Control
eQEP1
TZ1 to TZ3
TZ1 to TZ3
EPWM1SYNCO
EPWM2B
eCAPI
EPWMxB
EQEP1ERR
EPWMxA
EPWM2A
EPWM1A
G
P
I
O
M
U
X
ADCSOCBO
ADCSOCAO
Peripheral Bus
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCA1
SOCA2
SPCAx
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCB1
SOCB2
SPCBx
EPWMSYNCI
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Figure 6-23. ePWM
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TBPRD Shadow (24)
TBPRD Active (24)
Counter
Up/Down
(16 Bit)
TCBNT
Active (16)
TBCTL[PHSEN]
CTR=PRD
16
Phase
Control
CTR=ZERO
CTR_Dir
CTR=ZERO
CTR=CMPB
Disabled
TBCTL[SYNCOSEL]
EPWMxSYNCO
Time-Base (TB)
TBPHS Active (24)
Sync
In/Out
Select
Mux
CTR=PRD
CTR=ZERO
CTR=CMPA
CTR=CMPB
CTR_Dir
DCAEVT1.soc
(A)
DCBEVT1.soc
(A)
Event
Trigger
and
Interrupt
(ET)
EPWMxINT
EPWMxSOCA
EPWMxSOCB
EPWMxSOCA
EPWMxSOCB
ADC
Action
Qualifier
(AQ)
EPWMA
Dead
Band
(DB)
EPWMB
PWM
Chopper
(PC)
Trip
Zone
(TZ)
EPWMxA
EPWMxB
CTR=ZERO
EPWMxTZINT
TZ1 to TZ3
EMUSTOP
CLOCKFAIL
EQEP1ERR
DCAEVT1.force
(A)
DCAEVT2.force
(A)
DCBEVT1.force
(A)
DCBEVT2.force
(A)
CTR=CMPA
16
CTR=CMPB
16
CMPB Active (16)
CMPB Shadow (16)
CTR=PRD or ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter
EPWMxSYNCI
TBCTL[SWFSYNC]
(Software Forced
Sync)
DCAEVT1.sync
DCBEVT1.sync
CMPA Active (24)
CMPA Shadow (24)
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A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the
COMPxOUT and TZ signals.
Figure 6-24. ePWM Sub-Modules Showing Critical Internal Signal Interconnections
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6.8.2 Enhanced Pulse Width Modulator Register Descriptions
Table 6-30 and Table 6-31 show the complete ePWM register set per module.
Table 6-30. ePWM1–ePWM4 Control and Status Registers
NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / DESCRIPTION #SHADOW
TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register
Reserved 0x6802 0x6842 0x6882 0x68C2 1 / 0 Reserved
TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set
Reserved 0x6806 0x6846 0x6886 0x68C6 1 / 1 Reserved
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register
Reserved 0x6808 0x6848 0x6888 0x68C8 1 / 1 Reserved
CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register(1)
TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1 / 0 Trip Zone Digital Compare Register
TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register (1)
TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register
(1) Registers that are EALLOW protected.
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Table 6-30. ePWM1–ePWM4 Control and Status Registers (continued)
NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / DESCRIPTION #SHADOW
ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register
Reserved 0x6820 0x6860 0x68A0 0x68E0 1 / 0 Reserved
Reserved 0x6821 - - - 1 / 0 Reserved
Reserved 0x6826 - - - 1 / 0 Reserved
Reserved 0x6828 0x6868 0x68A8 0x68E8 1 / 0 Reserved
Reserved 0x682A 0x686A 0x68AA 0x68EA 1 / W(2) Reserved
TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W(2) Time Base Period Register Mirror
Reserved 0x682C 0x686C 0x68AC 0x68EC 1 / W(2) Reserved
CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W(2) Compare A Register Mirror
DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1 / 0 Digital Compare Trip Select Register (1)
DCACTL 0x6831 0x6871 0x68B1 0x68F1 1 / 0 Digital Compare A Control Register(1)
DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1 / 0 Digital Compare B Control Register(1)
DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1 / 0 Digital Compare Filter Control Register(1)
DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1 / 0 Digital Compare Capture Control Register(3)
DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1 / 1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1 / 0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1 / 0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1 / 0 Digital Compare Filter Window Counter Register
DCCAP 0x6839 0x6879 0x68B9 0x68F9 1 / 1 Digital Compare Counter Capture Register
(2) W = Write to shadow register
(3) Registers that are EALLOW protected.
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Table 6-31. ePWM5–ePWM7 Control and Status Registers
NAME ePWM5 ePWM6 ePWM7 SIZE (x16) / DESCRIPTION #SHADOW
TBCTL 0x6900 0x6940 0x6980 1 / 0 Time Base Control Register
TBSTS 0x6901 0x6941 0x6981 1 / 0 Time Base Status Register
Reserved 0x6902 0x6942 0x6982 1 / 0 Reserved
TBPHS 0x6903 0x6943 0x6983 1 / 0 Time Base Phase Register
TBCTR 0x6904 0x6944 0x6984 1 / 0 Time Base Counter Register
TBPRD 0x6905 0x6945 0x6985 1 / 1 Time Base Period Register Set
Reserved 0x6906 0x6946 0x6986 1 / 1 Reserved
CMPCTL 0x6907 0x6947 0x6987 1 / 0 Counter Compare Control Register
Reserved 0x6908 0x6948 0x6988 1 / 1 Reserved
CMPA 0x6909 0x6949 0x6989 1 / 1 Counter Compare A Register Set
CMPB 0x690A 0x694A 0x698A 1 / 1 Counter Compare B Register Set
AQCTLA 0x690B 0x694B 0x698B 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x690C 0x694C 0x698C 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x690D 0x694D 0x698D 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x690E 0x694E 0x698E 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x690F 0x694F 0x698F 1 / 1 Dead-Band Generator Control Register
DBRED 0x6910 0x6950 0x6990 1 / 0 Dead-Band Generator Rising Edge Delay Count
Register
DBFED 0x6911 0x6951 0x6991 1 / 0 Dead-Band Generator Falling Edge Delay Count
Register
TZSEL 0x6912 0x6952 0x6992 1 / 0 Trip Zone Select Register(1)
TZDCSEL 0x6913 0x6953 0x6993 1 / 0 Trip Zone Digital Compare Register
TZCTL 0x6914 0x6954 0x6994 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6915 0x6955 0x6995 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6916 0x6956 0x6996 1 / 0 Trip Zone Flag Register (1)
TZCLR 0x6917 0x6957 0x6997 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6918 0x6958 0x6998 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6919 0x6959 0x6999 1 / 0 Event Trigger Selection Register
ETPS 0x691A 0x695A 0x699A 1 / 0 Event Trigger Prescale Register
ETFLG 0x691B 0x695B 0x699B 1 / 0 Event Trigger Flag Register
ETCLR 0x691C 0x695C 0x699C 1 / 0 Event Trigger Clear Register
ETFRC 0x691D 0x695D 0x699D 1 / 0 Event Trigger Force Register
PCCTL 0x691E 0x695E 0x699E 1 / 0 PWM Chopper Control Register
Reserved 0x6920 0x6960 0x69A0 1 / 0 Reserved
Reserved - - - 1 / 0 Reserved
Reserved - - - 1 / 0 Reserved
Reserved 0x6928 0x6968 0x69A8 1 / 0 Reserved
Reserved 0x692A 0x696A 0x69AA 1 / W(2) Reserved
TBPRDM 0x692B 0x696B 0x69AB 1 / W(2) Time Base Period Register Mirror
Reserved 0x692C 0x696C 0x69AC 1 / W(2) Reserved
CMPAM 0x692D 0x696D 0x69AD 1 / W(2) Compare A Register Mirror
DCTRIPSEL 0x6930 0x6970 0x69B0 1 / 0 Digital Compare Trip Select Register (1)
DCACTL 0x6931 0x6971 0x69B1 1 / 0 Digital Compare A Control Register(1)
DCBCTL 0x6932 0x6972 0x69B2 1 / 0 Digital Compare B Control Register(1)
DCFCTL 0x6933 0x6973 0x69B3 1 / 0 Digital Compare Filter Control Register(1)
DCCAPCT 0x6934 0x6974 0x69B4 1 / 0 Digital Compare Capture Control Register(1)
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register
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Table 6-31. ePWM5–ePWM7 Control and Status Registers (continued)
NAME ePWM5 ePWM6 ePWM7 SIZE (x16) / DESCRIPTION #SHADOW
DCFOFFSET 0x6935 0x6975 0x69B5 1 / 1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6936 0x6976 0x69B6 1 / 0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6937 0x6977 0x69B7 1 / 0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6938 0x6978 0x69B8 1 / 0 Digital Compare Filter Window Counter Register
DCCAP 0x6939 0x6979 0x69B9 1 / 1 Digital Compare Counter Capture Register
6.8.3 Enhanced Pulse Width Modulator Electrical Data/Timing
PWM refers to PWM outputs on ePWM1–7. Table 6-32 shows the PWM timing requirements and Table 6-
33, switching characteristics.
Table 6-32. ePWM Timing Requirements(1)
MIN MAX UNIT
tw(SYCIN) Sync input pulse width Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 6-45.
Table 6-33. ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 33.33 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles
td(PWM)tza Delay time, trip input active to PWM forced high no pin load 25 ns
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns
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PWM
(B)
TZ
(A)
SYSCLK
tw(TZ)
td(TZ-PWM)HZ
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6.8.3.1 Trip-Zone Input Timing
Table 6-34. Trip-Zone Input Timing Requirements(1)
MIN MAX UNIT
tw(TZ) Pulse duration, TZx input low Asynchronous 2tc(TBCLK) cycles
Synchronous 2tc(TBCLK) cycles
With input qualifier 2tc(TBCLK) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 6-45.
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-25. PWM Hi-Z Characteristics
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TSCTR
(counter−32 bit)
RST
CAP1
(APRD active)
LD
CAP2
(ACMP active)
LD
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
LD
Continuous /
Oneshot
Capture Control
LD1
LD2
LD3
LD4
32
32
PRD [0−31]
CMP [0−31]
CTR [0−31]
eCAPx
Interrupt
Trigger
and
Flag
control
to PIE
CTR=CMP
32
32
32
32
32
ACMP
shadow
Event
Pre-scale
CTRPHS
(phase register−32 bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR [0−31]
PRD [0−31]
CMP [0−31]
CTR=CMP
CTR=PRD
OVF CTR_OVF
APWM mode
Delta−mode
SYNC
Capture events 4
CEVT[1:4]
APRD
shadow
32
32
MODE SELECT
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6.9 Enhanced Capture Module (eCAP)
6.9.1 Enhanced Capture Module Device-Specific Information
The device contains an enhanced capture module (eCAP1). Figure 6-26 shows a functional block diagram
of a module.
Figure 6-26. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for
low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
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6.9.2 Enhanced Capture Module Register Descriptions
Table 6-35 shows the eCAP Control and Status Registers.
Table 6-35. eCAP Control and Status Registers
NAME eCAP1 SIZE (x16) EALLOW PROTECTED DESCRIPTION
TSCTR 0x6A00 2 Time-Stamp Counter
CTRPHS 0x6A02 2 Counter Phase Offset Value Register
CAP1 0x6A04 2 Capture 1 Register
CAP2 0x6A06 2 Capture 2 Register
CAP3 0x6A08 2 Capture 3 Register
CAP4 0x6A0A 2 Capture 4 Register
Reserved 0x6A0C – 0x6A12 8 Reserved
ECCTL1 0x6A14 1 Capture Control Register 1
ECCTL2 0x6A15 1 Capture Control Register 2
ECEINT 0x6A16 1 Capture Interrupt Enable Register
ECFLG 0x6A17 1 Capture Interrupt Flag Register
ECCLR 0x6A18 1 Capture Interrupt Clear Register
ECFRC 0x6A19 1 Capture Interrupt Force Register
Reserved 0x6A1A – 0x6A1F 6 Reserved
6.9.3 Enhanced Capture Module Electrical Data/Timing
Table 6-36 shows the eCAP timing requirement and Table 6-37 shows the eCAP switching characteristics.
Table 6-36. Enhanced Capture (eCAP) Timing Requirement(1)
MIN MAX UNIT
tw(CAP) Capture input pulse width Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 6-45.
Table 6-37. eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns
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QWDTMR
QWDPRD
16
UTIME QWDOG
QUPRD
QUTMR
32
UTOUT
WDTOUT
Quadrature
Capture
Unit
(QCAP)
QCPRDLAT
QCTMRLAT
16
QFLG
QEPSTS
QEPCTL
Registers
Used by
Multiple Units
QCLK
QDIR
QI
QS
PHE
PCSOUT
Quadrature
Decoder
(QDU)
QDECCTL
16
Position Counter/
Control Unit
(PCCU)
QPOSLAT
QPOSSLAT
16
QPOSILAT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
GPIO
MUX
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxS
EQEPxI
QPOSCMP QEINT
QFRC
32
QCLR
QPOSCTL
32 16
QPOSCNT
QPOSMAX
QPOSINIT
PIE
EQEPxINT
Enhanced QEP (eQEP) Peripheral
System Control
Registers
QCTMR
QCPRD
16 16
QCAPCTL
EQEPxENCLK
SYSCLKOUT
To CPU
Data Bus
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6.10 Enhanced Quadrature Encoder Pulse (eQEP)
6.10.1 Enhanced Quadrature Encoder Pulse Device-Specific Information
The device contains one enhanced quadrature encoder pulse (eQEP) module.
Figure 6-27 shows the eQEP functional block diagram.
Figure 6-27. eQEP Functional Block Diagram
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6.10.2 Enhanced Quadrature Encoder Pulse Register Descriptions
Table 6-38 shows the eQEP Control and Status Registers.
Table 6-38. eQEP Control and Status Registers
eQEP1 eQEP1 NAME ADDRESS SIZE(x16)/ REGISTER DESCRIPTION #SHADOW
QPOSCNT 0x6B00 2/0 eQEP Position Counter
QPOSINIT 0x6B02 2/0 eQEP Initialization Position Count
QPOSMAX 0x6B04 2/0 eQEP Maximum Position Count
QPOSCMP 0x6B06 2/1 eQEP Position-compare
QPOSILAT 0x6B08 2/0 eQEP Index Position Latch
QPOSSLAT 0x6B0A 2/0 eQEP Strobe Position Latch
QPOSLAT 0x6B0C 2/0 eQEP Position Latch
QUTMR 0x6B0E 2/0 eQEP Unit Timer
QUPRD 0x6B10 2/0 eQEP Unit Period Register
QWDTMR 0x6B12 1/0 eQEP Watchdog Timer
QWDPRD 0x6B13 1/0 eQEP Watchdog Period Register
QDECCTL 0x6B14 1/0 eQEP Decoder Control Register
QEPCTL 0x6B15 1/0 eQEP Control Register
QCAPCTL 0x6B16 1/0 eQEP Capture Control Register
QPOSCTL 0x6B17 1/0 eQEP Position-compare Control Register
QEINT 0x6B18 1/0 eQEP Interrupt Enable Register
QFLG 0x6B19 1/0 eQEP Interrupt Flag Register
QCLR 0x6B1A 1/0 eQEP Interrupt Clear Register
QFRC 0x6B1B 1/0 eQEP Interrupt Force Register
QEPSTS 0x6B1C 1/0 eQEP Status Register
QCTMR 0x6B1D 1/0 eQEP Capture Timer
QCPRD 0x6B1E 1/0 eQEP Capture Period Register
QCTMRLAT 0x6B1F 1/0 eQEP Capture Timer Latch
QCPRDLAT 0x6B20 1/0 eQEP Capture Period Latch
Reserved 0x6B21 – 31/0
0x6B3F
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6.10.3 Enhanced Quadrature Encoder Pulse Electrical Data/Timing
Table 6-39 shows the eQEP timing requirement and Table 6-40 shows the eQEP switching
characteristics.
Table 6-39. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements(1)
TEST CONDITIONS MIN MAX UNIT
tw(QEPP) QEP input period Synchronous 2tc(SCO) cycles
With input qualifier 2[1tc(SCO) + tw(IQSW)] cycles
tw(INDEXH) QEP Index Input High time Synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) +tw(IQSW) cycles
tw(INDEXL) QEP Index Input Low time Synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW) cycles
tw(STROBH) QEP Strobe High time Synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW) cycles
tw(STROBL) QEP Strobe Input Low time Synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) +tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 6-45.
Table 6-40. eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SCO) cycles
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TRST
1
0
C28x
Core
TCK/GPIO38
TCK
XCLKIN
GPIO38_in
GPIO38_out
TDO
GPIO37_out
TDO/GPIO37
GPIO37_in
1
0
TMS
TMS/GPIO36
GPIO36_out
GPIO36_in
1
1
0
TDI
TDI/GPIO35
GPIO35_out
GPIO35_in
1
TRST
TRST
= 0: JTAG Disabled (GPIO Mode)
= 1: JTAG Mode
TRST
TMS320F28055, TMS320F28054, TMS320F28053
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6.11 JTAG Port
6.11.1 JTAG Port Device-Specific Information
On the 2805x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS
and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the
pins in Figure 6-28. During emulation/debug, the GPIO function of these pins are not available. If the
GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used
to clock the device during emulation/debug since this pin will be needed for the TCK function.
NOTE
In 2805x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in
the board design to ensure that the circuitry connected to these pins do not affect the
emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should
not prevent the emulator from driving (or being driven by) the JTAG pins for successful
debug.
Figure 6-28. JTAG/GPIO Multiplexing
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ADVANCE INFORMATION
TRST
TMS
TDI
TDO
TCK
VDDIO
MCU
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
TCK_RET
13
14
2
1
3
7
11
9
6 inches or less
PD
GND
GND
GND
GND
GND
5
4
6
8
10
12
JTAG Header
VDDIO
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6.11.1.1 Emulator Connection Without Signal Buffering for the MCU
Figure 6-29 shows the connection between the MCU and JTAG header for a single-processor
configuration. If the distance between the JTAG header and the MCU is greater than 6 inches, the
emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed.
Figure 6-29 shows the simpler, no-buffering situation. For the pullup and pulldown resistor values, see
Section 3.2.
A. See Figure 6-28 for JTAG/GPIO multiplexing.
Figure 6-29. Emulator Connection Without Signal Buffering for the MCU
NOTE
The 2805x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header
on-board, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ
(typical) resistor.
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6.12 General-Purpose Input/Output (GPIO)
6.12.1 General-Purpose Input/Output Device-Specific Information
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition
to providing individual pin bit-banging I/O capability.
Table 6-41. GPIOA MUX(1) (2)
DEFAULT AT RESET PRIMARY I/O PERIPHERAL PERIPHERAL PERIPHERAL FUNCTION SELECTION 1 SELECTION 2 SELECTION 3
GPAMUX1 REGISTER (GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11) BITS
1-0 GPIO0 EPWM1A (O) Reserved Reserved
3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O)
5-4 GPIO2 EPWM2A (O) Reserved Reserved
7-6 GPIO3 EPWM2B (O) SPISOMIA (I/O) COMP2OUT (O)
9-8 GPIO4 EPWM3A (O) Reserved Reserved
11-10 GPIO5 EPWM3B (O) SPISIMOA (I/O) ECAP1 (I/O)
13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15-14 GPIO7 EPWM4B (O) SCIRXDA (I) Reserved
17-16 GPIO8 EPWM5A (O) Reserved ADCSOCAO (O)
19-18 GPIO9 EPWM5B (O) Reserved Reserved
21-20 GPIO10 EPWM6A (O) Reserved ADCSOCBO (O)
23-22 GPIO11 EPWM6B (O) Reserved Reserved
25-24 GPIO12 TZ1 (I) SCITXDA (O) Reserved
27-26 GPIO13 TZ2 (I) Reserved Reserved
29-28 GPIO14 TZ3 (I) Reserved Reserved
31-30 GPIO15 TZ1 (I) Reserved Reserved
GPAMUX2 REGISTER (GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11) BITS
1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I)
3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I)
5-4 GPIO18 SPICLKA (I/O) Reserved XCLKOUT (O)
7-6 GPIO19/XCLKIN SPISTEA (I/O) Reserved ECAP1 (I/O)
9-8 GPIO20 EQEP1A (I) Reserved COMP1OUT (O)
11-10 GPIO21 EQEP1B (I) Reserved COMP2OUT (O)
13-12 GPIO22 EQEP1S (I/O) Reserved Reserved
15-14 GPIO23 EQEP1I (I/O) Reserved Reserved
17-16 GPIO24 ECAP1 (I/O) Reserved Reserved
19-18 GPIO25 Reserved Reserved Reserved
21-20 GPIO26 Reserved Reserved Reserved
23-22 GPIO27 Reserved Reserved Reserved
25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I)
27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I)
29-28 GPIO30 CANRXA (I) Reserved Reserved
31-30 GPIO31 CANTXA (O) Reserved Reserved
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should the Reserved GPxMUX1/2
register setting be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration
for future expansion.
(2) I = Input, O = Output, OD = Open Drain
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Table 6-42. GPIOB MUX(1)
DEFAULT AT RESET PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O FUNCTION SELECTION 1 SELECTION 2 SELECTION 3
GPBMUX1 REGISTER BITS (GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11)
1-0 GPIO32 SDAA (I/OD) EPWMSYNCI (I) ADCSOCAO (O)
3-2 GPIO33 SCLA (I/OD) EPWMSYNCO (O) ADCSOCBO (O)
5-4 GPIO34 COMP2OUT (O) Reserved COMP3OUT (O)
7-6 GPIO35 (TDI) Reserved Reserved Reserved
9-8 GPIO36 (TMS) Reserved Reserved Reserved
11-10 GPIO37 (TDO) Reserved Reserved Reserved
13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved
15-14 GPIO39 Reserved Reserved Reserved
17-16 GPIO40 EPWM7A (O) Reserved Reserved
19-18 GPIO41 EPWM7B (O) Reserved Reserved
21-20 GPIO42 Reserved Reserved COMP1OUT (O)
23-22 GPIO43 Reserved Reserved COMP2OUT (O)
25-24 GPIO44 Reserved Reserved Reserved
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
(1) I = Input, O = Output, OD = Open Drain
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
• Synchronization to SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This mode is the default mode of all
GPIO pins at reset and this mode simply synchronizes the input signal to the system clock
(SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,
after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles
before the input is allowed to change.
• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. The sampling period specifies a multiple of SYSCLKOUT cycles for sampling the
input signal. The sampling window is either 3-samples or 6-samples wide and the output is only
changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 6-32 (for 6 sample
mode).
• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.
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GPxDAT (read)
Input
Qualification
GPxMUX1/2
High Impedance
Output Control
GPIOx pin
XRS
0 = Input, 1 = Output
Low P ower
Modes Block
GPxDIR (latch)
Peripheral 2 Input
Peripheral 3 Input
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
Peripheral 1 Output Enable
Peripheral 2 Output Enable
Peripheral 3 Output Enable
00
01
10
11
00
01
10
11
00
01
10
11
GPxCTRL
Peripheral 1 Input
GPxPUD N/C
LPMCR0
Internal
Pullup
GPIOLMPSEL
GPxQSEL1/2
GPxSET
GPxDAT (latch)
GPxCLEAR
GPxTOGGLE
= Default at Reset
PIE
External Interrupt
MUX
Asynchronous
path
Asynchronous path
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
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A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This diagram is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the
Systems Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number
SPRUHE5) for pin-specific variations.
Figure 6-30. GPIO Multiplexing
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6.12.2 General-Purpose Input/Output Register Descriptions
The device supports 42 GPIO pins. The GPIO control and data registers are mapped to Peripheral
Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-43 shows the
GPIO register mapping.
Table 6-43. GPIO Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 44)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 44)
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 44)
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 44)
GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 44)
Reserved 0x6FB6 2 Reserved
Reserved 0x6FBA 2 Reserved
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 44)
GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 44)
GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 44)
GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 44)
Reserved 0x6FD8 2 Reserved
Reserved 0x6FDA 2 Reserved
Reserved 0x6FDC 2 Reserved
Reserved 0x6FDE 2 Reserved
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)
NOTE
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn and
GPxQSELn registers occurs to when the action is valid.
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GPIO
tr(GPO)
tf(GPO)
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6.12.3 General-Purpose Input/Output Electrical Data/Timing
6.12.3.1 GPIO - Output Timing
Table 6-44. General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tr(GPO) Rise time, GPIO switching low to high All GPIOs 13(1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 13(1) ns
tfGPO Toggling frequency 15 MHz
(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-44 are applicable for a 40-pF load on I/O pins.
Figure 6-31. General-Purpose Output Timing
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GPIO Signal
1
Sampling Window
Output From
Qualifier
1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(A)
GPxQSELn = 1,0 (6 samples)
[(SYSCLKOUT cycle * 2 * QUALPRD) * 5 ]
(C)
Sampling Period determined
by GPxCTRL[QUALPRD]
(B)
(D)
tw(SP)
tw(IQSW)
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6.12.3.2 GPIO - Input Timing
Table 6-45. General-Purpose Input Timing Requirements
MIN MAX UNIT
QUALPRD = 0 1tc(SCO) cycles
tw(SP) Sampling period
QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
Synchronous mode 2tc(SCO) cycles
tw(GPI)
(2) Pulse duration, GPIO low/high
With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO) cycles
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period.
The QUALPRD bit field value can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1
SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at
every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This condition would
ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-
SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 6-32. Sampling Mode
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VDDIO
VSS VSS
2 pF
> 1 MS
GPIOxn
SYSCLK
tw(GPI)
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6.12.3.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. The number of samples is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
Figure 6-33. General-Purpose Input Timing
Figure 6-34. Input Resistance Model for a GPIO Pin With an Internal Pull-up
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WAKE INT
(A)(B)
XCLKOUT
Address/Data
(internal)
td(WAKE−IDLE)
tw(WAKE−INT)
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6.12.3.4 Low-Power Mode Wakeup Timing
Table 6-46 shows the timing requirements, Table 6-47 shows the switching characteristics, and Figure 6-
35 shows the timing diagram for IDLE mode.
Table 6-46. IDLE Mode Timing Requirements(1)
MIN MAX UNIT
Without input qualifier 2tc(SCO) tw(WAKE-INT) Pulse duration, external wake-up signal cycles
With input qualifier 5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-45.
Table 6-47. IDLE Mode Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Delay time, external wake signal to program execution resume (2) cycles
• Wake-up from Flash Without input qualifier 20tc(SCO) cycles
– Flash module in active state With input qualifier 20tc(SCO) + tw(IQSW)
td(WAKE-IDLE) • Wake-up from Flash Without input qualifier 1050tc(SCO) cycles
– Flash module in sleep state With input qualifier 1050tc(SCO) + tw(IQSW)
• Wake-up from SARAM Without input qualifier 20tc(SCO) cycles
With input qualifier 20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-45.
(2) This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR
(triggered by the wake-up) signal involves additional latency.
A. WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5
OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-35. IDLE Entry and Exit Timing
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Table 6-48. STANDBY Mode Timing Requirements
MIN MAX UNIT
Pulse duration, external Without input qualification 3tc(OSCCLK) tw(WAKE-INT) wake-up signal cycles With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 6-49. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
t Delay time, IDLE instruction d(IDLE-XCOL) executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
Delay time, external wake signal to program execution cycles resume(1)
• Wake up from flash Without input qualifier 100tc(SCO) cycles
– Flash module in active state With input qualifier 100tc(SCO) + tw(WAKE-INT)
td(WAKE-STBY) Without input qualifier 1125tc(SCO) • Wake up from flash cycles
– Flash module in sleep state With input qualifier 1125tc(SCO) + tw(WAKE-INT)
Without input qualifier 100tc(SCO) • Wake up from SARAM cycles
With input qualifier 100tc(SCO) + tw(WAKE-INT)
(1) This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR
(triggered by the wake up signal) involves additional latency.
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td(IDLE−XCOL)
Wake-up
Signal
(H)
X1/X2 or
XCLKIN
XCLKOUT
Flushing Pipeline
(A)
Device
Status
STANDBY STANDBY Normal Execution
(B) (G)
(C)
(D)(E)
(F)
tw(WAKE-INT)
td(WAKE-STBY)
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A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the
wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-36. STANDBY Entry and Exit Timing Diagram
Table 6-50. HALT Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles
Table 6-51. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
tp PLL lock-up time 1 ms
Delay time, PLL lock to program execution resume
• Wake up from flash 1125tc(SCO) cycles
td(WAKE-HALT) – Flash module in sleep state
• Wake up from SARAM 35tc(SCO) cycles
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td(IDLE−XCOL)
X1/X2 or
XCLKIN
XCLKOUT
HALT HALT
Wake-up Latency
Flushing Pipeline
td(WAKE−HALT
Device
Status
PLL Lock-up Time Normal
Execution
tw(WAKE-GPIO)
GPIOn
(I)
Oscillator Start-up Time
(A)
(G)
(C)
(D)(E)
(F)
(B)
(H)
)
tp
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A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the
watchdog alive in HALT mode. Keeping INTOSC1, INTOSC2, and the watchdog alive in HALT mode is done by
writing to the appropriate bits in the CLKCTL register. After the IDLE instruction is executed, a delay of 5 OSCCLK
cycles (minimum) is needed before the wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized, which
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
H. Normal operation resumes.
I. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-37. HALT Wake-Up Using GPIOn
Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 135
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TMS320F28050
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TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797 –NOVEMBER 2012 www.ti.com
7 Device and Documentation Support
7.1 Device Support
7.1.1 Development Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of 2805x-based applications:
Software Development Tools
• Code Composer Studio™ Integrated Development Environment (IDE)
– C/C++ Compiler
– Code generation tools
– Assembler/Linker
– Cycle Accurate Simulator
• Application algorithms
• Sample applications code
Hardware Development Tools
• Development and evaluation boards
• JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100
• Flash programming tools
• Power supply
• Documentation and cables
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
7.1.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMX320F28055). Texas Instruments recommends two of
three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX
for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
136 Device and Documentation Support Copyright © 2012, Texas Instruments Incorporated
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TMS320F28050
ADVANCE INFORMATION
PREFIX
TMX
TMX = experimental device
TMP = prototype device
TMS = qualified device
320
DEVICE FAMILY
320 = TMS320 MCU Family
F
TECHNOLOGY
F = Flash
28055
DEVICE
28055
28054
28053
28052
28051
28050
PN
PACKAGE TYPE
80-Pin PN Low-Profile Quad Flatpack (LQFP)
TEMPERATURE RANGE
T
−40°C to 105°C
−40°C to 125°C
T
S
=
=
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PN) and temperature range (for example, T). Figure 7-1 provides a legend for
reading the complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your
TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F28055,
TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 Piccolo MCU
Silicon Errata (literature number SPRZ362).
Figure 7-1. Device Nomenclature
Copyright © 2012, Texas Instruments Incorporated Device and Documentation Support 137
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TMS320F28050
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
SPRS797 –NOVEMBER 2012 www.ti.com
7.2 Documentation Support
Extensive documentation supports all of the TMS320™ MCU family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications.
The following documents can be downloaded from the TI website (www.ti.com):
Data Manual and Errata
SPRS797 TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051,
TMS320F28050 Piccolo Microcontrollers Data Manual contains the pinout, signal
descriptions, as well as electrical and timing specifications for the 2805x devices.
SPRZ362 TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051,
TMS320F28050 Piccolo MCU Silicon Errata describes known advisories on silicon and
provides workarounds.
Technical Reference Manual
SPRUHE5 TMS320x2805x Piccolo Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral
and subsystem in the 2805x microcontrollers.
CPU User's Guides
SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing
unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital
signal processors (DSPs). This Reference Guide also describes emulation features available
on these DSPs.
Peripheral Guides
SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
Tools Guides
SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly
language tools (assembler and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives
for the TMS320C28x device.
SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the
TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code
and produces TMS320 DSP assembly language source code for the TMS320C28x device.
SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x™ core.
7.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
138 Device and Documentation Support Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
ADVANCE INFORMATION
TMS320F28055, TMS320F28054, TMS320F28053
TMS320F28052, TMS320F28051, TMS320F28050
www.ti.com SPRS797 –NOVEMBER 2012
8 Mechanical Packaging and Orderable Information
8.1 Thermal Data for Package
Table 8-1 shows the thermal data. See Section 2.9 for more information on thermal design considerations.
Table 8-1. Thermal Model 80-Pin PN Results
AIR FLOW
PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm
θJA [°C/W] High k PCB 49.9 38.3 36.7 34.4
ΨJT [°C/W] 0.8 1.18 1.34 1.62
ΨJB 21.6 20.7 20.5 20.1
θJC 14.2
θJB 21.9
8.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated devices. This data is subject to change without notice and without revision of this document.
Copyright © 2012, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 139
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Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051
TMS320F28050
PACKAGE OPTION ADDENDUM
www.ti.com 1-Dec-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Samples
(Requires Login)
TMS320F28050PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28050PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28050PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28051PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28051PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28051PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28052PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28052PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28052PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28053PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28053PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28053PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28054MPNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28054PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28054PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28054PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28055PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28055PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28055PNT ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TMX320F28055PNT ACTIVE LQFP PN 80 1 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Dec-2012
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
PN (S-PQFP-G80) PLASTIC QUAD FLATPACK
4040135 /B 11/96
0,17
0,27
0,13 NOM
40
21
0,25
0,45
0,75
0,05 MIN
Seating Plane
Gage Plane
60 41
61
80
20
SQ
SQ
1
13,80
14,20
12,20
9,50 TYP
11,80
1,45
1,35
1,60 MAX 0,08
0,50 0,08 M
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
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requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
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DSP dsp.ti.com Energy and Lighting www.ti.com/energy
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Interface interface.ti.com Medical www.ti.com/medical
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Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
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Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
REF102
SBVS022A – SEPTEMBER 2000 – REVISED NOVEMBER 2003
www.ti.com
FEATURES
+10V ±0.0025V OUTPUT
VERY LOW DRIFT: 2.5ppm/°C max
EXCELLENT STABILITY:
5ppm/1000hr typ
EXCELLENT LINE REGULATION:
1ppm/V max
EXCELLENT LOAD REGULATION:
10ppm/mA max
LOW NOISE: 5μVPP typ, 0.1Hz to 10Hz
WIDE SUPPLY RANGE: 11.4VDC to 36VDC
LOW QUIESCENT CURRENT: 1.4mA max
PACKAGE OPTIONS: PLASTIC DIP, SO-8
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000-2003, Texas Instruments Incorporated
10V Precision
Voltage Reference
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
APPLICATIONS
PRECISION-CALIBRATED VOLTAGE
STANDARD
D/A AND A/D CONVERTER REFERENCE
PRECISION CURRENT REFERENCE
ACCURATE COMPARATOR THRESHOLD
REFERENCE
DIGITAL VOLTMETERS
TEST EQUIPMENT
PC-BASED INSTRUMENTATION
DESCRIPTION
The REF102 is a precision 10V voltage reference. The drift
is laser-trimmed to 2.5ppm/°C max C-grade over the industrial
temperature range. The REF102 achieves its precision
without a heater. This results in low power, fast warm-up,
excellent stability, and low noise. The output voltage is
extremely insensitive to both line and load variations and can
be externally adjusted with minimal effect on drift and
stability. Single supply operation from 11.4V to 36V and
excellent overall specifications make the REF102 an ideal
choice for demanding instrumentation and system reference
applications.
–
+
A
R2 R3
R4
R6
R1
R5
1
50kΩ
22kΩ
7kΩ
4kΩ
8kΩ
DZ1
Noise
Reduction
Common
VOUT
Trim V+
14kΩ
5 2
6
8 4
REF102
REF102
REF102 2
www.ti.com SBVS022A
SPECIFIED
MAX INITIAL MAX DRIFT PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT ERROR (mV) (PPM/°C) PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
REF102AU ±10 ±10 SO-8 D –25°C to +85°C REF102AU REF102AU Tube, 100
" ±10 ±10 SO-8 D " REF102AU/2K5 REF102AU/2K5 Tape and Reel, 2500
REF102AP ±10 ±10 DIP-8 P " REF102AP REF102AP Tube, 50
REF102BU ±5 ±5 SO-8 D " REF102BU REF102BU Tube, 100
" ±5 ±5 SO-8 D " REF102BU/2K5 REF102BU/2K5 Tape and Reel, 2500
REF102BP ±5 ±5 DIP-8 P " REF102BP REF102BP Tube, 50
REF102CU ±2.5 ±2.5 SO-8 D " REF102CU REF102CU Tube, 100
" ±2.5 ±2.5 SO-8 D " REF102CU/2K5 REF102CU/2K5 Tape and Reel, 2500
REF102CP ±2.5 ±2.5 DIP-8 P " REF102CP REF102CP Tube, 50
PIN CONFIGURATIONS
Top View DIP, SO
Input Voltage ...................................................................................... +40V
Operating Temperature
P, U ................................................................................. –25°C to +85°C
Storage Temperature Range
P, U ............................................................................... –40°C to +125°C
Lead Temperature (soldering, 10s) ............................................... +300°C
(SO, 3s) ........................................................... +260°C
Short-Circuit Protection to Common or V+ .............................. Continuous
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION(1)
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
8
7
6
5
1
2
3
4
NC = Not Connected
Noise Reduction
NC
VOUT
Trim
NC
V+
Com
NC
REF102 3
SBVS022A www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C and VS = +15V power supply, unless otherwise noted.
REF102A REF102B REF102C
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
OUTPUT VOLTAGE
Initial TA = 25°C 9.99 10.01 9.995 10.005 9.9975 10.0025 V
vs Temperature (1) 10 5 2.5 ppm/°C
vs Supply
(Line Regulation) VS = 11.4V to 36V 2 1 1 ppm/V
vs Output Current
(Load Regulation) IL = 0mA to +10mA 20 10 10 ppm/mA
IL = 0mA to –5mA 40 20 20 ppm/mA
vs Time TA = +25°C
M Package 5 ✻ ✻ ppm/1000hr
P, U Packages (2) 20 ✻ ppm/1000hr
Trim Range (3) ±3 ✻ ✻ %
Capacitive Load, max 1000 ✻ ✻ pF
NOISE 0.1Hz to 10Hz 5 ✻ ✻ μVPP
OUTPUT CURRENT +10, –5 ✻ ✻ mA
INPUT VOLTAGE
RANGE +11.4 +36 ✻ ✻ ✻ ✻ V
QUIESCENT CURRENT IOUT = 0 +1.4 ✻ ✻ mA
WARM-UP TIME (4) To 0.1% 15 ✻ ✻ μs
TEMPERATURE
RANGE
Specification
REF102A, B, C –25 +85 ✻ ✻ ✻ ✻ °C
✻ Specifications same as REF102A.
NOTES: (1) The “box” method is used to specify output voltage drift vs temperature. See the Discussion of Performance section.
(2) Typically 5ppm/1000hrs after 168hr powered stabilization.
(3) Trimming the offset voltage affects drift slightly. See Installation and Operating Instructions for details.
(4) With noise reduction pin floating. See Typical Characteristics for details.
REF102 4
www.ti.com SBVS022A
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +15V, unless otherwise noted.
POWER TURN-ON RESPONSE
VOUT
VIN
Time (5μs/div)
Power Turn-On
POWER TURN-ON RESPONSE with 1μF CN
VOUT
VIN
Time (10ms/div)
Power Turn-On
POWER SUPPLY REJECTION vs FREQUENCY
130
120
110
100
90
80
70
60
1 100 1k 10k
Frequency (Hz)
Power Supply Rejection (dB)
LOAD REGULATION
+1.5
+1.0
+0.5
0
−0.5
−1.0
−1.5
–5 0 +5 +10
Output Current (mA)
Output Voltage Change (mV)
RESPONSE TO THERMAL SHOCK
0 15 30 45 60
+600
+300
0
–300
–600
TA =
+25°C
REF102C Immersed in +85°C Fluorinert Bath
Output Voltage Change (μV)
Time (s)
TA = +85°C
QUIESCENT CURRENT vs TEMPERATURE
1.6
1.4
1.2
1.0
0.8
−50 −25 0 +25 +50 +75 +100 +125
Temperature (°C)
Quiescent Current (mA)
−75
REF102 5
SBVS022A www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +15V, unless otherwise noted.
TYPICAL REF102 REFERENCE NOISE
6
4
2
0
−2
−4
−6
Low Frequency Noise (1s/div)
(See Noise Test Circuit)
Noise Voltage (μV)
–
+
OPA227
DUT
Noise Test Circuit.
100μF
15.8kΩ
20Ω 2kΩ
8kΩ
2μF
Oscilloscope
Gain = 100V/V
f − 3 d B = 0.1Hz and 10Hz
THEORY OF OPERATION
Refer to the diagram on the first page of this data sheet. The
10V output is derived from a compensated buried zener
diode DZ1, op amp A1, and resistor network R1 – R6.
Approximately 8.2V is applied to the non-inverting input of A1
by DZ1. R1, R2, and R3 are laser-trimmed to produce an exact
10V output. The zener bias current is established from the
regulated output voltage through R4. R5 allows user-trimming
of the output voltage by providing for small external adjustment
of the amplifier gain. Because the temperature coefficient
(TCR) of of R5 closely matches the TCR of R1, R2 and
R3 , the voltage trim has minimal effect on the reference drift.
The output voltage noise of the REF102 is dominated by the
noise of the zener diode. A capacitor can be connected
between the Noise Reduction pin and ground to form a lowpass
filter with R6 and roll off the high-frequency noise of the
zener.
DISCUSSION
OF PERFORMANCE
The REF102 is designed for applications requiring a precision
voltage reference where both the initial value at room
temperature and the drift over temperature are of importance
to the user. Two basic methods of specifying voltage reference
drift versus temperature are in common usage in the
industry—the “butterfly method” and the “box method.” The
REF102 is specified by the more commonly-used “box
method.” The “box” is formed by the high and low specification
temperatures and a diagonal, the slope of which is equal
to the maximum specified drift.
Since the shape of the actual drift curve is not known, the
vertical position of the box is not known, either. It is, however,
bounded by VUPPER BOUND and VLOWER BOUND (see Figure 1).
Figure 1 uses the REF102CU as an example. It has a drift
specification of 2.5ppm/°C maximum and a specification
temperature range of –25°C to +85°C. The “box” height,
V1 to V2, is 2.75mV.
REF102CU VUPPER BOUND
+10.00275
V1
VNOMINAL
+10.0000
2.75mV
Worst-case
ΔVOUT for
REF102CU
V2
+9.99725
REF102CU VLOWER BOUND
−25 0 +25 +50 +85
Output Voltage (V)
Temperature (°C)
FIGURE 1. REF102CU Output Voltage Drift.
REF102 6
www.ti.com SBVS022A
INSTALLATION AND
OPERATING INSTRUCTIONS
BASIC CIRCUIT CONNECTION
Figure 2 shows the proper connection of the REF102. To
achieve the specified performance, pay careful attention to
layout. A low resistance star configuration will reduce voltage
errors, noise pickup, and noise coupled from the power
supply. Commons should be connected as indicated, being
sure to minimize interconnection resistances.
OPTIONAL OUTPUT VOLTAGE ADJUSTMENT
Optional output voltage adjustment circuits are shown in
Figures 3 and 4. Trimming the output voltage will change the
voltage drift by approximately 0.008ppm/°C per mV of trimmed
voltage. In the circuit in Figure 3, any mismatch in TCR
between the two sections of the potentiometer will also affect
drift, but the effect of the ΔTCR is reduced by a factor of five
by the internal resistor divider. A high quality potentiometer,
with good mechanical stability, such as a cermet, should be
REF102
1μF
Tantalum
+
RL 1 RL 2 RL 3
V+
(1)
2 (2)
(1) (2)
4
6
NOTES: (1) Lead resistances here of up to a few ohms have
negligible effect on performance. (2) A resistance of 0.1Ω in
series with these leads will cause a 1mV error when the load
current is at its maximum of 10mA. This results in a 0.01%
error of 10V.
FIGURE 2. REF102 Installation.
REF102
1μF
Tantalum
+
V+
2
4
20k
Output
Voltage
Adjust
Minimum range (±300mV) and minimal
degradation of drift.
Ω
+10V
5
VTRIM
6
VOUT
FIGURE 3. REF102 Optional Output Voltage Adjust.
REF102
V+
2
4
20k
Output
Voltage
Adjust
Higher resolution, reduced range (typically ±25mV).
Ω
+10V
5
VTRIM
6
VOUT
RS
1M Ω
1μF
Tantalum
+
FIGURE 4. REF102 Optional Output Voltage, Fine Adjust.
used. The circuit in Figure 3 has a minimum trim range of
±300mV. The circuit in Figure 4 has less range but provides
higher resolution. The mismatch in TCR between RS and the
internal resistors can introduce some slight drift. This effect
is minimized if RS is kept significantly larger than the 50kΩ
internal resistor. A TCR of 100ppm/°C is normally sufficient.
REF102 7
SBVS022A www.ti.com
OPTIONAL NOISE REDUCTION
The high-frequency noise of the REF102 is dominated by the
zener diode noise. This noise can be greatly reduced by
connecting a capacitor between the Noise Reduction pin and
ground. The capacitor forms a low-pass filter with R6 (refer to
the figure on page 1) and attenuates the high-frequency
noise generated by the zener. Figure 5 shows the effect of a
1μF noise reduction capacitor on the high-frequency noise of
the REF102. R6 is typically 7kΩ so the filter has a –3dB
frequency of about 22Hz. The result is a reduction in noise
from about 800μVPP to under 200μVPP. If further noise
reduction is required, use the circuit in Figure 14.
APPLICATIONS INFORMATION
High accuracy, extremely low drift, outstanding stability, and
low cost make the REF102 an ideal choice for all instrumentation
and system reference applications. Figures 6 through
14 show a variety of useful application circuits.
6
b) Precision –10V Reference.
a) Resistor Biased –10V Reference
RS
IL
4
REF102
2
−10V Out
See SBVA008 for more detail.
V+ (1.4V to 26V)
1.4mA < < 5.4mA
(5V −IL)
RS
2
6
4
10V
OPA227
R1
2kΩ
C
1000pF
1
−10V Out
−15V
REF102
V+ (1.4V to 26V)
FIGURE 6. –10V Reference Using a) Resistor or b) OPA227.
NO CN
CN = 1μF
FIGURE 5. Effect of 1μF Noise Reduction Capacitor on
Broadband Noise (f–3dB = 1MHz)
REF102 8
www.ti.com SBVS022A
FIGURE 7. +10V Reference With Output Current Boosted to: a) ±20mA, b) +100mA, and c) IL (TYP) +10mA, –5A.
Ω
–
+
OPA227
6
220
+10V
IL
6
+10V
IL
2N2905
6
+10V
4 IL
REF102
V+
a) −20mA < IL < +20mA
(OPA227 also improves transient immunity)
b) −5mA < IL < +100mA c) IL (MAX) = IL (TYP) +10mA
IL (MIN) = IL (TYP) −5mA
VCC − 10V
IL (TYP)
R1 =
2
4
REF102
V+
2
4
REF102
V+
2
–
+
INA126
V
x100
2
4
6
+15V
−5V
–15V
357
1/2W
Ω
2
3
OPA227
–
+
357
1/2W
Ω
28mA
28.5mA
+5V
350 Strain
Gauge Bridge
Ω
5
10
R 8 G
OUT
6
REF102
V+
REF102
6
4
2
3
See SBVA007 for more details.
1
25kΩ
25kΩ 25kΩ
25kΩ
INA105
5
6
+10V
Out
−10V
Out
2
–
+ LOAD
IOUT
Can be connected
to ground or −VS .
V+
REF102
2
6
4
OPA277
R
IOUT = , R ≥ 1kΩ
See SBVA001 for more details and ISINK Circuit.
10V
R
FIGURE 8. Strain Gauge Conditioner for 350Ω Bridge.
FIGURE 9. ±10V Reference. FIGURE 10. Positive Precision Current Source.
REF102 9
SBVS022A www.ti.com
6 +30V
31.4V to 56V
2
4
6
2
6
2
4
+20V
+10V
REF102
4
REF102
REF102
NOTES: (1) REF102s can be stacked to obtain voltages in multiples of 10V.
(2) The supply voltage should be between 10n + 1.4 and 10n + 26, where n is
the number of REF102s. (3) Output current of each REF102 must not exceed
its rated output current of +10, −5mA. This includes the current delivered to
the lower REF102.
–
+
2
4
6 +5V
Out
INA105
2
5
1 3
6
–5V
Out
REF102
V+
–
+
2
4
6 +10V
+5V
INA105
5
1
3
6
2
REF102
V+
Ω
–
+
OPA227
6
2k
+10V
REF102
(2)
2
R
1k
1
4
VOUT 2 Ω
C VREF 1 1μF
C2
1μF
R2
2kΩ
VREF = (V01 + V02 … VOUT N)
N
eN = 5μVPP (f = 0.1Hz to 1MHz)
See SBVA002 for more details.
√N
2
3
Ω
6
2k
REF102
(1)
2
4
VOUT 1
Ω
6
2k
VOUT N
V+
REF102
(N)
2
4
V+
V+
FIGURE 11. Stacked References.
FIGURE 12. ±5V Reference.
FIGURE 13. +5V and +10V Reference.
FIGURE 14. Precision Voltage Reference with Extremely
Low Noise.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
REF102AM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
REF102AP ACTIVE PDIP P 8 50 TBD Call TI Level-NA-NA-NA
REF102AU ACTIVE SOIC D 8 100 TBD CU NIPDAU Level-2-240C-1 YEAR
REF102AU/2K5 ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
REF102BM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
REF102BP ACTIVE PDIP P 8 50 TBD Call TI Level-NA-NA-NA
REF102BU ACTIVE SOIC D 8 100 TBD CU NIPDAU Level-2-240C-1 YEAR
REF102CM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
REF102CP ACTIVE PDIP P 8 50 TBD Call TI Level-NA-NA-NA
REF102CU ACTIVE SOIC D 8 100 TBD CU NIPDAU Level-2-240C-1 YEAR
REF102RM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
REF102SM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Nov-2005
Addendum-Page 1
MECHANICAL DATA
MMBC008 – MARCH 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
LMC (O–MBCY–W8) METAL CYLINDRICAL
4202483/A 03/01
4
3
2
1
8 7
6
5
0.335 (8,51)
0.500 (12,70) MIN
0.021 (0,53)
0.016 (0,41)
0.040 (1,02)
0.305 (7,75) 0.010 (0,25)
0.335 (8,51)
0.165 (4,19)
0.185 (4,70)
0.370 (9,40)
0.040 (1,02) MAX
0.105 (2,67)
0.095 (2,41)
0.140 (3,56)
0.160 (4,06) 0.095 (2,41)
0.105 (2,67)
0.028 (0,71)
0.034 (0,86)
0.045 (1,14)
0.029 (0,74)
ø
ø
ø
ø
Seating Plane
0.200 (5,08)
45°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Leads in true position within 0.010 (0,25) R @ MMC at seating plane.
D. Pin numbers shown for reference only. Numbers may not be marked on package.
E. Falls within JEDEC MO-002/TO-99.
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
0.010 (0,25) M
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Copyright 2005, Texas Instruments Incorporated
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
Direct Upgrades to TL05x, TL07x, and
TL08x BiFET Operational Amplifiers
Greater Than 2× Bandwidth (10 MHz) and
3× Slew Rate (45 V/μs) Than TL08x
On-Chip Offset Voltage Trimming for
Improved DC Performance
Wider Supply Rails Increase Dynamic
Signal Range to ±19 V
description
The TLE208x series of JFET-input operational amplifiers more than double the bandwidth and triple the slew
rate of the TL07x and TL08x families of BiFET operational amplifiers. The TLE208x also have wider
supply-voltage rails, increasing the dynamic-signal range for BiFET circuits to ±19 V. On-chip zener trimming
of offset voltage yields precision grades for greater accuracy in dc-coupled applications. The TLE208x are
pin-compatible with lower performance BiFET operational amplifiers for ease in improving performance in
existing designs.
BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors, without
sacrificing the output drive associated with bipolar amplifiers. This makes these amplifiers better suited for
interfacing with high-impedance sensors or very low level ac signals. They also feature inherently better ac
response than bipolar or CMOS devices having comparable power consumption.
Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to
observe common-mode input-voltage limits and output voltage swing when operating from a single supply. DC
biasing of the input signal is required and loads should be terminated to a virtual ground node at mid-supply.
Texas Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from
single supplies.
The TLE208x are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems,
Texas Instruments LinCMOS families of operational amplifiers (TLC- and TLV-prefix) are recommended.
When moving from BiFET to CMOS amplifiers, particular attention should be paid to slew rate and bandwidth
requirements and output loading.
For BiFET circuits requiring low noise and/or tighter dc precision, the TLE207x offer the same ac response as
the TLE208x with more stringent dc and noise specifications.
PRODUCTION DATA information is current as of publication date. Copyright 2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081 AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
TA
VIOmax
AT 25°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
FORM
(Y)
0°C to 70°C
3 mV TLE2081ACD TLE2081ACP —
6 mV TLE2081CD
— —
TLE2081CP TLE2081Y
40°C to 85°C
3 mV TLE2081AID TLE2081AIP
–6 mV TLE2081ID
— —
TLE2081IP
—
55°C to 125°C
3 mV TLE2081AMFK TLE2081AMJG
–6 mV — TLE2081MFK TLE2081MJG — —
† The D packages are available taped and reeled. Add R suffix to device type (e.g., TLE2081ACDR).
‡ Chip forms are tested at TA = 25°C only.
TLE2082 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
CHIP FORM
(Y)
0°C to 70°C
4 mV TLE2082ACD TLE2082ACP
7 mV TLE2082CD
— —
TLE2082CP
—
40°C to 85°C
4 mV TLE2082AID TLE2082AIP
–TLE2082Y
7 mV TLE2082ID
— —
TLE2082IP
55°C to 125°C
4 mV TLE2082AMD TLE2082AMFK TLE2082AMJG TLE2082AMP
–7 mV TLE2082MD TLE2082MFK TLE2082MJG TLE2082MP —
‡ The D packages are available taped and reeled. Add R suffix to device type (e.g., TLE2082ACDR).
‡ Chip forms are tested at TA = 25°C only.
TLE2084 AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
TA
VIOmax
AT 25°C
SMALL
OUTLINE
(DW)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
FORM
(Y)
0°C to 70°C
4 mV TLE2084ACDW TLE2084ACN —
7 mV TLE2084CDW
— —
TLE2084CN TLE2084Y
55°C to 125°C
4 mV TLE2084AMFK TLE2084AMJ
–7 mV — TLE2084MFK TLE2084MJ — —
† The DW packages are available taped and reeled. Add R suffix to device type (e.g., TLE2084ACDWR).
‡ Chip forms are tested at TA = 25°C only.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
1
2
3
4
8
7
6
5
OFFSET N1
IN –
IN +
VCC–
NC
VCC+
OUT
OFFSET N2
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
NC
VCC+
NC
OUT
NC
NC
IN –
NC
IN +
NC
NC
OFFSET N1
NC
NC NC
NC
V
NC
OFFSET N2 NC
CC –
TLE2081
D, JG, OR P PACKAGE
(TOP VIEW)
TLE2081
FK PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN +
VCC–
VCC+
2OUT
2IN–
2IN+
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN–
NC
NC
1IN–
NC
1IN+
NC
NC
1OUT
NC
NC NC
NC
V
NC
2IN +
CC –
V CC +
TLE2082
D, JG, OR P PACKAGE
(TOP VIEW)
TLE2082
FK PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4IN+
NC
VCC–
NC
3IN+
1IN+
NC
VCC+
NC
2IN+
TLE2084
FK PACKAGE
(TOP VIEW)
1IN –
1OUT
NC
3IN – 4IN –
2 IN –
NC
3OUT
2OUT
4OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN–
1IN+
VCC+
2IN+
2IN–
2OUT
NC
4OUT
4IN–
4IN+
VCC–
3IN+
3IN–
3OUT
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN–
1IN+
VCC+
2IN+
2IN–
2OUT
4OUT
4IN–
4IN+
VCC–
3IN+
3IN–
3OUT
TLE2084
J OR N PACKAGE
(TOP VIEW)
TLE2084
DW PACKAGE
(TOP VIEW)
NC – No internal connection
symbol
+
–
OUT
IN+
IN–
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081Y chip information
This chip, when properly assembled, displays characteristics similar to the TLE2081. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF THE CHIP.
+
–
OUT
IN+
IN–
VCC+
(6)
(3)
(2)
(5)
(1)
(7)
(4)
OFFSET N1
OFFSET N2
VCC–
58
85
(1)
(2)
(4) (5)
(6)
(7)
(8)
(3)
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
TLE2082Y chip information
This chip, when properly assembled, displays characteristics similar to the TLE2082. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF THE CHIP.
+
–
1OUT
1IN+
1IN–
VCC+
(4)
(6)
(3)
(2)
(5)
(1)
(7)
(8)
–
+
2OUT
2IN+
2IN–
VCC–
80
90
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2084Y chip information
This chip, when properly assembled, displays characteristics similar to the TLE2084. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) IS INTERNALLY CONNECTED
TO BACKSIDE OF THE CHIP.
+
–
1OUT
1IN+
1IN–
VCC+
(11)
(6)
(3)
(2)
(5)
(1)
(7)
(4)
–
+
2OUT
2IN+
2IN–
VCC–
+
–
3OUT
3IN+
3IN–
(13)
(10)
(9)
(12)
(8)
(14)
–
+
4OUT
4IN+
4IN–
(2) (1) (14)
(4)
(5)
(6) (7) (8) (9)
(10)
(11)
(12)
(13)
100
150
(3)
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
equivalent schematic (each channel)
Q1
IN–
IN+
Q2 D1
Q7
Q5
Q6
Q9
Q10
C2
R4
Q14
Q4
Q3
R1
Q8
R2
Q11
R3
C1
Q12
D2
Q13
Q15
Q16
Q19
Q20
Q17
R6
VCC–
VCC+
R8
C3
Q18
R7
R5 C4
Q21
C5
R9 R10
Q22 Q26 Q27
Q31 R14
Q29
Q25 C6
Q30
R11
Q23
Q28
Q24
D3
OUT
R13
R12
OFFSET N1
(see Note A)
OFFSET N2
(see Note A)
NOTE A: OFFSET N1 and OFFSET N2 are only availiable on the TLE2081x devices.
ACTUAL DEVICE COMPONENT COUNT
COMPONENT TLE2081 TLE2082 TLE2084
Transistors 33 57 114
Resistors 25 37 74
Diodes 8 5 10
Capacitors 6 11 22
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V
Supply voltage, VCC– (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –19 V
Differential input voltage range, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC+ to VCC–
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC+ to VCC–
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80 mA
Total current into VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA
Total current out of VCC– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
2. Differential voltages are at IN+ with respect to IN–.
3. The output can be shorted to either supply. Temperatures and/or supply voltages must be limited to ensure that the maximum
dissipation rate is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW
DW 1025 mW 8.2 mW/°C 656 mW 533 mW 205 mW
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
N 1150 mW 9.2 mW/°C 736 mW 598 mW 230 mW
P 1000 mW 8.0 mW/°C 640 mW 344 mW 200 mW
recommended operating conditions
C SUFFIX I SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX
Supply voltage, VCC± ±2.25 ±19 ±2.25 ±19 ±2.25 ±19 V
Common mode input voltage VIC
VCC± = ±5 V –0.9 5 –0.8 5 –0.8 5
Common-voltage, V
VCC± = ±15 V –10.9 15 –10.8 15 –10.8 15
Operating free-air temperature, TA 0 70 –40 85 –55 125 °C
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
TLE2081C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2081C TLE2081AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.34 6 0.3 3
mV
VIC = 0, VO = 0, Full range 8 5
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 3.2 29 3.2 29 μV/°C
IIO Input offset current
25°C 5 100 5 100
nA
VIC = 0, VO = 0, Full range 1.4 1.4
IIB Input bias current
IC , O ,
See Figure 4 25°C 15 175 15 175
nA
Full range 5 5
5
5
5
5
25°C
to
to
to
to
VICR
Common-mode input
RS = 50 Ω
–1 –1.9 –1 –1.9
V
voltage range
5
5
Full range
to
g to
–0.9 –0.9
IO = 200 μA
25°C 3.8 4.1 3.8 4.1
–Full range 3.7 3.7
VOM
Maximum positive peak
IO = 2 mA
25°C 3.5 3.9 3.5 3.9
VOM+ V
output voltage swing
–Full range 3.4 3.4
IO = 20 mA
25°C 1.5 2.3 1.5 2.3
–Full range 1.5 1.5
IO = 200 μA
25°C –3.5 –4.2 –3.5 –4.2
Full range –3.4 –3.4
VOM
Maximum negative peak
IO = 2 mA
25°C –3.7 –4.1 –3.7 –4.1
VOM– V
g
output voltage swing
Full range –3.6 –3.6
IO = 20 mA
25°C –1.5 –2.4 –1.5 –2.4
Full range –1.5 –1.5
RL = 600 Ω
25°C 80 91 80 91
Full range 79 79
AVD
Large-signal differential
VO = ± 2 3 V RL = 2 kΩ
25°C 90 100 90 100
dB
g g
voltage amplification
2.3 Full range 89 89
RL = 10 kΩ
25°C 95 106 95 106
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0, Common mode 25°C 11 11
IC pF
,
See Figure 5 Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 70 89 70 89
dB
rejection ratio
IC ICR ,
VO = 0, RS = 50 Ω Full range 68 68
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio(ΔVCC± /ΔVIO)
CC±
VO = 0, RS = 50 Ω Full range 80 80
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2081C TLE2081AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
ICC Supply current VO = 0 No load
25°C 1.35 1.6 2.2 1.35 1.6 2.2
0, mA
Full range 2.2 2.2
IOS
Short-circuit output
VO = 0
VID = 1 V
25°C
–35 –35
mA
current
VID = –1 V
45 45
† Full range is 0°C to 70°C.
TLE2081C operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER TEST CONDITIONS T †
TLE2081C TLE2081AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 35 35
SR+ Positive slew rate
VO(PP) = ±2.3 V,
AVD 1 RL 2 kΩ
Full
range
23 23
V/μs
= –1, = kΩ,
CL = 100 pF, See Figure 1
25°C 38 38
SR– Negative slew rate
F, Full
range
23 23
V/μs
t Settling time
AVD = –1,
2-V step,
To 10 mV
25°C
0.25 0.25
ts , μs
RL = 1 kΩ,
CL = 100 pF To 1 mV
0.4 0.4
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1 Hz to
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
THD + N
Total harmonic distortion
VO(PP) = 5 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 013% 0 013%
plus noise = kHz, = kΩ,
RS = 25 Ω
0.013% 0.013%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 9 4 9 4 MHz
, L ,
CL = 25 pF, See Figure 2
9.4 9.4 BOM
Maximum output-swing VO(PP) = 4 V, AVD = –1,
25°C 2 8 2 8 MHz
g
bandwidth
O(, VD ,
RL = 2 kΩ , CL = 25 pF
2.8 2.8 φ Phase margin at unity gain
VI = 10 mV, RL = 2 kΩ,
φm I 25°C 56° 56°
, L ,
CL = 25 pF, See Figure 2
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
TLE2081C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2081C TLE2081AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.49 6 0.47 3
mV
VIC = 0, VO = 0, Full range 8 5
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 3.2 29 3.2 29 μV/°C
IIO Input offset current
25°C 6 100 6 100
nA
VIC = 0, VO = 0, Full range 1.4 1.4
IIB Input bias current
IC , O ,
See Figure 4 25°C 20 175 20 175
nA
Full range 5 5
15
15
15
15
25°C
to
to
to
to
VICR
Common-mode input
RS = 50 Ω
–11 –11.9 –11 –11.9
V
voltage range
15
15
Full range
to
g to
–10.9 –10.9
IO = 200 μA
25°C 13.8 14.1 13.8 14.1
–Full range 13.7 13.7
VOM
Maximum positive peak
IO = 2 mA
25°C 13.5 13.9 13.5 13.9
VOM+ V
output voltage swing
–Full range 13.4 13.4
IO = 20 mA
25°C 11.5 12.3 11.5 12.3
–Full range 11.5 11.5
IO = 200 μA
25°C –13.8 –14.2 –13.8 –14.2
Full range –13.7 –13.7
VOM
Maximum negative peak
IO = 2 mA
25°C –13.5 –14 –13.5 –14
VOM– V
g
output voltage swing
Full range –13.4 –13.4
IO = 20 mA
25°C –11.5 –12.4 –11.5 –12.4
Full range –11.5 –11.5
RL = 600 Ω
25°C 80 96 80 96
Full range 79 79
AVD
Large-signal differential
VO = ± 10 V RL = 2 kΩ
25°C 90 109 90 109
dB
g g
voltage amplification
Full range 89 89
RL = 10 kΩ
25°C 95 118 95 118
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0,
See Figure 5
Common
mode
25°C 7.5 7.5
i pF
Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 80 98 80 98
dB
rejection ratio
IC ICR ,
VO = 0, RS = 50 Ω Full range 79 79
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC± /ΔVIO)
CC±
VO = 0, RS = 50 Ω Full range 80 81
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2081C TLE2081AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
ICC Supply current VO = 0 No load
25°C 1.35 1.7 2.2 1.35 1.7 2.2
0, mA
Full range 2.2 2.2
I
Short-circuit output
V 0
VID = 1 V
25°C
–30 –45 –30 –45
IOS current VO = mA
VID = –1 V
30 48 30 48
† Full range is 0°C to 70°C.
TLE2081C operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER TEST CONDITIONS T †
TLE2081C TLE2081AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 30 40 30 40
SR+ Positive slew rate
VO(PP) = 10 V, AVD = –1,
RL 2 kΩ CL 100 pF
Full
range
27 27
V/μs
= kΩ, = pF,
See Figure 1
25°C 30 45 30 45
SR– Negative slew rate
Full
range
27 27
V/μs
t Settling time
AVD = –1,
10-V step,
To 10 mV
25°C
0.4 0.4
ts , μs
RL = 1 kΩ,
CL = 100 pF To 1 mV
1.5 1.5
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak
S
See Figure 3 10 kHz
25°C
equivalent input noise
μV
voltage f = 0.1 Hz to
10 Hz
0.6 0.6
I
Equivalent input noise
In VIC = 0 f = 10 kHz 25°C 2 8 2 8 fA/√Hz
q
current
0, 2.8 2.8 fA /√THD + N
Total harmonic
VO(PP) = 20 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 008% 0 008%
distortion plus noise = kHz, = kΩ,
RS = 25 Ω
0.008% 0.008%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 8 10 8 10 MHz
, L ,
CL = 25 pF, See Figure 2
BOM
Maximum output- VO(PP) = 20 V, AVD = –1,
25°C 478 637 478 637 kHz
swing bandwidth
O(, VD ,
RL = 2 kΩ, CL = 25 pF
φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 57° 57°
g y
gain
I L
CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
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TLE2081I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted)
PARAMETER TEST CONDITIONS T †
TLE2081I TLE2081AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.34 6 0.3 3
mV
VIC = 0, VO = 0, Full range 7.6 5.6
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω,
Full range 3.2 29 3.2 29 μV/°C
IIO Input offset current
25°C 5 100 5 100 pA
VIC = 0, VO = 0, Full range 5 5 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 15 175 15 175 pA
Full range 10 10 nA
5
5
5
5
25°C
to
to
to
to
VICR
Common-mode input
RS = 50 Ω
–1 –1.9 –1 –1.9
V
voltage range
5
5
Full range
to
g to
–0.8 –0.8
IO = 200 μA
25°C 3.8 4.1 3.8 4.1
–Full range 3.7 3.7
VOM
Maximum positive peak
IO = 2 mA
25°C 3.5 3.9 3.5 3.9
VOM+ V
output voltage swing
–Full range 3.4 3.4
IO = 20 mA
25°C 1.5 2.3 1.5 2.3
–Full range 1.5 1.5
IO = 200 μA
25°C –3.8 –4.2 –3.8 –4.2
Full range –3.7 –3.7
VOM
Maximum negative peak
IO = 2 mA
25°C –3.5 –4.1 –3.5 –4.1
VOM– V
g
output voltage swing
Full range –3.4 –3.4
IO = 20 mA
25°C –1.5 –2.4 –1.5 –2.4
Full range –1.5 –1.5
RL = 600 Ω
25°C 80 91 80 91
Full range 79 79
AVD
Large-signal differential
VO = ± 2 3 V RL = 2 kΩ
25°C 90 100 90 100
dB
g g
voltage amplification
2.3 Full range 89 89
RL = 10 kΩ
25°C 95 106 95 106
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0,
See Figure 5
Common
mode
25°C 11 11
i pF
Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 70 89 70 89
dB
rejection ratio
IC ICR ,
VO = 0, RS = 50 Ω Full range 68 68
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC±/ΔVIO)
CC± ,
VO = 0, RS = 50 Ω Full range 80 80
† Full range is –40°C to 85°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2081I TLE2081AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
ICC Supply current VO = 0 No load
25°C 1.35 1.6 2.2 1.35 1.6 2.2
0, mA
Full range 2.2 2.2
IOS
Short-circuit output
VO = 0
VID = 1 V
25°C
–35 –35
mA
current
VID = –1 V
45 45
† Full range is –40°C to 85°C.
TLE2081I operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER TEST CONDITIONS T †
TLE2081I TLE2081AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 35 35
SR+ Positive slew rate
VO(PP) = ±2.3 V,
AVD 1 RL 2 kΩ
Full
range
22 22
V/μs
= –1, = kΩ,
CL = 100 pF, See Figure 1
25°C 38 38
SR– Negative slew rate
F, Full
range
22 22
V/μs
t Settling time
AVD = –1,
2-V step,
To 10 mV
25°C
0.25 0.25
ts , μs
RL = 1 kΩ,
CL = 100 pF To 1 mV
0.4 0.4
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent
S
See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
THD + N
Total harmonic distortion
VO(PP) = 5 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 013% 0 013%
plus noise
= kHz, = kΩ,
RS = 25 Ω
0.013% 0.013%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 9 4 9 4 MHz
, L ,
CL = 25 pF, See Figure 2
9.4 9.4 BOM
Maximum output-swing VO(PP) = 4 V, AVD = –1,
25°C 2 8 2 8 MHz
g
bandwidth
O(, VD ,
RL = 2 kΩ , CL = 25 pF
2.8 2.8 φ Phase margin at unity gain
VI = 10 mV, RL = 2 kΩ,
φm I 25°C 56° 56°
, L ,
CL = 25 pF, See Figure 2
† Full range is –40°C to 85°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15
TLE2081I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2081I TLE2081AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.49 6 0.47 3
mV
VIC = 0, VO = 0, Full range 7.6 5.6
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω,
Full range 3.2 29 3.2 29 μV/°C
IIO Input offset current
25°C 6 100 6 100 pA
VIC = 0, VO = 0, Full range 5 5 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 20 175 20 175 pA
Full range 10 10 nA
15
15
15
15
25°C
to
to
to
to
VICR
Common-mode input
RS = 50 Ω
–11 –11.9 –11 –11.9
V
voltage range
15
15
Full range
to
g to
–10.8 –10.8
IO = 200 μA
25°C 13.8 14.1 13.8 14.1
–Full range 13.7 13.7
VOM
Maximum positive peak
IO = 2 mA
25°C 13.5 13.9 13.5 13.9
VOM+ V
output voltage swing
–Full range 13.4 13.4
IO = 20 mA
25°C 11.5 12.3 11.5 12.3
–Full range 11.5 11.5
IO = 200 μA
25°C –13.8 –14.2 –13.8 –14.2
Full range –13.7 –13.7
VOM
Maximum negative peak
IO = 2 mA
25°C –13.5 –14 –13.5 –14
VOM– V
g
output voltage swing
Full range –13.4 –13.4
IO = 20 mA
25°C –11.5 –12.4 –11.5 –12.4
Full range –11.5 –11.5
RL = 600 Ω
25°C 80 96 80 96
Full range 79 79
AVD
Large-signal differential
VO = ± 10 V RL = 2 kΩ
25°C 90 109 90 109
dB
g g
voltage amplification
Full range 89 89
RL = 10 kΩ
25°C 95 118 95 118
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0,
See Figure 5
Common
mode
25°C 7.5 7.5
i pF
Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode
VIC = VICRmin,
VO 0
25°C 80 98 80 98
dB
rejection ratio
= 0,
RS = 50 Ω Full range 79 79
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC±/ΔVIO)
CC± ,
VO = 0, RS = 50 Ω Full range 80 80
† Full range is –40°C to 85°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2081I TLE2081AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
ICC Supply current VO = 0 No load
25°C 1.35 1.7 2.2 1.35 1.7 2.2
0, mA
Full range 2.2 2.2
I
Short-circuit output
V 0
VID = 1 V
25°C
–30 –45 –30 –45
IOS current VO = mA
VID = –1 V
30 48 30 48
† Full range is –40°C to 85°C.
TLE2081I operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER TEST CONDITIONS TA†
TLE2081I TLE2081AI
UNIT
MIN TYP MAX MIN TYP MAX
25°C 30 40 30 40
SR+ Positive slew rate
VO(PP) = ±10 V,
AVD = –1 RL = 2 kΩ
Full
range
24 24
V/μs
1, kΩ,
CL = 100 pF, See Figure 1
25°C 30 45 30 45
SR– Negative slew rate
F, Full
range
24 24
V/μs
t Settling time
AVD = –1,
10-V step,
To 10 mV
25°C
0.4 0.4
ts R μs
L = 1 kΩ,
CL = 100 pF To 1 mV
1.5 1.5
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent See Figure 3 10 kHz
25°C
input noise voltage μV
f = 0.1 Hz to
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
THD + N
Total harmonic distortion
VO(PP) = 20 V, AVD = 10,
plus noise f = 1 kHz, RL = 2 kΩ, 25°C 0 008% 0 008%
RS = 25 Ω
0.008% 0.008%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I L 25°C 8 10 8 10 MHz
CL = 25 pF, See Figure 2 BOM
Maximum output-swing VO(PP) = 20 V, AVD = –1,
25°C 478 637 478 637 kHz
g
bandwidth
O(VD
RL = 2 kΩ, CL = 25 pF φm Phase margin at unity gain
VI = 10 mV, RL = 2 kΩ,
I L 25°C 57° 57°
CL = 25 pF, See Figure 2
† Full range is –40°C to 85°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17
TLE2081M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2081M TLE2081AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.34 6 0.3 3
mV
VIC = 0, VO = 0, Full range 11.2 8.2
αVIO
Temperature coefficient of
input offset voltage
RS = 50Ω
Full range 3.2 29∗ 3.2 29∗ μV/°C
IIO Input offset current
25°C 5 100 5 100 pA
VIC = 0, VO = 0, Full range 20 20 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 15 175 15 175 pA
Full range 65 65 nA
5
5
5
5
25°C
to
to
to
to
VICR
Common-mode input
RS = 50 Ω
–1 –1.9 –1 –1.9
V
voltage range
5
5
Full range
to
g to
–0.8 –0.8
IO = 200 μA
25°C 3.8 4.1 3.8 4.1
–Full range 3.6 3.6
VOM
Maximum positive peak
IO = 2 mA
25°C 3.5 3.9 3.5 3.9
VOM+ V
output voltage swing
–Full range 3.3 3.3
IO = 20 mA
25°C 1.5 2.3 1.5 2.3
–Full range 1.4 1.4
IO = 200 μA
25°C –3.8 –4.2 –3.8 –4.2
Full range –3.6 –3.6
VOM
Maximum negative peak
IO = 2 mA
25°C –3.5 –4.1 –3.5 –4.1
VOM– V
g
output voltage swing
Full range –3.3 –3.3
IO = 20 mA
25°C –1.5 –2.4 –1.5 –2.4
Full range –1.4 –1.4
RL = 600 Ω
25°C 80 91 80 91
Full range 78 78
AVD
Large-signal differential
VO = ± 2 3 V RL = 2 kΩ
25°C 90 100 90 100
dB
g g
voltage amplification
2.3 Full range 88 88
RL = 10 kΩ
25°C 95 106 95 106
Full range 93 93
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0,
See Figure 5
Common
mode
25°C 11 11
i pF
Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 70 89 70 89
dB
rejection ratio
IC ICR ,
VO = 0, RS = 50 Ω Full range 68 68
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC±/ΔVIO)
CC±
VO = 0, RS = 50 Ω Full range 80 80
∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2081M TLE2081AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
ICC Supply current VO = 0 No load
25°C 1.35 1.6 2.2 1.35 1.6 2.2
0, mA
Full range 2.2 2.2
IOS
Short-circuit output
VO = 0
VID = 1 V
25°C
–35 –35
mA
current
VID = –1 V
45 45
† Full range is –55°C to 125°C.
TLE2081M operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER TEST CONDITIONS T †
TLE2081M TLE2081AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 35 35
SR+ Positive slew rate
VO(PP) = ±2.3 V,
AVD 1 RL 2 kΩ
Full
range
20∗ 20∗ V/μs
= –1, = kΩ,
CL = 100 pF, See Figure 1
25°C 38 38
SR– Negative slew rate
F, Full
range
20∗ 20∗ V/μs
t Settling time
AVD = –1,
2-V step,
To 10 mV
25°C
0.25 0.25
ts , μs
RL = 1 kΩ,
CL = 100 pF To 1 mV
0.4 0.4
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak
S
See Figure 3 10 kHz
25°C
equivalent input noise
μV
voltage
f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA /√Hz
THD + N
Total harmonic
VO(PP) = 5 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 013% 0 013%
distortion plus noise = kHz, = kΩ,
RS = 25 Ω
0.013% 0.013%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 9 4 9 4 MHz
, L ,
CL = 25 pF, See Figure 2
9.4 9.4 BOM
Maximum output-swing VO(PP) = 4 V, AVD = –1,
25°C 2 8 2 8 MHz
g
bandwidth
O(, VD ,
RL = 2 kΩ , CL = 25 pF
2.8 2.8 φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 56° 56°
g y
gain
I L
CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19
TLE2081M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2081M TLE2081AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.49 6 0.47 3
mV
VIC = 0, VO = 0, Full range 11.2 8.2
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 3.2 29∗ 3.2 29∗ μV/°C
IIO Input offset current
25°C 6 100 6 100 pA
VIC = 0, VO = 0, Full range 20 20 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 20 175 20 175 pA
Full range 65 65 nA
15
15
15
15
25°C
to
to
to
to
VICR
Common-mode input
RS = 50 Ω
–11 –11.9 –11 –11.9
V
voltage range
15
15
Full range
to
g to
–10.8 –10.8
IO = 200 μA
25°C 13.8 14.1 13.8 14.1
–Full range 13.6 13.6
VOM
Maximum positive peak
IO = 2 mA
25°C 13.5 13.9 13.5 13.9
VOM+ V
output voltage swing
–Full range 13.3 13.3
IO = 20 mA
25°C 11.5 12.3 11.5 12.3
–Full range 11.4 11.4
IO = 200 μA
25°C –13.8 –14.2 –13.8 –14.2
Full range –13.6 –13.6
VOM
Maximum negative peak
IO = 2 mA
25°C –13.5 –14 –13.5 –14
VOM– V
g
output voltage swing
Full range –13.3 –13.3
IO = 20 mA
25°C –11.5 –12.4 –11.5 –12.4
Full range –11.4 –11.4
RL = 600 Ω
25°C 80 96 80 96
Full range 78 78
AVD
Large-signal differential
VO = ± 10 V RL = 2 kΩ
25°C 90 109 90 109
dB
g g
voltage amplification
Full range 88 88
RL = 10 kΩ
25°C 95 118 95 118
Full range 93 93
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0,
See Figure 5
Common
mode
25°C 7.5 7.5
i pF
Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 80 98 80 98
dB
rejection ratio
IC ICR ,
VO = 0, RS = 50 Ω Full range 78 78
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC± /ΔVIO)
CC±
VO = 0, RS = 50 Ω Full range 80 80
∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2081M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)(continued)
PARAMETER TEST CONDITIONS T †
TLE2081M TLE2081AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
ICC Supply current VO = 0 No load
25°C 1.35 1.7 2.2 1.35 1.7 2.2
0, mA
Full range 2.2 2.2
I
Short-circuit output
V 0
VID = 1 V
25°C
–30 –45 –30 –45
IOS current VO = mA
VID = –1 V
30 48 30 48
† Full range is –55°C to 125°C.
TLE2081M operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER TEST CONDITIONS T †
TLE2081M TLE2081AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 30 40 30 40
SR+ Positive slew rate
VO(PP) = 10 V,
AVD 1 RL 2 kΩ
Full
range
22 22
V/μs
= –1, = kΩ,
CL = 100 pF, See Figure 1
25°C 30 45 30 45
SR– Negative slew rate
F, Full
range
22 22
V/μs
t Settling time
AVD = –1,
10-V step,
To 10 mV
25°C
0.4 0.4
ts , μs
RL = 1 kΩ,
CL = 100 pF To 1 mV
1.5 1.5
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak
S
See Figure 3 10 kHz
25°C
equivalent input noise
μV
voltage
f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
THD + N
Total harmonic distortion
VO(PP) = 20 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 008% 0 008%
plus noise = kHz, = kΩ,
RS = 25 Ω
0.008% 0.008%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 8∗ 10 8∗ 10 MHz
, L ,
CL = 25 pF, See Figure 2
BOM
Maximum output-swing VO(PP) = 20 V, AVD = –1,
25°C 478∗ 637 478∗ 637 kHz
g
bandwidth
O(, VD ,
RL = 2 kΩ, CL = 25 pF
φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 57° 57°
g y
gain
I L
CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21
TLE2081Y electrical characteristics at VCC± = ±15 V, TA = 25°C
PARAMETER TEST CONDITIONS
TLE2081Y
UNIT
MIN TYP MAX
VIO Input offset voltage VIC = 0, VO = 0, RS = 50 Ω 0.49 6 mV
IIO Input offset current
VIC = 0 VO = 0 See Figure 4
6 100
pA
IIB Input bias current
0, 0, 20 175
15
15
VICR Common-mode input voltage range RS = 50 Ω
to
ICR g g S to V
–11 11.9
M i iti k
IO = –200 μA 13.8 14.1
VOM+
Maximum positive peak
output voltage swing
IO = –2 mA 13.5 13.9 V
out ut IO = –20 mA 11.5 12.3
M i ti k t t
IO = 200 μA –13.8 –14.2
VOM–
Maximum negative peak output
IO = 2 mA –13.5 –14 V
voltage swing
IO = 20 mA –11.5 –12.4
L i l diff ti l lt
RL = 600 Ω 80 96
AVD
Large-signal differential voltage
amplification
VO = ± 10 V RL = 2 kΩ 90 109 dB
am lification
RL = 10 kΩ 95 118
ri Input resistance VIC = 0 1012 Ω
ci Input capacitance VIC = 0 See Figure 5
Common mode 7.5
0, pF
Differential 2.5
zo Open-loop output impedance f = 1 MHz 80 Ω
CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω 80 98 dB
kSVR
Supply-voltage rejection ratio
(ΔVCC± /ΔVIO)
VCC±= ±5 V to ±15 V, VO = 0, RS = 50 Ω 82 99 dB
ICC Supply current VO = 0, No load 1.35 1.7 2.2 mA
I Short circuit output current V 0
VID = 1 V –30 –45
IOS Short-VO = mA
VID = –1 V 30 48
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2082C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2082C TLE2082AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.9 6 0.65 4
mV
VIC = 0, VO = 0, Full range 8.1 5.1
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 2.3 25 2.3 25 μV/°C
IIO Input offset current
25°C 5 100 5 100 pA
VIC = 0, VO = 0, Full range 1.4 1.4 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 15 175 15 175 pA
Full range 5 5 nA
5 5 5 5
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–1 –1.9 –1 –1.9
V
voltage range
5 5
Full range to to
–0.9 –0.9
IO = 200 μA
25°C 3.8 4.1 3.8 4.1
–Full range 3.7 3.7
VOM
Maximum positive peak
IO = 2 mA
25°C 3.5 3.9 3.5 3.9
VOM+ V
output voltage swing
–Full range 3.4 3.4
IO = 20 mA
25°C 1.5 2.3 1.5 2.3
–Full range 1.5 1.5
IO = 200 μA
25°C –3.8 –4.2 –3.8 –4.2
Full range –3.7 –3.7
VOM
Maximum negative peak
IO = 2 mA
25°C –3.5 –4.1 –3.5 –4.1
VOM– V
g
output voltage swing
Full range –3.4 –3.4
IO = 20 mA
25°C –1.5 –2.4 –1.5 –2.4
Full range –1.5 –1.5
RL = 600 Ω
25°C 80 91 80 91
Full range 79 79
AVD
Large-signal differential
VO = ± 2 3 V RL = 2 kΩ
25°C 90 100 90 100
dB
g g
voltage amplification
2.3 Full range 89 89
RL = 10 kΩ
25°C 95 106 95 106
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci
Input Common mode
VIC = 0 See Figure 5
25°C 11 11
pF
In ut
capacitance Differential
0, 25°C 2.5 2.5
zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω
CMRR Common mode rejection ratio
VIC = VICRmin, 25°C 70 89 70 89
Common-IC ICR dB
,
VO = 0, RS = 50 Ω Full range 68 68
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio(ΔVCC± /ΔVIO)
CC± ,
VO = 0, RS = 50 Ω Full range 80 80
ICC
Supply current
VO = 0 No load
25°C 2.7 2.9 3.9 2.7 2.9 3.9
mA
y
(both channels) 0, Full range 3.9 3.9
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23
TLE2082C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T
TLE2082C TLE2082AC
TA UNIT
MIN TYP MAX MIN TYP MAX
Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
IOS Short circuit output current VO = 0
VID = 1 V
25°C
–35 –35
Short-mA
VID = –1 V
45 45
TLE2082C operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER TEST CONDITIONS T †
TLE2082C TLE2082AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 35 35
SR+ Positive slew rate
VO(PP) = ±2.3 V,
AVD = 1 RL = 2 kΩ
Full
range 22 22
V/μs
–1, kΩ,
= 100 pF, See Figure 1
25°C 38 38
SR– Negative slew rate
CL F, Full
range 22 22
V/μs
t Settling time
AVD = –1,
2-V step,
To 10 mV
25°C
0.25 0.25
ts μs
,
RL = 1 kΩ,
CL = 100 pF To 1 mV
0.4 0.4
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1Hz to
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
THD + N
Total harmonic distortion
VO(PP) = 5 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 013% 0 013%
plus noise
= kHz, = kΩ,
RS = 25 Ω
0.013% 0.013%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 9 4 9 4 MHz
, L ,
CL = 25 pF, See Figure 2
9.4 9.4 BOM
Maximum output-swing VO(PP) = 4 V, AVD = –1,
25°C 2 8 2 8 MHz
g
bandwidth
O(VD
RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 56° 56°
g y
gain
I L
CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2082C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2082C TLE2082AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 1.1 7 0.7 4
mV
VIC = 0, VO = 0, Full range 8.1 5.1
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 2.4 25 2.4 25 μV/°C
IIO Input offset current
25°C 6 100 6 100 pA
VIC = 0, VO = 0, Full range 1.4 1.4 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 20 175 20 175 pA
Full range 5 5 nA
15 15 15 15
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–11 –11.9 –11 –11.9
V
voltage range
15 15
Full range to to
–10.9 –10.9
IO = 200 μA
25°C 13.8 14.1 13.8 14.1
–Full range 13.6 13.6
VOM
Maximum positive peak
IO = 2 mA
25°C 13.5 13.9 13.5 13.9
VOM+ V
output voltage swing
–Full range 13.4 13.4
IO = 20 mA
25°C 11.5 12.3 11.5 12.3
–Full range 11.5 11.5
IO = 200 μA
25°C –13.8 –14.2 –13.8 –14.2
Full range –13.7 –13.7
VOM
Maximum negative peak
IO = 2 mA
25°C –13.5 –14 –13.5 –14
VOM– V
g
output voltage swing
Full range –13.4 –13.4
IO = 20 mA
25°C –11.5 –12.4 –11.5 –12.4
Full range –11.5 –11.5
RL = 600 Ω
25°C 80 96 80 96
Full range 79 79
AVD
Large-signal differential
VO = ± 10 V RL = 2 kΩ
25°C 90 109 90 109
dB
g g
voltage amplification
Full range 89 89
RL = 10 kΩ
25°C 95 118 95 118
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci
Input
capacitance
Common
mode VIC = 0,
See Figure 5
25°C 7.5 7.5
i ca acitance pF
Differential
25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 80 98 80 98
dB
rejection ratio
IC ICR ,
VO = 0, RS = 50 Ω Full range 79 79
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC±/ΔVIO)
CC± ,
VO = 0, RS = 50 Ω Full range 81 81
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25
TLE2082C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T
TLE2082C TLE2082AC
TA UNIT
MIN TYP MAX MIN TYP MAX
Supply current
25°C 2.7 3.1 3.9 2.7 3.1 3.9
ICC
(both channels)
VO = 0, No load Full
range
3.9 3.9
mA
Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
IOS Short circuit output current VO = 0
VID = 1 V
25°C
–30 –45 –30 –45
Short-mA
VID = –1 V
30 48 30 48
TLE2082C operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER TEST CONDITIONS T †
TLE2082C TLE2082AC
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 28 40 28 40
SR+ Positive slew rate
VO(PP) = 10 V, AVD = –1,
RL = 2 kΩ CL = 100 pF
Full
range 25 25
V/μs
kΩ, pF,
Figure 1
25°C 30 45 30 45
SR– Negative slew rate
See Full
range 25 25
V/μs
t Settling time
AVD = –1,
10-V step,
To 10 mV
25°C
0.4 0.4
ts μs
,
RL = 1 kΩ,
CL = 100 pF To 1 mV
1.5 1.5
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
V
Peak-to-peak equivalent
S ,
See Figure 3 10 kHz
25°C
VN(PP) V
Peak to eak input noise voltage f = 0.1 Hz to
0 6 0 6
μV
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
Total harmonic distortion
VO(PP) = 20 V, AVD = 10,
THD + N
kHz kΩ 0 008% 0 008%
plus noise
f = 1 kHz, RL = 2 kΩ,
RS = 25 Ω
25°C 0.008% 0.008%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 8 10 8 10 MHz
, L ,
CL = 25 pF, See Figure 2
BOM
Maximum output-swing VO(PP) = 20 V, AVD = –1,
25°C 478 637 478 637 kHz
g
bandwidth
O(VD
RL = 2 kΩ, CL = 25 pF φ Phase margin at VI = 10 mV, RL = 2 kΩ,
φm 25°C 57° 57°
g
unity gain
I , L ,
CL = 25 pF, See Figure 2
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2082I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted)
PARAMETER TEST CONDITIONS T †
TLE2082I TLE2082AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.9 7 0.65 4
mV
VIC = 0, VO = 0, Full range 8.5 5.5
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 2.4 25 2.4 25 μV/°C
IIO Input offset current
25°C 5 100 5 100 pA
VIC = 0, VO = 0, Full range 5 5 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 15 175 15 175 pA
Full range 10 10 nA
5 5 5 5
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–1 –1.9 –1 –1.9
V
voltage range
5 5
Full range to to
–0.8 –0.8
IO = 200 μA
25°C 3.8 4.1 3.8 4.1
–Full range 3.7 3.7
VOM
Maximum positive peak
IO = 2 mA
25°C 3.5 3.9 3.5 3.9
VOM+ V
output voltage swing
–Full range 3.4 3.4
IO = 20 mA
25°C 1.5 2.3 1.5 2.3
–Full range 1.5 1.5
IO = 200 μA
25°C –3.8 –4.2 –3.8 –4.2
Full range –3.7 –3.7
VOM
Maximum negative peak
IO = 2 mA
25°C –3.5 –4.1 –3.5 –4.1
VOM– V
g
output voltage swing
Full range –3.4 –3.4
IO = 20 mA
25°C –1.5 –2.4 –1.5 –2.4
Full range –1.5 –1.5
RL = 600 Ω
25°C 80 91 80 91
Full range 79 79
AVD
Large-signal differential
VO = ± 2 3 V RL = 2 kΩ
25°C 90 100 90 100
dB
g g
voltage amplification
2.3 Full range 89 89
RL = 10 kΩ
25°C 95 106 95 106
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci
Input Common mode VIC = 0, 25°C 11 11
pF
In ut
capacitance Differential
IC ,
See Figure 5 25°C 2.5 2.5
zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω
CMRR Common mode rejection ratio
VIC = VICRmin, 25°C 70 89 70 89
Common-IC ICR dB
,
VO = 0, RS = 50 Ω Full range 68 68
kSVR
Supply-voltage rejection ratio VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
(ΔVCC±/ΔVIO)
CC± ,
VO = 0, RS = 50 Ω Full range 80 80
ICC
Supply current
VO = 0 No load
25°C 2.7 2.9 3.9 2.7 2.9 3.9
mA
y
(both channels)
0, Full range 3.9 3.9
† Full range is –40°C to 85°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27
TLE2082I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted) (continued)
PARAMETER TEST CONDITIONS T
TLE2082I TLE2082AI
TA UNIT
MIN TYP MAX MIN TYP MAX
Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
IOS Short circuit output current VO = 0
VID = 1 V
25°C
–35 –35
Short-mA
VID = –1 V
45 45
TLE2082I operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER TEST CONDITIONS T †
TLE2082I TLE2082AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 35 35
SR+ Positive slew rate
VO(PP) = ±2.3 V,
AVD = 1 RL = 2 kΩ
Full
range 20 20
V/μs
–1, kΩ,
= 100 pF, See Figure 1
25°C 38 38
SR– Negative slew rate
CL F, Full
range 20 20
V/μs
t Settling time
AVD = –1,
2-V step,
To 10 mV
25°C
0.25 0.25
ts μs
,
RL = 1 kΩ,
CL = 100 pF To 1 mV
0.4 0.4
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent
S
See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
THD + N
Total harmonic distortion
VO(PP) = 5 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 013% 0 013%
plus noise
= kHz, = kΩ,
RS = 25 Ω
0.013% 0.013%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 9 4 9 4 MHz
, L ,
CL = 25 pF, See Figure 2
9.4 9.4 BOM
Maximum output-swing VO(PP) = 4 V, AVD = –1,
25°C 2 8 2 8 MHz
g
bandwidth
O(VD
RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 56° 56°
g y
gain
I L
CL = 25 pF, See Figure 2 † Full range is 40°C to 85°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2082I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2082I TLE2082AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 1.1 7 0.7 4
mV
VIC = 0, VO = 0, Full range 8.5 5.5
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 2.4 25 2.4 25 μV/°C
IIO Input offset current
25°C 6 100 6 100 pA
VIC = 0, VO = 0, Full range 5 5 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 20 175 20 175 pA
Full range 10 10 nA
15 15 15 15
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–11 –11.9 –11 –11.9
V
voltage range
15 15
Full range to to
–10.8 –10.8
IO = 200 μA
25°C 13.8 14.1 13.8 14.1
–Full range 13.7 13.7
VOM
Maximum positive peak
IO = 2 mA
25°C 13.5 13.9 13.5 13.9
VOM+ V
output voltage swing
–Full range 13.4 13.4
IO = 20 mA
25°C 11.5 12.3 11.5 12.3
–Full range 11.5 11.5
IO = 200 μA
25°C –13.8 –14.2 –13.8 –14.2
Full range –13.7 –13.7
VOM
Maximum negative peak
IO = 2 mA
25°C –13.5 –14 –13.5 –14
VOM– V
g
output voltage swing
Full range –13.4 –13.4
IO = 20 mA
25°C –11.5 –12.4 –11.5 –12.4
Full range –11.5 –11.5
RL = 600 Ω
25°C 80 96 80 96
Full range 79 79
AVD
Large-signal differential
VO = ± 10 V RL = 2 kΩ
25°C 90 109 90 109
dB
g g
voltage amplification
Full range 89 89
RL = 10 kΩ
25°C 95 118 95 118
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci
Input
capacitance
Common
mode VIC = 0, See Figure 5
25°C 7.5 7.5
i ca acitance pF
Differential
IC , g
25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 80 98 80 98
dB
rejection ratio
IC ICR ,
VO = 0, RS = 50 Ω Full range 79 79
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC± /ΔVIO)
CC± ,
VO = 0, RS = 50 Ω Full range 80 80
† Full range is –40°C to 85°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29
TLE2082I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T
TLE2082I TLE2082AI
TA UNIT
MIN TYP MAX MIN TYP MAX
Supply current
25°C 2.7 3.1 3.9 2.7 3.1 3.9
ICC
(both channels)
VO = 0, No load Full
range
3.9 3.9
mA
Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
IOS Short circuit output current VO = 0
VID = 1 V
25°C
–30 –45 –30 –45
Short-mA
VID = –1 V
30 48 30 48
TLE2082I operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER TEST CONDITIONS T †
TLE2082I TLE2082AI
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 28 40 28 40
SR+ Positive slew rate
VO(PP) = 10 V, AVD = –1,
RL = 2 kΩ CL = 100 pF
Full
range 22 22
V/μs
kΩ, pF,
Figure 1
25°C 30 45 30 45
SR– Negative slew rate
See Full
range 22 22
V/μs
t Settling time
AVD = –1,
10-V step,
To 10 mV
25°C
0.4 0.4
ts μs
,
RL = 1 kΩ,
CL = 100 pF To 1 mV
1.5 1.5
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent
S
See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
THD + N
Total harmonic distortion
VO(PP) = 20 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 008% 0 008%
plus noise
= kHz, = kΩ,
RS = 25 Ω
0.008% 0.008%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 8 10 8 10 MHz
, L ,
CL = 25 pF, See Figure 2
BOM
Maximum output-swing VO(PP) = 20 V, AVD = –1,
25°C 478 637 478 637 kHz
g
bandwidth
O(VD
RL = 2 kΩ, CL = 25 pF φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 57° 57°
g y
gain
I L
CL = 25 pF, See Figure 2 † Full range is –40°C to 85°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2082M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2082M TLE2082AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 0.9 7 0.65 4
mV
VIC = 0, VO = 0, Full range 9.5 6.5
αVIO
Temperature coefficient
of input offset voltage
RS= 50Ω
Full range 2.3 25∗ 2.3 25∗ μV/°C
IIO Input offset current
25°C 5 100 5 100 pA
VIC = 0, VO = 0, Full range 20 20 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 15 175 15 175 pA
Full range 60 60 nA
5 5 5 5
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–1 –1.9 –1 –1.9
V
voltage range
5 5
Full range to to
–0.8 –0.8
IO = 200 μA
25°C 3.8 4.1 3.8 4.1
–Full range 3.6 3.6
VOM
Maximum positive peak
IO = 2 mA
25°C 3.5 3.9 3.5 3.9
VOM+ V
output voltage swing
–Full range 3.3 3.3
IO = 20 mA
25°C 1.5 2.3 1.5 2.3
–Full range 1.4 1.4
IO = 200 μA
25°C –3.8 –4.2 –3.8 –4.2
Full range –3.6 –3.6
VOM
Maximum negative peak
IO = 2 mA
25°C –3.5 –4.1 –3.5 –4.1
VOM– V
g
output voltage swing
Full range –3.3 –3.3
IO = 20 mA
25°C –1.5 –2.4 –1.5 –2.4
Full range –1.4 –1.4
RL = 600 Ω
25°C 80 91 80 91
Full range 78 78
AVD
Large-signal differential
VO = ± 2 3 V RL = 2 kΩ
25°C 90 100 90 100
dB
g g
voltage amplification
2.3 Full range 88 88
RL = 10 kΩ
25°C 95 106 95 106
Full range 93 93
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci
Input
capaci
Common mode
VIC = 0 See Figure 5
25°C 11 11
capaci- pF
tance Differential
0, 25°C 2.5 2.5
zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω
CMRR Common mode rejection ratio
VIC = VICRmin, 25°C 70 89 70 89
Common-IC ICR dB
,
VO = 0, RS = 50 Ω Full range 68 68
kSVR
Supply-voltage rejection ratio VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
(ΔVCC± /ΔVIO)
CC± ,
VO = 0, RS = 50 Ω Full range 80 80
∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31
TLE2082M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2082M TLE2082AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
Supply current
25°C 2.7 2.9 3.6 2.7 2.9 3.6
ICC
(both channels)
VO = 0, No load Full
range
3.6 3.6
mA
Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
IOS Short circuit output current VO = 0
VID = 1 V
25°C
–35 –35
Short-mA
VID = –1 V
45 45
† Full range is –55°C to 125°C.
TLE2082M operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER TEST CONDITIONS T †
TLE2082M TLE2082AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 35 35
SR+ Positive slew rate
VO(PP) = ±2.3 V,
1 kΩ
Full
range 18∗ 18∗ V/μs
AVD = –1, RL = 2 kΩ,
CL = 100 pF, See Figure 1
25°C 38 38
SR– Negative slew rate
F, Full
range 18∗ 18∗ V/μs
t Settling time
AVD = –1,
2-V step,
To 10 mV
25°C
0.25 0.25
ts μs
,
RL = 1 kΩ,
CL = 100 pF To 1 mV
0.4 0.4
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent
S
See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
THD + N
Total harmonic
VO(PP) = 5 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 013% 0 013%
distortion plus noise
= kHz, = kΩ,
RS = 25 Ω
0.013% 0.013%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 9 4 9 4 MHz
, L ,
CL = 25 pF, See Figure 2
9.4 9.4 BOM
Maximum output-swing VO(PP) = 4 V, AVD = –1,
25°C 2 8 2 8 MHz
g
bandwidth
O(VD
RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 56° 56°
g y
gain
I L
CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2082M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2082M TLE2082AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C 1.1 7 0.7 4
mV
VIC = 0, VO = 0, Full range 9.5 6.5
αVIO
Temperature coefficient
of input offset voltage
RS= 50 Ω
Full range 2.4 25∗ 2.4 25∗ μV/°C
IIO Input offset current
25°C 6 100 6 100 pA
VIC = 0, VO = 0, Full range 20 20 nA
IIB Input bias current
IC , O ,
See Figure 4 25°C 20 175 20 175 pA
Full range 65 65 nA
15 15 15 15
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–11 –11.9 –11 –11.9
V
voltage range
15 15
Full range to to
–10.8 –10.8
IO = 200 μA
25°C 13.8 14.1 13.8 14.1
–Full range 13.6 13.6
VOM
Maximum positive peak
IO = 2 mA
25°C 13.5 13.9 13.5 13.9
VOM+ V
output voltage swing
–Full range 13.3 13.3
IO = 20 mA
25°C 11.5 12.3 11.5 12.3
–Full range 11.4 11.4
IO = 200 μA
25°C –13.8 –14.2 –13.8 –14.2
Full range –13.6 –13.6
VOM
Maximum negative peak
IO = 2 mA
25°C –13.5 –14 –13.5 –14
VOM– V
g
output voltage swing
Full range –13.3 –13.3
IO = 20 mA
25°C –11.5 –12.4 –11.5 –12.4
Full range –11.4 –11.4
RL = 600 Ω
25°C 80 96 80 96
Full range 78 78
AVD
Large-signal differential
VO = ± 10 V RL = 2 kΩ
25°C 90 109 90 109
dB
g g
voltage amplification
Full range 88 88
RL = 10 kΩ
25°C 95 118 95 118
Full range 93 93
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci
Input
capacitance
Common
mode VIC = 0, See Figure 5
25°C 7.5 7.5
i ca acitance pF
Differential
IC , g
25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode rejection VIC = VICRmin, 25°C 80 98 80 98
dB
j
ratio
IC ICR ,
VO = 0, RS = 50 Ω Full range 78 78
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC±/ΔVIO)
CC± ,
VO = 0, RS = 50 Ω Full range 80 80
∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33
TLE2082M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2082M TLE2082AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
Supply current
25°C 2.7 3.1 3.6 2.7 3.1 3.6
ICC
(both channels)
VO = 0, No load Full
range
3.6 3.6
mA
Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
I
Short-circuit output
V 0
VID = 1 V
25°C
–30 –45 –30 –45
IOS current VO = mA
VID = –1 V
30 48 30 48
† Full range is –55°C to 125°C.
TLE2082M operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER TEST CONDITIONS T †
TLE2082M TLE2082AM
TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 28 40 28 40
SR+ Positive slew rate
VO(PP) = 10 V, AVD = –1,
kΩ pF
Full
range 20 20
V/μs
RL = 2 kΩ, CL = 100 pF,
See Figure 1
25°C 30 45 30 45
SR– Negative slew rate
Full
range 20 20
V/μs
t Settling time
AVD = –1,
10-V step,
To 10 mV
25°C
0.4 0.4
ts μs
,
RL = 1 kΩ,
CL = 100 pF To 1 mV
1.5 1.5
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent
S
See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz
Total harmonic distortion
VO(PP) = 20 V, AVD = 10,
THD + N
kHz kΩ 0 008% 0 008%
plus noise
f = 1 kHz, RL = 2 kΩ,
RS = 25 Ω
25°C 0.008% 0.008%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 8∗ 10 8∗ 10 MHz
, L ,
CL = 25 pF, See Figure 2
BOM
Maximum output-swing VO(PP) = 20 V, AVD = –1,
25°C 478∗ 637 478∗ 637 kHz
g
bandwidth
O(VD
RL = 2 kΩ, CL = 25 pF φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 57° 57°
g y
gain
I L
CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2082Y electrical characteristics at VCC± = ±15 V, TA = 25°C
PARAMETER TEST CONDITIONS
TLE2082Y
UNIT
MIN TYP MAX
VIO Input offset voltage VIC = 0, VO = 0, RS = 50 Ω 1.1 6 mV
IIO Input offset current
VIC = 0 VO = 0 See Figure 4
6 100 pA
IIB Input bias current
0, 0, 20 175 pA
15 15
VICR Common-mode input voltage range RS = 50 Ω to to V
–11 11.9
IO = –200 μA 13.8 14.1
VOM+ Maximum positive peak output voltage swing IO = –2 mA 13.5 13.9 V
IO = –20 mA 11.5 12.3
IO = 200 μA –13.8 –14.2
VOM– Maximum negative peak output voltage swing IO = 2 mA –13.5 –14 V
IO = 20 mA –11.5 –12.4
RL = 600 Ω 80 96
AVD Large-signal differential voltage amplification VO = ± 10 V RL = 2 kΩ 90 109 dB
RL = 10 kΩ 95 118
ri Input resistance VIC = 0 1012 Ω
ci Input capacitance
Common mode
VO = 0 See Figure 5
7.5
pF
Differential
0, 2.5
zo Open-loop output impedance f = 1 MHz 80 Ω
CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω 80 98 dB
kSVR Supply-voltage rejection ratio (ΔVCC± /ΔVIO)
VCC± = ±5 V to ±15 V, VO = 0,
RS = 50 Ω 82 99 dB
ICC Supply current (both channels) VO = 0, No load 2.7 3.1 3.9 mA
IOS Short circuit output current VO = 0
VID = 1 V –30 –45
Short-mA
VID = –1 V 30 48
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35
TLE2084C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2084C TLE2084AC
TA UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C –1.6 7 –0.5 4
mV
VIC = 0, VO = 0, Full range 9.1 6.1
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 10.1 30 10.1 30 μV/°C
IIO Input offset current
25°C 15 100 15 100 pA
VIC = 0, VO = 0, Full range 1.4 1.4 nA
IIB Input bias current
IC O
See Figure 4 25°C 20 175 20 175 pA
Full range 5 5 nA
25°C
5
to
5
to
5
to
5
to
VICR
Common-mode input
RS = 50 Ω
–1
–1.9
–1
–1.9
voltage range V
Full range
5
to
5
to
–0.9
–0.9
IO = 200 μA
25°C 3.8 4.1 3.8 4.1
–Full range 3.7 3.7
VOM
Maximum positive peak
IO = 2 mA
25°C 3.5 3.9 3.5 3.9
VOM+ output voltage swing –V
Full range 3.4 3.4
IO = 20 mA
25°C 1.5 2.3 1.5 2.3
–Full range 1.5 1.5
IO = 200 μA
25°C –3.8 –4.2 –3.8 –4.2
Full range –3.7 –3.7
VOM
Maximum negative peak
IO = 2 mA
25°C –3.5 –4.1 –3.5 –4.1
VOM– V
g
output voltage swing Full range –3.4 –3.4
IO = 20 mA
25°C –1.5 –2.4 –1.5 –2.4
Full range –1.5 –1.5
RL = 600 Ω
25°C 80 91 80 91
Full range 79 79
AVD
Large-signal differential
VO = ± 2 3 V RL = 2 kΩ
25°C 90 100 90 100
dB
g g
voltage amplification 2.3 Full range 89 89
RL = 10 kΩ
25°C 95 106 95 106
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0, Common mode 25°C 11 11
IC pF
See Figure 5 Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 70 89 70 89
rejection ratio dB
IC ICR
VO = 0, RS = 50 Ω Full range 68 68
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC± /ΔVIO)
CC±
VO = 0, RS = 50 Ω Full range 80 80
ICC
Supply current
VO = 0 No load
25°C 5.2 6.3 7.5 5.2 6.3 7.5
mA
y
( four amplifiers ) 0, Full range 7.5 7.5
ax Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2084C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2084C TLE2084AC
TA UNIT
MIN TYP MAX MIN TYP MAX
I
Short-circuit output
V 0
VID = 1 V
25°C
–35 –35
IOS current VO = mA
VID = –1 V
45 45
† Full range is 0°C to 70°C.
TLE2084C operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER TEST CONDITIONS T †
TLE2084C TLE2084AC
TA UNIT
MIN TYP MAX MIN TYP MAX
25°C 35 35
SR+ Positive slew rate
VO(PP) = ±2.3 V,
1 kΩ
Full
range
22 22
V/μs
AVD = –1, RL = 2 kΩ,
CL = 100 pF, See Figure 1
25°C 38 38
SR– Negative slew rate
F, Full
range
22 22
V/μs
t Settling time
AVD = –1,
2-V step,
To 10 mV
25°C
0.25 0.25
ts R μs
L = 1 kΩ,
CL = 100 pF To 1 mV
0.4 0.4
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent See Figure 3 10 kHz
25°C
input noise voltage μV
f = 0.1Hz to
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA /√Hz
THD + N
Total harmonic distortion
VO(PP) = 5 V, AVD = 10,
f = 1 kHz RL = 2 kΩ 25°C 0 013% 0 013% plus noise
kHz, kΩ,
RS = 25 Ω
0.013% 0.013%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I L 25°C 9 4 9 4 MHz
CL = 25 pF, See Figure 2 9.4 9.4 BOM
Maximum output-swing VO(PP) = 4 V, AVD = –1,
25°C 2 8 2 8 MHz
g
bandwidth
O(VD
RL = 2 kΩ , CL = 25 pF 2.8 2.8 φm
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
25°C 56° 56°
g y
gain
I L
CL = 25 pF, See Figure 2
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37
TLE2084C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2084C TLE2084AC
TA UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C –1.6 7 –0.5 4
mV
VIC = 0, VO = 0, Full range 9.1 6.1
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 10.1 30 10.1 30 μV/°C
IIO Input offset current
25°C 15 100 15 100 pA
VIC = 0, VO = 0, Full range 1.4 1.4 nA
IIB Input bias current
IC O
See Figure 4 25°C 25 175 25 175 pA
Full range 5 5 nA
15 15 15 15
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–11 –11.9 –11 –11.9
voltage range V
15 15
Full range to to
–10.9 –10.9
IO = 200 μA
25°C 13.8 14.1 13.8 14.1
–Full range 13.7 13.7
VOM
Maximum positive peak
IO = 2 mA
25°C 13.5 13.9 13.5 13.9
VOM+ output voltage swing –V
Full range 13.4 13.4
IO = 20 mA
25°C 11.5 12.3 11.5 12.3
–Full range 11.5 11.5
IO = 200 μA
25°C –13.8 –14.2 –13.8 –14.2
M i ti
Full range –13.7 –13.7
VOM
Maximum negative
peak output voltage IO = 2 mA
25°C –13.7 –14 –13.7 –14
VOM– eak out ut V
swing
Full range –13.6 –13.6
IO = 20 mA
25°C –11.5 –12.4 –11.5 –12.4
Full range –11.5 –11.5
RL = 600 Ω
25°C 80 96 80 96
Full range 79 79
AVD
Large-signal differential
VO = ± 10 V RL = 2 kΩ
25°C 90 109 90 109
dB
g g
voltage amplification Full range 89 89
RL = 10 kΩ
25°C 95 118 95 118
Full range 94 94
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0, Common mode 25°C 7.5 7.5
IC pF
See Figure 5 Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 80 98 80 98
rejection ratio dB
IC ICR
VO = 0, RS = 50 Ω Full range 79 79
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC±/ΔVIO)
CC±
VO = 0, RS = 50 Ω Full range 81 81
ICC
Supply current
VO = 0 No load
25°C 5.2 6.5 7.5 5.2 6.5 7.5
mA
y
( four amplifiers ) 0, Full range 7.5 7.5
ax Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
† Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2084C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T †
TLE2084C TLE2084AC
TA UNIT
MIN TYP MAX MIN TYP MAX
I
Short-circuit output
V 0
VID = 1 V
25°C
–30 –45 –30 –45
IOS current VO = mA
VID = –1 V
30 48 30 48
† Full range is 0°C to 70°C.
TLE2084C operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER TEST CONDITIONS T †
TLE2084C TLE2084AC
TA UNIT
MIN TYP MAX MIN TYP MAX
25°C 25 40 25 40
SR+ Positive slew rate
VO(PP) = 10 V, AVD = –1,
kΩ pF
Full
range
22 22
V/μs
RL = 2 kΩ, CL = 100 pF,
See Figure 1
25°C 30 45 30 45
SR– Negative slew rate
Full
range
25 25
V/μs
t Settling time
AVD = –1,
10-V step,
To 10 mV
25°C
0.4 0.4
ts , μs
RL = 1 kΩ,
CL = 100 pF To 1 mV
1.5 1.5
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
V
Peak-to-peak equivalent
S ,
See Figure 3 10 kHz
25°C
VN(PP) V
Peak to eak input noise voltage f = 0.1 Hz to
0 6 0 6
μV
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA /√Hz
THD + N
Total harmonic distortion
VO(PP) = 20 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 008% 0 008%
plus noise
= kHz, = kΩ,
RS = 25 Ω
0.008% 0.008%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 8 10 8 10 MHz
, L ,
CL = 25 pF, See Figure 2
BOM
Maximum output-swing VO(PP) = 20 V, AVD = –1,
25°C 478 637 478 637 kHz
g
bandwidth
O(, VD ,
RL = 2 kΩ, CL = 25 pF
φ
Phase margin at VI = 10 mV, RL = 2 kΩ,
φm 25°C 57° 57°
g
unity gain
I L
CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39
TLE2084M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2084M TLE2084AM
TA UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C –1.6 7 –0.5 4
mV
VIC = 0, VO = 0, Full range 12.5 9.5
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 10.1 30∗ 10.1 30∗ μV/°C
IIO Input offset current
25°C 15 100 15 100 pA
VIC = 0, VO = 0, Full range 20 20 nA
IIB Input bias current
IC O
See Figure 4 25°C 20 175 20 175 pA
Full range 65 65 nA
5 5 5 5
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–1 –1.9 –1 –1.9
voltage range V
5 5
Full range to to
–0.8 –0.8
IO = 200 μA
25°C 3.8 4.1 3.8 4.1
–Full range 3.6 3.6
VOM
Maximum positive peak
IO = 2 mA
25°C 3.5 3.9 3.5 3.9
VOM+ output voltage swing –V
Full range 3.3 3.3
IO = 20 mA
25°C 1.5 2.3 1.5 2.3
–Full range 1.4 1.4
IO = 200 μA
25°C –3.8 –4.2 –3.8 –4.2
M i ti
Full range –3.6 –3.6
VOM
Maximum negative
peak output voltage IO = 2 mA
25°C –3.5 –4.1 –3.5 –4.1
VOM– eak out ut V
swing
Full range –3.3 –3.3
IO = 20 mA
25°C –1.5 –2.4 –1.5 –2.4
Full range –1.4 –1.4
RL = 600 Ω
25°C 80 91 80 91
Full range 78 78
AVD
Large-signal differential
VO = ± 2 3 V RL = 2 kΩ
25°C 90 100 90 100
dB
g g
voltage amplification 2.3 Full range 88 88
RL = 10 kΩ
25°C 95 106 95 106
Full range 93 93
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0, Common mode 25°C 11 11
IC pF
See Figure 5 Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 70 89 70 89
rejection ratio dB
IC ICR
VO = 0, RS = 50 Ω Full range 68 68
kSVR
Supply-voltage rejec- VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
tion ratio (ΔVCC± /ΔVIO)
CC±
VO = 0, RS = 50 Ω Full range 80 80
ICC
Supply current
VO = 0 No load
25°C 5.2 6.3 7.5 5.2 6.3 7.5
mA
y
( four amplifiers ) 0, Full range 7.5 7.5
ax Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
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40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2084M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T
TLE2084M TLE2084AM
TA UNIT
MIN TYP MAX MIN TYP MAX
I
Short-circuit output
V 0
VID = 1 V
25°C
–35 –35
IOS current VO = mA
VID = –1 V
45 45
TLE2084M operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER TEST CONDITIONS T †
TLE2084M TLE2084AM
TA UNIT
MIN TYP MAX MIN TYP MAX
25°C 35 35
SR+ Positive slew rate
VO(PP) = ±2.3 V,
AVD 1 RL 2 kΩ
Full
range
18∗ 18∗ V/μs
= –1, = kΩ,
CL = 100 pF, See Figure 1
25°C 38 38
SR– Negative slew rate
F, Full
range
18∗ 18∗ V/μs
t Settling time
AVD = –1,
2-V step,
To 10 mV
25°C
0.25 0.25
ts , μs
RL = 1 kΩ,
CL = 100 pF To 1 mV
0.4 0.4
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent
S
See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
In
Equivalent input noise
current
VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA /√Hz
THD + N
Total harmonic distortion
VO(PP) = 5 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 013% 0 013%
plus noise
= kHz, = kΩ,
RS = 25 Ω
0.013% 0.013%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 9 4 9 4 MHz
, L ,
CL = 25 pF, See Figure 2
9.4 9.4 BOM
Maximum output-swing VO(PP) = 4 V, AVD = –1,
25°C 2 8 2 8 MHz
g
bandwidth
O(, VD ,
RL = 2 kΩ , CL = 25 pF
2.8 2.8 φ
Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 56° 56°
g y
gain
I L
CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41
TLE2084M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS T †
TLE2084M TLE2084AM
TA UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage
25°C –1.6 7 –0.5 4
mV
VIC = 0, VO = 0, Full range 12.5 7.5
αVIO
Temperature coefficient
of input offset voltage
RS = 50 Ω
Full range 10.1 30∗ 10.1 30∗ μV/°C
IIO Input offset current
25°C 15 100 15 100 pA
VIC = 0, VO = 0, Full range 20 20 nA
IIB Input bias current
IC O
See Figure 4 25°C 25 175 25 175 pA
Full range 65 65 nA
15 15 15 15
25°C to to to to
VICR
Common-mode input
RS = 50 Ω
–11 –11.9 –11 –11.9
voltage range V
15 15
Full range to to
–10.8 –10.8
IO = 200 μA
25°C 13.8 14.1 13.8 14.1
–Full range 13.6 13.6
VOM
Maximum positive peak
IO = 2 mA
25°C 13.5 13.9 13.5 13.9
VOM+ output voltage swing –V
Full range 13.3 13.3
IO = 20 mA
25°C 11.5 12.3 11.5 12.3
–Full range 11.4 11.4
IO = 200 μA
25°C –13.8 –14.2 –13.8 –14.2
Full range –13.6 –13.6
VOM
Maximum negative peak
IO = 2 mA
25°C –13.5 –14 –13.5 –14
VOM– V
g
output voltage swing Full range –13.3 –13.3
IO = 20 mA
25°C –11.5 –12.4 –11.5 –12.4
Full range –11.4 –11.4
RL = 600 Ω
25°C 80 96 80 96
Full range 78 78
AVD
Large-signal differential
VO = ± 10 V RL = 2 kΩ
25°C 90 109 90 109
dB
g g
voltage amplification Full range 88 88
RL = 10 kΩ
25°C 95 118 95 118
Full range 93 93
ri Input resistance VIC = 0 25°C 1012 1012 Ω
ci Input capacitance
VIC = 0, Common mode 25°C 7.5 7.5
IC pF
See Figure 5 Differential 25°C 2.5 2.5
zo
Open-loop output
impedance
f = 1 MHz 25°C 80 80 Ω
CMRR
Common-mode VIC = VICRmin, 25°C 80 98 80 98
rejection ratio dB
IC ICR
VO = 0, RS = 50 Ω Full range 78 78
kSVR
Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99
dB
y g j
ratio (ΔVCC±/ΔVIO)
CC±
VO = 0, RS = 50 Ω Full range 80 80
ICC
Supply current
VO = 0 No load
25°C 5.2 6.5 7.5 5.2 6.5 7.5
mA
y
( four amplifiers ) 0, Full range 7.5 7.5
ax Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB
∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2084M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS T
TLE2084M TLE2084AM
TA UNIT
MIN TYP MAX MIN TYP MAX
I
Short-circuit output
V 0
VID = 1 V
25°C
–30 –45 –30 –45
IOS current VO = mA
VID = –1 V
30 48 30 48
TLE2084M operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER TEST CONDITIONS T †
TLE2084M TLE2084AM
TA UNIT
MIN TYP MAX MIN TYP MAX
25°C 25 40 25 40
SR+ Positive slew rate
VO(PP) = 10 V,
AVD 1 RL 2 kΩ
Full
range
17 17
V/μs
= –1, = kΩ,
CL = 100 pF, See Figure 1
25°C 30 45 30 45
SR– Negative slew rate
F, Full
range
20 20
V/μs
t Settling time
AVD = –1,
10-V step,
To 10 mV
25°C
0.4 0.4
ts , μs
RL = 1 kΩ,
CL = 100 pF To 1 mV
1.5 1.5
V
Equivalent input noise f = 10 Hz
25°C
28 28
Vn nV/√Hz
q
voltage f = 10 kHz
11.6 11.6
RS = 20 Ω, f = 10 Hz to
6 6
VN(PP)
Peak-to-peak equivalent
S
See Figure 3 10 kHz
25°C
μV
q
input noise voltage f = 0.1 Hz to
0 6 0 6
10 Hz
0.6 0.6
I
Equivalent input noise
In VIC = 0 f = 10 kHz 25°C 2 8 2 8 fA/√Hz
q
current
0, 2.8 2.8 fA /√THD + N
Total harmonic distortion
VO(PP) = 20 V, AVD = 10,
f 1 kHz RL 2 kΩ 25°C 0 008% 0 008%
plus noise
= kHz, = kΩ,
RS = 25 Ω
0.008% 0.008%
B1 Unity gain bandwidth
VI = 10 mV, RL = 2 kΩ,
Unity-I 25°C 8∗ 10 8∗ 10 MHz
, L ,
CL = 25 pF, See Figure 2
BOM
Maximum output-swing VO(PP) = 20 V, AVD = –1,
25°C 478∗ 637 478∗ 637 kHz
g
bandwidth
O(, VD ,
RL = 2 kΩ, CL = 25 pF
φ Phase margin at unity VI = 10 mV, RL = 2 kΩ,
φm 25°C 57° 57°
g y
gain
I , L ,
CL = 25 pF, See Figure 2
∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested.
† Full range is –55°C to 125°C.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43
TLE2084Y electrical characteristics at VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS
TLE2084Y
UNIT
MIN TYP MAX
VIO Input offset voltage
VIC = 0, VO = 0,
RS = 50 Ω 7 mV
IIO Input offset current VIC = 0, VO = 0, 15 100 pA
IIB Input bias current
IC O
See Figure 4 25 175 pA
15 15
VICR Common-mode input voltage range RS = 50 Ω to to V
–11 11.9
IO = –200 μA 13.8 14.1
VOM+ Maximum positive peak output voltage swing IO = –2 mA 13.5 13.9 V
IO = –20 mA 11.5 12.3
IO = 200 μA –13.8 –14.2
VOM– Maximum negative peak output voltage swing IO = 2 mA –13.5 –14 V
IO = 20 mA –11.5 –12.4
RL = 600 Ω 80 96
AVD Large-signal differential voltage amplification VO = ± 10 V RL = 2 kΩ 90 109 dB
RL = 10 kΩ 95 118
ri Input resistance VIC = 0 1012 Ω
ci Input capacitance
VIC = 0, Common mode 7.5
IC pF
See Figure 5 Differential 2.5
zo Open-loop output impedance f = 1 MHz 80 Ω
CMRR Common-mode rejection ratio
VIC = VICRmin, VO = 0,
RS = 50 Ω 80 98 dB
kSVR Supply-voltage rejection ratio (ΔVCC± /ΔVIO)
VCC± = ±5 V to ±15 V, VO = 0,
RS = 50 Ω 82 99 dB
ICC Supply current ( four amplifiers ) VO = 0, No load 5.2 6.5 7.5 mA
IOS Short circuit output current VO = 0
VID = 1 V –30 –45
Short-mA
VID = –1 V 30 48
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
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44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
–
+
2 kΩ
2 kΩ
RL CL†
VO
VCC+
VCC+
VI –
+
10 kΩ
VO
CL†
100Ω
RL
VCC+
VCC+
VI
† Includes fixture capacitance † Includes fixture capacitance
Figure 1. Slew-Rate Test Circuit Figure 2. Unity-Gain Bandwidth
and Phase-Margin Test Circuit
† Includes fixture capacitance
–
+
–
+
2 kΩ
VCC+ VCC+
VO VO
VCC–
RS RS VCC–
Ground Shield
Picoammeters
Figure 3. Noise-Voltage Test Circuit Figure 4. Input-Bias and Offset-
Current Test Circuit
–
+
VCC+
VO
VCC–
IN–
IN+
Cic Cic
Cid
Figure 5. Internal Input Capacitance
typical values
Typical values presented in this data sheet represent the median (50% point) of device parametric performance.
input bias and offset current
At the picoampere bias-current level typical of the TLE208x and TLE208xA, accurate measurement of the bias
becomes difficult. Not only does this measurement require a picoammeter, but test socket leakages can easily
exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses
a two-step process. The socket leakage is measured using picoammeters with bias voltages applied but with
no device in the socket. The device is then inserted in the socket and a second test is performed that measures
both the socket leakage and the device input bias current. The two measurements are then subtracted
algebraically to determine the bias current of the device.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 6, 7, 8
αVIO Input offset voltage temperature coefficient Distribution 9, 10, 11
IIO Input offset current vs Free-air temperature 12 – 15
IIB Input bias current
vs Free-air temperature 12 – 15
vs Supply voltage 16
VICR Common-mode input voltage range vs Free-air temperature 17
VID Differential input voltage vs Output voltage 18, 19
vs Output current 20, 21
VOM+ Maximum positive peak output voltage vs Free-air temperature
,
OM+ g 24, 25
vs Supply voltage 26
vs Output current 22, 23
VOM– Maximum negative peak output voltage vs Free-air temperature
,
OM g g 24, 25
vs Supply voltage 26
VO(PP) Maximum peak-to-peak output voltage vs Frequency 27
VO Output voltage vs Settling time 28
AVD Large signal differential voltage amplification
vs Load resistance 29
Large-vs Free-air temperature 30, 31
AVD Small-signal differential voltage amplification vs Frequency 32, 33
CMRR Common mode rejection ratio
vs Frequency 34
Common-q y
vs Free-air temperature 35
kSVR Supply voltage rejection ratio
vs Frequency 36
Supply-q y
vs Free-air temperature 37
vs Supply voltage 38, 39, 40
ICC Supply current
y g
vs Free-air temperature
, ,
CC y 41, 42, 43
vs Differential input voltage 44 – 49
vs Supply voltage 50
IOS Short-circuit output current
y g
OS vs Elapsed time 51
vs Free-air temperature 52
vs Free-air temperature 53, 54
SR Slew rate vs Load resistance
,
55
vs Differential input voltage 56
Vn Equivalent input noise voltage vs Frequency 57
V Input referred noise voltage
vs Noise bandwidth frequency 58
Vn Input-q y
Over a 10-second time interval 59
Third-octave spectral noise density vs Frequency bands 60
THD +N Total harmonic distortion plus noise vs Frequency 61, 62
B1 Unity-gain bandwidth vs Load capacitance 63
Gain bandwidth product
vs Free-air temperature 64
Gain-vs Supply voltage 65
Gain margin vs Load capacitance 66
vs Free-air temperature 67
φm Phase margin vs Supply voltage 68
vs Load capacitance 69
Phase shift vs Frequency 32, 33
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
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46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs (Continued)
FIGURE
Noninverting large-signal pulse response vs Time 70
Small-signal pulse response vs Time 71
zo Closed-loop output impedance vs Frequency 72
ax Crosstalk attenuation vs Frequency 73
Figure 6
15
12
6
3
0
27
9
– 4 – 2.4 – 0.8 0.8
Percentage of Units – %
21
18
24
DISTRIBUTION OF TLE2081
INPUT OFFSET VOLTAGE
30
2.4 4
VIO – Input Offset Voltage – mV
VCC = ±15 V
TA = 25°C
P Package
Figure 7
VIO
– Input Offset Voltage – mV
10
8
4
2
0
18
6
– 4 – 2.4 – 0.8 0.8
Percentage of Units – %
14
12
16
DISTRIBUTION OF TLE2082
INPUT OFFSET VOLTAGE
20
2.4 4
600 Units Tested From One Wafer Lot
VCC = ±15 V
TA = 25°C
P Package
– 3.2 – 1.6 0 1.6 3.2
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
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TYPICAL CHARACTERISTICS
Figure 8
VIO
– Input Offset Voltage – mV
25
20
10
5
0
45
15
– 8 – 4.8 – 1.6 1.6
Percentage of Units – %
35
30
40
DISTRIBUTION OF TLE2084
INPUT OFFSET VOLTAGE
50
4.8 8
TA = 25°C
N Package
VCC± = ±15 V
Figure 9
15
12
6
3
0
27
9
– 40 – 32 – 24 –16 – 8 0 8
Percentage of Amplifiers – %
21
18
24
DISTRIBUTION OF TLE2081 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
30
16 24 32 40
VCC = ±15 V
TA = – 55 °C to 125°C
P Package
αVIO – Temperature Coefficient – μV/°C
Figure 10
15
12
6
3
0
27
9
– 30 – 24 –18 –12 – 6 0 6
Percentage of Amplifiers – %
21
18
24
DISTRIBUTION OF TLE2082 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
30
12 18 24 30
310 Amplifiers
VCC = ±15 V
TA = – 55°C to 125°C
αVIO – Temperature Coefficient – μV/°C
P Package
Figure 11
15
12
6
3
0
27
9
– 40 – 32 – 24 –16 – 8 0 8
Percentage of Amplifiers – % 21
18
24
DISTRIBUTION OF TLE2084 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
30
16 24 32 40
VCC± = ±15 V
TA = – 55°C to 125°C
N Package
αVIO – Temperature Coefficient – μV/°C
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
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48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 12
IIB and – Input Bias and Input Offset Currents – nA
0.01
0.001
25 45
100
65 85 105 125
0.1
1
10
IIO
VCC± = ±5 V
VIC = 0
VO = 0
IIB
IIO
–75 –55 –35 –15 –5
TA – Free-Air Temperature – °C
TLE2081 AND TLE2082
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
Figure 13
and IIO – Input Bias and Offset Currents – nA
0.01
0.001
25 45
100
65 85 105 125
0.1
1
10
IIB IIO
VCC± = ±5 V
VIC = 0
VO = 0
IIB
IIO
–75 –55 –35 –15 –5
TA – Free-Air Temperature – °C
TLE2084
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
Figure 14
25 45 65 85 105 125
0.01
0.001
100
0.1
1
10
VCC± = ±15 V
VIC = 0
VO = 0
IIO
IIB
–75 –55 –35 –15 5
TA – Free-Air Temperature – °C
IIIIBB and IIIIOO – Input Bias and Input Offset Currents – nA
TLE2081 AND TLE2082
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
Figure 15
IIIIBB and IIOIO – Input Bias and Offset Currents – nA
25 45 65 85 105 125
0.01
0.001
100
0.1
1
10
VCC± = ±15 V
VIC = 0
VO = 0
IIO
IIB
–75 –55 –35 –15 5
TA – Free-Air Temperature – °C
TLE2084
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
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TYPICAL CHARACTERISTICS†
Figure 16
104
103
102
100
101
106
– Input Bias Current – pA
INPUT BIAS CURRENT
vs
TOTAL SUPPLY VOLTAGE
0 5 10 15 20 25 30 35 40 45
IIB
TA = 25°C
TA = –55°C
105 VICmin
TA = 125°C
VICmax = VCC+
VCC – Total Supply Voltage (referred to VCC–) – V
Figure 17
VVIICC – Common-Mode Input Voltage Range – V
5 25 45
COMMON-MODE INPUT VOLTAGE RANGE
vs
FREE-AIR TEMPERATURE
65 85 105 125
RS = 50 Ω
VCC+ + 0.5
VCC+ –0.5
VCC– + 3.5
VCC+
VCC– +3
VCC– + 2.5
VCC– +2
VICmin
VICmax
– 75 –55 –35 –15
TA – Free-Air Temperature – °C
Figure 18
VVIIDD – Differential Input Voltage – uV
– 5 – 4 – 3 – 2 – 10 0 1
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
2 5
RL = 2 kΩ
RL = 2 kΩ
RL = 10 kΩ
RL = 10 kΩ
VCC± = ±5 V
VIC = 0
RS = 50 Ω
TA = 25°C
RL = 600 Ω
RL = 600 Ω
– 100
– 200
– 300
– 400
100
200
400
300
0
3 4
VO – Output Voltage – V
μV
Figure 19
– 100
– 200
– 300
– 400
– 15 – 10 – 5 0 5
100
200
400
10 15
RL = 2 kΩ
VCC± = ±15 V
RL = 10 kΩ
RL = 10 kΩ
RL = 2 kΩ
RL = 600 Ω
RL = 600 Ω
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
300
0
VO – Output Voltage – V
VVIIDD – Differential Input Voltage – uμVV
VIC = 0
RS = 50 Ω
TA = 25°C
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
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TYPICAL CHARACTERISTICS†
Figure 20
VOM – Maximum Positive Peak Output Voltage – V
7.5
6
3
1.5
0
13.5
4.5
0 – 5 –10 –15 – 20 – 25 – 30
10.5
9
12
15
– 35 – 40 – 45 – 50
VOM+
TA = 25°C
TA = 125°C TA = 85°C
IO – Output Current – mA
VCC± = ±15 V
TA = –55°C
TLE2081 AND TLE2082
MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
Figure 21
VOM – Maximum Positive Peak Output Voltage – V
6
3
0
0 – 10 – 20 – 30
9
12
15
– 40 – 50
VOM+
TA = 25°C
TA = 125°C TA = 85°C
IO – Output Current – mA
VCC± = ±15 V
TLE2084
MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
Figure 22
– Maximum Negative Peak Output Voltage – V
–7.5
– 6
– 3
–1.5
0
–13.5
– 4.5
0 5 10 15 20 25 30
–10.5
– 9
–12
–15
35 40 45 50
VOM –
TA = 25°C
TA = 125°C
TA = –55°C
VCC± = ±15 V
TA = 85°C
IO – Output Current – mA
TLE2081 AND TLE2082
MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
Figure 23
– Maximum Negative Peak Output Voltage – V
– 6
– 3
0
0 10 20 30
– 9
–12
–15
40 50
VOM –
TA = 25°C
TA = 125°C
TA = –55°C
VCC± = ±15 V
TA = 85°C
IO – Output Current – mA
TLE2084
MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
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TYPICAL CHARACTERISTICS†
Figure 24
VOM – Maximum Peak Output Voltage – V
0
– 1
– 3
– 4
– 5
4
– 2
5 25 45
2
1
3
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
65 85 105 125
VOM
IO = –200 μA
IO = –2 mA
IO = –20 mA
VCC± = ±5 V
IO = 20 mA
IO = 2 mA
IO = 200 μA
–75 –55 –35 –15
TA – Free-Air Temperature – °C
Figure 25
12.5
12
11
10.5
10
14.5
11.5
5 25 45
| | – Maximum Peak Output Voltage – V
13.5
13
14
15
65 85 105 125
VOM
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
IO = –20 mA
IO = 20 mA
IO = 2 mA
IO = –200 μA
IO = 200 μA
VCC± = ±15 V
–75 –55 –35 –15
TA – Free-Air Temperature – °C
IO = –2 mA
Figure 26
VOM – Maximum Peak Output Voltage – V
0
– 5
–15
– 20
– 25
20
–10
0 2.5 5 7.5 10 12.5 15
10
5
15
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
25
17.5 20 22.5 25
VOM
IO = –200 μA
IO = –2 mA
IO = –20 mA
IO = 20 mA
IO = 200 μA
IO = 2 mA
TA = 25°C
|VCC±| – Supply Voltage – V
Figure 27
PP) – Maximum Peak-to-Peak Output Voltage – V
20
5
0
30
10
25
100 k 1 M 10 M
f – Frequency – Hz
VO(PP)
15
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
TA = –55°C
TA = 25°C,
125°C
TA = 25°C,
125°C
TA = –55°C
VCC± = ±15 V RL = 2 kΩ
VCC± = ±5 V
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 28
0 0.5 1 1.5 2
– Output Voltage – V
OUTPUT VOLTAGE
vs
SETTLING TIME
VO
VCC± = ±15 V
RL = 1 kΩ
CL = 100 pF
AV = –1
TA = 25°C
1 mV
1 mV
Rising
Falling
10 mV
10 mV
– 2.5
– 10
– 12.5
10
12.5
– 5
7.5
2.5
– 7.5
5
0
ts – Settling Time – μs
Figure 29
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
115
110
100
95
90
125
105
0.1 1 10 100
120
VCC± = ±15 V
VIC = 0
RS = 50 Ω
TA = 25°C
RL – Load Resistance – kΩ
VCC± = ±5 V
– Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification – dB
Figure 30
TA – Free-Air Temperature – °C
95
92
86
83
80
107
89
– 75 – 55 – 35 –15 5 25 45
101
98
104
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
110
65 85 105 125
RL = 10 kΩ
RL = 2 kΩ
VCC± = ±5 V
RL = 600 Ω
VO = ±2.3 V
– Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification – dB
Figure 31
– 55 – 35 –15 105 125
105
101
93
89
85
121
97
113
109
117
125
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
RL = 10 kΩ
– 75 5 25 45 65 85
TA – Free-Air Temperature – °C
RL = 600 Ω
RL = 2 kΩ
VCC± = ±15 V
VO = ±10 V
– Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification – dB
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53
TYPICAL CHARACTERISTICS
60
20
0
– 40
1 10 100 1 k 10 k 100 k
100
120
f – Frequency – Hz
SMALL-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
140
1 M 10 M 100 M
80
40
Gain
Phase Shift
– 20
140°
120°
100°
80°
60°
40°
20°
0°
Phase Shift
180°
160°
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
AVD – Small-Signal Differential
Voltage Amplification – dB
Figure 32
– 10
– 20
30
1 4 10 40 100
f – Frequency – MHz
SMALL-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
20
10
0
CL = 100 pF
CL = 25 pF
VCC± = ± 15 V
Phase Shift
Gain
80°
120°
100°
140°
160°
180°
Phase Shift
CL = 100 pF
CL = 25 pF
VIC = 0
RC = 2 kΩ
TA = 25°C
AVD – Small-Signal Differential
Voltage Amplification – dB
Figure 33
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 34
10 100 1 k 10 k
CMRR – Common-Mode Rejection Ratio – dB
f – Frequency – Hz
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
100 k 1 M 10 M
VCC± = ±15 V
VCC± = ±5 V
VIC = 0
VO = 0
RS = 50 Ω
TA = 25°C
50
40
20
10
0
90
30
70
60
80
100
Figure 35
TA – Free-Air Temperature – °C
85
82
76
73
70
97
79
– 75 – 55 – 35 –15 5 25 45
CMRR – Common-Mode Rejection Ratio – dB
91
88
94
100
65 85 105 125
VO = 0
RS = 50 Ω
VCC± = ±5 V
VCC± = ±15 V
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
VIC = VICRmin
Figure 36
kX SXVXRX – Supply-Voltage Rejection Ratio – dB
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
40
20
0
– 20
10 100 1 k 10 k 100 k
60
80
f – Frequency – Hz
100
1 M 10 M
120
kSVR+
kSVR–
ΔVCC± = ±5 V to ±15 V
VIC = 0
VO = 0
RS = 50 Ω
TA = 25°C
Figure 37
TA – Free-Air Temperature – °C
90
84
72
66
60
114
78
– 75 – 55 – 35 –15 5 25 45
102
96
108
120
65 85 105 125
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
kSVR+
kSVR–
kX SXVXRX – Supply-Voltage Rejection Ratio – dB
ΔVCC± = ±5 V to ±15 V
VIC = 0
VO = 0
RS = 50 Ω
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLE208x, TLE208xA, TLE208xY
EXCALIBUR HIGH-SPEED JFET-INPUT
OPERATIONAL AMPLIFIERS
SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55
TYPICAL CHARACTERISTICS†
Figure 38
|VCC±| – Supply Voltage – V
ICC – Supply Current – mA
2
1.6
0.8
0.4
0
3.6
1.2
0 2 4 6 8 10 12
2.8
2.4
3.2
4
14 16 18 20
ICC
TA = 25°C
TA = –55°C
TA = 125°C
VIC = 0
VO = 0
No Load
TLE2081
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
Figure 39
|VCC±| – Supply Voltage – V
ICC – Supply Current – mA
3
2.8
2.4
2.2
2
3.8
2.6
0 2.5 5 7.5 10 12.5 15
3.4
3.2
3.6
4
17.5 20 22.5 25
ICC
TA = 25°C
TA = –55°C
TA = 125°C
VIC = 0
VO = 0
No Load
TLE2082
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
