DS3231 DS - Farnell - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Microchip - 8-bit Wireless Development Kit

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Autres documentations :

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General Description The DS3231 is a low-cost, extremely accurate I2C realtime clock (RTC) with an integrated temperaturecompensated crystal oscillator (TCXO) and crystal. The device incorporates a battery input, and maintains accurate timekeeping when main power to the device is interrupted. The integration of the crystal resonator enhances the long-term accuracy of the device as well as reduces the piece-part count in a manufacturing line. The DS3231 is available in commercial and industrial temperature ranges, and is offered in a 16-pin, 300-mil SO package. The RTC maintains seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Two programmable time-ofday alarms and a programmable square-wave output are provided. Address and data are transferred serially through an I2C bidirectional bus. A precision temperature-compensated voltage reference and comparator circuit monitors the status of VCC to detect power failures, to provide a reset output, and to automatically switch to the backup supply when necessary. Additionally, the RST pin is monitored as a pushbutton input for generating a reset externally. Applications Servers Utility Power Meters Telematics GPS Features ♦ Accuracy ±2ppm from 0°C to +40°C ♦ Accuracy ±3.5ppm from -40°C to +85°C ♦ Battery Backup Input for Continuous Timekeeping ♦ Operating Temperature Ranges Commercial: 0°C to +70°C Industrial: -40°C to +85°C ♦ Low-Power Consumption ♦ Real-Time Clock Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap Year Compensation Valid Up to 2100 ♦ Two Time-of-Day Alarms ♦ Programmable Square-Wave Output ♦ Fast (400kHz) I2C Interface ♦ 3.3V Operation ♦ Digital Temp Sensor Output: ±3°C Accuracy ♦ Register for Aging Trim ♦ RST Output/Pushbutton Reset Debounce Input ♦ Underwriters Laboratories (UL) Recognized DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal ______________________________________________ Maxim Integrated Products 1 Rev 5; 4/08 Ordering Information PART TEMP RANGE PIN-PACKAGE TOP MARK DS3231S 0°C to +70°C 16 SO DS3231 DS3231SN -40°C to +85°C 16 SO DS3231N DS3231S# 0°C to +70°C 16 SO DS3231S DS3231SN# -40°C to +85°C 16 SO DS3231SN Pin Configuration appears at end of data sheet. DS3231 VCC SCL RPU RPU = tR/CB RPU INT/SQW 32kHz VBAT PUSHBUTTON RESET SDA RST N.C. N.C. N.C. N.C. VCC VCC GND VCC CPU N.C. N.C. N.C. N.C. Typical Operating Circuit # Denotes a RoHS-compliant device that may include lead that is exempt under RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and leadfree soldering processes. A "#" anywhere on the top mark denotes a RoHS-compliant device. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 2 _____________________________________________________________________ ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on VCC, VBAT, 32kHz, SCL, SDA, RST, INT/SQW Relative to Ground.............................-0.3V to +6.0V Operating Temperature Range (noncondensing) .............................................-40°C to +85°C Junction Temperature......................................................+125°C Storage Temperature Range ...............................-40°C to +85°C Lead Temperature (Soldering, 10s).....................................................+260°C/10s Soldering Temperature....................................See the Handling, PC Board Layout, and Assembly section. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 2.3 3.3 5.5 V Supply Voltage VBAT 2.3 3.0 5.5 V Logic 1 Input SDA, SCL VIH 0.7 x VCC VCC + 0.3 V Logic 0 Input SDA, SCL VIL -0.3 +0.3 x VCC V Pullup Voltage (SDA, SCL, 32kHz, INT/SQW) VPU VCC = 0V 5.5V V ELECTRICAL CHARACTERISTICS (VCC = 2.3V to 5.5V, VCC = Active Supply (see Table 1), TA = TMIN to TMAX, unless otherwise noted.) (Typical values are at VCC = 3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC = 3.63V 200 Active Supply Current ICCA (Notes 3, 4) VCC = 5.5V 300 μA VCC = 3.63V 110 Standby Supply Current ICCS I2C bus inactive, 32kHz output on, SQW output off (Note 4) VCC = 5.5V 170 μA VCC = 3.63V 575 Temperature Conversion Current ICCSCONV I2C bus inactive, 32kHz output on, SQW output off VCC = 5.5V 650 μA Power-Fail Voltage VPF 2.45 2.575 2.70 V Logic 0 Output, 32kHz, INT/SQW, SDA VOL IOL = 3mA 0.4 V Logic 0 Output, RST VOL IOL = 1mA 0.4 V Output Leakage Current 32kHz, INT/SQW, SDA ILO Output high impedance -1 0 +1 μA Input Leakage SCL ILI -1 +1 μA RST Pin I/O Leakage IOL RST high impedance (Note 5) -200 +10 μA VBAT Leakage Current (VCC Active) IBATLKG 25 100 nA DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal _____________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.3V to 5.5V, VCC = Active Supply (see Table 1), TA = TMIN to TMAX, unless otherwise noted.) (Typical values are at VCC = 3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency fOUT VCC = 3.3V or VBAT = 3.3V 32.768 kHz Frequency Stability vs. 0°C to +40°C ±2 Temperature (Commercial) 􀀁f/fOUT VCC = 3.3V or VBAT = 3.3V, aging offset = 00h >40°C to +70°C ±3.5 ppm -40°C to <0°C ±3.5 0°C to +40°C ±2 Frequency Stability vs. Temperature (Industrial) 􀀁f/fOUT VCC = 3.3V or VBAT = 3.3V, aging offset = 00h >40°C to +85°C ±3.5 ppm Frequency Stability vs. Voltage 􀀁f/V 1 ppm/V -40°C 0.7 +25°C 0.1 +70°C 0.4 Trim Register Frequency Sensitivity per LSB 􀀁f/LSB Specified at: +85°C 0.8 ppm Temperature Accuracy Temp VCC = 3.3V or VBAT = 3.3V -3 +3 °C First year ±1.0 Crystal Aging 􀀁f/fO After reflow, not production tested 0–10 years ±5.0 ppm ELECTRICAL CHARACTERISTICS (VCC = 0V, VBAT = 2.3V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBAT = 3.63V 70 Active Battery Current IBATA EOSC = 0, BBSQW = 0, SCL = 400kHz (Note 4) VBAT = 5.5V 150 μA VBAT = 3.63V 0.84 3.0 Timekeeping Battery Current IBATT EOSC = 0, BBSQW = 0, EN32kHz = 1, SCL = SDA = 0V or SCL = SDA = VBAT (Note 4) VBAT = 5.5V 1.0 3.5 μA VBAT = 3.63V 575 Temperature Conversion Current IBATTC EOSC = 0, BBSQW = 0, SCL = SDA = 0V or SCL = SDA = VBAT VBAT = 5.5V 650 μA Data-Retention Current IBATTDR EOSC = 1, SCL = SDA = 0V, +25°C 100 nA DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 4 _____________________________________________________________________ AC ELECTRICAL CHARACTERISTICS (VCC = VCC(MIN) to VCC(MAX) or VBAT = VBAT(MIN) to VBAT(MAX), VBAT > VCC, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast mode 100 400 SCL Clock Frequency fSCL Standard mode 0 100 kHz Bus Free Time Between STOP Fast mode 1.3 and START Conditions tBUF Standard mode 4.7 μs Hold Time (Repeated) START Fast mode 0.6 Condition (Note 6) tHD:STA Standard mode 4.0 μs Fast mode 1.3 Low Period of SCL Clock tLOW Standard mode 4.7 μs Fast mode 0.6 High Period of SCL Clock tHIGH Standard mode 4.0 μs Fast mode 0 0.9 Data Hold Time (Notes 7, 8) tHD:DAT Standard mode 0 0.9 μs Fast mode 100 Data Setup Time (Note 9) tSU:DAT Standard mode 250 ns Fast mode 0.6 START Setup Time tSU:STA Standard mode 4.7 μs Rise Time of Both SDA and SCL Fast mode 300 Signals (Note 10) tR Standard mode 20 + 0.1CB 1000 ns Fall Time of Both SDA and SCL Fast mode 300 Signals (Note 10) tF Standard mode 20 + 0.1CB 300 ns Fast mode 0.6 Setup Time for STOP Condition tSU:STO Standard mode 4.7 μs Capacitive Load for Each Bus Line (Note 10) CB 400 pF Capacitance for SDA, SCL CI/O 10 pF Pulse Width of Spikes That Must Be Suppressed by the Input Filter tSP 30 ns Pushbutton Debounce PBDB 250 ms Reset Active Time tRST 250 ms Oscillator Stop Flag (OSF) Delay tOSF (Note 11) 100 ms Temperature Conversion Time tCONV 125 200 ms POWER-SWITCH CHARACTERISTICS (TA = TMIN to TMAX) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 μs VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0 μs Recovery at Power-Up tREC (Note 12) 250 300 ms DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal _____________________________________________________________________ 5 Pushbutton Reset Timing PBDB tRST RST Power-Switch Timing VCC tVCCF tVCCR tREC VPF(MAX) VPF VPF VPF(MIN) RST DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 6 _____________________________________________________________________ Data Transfer on I2C Serial Bus SDA SCL tHD:STA tLOW tHIGH tR tF tBUF tHD:DAT tSU:DAT REPEATED START tSU:STA tHD:STA tSU:STO tSP STOP START WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data. Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: ICCA—SCL clocking at max frequency = 400kHz. Note 4: Current is the averaged input current, which includes the temperature conversion current. Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC. Note 6: After this period, the first clock pulse is generated. Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 10: CB—total capacitance of one bus line in pF. Note 11: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ 3.4V. Note 12: This delay applies only if the oscillator is enabled and running. If the EOSC bit is a 1, tREC is bypassed and RST immediately goes high. The state of RST does not affect the I2C interface, RTC, or TCXO. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal _____________________________________________________________________ 7 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) STANDBY SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3231 toc01 VCC (V) ICCS (μA) 2.5 3.0 3.5 4.0 4.5 5.0 25 50 75 100 125 150 0 2.0 5.5 RST ACTIVE BSY = 0, SCL = SDA = VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3231 toc02 VBAT (V) IBAT (μA) 3.3 4.3 5.3 0.7 0.8 0.9 1.0 1.1 1.2 0.6 2.3 VCC = 0V, BSY = 0, SDA = SCL = VBAT OR VCC EN32kHz = 1 EN32kHz = 0 SUPPLY CURRENT vs. TEMPERATURE DS3231 toc03 TEMPERATURE (°C) IBAT (μA) -15 10 35 60 0.7 0.8 0.9 1.0 0.6 -40 85 VCC = 0, EN32kHz = 1, BSY = 0, SDA = SCL = VBAT OR GND FREQUENCY DEVIATION vs. TEMPERATURE vs. AGING VALUE DS3231 toc04 TEMPERATURE (°C) FREQUENCY DEVIATION (ppm) -15 10 35 60 -30 -20 -10 0 10 20 30 40 50 60 -40 -40 85 127 32 0 -33 8 DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 8 _____________________________________________________________________ Block Diagram N N N RST VCC 32kHz INT/SQW CLOCK AND CALENDAR REGISTERS USER BUFFER (7 BYTES) I2C INTERFACE AND ADDRESS REGISTER DECODE POWER CONTROL VCC VBAT GND SCL SDA TEMPERATURE SENSOR CONTROL LOGIC/ DIVIDER PUSHBUTTON RESET; SQUARE-WAVE BUFFER; INT/SQW CONTROL CONTROL AND STATUS REGISTERS OSCILLATOR AND CAPACITOR ARRAY X1 X2 DS3231 DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal _____________________________________________________________________ 9 Pin Description PIN NAME FUNCTION 1 32kHz 32kHz Output. This open-drain pin requires an external pullup resistor. When enabled, the output operates on either power supply. It may be left open if not used. 2 VCC DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1μF to 1.0μF capacitor. If not used, connect to ground. 3 INT/SQW Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor connected to a supply at 5.5V or less. It may be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by RS2 and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled. 4 RST Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the RST pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal 50k nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the oscillator is disabled, tREC is bypassed and RST immediately goes high. 5–12 N.C. No Connection. Must be connected to ground. 13 GND Ground 14 VBAT Backup Power-Supply Input. This pin should be decoupled using a 0.1μF to 1.0μF low-leakage capacitor. If the I2C interface is inactive whenever the device is powered by the VBAT input, the decoupling capacitor is not required. If VBAT is not used, connect to ground. UL recognized to ensure against reverse charging when used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul. 15 SDA Serial Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin requires an external pullup resistor. 16 SCL Serial Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data movement on the serial interface. Detailed Description The DS3231 is a serial RTC driven by a temperaturecompensated 32kHz crystal oscillator. The TCXO provides a stable and accurate reference clock, and maintains the RTC to within ±2 minutes per year accuracy from -40°C to +85°C. The TCXO frequency output is available at the 32kHz pin. The RTC is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. The INT/SQW provides either an interrupt signal due to alarm conditions or a square-wave output. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. The internal registers are accessible though an I2C bus interface. A temperature-compensated voltage reference and comparator circuit monitors the level of VCC to detect power failures and to automatically switch to the backup supply when necessary. The RST pin provides an external pushbutton function and acts as an indicator of a power-fail event. DS3231 Operation The block diagram shows the main elements of the DS3231. The eight blocks can be grouped into four functional groups: TCXO, power control, pushbutton function, and RTC. Their operations are described separately in the following sections. 32kHz TCXO The temperature sensor, oscillator, and control logic form the TCXO. The controller reads the output of the on-chip temperature sensor and uses a lookup table to determine the capacitance required, adds the aging correction in AGE register, and then sets the capacitance selection registers. New values, including changes to the AGE register, are loaded only when a change in the temperature value occurs, or when a user-initiated temperature conversion is completed. The temperature is read on initial application of VCC and once every 64 seconds afterwards. Power Control This function is provided by a temperature-compensated voltage reference and a comparator circuit that monitors the VCC level. When VCC is greater than VPF, the part is powered by VCC. When VCC is less than VPF but greater than VBAT, the DS3231 is powered by VCC. If VCC is less than VPF and is less than VBAT, the device is powered by VBAT. See Table 1. To preserve the battery, the first time VBAT is applied to the device, the oscillator will not start up until VCC exceeds VPF, or until a valid I2C address is written to the part. Typical oscillator startup time is less than one second. Approximately 2 seconds after VCC is applied, or a valid I2C address is written, the device makes a temperature measurement and applies the calculated correction to the oscillator. Once the oscillator is running, it continues to run as long as a valid power source is available (VCC or VBAT), and the device continues to measure the temperature and correct the oscillator frequency every 64 seconds. On the first application of power (VCC) or when a valid I2C address is written to the part (VBAT), the time and date registers are reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS). Pushbutton Reset Function The DS3231 provides for a pushbutton switch to be connected to the RST output pin. When the DS3231 is not in a reset cycle, it continuously monitors the RST signal for a low going edge. If an edge transition is detected, the DS3231 debounces the switch by pulling the RST low. After the internal timer has expired (PBDB), the DS3231 continues to monitor the RST line. If the line is still low, the DS3231 continuously monitors the line looking for a rising edge. Upon detecting release, the DS3231 forces the RST pin low and holds it low for tRST. RST is also used to indicate a power-fail condition. When VCC is lower than VPF, an internal power-fail signal is generated, which forces the RST pin low. When VCC returns to a level above VPF, the RST pin is held low for approximately 250ms (tREC) to allow the power supply to stabilize. If the oscillator is not running (see the Power Control section) when VCC is applied, tREC is bypassed and RST immediately goes high. The state of RST does not affect the operation of the TCXO, I2C interface, or RTC functions. Real-Time Clock With the clock source from the TCXO, the RTC provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. The clock provides two programmable time-of-day alarms and a programmable square-wave output. The INT/SQW pin either generates an interrupt due to alarm condition or outputs a square-wave signal and the selection is controlled by the bit INTCN. Address Map Figure 1 shows the address map for the DS3231 timekeeping registers. During a multibyte access, when the address pointer reaches the end of the register space (12h), it wraps around to location 00h. On an I2C START or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to reread the registers in case the main registers update during a read. I2C Interface The I2C interface is accessible whenever either VCC or VBAT is at a valid level. If a microcontroller connected to the DS3231 resets because of a loss of VCC or other event, it is possible that the microcontroller and DS3231 I2C communications could become unsynchronized, Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 10 ____________________________________________________________________ SUPPLY CONDITION ACTIVE SUPPLY VCC < VPF, VCC < VBAT VBAT VCC < VPF, VCC > VBAT VCC VCC > VPF, VCC < VBAT VCC VCC > VPF, VCC > VBAT VCC Table 1. Power Control e.g., the microcontroller resets while reading data from the DS3231. When the microcontroller resets, the DS3231 I2C interface may be placed into a known state by toggling SCL until SDA is observed to be at a high level. At that point the microcontroller should pull SDA low while SCL is high, generating a START condition. Clock and Calendar The time and calendar information is obtained by reading the appropriate register bytes. Figure 1 illustrates the RTC registers. The time and calendar data are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The DS3231 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic-high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. The day-of-week register increments at midnight. Values that correspond to the day of week are userdefined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any START and when the register pointer rolls over to zero. The time information is read DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal ____________________________________________________________________ 11 Figure 1. Timekeeing Registers Note: Unless otherwise specified, the registers’ state is not defined when power is first applied. ADDRESS BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LSB FUNCTION RANGE 00h 0 10 Seconds Seconds Seconds 00–59 01h 0 10 Minutes Minutes Minutes 00–59 AM/PM 02h 0 12/24 10 Hour 10 Hour Hour Hours 1–12 + AM/PM 00–23 03h 0 0 0 0 0 Day Day 1–7 04h 0 0 10 Date Date Date 01–31 05h Century 0 0 10 Month Month Month/ Century 01–12 + Century 06h 10 Year Year Year 00–99 07h A1M1 10 Seconds Seconds Alarm 1 Seconds 00–59 08h A1M2 10 Minutes Minutes Alarm 1 Minutes 00–59 AM/PM 09h A1M3 12/24 10 Hour 10 Hour Hour Alarm 1 Hours 1–12 + AM/PM 00–23 Day Alarm 1 Day 1–7 0Ah A1M4 DY/DT 10 Date Date Alarm 1 Date 1–31 0Bh A2M2 10 Minutes Minutes Alarm 2 Minutes 00–59 AM/PM 0Ch A2M3 12/24 10 Hour 10 Hour Hour Alarm 2 Hours 1–12 + AM/PM 00–23 Day Alarm 2 Day 1–7 0Dh A2M4 DY/DT 10 Date Date Alarm 2 Date 1–31 0Eh EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE Control — 0Fh OSF 0 0 0 EN32kHz BSY A2F A1F Control/Status — 10h SIGN DATA DATA DATA DATA DATA DATA DATA Aging Offset — 11h SIGN DATA DATA DATA DATA DATA DATA DATA MSB of Temp — 12h DATA DATA 0 0 0 0 0 0 LSB of Temp — DS3231 from these secondary registers, while the clock continues to run. This eliminates the need to reread the registers in case the main registers update during a read. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge from the DS3231. Once the countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. Alarms The DS3231 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the alarm enable and INTCN bits of the control register) to activate the INT/SQW output on an alarm match condition. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 2). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers match the corresponding values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 2 shows the possible settings. Configurations not listed in the table will result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm will be the result of a match with date of the month. If DY/DT is written to logic 1, the alarm will be the result of a match with day of the week. When the RTC register values match alarm register settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is set to logic 1. If the corresponding Alarm Interrupt Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition will activate the INT/SQW signal. The match is tested on the once-per-second update of the time and date registers. Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 12 ____________________________________________________________________ Table 2. Alarm Mask Bits ALARM 1 REGISTER MASK BITS (BIT 7) DY/DT A1M4 A1M3 A1M2 A1M1 ALARM RATE X 1 1 1 1 Alarm once per second X 1 1 1 0 Alarm when seconds match X 1 1 0 0 Alarm when minutes and seconds match X 1 0 0 0 Alarm when hours, minutes, and seconds match 0 0 0 0 0 Alarm when date, hours, minutes, and seconds match 1 0 0 0 0 Alarm when day, hours, minutes, and seconds match ALARM 2 REGISTER MASK BITS (BIT 7) DY/DT A2M4 A2M3 A2M2 ALARM RATE X 1 1 1 Alarm once per minute (00 seconds of every minute) X 1 1 0 Alarm when minutes match X 1 0 0 Alarm when hours and minutes match 0 0 0 0 Alarm when date, hours, and minutes match 1 0 0 0 Alarm when day, hours, and minutes match Special-Purpose Registers The DS3231 has two additional registers (control and status) that control the real-time clock, alarms, and square-wave output. Control Register (0Eh) Bit 7: Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped when the DS3231 switches to VBAT. This bit is clear (logic 0) when power is first applied. When the DS3231 is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit. Bit 6: Battery-Backed Square-Wave Enable (BBSQW). When set to logic 1 and the DS3231 is being powered by the VBAT pin, this bit enables the squarewave or interrupt output when VCC is absent. When BBSQW is logic 0, the INT/SQW pin goes high impedance when VCC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bit 5: Convert Temperature (CONV). Setting this bit to 1 forces the temperature sensor to convert the temperature into digital code and execute the TCXO algorithm to update the capacitance array to the oscillator. This can only happen when a conversion is not already in progress. The user should check the status bit BSY before forcing the controller to start a new TCXO execution. A user-initiated temperature conversion does not affect the internal 64-second update cycle. A user-initiated temperature conversion does not affect the BSY bit for approximately 2ms. The CONV bit remains at a 1 from the time it is written until the conversion is finished, at which time both CONV and BSY go to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The following table shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (8.192kHz) when power is first applied. Bit 2: Interrupt Control (INTCN). This bit controls the INT/SQW signal. When the INTCN bit is set to logic 0, a square wave is output on the INT/SQW pin. When the INTCN bit is set to logic 1, then a match between the timekeeping registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to logic 1 when power is first applied. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate the INT/SQW signal. The A1IE bit is disabled (logic 0) when power is first applied. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal ____________________________________________________________________ 13 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE RS2 RS1 SQUARE-WAVE OUTPUT FREQUENCY 0 0 1Hz 0 1 1.024kHz 1 0 4.096kHz 1 1 8.192kHz SQUARE-WAVE OUTPUT FREQUENCY Control Register (0Eh) DS3231 Status Register (0Fh) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltages present on both VCC and VBAT are insufficient to support oscillation. 3) The EOSC bit is turned off in battery-backed mode. 4) External influences on the crystal (i.e., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. Bit 3: Enable 32kHz Output (EN32kHz). This bit controls the status of the 32kHz pin. When set to logic 1, the 32kHz pin is enabled and outputs a 32.768kHz square-wave signal. When set to logic 0, the 32kHz pin goes to a high-impedance state. The initial power-up state of this bit is logic 1, and a 32.768kHz square-wave signal appears at the 32kHz pin after a power source is applied to the DS3231 (if the oscillator is running). Bit 2: Busy (BSY). This bit indicates the device is busy executing TCXO functions. It goes to logic 1 when the conversion signal to the temperature sensor is asserted and then is cleared when the device is in the 1-minute idle state. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the A2IE bit is logic 1 and the INTCN bit is set to logic 1, the INT/SQW pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is logic 1 and the INTCN bit is set to logic 1, the INT/SQW pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Aging Offset The crystal aging offset register provides an 8-bit code to add to the codes in the capacitance array registers. The code is encoded in two’s complement. One LSB represents one small capacitor to be switched in or out of the capacitance array at the crystal pins. The offset register is added to the capacitance array register under the following conditions: during a normal temperature conversion, if the temperature changes from the previous conversion, or during a manual user conversion (setting the CONV bit). To see the effects of the aging register on the 32kHz output frequency immediately, a manual conversion should be started after each aging register change. Positive aging values add capacitance to the array, slowing the oscillator frequency. Negative values remove capacitance from the array, increasing the oscillator frequency. The change in ppm per LSB is different at different temperatures. The frequency vs. temperature curve is shifted by the values used in this register. At +25°C, one LSB typically provides about 0.1ppm change in frequency. Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 14 ____________________________________________________________________ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sign Data Data Data Data Data Data Data Aging Offset (10h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSF 0 0 0 EN32kHz BSY A2F A1F Status Register (0Fh) Temperature Registers (11h–12h) Temperature is represented as a 10-bit code with a resolution of +0.25°C and is accessible at location 11h and 12h. The temperature is encoded in two’s complement format. The upper 8 bits are at location 11h and the lower 2 bits are in the upper nibble at location 12h. Upon power reset, the registers are set to a default temperature of 0°C and the controller starts a temperature conversion. New temperature readings are stored in this register. I2C Serial Data Bus The DS3231 supports a bidirectional I2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data is defined as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS3231 operates as a slave on the I2C bus. Connections to the bus are made through the SCL input and open-drain SDA I/O lines. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS3231 works in both modes. The following bus protocol has been defined (Figure 2): • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. START data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. STOP data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal ____________________________________________________________________ 15 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sign Data Data Data Data Data Data Data Temperature Register (Upper Byte) (11h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Data Data 0 0 0 0 0 0 Temperature Register (Lower Byte) (12h) DS3231 Figures 3 and 4 detail how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most significant bit (MSB) first. The DS3231 can operate in the following two modes: Slave receiver mode (DS3231 write mode): Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS3231 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS3231 outputs an Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 16 ____________________________________________________________________ STOP CONDITION OR REPEATED START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED ACK START CONDITION ACK ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SLAVE ADDRESS MSB SCL SDA R/W DIRECTION BIT 1 2 6 7 8 9 1 2 3–7 8 9 Figure 2. I2C Data Transfer Overview S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P S = START A = ACKNOWLEDGE P = STOP R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D0h DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) Figure 3. Slave Receiver Mode (Write Mode) S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P S = START A = ACKNOWLEDGE P = STOP A = NOT ACKNOWLEDGE R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D1h DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL Figure 4. Slave Transmitter Mode (Read Mode) acknowledge on SDA. After the DS3231 acknowledges the slave address + write bit, the master transmits a word address to the DS3231. This sets the register pointer on the DS3231, with the DS3231 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS3231 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. Slave transmitter mode (DS3231 read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3231 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS3231 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte, the DS3231 outputs an acknowledge on SDA. The DS3231 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The DS3231 must receive a not acknowledge to end a read. Handling, PC Board Layout, and Assembly The DS3231 package contains a quartz tuning-fork crystal. Pick-and-place equipment can be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground. Moisture-sensitive packages are shipped from the factory dry packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications and reflow profiles. Exposure to reflow is limited to 2 times maximum. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal ____________________________________________________________________ 17 DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 18 ____________________________________________________________________ Chip Information TRANSISTOR COUNT: 33,000 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS Thermal Information Theta-JA: +73°C/W Theta-JC: +23°C/W 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 32kHz SCL SDA VBAT GND N.C. N.C. N.C. N.C. TOP VIEW SO VCC INT/SQW N.C. RST N.C. N.C. N.C. DS3231S Pin Configuration PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 16 SO — 56-G4009-001 Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 1/05 Initial release. — Changed Digital Temp Sensor Output from ±2°C to ±3°C. 1, 3 Updated Typical Operating Circuit. 1 Changed TA = -40°C to +85°C to TA = TMIN to TMAX. 2, 3, 4 1 2/05 Updated Block Diagram. 8 Added “UL Recognized” to Features; added lead-free packages and removed S from top mark info in Ordering Information table; added ground connections to the N.C. pin in the Typical Operating Circuit. 1 Added “noncondensing” to operating temperature range; changed VPF MIN from 2.35V to 2.45V. 2 Added aging offset specification. 3 Relabeled TOC4. 7 Added arrow showing input on X1 in the Block Diagram. 8 Updated pin descriptions for VCC and VBAT. 9 Added the I2C Interface section. 10 Figure 1: Added sign bit to aging and temperature registers; added MSB and LSB. 11 Corrected title for rate select bits frequency table. 13 Added note that frequency stability over temperature spec is with aging offset register = 00h; changed bit 7 from Data to Sign (Crystal Aging Offset Register). 14 Changed bit 7 from Data to Sign (Temperature Register); correct pin definitions in I2C Serial Data Bus section. 15 2 6/05 Modified the Handing, PC Board Layout, and Assembly section to refer to J-STD-020 for reflow profiles for lead-free and leaded packages. 17 3 11/05 Changed lead-free packages to RoHS-compliant packages. 1 Changed RST and UL bullets in Features. 1 Changed EC condition “VCC > VBAT” to “VCC = Active Supply (see Table 1).” 2, 3 Modified Note 12 to correct tREC operation. 6 Added various conditions text to TOCs 1, 2, and 3. 7 Added text to pin descriptions for 32kHz, VCC, and RST. 9 Table 1: Changed column heading “Powered By” to “Active Supply”; changed “applied” to “exceeds VPF” in the Power Control section. 10 Indicated BBSQW applies to both SQW and interrupts; simplified temp convert description (bit 5); added “output” to INT\SQW (bit 2). 13 4 10/06 Changed the Crystal Aging section to the Aging Offset section; changed “this bit indicates” to “this bit controls” for the enable 32kHz output bit. 14 Added Warning note to EC table notes; updated Note 12. 6 Updated the Typical Operating Characteristics graphs. 7 In the Power Control section, added information about the POR state of the time and date registers; in the Real-Time Clock section, added to the description of the RST function. 10 5 4/08 In Figure 1, corrected the months date range for 04h from 00–31 to 01–31. 11 © 2007 Microchip Technology Inc. Preliminary DS39631B PIC18F2420/2520/4420/4520 Data Sheet Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology DS39631B-page ii Preliminary © 2007 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 1 PIC18F2420/2520/4420/4520 Power Managed Modes: • Run: CPU on, peripherals on • Idle: CPU off, peripherals on • Sleep: CPU off, peripherals off • Idle mode currents down to 5.8 μA typical • Sleep mode current down to 0.1 μA typical • Timer1 Oscillator: 1.8 μA, 32 kHz, 2V • Watchdog Timer: 2.1 μA • Two-Speed Oscillator Start-up Peripheral Highlights: • High-current sink/source 25 mA/25 mA • Three programmable external interrupts • Four input change interrupts • Up to 2 Capture/Compare/PWM (CCP) modules, one with Auto-Shutdown (28-pin devices) • Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only): - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart • Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI™ (all 4 modes) and I2C™ Master and Slave Modes • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN 1.2 - RS-232 operation using internal oscillator block (no external crystal required) - Auto-Wake-up on Start bit - Auto-Baud Detect • 10-bit, up to 13-channel Analog-to-Digital Converter module (A/D): - Auto-acquisition capability - Conversion available during Sleep • Dual analog comparators with input multiplexing) Flexible Oscillator Structure: • Four Crystal modes, up to 40 MHz • 4X Phase Lock Loop (available for crystal and internal oscillators) • Two External RC modes, up to 4 MHz • Two External Clock modes, up to 40 MHz • Internal oscillator block: - 8 user selectable frequencies, from 31 kHz to 8 MHz - Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL - User tunable to compensate for frequency drift • Secondary oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops Special Microcontroller Features: • C compiler optimized architecture: - Optional extended instruction set designed to optimize re-entrant code • 100,000 erase/write cycle Enhanced Flash program memory typical • 1,000,000 erase/write cycle Data EEPROM memory typical • Flash/Data EEPROM Retention: 100 years typical • Self-programmable under software control • Priority levels for interrupts • 8 x 8 Single-Cycle Hardware Multiplier • Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s • Single-supply 5V In-Circuit Serial Programming™ (ICSP™) via two pins • In-Circuit Debug (ICD) via two pins • Wide operating voltage range: 2.0V to 5.5V • Programmable 16-level High/Low-Voltage Detection (HLVD) module: - Supports interrupt on High/Low-Voltage Detection • Programmable Brown-out Reset (BOR - With software enable option 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology PIC18F2420/2520/4420/4520 DS39631B-page 2 Preliminary © 2007 Microchip Technology Inc. - Device Program Memory Data Memory I/O 10-bit A/D (ch) CCP/ ECCP (PWM) MSSP EUSART Comp. Timers Flash 8/16-bit (bytes) # Single-Word Instructions SRAM (bytes) EEPROM (bytes) SPI Master I2C PIC18F2420 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3 PIC18F2520 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3 PIC18F4420 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3 PIC18F4520 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 3 PIC18F2420/2520/4420/4520 Pin Diagrams RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2(1) RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC18F4520 PIC18F2520 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2(1) RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 40-pin PDIP 28-pin PDIP, SOIC PIC18F4420 PIC18F2420 Note 1: RB3 is the alternate pin for CCP2 multiplexing. 1011 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 2827 2625 2423 9 PIC18F2420 RC0/T1OSO/T13CKI 5 4 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4KBI0/AN11 RB3/AN9/CCP2(1) RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL PIC18F2520 28-pin QFN PIC18F2420/2520/4420/4520 DS39631B-page 4 Preliminary © 2007 Microchip Technology Inc. Pin Diagrams (Cont.’d) Note 1: RB3 is the alternate pin for CCP2 multiplexing. 10 11 2 345 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 PIC18F4420 37 RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 MCLR/VPP/RE3 RB3/AN9/CCP2(1) RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2(1) RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VSS VDD VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD VDD RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 44-pin QFN PIC18F4520 10 11 2 345 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 PIC18F4420 37 RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 MCLR/VPP/RE3 NC RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2(1) NC NC RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2(1) 44-pin TQFP PIC18F4520 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 5 PIC18F2420/2520/4420/4520 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 23 3.0 Power Managed Modes ............................................................................................................................................................. 33 4.0 Reset .......................................................................................................................................................................................... 41 5.0 Memory Organization................................................................................................................................................................. 53 6.0 Flash Program Memory.............................................................................................................................................................. 73 7.0 Data EEPROM Memory ............................................................................................................................................................. 83 8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 89 9.0 Interrupts .................................................................................................................................................................................... 91 10.0 I/O Ports ................................................................................................................................................................................... 105 11.0 Timer0 Module ......................................................................................................................................................................... 123 12.0 Timer1 Module ......................................................................................................................................................................... 127 13.0 Timer2 Module ......................................................................................................................................................................... 133 14.0 Timer3 Module ......................................................................................................................................................................... 135 15.0 Capture/Compare/Pwm (CCP) Modules .................................................................................................................................. 139 16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 147 17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 161 18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 201 19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 223 20.0 Comparator Module.................................................................................................................................................................. 233 21.0 Comparator Voltage Reference Module................................................................................................................................... 239 22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 243 23.0 Special Features of the CPU.................................................................................................................................................... 249 24.0 Instruction Set Summary .......................................................................................................................................................... 267 25.0 Development Support............................................................................................................................................................... 317 26.0 Electrical Characteristics .......................................................................................................................................................... 323 27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 361 28.0 Packaging Information.............................................................................................................................................................. 363 Appendix A: Revision History............................................................................................................................................................. 371 Appendix B: Device Differences ........................................................................................................................................................ 371 Appendix C: Conversion Considerations ........................................................................................................................................... 372 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 372 Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 373 Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 373 Index .................................................................................................................................................................................................. 375 On-Line Support................................................................................................................................................................................. 385 Systems Information and Upgrade Hot Line ...................................................................................................................................... 385 Reader Response .............................................................................................................................................................................. 386 PIC18F2420/2520/4420/4520 Product Identification System ............................................................................................................ 387 PIC18F2420/2520/4420/4520 DS39631B-page 6 Preliminary © 2007 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 7 PIC18F2420/2520/4420/4520 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of highendurance, Enhanced Flash program memory. On top of these features, the PIC18F2420/2520/4420/4520 family introduces design enhancements that make these microcontrollers a logical choice for many highperformance, power sensitive applications. 1.1 New Core Features 1.1.1 nanoWatt TECHNOLOGY All of the devices in the PIC18F2420/2520/4420/4520 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. • On-the-fly Mode Switching: The power managed modes are invoked by user code during operation, allowing the user to incorporate powersaving ideas into their application’s software design. • Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 26.0 “Electrical Characteristics” for values. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2420/2520/4420/4520 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators • Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O) • Two External RC Oscillator modes with the same pin options as the External Clock modes • An internal oscillator block which provides an 8 MHz clock and an INTRC source (approximately 31 kHz), as well as a range of 6 user selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O. • A Phase Lock Loop (PLL) frequency multiplier, available to both the high-speed crystal and internal oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz – all without using an external crystal or clock circuit. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. • PIC18F2420 • PIC18LF2420 • PIC18F2520 • PIC18LF2520 • PIC18F4420 • PIC18LF4420 • PIC18F4520 • PIC18LF4520 PIC18F2420/2520/4420/4520 DS39631B-page 8 Preliminary © 2007 Microchip Technology Inc. 1.2 Other Special Features • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Extended Instruction Set: The PIC18F2420/ 2520/4420/4520 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. • Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include Auto-Shutdown, for disabling PWM outputs on interrupt or other select conditions and Auto-Restart, to reactivate outputs once the condition has cleared. • Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the USART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 26.0 “Electrical Characteristics” for time-out periods. 1.3 Details on Individual Family Members Devices in the PIC18F2420/2520/4420/4520 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory (16 Kbytes for PIC18F2420/4420 devices and 32 Kbytes for PIC18F2520/4520). 2. A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices). 3. I/O ports (3 bidirectional ports on 28-pin devices, 5 bidirectional ports on 40/44-pin devices). 4. CCP and Enhanced CCP implementation (28-pin devices have 2 standard CCP modules, 40/44-pin devices have one standard CCP module and one ECCP module). 5. Parallel Slave Port (present only on 40/44-pin devices). All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. Like all Microchip PIC18 devices, members of the PIC18F2420/2520/4420/4520 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2420), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by “LF” (such as PIC18LF2420), function over an extended VDD range of 2.0V to 5.5V. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 9 PIC18F2420/2520/4420/4520 TABLE 1-1: DEVICE FEATURES Features PIC18F2420 PIC18F2520 PIC18F4420 PIC18F4520 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16384 32768 16384 32768 Program Memory (Instructions) 8192 16384 8192 16384 Data Memory (Bytes) 768 1536 768 1536 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 2 2 1 1 Enhanced Capture/Compare/PWM Modules 0 0 1 1 Serial Communications MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART Parallel Communications (PSP) No No Yes Yes 10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Programmable High/Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled Packages 28-pin PDIP 28-pin SOIC 28-pin QFN 28-pin PDIP 28-pin SOIC 28-pin QFN 40-pin PDIP 44-pin QFN 44-pin TQFP 40-pin PDIP 44-pin QFN 44-pin TQFP PIC18F2420/2520/4420/4520 DS39631B-page 10 Preliminary © 2007 Microchip Technology Inc. FIGURE 1-1: PIC18F2420/2520 (28-PIN) BLOCK DIAGRAM Instruction Decode and Control PORTA PORTB PORTC RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RB0/INT0/FLT0/AN12 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 RB1/INT1/AN10 Data Latch Data Memory ( 3.9 Kbytes ) Address Latch Data Address<12> 12 BSR FSR0 Access FSR1 FSR2 inc/dec logic Address 4 12 4 PCH PCL PCLATH 8 31 Level Stack Program Counter PRODH PRODL 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (16/32 Kbytes) Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 ROM Latch RB2/INT2/AN8 RB3/AN9/CCP2(1) PCLATU PCU OSC2/CLKO(3)/RA6 Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD Comparator MSSP EUSART 10-bit ADC Timer0 Timer1 Timer2 Timer3 CCP2 HLVD CCP1 BOR Data EEPROM W Instruction Bus <16> STKPTR Bank 8 State machine control signals Decode 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1(3) OSC2(3) VDD, Brown-out Reset Internal Oscillator Fail-Safe Clock Monitor Precision Reference Band Gap VSS MCLR(2) Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger T1OSO OSC1/CLKI(3)/RA7 T1OSI PORTE MCLR/VPP/RE3(2) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 11 PIC18F2420/2520/4420/4520 FIGURE 1-2: PIC18F4420/4520 (40/44-PIN) BLOCK DIAGRAM Instruction Decode and Control Data Latch Data Memory ( 3.9 Kbytes ) Address Latch Data Address<12> 12 BSR FSR0 Access FSR1 FSR2 inc/dec logic Address 4 12 4 PCH PCL PCLATH 8 31 Level Stack Program Counter PRODH PRODL 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (16/32 Kbytes) Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 ROM Latch PORTD RD0/PSP0 PCLATU PCU PORTE MCLR/VPP/RE3(2) RE2/CS/AN7 RE0/RD/AN5 RE1/WR/AN6 Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. :RD4/PSP4 Comparator MSSP EUSART 10-bit ADC Timer0 Timer1 Timer2 Timer3 CCP2 HLVD ECCP1 BOR Data EEPROM W Instruction Bus <16> STKPTR Bank 8 State machine control signals Decode 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1(3) OSC2(3) VDD, Brown-out Reset Internal Oscillator Fail-Safe Clock Monitor Precision Reference Band Gap VSS MCLR(2) Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger T1OSI T1OSO RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D PORTA PORTB PORTC RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RB0/INT0/FLT0/AN12 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2(1) OSC2/CLKO(3)/RA6 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD OSC1/CLKI(3)/RA7 PIC18F2420/2520/4420/4520 DS39631B-page 12 Preliminary © 2007 Microchip Technology Inc. TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type PDIP, Description SOIC QFN MCLR/VPP/RE3 MCLR VPP RE3 1 26 I P I ST ST Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. OSC1/CLKI/RA7 OSC1 CLKI RA7 9 6 I I I/O ST CMOS TTL Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. OSC2/CLKO/RA6 OSC2 CLKO RA6 10 7 O O I/O — — TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 13 PIC18F2420/2520/4420/4520 PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 27 I/O I TTL Analog Digital I/O. Analog input 0. RA1/AN1 RA1 AN1 3 28 I/O I TTL Analog Digital I/O. Analog input 1. RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 1 I/O I I O TTL Analog Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. Comparator reference voltage output. RA3/AN3/VREF+ RA3 AN3 VREF+ 5 2 I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. RA4/T0CKI/C1OUT RA4 T0CKI C1OUT 6 3 I/O I O ST ST — Digital I/O. Timer0 external clock input. Comparator 1 output. RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT 7 4 I/O I I I O TTL Analog TTL Analog — Digital I/O. Analog input 4. SPI™ slave select input. High/Low-Voltage Detect input. Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type PDIP, Description SOIC QFN Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. PIC18F2420/2520/4420/4520 DS39631B-page 14 Preliminary © 2007 Microchip Technology Inc. PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 RB0 INT0 FLT0 AN12 21 18 I/O I I I TTL ST ST Analog Digital I/O. External interrupt 0. PWM Fault input for CCP1. Analog input 12. RB1/INT1/AN10 RB1 INT1 AN10 22 19 I/O I I TTL ST Analog Digital I/O. External interrupt 1. Analog input 10. RB2/INT2/AN8 RB2 INT2 AN8 23 20 I/O I I TTL ST Analog Digital I/O. External interrupt 2. Analog input 8. RB3/AN9/CCP2 RB3 AN9 CCP2(1) 24 21 I/O I I/O TTL Analog ST Digital I/O. Analog input 9. Capture 2 input/Compare 2 output/PWM 2 output. RB4/KBI0/AN11 RB4 KBI0 AN11 25 22 I/O I I TTL TTL Analog Digital I/O. Interrupt-on-change pin. Analog input 11. RB5/KBI1/PGM RB5 KBI1 PGM 26 23 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC RB6 KBI2 PGC 27 24 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD RB7 KBI3 PGD 28 25 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type PDIP, Description SOIC QFN Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 15 PIC18F2420/2520/4420/4520 PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 11 8 I/O O I ST — ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 12 9 I/O I I/O ST Analog ST Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM 2 output. RC2/CCP1 RC2 CCP1 13 10 I/O I/O ST ST Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output. RC3/SCK/SCL RC3 SCK SCL 14 11 I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI™ mode. Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA RC4 SDI SDA 15 12 I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. RC5/SDO RC5 SDO 16 13 I/O O ST — Digital I/O. SPI data out. RC6/TX/CK RC6 TX CK 17 14 I/O O I/O ST — ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). RC7/RX/DT RC7 RX DT 18 15 I/O I I/O ST ST ST Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). RE3 — — — — See MCLR/VPP/RE3 pin. VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins. TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type PDIP, Description SOIC QFN Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. PIC18F2420/2520/4420/4520 DS39631B-page 16 Preliminary © 2007 Microchip Technology Inc. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP MCLR/VPP/RE3 MCLR VPP RE3 1 18 18 I P I ST ST Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. OSC1/CLKI/RA7 OSC1 CLKI RA7 13 32 30 I I I/O ST CMOS TTL Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; analog otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. OSC2/CLKO/RA6 OSC2 CLKO RA6 14 33 31 O O I/O — — TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 17 PIC18F2420/2520/4420/4520 PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 19 19 I/O I TTL Analog Digital I/O. Analog input 0. RA1/AN1 RA1 AN1 3 20 20 I/O I TTL Analog Digital I/O. Analog input 1. RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 21 21 I/O I I O TTL Analog Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. Comparator reference voltage output. RA3/AN3/VREF+ RA3 AN3 VREF+ 5 22 22 I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. RA4/T0CKI/C1OUT RA4 T0CKI C1OUT 6 23 23 I/O I O ST ST — Digital I/O. Timer0 external clock input. Comparator 1 output. RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT 7 24 24 I/O I I I O TTL Analog TTL Analog — Digital I/O. Analog input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. PIC18F2420/2520/4420/4520 DS39631B-page 18 Preliminary © 2007 Microchip Technology Inc. PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 RB0 INT0 FLT0 AN12 33 9 8 I/O I I I TTL ST ST Analog Digital I/O. External interrupt 0. PWM Fault input for Enhanced CCP1. Analog input 12. RB1/INT1/AN10 RB1 INT1 AN10 34 10 9 I/O I I TTL ST Analog Digital I/O. External interrupt 1. Analog input 10. RB2/INT2/AN8 RB2 INT2 AN8 35 11 10 I/O I I TTL ST Analog Digital I/O. External interrupt 2. Analog input 8. RB3/AN9/CCP2 RB3 AN9 CCP2(1) 36 12 11 I/O I I/O TTL Analog ST Digital I/O. Analog input 9. Capture 2 input/Compare 2 output/PWM 2 output. RB4/KBI0/AN11 RB4 KBI0 AN11 37 14 14 I/O I I TTL TTL Analog Digital I/O. Interrupt-on-change pin. Analog input 11. RB5/KBI1/PGM RB5 KBI1 PGM 38 15 15 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC RB6 KBI2 PGC 39 16 16 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD RB7 KBI3 PGD 40 17 17 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 19 PIC18F2420/2520/4420/4520 PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 15 34 32 I/O O I ST — ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 16 35 35 I/O I I/O ST CMOS ST Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM 2 output. RC2/CCP1/P1A RC2 CCP1 P1A 17 36 36 I/O I/O O ST ST — Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output. Enhanced CCP1 output. RC3/SCK/SCL RC3 SCK SCL 18 37 37 I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI™ mode. Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA RC4 SDI SDA 23 42 42 I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. RC5/SDO RC5 SDO 24 43 43 I/O O ST — Digital I/O. SPI data out. RC6/TX/CK RC6 TX CK 25 44 44 I/O O I/O ST — ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). RC7/RX/DT RC7 RX DT 26 1 1 I/O I I/O ST ST ST Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. PIC18F2420/2520/4420/4520 DS39631B-page 20 Preliminary © 2007 Microchip Technology Inc. PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0 RD0 PSP0 19 38 38 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD1/PSP1 RD1 PSP1 20 39 39 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD2/PSP2 RD2 PSP2 21 40 40 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD3/PSP3 RD3 PSP3 22 41 41 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD4/PSP4 RD4 PSP4 27 2 2 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD5/PSP5/P1B RD5 PSP5 P1B 28 3 3 I/O I/O O ST TTL — Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. RD6/PSP6/P1C RD6 PSP6 P1C 29 4 4 I/O I/O O ST TTL — Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. RD7/PSP7/P1D RD7 PSP7 P1D 30 5 5 I/O I/O O ST TTL — Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 21 PIC18F2420/2520/4420/4520 PORTE is a bidirectional I/O port. RE0/RD/AN5 RE0 RD AN5 8 25 25 I/O I I ST TTL Analog Digital I/O. Read control for Parallel Slave Port (see also WR and CS pins). Analog input 5. RE1/WR/AN6 RE1 WR AN6 9 26 26 I/O I I ST TTL Analog Digital I/O. Write control for Parallel Slave Port (see CS and RD pins). Analog input 6. RE2/CS/AN7 RE2 CS AN7 10 27 27 I/O I I ST TTL Analog Digital I/O. Chip Select control for Parallel Slave Port (see related RD and WR). Analog input 7. RE3 — — — — — See MCLR/VPP/RE3 pin. VSS 12, 31 6, 30, 31 6, 29 P — Ground reference for logic and I/O pins. VDD 11, 32 7, 8, 28, 29 7, 28 P — Positive supply for logic and I/O pins. NC — 13 12, 13, 33, 34 — — No connect. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. PIC18F2420/2520/4420/4520 DS39631B-page 22 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 23 PIC18F2420/2520/4420/4520 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F2420/2520/4420/4520 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. LP Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6. RCIO External Resistor/Capacitor with I/O on RA6 7. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 8. INTIO2 Internal Oscillator with I/O on RA6 and RA7 9. EC External Clock with FOSC/4 output 10. ECIO External Clock with I/O on RA6 2.2 Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. Typical Capacitor Values Used: Mode Freq OSC1 OSC2 XT 3.58 MHz 4.19 MHz 4 MHz 4 MHz 15 pF 15 pF 30 pF 50 pF 15 pF 15 pF 30 pF 50 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 2-2 for additional information. Note: When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330Ω. Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen. C1(1) C2(1) XTAL OSC2 OSC1 RF(3) Sleep To Logic PIC18FXXXX RS(2) Internal PIC18F2420/2520/4420/4520 DS39631B-page 24 Preliminary © 2007 Microchip Technology Inc. TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2. FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) 2.3 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC Oscillator mode. FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-4 shows the pin connections for the ECIO Oscillator mode. FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) Osc Type Crystal Freq Typical Capacitor Values Tested: C1 C2 LP 32 kHz 30 pF 30 pF XT 1 MHz 4 MHz 15 pF 15 pF 15 pF 15 pF HS 4 MHz 10 MHz 20 MHz 25 MHz 25 MHz 15 pF 15 pF 15 pF 0 pF 15 pF 15 pF 15 pF 15 pF 5 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 32 kHz 4 MHz 25 MHz 10 MHz 1 MHz 20 MHz Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. OSC1 Open OSC2 Clock from Ext. System PIC18FXXXX (HS Mode) OSC1/CLKI FOSC/4 OSC2/CLKO Clock from Ext. System PIC18FXXXX OSC1/CLKI RA6 I/O (OSC2) Clock from Ext. System PIC18FXXXX © 2007 Microchip Technology Inc. Preliminary DS39631B-page 25 PIC18F2420/2520/4420/4520 2.4 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors: • supply voltage • values of the external resistor (REXT) and capacitor (CEXT) • operating temperature Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations. These are due to factors such as: • normal manufacturing variation • difference in lead frame capacitance between package types (especially for low CEXT values) • variations within the tolerance of limits of REXT and CEXT In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-5 shows how the R/C combination is connected. FIGURE 2-5: RC OSCILLATOR MODE The RCIO Oscillator mode (Figure 2-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). FIGURE 2-6: RCIO OSCILLATOR MODE 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.5.1 HSPLL OSCILLATOR MODE The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode. The PLL is only available to the crystal oscillator when the FOSC3:FOSC0 configuration bits are programmed for HSPLL mode (= 0110). FIGURE 2-7: PLL BLOCK DIAGRAM (HS MODE) 2.5.2 PLL AND INTOSC The PLL is also available to the internal oscillator block in selected oscillator modes. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the PLL is described in Section 2.6.4 “PLL in INTOSC Modes”. OSC2/CLKO CEXT REXT PIC18FXXXX OSC1 FOSC/4 Internal Clock VDD VSS Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF CEXT REXT PIC18FXXXX OSC1 Internal Clock VDD VSS Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF RA6 I/O (OSC2) MUX VCO Loop Filter Crystal Osc OSC2 OSC1 PLL Enable FIN FOUT SYSCLK Phase Comparator HS Oscillator Enable ÷4 (from Configuration Register 1H) HS Mode PIC18F2420/2520/4420/4520 DS39631B-page 26 Preliminary © 2007 Microchip Technology Inc. 2.6 Internal Oscillator Block The PIC18F2420/2520/4420/4520 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of clock frequencies from 31 kHz to 4 MHz. The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC), which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: • Power-up Timer • Fail-Safe Clock Monitor • Watchdog Timer • Two-Speed Start-up These features are discussed in greater detail in Section 23.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 30). 2.6.1 INTIO MODES Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: • In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. 2.6.2 INTOSC OUTPUT FREQUENCY The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. 2.6.3 OSCTUNE REGISTER The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 2-1). When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 μs = 256 μs). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register also implements the INTSRC and PLLEN bits, which control certain features of the internal oscillator block. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in greater detail in Section 2.7.1 “Oscillator Control Register”. The PLLEN bit controls the operation of the frequency multiplier, PLL, in internal oscillator modes. 2.6.4 PLL IN INTOSC MODES The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator. When enabled, the PLL produces a clock speed of up to 32 MHz. Unlike HSPLL mode, the PLL is controlled through software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. The PLL is available when the device is configured to use the internal oscillator block as its primary clock source (FOSC3:FOSC0 = 1001 or 1000). Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). If both of these conditions are not met, the PLL is disabled. The PLLEN control bit is only functional in those internal oscillator modes where the PLL is available. In all other modes, it is forced to ‘0’ and is effectively unavailable. 2.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. Three compensation techniques are discussed in Section 2.6.5.1 “Compensating with the USART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP Module in Capture Mode”, but other techniques may be used. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 27 PIC18F2420/2520/4420/4520 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER 2.6.5.1 Compensating with the USART An adjustment may be required when the USART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. 2.6.5.2 Compensating with the Timers This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2.6.5.3 Compensating with the CCP Module in Capture Mode A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4 MHz and 8 MHz only) 0 = PLL disabled Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details. bit 5 Unimplemented: Read as ‘0’ bit 4-0 TUN4:TUN0: Frequency Tuning bits 01111 = Maximum frequency • • • • 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • • • 10000 = Minimum frequency Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 28 Preliminary © 2007 Microchip Technology Inc. 2.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2420/2520/ 4420/4520 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2420/2520/4420/4520 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power managed operating modes are available. Essentially, there are three clock sources for these devices: • Primary oscillators • Secondary oscillators • Internal oscillator block The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined by the FOSC3:FOSC0 configuration bits. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power managed mode. PIC18F2420/2520/4420/4520 devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all power managed modes, is often the time base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 12.3 “Timer1 Oscillator”. In addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2420/2520/4420/4520 devices are shown in Figure 2-8. See Section 23.0 “Special Features of the CPU” for Configuration register details. FIGURE 2-8: PIC18F2420/2520/4420/4520 CLOCK DIAGRAM PIC18F2420/2520/4420/4520 4 x PLL FOSC3:FOSC0 Secondary Oscillator T1OSCEN Enable Oscillator T1OSO T1OSI Clock Source Option for other Modules OSC1 OSC2 Sleep HSPLL, INTOSC/PLL LP, XT, HS, RC, EC T1OSC CPU Peripherals IDLEN Postscaler MUX MUX 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 250 kHz OSCCON<6:4> 111 110 101 100 011 010 001 000 31 kHz INTRC Source Internal Oscillator Block WDT, PWRT, FSCM 8 MHz Internal Oscillator (INTOSC) OSCCON<6:4> Clock Control OSCCON<1:0> Source 8 MHz 31 kHz (INTRC) OSCTUNE<6> 0 1 OSCTUNE<7> and Two-Speed Start-up Primary Oscillator © 2007 Microchip Technology Inc. Preliminary DS39631B-page 29 PIC18F2420/2520/4420/4520 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the device clock’s operation, both in full power operation and in power managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Frequency Select bits (IRCF2:IRCF0) select the frequency output of the internal oscillator block to drive the device clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the frequencies derived from the INTOSC postscaler (31.25 kHz to 4 MHz). If the internal oscillator block is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. On device Resets, the default output frequency of the internal oscillator block is set at 1 MHz. When a nominal output frequency of 31 kHz is selected (IRCF2:IRCF0 = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25 kHz clock source by enabling the divide-by-256 output of the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31 kHz) as the clock source. This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the device clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 “Power Managed Modes”. 2.7.2 OSCILLATOR TRANSITIONS PIC18F2420/2520/4420/4520 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power Managed Modes”. Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the Timer1 oscillator starts. PIC18F2420/2520/4420/4520 DS39631B-page 30 Preliminary © 2007 Microchip Technology Inc. REGISTER 2-2: OSCCON REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz(3) 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator start-up time-out timer has expired; primary oscillator is running 0 = Oscillator start-up time-out timer is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Note 1: Reset state depends on state of the IESO configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 31 PIC18F2420/2520/4420/4520 2.8 Effects of Power Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power managed modes if required to clock Timer1 or Timer3. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power managed mode (see Section 23.2 “Watchdog Timer (WDT)”, Section 23.3 “Two-Speed Start-up” and Section 23.4 “Fail-Safe Clock Monitor” for more information on WDT, Fail-Safe Clock Monitor and Two- Speed Start-up). The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is disabled if the clock is provided directly from the INTRC output. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a realtime clock. Other features may be operating that do not require a device clock source (i.e., SSP slave, PSP, INTn pins and others). Peripherals that may add significant current consumption are listed in Section 26.2 “DC Characteristics”. 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.5 “Device Reset Timers”. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 26-10). It is enabled by clearing (= 0) the PWRTEN configuration bit. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of interval TCSD (parameter 38, Table 26-10), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source. TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. PIC18F2420/2520/4420/4520 DS39631B-page 32 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS39631B-page 33 PIC18F2420/2520/4420/4520 3.0 POWER MANAGED MODES PIC18F2420/2520/4420/4520 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power managed modes: • Run modes • Idle modes • Sleep mode These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power managed modes include several powersaving features offered on previous PIC® devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC devices, where all device clocks are stopped. 3.1 Selecting Power Managed Modes Selecting a power managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS1:SCS0 bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power managed modes. They are: • the primary clock, as defined by the FOSC3:FOSC0 configuration bits • the secondary clock (the Timer1 oscillator) • the internal oscillator block (for RC modes) 3.1.2 ENTERING POWER MANAGED MODES Switching from one power managed mode to another begins by loading the OSCCON register. The SCS1:SCS0 bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 3.1.3 “Clock Transitions and Status Indicators” and subsequent sections. Entry to the Power Managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. TABLE 3-1: POWER MANAGED MODES Mode OSCCON Bits Module Clocking IDLEN(1) Available Clock and Oscillator Source <7> SCS1:SCS0 <1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block(2). This is the normal full power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. PIC18F2420/2520/4420/4520 DS39631B-page 34 © 2007 Microchip Technology Inc. 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If none of these bits are set, then either the INTRC clock source is clocking the device, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source by the FOSC3:FOSC0 configuration bits, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering another RC Power Managed mode at the same frequency would clear the OSTS bit. 3.1.4 MULTIPLE SLEEP COMMANDS The power managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power managed mode specified by the new setting. 3.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 3.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full power execution mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up is enabled (see Section 23.3 “Two-Speed Start-up” for details). In this mode, the OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 “Oscillator Control Register”). 3.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by setting the SCS1:SCS0 bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS1:SCS0 bits are set to ‘01’, entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. © 2007 Microchip Technology Inc. DS39631B-page 35 PIC18F2420/2520/4420/4520 FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. This mode is entered by setting the SCS1 bit to ‘1’. Although it is ignored, it is recommended that the SCS0 bit also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to the INTOSC multiplexer (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed. Q2 Q3 Q4 OSC1 Peripheral Program Q1 T1OSI Q1 Counter Clock CPU Clock PC PC + 2 1 2 3 n-1 n Clock Transition(1) Q2 Q3 Q4 Q1 Q2 Q3 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. Q1 Q3 Q4 OSC1 Peripheral Program PC T1OSI PLL Clock Q1 PC + 4 Q2 Output Q3 Q4 Q1 CPU Clock PC + 2 Clock Counter Q2 Q2 Q3 Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. SCS1:SCS0 bits changed TPLL(1) 1 2 n-1 n Clock OSTS bit set Transition(2) TOST(1) Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. PIC18F2420/2520/4420/4520 DS39631B-page 36 © 2007 Microchip Technology Inc. If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output) or if INTSRC is set, the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST. If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q2 Q3 Q4 OSC1 Peripheral Program Q1 INTRC Q1 Counter Clock CPU Clock PC PC + 2 1 2 3 n-1 n Clock Transition(1) Q2 Q3 Q4 Q1 Q2 Q3 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. Q1 Q3 Q4 OSC1 Peripheral Program PC INTOSC PLL Clock Q1 PC + 4 Q2 Output Q3 Q4 Q1 CPU Clock PC + 2 Clock Counter Q2 Q2 Q3 Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. SCS1:SCS0 bits changed TPLL(1) 1 2 n-1 n Clock OSTS bit set Transition(2) Multiplexer TOST(1) © 2007 Microchip Technology Inc. DS39631B-page 37 PIC18F2420/2520/4420/4520 3.3 Sleep Mode The Power Managed Sleep mode in the PIC18F2420/ 2520/4420/4520 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS1:SCS0 bits becomes ready (see Figure 3-6), or it will be clocked from the internal oscillator block if either the Two- Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 23.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 26-10) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 OSC1 Peripheral Sleep Program Q1 Q1 Counter Clock CPU Clock PC PC + 2 Q3 Q4 Q1 Q2 OSC1 Peripheral Program PC PLL Clock Q3 Q4 Output CPU Clock Q1 Q2 Q3 Q4 Q1 Q2 Clock Counter PC + 6 PC + 4 Q1 Q2 Q3 Q4 Wake Event Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. TOST(1) TPLL(1) OSTS bit set PC + 2 PIC18F2420/2520/4420/4520 DS39631B-page 38 © 2007 Microchip Technology Inc. 3.4.1 PRI_IDLE MODE This mode is unique among the three Low-Power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC3:FOSC0 configuration bits. The OSTS bit remains set (see Figure 3-7). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval TCSD is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8). 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS1:SCS0 bits to ‘01’ and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 3-8). FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. Q1 Peripheral Program PC PC + 2 OSC1 Q3 Q4 Q1 CPU Clock Clock Counter Q2 OSC1 Peripheral Program PC CPU Clock Q1 Q3 Q4 Clock Counter Q2 Wake Event TCSD © 2007 Microchip Technology Inc. DS39631B-page 39 PIC18F2420/2520/4420/4520 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. Although its value is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to any non-zero value, or the INTSRC bit is set, the INTOSC output is enabled. The IOFS bit becomes set, after the INTOSC output becomes stable, after an interval of TIOBST (parameter 39, Table 26-10). Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value, or INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits and INTSRC are all clear, the INTOSC output will not be enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wakeup. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power managed modes. The clocking subsystem actions are discussed in each of the power managed modes (see Section 3.2 “Run Modes”, Section 3.3 “Sleep Mode” and Section 3.4 “Idle Modes”). 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). A fixed delay of interval TCSD following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power managed mode (see Section 3.2 “Run Modes” and Section 3.3 “Sleep Mode”). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 23.2 “Watchdog Timer (WDT)”). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source. 3.5.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. If the internal oscillator block is the new clock source, the IOFS bit is set instead. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are summarized in Table 3-2. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 23.3 “Two-Speed Start-up”) or Fail-Safe Clock Monitor (see Section 23.4 “Fail-Safe Clock Monitor”) is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. PIC18F2420/2520/4420/4520 DS39631B-page 40 © 2007 Microchip Technology Inc. 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped and • the primary clock source is not any of the LP, XT, HS or HSPLL modes. In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source before Wake-up Clock Source after Wake-up Exit Delay Clock Ready Status Bit (OSCCON) Primary Device Clock (PRI_IDLE mode) LP, XT, HS TCSD HSPLL (1) OSTS EC, RC INTOSC(2) IOFS T1OSC or INTRC(1) LP, XT, HS TOST(3) HSPLL TOST + trc OSTS (3) EC, RC TCSD(1) INTOSC(1) TIOBST(4) IOFS INTOSC(2) LP, XT, HS TOST(4) HSPLL TOST + trc OSTS (3) EC, RC TCSD(1) INTOSC(1) None IOFS None (Sleep mode) LP, XT, HS TOST(3) HSPLL TOST + trc OSTS (3) EC, RC TCSD(1) INTOSC(1) TIOBST(4) IOFS Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section 3.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz. 2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies. 3: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is also designated as TPLL. 4: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 41 PIC18F2420/2520/4420/4520 4.0 RESET The PIC18F2420/2520/4420/4520 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.2.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 23.2 “Watchdog Timer (WDT)”. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 “Reset State of Registers”. The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 9.0 “Interrupts”. BOR is covered in Section 4.4 “Brown-out Reset (BOR)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR VDD OSC1 WDT Time-out VDD Rise Detect OST/PWRT INTRC(1) POR Pulse OST 10-bit Ripple Counter PWRT 11-bit Ripple Counter Enable OST(2) Enable PWRT Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. Brown-out Reset BOREN RESET Instruction Stack Pointer Stack Full/Underflow Reset Sleep ( )_IDLE 1024 Cycles 32 μs 65.5 ms MCLRE S R Q Chip_Reset PIC18F2420/2520/4420/4520 DS39631B-page 42 Preliminary © 2007 Microchip Technology Inc. REGISTER 4-1: RCON REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN1:BOREN0 = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 4.6 “Reset State of Registers” for additional information. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). © 2007 Microchip Technology Inc. Preliminary DS39631B-page 43 PIC18F2420/2520/4420/4520 4.2 Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2420/2520/4420/4520 devices, the MCLR input can be disabled with the MCLRE configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 “PORTE, TRISE and LATE Registers” for more information. 4.3 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure that the voltage drop across R does not violate the device’s electrical specification. 3: R1 ≥ 1 kΩ will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). C R1 D R VDD MCLR PIC18FXXXX VDD PIC18F2420/2520/4420/4520 DS39631B-page 44 Preliminary © 2007 Microchip Technology Inc. 4.4 Brown-out Reset (BOR) PIC18F2420/2520/4420/4520 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0, except ‘00’), any drop of VDD below VBOR (parameter D005) for greater than TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. BOR and the Power-on Timer (PWRT) are independently configured. Enabling BOR Reset does not automatically enable the PWRT. 4.4.1 SOFTWARE ENABLED BOR When BOREN1:BOREN0 = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’. Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. 4.4.2 DETECTING BOR When BOR is enabled, the BOR bit always resets to ‘0’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to ‘1’ in software immediately after any POR event. If BOR is ‘0’ while POR is ‘1’, it can be reliably assumed that a BOR event has occurred. 4.4.3 DISABLING BOR IN SLEEP MODE When BOREN1:BOREN0 = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. TABLE 4-1: BOR CONFIGURATIONS Note: Even when BOR is under software control, the BOR Reset voltage level is still set by the BORV1:BORV0 configuration bits. It cannot be changed in software. BOR Configuration Status of SBOREN (RCON<6>) BOR Operation BOREN1 BOREN0 0 0 Unavailable BOR disabled; must be enabled by reprogramming the configuration bits. 0 1 Available BOR enabled in software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the configuration bits. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 45 PIC18F2420/2520/4420/4520 4.5 Device Reset Timers PIC18F2420/2520/4420/4520 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18F2420/2520/ 4420/4520 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation. See DC parameter 33 for details. The PWRT is enabled by clearing the PWRTEN configuration bit. 4.5.2 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power managed modes. 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 4.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 1. After the POR pulse has cleared, PWRT time-out is invoked (if enabled). 2. Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 4-3 through 4-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration Power-up(2) and Brown-out Exit from PWRTEN = 0 PWRTEN = 1 Power Managed Mode HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. PIC18F2420/2520/4420/4520 DS39631B-page 46 Preliminary © 2007 Microchip Technology Inc. FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TPWRT TOST © 2007 Microchip Technology Inc. Preliminary DS39631B-page 47 PIC18F2420/2520/4420/4520 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 0V 5V TPWRT TOST TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET PLL TIME-OUT TPLL Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. PIC18F2420/2520/4420/4520 DS39631B-page 48 Preliminary © 2007 Microchip Technology Inc. 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset. Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Condition Program Counter RCON Register STKPTR Register SBOREN RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR during Power Managed Run Modes 0000h u(2) u 1 u u u u u MCLR during Power Managed Idle Modes and Sleep Mode 0000h u(2) u 1 0 u u u u WDT Time-out during Full Power or Power Managed Run Mode 0000h u(2) u 0 u u u u u MCLR during Full Power Execution 0000h u(2) u u u u u u u Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset (STVREN = 1) 0000h u(2) u u u u u u 1 Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u(2) u u u u u u 1 WDT Time-out during Power Managed Idle or Sleep Modes PC + 2 u(2) u 0 0 u u u u Interrupt Exit from Power Managed Modes PC + 2(1) u(2) u u 0 u u u u Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is ‘0’. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 49 PIC18F2420/2520/4420/4520 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 2420 2520 4420 4520 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2420 2520 4420 4520 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2420 2520 4420 4520 ---0 0000 ---0 0000 ---u uuuu PCLATH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PCL 2420 2520 4420 4520 0000 0000 0000 0000 PC + 2(2) TBLPTRU 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu TBLPTRH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TABLAT 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PRODH 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2420 2520 4420 4520 0000 000x 0000 000u uuuu uuuu(1) INTCON2 2420 2520 4420 4520 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 2420 2520 4420 4520 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 2420 2520 4420 4520 N/A N/A N/A POSTINC0 2420 2520 4420 4520 N/A N/A N/A POSTDEC0 2420 2520 4420 4520 N/A N/A N/A PREINC0 2420 2520 4420 4520 N/A N/A N/A PLUSW0 2420 2520 4420 4520 N/A N/A N/A FSR0H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu FSR0L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2420 2520 4420 4520 N/A N/A N/A POSTINC1 2420 2520 4420 4520 N/A N/A N/A POSTDEC1 2420 2520 4420 4520 N/A N/A N/A PREINC1 2420 2520 4420 4520 N/A N/A N/A PLUSW1 2420 2520 4420 4520 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. PIC18F2420/2520/4420/4520 DS39631B-page 50 Preliminary © 2007 Microchip Technology Inc. FSR1H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu FSR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu INDF2 2420 2520 4420 4520 N/A N/A N/A POSTINC2 2420 2520 4420 4520 N/A N/A N/A POSTDEC2 2420 2520 4420 4520 N/A N/A N/A PREINC2 2420 2520 4420 4520 N/A N/A N/A PLUSW2 2420 2520 4420 4520 N/A N/A N/A FSR2H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu FSR2L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2420 2520 4420 4520 ---x xxxx ---u uuuu ---u uuuu TMR0H 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TMR0L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu OSCCON 2420 2520 4420 4520 0100 q000 0100 q000 uuuu uuqu HLVDCON 2420 2520 4420 4520 0-00 0101 0-00 0101 u-uu uuuu WDTCON 2420 2520 4420 4520 ---- ---0 ---- ---0 ---- ---u RCON(4) 2420 2520 4420 4520 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2420 2520 4420 4520 0000 0000 u0uu uuuu uuuu uuuu TMR2 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PR2 2420 2520 4420 4520 1111 1111 1111 1111 1111 1111 T2CON 2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu SSPBUF 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPCON1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPCON2 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 51 PIC18F2420/2520/4420/4520 ADRESH 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu ADCON1 2420 2520 4420 4520 --00 0qqq --00 0qqq --uu uuuu ADCON2 2420 2520 4420 4520 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu CCPR2H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu BAUDCON 2420 2520 4420 4520 01-0 0-00 01-0 0-00 --uu uuuu PWM1CON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 0000 00-- 0000 00-- uuuu uu-- CVRCON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu CMCON 2420 2520 4420 4520 0000 0111 0000 0111 uuuu uuuu TMR3H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 2420 2520 4420 4520 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SPBRG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu RCREG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TXREG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TXSTA 2420 2520 4420 4520 0000 0010 0000 0010 uuuu uuuu RCSTA 2420 2520 4420 4520 0000 000x 0000 000x uuuu uuuu EEADR 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu EEDATA 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu EECON2 2420 2520 4420 4520 0000 0000 0000 0000 0000 0000 EECON1 2420 2520 4420 4520 xx-0 x000 uu-0 u000 uu-0 u000 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. PIC18F2420/2520/4420/4520 DS39631B-page 52 Preliminary © 2007 Microchip Technology Inc. IPR2 2420 2520 4420 4520 11-1 1111 11-1 1111 uu-u uuuu PIR2 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu(1) PIE2 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu IPR1 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu 2420 2520 4420 4520 -111 1111 -111 1111 -uuu uuuu PIR1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(1) 2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu(1) PIE1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu OSCTUNE 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu TRISE 2420 2520 4420 4520 0000 -111 0000 -111 uuuu -uuu TRISD 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISC 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISB 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2420 2520 4420 4520 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATE 2420 2520 4420 4520 ---- -xxx ---- -uuu ---- -uuu LATD 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 2420 2520 4420 4520 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTE 2420 2520 4420 4520 ---- xxxx ---- uuuu ---- uuuu PORTD 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2420 2520 4420 4520 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 53 PIC18F2420/2520/4420/4520 5.0 MEMORY ORGANIZATION There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 7.0 “Data EEPROM Memory”. 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The PIC18F2420 and PIC18F4420 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The PIC18F2520 and PIC18F4520 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for PIC18F2420/2520/ 4420/4520 devices is shown in Figure 5-1. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2420/2520/4420/4520 DEVICES PC<20:0> Stack Level 1 • Stack Level 31 Reset Vector Low Priority Interrupt Vector •• CALL,RCALL,RETURN RETFIE,RETLW 21 0000h 0018h On-Chip Program Memory High Priority Interrupt Vector 0008h User Memory Space 1FFFFFh 4000h 3FFFh Read ‘0’ 200000h PIC18FX4X0 PIC18FX5X0 8000h 7FFFh On-Chip Program Memory Read ‘0’ PIC18F2420/2520/4420/4520 DS39631B-page 54 Preliminary © 2007 Microchip Technology Inc. 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.1.4.1 “Computed GOTO”). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 5.1.2 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, STKPTR. The stack space is not part of either program or data space. The stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-ofstack Special File Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the stack pointer is first incremented and the location pointed to by the stack pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the stack pointer is decremented. The stack pointer is initialized to ‘00000’ after all Resets. There is no RAM associated with the location corresponding to a stack pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed. 5.1.2.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS 00011 001A34h 11111 11110 11101 00010 00001 00000 00010 Return Address Stack <20:0> Top-of-Stack 000D58h TOSU TOSH TOSL 00h 1Ah 34h STKPTR<4:0> Top-of-Stack Registers Stack Pointer © 2007 Microchip Technology Inc. Preliminary DS39631B-page 55 PIC18F2420/2520/4420/4520 5.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the stack pointer value, the STKFUL (stack full) status bit and the STKUNF (stack underflow) status bits. The value of the stack pointer can be 0 through 31. The stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the stack pointer value will be zero. The user may read and write the stack pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. (Refer to Section 23.1 “Configuration Bits” for a description of the device configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the stack pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the stack pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. 5.1.2.3 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the stack pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. REGISTER 5-1: STKPTR REGISTER Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 56 Preliminary © 2007 Microchip Technology Inc. 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 5.1.3 FAST REGISTER STACK A fast register stack is provided for the Status, WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction must be executed to save the Status, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack. Example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. EXAMPLE 5-1: FAST REGISTER STACK CODE EXAMPLE 5.1.4 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • Computed GOTO • Table Reads 5.1.4.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 5-2: COMPUTED GOTO USING AN OFFSET VALUE 5.1.4.2 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK •• SUB1 •• RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK MOVF OFFSET, W CALL TABLE ORG nn00h TABLE ADDWF PCL RETLW nnh RETLW nnh RETLW nnh . . . © 2007 Microchip Technology Inc. Preliminary DS39631B-page 57 PIC18F2420/2520/4420/4520 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-3. 5.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-3). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-3: CLOCK/INSTRUCTION CYCLE EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode) PC PC + 2 PC + 4 Fetch INST (PC) Execute INST (PC – 2) Fetch INST (PC + 2) Execute INST (PC) Fetch INST (PC + 4) Execute INST (PC + 2) Internal Phase Clock All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 PIC18F2420/2520/4420/4520 DS39631B-page 58 Preliminary © 2007 Microchip Technology Inc. 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 5.1.1 “Program Counter”). Figure 5-4 shows an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-4 shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 24.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY 5.2.4 TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has ‘1111’ as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence – immediately after the first word – the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 5-4 shows how this works. EXAMPLE 5-4: TWO-WORD INSTRUCTIONS Word Address LSB = 1 LSB = 0 ↓ Program Memory Byte Locations → 000000h 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h Note: See Section 5.6 “PIC18 Instruction Execution and the Extended Instruction Set” for information on two-word instructions in the extended instruction set. CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code © 2007 Microchip Technology Inc. Preliminary DS39631B-page 59 PIC18F2420/2520/4420/4520 5.3 Data Memory Organization The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F2420/ 2520/4420/4520 devices implement all 16 banks. Figure 5-5 shows the data memory organization for the PIC18F2420/2520/4420/4520 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit bank pointer. Most instructions in the PIC18 instruction set make use of the bank pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location’s address; the instruction itself includes the 8 Least Significant bits. Only the four lower bits of the BSR are implemented (BSR3:BSR0). The upper four bits are unused; they will always read ‘0’ and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory; the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is shown in Figure 5-7. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the Status register will still be affected as if the operation was successful. The data memory map in Figure 5-5 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Note: The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information. PIC18F2420/2520/4420/4520 DS39631B-page 60 Preliminary © 2007 Microchip Technology Inc. FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2420/4420 DEVICES Bank 0 Bank 1 Bank 14 Bank 15 BSR<3:0> Data Memory Map = 0000 = 0001 = 1111 080h 07Fh F80h FFFh 00h 7Fh 80h FFh Access Bank When ‘a’ = 0: The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When ‘a’ = 1: The BSR specifies the Bank used by the instruction. F7Fh F00h EFFh 1FFh 100h 0FFh Access RAM 000h FFh 00h FFh 00h FFh 00h GPR GPR SFR Access RAM High Access RAM Low Bank 2 = 0110 = 0010 (SFRs) 2FFh 200h 3FFh 300h 4FFh 400h 5FFh 500h 6FFh 600h 7FFh 700h 8FFh 800h 9FFh 900h AFFh A00h BFFh B00h CFFh C00h DFFh D00h E00h Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h GPR FFh 00h = 0011 = 0100 = 0101 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 Unused Read 00h Unused © 2007 Microchip Technology Inc. Preliminary DS39631B-page 61 PIC18F2420/2520/4420/4520 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2520/4520 DEVICES Bank 0 Bank 1 Bank 14 Bank 15 BSR<3:0> Data Memory Map = 0000 = 0001 = 1111 080h 07Fh F80h FFFh 00h 7Fh 80h FFh Access Bank When ‘a’ = 0: The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When ‘a’ = 1: The BSR specifies the Bank used by the instruction. F7Fh F00h EFFh 1FFh 100h 0FFh Access RAM 000h FFh 00h FFh 00h FFh 00h GPR GPR SFR Access RAM High Access RAM Low Bank 2 = 0110 = 0010 (SFRs) 2FFh 200h 3FFh 300h 4FFh 400h 5FFh 500h 6FFh 600h 7FFh 700h 8FFh 800h 9FFh 900h AFFh A00h BFFh B00h CFFh C00h DFFh D00h E00h Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h GPR FFh 00h = 0011 = 0100 = 0101 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 Unused Read 00h Unused GPR GPR GPR PIC18F2420/2520/4420/4520 DS39631B-page 62 Preliminary © 2007 Microchip Technology Inc. FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 5.3.2 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 128 bytes of memory (00h-7Fh) in Bank 0 and the last 128 bytes of memory (80h-FFh) in Block 15. The lower half is known as the “Access RAM” and is composed of GPRs. This upper half is also where the device’s SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 5-5). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 80h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 80h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST configuration bit = 1). This is discussed in more detail in Section 5.5.3 “Mapping the Access Bank in Indexed Literal Offset Mode”. 5.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. Data Memory Bank Select(2) 7 0 From Opcode(2) 0 0 0 0 000h 100h 200h 300h F00h E00h FFFh Bank 0 Bank 1 Bank 2 Bank 14 Bank 15 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh Bank 3 through Bank 13 0 0 1 1 1 1 1 1 1 1 1 1 7 0 BSR(1) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 63 PIC18F2420/2520/4420/4520 5.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The reset and interrupt registers are described in their respective chapters, while the ALU’s Status register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2420/2520/4420/4520 DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2) FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON(3) F97h —(2) FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3) FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2) FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2) FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2) FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2) FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2) FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE(3) FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on 28-pin devices. PIC18F2420/2520/4420/4520 DS39631B-page 64 Preliminary © 2007 Microchip Technology Inc. TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 54 TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 49, 54 TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 49, 54 STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 49, 55 PCLATU — — — Holding Register for PC<20:16> ---0 0000 49, 54 PCLATH Holding Register for PC<15:8> 0000 0000 49, 54 PCL PC, Low Byte (PC<7:0>) 0000 0000 49, 54 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 76 TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 49, 76 TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 49, 76 TABLAT Program Memory Table Latch 0000 0000 49, 76 PRODH Product Register, High Byte xxxx xxxx 49, 89 PRODL Product Register, Low Byte xxxx xxxx 49, 89 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49, 93 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 49, 94 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 49, 95 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 69 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 69 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 69 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 69 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by W N/A 49, 69 FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 49, 69 FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 49, 69 WREG Working Register xxxx xxxx 49 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 49, 69 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 49, 69 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 49, 69 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 69 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of FSR1 offset by W N/A 49, 69 FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 50, 69 FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 50, 69 BSR — — — — Bank Select Register ---- 0000 50, 59 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 50, 69 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 50, 69 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 50, 69 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 69 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by W N/A 50, 69 FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 50, 69 FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 50, 69 STATUS — — — N OV Z DC C ---x xxxx 50, 67 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 65 PIC18F2420/2520/4420/4520 TMR0H Timer0 Register, High Byte 0000 0000 50, 125 TMR0L Timer0 Register, Low Byte xxxx xxxx 50, 125 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50, 123 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 30, 50 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 50, 245 WDTCON — — — — — — — SWDTEN --- ---0 50, 259 RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 42, 48, 102 TMR1H Timer1 Register, High Byte xxxx xxxx 50, 131 TMR1L Timer1 Register, Low Bytes xxxx xxxx 50, 131 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 127 TMR2 Timer2 Register 0000 0000 50, 134 PR2 Timer2 Period Register 1111 1111 50, 134 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 133 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 50, 169, 170 SSPADD SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 50, 170 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 50, 162, 171 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 163, 172 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50, 173 ADRESH A/D Result Register, High Byte xxxx xxxx 51, 232 ADRESL A/D Result Register, Low Byte xxxx xxxx 51, 232 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 51, 223 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 51, 224 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 51, 225 CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx 51, 140 CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx 51, 140 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 51, 139, 147 CCPR2H Capture/Compare/PWM Register 2, High Byte xxxx xxxx 51, 140 CCPR2L Capture/Compare/PWM Register 2, Low Byte xxxx xxxx 51, 140 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 51, 139 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 51, 204 PWM1CON PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 0000 0000 51, 156 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 0000 0000 51, 157 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 51, 239 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 51, 233 TMR3H Timer3 Register, High Byte xxxx xxxx 51, 137 TMR3L Timer3 Register, Low Byte xxxx xxxx 51, 137 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 51, 135 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. PIC18F2420/2520/4420/4520 DS39631B-page 66 Preliminary © 2007 Microchip Technology Inc. SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 51, 206 SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 51, 206 RCREG EUSART Receive Register 0000 0000 51, 213 TXREG EUSART Transmit Register 0000 0000 51, 211 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 202 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 203 EEADR EEPROM Address Register 0000 0000 51, 74, 83 EEDATA EEPROM Data Register 0000 0000 51, 74, 83 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 51, 74, 83 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 51, 75, 84 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 11-1 1111 52, 101 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 00-0 0000 52, 97 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 00-0 0000 52, 99 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52, 100 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52, 96 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52, 98 OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 27, 52 TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 52, 118 TRISD(2) PORTD Data Direction Control Register 1111 1111 52, 114 TRISC PORTC Data Direction Control Register 1111 1111 52, 111 TRISB PORTB Data Direction Control Register 1111 1111 52, 108 TRISA TRISA7(5) TRISA6(5) Data Direction Control Register for PORTA 1111 1111 52, 105 LATE(2) — — — — — PORTE Data Latch Register (Read and Write to Data Latch) ---- -xxx 52, 117 LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 114 LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 111 LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 108 LATA LATA7(5) LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 105 PORTE — — — — RE3(4) RE2(2) RE1(2) RE0(2) ---- xxxx 52, 117 PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 52, 114 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 52, 111 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52, 108 PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 52, 105 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 67 PIC18F2420/2520/4420/4520 5.3.5 STATUS REGISTER The Status register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the Status register is updated according to the instruction performed. Therefore, the result of an instruction with the Status register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining status bits unchanged (‘000u u1uu’). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status register, because these instructions do not affect the Z, C, DC, OV or N bits in the Status register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 24-2 and Table 24-3. REGISTER 5-2: STATUS REGISTER Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 68 Preliminary © 2007 Microchip Technology Inc. 5.4 Data Addressing Modes While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: • Inherent • Literal • Direct • Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST configuration bit = 1). Its operation is discussed in greater detail in Section 5.5.1 “Indexed Addressing with Literal Offset”. 5.4.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. 5.4.2 DIRECT ADDRESSING Direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of direct addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 “General Purpose Register File”) or a location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation’s results is determined by the destination bit ‘d’. When ‘d’ is ‘1’, the results are stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 5.4.3 INDIRECT ADDRESSING Indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special File Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for indirect addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 5-5. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information. LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H, 1 ; All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2007 Microchip Technology Inc. Preliminary DS39631B-page 69 PIC18F2420/2520/4420/4520 5.4.3.1 FSR Registers and the INDF Operand At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as “virtual” registers: they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient way of using the pointer. Because indirect addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on it stored value. They are: • POSTDEC: accesses the FSR value, then automatically decrements it by 1 afterwards • POSTINC: accesses the FSR value, then automatically increments it by 1 afterwards • PREINC: increments the FSR value by 1, then uses it in the operation • PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the Status register (e.g., Z, N, OV, etc.). FIGURE 5-8: INDIRECT ADDRESSING FSR1H:FSR1L 7 0 Data Memory 000h 100h 200h 300h F00h E00h FFFh Bank 0 Bank 1 Bank 2 Bank 14 Bank 15 Bank 3 through Bank 13 ADDWF, INDF1, 1 7 0 Using an instruction with one of the indirect addressing registers as the operand.... ...uses the 12-bit address stored in the FSR pair associated with that register.... ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. x x x x 1 1 1 0 1 1 0 0 1 1 0 0 PIC18F2420/2520/4420/4520 DS39631B-page 70 Preliminary © 2007 Microchip Technology Inc. The PLUSW register can be used to implement a form of indexed addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.4.3.3 Operations by FSRs on FSRs Indirect addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. Similarly, operations by indirect addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 5.5 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank – that is, most bit-oriented and byte-oriented instructions – can invoke a form of indexed addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0) and • The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in direct addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an address pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 5.5.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use direct addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is ‘1’), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled in shown in Figure 5-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 24.2.1 “Extended Instruction Syntax”. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 71 PIC18F2420/2520/4420/4520 FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations 060h to 07Fh (Bank 0) and F80h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode. When ‘a’ = 0 and f ≤ 5Fh: The instruction executes in Indexed Literal Offset mode. ‘f’ is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where ‘k’ is the same as ‘f’. When ‘a’ = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). ‘f’ is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 000h 060h 100h F00h F80h FFFh Valid range 00h 60h 80h FFh Data Memory Access RAM Bank 0 Bank 1 through Bank 14 Bank 15 SFRs 000h 080h 100h F00h F80h FFFh Data Memory Bank 0 Bank 1 through Bank 14 Bank 15 SFRs FSR2H FSR2L 001001da ffffffff 001001da ffffffff 000h 080h 100h F00h F80h FFFh Data Memory Bank 0 Bank 1 through Bank 14 Bank 15 SFRs for ‘f’ BSR 00000000 080h PIC18F2420/2520/4420/4520 DS39631B-page 72 Preliminary © 2007 Microchip Technology Inc. 5.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user defined “window” that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 5.3.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure 5-10. Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. 5.6 PIC18 Instruction Execution and the Extended Instruction Set Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in Section 24.2 “Extended Instruction Set”. FIGURE 5-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Data Memory 000h 100h 200h F80h F00h FFFh Bank 1 Bank 15 Bank 2 through Bank 14 SFRs 05Fh ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). Locations in Bank 0 from 060h to 07Fh are mapped, as usual, to the middle half of the Access Bank. Special File Registers at F80h through FFFh are mapped to 80h through FFh, as usual. Bank 0 addresses below 5Fh can still be addressed by using the BSR. Access Bank 00h 80h FFh 7Fh Bank 0 SFRs Bank 1 “Window” Bank 0 Bank 0 Window Example Situation: 07Fh 120h 17Fh 5Fh Bank 1 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 73 PIC18F2420/2520/4420/4520 6.0 FLASH PROGRAM MEMORY The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: • Table Read (TBLRD) • Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and places it into the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 “Writing to Flash Program Memory”. Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 6-1: TABLE READ OPERATION Table Pointer(1) Table Latch (8-bit) Program Memory TBLPTRH TBLPTRL TABLAT TBLPTRU Instruction: TBLRD* Note 1: Table Pointer register points to a byte in program memory. Program Memory (TBLPTR) PIC18F2420/2520/4420/4520 DS39631B-page 74 Preliminary © 2007 Microchip Technology Inc. FIGURE 6-2: TABLE WRITE OPERATION 6.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: • EECON1 register • EECON2 register • TABLAT register • TBLPTR registers 6.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register 6-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. The CFGS control bit determines if the access will be to the configuration/calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on configuration registers regardless of EEPGD (see Section 23.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Table Pointer(1) Table Latch (8-bit) TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) TBLPTRU Instruction: TBLWT* Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. Holding Registers Program Memory Note: During normal operation, the WRERR is read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 75 PIC18F2420/2520/4420/4520 REGISTER 6-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 76 Preliminary © 2007 Microchip Technology Inc. 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the configuration bits. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits. 6.2.4 TABLE POINTER BOUNDARIES TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of the 64 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 16 MSbs of the TBLPTR (TBLPTR<21:6>) determine which program memory block of 64 bytes is written to. For more detail, see Section 6.5 “Writing to Flash Program Memory”. When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*- TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write 21 16 15 8 7 0 TABLE ERASE/WRITE TABLE WRITE TABLE READ – TBLPTR<21:0> TBLPTRU TBLPTRH TBLPTRL TBLPTR<21:6> TBLPTR<5:0> © 2007 Microchip Technology Inc. Preliminary DS39631B-page 77 PIC18F2420/2520/4420/4520 6.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD (Even Byte Address) Program Memory (Odd Byte Address) TBLRD TABLAT TBLPTR = xxxxx1 FETCH Instruction Register (IR) Read Register TBLPTR = xxxxx0 MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVFW TABLAT, W ; get data MOVF WORD_ODD PIC18F2420/2520/4420/4520 DS39631B-page 78 Preliminary © 2007 Microchip Technology Inc. 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. 6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1. Load Table Pointer register with address of row being erased. 2. Set the EECON1 register for the erase operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN bit to enable writes; • set FREE bit to enable the erase. 3. Disable interrupts. 4. Write 55h to EECON2. 5. Write 0AAh to EECON2. 6. Set the WR bit. This will begin the row erase cycle. 7. The CPU will stall for duration of the erase (about 2 ms using internal timer). 8. Re-enable interrupts. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts © 2007 Microchip Technology Inc. Preliminary DS39631B-page 79 PIC18F2420/2520/4420/4520 6.5 Writing to Flash Program Memory The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. Read 64 bytes into RAM. 2. Update data values in RAM as necessary. 3. Load Table Pointer register with address being erased. 4. Execute the row erase procedure. 5. Load Table Pointer register with address of first byte being written. 6. Write the 64 bytes into the holding registers with auto-increment. 7. Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. 8. Disable interrupts. 9. Write 55h to EECON2. 10. Write 0AAh to EECON2. 11. Set the WR bit. This will begin the write cycle. 12. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Verify the memory (table read). This procedure will require about 6 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3. Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a ‘0’ to a ‘1’. When modifying individual bytes, it is not necessary to load all 64 holding registers before executing a write operation. TABLAT TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxx3F Write Register TBLPTR = xxxxx2 Program Memory Holding Register Holding Register Holding Register Holding Register 8 8 8 8 Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 64 bytes in the holding register. PIC18F2420/2520/4420/4520 DS39631B-page 80 Preliminary © 2007 Microchip Technology Inc. EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L WRITE_BUFFER_BACK MOVLW D’64 ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS © 2007 Microchip Technology Inc. Preliminary DS39631B-page 81 PIC18F2420/2520/4420/4520 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) 6.5.2 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. 6.5.4 PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 23.0 “Special Features of the CPU” for more detail. 6.6 Flash Program Operation During Code Protection See Section 23.5 “Program Verification and Code Protection” for details on code protection of Flash program memory. TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 49 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 49 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 49 TABLAT Program Memory Table Latch 49 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 EECON2 EEPROM Control Register 2 (not a physical register) 51 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 51 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. PIC18F2420/2520/4420/4520 DS39631B-page 82 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 83 PIC18F2420/2520/4420/4520 7.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range. Five SFRs are used to read and write to the data EEPROM as well as the program memory. They are: • EECON1 • EECON2 • EEDATA • EEADR The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and the EEADR register holds the address of the EEPROM location being accessed. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will vary with voltage and temperature as well as from chip to chip. Please refer to parameter D122 (Table 26-1 in Section 26.0 “Electrical Characteristics”) for exact limits. 7.1 EEADR Register The EEADR register is used to address the data EEPROM for read and write operations. The 8-bit range of the register can address a memory range of 256 bytes (00h to FFh). 7.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. The WR control bit initiates write operations. The bit can be set but not cleared in software. It is only cleared in hardware at the completion of the write operation. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. Note: During normal operation, the WRERR may read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. PIC18F2420/2520/4420/4520 DS39631B-page 84 Preliminary © 2007 Microchip Technology Inc. REGISTER 7-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 85 PIC18F2420/2520/4420/4520 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in Example 7-1. 7.4 Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit, EEIF, is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software. 7.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. EXAMPLE 7-1: DATA EEPROM READ EXAMPLE 7-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set) PIC18F2420/2520/4420/4520 DS39631B-page 86 Preliminary © 2007 Microchip Technology Inc. 7.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in configuration words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect configuration bit. Refer to Section 23.0 “Special Features of the CPU” for additional information. 7.7 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked during the Power-up Timer period (TPWRT, parameter 33). The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. 7.8 Using the Data EEPROM The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 7-3. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124. CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts © 2007 Microchip Technology Inc. Preliminary DS39631B-page 87 PIC18F2420/2520/4420/4520 TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 EEADR EEPROM Address Register 51 EEDATA EEPROM Data Register 51 EECON2 EEPROM Control Register 2 (not a physical register) 51 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 51 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. PIC18F2420/2520/4420/4520 DS39631B-page 88 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 89 PIC18F2420/2520/4420/4520 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the Status register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 8-1. 8.2 Operation Example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY ROUTINE TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL MOVF ARG1, W MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH ; - ARG1 MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 Routine Multiply Method Program Memory (Words) Cycles (Max) Time @ 40 MHz @ 10 MHz @ 4 MHz 8 x 8 unsigned Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs Hardware multiply 1 1 100 ns 400 ns 1 μs 8 x 8 signed Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs Hardware multiply 6 6 600 ns 2.4 μs 6 μs 16 x 16 unsigned Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs 16 x 16 signed Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs PIC18F2420/2520/4420/4520 DS39631B-page 90 Preliminary © 2007 Microchip Technology Inc. Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM EXAMPLE 8-3: 16 x 16 UNSIGNED MULTIPLY ROUTINE Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. EQUATION 8-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY ROUTINE RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + (ARG1L • ARG2L) MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L-> ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ; ; MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H-> ; PRODH:PRODL MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ; ; MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H-> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; ; MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L-> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + (-1 • ARG1H<7> • ARG2H:ARG2L • 216) MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ; ; MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ; ; MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; ; MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; SUBWF RES2 ; MOVF ARG1H, W ; SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : © 2007 Microchip Technology Inc. Preliminary DS39631B-page 91 PIC18F2420/2520/4420/4520 9.0 INTERRUPTS The PIC18F2420/2520/4420/4520 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: • RCON • INTCON • INTCON2 • INTCON3 • PIR1, PIR2 • PIE1, PIE2 • IPR1, IPR2 It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: • Flag bit to indicate that an interrupt event occurred • Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set • Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC® mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 0008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. PIC18F2420/2520/4420/4520 DS39631B-page 92 Preliminary © 2007 Microchip Technology Inc. FIGURE 9-1: PIC18 INTERRUPT LOGIC TMR0IE GIEH/GIE GIEL/PEIE Wake-up if in Interrupt to CPU Vector to Location 0008h INT2IF INT2IE INT2IP INT1IF INT1IE INT1IP TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP IPEN TMR0IF TMR0IP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP RBIF RBIE RBIP INT0IF INT0IE GIEL/PEIE Interrupt to CPU Vector to Location IPEN IPEN 0018h SSPIF SSPIE SSPIP SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts ADIF ADIE ADIP High Priority Interrupt Generation Low Priority Interrupt Generation RCIF RCIE RCIP Additional Peripheral Interrupts Idle or Sleep modes GIEH/GIE © 2007 Microchip Technology Inc. Preliminary DS39631B-page 93 PIC18F2420/2520/4420/4520 9.1 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: INTCON REGISTER Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 94 Preliminary © 2007 Microchip Technology Inc. REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 95 PIC18F2420/2520/4420/4520 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. PIC18F2420/2520/4420/4520 DS39631B-page 96 Preliminary © 2007 Microchip Technology Inc. 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request Flag registers (PIR1 and PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 97 PIC18F2420/2520/4420/4520 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A high/low-voltage condition occurred (direction determined by VDIRMAG bit, HLVDCON<7>) 0 = A high/low-voltage condition has not occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCPx Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 98 Preliminary © 2007 Microchip Technology Inc. 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 99 PIC18F2420/2520/4420/4520 REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 100 Preliminary © 2007 Microchip Technology Inc. 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’. bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 101 PIC18F2420/2520/4420/4520 REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 102 Preliminary © 2007 Microchip Technology Inc. 9.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 4.1 “RCON Register”. REGISTER 9-10: RCON REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(1) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16XXX Compatibility mode) bit 6 SBOREN: Software BOR Enable bit(1) For details of bit operation, see Register 4-1. Note 1: Actual Reset values are determined by device configuration and the nature of the device Reset. See Register 4-1 for additional information. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 4-1. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 4-1. bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 103 PIC18F2420/2520/4420/4520 9.6 INTn Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE. Flag bit, INTxF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wakeup the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high priority interrupt source. 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0 “Timer0 Module” for further details on the Timer0 module. 9.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 9.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, Status and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 5.3 “Data Memory Organization”), the user may need to save the WREG, Status and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS PIC18F2420/2520/4420/4520 DS39631B-page 104 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 105 PIC18F2420/2520/4420/4520 10.0 I/O PORTS Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: • TRIS register (data direction register) • PORT register (reads the levels on the pins of the device) • LAT register (output latch) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 10-1. FIGURE 10-1: GENERIC I/O PORT OPERATION 10.1 PORTA, TRISA and LATA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RA4/T0CKI/C1OUT pin. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in the configuration register (see Section 23.1 “Configuration Bits” for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins RA3:RA0 and RA5 as A/D converter inputs is selected by clearing or setting the control bits in the ADCON1 register (A/D Control Register 1). Pins RA0 through RA5 may also be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register. To use RA3:RA0 as digital inputs, it is also necessary to turn off the comparators. The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input. All other PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 10-1: INITIALIZING PORTA Data Bus WR LAT WR TRIS RD Port Data Latch TRIS Latch RD TRIS Input Buffer I/O pin(1) D Q CK D Q CK EN Q D EN RD LAT or Port Note 1: I/O pins have diode protection to VDD and VSS. Note: On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read as ‘0’. RA4 is configured as a digital input. CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 07h ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs PIC18F2420/2520/4420/4520 DS39631B-page 106 Preliminary © 2007 Microchip Technology Inc. TABLE 10-1: PORTA I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D input channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D input channel 1 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RA2/AN2/ VREF-/CVREF RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D input channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and comparator voltage reference low input. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D input channel 3 and Comparator C1+ input. Default input configuration on POR. VREF+ 1 I ANA A/D and comparator voltage reference high input. RA4/T0CKI/C1OUT RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI 1 I ST Timer0 clock input. C1OUT 0 O DIG Comparator 1 output; takes priority over port data. RA5/AN4/SS/ HLVDIN/C2OUT RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D input channel 4. Default configuration on POR. SS 1 I TTL Slave select input for SSP (MSSP module). HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. OSC2/CLKO/RA6 RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes). CLKO x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator modes. OSC1/CLKI/RA7 RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes. 1 I TTL PORTA<7> data input. Disabled in external oscillator modes. OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2007 Microchip Technology Inc. Preliminary DS39631B-page 107 PIC18F2420/2520/4420/4520 TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 52 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 52 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. PIC18F2420/2520/4420/4520 DS39631B-page 108 Preliminary © 2007 Microchip Technology Inc. 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 10-2: INITIALIZING PORTB Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of the PORTB pins (RB7:RB4) have an interrupton- change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton- change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from the Sleep mode, or any of the Idle modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). b) Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the configuration bit, CCP2MX, as the alternate peripheral pin for the CCP2 module (CCP2MX = 0). Note: On a Power-on Reset, RB4:RB0 are configured as analog inputs by default and read as ‘0’; RB7:RB5 are configured as digital inputs. By programming the configuration bit, PBADEN, RB4:RB0 will alternatively be configured as digital inputs on POR. CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches CLRF LATB ; Alternate method ; to clear output ; data latches MOVLW 0Fh ; Set RB<4:0> as MOVWF ADCON1 ; digital I/O pins ; (required if config bit ; PBADEN is set) MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs © 2007 Microchip Technology Inc. Preliminary DS39631B-page 109 PIC18F2420/2520/4420/4520 TABLE 10-3: PORTB I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RB0/INT0/FLT0/ AN12 RB0 0 O DIG LATB<0> data output; not affected by analog input. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT0 1 I ST External interrupt 0 input. FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. AN12 1 I ANA A/D input channel 12.(1) RB1/INT1/AN10 RB1 0 O DIG LATB<1> data output; not affected by analog input. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT1 1 I ST External Interrupt 1 input. AN10 1 I ANA A/D input channel 10.(1) RB2/INT2/AN8 RB2 0 O DIG LATB<2> data output; not affected by analog input. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT2 1 I ST External interrupt 2 input. AN8 1 I ANA A/D input channel 8.(1) RB3/AN9/CCP2 RB3 0 O DIG LATB<3> data output; not affected by analog input. 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) AN9 1 I ANA A/D input channel 9.(1) CCP2(2) 0 O DIG CCP2 compare and PWM output. 1 I ST CCP2 capture input RB4/KBI0/AN11 RB4 0 O DIG LATB<4> data output; not affected by analog input. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) KBI0 1 I TTL Interrupt on pin change. AN11 1 I ANA A/D input channel 11.(1) RB5/KBI1/PGM RB5 0 O DIG LATB<5> data output. 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt on pin change. PGM x I ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP configuration bit; all other pin functions disabled. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt on pin change. PGC x I ST Serial execution (ICSP) clock input for ICSP and ICD operation.(3) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt on pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation.(3) x I ST Serial execution data input for ICSP and ICD operation.(3) Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Configuration on POR is determined by the PBADEN configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. PIC18F2420/2520/4420/4520 DS39631B-page 110 Preliminary © 2007 Microchip Technology Inc. TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52 LATB PORTB Data Latch Register (Read and Write to Data Latch) 52 TRISB PORTB Data Direction Control Register 52 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 49 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 49 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 111 PIC18F2420/2520/4420/4520 10.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 10-5). The pins have Schmitt Trigger input buffers. RC1 is normally configured by configuration bit, CCP2MX, as the default peripheral pin of the CCP2 module (default/erased state, CCP2MX = 1). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 10-3: INITIALIZING PORTC Note: On a Power-on Reset, these pins are configured as digital inputs. CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches CLRF LATC ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs PIC18F2420/2520/4420/4520 DS39631B-page 112 Preliminary © 2007 Microchip Technology Inc. TABLE 10-5: PORTC I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RC0/T1OSO/ T13CKI RC0 0 O DIG LATC<0> data output. 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/CCP2 RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2(1) 0 O DIG CCP2 compare and PWM output; takes priority over port data. 1 I ST CCP2 capture input. RC2/CCP1/P1A RC2 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. CCP1 0 O DIG ECCP1 compare or PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A(2) 0 O DIG ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK/SCL RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. SCK 0 O DIG SPI™ clock output (MSSP module); takes priority over port data. 1 I ST SPI clock input (MSSP module). SCL 0 O DIG I2 C™ clock output (MSSP module); takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP module); input type depends on module setting. RC4/SDI/SDA RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. SDI 1 I ST SPI data input (MSSP module). SDA 1 O DIG I2 C data output (MSSP module); takes priority over port data. 1 I I2C/SMB I2C data input (MSSP module); input type depends on module setting. RC5/SDO RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO 0 O DIG SPI data output (MSSP module); takes priority over port data. RC6/TX/CK RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX 1 O DIG Asynchronous serial transmit data output (USART module); takes priority over port data. User must configure as output. CK 1 O DIG Synchronous serial clock output (USART module); takes priority over port data. 1 I ST Synchronous serial clock input (USART module). RC7/RX/DT RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX 1 I ST Asynchronous serial receive data input (USART module). DT 1 O DIG Synchronous serial data output (USART module); takes priority over port data. 1 I ST Synchronous serial data input (USART module). User must configure as an input. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3. 2: Enhanced PWM output is available only on PIC18F4520 devices. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 113 PIC18F2420/2520/4420/4520 TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 52 LATC PORTC Data Latch Register (Read and Write to Data Latch) 52 TRISC PORTC Data Direction Control Register 52 PIC18F2420/2520/4420/4520 DS39631B-page 114 Preliminary © 2007 Microchip Technology Inc. 10.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Three of the PORTD pins are multiplexed with outputs P1B, P1C and P1D of the enhanced CCP module. The operation of these additional PWM output pins is covered in greater detail in Section 16.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.6 “Parallel Slave Port” for additional information on the Parallel Slave Port (PSP). EXAMPLE 10-4: INITIALIZING PORTD Note: PORTD is only available on 40/44-pin devices. Note: On a Power-on Reset, these pins are configured as digital inputs. Note: When the enhanced PWM mode is used with either dual or quad outputs, the PSP functions of PORTD are automatically disabled. CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2007 Microchip Technology Inc. Preliminary DS39631B-page 115 PIC18F2420/2520/4420/4520 TABLE 10-7: PORTD I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. PSP0 x O DIG PSP read data output (LATD<0>); takes priority over port data. x I TTL PSP write data input. RD1/PSP1 RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. PSP1 x O DIG PSP read data output (LATD<1>); takes priority over port data. x I TTL PSP write data input. RD2/PSP2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. PSP2 x O DIG PSP read data output (LATD<2>); takes priority over port data. x I TTL PSP write data input. RD3/PSP3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. PSP3 x O DIG PSP read data output (LATD<3>); takes priority over port data. x I TTL PSP write data input. RD4/PSP4 RD4 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. PSP4 x O DIG PSP read data output (LATD<4>); takes priority over port data. x I TTL PSP write data input. RD5/PSP5/P1B RD5 0 O DIG LATD<5> data output. 1 I ST PORTD<5> data input. PSP5 x O DIG PSP read data output (LATD<5>); takes priority over port data. x I TTL PSP write data input. P1B 0 O DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD6/PSP6/P1C RD6 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input. PSP6 x O DIG PSP read data output (LATD<6>); takes priority over port data. x I TTL PSP write data input. P1C 0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD7/PSP7/P1D RD7 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. PSP7 x O DIG PSP read data output (LATD<7>); takes priority over port data. x I TTL PSP write data input. P1D 0 O DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). PIC18F2420/2520/4420/4520 DS39631B-page 116 Preliminary © 2007 Microchip Technology Inc. TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52 LATD PORTD Data Latch Register (Read and Write to Data Latch) 52 TRISD PORTD Data Direction Control Register 52 TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 117 PIC18F2420/2520/4420/4520 10.5 PORTE, TRISE and LATE Registers Depending on the particular PIC18F2420/2520/4420/ 4520 device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. The upper four bits of the TRISE register also control the operation of the Parallel Slave Port. Their operation is explained in Register 10-1. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. The fourth pin of PORTE (MCLR/VPP/RE3) is an input only pin. Its operation is controlled by the MCLRE configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. EXAMPLE 10-5: INITIALIZING PORTE 10.5.1 PORTE IN 28-PIN DEVICES For 28-pin devices, PORTE is only available when Master Clear functionality is disabled (MCLRE = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described. Note: On a Power-on Reset, RE2:RE0 are configured as analog inputs. Note: On a Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled. CLRF PORTE ; Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 0Ah ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 03h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs PIC18F2420/2520/4420/4520 DS39631B-page 118 Preliminary © 2007 Microchip Technology Inc. REGISTER 10-1: TRISE REGISTER (40/44-PIN DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode bit 3 Unimplemented: Read as ‘0’ bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 119 PIC18F2420/2520/4420/4520 TABLE 10-9: PORTE I/O SUMMARY TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Pin Function TRIS Setting I/O I/O Type Description RE0/RD/AN5 RE0 0 O DIG LATE<0> data output; not affected by analog input. 1 I ST PORTE<0> data input; disabled when analog input enabled. RD 1 I TTL PSP read enable input (PSP enabled). AN5 1 I ANA A/D input channel 5; default input configuration on POR. RE1/WR/AN6 RE1 0 O DIG LATE<1> data output; not affected by analog input. 1 I ST PORTE<1> data input; disabled when analog input enabled. WR 1 I TTL PSP write enable input (PSP enabled). AN6 1 I ANA A/D input channel 6; default input configuration on POR. RE2/CS/AN7 RE2 0 O DIG LATE<2> data output; not affected by analog input. 1 I ST PORTE<2> data input; disabled when analog input enabled. CS 1 I TTL PSP write enable input (PSP enabled). AN7 1 I ANA A/D input channel 7; default input configuration on POR. MCLR/VPP/RE3(1) MCLR — I ST External Master Clear input; enabled when MCLRE configuration bit is set. VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always available, regardless of pin mode. RE3 —(2) I ST PORTE<3> data input; enabled when MCLRE configuration bit is clear. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin devices. 2: RE3 does not have a corresponding TRIS bit to control data direction. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTE — — — — RE3(1,2) RE2 RE1 RE0 52 LATE(2) — — — — — LATE Data Output Register 52 TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). PIC18F2420/2520/4420/4520 DS39631B-page 120 Preliminary © 2007 Microchip Technology Inc. 10.6 Parallel Slave Port In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 10-1). Setting control bit, PSPMODE (TRISE<4>), enables PSP operation as long as the enhanced CCP module is not operating in dual output or quad output PWM mode. In Slave mode, the port is asynchronously readable and writable by the external world. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting the control bit, PSPMODE, enables the PORTE I/O pins to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, PFCG3:PFCG0 (ADCON1<3:0>), must also be set to a value in the range of ‘1010’ through ‘1111’. A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set when the write ends. A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is clear. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure 10-3 and Figure 10-4, respectively. FIGURE 10-2: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Note: The Parallel Slave Port is only available on 40/44-pin devices. Data Bus WR LATD RDx pin D Q CK EN Q D RD PORTD EN One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read Chip Select Write RD CS WR TTL TTL TTL TTL or WR PORTD RD LATD Data Latch Note: I/O pins have diode protection to VDD and VSS. PORTE Pins © 2007 Microchip Technology Inc. Preliminary DS39631B-page 121 PIC18F2420/2520/4420/4520 FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52 LATD PORTD Data Latch Register (Read and Write to Data Latch) 52 TRISD PORTD Data Direction Control Register 52 PORTE — — — — RE3 RE2 RE1 RE0 52 LATE — — — — — LATE Data Output bits 52 TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52 INTCON GIE/GIEH PEIE/GIEL TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Q1 Q2 Q3 Q4 CS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 WR RD IBF OBF PSPIF PORTD<7:0> Q1 Q2 Q3 Q4 CS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 WR IBF PSPIF RD OBF PORTD<7:0> PIC18F2420/2520/4420/4520 DS39631B-page 122 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 123 PIC18F2420/2520/4420/4520 11.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1. Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 124 Preliminary © 2007 Microchip Technology Inc. 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. 11.2 Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode; it is actually a buffered version of the real high byte of Timer0 which is not directly readable nor writable (refer to Figure 11-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. T0CKI pin T0SE 0 1 0 1 T0CS FOSC/4 Programmable Prescaler Sync with Internal Clocks TMR0L (2 TCY Delay) PSA Internal Data Bus T0PS2:T0PS0 Set TMR0IF on Overflow 3 8 8 Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. T0CKI pin T0SE 0 1 0 1 T0CS FOSC/4 Programmable Prescaler Sync with Internal Clocks TMR0L (2 TCY Delay) Internal Data Bus 8 PSA T0PS2:T0PS0 Set TMR0IF on Overflow 3 TMR0 TMR0H High Byte 8 8 8 Read TMR0L Write TMR0L 8 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 125 PIC18F2420/2520/4420/4520 11.3 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS2:T0PS0 bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. 11.4 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0 Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0L Timer0 Register, Low Byte 50 TMR0H Timer0 Register, High Byte 50 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 50 TRISA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. PIC18F2420/2520/4420/4520 DS39631B-page 126 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 127 PIC18F2420/2520/4420/4520 12.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Reset on CCP Special Event Trigger • Device clock status flag (T1RUN) A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power managed operation. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Timer1 is controlled through the T1CON Control register (Register 12-1). It also contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 128 Preliminary © 2007 Microchip Technology Inc. 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR3CS is cleared (= 0), Timer1 increments on every internal instruction cycle (Fosc/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. When Timer1 is enabled, the RC1/T1OSI and RC0/ T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 12-1: TIMER1 BLOCK DIAGRAM FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) T1SYNC TMR1CS T1CKPS1:T1CKPS0 Sleep Input T1OSCEN(1) FOSC/4 Internal Clock On/Off Prescaler 1, 2, 4, 8 Synchronize Detect 1 0 2 T1OSO/T13CKI T1OSI 1 0 TMR1ON TMR1L Set TMR1IF on Overflow TMR1 Clear TMR1 High Byte (CCP Special Event Trigger) Timer1 Oscillator Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. On/Off Timer1 Timer1 Clock Input T1SYNC TMR1CS T1CKPS1:T1CKPS0 Sleep Input T1OSCEN(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronize Detect 1 0 2 T1OSO/T13CKI T1OSI Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 1 0 TMR1L Internal Data Bus 8 Set TMR1IF on Overflow TMR1 TMR1H High Byte 8 8 8 Read TMR1L Write TMR1L 8 TMR1ON Clear TMR1 (CCP Special Event Trigger) Timer1 Oscillator On/Off Timer1 Timer1 Clock Input © 2007 Microchip Technology Inc. Preliminary DS39631B-page 129 PIC18F2420/2520/4420/4520 12.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 12.3 Timer1 Oscillator An on-chip crystal oscillator circuit is incorporated between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON<3>). The oscillator is a lowpower circuit rated for 32 kHz crystals. It will continue to run during all power managed modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 12-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR 12.3.1 USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power managed modes. By setting the clock select bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device switches to SEC_RUN mode; both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 3.0 “Power Managed Modes”. Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (T1CON<6>), is set. This can be used to determine the controller’s current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. 12.3.2 LOW-POWER TIMER1 OPTION The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. When the LPT1OSC configuration bit is set, the Timer1 oscillator operates in a low-power mode. When LPT1OSC is not set, Timer1 operates at a higher power level. Power consumption for a particular mode is relatively constant, regardless of the device’s operating mode. The default Timer1 configuration is the higher power mode. As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. Note: See the Notes with Table 12-1 for additional information about capacitor selection. C1 C2 XTAL PIC18FXXXX T1OSI T1OSO 32.768 kHz 27 pF 27 pF Osc Type Freq C1 C2 LP 32 kHz 27 pF(1) 27 pF(1) Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. PIC18F2420/2520/4420/4520 DS39631B-page 130 Preliminary © 2007 Microchip Technology Inc. 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. FIGURE 12-4: OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING 12.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). 12.5 Resetting Timer1 Using the CCP Special Event Trigger If either of the CCP modules is configured to use Timer1 and generate a Special Event Trigger in Compare mode (CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this signal will reset Timer1. The trigger from CCP2 will also start an A/D conversion if the A/D module is enabled (see Section 15.3.4 “Special Event Trigger” for more information). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPRH:CCPRL register pair effectively becomes a period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special Event Trigger, the write operation will take precedence. 12.6 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 12.3 “Timer1 Oscillator” above) gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. VDD OSC1 VSS OSC2 RC0 RC1 RC2 Note: Not drawn to scale. Note: The Special Event Triggers from the CCP2 module will not set the TMR1IF interrupt flag bit (PIR1<0>). © 2007 Microchip Technology Inc. Preliminary DS39631B-page 131 PIC18F2420/2520/4420/4520 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TMR1L Timer1 Register, Low Byte 50 TMR1H Timer1 Register, High Byte 50 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. PIC18F2420/2520/4420/4520 DS39631B-page 132 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 133 PIC18F2420/2520/4420/4520 13.0 TIMER2 MODULE The Timer2 module timer incorporates the following features: • 8-bit timer and period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4 and 1:16) • Software programmable postscaler (1:1 through 1:16) • Interrupt on TMR2-to-PR2 match • Optional use as the shift clock for the MSSP module The module is controlled through the T2CON register (Register 13-1), which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure 13-1. 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by- 16 prescale options; these are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The value of TMR2 is compared to that of the period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/ postscaler (see Section 13.2 “Timer2 Interrupt”). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMR2 register • a write to the T2CON register • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 134 Preliminary © 2007 Microchip Technology Inc. 13.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>). 13.3 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section 17.0 “Master Synchronous Serial Port (MSSP) Module”. FIGURE 13-1: TIMER2 BLOCK DIAGRAM TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TMR2 Timer2 Register 50 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50 PR2 Timer2 Period Register 50 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. Comparator TMR2 Output TMR2 Postscaler Prescaler PR2 2 FOSC/4 1:1 to 1:16 1:1, 1:4, 1:16 4 T2OUTPS3:T2OUTPS0 T2CKPS1:T2CKPS0 Set TMR2IF Internal Data Bus 8 Reset TMR2/PR2 8 8 (to PWM or MSSP) Match © 2007 Microchip Technology Inc. Preliminary DS39631B-page 135 PIC18F2420/2520/4420/4520 14.0 TIMER3 MODULE The Timer3 module timer/counter incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1). It also selects the clock source options for the CCP modules (see Section 15.1.1 “CCP Modules and Timer Resources” for more information). REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x = Timer3 is the capture/compare clock source for the CCP modules 01 = Timer3 is the capture/compare clock source for CCP2; Timer1 is the capture/compare clock source for CCP1 00 = Timer1 is the capture/compare clock source for the CCP modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 136 Preliminary © 2007 Microchip Technology Inc. 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 14-1: TIMER3 BLOCK DIAGRAM FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) T3SYNC TMR3CS T3CKPS1:T3CKPS0 Sleep Input T1OSCEN(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronize Detect 1 0 2 T1OSO/T13CKI T1OSI 1 0 TMR3ON TMR3L Set TMR3IF on Overflow TMR3 High Byte Timer1 Oscillator Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. On/Off Timer3 CCP1/CCP2 Special Event Trigger CCP1/CCP2 Select from T3CON<6,3> Clear TMR3 Timer1 Clock Input T3SYNC TMR3CS T3CKPS1:T3CKPS0 Sleep Input T1OSCEN(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronize Detect 1 0 2 T13CKI/T1OSO T1OSI Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 1 0 TMR3L Internal Data Bus 8 Set TMR3IF on Overflow TMR3 TMR3H High Byte 8 8 8 Read TMR1L Write TMR1L 8 TMR3ON CCP1/CCP2 Special Event Trigger Timer1 Oscillator On/Off Timer3 Timer1 Clock Input CCP1/CCP2 Select from T3CON<6,3> Clear TMR3 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 137 PIC18F2420/2520/4420/4520 14.2 Timer3 16-Bit Read/Write Mode Timer3 can be configured for 16-bit reads and writes (see Figure 14-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer3 must also take place through the TMR3H Buffer register. The Timer3 high byte is updated with the contents of TMR3H when a write occurs to TMR3L. This allows a user to write all 16 bits to both the high and low bytes of Timer3 at once. The high byte of Timer3 is not directly readable or writable in this mode. All reads and writes must take place through the Timer3 High Byte Buffer register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L. 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source The Timer1 internal oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. To use it as the Timer3 clock source, the TMR3CS bit must also be set. As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section 12.0 “Timer1 Module”. 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled or disabled by setting or clearing the Timer3 Interrupt Enable bit, TMR3IE (PIE2<1>). 14.5 Resetting Timer3 Using the CCP Special Event Trigger If either of the CCP modules is configured to use Timer3 and to generate a Special Event Trigger in Compare mode (CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this signal will reset Timer3. It will also start an A/D conversion if the A/D module is enabled (see Section 15.3.4 “Special Event Trigger” for more information). The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPR2H:CCPR2L register pair effectively becomes a period register for Timer3. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timer3 coincides with a Special Event Trigger from a CCP module, the write will take precedence. TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Note: The Special Event Triggers from the CCP2 module will not set the TMR3IF interrupt flag bit (PIR1<0>). Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 TMR3L Timer3 Register, Low Byte 51 TMR3H Timer3 Register, High Byte 51 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. PIC18F2420/2520/4420/4520 DS39631B-page 138 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 139 PIC18F2420/2520/4420/4520 15.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F2420/2520/4420/4520 devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 28-pin devices, the two standard CCP modules (CCP1 and CCP2) operate as described in this chapter. In 40/ 44-pin devices, CCP1 is implemented as an enhanced CCP module with standard Capture and Compare modes and enhanced PWM modes. The ECCP implementation is discussed in Section 16.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. The Capture and Compare operations described in this chapter apply to all standard and enhanced CCP modules. REGISTER 15-1: CCPXCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES) Note: Throughout this section and Section 16.0 “Enhanced Capture/Compare/PWM (ECCP) Module”, references to the register and bit names for CCP modules are referred to generically by the use of ‘x’ or ‘y’ in place of the specific module number. Thus, “CCPxCON” might refer to the control register for CCP1, CCP2 or ECCP1. “CCPxCON” is used throughout these sections to refer to the module control register, regardless of whether the CCP module is a standard or enhanced implementation. U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCP Module x Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high (CCPIF bit is set) 1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low (CCPIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCP pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match (CCPxIF bit is set) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 140 Preliminary © 2007 Microchip Technology Inc. 15.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 15.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers 1, 2 or 3, depending on the mode selected. Timer1 and Timer3 are available to modules in Capture or Compare modes, while Timer2 is available for modules in PWM mode. TABLE 15-1: CCP MODE – TIMER RESOURCE The assignment of a particular timer to a module is determined by the Timer-to-CCP enable bits in the T3CON register (Register 14-1). Both modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same time. The interactions between the two modules are summarized in Figure 15-1 and Figure 15-2. In Timer1 in Asynchronous Counter mode, the capture operation will not work. 15.1.2 CCP2 PIN ASSIGNMENT The pin assignment for CCP2 (Capture input, Compare and PWM output) can change, based on device configuration. The CCP2MX configuration bit determines which pin CCP2 is multiplexed to. By default, it is assigned to RC1 (CCP2MX = 1). If the configuration bit is cleared, CCP2 is multiplexed with RB3. Changing the pin assignment of CCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCP/ECCP Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different for each CCP. Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on trigger event can also be done. Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Operation of CCP2 could be affected if it is using the same timer as a time base. Compare Compare Either module can be configured for the Special Event Trigger to reset the time base. Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if both modules are using the same time base. Capture PWM(1) None Compare PWM(1) None PWM(1) Capture None PWM(1) Compare None PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). Note 1: Includes standard and enhanced PWM operation. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 141 PIC18F2420/2520/4420/4520 15.2 Capture Mode In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin. An event is defined as one of the following: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge The event is selected by the mode select bits, CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old captured value is overwritten by the new captured value. 15.2.1 CCP PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. 15.2.2 TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation will not work. The timer to be used with each CCP module is selected in the T3CON register (see Section 15.1.1 “CCP Modules and Timer Resources”). 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. 15.2.4 CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM3:CCPxM0). Whenever the CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. EXAMPLE 15-1: CHANGING BETWEEN CAPTURE PRESCALERS (CCP2 SHOWN) FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Note: If RB3/CCP2 or RC1/CCP2 is configured as an output, a write to the port can cause a capture condition. CLRF CCP2CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON MOVWF CCP2CON ; Load CCP2CON with ; this value CCPR1H CCPR1L TMR1H TMR1L Set CCP1IF TMR3 Enable Q1:Q4 CCP1CON<3:0> CCP1 pin Prescaler ÷ 1, 4, 16 and Edge Detect TMR1 Enable T3CCP2 T3CCP2 CCPR2H CCPR2L TMR1H TMR1L Set CCP2IF TMR3 Enable CCP2CON<3:0> CCP2 pin Prescaler ÷ 1, 4, 16 TMR3H TMR3L TMR1 Enable T3CCP2 T3CCP1 T3CCP2 T3CCP1 TMR3H TMR3L and Edge Detect 4 4 4 PIC18F2420/2520/4420/4520 DS39631B-page 142 Preliminary © 2007 Microchip Technology Inc. 15.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the I/O latch) The action on the pin is based on the value of the mode select bits (CCPxM3:CCPxM0). At the same time, the interrupt flag bit, CCPxIF, is set. 15.3.1 CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. 15.3.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 15.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCPxM3:CCPxM0 = 1010), the corresponding CCPx pin is not affected. Only a CCP interrupt is generated, if enabled and the CCPxIE bit is set. 15.3.4 SPECIAL EVENT TRIGGER Both CCP modules are equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCPxM3:CCPxM0 = 1011). For either CCP module, the Special Event Trigger resets the timer register pair for whichever timer resource is currently assigned as the module’s time base. This allows the CCPRx registers to serve as a programmable period register for either timer. The Special Event Trigger for CCP2 can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM Note: Clearing the CCP2CON register will force the RB3 or RC1 compare output latch (depending on device configuration) to the default low level. This is not the PORTB or PORTC I/O data latch. CCPR1H CCPR1L TMR1H TMR1L Comparator S Q R Output Logic Special Event Trigger Set CCP1IF CCP1 pin TRIS CCP1CON<3:0> Output Enable TMR3H TMR3L CCPR2H CCPR2L Comparator 1 0 T3CCP2 T3CCP1 Set CCP2IF 1 0 Compare 4 (Timer1/Timer3 Reset) S Q R Output Logic Special Event Trigger CCP2 pin TRIS CCP2CON<3:0> 4 Output Enable (Timer1/Timer3 Reset, A/D Trigger) Match Compare Match © 2007 Microchip Technology Inc. Preliminary DS39631B-page 143 PIC18F2420/2520/4420/4520 TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 RCON IPEN SBOREN — RI TO PD POR BOR 48 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 TRISB PORTB Data Direction Control Register 52 TRISC PORTC Data Direction Control Register 52 TMR1L Timer1 Register, Low Byte 50 TMR1H Timer1 Register, High Byte 50 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 TMR3H Timer3 Register, High Byte 51 TMR3L Timer3 Register, Low Byte 51 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51 CCPR1L Capture/Compare/PWM Register 1, Low Byte 51 CCPR1H Capture/Compare/PWM Register 1, High Byte 51 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 CCPR2L Capture/Compare/PWM Register 2, Low Byte 51 CCPR2H Capture/Compare/PWM Register 2, High Byte 51 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. PIC18F2420/2520/4420/4520 DS39631B-page 144 Preliminary © 2007 Microchip Technology Inc. 15.4 PWM Mode In Pulse Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Figure 15-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 15.4.4 “Setup for PWM Operation”. FIGURE 15-3: SIMPLIFIED PWM BLOCK DIAGRAM A PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 15-4: PWM OUTPUT 15.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: EQUATION 15-1: PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set) • The PWM duty cycle is latched from CCPRxL into CCPRxH 15.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. The following equation is used to calculate the PWM duty cycle in time: EQUATION 15-2: CCPRxL and CCPxCON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Note: Clearing the CCP2CON register will force the RB3 or RC1 output latch (depending on device configuration) to the default low level. This is not the PORTB or PORTC I/O data latch. CCPRxL CCPRxH (Slave) Comparator TMR2 Comparator PR2 (Note 1) R Q S Duty Cycle Registers CCPxCON<5:4> Clear Timer, CCP1 pin and latch D.C. Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. CCPx Output Corresponding TRIS bit Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 Note: The Timer2 postscalers (see Section 13.0 “Timer2 Module”) are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • TOSC • (TMR2 Prescale Value) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 145 PIC18F2420/2520/4420/4520 The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCPx pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 15-3: TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz 15.4.3 PWM AUTO-SHUTDOWN (CCP1 ONLY) The PWM auto-shutdown features of the enhanced CCP module are also available to CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. 15.4.4 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. 2. Set the PWM duty cycle by writing to the CCPRxL register and CCPxCON<5:4> bits. 3. Make the CCPx pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. 5. Configure the CCPx module for PWM operation. Note: If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be cleared. FOSC FPWM ⎝---------------⎠ log⎛ ⎞ log(2) PWM Resolution (max) = -----------------------------bits PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 PIC18F2420/2520/4420/4520 DS39631B-page 146 Preliminary © 2007 Microchip Technology Inc. TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 RCON IPEN SBOREN — RI TO PD POR BOR 48 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TRISB PORTB Data Direction Control Register 52 TRISC PORTC Data Direction Control Register 52 TMR2 Timer2 Register 50 PR2 Timer2 Period Register 50 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50 CCPR1L Capture/Compare/PWM Register 1, Low Byte 51 CCPR1H Capture/Compare/PWM Register 1, High Byte 51 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 CCPR2L Capture/Compare/PWM Register 2, Low Byte 51 CCPR2H Capture/Compare/PWM Register 2, High Byte 51 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 51 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 51 PWM1CON PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 147 PIC18F2420/2520/4420/4520 16.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE In PIC18F4420/4520 devices, CCP1 is implemented as a standard CCP module with enhanced PWM capabilities. These include the provision for 2 or 4 output channels, user selectable polarity, dead-band control and automatic shutdown and restart. The enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of the ECCP module are the same as described for the standard CCP module. The control register for the enhanced CCP module is shown in Register 16-1. It differs from the CCPxCON registers in PIC18F2420/2520 devices in that the two Most Significant bits are implemented to control PWM functionality. REGISTER 16-1: CCP1CON REGISTER (ECCP1 MODULE, 40/44-PIN DEVICES) Note: The ECCP module is implemented only in 40/44-pin devices. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits If CCP1M3:CCP1M2 = 00, 01, 10: xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If CCP1M3:CCP1M2 = 11: 00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Capture mode 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF) 1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF) 1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 148 Preliminary © 2007 Microchip Technology Inc. In addition to the expanded range of modes available through the CCP1CON register and ECCP1AS register, the ECCP module has an additional register associated with Enhanced PWM operation and auto-shutdown features. It is: • PWM1CON (Dead-band delay) 16.1 ECCP Outputs and Configuration The enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTC and PORTD. The outputs that are active depend on the CCP operating mode selected. The pin assignments are summarized in Table 16-1. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1M1:P1M0 and CCP1M3:CCP1M0 bits. The appropriate TRISC and TRISD direction bits for the port pins must also be set as outputs. 16.1.1 ECCP MODULES AND TIMER RESOURCES Like the standard CCP modules, the ECCP module can utilize Timers 1, 2 or 3, depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 is available for modules in PWM mode. Interactions between the standard and enhanced CCP modules are identical to those described for standard CCP modules. Additional details on timer resources are provided in Section 15.1.1 “CCP Modules and Timer Resources”. 16.2 Capture and Compare Modes Except for the operation of the Special Event Trigger discussed below, the Capture and Compare modes of the ECCP module are identical in operation to that of CCP2. These are discussed in detail in Section 15.2 “Capture Mode” and Section 15.3 “Compare Mode”. No changes are required when moving between 28-pin and 40/44-pin devices. 16.2.1 SPECIAL EVENT TRIGGER The Special Event Trigger output of ECCP1 resets the TMR1 or TMR3 register pair, depending on which timer resource is currently selected. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1 or Timer3. 16.3 Standard PWM Mode When configured in Single Output mode, the ECCP module functions identically to the standard CCP module in PWM mode, as described in Section 15.4 “PWM Mode”. This is also sometimes referred to as “Compatible CCP” mode, as in Table 16-1. TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES Note: When setting up single output PWM operations, users are free to use either of the processes described in Section 15.4.4 “Setup for PWM Operation” or Section 16.4.9 “Setup for PWM Operation”. The latter is more generic and will work for either single or multi-output PWM. ECCP Mode CCP1CON Configuration RC2 RD5 RD6 RD7 All 40/44-pin devices: Compatible CCP 00xx 11xx CCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7 Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 149 PIC18F2420/2520/4420/4520 16.4 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low). The module’s output mode and polarity are configured by setting the P1M1:P1M0 and CCP1M3:CCP1M0 bits of the CCP1CON register. Figure 16-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the PWM Delay register, PWM1CON, which is loaded at either the duty cycle boundary or the period boundary (whichever comes first). Because of the buffering, the module waits until the assigned timer resets, instead of starting immediately. This means that enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRIS bits for output. 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation. EQUATION 16-1: PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set) • The PWM duty cycle is copied from CCPR1L into CCPR1H FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE Note: The Timer2 postscaler (see Section 13.0 “Timer2 Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) CCPR1L CCPR1H (Slave) Comparator TMR2 Comparator PR2 (Note 1) R Q S Duty Cycle Registers CCP1CON<5:4> Clear Timer, set CCP1 pin and latch D.C. Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. TRISx CCP1/P1A TRISx P1B TRISx TRISx P1D Output Controller P1M1<1:0> 2 CCP1M<3:0> 4 PWM1CON CCP1/P1A P1B P1C P1D P1C PIC18F2420/2520/4420/4520 DS39631B-page 150 Preliminary © 2007 Microchip Technology Inc. 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation. EQUATION 16-2: CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. EQUATION 16-3: 16.4.3 PWM OUTPUT CONFIGURATIONS The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: • Single Output • Half-Bridge Output • Full-Bridge Output, Forward mode • Full-Bridge Output, Reverse mode The Single Output mode is the standard PWM mode discussed in Section 16.4 “Enhanced PWM Mode”. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 16-2. TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 Prescale Value) Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. ( ) PWM Resolution (max) = FOSC FPWM log log(2) bits PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 151 PIC18F2420/2520/4420/4520 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 Period 00 10 01 11 SIGNAL PR2 + 1 CCP1CON <7:6> P1A Modulated P1A Modulated P1B Modulated P1A Active P1B Inactive P1C Inactive P1D Modulated P1A Inactive P1B Modulated P1C Active P1D Inactive Duty Cycle (Single Output) (Half-Bridge) (Full-Bridge, Forward) (Full-Bridge, Reverse) Delay(1) Delay(1) 0 Period 00 10 01 11 SIGNAL PR2 + 1 CCP1CON <7:6> P1A Modulated P1A Modulated P1B Modulated P1A Active P1B Inactive P1C Inactive P1D Modulated P1A Inactive P1B Modulated P1C Active P1D Inactive Duty Cycle (Single Output) (Half-Bridge) (Full-Bridge, Forward) (Full-Bridge, Reverse) Delay(1) Delay(1) Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (see Section 16.4.6 “Programmable Dead-Band Delay”). PIC18F2420/2520/4420/4520 DS39631B-page 152 Preliminary © 2007 Microchip Technology Inc. 16.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown in Figure 16-5, or for full-bridge applications where four power switches are being modulated with two PWM signals. In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, PDC6:PDC0, sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 16.4.6 “Programmable Dead-Band Delay” for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTD<5> data latches, the TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 16-4: HALF-BRIDGE PWM OUTPUT FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Period Duty Cycle td td (1) P1A(2) P1B(2) td = Dead-Band Delay Period (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. PIC18F4X2X P1A P1B FET Driver FET Driver V+ VLoad + V- + VFET Driver FET Driver V+ VLoad FET Driver FET Driver PIC18F4X2X P1A P1B Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit © 2007 Microchip Technology Inc. Preliminary DS39631B-page 153 PIC18F2420/2520/4420/4520 16.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 16-6. P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs. FIGURE 16-6: FULL-BRIDGE PWM OUTPUT Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) Forward Mode (1) Period Duty Cycle P1A(2) P1C(2) P1D(2) P1B(2) Reverse Mode (1) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. PIC18F2420/2520/4420/4520 DS39631B-page 154 Preliminary © 2007 Microchip Technology Inc. FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows user to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of 4 TOSC * (Timer2 Prescale Value) before the next PWM period begins. The Timer2 prescaler will be either 1, 4 or 16, depending on the value of the T2CKPS1:T2CKPS0 bits (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 16-8. Note that in the Full-Bridge Output mode, the CCP1 module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. Figure 16-9 shows an example where the PWM direction changes from forward to reverse at a near 100% duty cycle. At time t1, the outputs P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices, QC and QD (see Figure 16-7), for the duration of ‘t’. The same phenomenon will occur to power devices, QA and QB, for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. P1A P1C FET Driver FET Driver V+ VLoad FET Driver FET Driver P1B P1D QA QB QD PIC18F4X2X QC © 2007 Microchip Technology Inc. Preliminary DS39631B-page 155 PIC18F2420/2520/4420/4520 FIGURE 16-8: PWM DIRECTION CHANGE FIGURE 16-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE DC Period(1) SIGNAL Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. Period (Note 2) P1A (Active-High) P1B (Active-High) P1C (Active-High) P1D (Active-High) DC Forward Period Reverse Period P1A(1) tON (2) tOFF (3) t = tOFF – tON (2,3) P1B(1) P1C(1) P1D(1) External Switch D(1) Potential Shoot-Through Current(1) Note 1: All signals are shown as active-high. 2: tON is the turn-on delay of power switch QC and its driver. 3: tOFF is the turn-off delay of power switch QD and its driver. External Switch C(1) t1 DC DC PIC18F2420/2520/4420/4520 DS39631B-page 156 Preliminary © 2007 Microchip Technology Inc. 16.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the nonactive state to the active state. See Figure 16-4 for illustration. Bits PDC6:PDC0 of the PWM1CON register (Register 16-2) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). These bits are not available on 28-pin devices as the standard CCP module does not support half-bridge operation. 16.4.7 ENHANCED PWM AUTO-SHUTDOWN When the CCP1 is programmed for any of the enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. A shutdown event can be caused by either of the comparator modules, a low level on the Fault input pin (FLT0) or any combination of these three sources. The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a low digital signal on FLT0 can also trigger a shutdown. The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The autoshutdown sources to be used are selected using the ECCPAS2:ECCPAS0 bits (bits<6:4> of the ECCP1AS register). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits (ECCPAS2:ECCPAS0). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low or be tristated (not driving). The ECCPASE bit (ECCP1AS<7>) is also set to hold the enhanced PWM outputs in their shutdown states. The ECCPASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCPASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the cause of the auto-shutdown has cleared. If the ECCPASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. REGISTER 16-2: PWM1CON: PWM CONFIGURATION REGISTER Note: Programmable dead-band delay is not implemented in 28-pin devices with standard CCP modules. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) bit 7 bit 0 bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC6:PDC0: PWM Delay Count bits(1) Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Note 1: Reserved on 28-pin devices; maintain these bits clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 157 PIC18F2420/2520/4420/4520 REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) bit 7 bit 0 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits 111 = FLT0 or Comparator 1 or Comparator 2 110 = FLT0 or Comparator 2 101 = FLT0 or Comparator 1 100 = FLT0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits 1x = Pins A and C are tri-state (40/44-pin devices); PWM output is tri-state (28-pin devices) 01 = Drive Pins A and C to ‘1’ 00 = Drive Pins A and C to ‘0’ bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1) 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ 00 = Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 158 Preliminary © 2007 Microchip Technology Inc. 16.4.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared. If PRSEN = 0 (Figure 16-11), once a shutdown condition occurs, the ECCPASE bit will remain set until it is cleared by firmware. Once ECCPASE is cleared, the enhanced PWM will resume at the beginning of the next PWM period. Independent of the PRSEN bit setting, if the autoshutdown source is one of the comparators, the shutdown condition is a level. The ECCPASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a ‘1’ to the ECCPASE bit. 16.4.8 START-UP CONSIDERATIONS When the ECCP module is used in the PWM mode, the application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the off state until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended, since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the application circuit. The ECCP module must be enabled in the proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 16-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. Shutdown PWM ECCPASE bit Activity Event Shutdown Event Occurs Shutdown Event Clears PWM Resumes Normal PWM Start of PWM Period PWM Period Shutdown PWM ECCPASE bit Activity Event Shutdown Event Occurs Shutdown Event Clears PWM Resumes Normal PWM Start of PWM Period ECCPASE Cleared by Firmware PWM Period © 2007 Microchip Technology Inc. Preliminary DS39631B-page 159 PIC18F2420/2520/4420/4520 16.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation: 1. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. 2. Set the PWM period by loading the PR2 register. 3. If auto-shutdown is required: • Disable auto-shutdown (ECCP1AS = 0) • Configure source (FLT0, Comparator 1 or Comparator 2) • Wait for non-shutdown condition 4. Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: • Select one of the available output configurations and direction with the P1M1:P1M0 bits. • Select the polarities of the PWM output signals with the CCP1M3:CCP1M0 bits. 5. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. 6. For Half-Bridge Output mode, set the deadband delay by loading PWM1CON<6:0> with the appropriate value. 7. If auto-shutdown operation is required, load the ECCP1AS register: • Select the auto-shutdown sources using the ECCPAS2:ECCPAS0 bits. • Select the shutdown states of the PWM output pins using the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits. • Set the ECCPASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 8. If auto-restart operation is required, set the PRSEN bit (PWM1CON<7>). 9. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). • Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: • Wait until TMRn overflows (TMRnIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). 16.4.10 OPERATION IN POWER MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from INTOSC and the postscaler may not be stable immediately. In PRI_IDLE mode, the primary clock will continue to clock the ECCP module without change. In all other power managed modes, the selected power managed mode clock will clock Timer2. Other power managed mode clocks will most likely be different than the primary clock frequency. 16.4.10.1 Operation with Fail-Safe Clock Monitor If the Fail-Safe Clock Monitor is enabled, a clock failure will force the device into the RC_RUN Power Managed mode and the OSCFIF bit (PIR2<7>) will be set. The ECCP will then be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. See the previous section for additional details. 16.4.11 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the enhanced CCP module to reset to a state compatible with the standard CCP module. PIC18F2420/2520/4420/4520 DS39631B-page 160 Preliminary © 2007 Microchip Technology Inc. TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 RCON IPEN SBOREN — RI TO PD POR BOR 48 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 TRISB PORTB Data Direction Control Register 52 TRISC PORTC Data Direction Control Register 52 TRISD PORTD Data Direction Control Register 52 TMR1L Timer1 Register, Low Byte 50 TMR1H Timer1 Register, High Byte 50 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 TMR2 Timer2 Register 50 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50 PR2 Timer2 Period Register 50 TMR3L Timer3 Register, Low Byte 51 TMR3H Timer3 Register, High Byte 51 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51 CCPR1L Capture/Compare/PWM Register 1, Low Byte 51 CCPR1H Capture/Compare/PWM Register 1, High Byte 51 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 51 PWM1CON PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 161 PIC18F2420/2520/4420/4520 17.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 17.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode 17.2 Control Registers The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections. 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) – RC5/SDO • Serial Data In (SDI) – RC4/SDI/SDA • Serial Clock (SCK) – RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) – RA5/SS Figure 17-1 shows the block diagram of the MSSP module when operating in SPI mode. FIGURE 17-1: MSSP BLOCK DIAGRAM (SPI MODE) ( ) Read Write Internal Data Bus SSPSR reg SSPM3:SSPM0 bit 0 Shift Clock SS Control Enable Edge Select Clock Select TMR2 Output Prescaler TOSC 4, 16, 64 2 Edge Select 2 4 Data to TX/RX in SSPSR TRIS bit 2 SMP:CKE RC5/SDO SSPBUF reg RC4/SDI/SDA RA5/AN4/SS/ RC3/SCK/ SCL HLVDIN/C2OUT PIC18F2420/2520/4420/4520 DS39631B-page 162 Preliminary © 2007 Microchip Technology Inc. 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR. REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 163 PIC18F2420/2520/4420/4520 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 164 Preliminary © 2007 Microchip Technology Inc. 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • Clock Polarity (Idle state of SCK) • Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The Buffer Full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions. EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit © 2007 Microchip Technology Inc. Preliminary DS39631B-page 165 PIC18F2420/2520/4420/4520 17.3.3 ENABLING SPI I/O To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDI is automatically controlled by the SPI module • SDO must have TRISC<5> bit cleared • SCK (Master mode) must have TRISC<3> bit cleared • SCK (Slave mode) must have TRISC<3> bit set • SS must have TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: • Master sends data – Slave sends dummy data • Master sends data – Slave sends data • Master sends dummy data – Slave sends data FIGURE 17-2: SPI MASTER/SLAVE CONNECTION Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb SDO SDI PROCESSOR 1 SCK SPI Master SSPM3:SSPM0 = 00xxb Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb SDI SDO PROCESSOR 2 SCK SPI Slave SSPM3:SSPM0 = 010xb Serial Clock PIC18F2420/2520/4420/4520 DS39631B-page 166 Preliminary © 2007 Microchip Technology Inc. 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 17-3, Figure 17-5 and Figure 17-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • FOSC/4 (or TCY) • FOSC/16 (or 4 • TCY) • FOSC/64 (or 16 • TCY) • Timer2 output/2 This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 17-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE) SCK (CKP = 0 SCK (CKP = 1 SCK (CKP = 0 SCK (CKP = 1 4 Clock Modes Input Sample Input Sample SDI bit 7 bit 0 SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 SDI SSPIF (SMP = 1) (SMP = 0) (SMP = 1) CKE = 1) CKE = 0) CKE = 1) CKE = 0) (SMP = 0) Write to SSPBUF SSPSR to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) (CKE = 1) Next Q4 Cycle after Q2↓ bit 0 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 167 PIC18F2420/2520/4420/4520 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit (SSPCON1<4>). While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from Sleep. 17.3.7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The data latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SS pin control must be enabled. SCK (CKP = 1 SCK (CKP = 0 Input Sample SDI bit 7 SDO bit 7 bit 6 bit 7 SSPIF Interrupt (SMP = 0) CKE = 0) CKE = 0) (SMP = 0) Write to SSPBUF SSPSR to SSPBUF SS Flag bit 0 bit 7 bit 0 Next Q4 Cycle after Q2↓ PIC18F2420/2520/4420/4520 DS39631B-page 168 Preliminary © 2007 Microchip Technology Inc. FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SCK (CKP = 1 SCK (CKP = 0 Input Sample SDI bit 7 SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPIF Interrupt (SMP = 0) CKE = 0) CKE = 0) (SMP = 0) Write to SSPBUF SSPSR to SSPBUF SS Flag Optional Next Q4 Cycle after Q2↓ bit 0 SCK (CKP = 1 SCK (CKP = 0 Input Sample SDI bit 7 bit 0 SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPIF Interrupt (SMP = 0) CKE = 1) CKE = 1) (SMP = 0) Write to SSPBUF SSPSR to SSPBUF SS Flag Not Optional Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. Preliminary DS39631B-page 169 PIC18F2420/2520/4420/4520 17.3.8 OPERATION IN POWER MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. In most Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 2.7 “Clock Sources and Oscillator Switching” for additional information. In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power managed mode and data to be shifted into the SPI Transmit/ Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.3.10 BUS MODE COMPATIBILITY Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 17-1: SPI BUS MODES There is also an SMP bit which controls when the data is sampled. TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION Standard SPI Mode Terminology Control Bits State CKP CKE 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 52 TRISC PORTC Data Direction Control Register 52 SSPBUF SSP Receive Buffer/Transmit Register 50 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50 SSPSTAT SMP CKE D/A P S R/W UA BF 50 Legend: Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. PIC18F2420/2520/4420/4520 DS39631B-page 170 Preliminary © 2007 Microchip Technology Inc. 17.4 I2C Mode The MSSP module in I2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: • Serial clock (SCL) – RC3/SCK/SCL • Serial data (SDA) – RC4/SDI/SDA The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. FIGURE 17-7: MSSP BLOCK DIAGRAM (I2C MODE) 17.4.1 REGISTERS The MSSP module has six registers for I2C operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Control Register 2 (SSPCON2) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible • MSSP Address Register (SSPADD) SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When the SSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload value. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Read Write SSPSR reg Match Detect SSPADD reg Start and Stop bit Detect SSPBUF reg Internal Data Bus Addr Match Set, Reset S, P bits (SSPSTAT reg) RC3/SCK/SCL RC4/SDI/ Shift Clock MSb SDA LSb © 2007 Microchip Technology Inc. Preliminary DS39631B-page 171 PIC18F2420/2520/4420/4520 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high-speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 2 R/W: Read/Write Information bit (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 172 Preliminary © 2007 Microchip Technology Inc. REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 173 PIC18F2420/2520/4420/4520 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only)(1) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(1) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(1) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(1) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 174 Preliminary © 2007 Microchip Technology Inc. 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: • I2C Master mode, clock = (FOSC/4) x (SSPADD + 1) • I2C Slave mode (7-bit address) • I2C Slave mode (10-bit address) • I2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled • I2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled • I2C Firmware Controlled Master mode, slave is Idle Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins. 17.4.3 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I2C Slave mode hardware will always generate an interrupt on an address match. Through the mode select bits, the user can also choose to interrupt on Start and Stop bits When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: • The Buffer Full bit, BF (SSPSTAT<0>), was set before the transfer was received. • The overflow bit, SSPOV (SSPCON<6>), was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. 17.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. The SSPSR register value is loaded into the SSPBUF register. 2. The Buffer Full bit, BF, is set. 3. An ACK pulse is generated. 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is set (interrupt is generated, if enabled) on the falling edge of the ninth SCL pulse. In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. Receive first (high) byte of address (bits SSPIF, BF and UA (SSPSTAT<1>) are set). 2. Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). 3. Read the SSPBUF register (clears bit BF) and clear flag bit, SSPIF. 4. Receive second (low) byte of address (bits SSPIF, BF and UA are set). 5. Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit UA. 6. Read the SSPBUF register (clears bit BF) and clear flag bit, SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit, SSPIF. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 175 PIC18F2420/2520/4420/4520 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set. An MSSP interrupt is generated for each data transfer byte. Flag bit, SSPIF (PIR1<3>), must be cleared in software. The SSPSTAT register is used to determine the status of the byte. If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit, CKP (SSPCON<4>). See Section 17.4.4 “Clock Stretching” for more detail. 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section 17.4.4 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. Then pin RC3/ SCK/SCL should be enabled by setting bit, CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 17-9). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. PIC18F2420/2520/4420/4520 DS39631B-page 176 Preliminary © 2007 Microchip Technology Inc. FIGURE 17-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) SDA SCL SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0 R/W = 0 Receiving Data ACK Receiving Data ACK ACK Receiving Address Cleared in software SSPBUF is read Bus master terminates transfer SSPOV is set because SSPBUF is still full. ACK is not sent. D2 6 (PIR1<3>) CKP (CKP does not reset to ‘0’ when SEN = 0) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 177 PIC18F2420/2520/4420/4520 FIGURE 17-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) SDA SCL SSPIF (PIR1<3>) BF (SSPSTAT<0>) A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 SSPBUF is written in software Cleared in software From SSPIF ISR Data in sampled S ACK R/W = 0 Transmitting Data ACK Receiving Address A7 D7 9 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPBUF is written in software Cleared in software From SSPIF ISR Transmitting Data D7 1 CKP P ACK CKP is set in software CKP is set in software SCL held low while CPU responds to SSPIF PIC18F2420/2520/4420/4520 DS39631B-page 178 Preliminary © 2007 Microchip Technology Inc. FIGURE 17-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) SDA SCL SSPIF BF (SSPSTAT<0>) S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P 1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0 Receive Data Byte ACK R/W = 0 ACK Receive First Byte of Address Cleared in software D2 6 (PIR1<3>) Cleared in software Receive Second Byte of Address Cleared by hardware when SSPADD is updated with low byte of address UA (SSPSTAT<1>) Clock is held low until update of SSPADD has taken place UA is set indicating that the SSPADD needs to be updated UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address SSPBUF is written with contents of SSPSR Dummy read of SSPBUF to clear BF flag ACK CKP 1 2 3 4 5 7 8 9 D7 D6 D5 D4 D3 D1 D0 Receive Data Byte Bus master terminates transfer D2 6 ACK Cleared in software Cleared in software SSPOV (SSPCON1<6>) SSPOV is set because SSPBUF is still full. ACK is not sent. (CKP does not reset to ‘0’ when SEN = 0) Clock is held low until update of SSPADD has taken place © 2007 Microchip Technology Inc. Preliminary DS39631B-page 179 PIC18F2420/2520/4420/4520 FIGURE 17-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) SDA SCL SSPIF BF (SSPSTAT<0>) S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P 1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 A8 R/W=1 ACK ACK R/W = 0 ACK Receive First Byte of Address Cleared in software Bus master terminates transfer A9 6 (PIR1<3>) Receive Second Byte of Address Cleared by hardware when SSPADD is updated with low byte of address UA (SSPSTAT<1>) Clock is held low until update of SSPADD has taken place UA is set indicating that the SSPADD needs to be updated UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address. SSPBUF is written with contents of SSPSR Dummy read of SSPBUF to clear BF flag Receive First Byte of Address 1 2 3 4 5 7 8 9 D7 D6 D5 D4 D3 D1 ACK D2 6 Transmitting Data Byte D0 Dummy read of SSPBUF to clear BF flag Sr Cleared in software Write of SSPBUF initiates transmit Cleared in software Completion of clears BF flag CKP (SSPCON1<4>) CKP is set in software CKP is automatically cleared in hardware, holding SCL low Clock is held low until update of SSPADD has taken place data transmission Clock is held low until CKP is set to ‘1’ third address sequence BF flag is clear at the end of the PIC18F2420/2520/4420/4520 DS39631B-page 180 Preliminary © 2007 Microchip Technology Inc. 17.4.4 CLOCK STRETCHING Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.1 Clock Stretching for 7-bit Slave Receive Mode (SEN = 1) In 7-bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence if the BF bit is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held low. The CKP being cleared to ‘0’ will assert the SCL line low. The CKP bit must be set in the user’s ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 17-13). 17.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. 17.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode 7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user’s ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 17-9). 17.4.4.4 Clock Stretching for 10-bit Slave Transmit Mode In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-bit Slave Receive mode. The first two addresses are followed by a third address sequence which contains the high-order bits of the 10-bit address and the R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 17-11). Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. Note 1: If the user loads the contents of SSPBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 181 PIC18F2420/2520/4420/4520 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12). FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING SDA SCL DX DX – 1 WR Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SSPCON CKP Master device deasserts clock Master device asserts clock PIC18F2420/2520/4420/4520 DS39631B-page 182 Preliminary © 2007 Microchip Technology Inc. FIGURE 17-13: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) SDA SCL SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0 R/W = 0 Receiving Data ACK Receiving Data ACK ACK Receiving Address Cleared in software SSPBUF is read Bus master terminates transfer SSPOV is set because SSPBUF is still full. ACK is not sent. D2 6 (PIR1<3>) CKP CKP written to ‘1’ in If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur software Clock is held low until CKP is set to ‘1’ Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is not held low because ACK = 1 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs © 2007 Microchip Technology Inc. Preliminary DS39631B-page 183 PIC18F2420/2520/4420/4520 FIGURE 17-14: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) SDA SCL SSPIF BF (SSPSTAT<0>) S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P 1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0 Receive Data Byte ACK R/W = 0 ACK Receive First Byte of Address Cleared in software D2 6 (PIR1<3>) Cleared in software Receive Second Byte of Address Cleared by hardware when SSPADD is updated with low byte of address after falling edge UA (SSPSTAT<1>) Clock is held low until update of SSPADD has taken place UA is set indicating that the SSPADD needs to be updated UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address after falling edge SSPBUF is written with contents of SSPSR Dummy read of SSPBUF to clear BF flag ACK CKP 1 2 3 4 5 7 8 9 D7 D6 D5 D4 D3 D1 D0 Receive Data Byte Bus master terminates transfer D2 6 ACK Cleared in software Cleared in software SSPOV (SSPCON1<6>) CKP written to ‘1’ Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. in software Clock is held low until update of SSPADD has taken place of ninth clock of ninth clock SSPOV is set because SSPBUF is still full. ACK is not sent. Dummy read of SSPBUF to clear BF flag Clock is held low until CKP is set to ‘1’ Clock is not held low because ACK = 1 PIC18F2420/2520/4420/4520 DS39631B-page 184 Preliminary © 2007 Microchip Technology Inc. 17.4.5 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all ‘0’s with R/W = 0. The general call address is recognized when the General Call Enable bit, GCEN, is enabled (SSPCON2<7> is set). Following a Start bit detect, 8 bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 17-15). FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) SDA SCL S SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) Cleared in software SSPBUF is read R/W = 0 General Call Address ACK Address is compared to General Call Address GCEN (SSPCON2<7>) Receiving Data ACK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 after ACK, set interrupt ‘0’ ‘1’ © 2007 Microchip Technology Inc. Preliminary DS39631B-page 185 PIC18F2420/2520/4420/4520 17.4.6 MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P bits clear. In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and Stop bit conditions. Once Master mode is enabled, the user has six options. 1. Assert a Start condition on SDA and SCL. 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP interrupt, if enabled): • Start condition • Stop condition • Data transfer byte transmitted/received • Acknowledge transmit • Repeated Start FIGURE 17-16: MSSP BLOCK DIAGRAM (I2C MASTER MODE) Note: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. Read Write SSPSR Start bit, Stop bit, SSPBUF Internal Data Bus Set/Reset, S, P, WCOL (SSPSTAT) Shift Clock MSb LSb SDA Acknowledge Generate Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV SCL SCL In Bus Collision SDA In Receive Enable Clock Cntl Clock Arbitrate/WCOL Detect (hold off clock source) SSPADD<6:0> Baud Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2) Rate Generator SSPM3:SSPM0 Start bit Detect PIC18F2420/2520/4420/4520 DS39631B-page 186 Preliminary © 2007 Microchip Technology Inc. 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. The Baud Rate Generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 17.4.7 “Baud Rate” for more detail. A typical transmit sequence would go as follows: 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPCON2<0>). 2. SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPBUF with the slave address to transmit. 4. Address is shifted out the SDA pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 7. The user loads the SSPBUF with eight bits of data. 8. Data is shifted out the SDA pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 187 PIC18F2420/2520/4420/4520 17.4.7 BAUD RATE In I2C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to ‘0’ and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. Table 17-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM TABLE 17-3: I2C CLOCK RATE W/BRG SSPM3:SSPM0 CLKO BRG Down Counter FOSC/4 SSPADD<6:0> SSPM3:SSPM0 SCL Reload Control Reload FCY FCY*2 BRG Value FSCL (2 Rollovers of BRG) 10 MHz 20 MHz 18h 400 kHz(1) 10 MHz 20 MHz 1Fh 312.5 kHz 10 MHz 20 MHz 63h 100 kHz 4 MHz 8 MHz 09h 400 kHz(1) 4 MHz 8 MHz 0Ch 308 kHz 4 MHz 8 MHz 27h 100 kHz 1 MHz 2 MHz 02h 333 kHz(1) 1 MHz 2 MHz 09h 100 kHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. PIC18F2420/2520/4420/4520 DS39631B-page 188 Preliminary © 2007 Microchip Technology Inc. 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 17-18). FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA SCL SCL deasserted but slave holds DX DX – 1 BRG SCL is sampled high, reload takes place and BRG starts its count 03h 02h 01h 00h (hold off) 03h 02h Reload BRG Value SCL low (clock arbitration) SCL allowed to transition high BRG decrements on Q2 and Q4 cycles © 2007 Microchip Technology Inc. Preliminary DS39631B-page 189 PIC18F2420/2520/4420/4520 17.4.8 I2C MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. 17.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 17-19: FIRST START BIT TIMING Note: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete. SDA SCL S TBRG 1st bit 2nd bit TBRG SDA = 1, SCL = At completion of Start bit, 1 TBRG Write to SSPBUF occurs here hardware clears SEN bit TBRG Write to SEN bit occurs here Set S bit (SSPSTAT<3>) and sets SSPIF bit PIC18F2420/2520/4420/4520 DS39631B-page 190 Preliminary © 2007 Microchip Technology Inc. 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 17.4.9.1 WCOL Status Flag If the user writes the SSPBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 17-20: REPEAT START CONDITION WAVEFORM Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. SDA SCL Sr = Repeated Start Write to SSPCON2 on falling edge of ninth clock, Write to SSPBUF occurs here end of Xmit At completion of Start bit, hardware clears RSEN bit 1st bit S bit set by hardware TBRG TBRG SDA = 1, SDA = 1, SCL (no change). SCL = 1 occurs here. TBRG TBRG TBRG and sets SSPIF RSEN bit set by hardware © 2007 Microchip Technology Inc. Preliminary DS39631B-page 191 PIC18F2420/2520/4420/4520 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106). SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 17-21). After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 17.4.10.1 BF Status Flag In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 17.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 17.4.11 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPCON2<3>). The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/ low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>). 17.4.11.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 17.4.11.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 17.4.11.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. PIC18F2420/2520/4420/4520 DS39631B-page 192 Preliminary © 2007 Microchip Technology Inc. FIGURE 17-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) SDA SCL SSPIF BF (SSPSTAT<0>) SEN A7 A6 A5 A4 A3 A2 A1 ACK = ‘0’ D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data or Second Half Transmit Address to Slave R/W = 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software service routine SSPBUF is written in software from SSP interrupt After Start condition, SEN cleared by hardware S SSPBUF written with 7-bit address and R/W start transmit SCL held low while CPU responds to SSPIF SEN = 0 of 10-bit Address Write SSPCON2<0> SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSPCON2<6> ACKSTAT in SSPCON2 = 1 Cleared in software SSPBUF written PEN R/W Cleared in software © 2007 Microchip Technology Inc. Preliminary DS39631B-page 193 PIC18F2420/2520/4420/4520 FIGURE 17-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) P 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 S SDA A7 A6 A5 A4 A3 A2 A1 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 Bus master terminates transfer ACK Receiving Data from Slave Receiving Data from Slave ACK D7 D6 D5 D4 D3 D2 D1 D0 Transmit Address to Slave R/W = 0 SSPIF BF ACK is not sent Write to SSPCON2<0> (SEN = 1), Write to SSPBUF occurs here, ACK from Slave Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) PEN bit = 1 written here Data shifted in on falling edge of CLK Cleared in software start XMIT SEN = 0 SSPOV SDA = 0, SCL = 1 while CPU (SSPSTAT<0>) ACK Cleared in software Cleared in software Set SSPIF interrupt at end of receive Set P bit (SSPSTAT<4>) and SSPIF Cleared in software ACK from Master Set SSPIF at end Set SSPIF interrupt at end of Acknowledge sequence Set SSPIF interrupt at end of Acknowledge sequence of receive Set ACKEN, start Acknowledge sequence SSPOV is set because SSPBUF is still full SDA = ACKDT = 1 RCEN cleared automatically RCEN = 1, start next receive Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 RCEN cleared automatically responds to SSPIF ACKEN begin Start condition Cleared in software SDA = ACKDT = 0 Last bit is shifted into SSPSR and contents are unloaded into SSPBUF PIC18F2420/2520/4420/4520 DS39631B-page 194 Preliminary © 2007 Microchip Technology Inc. 17.4.12 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 17-23). 17.4.12.1 WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). 17.4.13 STOP CONDITION TIMING A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 17-24). 17.4.13.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Note: TBRG = one Baud Rate Generator period. SDA SCL SSPIF set at Acknowledge sequence starts here, write to SSPCON2 ACKEN automatically cleared Cleared in TBRG TBRG the end of receive 8 ACKEN = 1, ACKDT = 0 D0 9 SSPIF software SSPIF set at the end of Acknowledge sequence Cleared in software ACK SCL SDA SDA asserted low before rising edge of clock Write to SSPCON2, set PEN Falling edge of SCL = 1 for TBRG, followed by SDA = 1 for TBRG 9th clock SCL brought high after TBRG Note: TBRG = one Baud Rate Generator period. TBRG TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. TBRG to setup Stop condition ACK P TBRG PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set © 2007 Microchip Technology Inc. Preliminary DS39631B-page 195 PIC18F2420/2520/4420/4520 17.4.14 SLEEP OPERATION While in Sleep mode, the I2C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit (SSPSTAT<4>) is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: • Address Transfer • Data Transfer • A Start Condition • A Repeated Start Condition • An Acknowledge Condition 17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its Idle state (Figure 17-25). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA SCL BCLIF SDA released SDA line pulled low by another source Sample SDA. While SCL is high, data doesn’t match what is driven Bus collision has occurred. Set bus collision interrupt (BCLIF) by the master. by master Data changes while SCL = 0 PIC18F2420/2520/4420/4520 DS39631B-page 196 Preliminary © 2007 Microchip Technology Inc. 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). b) SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCLIF flag is set and • the MSSP module is reset to its Idle state (Figure 17-26). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to 0; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY) Note: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. SDA SCL SEN SDA sampled low before SDA goes low before the SEN bit is set. S bit and SSPIF set because SSP module reset into Idle state. SEN cleared automatically because of bus collision. S bit and SSPIF set because Set SEN, enable Start condition if SDA = 1, SCL = 1 SDA = 0, SCL = 1. BCLIF S SSPIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software Set BCLIF, Start condition. Set BCLIF. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 197 PIC18F2420/2520/4420/4520 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA SCL SEN bus collision occurs. Set BCLIF. SCL = 0 before SDA = 0, Set SEN, enable Start sequence if SDA = 1, SCL = 1 TBRG TBRG SDA = 0, SCL = 1 BCLIF S SSPIF Interrupt cleared in software bus collision occurs. Set BCLIF. SCL = 0 before BRG time-out, ‘0’ ‘0’ ‘0’ ‘0’ SDA SCL SEN Set S Less than TBRG TBRG SDA = 0, SCL = 1 BCLIF S SSPIF S Interrupts cleared set SSPIF in software SDA = 0, SCL = 1, SCL pulled low after BRG time-out Set SSPIF ‘0’ SDA pulled low by other master. Reset BRG and assert SDA. Set SEN, enable START sequence if SDA = 1, SCL = 1 PIC18F2420/2520/4420/4520 DS39631B-page 198 Preliminary © 2007 Microchip Technology Inc. 17.4.17.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if: a) A low level is sampled on SDA when SCL goes from low level to high level. b) SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’. When the user deasserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to 0. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 17-30. If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) FIGURE 17-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) SDA SCL RSEN BCLIF S SSPIF Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software ‘0’ ‘0’ SDA SCL BCLIF RSEN S SSPIF Interrupt cleared in software SCL goes low before SDA, set BCLIF. Release SDA and SCL. TBRG TBRG ‘0’ © 2007 Microchip Technology Inc. Preliminary DS39631B-page 199 PIC18F2420/2520/4420/4520 17.4.17.3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: a) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. b) After the SCL pin is deasserted, SCL is sampled low before SDA goes high. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 17-31). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 17-32). FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) SDA SCL BCLIF PEN P SSPIF TBRG TBRG TBRG SDA asserted low SDA sampled low after TBRG, set BCLIF ‘0’ ‘0’ SDA SCL BCLIF PEN P SSPIF TBRG TBRG TBRG Assert SDA SCL goes low before SDA goes high, set BCLIF ‘0’ ‘0’ PIC18F2420/2520/4420/4520 DS39631B-page 200 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 201 PIC18F2420/2520/4420/4520 18.0 ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a halfduplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. The EUSART can be configured in the following modes: • Asynchronous (full duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission • Synchronous – Master (half duplex) with selectable clock polarity • Synchronous – Slave (half duplex) with selectable clock polarity The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/DT as a USART: • bit SPEN (RCSTA<7>) must be set (= 1) • bit TRISC<7> must be set (= 1) • bit TRISC<6> must be set (= 1) The operation of the Enhanced USART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These are detailed on the following pages in Register 18-1, Register 18-2 and Register 18-3, respectively. Note: The EUSART control will automatically reconfigure the pin from input to output as needed. PIC18F2420/2520/4420/4520 DS39631B-page 202 Preliminary © 2007 Microchip Technology Inc. REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 203 PIC18F2420/2520/4420/4520 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 204 Preliminary © 2007 Microchip Technology Inc. REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. Preliminary DS39631B-page 205 PIC18F2420/2520/4420/4520 18.1 Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also control the baud rate. In Synchronous mode, BRGH is ignored. Table 18-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 18-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 18-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 18-2. It may be advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 18.1.1 OPERATION IN POWER MANAGED MODES The device clock is used to generate the desired baud rate. When one of the power managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRG register pair. 18.1.2 SAMPLING The data on the RX pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. TABLE 18-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair PIC18F2420/2520/4420/4520 DS39631B-page 206 Preliminary © 2007 Microchip Technology Inc. EXAMPLE 18-1: CALCULATING BAUD RATE ERROR TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register, High Byte 51 SPBRG EUSART Baud Rate Generator Register, Low Byte 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 207 PIC18F2420/2520/4420/4520 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES BAUD RATE (K) SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — BAUD RATE (K) SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — BAUD RATE (K) SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — BAUD RATE (K) SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 — — — — — — 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — PIC18F2420/2520/4420/4520 DS39631B-page 208 Preliminary © 2007 Microchip Technology Inc. BAUD RATE (K) SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — BAUD RATE (K) SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — BAUD RATE (K) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 BAUD RATE (K) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832 1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 209 PIC18F2420/2520/4420/4520 18.1.3 AUTO-BAUD RATE DETECT The enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 18-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII “U”, which is also the LIN bus Sync character) in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up, using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCON<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 18-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table 18-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. TABLE 18-4: BRG COUNTER CLOCK RATES 18.1.3.1 ABD and EUSART Transmission Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREG cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. BRG16 BRGH BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/128 1 0 FOSC/128 1 1 FOSC/32 Note: During the ABD sequence, SPBRG and SPBRGH are both used as a 16-bit counter, independent of BRG16 setting. PIC18F2420/2520/4420/4520 DS39631B-page 210 Preliminary © 2007 Microchip Technology Inc. FIGURE 18-1: AUTOMATIC BAUD RATE CALCULATION FIGURE 18-2: BRG OVERFLOW SEQUENCE BRG Value RX pin ABDEN bit RCIF bit Bit 0 Bit 1 (Interrupt) Read RCREG BRG Clock Start Set by User Auto-Cleared XXXXh 0000h Edge #1 Bit 2 Bit 3 Edge #2 Bit 4 Bit 5 Edge #3 Bit 6 Bit 7 Edge #4 Stop Bit Edge #5 001Ch Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Start Bit 0 XXXXh 0000h 0000h FFFFh BRG Clock ABDEN bit RX pin ABDOVF bit BRG Value © 2007 Microchip Technology Inc. Preliminary DS39631B-page 211 PIC18F2420/2520/4420/4520 18.2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. When operating in Asynchronous mode, the EUSART module consists of the following important elements: • Baud Rate Generator • Sampling Circuit • Asynchronous Transmitter • Asynchronous Receiver • Auto-Wake-up on Sync Break Character • 12-bit Break Character Transmit • Auto-Baud Rate Detection 18.2.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 18-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF will be set regardless of the state of TXIE; it cannot be cleared in software. TXIF is also not cleared immediately upon loading TXREG, but becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. To set up an Asynchronous Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. 5. Enable the transmission by setting bit TXEN which will also set bit TXIF. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Load data to the TXREG register (starts transmission). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 18-3: EUSART TRANSMIT BLOCK DIAGRAM Note 1: The TSR register is not mapped in data memory so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF TXIE Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator TX9D MSb LSb Data Bus TXREG Register TSR Register (8) 0 TX9 TRMT SPEN TX pin Pin Buffer and Control 8 • • • BRG16 SPBRGH PIC18F2420/2520/4420/4520 DS39631B-page 212 Preliminary © 2007 Microchip Technology Inc. FIGURE 18-4: ASYNCHRONOUS TRANSMISSION FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Word 1 Word 1 Transmit Shift Reg Start bit bit 0 bit 1 bit 7/8 Write to TXREG BRG Output (Shift Clock) TX (pin) TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) 1 TCY Stop bit Word 1 Transmit Shift Reg. Write to TXREG BRG Output (Shift Clock) TX (pin) TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Word 2 Word 1 Word 2 Stop bit Start bit Transmit Shift Reg. Word 1 Word 2 bit 0 bit 1 bit 7/8 bit 0 Note: This timing diagram shows two consecutive transmissions. 1 TCY 1 TCY Start bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 TXREG EUSART Transmit Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register, High Byte 51 SPBRG EUSART Baud Rate Generator Register, Low Byte 51 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: Reserved in 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 213 PIC18F2420/2520/4420/4520 18.2.2 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 18-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCIE, was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 18.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. FIGURE 18-6: EUSART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK Baud Rate Generator RX Pin Buffer and Control SPEN Data Recovery CREN OERR FERR MSb RSR Register LSb RX9D RCREG Register FIFO Interrupt RCIF RCIE Data Bus 8 ÷ 64 ÷ 16 or Stop (8) 7 1 0 Start RX9 • • • BRG16 SPBRGH SPBRG or ÷ 4 PIC18F2420/2520/4420/4520 DS39631B-page 214 Preliminary © 2007 Microchip Technology Inc. FIGURE 18-7: ASYNCHRONOUS RECEPTION TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION 18.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>). Once set, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 18-8) and asynchronously, if the device is in Sleep mode (Figure 18-9). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-tohigh transition is observed on the RX line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCREG EUSART Receive Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register, High Byte 51 SPBRG EUSART Baud Rate Generator Register, Low Byte 51 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. Start bit bit 0 bit 1 bit 7/8 Stop bit 0 bit 7/8 bit Start bit Start bit 7/8 Stop bit bit RX (pin) Rcv Buffer Reg Rcv Shift Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Word 1 RCREG Word 2 RCREG Stop bit Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (overrun) bit to be set. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 215 PIC18F2420/2520/4420/4520 18.2.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false end-ofcharacter and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., XT or HS mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. 18.2.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION FIGURE 18-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit(1) RX/DT Line RCIF Note 1: The EUSART remains in Idle while the WUE bit is set. Bit set by user Cleared due to user read of RCREG Auto-Cleared Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit(2) RX/DT Line RCIF Bit set by user Cleared due to user read of RCREG Sleep Command Executed Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. Sleep Ends Note 1 Auto-Cleared PIC18F2420/2520/4420/4520 DS39631B-page 216 Preliminary © 2007 Microchip Technology Inc. 18.2.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 18-10 for the timing of the Break character sequence. 18.2.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN bus master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to set up the Break character. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 18.2.6 RECEIVING A BREAK CHARACTER The enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 18.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. FIGURE 18-10: SEND BREAK CHARACTER SEQUENCE Write to TXREG BRG Output (Shift Clock) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TX (pin) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared Dummy Write © 2007 Microchip Technology Inc. Preliminary DS39631B-page 217 PIC18F2420/2520/4420/4520 18.3 EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the TX and RX pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCON<4>); setting SCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 18.3.1 EUSART SYNCHRONOUS MASTER TRANSMISSION The EUSART transmitter block diagram is shown in Figure 18-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 18-11: SYNCHRONOUS TRANSMISSION bit 0 bit 1 bit 7 Word 1 Q1 Q2 Q3Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4Q1 Q2 Q3 Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 2 bit 0 bit 1 bit 7 RC7/RX/DT RC6/TX/CK pin Write to TXREG Reg TXIF bit (Interrupt Flag) TXEN bit ‘1’ ‘1’ Word 2 TRMT bit Write Word 1 Write Word 2 Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. RC6/TX/CK pin (SCKP = 0) (SCKP = 1) PIC18F2420/2520/4420/4520 DS39631B-page 218 Preliminary © 2007 Microchip Technology Inc. FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit bit 0 bit 1 bit 2 bit 6 bit 7 TXEN bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 TXREG EUSART Transmit Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register, High Byte 51 SPBRG EUSART Baud Rate Generator Register, Low Byte 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: Reserved in 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 219 PIC18F2420/2520/4420/4520 18.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set enable bit RCIE. 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 18-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCREG EUSART Receive Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register, High Byte 51 SPBRG EUSART Baud Rate Generator Register, Low Byte 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. CREN bit RC7/RX/DT RC6/TX/CK pin Write to bit SREN SREN bit RCIF bit (Interrupt) Read RXREG Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4 ‘0’ bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ‘0’ Q1 Q2 Q3 Q4 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. RC6/TX/CK pin pin (SCKP = 0) (SCKP = 1) PIC18F2420/2520/4420/4520 DS39631B-page 220 Preliminary © 2007 Microchip Technology Inc. 18.4 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 18.4.1 EUSART SYNCHRONOUS SLAVE TRANSMISSION The operation of the Synchronous Master and Slave modes are identical, except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in the TXREG register. c) Flag bit, TXIF, will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. e) If enable bit TXIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. 2. Clear bits CREN and SREN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting enable bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREGx register. 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 TXREG EUSART Transmit Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register, High Byte 51 SPBRG EUSART Baud Rate Generator Register, Low Byte 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: Reserved in 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 221 PIC18F2420/2520/4420/4520 18.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from the low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. 2. If interrupts are desired, set enable bit RCIE. 3. If 9-bit reception is desired, set bit RX9. 4. To enable reception, set enable bit CREN. 5. Flag bit, RCIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCIE, was set. 6. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51 RCREG EUSART Receive Register 51 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51 SPBRGH EUSART Baud Rate Generator Register, High Byte 51 SPBRG EUSART Baud Rate Generator Register, Low Byte 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. PIC18F2420/2520/4420/4520 DS39631B-page 222 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 223 PIC18F2420/2520/4420/4520 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) converter module has 10 inputs for the 28-pin devices and 13 for the 40/44-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) The ADCON0 register, shown in Register 19-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 19-2, configures the functions of the port pins. The ADCON2 register, shown in Register 19-3, configures the A/D clock source, programmed acquisition time and justification. REGISTER 19-1: ADCON0 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) Note 1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 224 Preliminary © 2007 Microchip Technology Inc. REGISTER 19-2: ADCON1 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits: Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown A = Analog input D = Digital I/O Note 1: The POR value of the PCFG bits depends on the value of the PBADEN configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. 2: AN5 through AN7 are available only on 40/44-pin devices. PCFG3: PCFG0 AN12 AN11 AN10 AN9 AN8 AN7(2) AN6(2) AN5(2) AN4 AN3 AN2 AN1 AN0 0000(1) A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 0111(1) D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D © 2007 Microchip Technology Inc. Preliminary DS39631B-page 225 PIC18F2420/2520/4420/4520 REGISTER 19-3: ADCON2 REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 226 Preliminary © 2007 Microchip Technology Inc. The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 19-1. FIGURE 19-1: A/D BLOCK DIAGRAM (Input Voltage) VAIN VREF+ Reference Voltage VDD VCFG1:VCFG0 CHS3:CHS0 AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0 0111 0110 0101 0100 0011 0010 0001 0000 10-Bit Converter VREFVSS A/D AN12 AN11 AN10 AN9 AN8 1100 1011 1010 1001 1000 Note 1: Channels AN5 through AN7 are not available on 28-pin devices. 2: I/O pins have diode protection to VDD and VSS. 0X 1X X1 X0 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 227 PIC18F2420/2520/4420/4520 The value in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 19.1 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. The following steps should be followed to perform an A/D conversion: 1. Configure the A/D module: • Configure analog pins, voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D acquisition time (ADCON2) • Select A/D conversion clock (ADCON2) • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit 3. Wait the required acquisition time (if required). 4. Start conversion: • Set GO/DONE bit (ADCON0 register) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. 7. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. FIGURE 19-2: A/D TRANSFER FUNCTION FIGURE 19-3: ANALOG INPUT MODEL Digital Code Output 3FEh 003h 002h 001h 000h 0.5 LSB 1 LSB 1.5 LSB 2 LSB 2.5 LSB 1022 LSB 1022.5 LSB 3 LSB Analog Input Voltage 3FFh 1023 LSB 1023.5 LSB VAIN CPIN Rs ANx 5 pF VT = 0.6V VT = 0.6V ILEAKAGE RIC ≤ 1k Sampling Switch SS RSS CHOLD = 25 pF VSS VDD ± 100 nA Legend: CPIN VT ILEAKAGE RIC SS CHOLD = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) various junctions RSS = sampling switch resistance VDD 6 V Sampling Switch 5 V 4 V 3 V 2 V 1 2 3 4 (kΩ) PIC18F2420/2520/4420/4520 DS39631B-page 228 Preliminary © 2007 Microchip Technology Inc. 19.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 19-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 kΩ. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. To calculate the minimum acquisition time, Equation 19-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 19-3 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: CHOLD = 25 pF Rs = 2.5 kΩ Conversion Error ≤ 1/2 LSb VDD = 5V → Rss = 2 kΩ Temperature = 85°C (system max.) EQUATION 19-1: ACQUISITION TIME EQUATION 19-2: A/D MINIMUM CHARGING TIME EQUATION 19-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME Note: When the conversion is started, the holding capacitor is disconnected from the input pin. TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) μs -(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs 1.05 μs TACQ = 0.2 μs + 1 μs + 1.2 μs 2.4 μs © 2007 Microchip Technology Inc. Preliminary DS39631B-page 229 PIC18F2420/2520/4420/4520 19.2 Selecting and Configuring Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. Acquisition time may be set with the ACQT2:ACQT0 bits (ADCON2<5:3>), which provides a range of 2 to 20 TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. Manual acquisition is selected when ACQT2:ACQT0 = 000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT2:ACQT0 bits and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 19.3 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: • 2 TOSC • 4 TOSC • 8 TOSC • 16 TOSC • 32 TOSC • 64 TOSC • Internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (see parameter 130 for more information). Table 19-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18F2X20/4X20 PIC18LF2X20/4X20(4) 2 TOSC 000 2.86 MHz 1.43 kHz 4 TOSC 100 5.71 MHz 2.86 MHz 8 TOSC 001 11.43 MHz 5.72 MHz 16 TOSC 101 22.86 MHz 11.43 MHz 32 TOSC 010 40.0 MHz 22.86 MHz 64 TOSC 110 40.0 MHz 22.86 MHz RC(3) x11 1.00 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 1.2 μs. 2: The RC source has a typical TAD time of 2.5 μs. 3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power (PIC18LFXXXX) devices only. PIC18F2420/2520/4420/4520 DS39631B-page 230 Preliminary © 2007 Microchip Technology Inc. 19.4 Operation in Power Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power managed mode. If the A/D is expected to operate while the device is in a power managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in the Sleep mode requires the A/D FRC clock to be selected. If bits ACQT2:ACQT0 are set to ‘000’ and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. 19.5 Configuring Analog Port Pins The ADCON1, TRISA, TRISB and TRISE registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the Port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert as analog inputs. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device’s specification limits. 3: The PBADEN bit in Configuration Register 3H configures PORTB pins to reset as analog or digital pins by controlling how the PCFG0 bits in ADCON1 are reset. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 231 PIC18F2420/2520/4420/4520 19.6 A/D Conversions Figure 19-4 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 19-5 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are set to ‘010’ and selecting a 4 TAD acquisition time before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. 19.7 Discharge The discharge phase is used to initialize the value of the capacitor array. The array is discharged before every sample. This feature helps to optimize the unitygain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. FIGURE 19-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) FIGURE 19-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11 Set GO bit Holding capacitor is disconnected from analog input (typically 100 ns) TCY - TAD TAD9 TAD10 ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Conversion starts b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 On the following cycle: TAD1 Discharge 1 2 3 4 5 6 7 8 11 Set GO bit (Holding capacitor is disconnected) 9 10 Conversion starts 1 2 3 4 (Holding capacitor continues acquiring input) TACQT Cycles TAD Cycles Automatic Acquisition Time b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. On the following cycle: TAD1 Discharge PIC18F2420/2520/4420/4520 DS39631B-page 232 Preliminary © 2007 Microchip Technology Inc. 19.8 Use of the CCP2 Trigger An A/D conversion can be started by the Special Event Trigger of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter. TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 ADRESH A/D Result Register, High Byte 51 ADRESL A/D Result Register, Low Byte 51 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 51 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 51 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52 TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 52 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52 TRISB PORTB Data Direction Control Register 52 LATB PORTB Data Latch Register (Read and Write to Data Latch) 52 PORTE(4) — — — — RE3(3) RE2 RE1 RE0 52 TRISE(4) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52 LATE(4) — — — — — PORTE Data Latch Register 52 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 3: RE3 port bit is available only as an input pin when the MCLRE configuration bit is ‘0’. 4: These registers are not implemented on 28-pin devices. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 233 PIC18F2420/2520/4420/4520 20.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip voltage reference (see Section 21.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register. The CMCON register (Register 20-1) selects the comparator input and output configuration. Block diagrams of the various comparator configurations are shown in Figure 20-1. REGISTER 20-1: CMCON REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VINbit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VINbit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RA3/AN3/VREF+ C2 VIN- connects to RA2/AN2/VREF-/CVREF 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 bit 2-0 CM2:CM0: Comparator Mode bits Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 234 Preliminary © 2007 Microchip Technology Inc. 20.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 20-1. Bits CM2:CM0 of the CMCON register are used to select these modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 26.0 “Electrical Characteristics”. FIGURE 20-1: COMPARATOR I/O OPERATING MODES Note: Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur. C1 RA0/AN0 VINRA3/ AN3/ VIN+ Off (Read as ‘0’) Comparators Reset A A CM2:CM0 = 000 C2 RA1/AN1 VINRA2/ AN2/ VIN+ Off (Read as ‘0’) A A C1 VINVIN+ C1OUT Two Independent Comparators A A CM2:CM0 = 010 C2 VINVIN+ C2OUT A A C1 VINVIN+ C1OUT Two Common Reference Comparators A A CM2:CM0 = 100 C2 VINVIN+ C2OUT A D C2 VINVIN+ Off (Read as ‘0’) One Independent Comparator with Output D D CM2:CM0 = 001 C1 VINVIN+ C1OUT A A C1 VINVIN+ Off (Read as ‘0’) Comparators Off (POR Default Value) D D CM2:CM0 = 111 C2 VINVIN+ Off (Read as ‘0’) D D C1 VINVIN+ C1OUT Four Inputs Multiplexed to Two Comparators A A CM2:CM0 = 110 C2 VINVIN+ C2OUT A A From VREF Module CIS = 0 CIS = 1 CIS = 0 CIS = 1 C1 VINVIN+ C1OUT Two Common Reference Comparators with Outputs A A CM2:CM0 = 101 C2 VINVIN+ C2OUT A D A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch CVREF C1 VINVIN+ C1OUT Two Independent Comparators with Outputs A A CM2:CM0 = 011 C2 VINVIN+ C2OUT A A RA5/AN4/SS/HLVDIN/C2OUT* RA4/T0CKI/C1OUT* VREF+ VREF-/CVREF RA0/AN0 RA3/AN3/ RA1/AN1 RA2/AN2/ VREF+ VREF-/CVREF RA0/AN0 RA3/AN3/ RA1/AN1 RA2/AN2/ VREF+ VREF-/CVREF RA0/AN0 RA3/AN3/ RA1/AN1 RA2/AN2/ VREF+ VREF-/CVREF RA0/AN0 RA3/AN3/ RA1/AN1 RA2/AN2/ VREF+ VREF-/CVREF RA0/AN0 RA3/AN3/ RA1/AN1 RA2/AN2/ VREF+ VREF-/CVREF RA0/AN0 RA3/AN3/ VREF+ RA1/AN1 RA2/AN2/ VREF-/CVREF RA4/T0CKI/C1OUT* RA5/AN4/SS/HLVDIN/C2OUT* RA0/AN0 RA3/AN3/ VREF+ RA1/AN1 RA2/AN2/ VREF-/CVREF RA4/T0CKI/C1OUT* * Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 235 PIC18F2420/2520/4420/4520 20.2 Comparator Operation A single comparator is shown in Figure 20-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 20-2 represent the uncertainty, due to input offsets and response time. 20.3 Comparator Reference Depending on the comparator operating mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly (Figure 20-2). FIGURE 20-2: SINGLE COMPARATOR 20.3.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s). 20.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. This module is described in more detail in Section 21.0 “Comparator Voltage Reference Module”. The internal reference is only available in the mode where four inputs are multiplexed to two comparators (CM2:CM0 = 110). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. 20.4 Comparator Response Time Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section 26.0 “Electrical Characteristics”). 20.5 Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RA4 and RA5 I/O pins. When enabled, multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 20-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RA4 and RA5 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). – VIN+ + VINOutput Output VINVIN+ Note 1: When reading the Port register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. PIC18F2420/2520/4420/4520 DS39631B-page 236 Preliminary © 2007 Microchip Technology Inc. FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM 20.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR2<6>) is the Comparator Interrupt Flag. The CMIF bit must be reset by clearing it. Since it is also possible to write a ‘1’ to this register, a simulated interrupt may be initiated. Both the CMIE bit (PIE2<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. 20.7 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators (CM2:CM0 = 111) before entering Sleep. If the device wakes up from Sleep, the contents of the CMCON register are not affected. 20.8 Effects of a Reset A device Reset forces the CMCON register to its Reset state, causing the comparator modules to be turned off (CM2:CM0 = 111). However, the input pins (RA0 through RA3) are configured as analog inputs by default on device Reset. The I/O configuration for these pins is determined by the setting of the PCFG3:PCFG0 bits (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset time. D Q EN To RA4 or RA5 pin Bus Data Set MULTIPLEX CMIF bit - + Port pins Read CMCON Reset From other Comparator CxINV D Q EN CL Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR registers) interrupt flag may not get set. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 237 PIC18F2420/2520/4420/4520 20.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 20-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. FIGURE 20-4: COMPARATOR ANALOG INPUT MODEL TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE VA RS < 10k AIN CPIN 5 pF VDD VT = 0.6V VT = 0.6V RIC ILEAKAGE ±500 nA VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage Comparator Input Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 52 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 52 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 52 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. PIC18F2420/2520/4420/4520 DS39631B-page 238 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 239 PIC18F2420/2520/4420/4520 21.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 21-1. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. 21.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 21-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. The equations used to calculate the output of the comparator voltage reference are as follows: If CVRR = 1: CVREF = ((CVR3:CVR0)/24) x CVRSRC If CVRR = 0: CVREF = (CVRSRC x 1/4) + (((CVR3:CVR0)/32) x CVRSRC) The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 26-3 in Section 26.0 “Electrical Characteristics”). REGISTER 21-1: CVRCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin Note 1: CVROE overrides the TRISA<2> bit setting. bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15) When CVRR = 1: CVREF = ((CVR3:CVR0)/24) • (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 240 Preliminary © 2007 Microchip Technology Inc. FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM 21.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 21-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 26.0 “Electrical Characteristics”. 21.3 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 21.4 Effects of a Reset A device Reset disables the voltage reference by clearing bit, CVREN (CVRCON<7>). This Reset also disconnects the reference from the RA2 pin by clearing bit, CVROE (CVRCON<6>) and selects the high-voltage range by clearing bit, CVRR (CVRCON<5>). The CVR value select bits are also cleared. 21.5 Connection Considerations The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the CVROE bit is set. Enabling the voltage reference output onto RA2 when it is configured as a digital input will increase current consumption. Connecting RA2 as a digital output with CVRSS enabled will also increase current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 21-2 shows an example buffering technique. 16-to-1 MUX CVR3:CVR0 8R CVREN R CVRSS = 0 VDD VREF+ CVRSS = 1 8R CVRSS = 0 VREFCVRSS = 1 R R R R R R 16 Steps CVRR CVREF © 2007 Microchip Technology Inc. Preliminary DS39631B-page 241 PIC18F2420/2520/4420/4520 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE CVREF Output + – CVREF Module Voltage Reference Output Impedance R(1) RA2 Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. PIC18FXXXX Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 52 Legend: Shaded cells are not used with the comparator voltage reference. Note 1: PORTA pins are enabled based on oscillator configuration. PIC18F2420/2520/4420/4520 DS39631B-page 242 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS39631B-page 243 PIC18F2420/2520/4420/4520 22.0 HIGH/LOW-VOLTAGE DETECT (HLVD) PIC18F2420/2520/4420/4520 devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. The High/Low-Voltage Detect Control register (Register 22-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. The block diagram for the HLVD module is shown in Figure 22-1. REGISTER 22-1: HLVDCON REGISTER (HIGH/LOW-VOLTAGE DETECT CONTROL) R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0) 0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0) bit 6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL3:HLVDL0: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: See Table 26-4 for specifications. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PIC18F2420/2520/4420/4520 DS39631B-page 244 © 2007 Microchip Technology Inc. The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. The VDIRMAG bit determines the overall operation of the module. When VDIRMAG is cleared, the module monitors for drops in VDD below a predetermined set point. When the bit is set, the module monitors for rises in VDD above the set point. 22.1 Operation When the HLVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The “trip point” voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The trip point voltage is software programmable to any one of 16 values. The trip point is selected by programming the HLVDL3:HLVDL0 bits (HLVDCON<3:0>). The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits HLVDL3:HLVDL0 are set to ‘1111’. In this state, the comparator input is multiplexed from the external input pin, HLVDIN. This gives users flexibility because it allows them to configure the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. FIGURE 22-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Set VDD 16 to 1 MUX HLVDEN HLVDCON HLVDIN HLVDL3:HLVDL0 Register HLVDIN VDD Externally Generated Trip Point HLVDIF HLVDEN BOREN Internal Voltage Reference VDIRMAG © 2007 Microchip Technology Inc. DS39631B-page 245 PIC18F2420/2520/4420/4520 22.2 HLVD Setup The following steps are needed to set up the HLVD module: 1. Write the value to the HLVDL3:HLVDL0 bits that selects the desired HLVD trip point. 2. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). 3. Enable the HLVD module by setting the HLVDEN bit. 4. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt. 5. Enable the HLVD interrupt if interrupts are desired by setting the HLVDIE and GIE bits (PIE2<2> and INTCON<7>). An interrupt will not be generated until the IRVST bit is set. 22.3 Current Consumption When the module is enabled, the HLVD comparator and voltage divider are enabled and will consume static current. The total current consumption, when enabled, is specified in electrical specification parameter D022B. Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled. 22.4 HLVD Start-up Time The internal reference voltage of the HLVD module, specified in electrical specification parameter D420, may be used by other internal circuitry, such as the Programmable Brown-out Reset. If the HLVD or other circuits using the voltage reference are disabled to lower the device’s current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification parameter 36. The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval. Refer to Figure 22-2 or Figure 22-3. FIGURE 22-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) VLVD VDD HLVDIF VLVD VDD Enable HLVD TIVRST HLVDIF may not be set Enable HLVD HLVDIF HLVDIF cleared in software HLVDIF cleared in software HLVDIF cleared in software, CASE 1: CASE 2: HLVDIF remains set since HLVD condition still exists TIVRST Internal Reference is stable Internal Reference is stable IRVST IRVST PIC18F2420/2520/4420/4520 DS39631B-page 246 © 2007 Microchip Technology Inc. FIGURE 22-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) 22.5 Applications In many applications, the ability to detect a drop below or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin). For general battery applications, Figure 22-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA. The interrupt could cause the execution of an ISR, which would allow the application to perform “housekeeping tasks” and perform a controlled shutdown before the device voltage exits the valid operating range at TB. The HLVD, thus, would give the application a time window, represented by the difference between TA and TB, to safely exit. FIGURE 22-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION VLVD VDD HLVDIF VLVD VDD Enable HLVD TIVRST HLVDIF may not be set Enable HLVD HLVDIF HLVDIF cleared in software HLVDIF cleared in software HLVDIF cleared in software, CASE 1: CASE 2: HLVDIF remains set since HLVD condition still exists TIVRST IRVST Internal Reference is stable Internal Reference is stable IRVST Time Voltage VA VB TA TB VA = HLVD trip point VB = Minimum valid device operating voltage Legend: © 2007 Microchip Technology Inc. DS39631B-page 247 PIC18F2420/2520/4420/4520 22.6 Operation During Sleep When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 22.7 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. TABLE 22-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 50 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OCSFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. PIC18F2420/2520/4420/4520 DS39631B-page 248 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 249 PIC18F2420/2520/4420/4520 23.0 SPECIAL FEATURES OF THE CPU PIC18F2420/2520/4420/4520 devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: • Oscillator Selection • Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Fail-Safe Clock Monitor • Two-Speed Start-up • Code Protection • ID Locations • In-Circuit Serial Programming The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 2.0 “Oscillator Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2420/2520/4420/ 4520 devices have a Watchdog Timer, which is either permanently enabled via the configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two- Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate configuration register bits. 23.1 Configuration Bits The configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. Programming the configuration registers is done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a self-timed write to the configuration register. In normal operation mode, a TBLWT instruction with the TBLPTR pointing to the configuration register sets up the address and the data for the configuration register write. Setting the WR bit starts a long write to the configuration register. The configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a ‘1’ or a ‘0’ into the cell. For additional details on Flash programming, refer to Section 6.5 “Writing to Flash Program Memory”. TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011 300006h CONFIG4L DEBUG XINST — — — LVP — STVREN 10-- -1-1 300008h CONFIG5L — — — — CP3(1) CP2(1) CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — WRT3(1) WRT2(1) WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(1) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2) 3FFFFFh DEVID2(1) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F2420/4420 devices; maintain this bit set. 2: See Register 23-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. PIC18F2420/2520/4420/4520 DS39631B-page 250 Preliminary © 2007 Microchip Technology Inc. REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC3:FOSC0: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2007 Microchip Technology Inc. Preliminary DS39631B-page 251 PIC18F2420/2520/4420/4520 REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2) bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1) 11 = Maximum setting . . . 00 = Minimum setting bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section 26.1 “DC Characteristics: Supply Voltage” for specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state PIC18F2420/2520/4420/4520 DS39631B-page 252 Preliminary © 2007 Microchip Technology Inc. REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2007 Microchip Technology Inc. Preliminary DS39631B-page 253 PIC18F2420/2520/4420/4520 REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) REGISTER 23-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1 MCLRE — — — — LPT1OSC PBADEN CCP2MX bit 7 bit 0 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Read as ‘0’ bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 CCP2MX: CCP2 Mux bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5-3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state PIC18F2420/2520/4420/4520 DS39631B-page 254 Preliminary © 2007 Microchip Technology Inc. REGISTER 23-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) REGISTER 23-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1,2) CP2(1) CP1 CP0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1,2) 1 = Block 3 (006000-007FFFh) not code-protected 0 = Block 3 (006000-007FFFh) code-protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code-protected 0 = Block 2 (004000-005FFFh) code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) not code-protected 0 = Block 1 (002000-003FFFh) code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000800-001FFFh) not code-protected 0 = Block 0 (000800-001FFFh) code-protected Note 1: Unimplemented in PIC18F2420/4420 devices; maintain this bit set. 2: Unimplemented in PIC18F2425/4425 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) not code-protected 0 = Boot block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2007 Microchip Technology Inc. Preliminary DS39631B-page 255 PIC18F2420/2520/4420/4520 REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) REGISTER 23-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1,2) WRT2(1) WRT1 WRT0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1,2) 1 = Block 3 (006000-007FFFh) not write-protected 0 = Block 3 (006000-007FFFh) write-protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 (004000-005FFFh) not write-protected 0 = Block 2 (004000-005FFFh) write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) not write-protected 0 = Block 1 (002000-003FFFh) write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 (000800-001FFFh) not write-protected 0 = Block 0 (000800-001FFFh) write-protected Note 1: Unimplemented in PIC18F2420/4420 devices; maintain this bit set. 2: Unimplemented in PIC18F2425/4425 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0007FFh) not write-protected 0 = Boot block (000000-0007FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode. bit 4-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state PIC18F2420/2520/4420/4520 DS39631B-page 256 Preliminary © 2007 Microchip Technology Inc. REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) REGISTER 23-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1,2) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1,2) 1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks 0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks 0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks 0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000800-001FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800-001FFFh) protected from table reads executed in other blocks Note 1: Unimplemented in PIC18F2420/4420 devices; maintain this bit set. 2: Unimplemented in PIC18F2425/4425 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot block (000000-0007FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2007 Microchip Technology Inc. Preliminary DS39631B-page 257 PIC18F2420/2520/4420/4520 REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2420/2520/4420/4520 REGISTER 23-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2420/2520/4420/4520 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F4520 010 = PIC18F4420 100 = PIC18F2520 110 = PIC18F2420 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0000 1100 = PIC18F2420/2520/4420/4520 devices Note: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state PIC18F2420/2520/4420/4520 DS39631B-page 258 Preliminary © 2007 Microchip Technology Inc. 23.2 Watchdog Timer (WDT) For PIC18F2420/2520/4420/4520 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. 23.2.1 CONTROL REGISTER Register 23-14 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable configuration bit, but only if the configuration bit has disabled the WDT. FIGURE 23-1: WDT BLOCK DIAGRAM Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. INTRC Source WDT Wake-up Reset WDT Counter Programmable Postscaler 1:1 to 1:32,768 Enable WDT WDTPS<3:0> SWDTEN WDTEN CLRWDT 4 from Power Reset All Device Resets Sleep ÷128 Change on IRCF bits Managed Modes © 2007 Microchip Technology Inc. Preliminary DS39631B-page 259 PIC18F2420/2520/4420/4520 REGISTER 23-14: WDTCON REGISTER TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the configuration bit, WDTEN, is enabled. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RCON IPEN SBOREN — RI TO PD POR BOR 48 WDTCON — — — — — — — SWDTEN 50 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. PIC18F2420/2520/4420/4520 DS39631B-page 260 Preliminary © 2007 Microchip Technology Inc. 23.3 Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTOSC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO configuration bit. Two-Speed Start-up should be enabled only if the primary oscillator mode is LP, XT, HS or HSPLL (crystal-based modes). Other sources do not require an OST start-up delay; for these, Two-Speed Start-up should be disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IRCF2:IRCF0 immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. In all other power managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. 23.3.1 SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP While using the INTOSC oscillator in Two-Speed Startup, the device still obeys the normal command sequences for entering power managed modes, including multiple SLEEP instructions (refer to Section 3.1.4 “Multiple Sleep Commands”). In practice, this means that user code can change the SCS1:SCS0 bit settings or issue SLEEP instructions before the OST times out. This would allow an application to briefly wake-up, perform routine “housekeeping” tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. FIGURE 23-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q3 Q4 OSC1 Peripheral Program PC PC + 2 INTOSC PLL Clock Q1 PC + 6 Q2 Output Q3 Q4 Q1 CPU Clock PC + 4 Clock Counter Q2 Q2 Q3 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. Wake from Interrupt Event TPLL(1) 1 2 n-1 n Clock OSTS bit Set Transition(2) Multiplexer TOST(1) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 261 PIC18F2420/2520/4420/4520 23.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 23-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the device clock source, but cleared on the rising edge of the sample clock. FIGURE 23-3: FSCM BLOCK DIAGRAM Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 23-4). This causes the following: • the FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); • the device clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source – this is the fail-safe condition) and • the WDT is reset. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section 3.1.4 “Multiple Sleep Commands” and Section 23.3.1 “Special Considerations for Using Two-Speed Start-up” for more details. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF2:IRCF0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 23.4.1 FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. 23.4.2 EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset or by entering a power managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the device clock until the primary clock source becomes ready (similar to a Two-Speed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power managed mode is entered. Peripheral INTRC ÷ 64 S C Q (32 μs) 488 Hz (2.048 ms) Clock Monitor Latch (CM) (edge-triggered) Clock Failure Detected Source Clock Q PIC18F2420/2520/4420/4520 DS39631B-page 262 Preliminary © 2007 Microchip Technology Inc. FIGURE 23-4: FSCM TIMING DIAGRAM 23.4.3 FSCM INTERRUPTS IN POWER MANAGED MODES By entering a power managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe Monitoring of the power managed clock source resumes in the power managed mode. If an oscillator failure occurs during power managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTOSC source. 23.4.4 POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary device clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. As noted in Section 23.3.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power managed mode while waiting for the primary clock to become stable. When the new power managed mode is selected, the primary clock is disabled. OSCFIF CM Output Device Clock Output Sample Clock Failure Detected Oscillator Failure Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. (Q) CM Test CM Test CM Test Note: The same logic that prevents false oscillator failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator’s failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 263 PIC18F2420/2520/4420/4520 23.5 Program Verification and Code Protection The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® devices. The user program memory is divided into five blocks. One of these is a boot block of 2 Kbytes. The remainder of the memory is divided into four blocks on binary boundaries. Each of the five blocks has three code protection bits associated with them. They are: • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) Figure 23-5 shows the program memory organization for 16 and 32-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 23-3. FIGURE 23-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2420/2520/4420/4520 TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3(1,2) CP2(1) CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3(1,2) WRT2(1) WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3(1,2) EBTR2(1) EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18F2420/4420 devices; maintain this bit set. 2: Unimplemented in PIC18F2425/4425 devices; maintain this bit set. MEMORY SIZE/DEVICE Block Code Protection 16 Kbytes Controlled By: (PIC18F2420/4420) 32 Kbytes (PIC18F2520/4520) Address Range Boot Block Boot Block 000000h 0007FFh CPB, WRTB, EBTRB Block 0 Block 0 000800h 001FFFh CP0, WRT0, EBTR0 Block 1 Block 1 002000h 003FFFh CP1, WRT1, EBTR1 Unimplemented Read ‘0’s Block 2 004000h 005FFFh CP2, WRT2, EBTR2 Block 3 006000h 007FFFh CP3, WRT3, EBTR3 Unimplemented Read ‘0’s 1FFFFFh (Unimplemented Memory Space) PIC18F2420/2520/4420/4520 DS39631B-page 264 Preliminary © 2007 Microchip Technology Inc. 23.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is ‘0’. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s. Figures 23-6 through 23-8 illustrate table write and table read protection. FIGURE 23-6: TABLE WRITE (WRTn) DISALLOWED Note: Code protection bits may only be written to a ‘0’ from a ‘1’ state. It is not possible to write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer. 000000h 0007FFh 000800h 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh WRTB, EBTRB = 11 WRT0, EBTR0 = 01 WRT1, EBTR1 = 11 WRT2, EBTR2 = 11 WRT3, EBTR3 = 11 TBLWT* TBLPTR = 0008FFh PC = 001FFEh PC = 005FFEh TBLWT* Register Values Program Memory Configuration Bit Settings Results: All table writes disabled to Blockn whenever WRTn = 0. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 265 PIC18F2420/2520/4420/4520 FIGURE 23-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED FIGURE 23-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED WRTB, EBTRB = 11 WRT0, EBTR0 = 10 WRT1, EBTR1 = 11 WRT2, EBTR2 = 11 WRT3, EBTR3 = 11 TBLRD* TBLPTR = 0008FFh PC = 003FFEh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 WRT1, EBTR1 = 11 WRT2, EBTR2 = 11 WRT3, EBTR3 = 11 TBLRD* TBLPTR = 0008FFh PC = 001FFEh Register Values Program Memory Configuration Bit Settings Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. 000000h 0007FFh 000800h 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh PIC18F2420/2520/4420/4520 DS39631B-page 266 Preliminary © 2007 Microchip Technology Inc. 23.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 23.5.3 CONFIGURATION REGISTER PROTECTION The configuration registers can be write-protected. The WRTC bit controls protection of the configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 23.6 ID Locations Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions or during program/verify. The ID locations can be read when the device is code-protected. 23.7 In-Circuit Serial Programming PIC18F2420/2520/4420/4520 devices can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 23.8 In-Circuit Debugger When the DEBUG configuration bit is programmed to a ‘0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB® IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 23-4 shows which resources are required by the background debugger. TABLE 23-4: DEBUGGER RESOURCES To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP/RE3, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies. 23.9 Single-Supply ICSP Programming The LVP configuration bit enables Single-Supply ICSP Programming (formerly known as Low-Voltage ICSP Programming or LVP). When Single-Supply Programming is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. While programming, using Single-Supply Programming mode, VDD is applied to the MCLR/VPP/RE3 pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. If Single-Supply ICSP Programming mode will not be used, the LVP bit can be cleared. RB5/KBI1/PGM then becomes available as the digital I/O pin, RB5. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the MCLR/ VPP/RE3 pin). Once LVP has been disabled, only the standard high-voltage programming is available and must be used to program the device. Memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required. If a block erase is to be performed when using Low-Voltage Programming, the device must be supplied with VDD of 4.5V to 5.5V. I/O pins: RB6, RB7 Stack: 2 levels Program Memory: 512 bytes Data Memory: 10 bytes Note 1: High-voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: By default, Single-Supply ICSP is enabled in unprogrammed devices (as supplied from Microchip) and erased devices. 3: When Single-Supply Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. 4: When LVP is enabled, externally pull the PGM pin to VSS to allow normal program execution. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 267 PIC18F2420/2520/4420/4520 24.0 INSTRUCTION SET SUMMARY PIC18F2420/2520/4420/4520 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 24.1 Standard Instruction Set The standard PIC18 instruction set adds many enhancements to the previous PIC® instruction sets, while maintaining an easy migration from these PIC instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • Byte-oriented operations • Bit-oriented operations • Literal operations • Control operations The PIC18 instruction set summary in Table 24-2 lists byte-oriented, bit-oriented, literal and control operations. Table 24-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. The file register (specified by ‘f’) 2. The destination of the result (specified by ‘d’) 3. The accessed memory (specified by ‘a’) The file register designator ‘f’ specifies which file register is to be used by the instruction. The destination designator ‘d’ specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. The file register (specified by ‘f’) 2. The bit in the file register (specified by ‘b’) 3. The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: • A literal value to be loaded into a file register (specified by ‘k’) • The desired FSR register to load the literal value into (specified by ‘f’) • No operand required (specified by ‘—’) The control instructions may use some of the following operands: • A program memory address (specified by ‘n’) • The mode of the CALL or RETURN instructions (specified by ‘s’) • The mode of the table read and table write instructions (specified by ‘m’) • No operand required (specified by ‘—’) All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are ‘1’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 μs. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 μs. Two-word branch instructions (if true) would take 3 μs. Figure 24-1 shows the general formats that the instructions can have. All examples use the convention ‘nnh’ to represent a hexadecimal number. The Instruction Set Summary, shown in Table 24-2, lists the standard instructions recognized by the Microchip Assembler (MPASMTM). Section 24.1.1 “Standard Instruction Set” provides a description of each instruction. PIC18F2420/2520/4420/4520 DS39631B-page 268 Preliminary © 2007 Microchip Technology Inc. TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). fs 12-bit Register file address (000h to FFFh). This is the source address. fd 12-bit Register file address (000h to FFFh). This is the destination address. GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. zs 7-bit offset value for indirect addressing of register files (source). zd 7-bit offset value for indirect addressing of register files (destination). { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr] Specifies bit n of the register indicated by the pointer expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User defined term (font is Courier). © 2007 Microchip Technology Inc. Preliminary DS39631B-page 269 PIC18F2420/2520/4420/4520 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be WREG register OPCODE d a f (FILE #) d = 1 for result destination to be file register (f) a = 0 to force Access Bank Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) b = 3-bit position of bit in file register (f) Literal operations 15 8 7 0 OPCODE k (literal) k = 8-bit immediate value Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) n = 20-bit immediate value a = 1 for BSR to select bank f = 8-bit file register address a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Control operations Example Instruction ADDWF MYREG, W, B MOVFF MYREG1, MYREG2 BSF MYREG, bit, B MOVLW 7Fh GOTO Label 15 8 7 0 OPCODE n<7:0> (literal) 15 12 11 0 1111 n<19:8> (literal) CALL MYFUNC 15 11 10 0 OPCODE n<10:0> (literal) S = Fast bit BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC S PIC18F2420/2520/4420/4520 DS39631B-page 270 Preliminary © 2007 Microchip Technology Inc. TABLE 24-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word Status Affected Notes MSb LSb BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and CARRY bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da0 0da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N C, DC, Z, OV, N C, DC, Z, OV, N None None Z, N 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 271 PIC18F2420/2520/4420/4520 BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1, 2 1, 2 3, 4 3, 4 1, 2 CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP n n n n n n n n n n, s — — n — — — — n s k s — Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable Return with literal in WREG Return from Subroutine Go into Standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 None None None None None None None None None None TO, PD C None None None None None None All GIE/GIEH, PEIE/GIEL None None TO, PD 4 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word Status Affected Notes MSb LSb Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. PIC18F2420/2520/4420/4520 DS39631B-page 272 Preliminary © 2007 Microchip Technology Inc. LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k f, k k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*- TBLRD+* TBLWT* TBLWT*+ TBLWT*- TBLWT+* Table Read Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write Table Write with post-increment Table Write with post-decrement Table Write with pre-increment 2 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word Status Affected Notes MSb LSb Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 273 PIC18F2420/2520/4420/4520 24.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W Syntax: ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: ADDLW 15h Before Instruction W = 10h After Instruction W = 25h ADDWF ADD W to f Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z Encoding: 0010 01da ffff ffff Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). PIC18F2420/2520/4420/4520 DS39631B-page 274 Preliminary © 2007 Microchip Technology Inc. ADDWFC ADD W and CARRY bit to f Syntax: ADDWFC f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) + (C) → dest Status Affected: N,OV, C, DC, Z Encoding: 0010 00da ffff ffff Description: Add W, the CARRY flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ADDWFC REG, 0, 1 Before Instruction CARRY bit = 1 REG = 02h W = 4Dh After Instruction CARRY bit = 0 REG = 02h W = 50h ANDLW AND literal with W Syntax: ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. k → W Status Affected: N, Z Encoding: 0000 1011 kkkk kkkk Description: The contents of W are AND’ed with the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: ANDLW 05Fh Before Instruction W = A3h After Instruction W = 03h © 2007 Microchip Technology Inc. Preliminary DS39631B-page 275 PIC18F2420/2520/4420/4520 ANDWF AND W with f Syntax: ANDWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 01da ffff ffff Description: The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ANDWF REG, 0, 0 Before Instruction W = 17h REG = C2h After Instruction W = 02h REG = C2h BC Branch if Carry Syntax: BC n Operands: -128 ≤ n ≤ 127 Operation: if CARRY bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0010 nnnn nnnn Description: If the CARRY bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BC 5 Before Instruction PC = address (HERE) After Instruction If CARRY = 1; PC = address (HERE + 12) If CARRY = 0; PC = address (HERE + 2) PIC18F2420/2520/4420/4520 DS39631B-page 276 Preliminary © 2007 Microchip Technology Inc. BCF Bit Clear f Syntax: BCF f, b {,a} Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0,1] Operation: 0 → f Status Affected: None Encoding: 1001 bbba ffff ffff Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BCF FLAG_REG, 7, 0 Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h BN Branch if Negative Syntax: BN n Operands: -128 ≤ n ≤ 127 Operation: if NEGATIVE bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0110 nnnn nnnn Description: If the NEGATIVE bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 1; PC = address (Jump) If NEGATIVE = 0; PC = address (HERE + 2) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 277 PIC18F2420/2520/4420/4520 BNC Branch if Not Carry Syntax: BNC n Operands: -128 ≤ n ≤ 127 Operation: if CARRY bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0011 nnnn nnnn Description: If the CARRY bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BNC Jump Before Instruction PC = address (HERE) After Instruction If CARRY = 0; PC = address (Jump) If CARRY = 1; PC = address (HERE + 2) BNN Branch if Not Negative Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operation: if NEGATIVE bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0111 nnnn nnnn Description: If the NEGATIVE bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BNN Jump Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 0; PC = address (Jump) If NEGATIVE = 1; PC = address (HERE + 2) PIC18F2420/2520/4420/4520 DS39631B-page 278 Preliminary © 2007 Microchip Technology Inc. BNOV Branch if Not Overflow Syntax: BNOV n Operands: -128 ≤ n ≤ 127 Operation: if OVERFLOW bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0101 nnnn nnnn Description: If the OVERFLOW bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BNOV Jump Before Instruction PC = address (HERE) After Instruction If OVERFLOW= 0; PC = address (Jump) If OVERFLOW= 1; PC = address (HERE + 2) BNZ Branch if Not Zero Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operation: if ZERO bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0001 nnnn nnnn Description: If the ZERO bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BNZ Jump Before Instruction PC = address (HERE) After Instruction If ZERO = 0; PC = address (Jump) If ZERO = 1; PC = address (HERE + 2) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 279 PIC18F2420/2520/4420/4520 BRA Unconditional Branch Syntax: BRA n Operands: -1024 ≤ n ≤ 1023 Operation: (PC) + 2 + 2n → PC Status Affected: None Encoding: 1101 0nnn nnnn nnnn Description: Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Example: HERE BRA Jump Before Instruction PC = address (HERE) After Instruction PC = address (Jump) BSF Bit Set f Syntax: BSF f, b {,a} Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: 1000 bbba ffff ffff Description: Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah PIC18F2420/2520/4420/4520 DS39631B-page 280 Preliminary © 2007 Microchip Technology Inc. BTFSC Bit Test File, Skip if Clear Syntax: BTFSC f, b {,a} Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0,1] Operation: skip if (f) = 0 Status Affected: None Encoding: 1011 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE BTFSC : : FLAG, 1, 0 Before Instruction PC = address (HERE) After Instruction If FLAG<1> = 0; PC = address (TRUE) If FLAG<1> = 1; PC = address (FALSE) BTFSS Bit Test File, Skip if Set Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 0 ≤ b < 7 a ∈ [0,1] Operation: skip if (f) = 1 Status Affected: None Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE BTFSS : : FLAG, 1, 0 Before Instruction PC = address (HERE) After Instruction If FLAG<1> = 0; PC = address (FALSE) If FLAG<1> = 1; PC = address (TRUE) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 281 PIC18F2420/2520/4420/4520 BTG Bit Toggle f Syntax: BTG f, b {,a} Operands: 0 ≤ f ≤ 255 0 ≤ b < 7 a ∈ [0,1] Operation: (f) → f Status Affected: None Encoding: 0111 bbba ffff ffff Description: Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BTG PORTC, 4, 0 Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h] BOV Branch if Overflow Syntax: BOV n Operands: -128 ≤ n ≤ 127 Operation: if OVERFLOW bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0100 nnnn nnnn Description: If the OVERFLOW bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BOV Jump Before Instruction PC = address (HERE) After Instruction If OVERFLOW= 1; PC = address (Jump) If OVERFLOW= 0; PC = address (HERE + 2) PIC18F2420/2520/4420/4520 DS39631B-page 282 Preliminary © 2007 Microchip Technology Inc. BZ Branch if Zero Syntax: BZ n Operands: -128 ≤ n ≤ 127 Operation: if ZERO bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0000 nnnn nnnn Description: If the ZERO bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BZ Jump Before Instruction PC = address (HERE) After Instruction If ZERO = 1; PC = address (Jump) If ZERO = 0; PC = address (HERE + 2) CALL Subroutine Call Syntax: CALL k {,s} Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: (PC) + 4 → TOS, k → PC<20:1>, if s = 1 (W) → WS, (Status) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8 Description: Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If ‘s’ = 1, the W, Status and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no update occurs (default). Then, the 20-bit value ‘k’ is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’<7:0>, PUSH PC to stack Read literal ‘k’<19:8>, Write to PC No operation No operation No operation No operation Example: HERE CALL THERE, 1 Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= Status © 2007 Microchip Technology Inc. Preliminary DS39631B-page 283 PIC18F2420/2520/4420/4520 CLRF Clear f Syntax: CLRF f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: 000h → f 1 → Z Status Affected: Z Encoding: 0110 101a ffff ffff Description: Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: CLRF FLAG_REG, 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h CLRWDT Clear Watchdog Timer Syntax: CLRWDT Operands: None Operation: 000h → WDT, 000h → WDT postscaler, 1 → TO, 1 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Description: CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data No operation Example: CLRWDT Before Instruction WDT Counter = ? After Instruction WDT Counter = 00h WDT Postscaler = 0 TO = 1 PD = 1 PIC18F2420/2520/4420/4520 DS39631B-page 284 Preliminary © 2007 Microchip Technology Inc. COMF Complement f Syntax: COMF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: COMF REG, 0, 0 Before Instruction REG = 13h After Instruction REG = 13h W = ECh CPFSEQ Compare f with W, skip if f = W Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 001a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If ‘f’ = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) © 2007 Microchip Technology Inc. Preliminary DS39631B-page 285 PIC18F2420/2520/4420/4520 CPFSGT Compare f with W, skip if f > W Syntax: CPFSGT f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) > (W) (unsigned comparison) Status Affected: None Encoding: 0110 010a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of the W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSGT REG, 0 NGREATER : GREATER : Before Instruction PC = Address (HERE) W = ? After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) CPFSLT Compare f with W, skip if f < W Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSLT REG, 1 NLESS : LESS : Before Instruction PC = Address (HERE) W = ? After Instruction If REG < W; PC = Address (LESS) If REG ≥ W; PC = Address (NLESS) PIC18F2420/2520/4420/4520 DS39631B-page 286 Preliminary © 2007 Microchip Technology Inc. DAW Decimal Adjust W Register Syntax: DAW Operands: None Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 → W<3:0>; else (W<3:0>) → W<3:0>; If [W<7:4> + DC > 9] or [C = 1] then (W<7:4>) + 6 + DC → W<7:4> ; else (W<7:4>) + DC → W<7:4> Status Affected: C Encoding: 0000 0000 0000 0111 Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Example1: DAW Before Instruction W = A5h C = 0 DC = 0 After Instruction W = 05h C = 1 DC = 0 Example 2: Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DECF Decrement f Syntax: DECF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 0000 01da ffff ffff Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: DECF CNT, 1, 0 Before Instruction CNT = 01h Z = 0 After Instruction CNT = 00h Z = 1 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 287 PIC18F2420/2520/4420/4520 DECFSZ Decrement f, skip if 0 Syntax: DECFSZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Status Affected: None Encoding: 0010 11da ffff ffff Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP CONTINUE Before Instruction PC = Address (HERE) After Instruction CNT = CNT - 1 If CNT = 0; PC = Address (CONTINUE) If CNT ≠ 0; PC = Address (HERE + 2) DCFSNZ Decrement f, skip if not 0 Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DCFSNZ TEMP, 1, 0 ZERO : NZERO : Before Instruction TEMP = ? After Instruction TEMP = TEMP – 1, If TEMP = 0; PC = Address (ZERO) If TEMP ≠ 0; PC = Address (NZERO) PIC18F2420/2520/4420/4520 DS39631B-page 288 Preliminary © 2007 Microchip Technology Inc. GOTO Unconditional Branch Syntax: GOTO k Operands: 0 ≤ k ≤ 1048575 Operation: k → PC<20:1> Status Affected: None Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’<7:0>, No operation Read literal ‘k’<19:8>, Write to PC No operation No operation No operation No operation Example: GOTO THERE After Instruction PC = Address (THERE) INCF Increment f Syntax: INCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 0010 10da ffff ffff Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 289 PIC18F2420/2520/4420/4520 INCFSZ Increment f, skip if 0 Syntax: INCFSZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result = 0 Status Affected: None Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE INCFSZ CNT, 1, 0 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction CNT = CNT + 1 If CNT = 0; PC = Address (ZERO) If CNT ≠ 0; PC = Address (NZERO) INFSNZ Increment f, skip if not 0 Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Encoding: 0100 10da ffff ffff Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE INFSNZ REG, 1, 0 ZERO NZERO Before Instruction PC = Address (HERE) After Instruction REG = REG + 1 If REG ≠ 0; PC = Address (NZERO) If REG = 0; PC = Address (ZERO) PIC18F2420/2520/4420/4520 DS39631B-page 290 Preliminary © 2007 Microchip Technology Inc. IORLW Inclusive OR literal with W Syntax: IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → W Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: IORLW 35h Before Instruction W = 9Ah After Instruction W = BFh IORWF Inclusive OR W with f Syntax: IORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z Encoding: 0001 00da ffff ffff Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h © 2007 Microchip Technology Inc. Preliminary DS39631B-page 291 PIC18F2420/2520/4420/4520 LFSR Load FSR Syntax: LFSR f, k Operands: 0 ≤ f ≤ 2 0 ≤ k ≤ 4095 Operation: k → FSRf Status Affected: None Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ MSB Process Data Write literal ‘k’ MSB to FSRfH Decode Read literal ‘k’ LSB Process Data Write literal ‘k’ to FSRfL Example: LFSR 2, 3ABh After Instruction FSR2H = 03h FSR2L = ABh MOVF Move f Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: f → dest Status Affected: N, Z Encoding: 0101 00da ffff ffff Description: The contents of register ‘f’ are moved to a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h PIC18F2420/2520/4420/4520 DS39631B-page 292 Preliminary © 2007 Microchip Technology Inc. MOVFF Move f to f Syntax: MOVFF fs,fd Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operation: (fs) → fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff ffffs ffffd Description: The contents of source register ‘fs’ are moved to destination register ‘fd’. Location of source ‘fs’ can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination ‘fd’ can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ (src) Process Data No operation Decode No operation No dummy read No operation Write register ‘f’ (dest) Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h MOVLB Move literal to low nibble in BSR Syntax: MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → BSR Status Affected: None Encoding: 0000 0001 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains ‘0’, regardless of the value of k7:k4. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write literal ‘k’ to BSR Example: MOVLB 5 Before Instruction BSR Register = 02h After Instruction BSR Register = 05h © 2007 Microchip Technology Inc. Preliminary DS39631B-page 293 PIC18F2420/2520/4420/4520 MOVLW Move literal to W Syntax: MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → W Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: MOVLW 5Ah After Instruction W = 5Ah MOVWF Move W to f Syntax: MOVWF f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) → f Status Affected: None Encoding: 0110 111a ffff ffff Description: Move data from W to register ‘f’. Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh PIC18F2420/2520/4420/4520 DS39631B-page 294 Preliminary © 2007 Microchip Technology Inc. MULLW Multiply literal with W Syntax: MULLW k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: 0000 1101 kkkk kkkk Description: An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write registers PRODH: PRODL Example: MULLW 0C4h Before Instruction W = E2h PRODH = ? PRODL = ? After Instruction W = E2h PRODH = ADh PRODL = 08h MULWF Multiply W with f Syntax: MULWF f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the register file location ‘f’. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and ‘f’ are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h © 2007 Microchip Technology Inc. Preliminary DS39631B-page 295 PIC18F2420/2520/4420/4520 NEGF Negate f Syntax: NEGF f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: ( f ) + 1 → f Status Affected: N, OV, C, DC, Z Encoding: 0110 110a ffff ffff Description: Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] NOP No Operation Syntax: NOP Operands: None Operation: No operation Status Affected: None Encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx Description: No operation. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None. PIC18F2420/2520/4420/4520 DS39631B-page 296 Preliminary © 2007 Microchip Technology Inc. POP Pop Top of Return Stack Syntax: POP Operands: None Operation: (TOS) → bit bucket Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation POP TOS value No operation Example: POP GOTO NEW Before Instruction TOS = 0031A2h Stack (1 level down) = 014332h After Instruction TOS = 014332h PC = NEW PUSH Push Top of Return Stack Syntax: PUSH Operands: None Operation: (PC + 2) → TOS Status Affected: None Encoding: 0000 0000 0000 0101 Description: The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode PUSH PC + 2 onto return stack No operation No operation Example: PUSH Before Instruction TOS = 345Ah PC = 0124h After Instruction PC = 0126h TOS = 0126h Stack (1 level down) = 345Ah © 2007 Microchip Technology Inc. Preliminary DS39631B-page 297 PIC18F2420/2520/4420/4520 RCALL Relative Call Syntax: RCALL n Operands: -1024 ≤ n ≤ 1023 Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Status Affected: None Encoding: 1101 1nnn nnnn nnnn Description: Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ PUSH PC to stack Process Data Write to PC No operation No operation No operation No operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) RESET Reset Syntax: RESET Operands: None Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: All Encoding: 0000 0000 1111 1111 Description: This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example: RESET After Instruction Registers = Reset Value Flags* = Reset Value PIC18F2420/2520/4420/4520 DS39631B-page 298 Preliminary © 2007 Microchip Technology Inc. RETFIE Return from Interrupt Syntax: RETFIE {s} Operands: s ∈ [0,1] Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL, if s = 1 (WS) → W, (STATUSS) → Status, (BSRS) → BSR, PCLATU, PCLATH are unchanged. Status Affected: GIE/GIEH, PEIE/GIEL. Encoding: 0000 0000 0001 000s Description: Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If ‘s’ = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation POP PC from stack Set GIEH or GIEL No operation No operation No operation No operation Example: RETFIE 1 After Interrupt PC = TOS W = WS BSR = BSRS Status = STATUSS GIE/GIEH, PEIE/GIEL = 1 RETLW Return literal to W Syntax: RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 1100 kkkk kkkk Description: W is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data POP PC from stack, Write to W No operation No operation No operation No operation Example: CALL TABLE ; W contains table ; offset value ; W now has ; table value : TABLE ADDWF PCL ; W = offset RETLW k0 ; Begin table RETLW k1 ; : : RETLW kn ; End of table Before Instruction W = 07h After Instruction W = value of kn © 2007 Microchip Technology Inc. Preliminary DS39631B-page 299 PIC18F2420/2520/4420/4520 RETURN Return from Subroutine Syntax: RETURN {s} Operands: s ∈ [0,1] Operation: (TOS) → PC, if s = 1 (WS) → W, (STATUSS) → Status, (BSRS) → BSR, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If ‘s’= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data POP PC from stack No operation No operation No operation No operation Example: RETURN After Instruction: PC = TOS RLCF Rotate Left f through Carry Syntax: RLCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Encoding: 0011 01da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left through the CARRY flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 C register f PIC18F2420/2520/4420/4520 DS39631B-page 300 Preliminary © 2007 Microchip Technology Inc. RLNCF Rotate Left f (No Carry) Syntax: RLNCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Status Affected: N, Z Encoding: 0100 01da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 After Instruction REG = 0101 0111 register f RRCF Rotate Right f through Carry Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the right through the CARRY flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RRCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 C register f © 2007 Microchip Technology Inc. Preliminary DS39631B-page 301 PIC18F2420/2520/4420/4520 RRNCF Rotate Right f (No Carry) Syntax: RRNCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<0>) → dest<7> Status Affected: N, Z Encoding: 0100 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 register f SETF Set f Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: FFh → f Status Affected: None Encoding: 0110 100a ffff ffff Description: The contents of the specified register are set to FFh. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: SETF REG, 1 Before Instruction REG = 5Ah After Instruction REG = FFh PIC18F2420/2520/4420/4520 DS39631B-page 302 Preliminary © 2007 Microchip Technology Inc. SLEEP Enter Sleep mode Syntax: SLEEP Operands: None Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0011 Description: The Power-down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Go to Sleep Example: SLEEP Before Instruction TO = ? PD = ? After Instruction TO = 1 † PD = 0 † If WDT causes wake-up, this bit is cleared. SUBFWB Subtract f from W with borrow Syntax: SUBFWB f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Encoding: 0101 01da ffff ffff Description: Subtract register ‘f’ and CARRY flag (borrow) from W (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBFWB REG, 1, 0 Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 303 PIC18F2420/2520/4420/4520 SUBLW Subtract W from literal Syntax: SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k – (W) → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description W is subtracted from the eight-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example 1: SUBLW 02h Before Instruction W = 01h C = ? After Instruction W = 01h C = 1 ; result is positive Z = 0 N = 0 Example 2: SUBLW 02h Before Instruction W = 02h C = ? After Instruction W = 00h C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBLW 02h Before Instruction W = 03h C = ? After Instruction W = FFh ; (2’s complement) C = 0 ; result is negative Z = 0 N = 1 SUBWF Subtract W from f Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0101 11da ffff ffff Description: Subtract W from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBWF REG, 1, 0 Before Instruction REG = 3 W = 2 C = ? After Instruction REG = 1 W = 2 C = 1 ; result is positive Z = 0 N = 0 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 PIC18F2420/2520/4420/4520 DS39631B-page 304 Preliminary © 2007 Microchip Technology Inc. SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Status Affected: N, OV, C, DC, Z Encoding: 0101 10da ffff ffff Description: Subtract W and the CARRY flag (borrow) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBWFB REG, 1, 0 Before Instruction REG = 19h (0001 1001) W = 0Dh (0000 1101) C = 1 After Instruction REG = 0Ch (0000 1011) W = 0Dh (0000 1101) C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative SWAPF Swap f Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0011 10da ffff ffff Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: SWAPF REG, 1, 0 Before Instruction REG = 53h After Instruction REG = 35h © 2007 Microchip Technology Inc. Preliminary DS39631B-page 305 PIC18F2420/2520/4420/4520 TBLRD Table Read Syntax: TBLRD ( *; *+; *-; +*) Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR; (Prog Mem (TBLPTR)) → TABLAT; Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) TBLRD Table Read (Continued) Example1: TBLRD *+ ; Before Instruction TABLAT = 55h TBLPTR = 00A356h MEMORY (00A356h) = 34h After Instruction TABLAT = 34h TBLPTR = 00A357h Example2: TBLRD +* ; Before Instruction TABLAT = AAh TBLPTR = 01A357h MEMORY (01A357h) = 12h MEMORY (01A358h) = 34h After Instruction TABLAT = 34h TBLPTR = 01A358h PIC18F2420/2520/4420/4520 DS39631B-page 306 Preliminary © 2007 Microchip Technology Inc. TBLWT Table Write Syntax: TBLWT ( *; *+; *-; +*) Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register; (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register; (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR; (TABLAT) → Holding Register; Status Affected: None Encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read TABLAT) No operation No operation (Write to Holding Register ) TBLWT Table Write (Continued) Example1: TBLWT *+; Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: TBLWT +*; Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h © 2007 Microchip Technology Inc. Preliminary DS39631B-page 307 PIC18F2420/2520/4420/4520 TSTFSZ Test f, skip if 0 Syntax: TSTFSZ f {,a} Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: skip if f = 0 Status Affected: None Encoding: 0110 011a ffff ffff Description: If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) XORLW Exclusive OR literal with W Syntax: XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W Status Affected: N, Z Encoding: 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: XORLW 0AFh Before Instruction W = B5h After Instruction W = 1Ah PIC18F2420/2520/4420/4520 DS39631B-page 308 Preliminary © 2007 Microchip Technology Inc. XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h © 2007 Microchip Technology Inc. Preliminary DS39631B-page 309 PIC18F2420/2520/4420/4520 24.2 Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2420/2520/4420/4520 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: • dynamic allocation and deallocation of software stack space when entering and leaving subroutines • function pointer invocation • software stack pointer manipulation • manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in Table 24-3. Detailed descriptions are provided in Section 24.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 24-1 (page 268) apply to both the standard and extended PIC18 instruction sets. 24.2.1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets (“[ ]”). This is done to indicate that the argument is used as an index or offset. MPASM™ Assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 24.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”. TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). Mnemonic, Operands Description Cycles 16-Bit Instruction Word Status MSb LSb Affected ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK f, k k zs, fd zs, zd k f, k k Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store literal at FSR2, decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk None None None None None None None None PIC18F2420/2520/4420/4520 DS39631B-page 310 Preliminary © 2007 Microchip Technology Inc. 24.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR Syntax: ADDFSR f, k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR(f) + k → FSR(f) Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to FSR Example: ADDFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 0422h ADDULNK Add Literal to FSR2 and Return Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operation: FSR2 + k → FSR2, (TOS) → PC Status Affected: None Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to FSR No Operation No Operation No Operation No Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). © 2007 Microchip Technology Inc. Preliminary DS39631B-page 311 PIC18F2420/2520/4420/4520 CALLW Subroutine Call Using WREG Syntax: CALLW Operands: None Operation: (PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, Status or BSR. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read WREG PUSH PC to stack No operation No operation No operation No operation No operation Example: HERE CALLW Before Instruction PC = address (HERE) PCLATH = 10h PCLATU = 00h W = 06h After Instruction PC = 001006h TOS = address (HERE + 2) PCLATH = 10h PCLATU = 00h W = 06h MOVSF Move Indexed to f Syntax: MOVSF [zs], fd Operands: 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 Operation: ((FSR2) + zs) → fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) 1110 1111 1011 ffff 0zzz ffff zzzzs ffffd Description: The contents of the source register are moved to destination register ‘fd’. The actual address of the source register is determined by adding the 7-bit literal offset ‘zs’ in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal ‘fd’ in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine source addr Determine source addr Read source reg Decode No operation No dummy read No operation Write register ‘f’ (dest) Example: MOVSF [05h], REG2 Before Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h PIC18F2420/2520/4420/4520 DS39631B-page 312 Preliminary © 2007 Microchip Technology Inc. MOVSS Move Indexed to Indexed Syntax: MOVSS [zs], [zd] Operands: 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 Operation: ((FSR2) + zs) → ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd Description The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets ‘zs’ or ‘zd’, respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine source addr Determine source addr Read source reg Decode Determine dest addr Determine dest addr Write to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: PUSHL k Operands: 0 ≤ k ≤ 255 Operation: k → (FSR2), FSR2 – 1 → FSR2 Status Affected: None Encoding: 1111 1010 kkkk kkkk Description: The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process data Write to destination Example: PUSHL 08h Before Instruction FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h After Instruction FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h © 2007 Microchip Technology Inc. Preliminary DS39631B-page 313 PIC18F2420/2520/4420/4520 SUBFSR Subtract Literal from FSR Syntax: SUBFSR f, k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR(f) – k → FSRf Status Affected: None Encoding: 1110 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: SUBFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 03DCh SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operation: FSR2 – k → FSR2 (TOS) → PC Status Affected: None Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No Operation No Operation No Operation No Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) PIC18F2420/2520/4420/4520 DS39631B-page 314 Preliminary © 2007 Microchip Technology Inc. 24.2.3 BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.5.1 “Indexed Addressing with Literal Offset”). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (‘a’ = 0), or in a GPR bank designated by the BSR (‘a’ = 1). When the extended instruction set is enabled and ‘a’ = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bitoriented instructions, or almost half of the core PIC18 instructions – may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the stack pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 24.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types. 24.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled, the file register argument, ‘f’, in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets (“[ ]”). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be ‘0’. This is in contrast to standard operation (extended instruction set disabled) when ‘a’ is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument, ‘d’, functions as before. In the latest versions of the MPASM assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing. 24.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F2420/2520/ 4420/4520, it is very important to consider the type of code. A large, re-entrant application that is written in ‘C’ and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. Note: Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 315 PIC18F2420/2520/4420/4520 ADDWF ADD W to Indexed (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Operands: 0 ≤ k ≤ 95 d ∈ [0,1] Operation: (W) + ((FSR2) + k) → dest Status Affected: N, OV, C, DC, Z Encoding: 0010 01d0 kkkk kkkk Description: The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘k’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Data Write to destination Example: ADDWF [OFST] , 0 Before Instruction W = 17h OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Contents of 0A2Ch = 20h BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: BSF [k], b Operands: 0 ≤ f ≤ 95 0 ≤ b ≤ 7 Operation: 1 → ((FSR2) + k) Status Affected: None Encoding: 1000 bbb0 kkkk kkkk Description: Bit ‘b’ of the register indicated by FSR2, offset by the value ‘k’, is set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: BSF [FLAG_OFST], 7 Before Instruction FLAG_OFST = 0Ah FSR2 = 0A00h Contents of 0A0Ah = 55h After Instruction Contents of 0A0Ah = D5h SETF Set Indexed (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Data Write register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh PIC18F2420/2520/4420/4520 DS39631B-page 316 Preliminary © 2007 Microchip Technology Inc. 24.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F2420/2520/4420/4520 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default configuration bits for that device. The default setting for the XINST configuration bit is ‘0’, disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: • A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project • A command line option • A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 317 PIC18F2420/2520/4420/4520 25.0 DEVELOPMENT SUPPORT The PIC® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PRO MATE® II Universal Device Programmer - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board • Evaluation Kits - KEELOQ® Evaluation and Programming Tools - PICDEM MSC - microID® Developer Kits - CAN - PowerSmart® Developer Kits - Analog 25.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® based application that contains: • An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) • A full-featured editor with color coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Extensive on-line help The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC emulator and simulator tools (automatically updates all project information) • Debug using: - source files (assembly or C) - mixed assembly and C - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power. 25.2 MPASM Assembler The MPASM assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process PIC18F2420/2520/4420/4520 DS39631B-page 318 Preliminary © 2007 Microchip Technology Inc. 25.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 25.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 25.5 MPLAB C30 C Compiler The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many command line options and language extensions to take full advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code generator. MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE. 25.6 MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it’s object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • Support for the entire dsPIC30F instruction set • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility 25.7 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PIC series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 25.8 MPLAB SIM30 Software Simulator The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 319 PIC18F2420/2520/4420/4520 25.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 25.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PIC microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory and the ability to view variables in real-time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 25.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC microcontrollers. The MPLAB ICD 2 utilizes the incircuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, singlestepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 25.12 PRO MATE II Universal Device Programmer The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. 25.13 MPLAB PM3 Device Programmer The MPLAB PM3 is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand- Alone mode, the MPLAB PM3 device programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. MPLAB PM3 connects to the host PC via an RS-232 or USB cable. MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. PIC18F2420/2520/4420/4520 DS39631B-page 320 Preliminary © 2007 Microchip Technology Inc. 25.14 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PIC devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 25.15 PICDEM 1 PIC Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs. 25.16 PICDEM.net Internet/Ethernet Demonstration Board The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a 16 x 2 LCD display. Also included is the book and CD-ROM “TCP/IP Lean, Web Servers for Embedded Systems,” by Jeremy Bentham 25.17 PICDEM 2 Plus Demonstration Board The PICDEM 2 Plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers. 25.18 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs. 25.19 PICDEM 4 8/14/18-Pin Demonstration Board The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow onboard hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2 x 16 liquid crystal display, PCB footprints for H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 321 PIC18F2420/2520/4420/4520 25.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion. 25.21 PICDEM 18R PIC18C601/801 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801. 25.22 PICDEM LIN PIC16C43X Demonstration Board The powerful LIN hardware and software kit includes a series of boards and three PIC microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature onboard LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication. 25.23 PICkitTM 1 Flash Starter Kit A complete “development system in a box”, the PICkit™ Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC® microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the User’s Guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB® IDE (Integrated Development Environment) software, software and hardware “Tips 'n Tricks for 8-pin Flash PIC® Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 25.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products. 25.25 Evaluation and Programming Tools In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. • KEELOQ evaluation and programming tools for Microchip’s HCS Secure Data Products • CAN developers kit for automotive network applications • Analog design boards and filter design software • PowerSmart battery charging evaluation/ calibration kits • IrDA® development kit • microID development and rfLabTM development software • SEEVAL® designer kit for memory evaluation and endurance calculations • PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits. PIC18F2420/2520/4420/4520 DS39631B-page 322 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 323 PIC18F2420/2520/4420/4520 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – Σ IOH} + Σ {(VDD – VOH) x IOH} + Σ(VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. PIC18F2420/2520/4420/4520 DS39631B-page 324 Preliminary © 2007 Microchip Technology Inc. FIGURE 26-1: PIC18F2420/2520/4420/4520 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) FIGURE 26-2: PIC18LF2X1X/4X1X VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) Frequency Voltage 6.0V 5.5V 4.5V 4.0V 2.0V 40 MHz 5.0V 3.5V 3.0V 2.5V PIC18FX42X/X52X 4.2V Frequency Voltage 6.0V 5.5V 4.5V 4.0V 2.0V 40 MHz 5.0V 3.5V 3.0V 2.5V PIC18LFX42X/X52X FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. 4 MHz 4.2V © 2007 Microchip Technology Inc. Preliminary DS39631B-page 325 PIC18F2420/2520/4420/4520 26.1 DC Characteristics:Supply Voltage PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Symbol Characteristic Min Typ Max Units Conditions D001 VDD Supply Voltage 2.0 — 5.5 V HS, XT, RC and LP Oscillator modes D002 VDR RAM Data Retention Voltage(1) 1.5 — — V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal — — 0.7 V See section on Power-on Reset for details D004 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 — — V/ms See section on Power-on Reset for details D005 VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 1.94 2.05 2.16 V BORV1:BORV0 = 10 2.65 2.79 2.93 V BORV1:BORV0 = 01 4.11 4.33 4.55 V BORV1:BORV0 = 00 4.36 4.59 4.82 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. PIC18F2420/2520/4420/4520 DS39631B-page 326 Preliminary © 2007 Microchip Technology Inc. 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Power-down Current (IPD)(1) PIC18LF2X1X/4X1X 20 950 nA -40°C VDD = 2.0V, (Sleep mode) 0.02 1.0 μA +25°C 0.6 1.1 μA +85°C PIC18LF2X1X/4X1X 0.03 1.4 μA -40°C VDD = 3.0V, (Sleep mode) 0.03 1.5 μA +25°C 0.8 1.6 μA +85°C All devices 0.04 1.9 μA -40°C VDD = 5.0V, (Sleep mode) 0.04 2.0 μA +25°C 1.7 2.1 μA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 327 PIC18F2420/2520/4420/4520 Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 15 31.5 μA -40°C FOSC = 31 kHz (RC_RUN mode, INTRC source) 15 30 μA +25°C VDD = 2.0V 15 28.5 μA +85°C PIC18LF2X1X/4X1X 40 63 μA -40°C 35 60 μA +25°C VDD = 3.0V 30 57 μA +85°C All devices 105 168 μA -40°C 90 160 μA +25°C VDD = 5.0V 80 152 μA +85°C PIC18LF2X1X/4X1X 0.32 630 μA -40°C FOSC = 1 MHz (RC_RUN mode, INTOSC source) 0.33 600 μA +25°C VDD = 2.0V 0.33 570 μA +85°C PIC18LF2X1X/4X1X 0.6 1.3 mA -40°C 0.55 1.2 mA +25°C VDD = 3.0V 0.6 1.1 mA +85°C All devices 1.1 2.3 mA -40°C 1.1 2.2 mA +25°C VDD = 5.0V 1.0 2.1 mA +85°C 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. PIC18F2420/2520/4420/4520 DS39631B-page 328 Preliminary © 2007 Microchip Technology Inc. Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 0.8 2.1 μA -40°C FOSC = 4 MHz (RC_RUN mode, INTRC source) 0.8 2.0 μA +25°C VDD = 2.0V 0.8 1.9 μA +85°C PIC18LF2X1X/4X1X 1.3 2.7 mA -40°C 1.3 2.6 mA +25°C VDD = 3.0V 1.3 2.5 mA +85°C All devices 2.5 5.3 mA -40°C 2.5 5.0 mA +25°C VDD = 5.0V 2.5 4.8 mA +85°C PIC18LF2X1X/4X1X 2.9 6.5 μA -40°C FOSC = 31 kHz (RC_IDLE mode, INTRC source) 3.1 6.2 μA +25°C VDD = 2.0V 3.6 5.9 μA +85°C PIC18LF2X1X/4X1X 4.5 10.1 μA -40°C 4.8 9.6 μA +25°C VDD = 3.0V 5.8 9.1 μA +85°C All devices 9.2 15.8 μA -40°C 9.8 15 μA +25°C VDD = 5.0V 11.4 14.3 μA +85°C 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 329 PIC18F2420/2520/4420/4520 Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 165 315 μA -40°C FOSC = 1 MHz (RC_IDLE mode, INTOSC source) 175 300 μA +25°C VDD = 2.0V 190 285 μA +85°C PIC18LF2X1X/4X1X 250 470 μA -40°C 270 450 μA +25°C VDD = 3.0V 290 430 μA +85°C All devices 500 840 μA -40°C 520 800 μA +25°C VDD = 5.0V 550 760 μA +85°C PIC18LF2X1X/4X1X 340 525 μA -40°C FOSC = 4 MHz (RC_IDLE mode, INTOSC source) 350 500 μA +25°C VDD = 2.0V 360 475 μA +85°C PIC18LF2X1X/4X1X 520 735 μA -40°C 540 700 μA +25°C VDD = 3.0V 580 665 μA +85°C All devices 1.0 1.6 mA -40°C 1.1 1.5 mA +25°C VDD = 5.0V 1.1 1.4 mA +85°C 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. PIC18F2420/2520/4420/4520 DS39631B-page 330 Preliminary © 2007 Microchip Technology Inc. Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 250 420 μA -40°C FOSC = 1 MHZ (PRI_RUN, EC oscillator) 260 400 μA +25°C VDD = 2.0V 250 380 μA +85°C PIC18LF2X1X/4X1X 550 740 μA -40°C 480 700 μA +25°C VDD = 3.0V 460 670 μA +85°C All devices 1.2 1.6 mA -40°C 1.1 1.5 mA +25°C VDD = 5.0V 1.0 1.4 mA +85°C PIC18LF2X1X/4X1X 0.72 1.6 mA -40°C FOSC = 4 MHz (PRI_RUN, EC oscillator) 0.74 1.5 mA +25°C VDD = 2.0V 0.74 1.4 mA +85°C PIC18LF2X1X/4X1X 1.3 2.6 mA -40°C 1.3 2.5 mA +25°C VDD = 3.0V 1.3 2.4 mA +85°C All devices 2.7 4.7 mA -40°C 2.6 4.5 mA +25°C VDD = 5.0V 2.5 4.3 mA +85°C All devices 15 26 mA -40°C FOSC = 40 MHZ (PRI_RUN, EC oscillator) 16 25 mA +25°C VDD = 4.2V 16 24 mA +85°C All devices 21 32 mA -40°C 21 30 mA +25°C VDD = 5.0V 21 28 mA +85°C 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 331 PIC18F2420/2520/4420/4520 Supply Current (IDD)(2,3) All devices 7.5 16 mA -40°C VDD = 4.2V FOSC = 4 MHZ (PRI_RUN HS+PLL) 7.4 15 mA +25°C 7.3 14 mA +85°C All devices 10 21 mA -40°C VDD = 5.0V FOSC = 4 MHZ 10 20 mA +25°C (PRI_RUN HS+PLL) 9.7 19 mA +85°C All devices 17 35 mA -40°C VDD = 4.2V FOSC = 10 MHZ 17 34 mA +25°C (PRI_RUN HS+PLL) 17 33 mA +85°C All devices 23 46 mA -40°C VDD = 5.0V FOSC = 10 MHZ 23 45 mA +25°C (PRI_RUN HS+PLL) 23 43 mA +85°C 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. PIC18F2420/2520/4420/4520 DS39631B-page 332 Preliminary © 2007 Microchip Technology Inc. Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 65 130 μA -40°C FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) 65 120 μA +25°C VDD = 2.0V 70 115 μA +85°C PIC18LF2X1X/4X1X 120 270 μA -40°C 120 250 μA +25°C VDD = 3.0V 130 240 μA +85°C All devices 300 480 μA -40°C 240 450 μA +25°C VDD = 5.0V 300 430 μA +85°C PIC18LF2X1X/4X1X 260 475 μA -40°C FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) 255 450 μA +25°C VDD = 2.0V 270 430 μA +85°C PIC18LF2X1X/4X1X 420 900 μA -40°C 430 850 μA +25°C VDD = 3.0V 450 810 μA +85°C All devices 0.9 1.5 mA -40°C 0.9 1.4 mA +25°C VDD = 5.0V 0.9 1.3 mA +85°C All devices 6.0 9.5 mA -40°C FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) 6.2 9.0 mA +25°C VDD = 4.2 V 6.6 8.6 mA +85°C All devices 8.1 12.6 mA -40°C 9.1 12.0 mA +25°C VDD = 5.0V 8.3 11.4 mA +85°C 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 333 PIC18F2420/2520/4420/4520 Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 14 31.5 μA -10°C FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) 15 30 μA +25°C VDD = 2.0V 16 29 μA +70°C PIC18LF2X1X/4X1X 40 74 μA -10°C 35 70 μA +25°C VDD = 3.0V 31 67 μA +70°C All devices 99 126 μA -10°C 81 120 μA +25°C VDD = 5.0V 75 114 μA +70°C PIC18LF2X1X/4X1X 2.5 7.4 μA -10°C FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) 3.7 7.0 μA +25°C VDD = 2.0V 4.5 6.7 μA +70°C PIC18LF2X1X/4X1X 5.0 10.5 μA -10°C 5.4 10 μA +25°C VDD = 3.0V 6.3 9.5 μA +70°C All devices 8.5 17 μA -10°C 9.0 16 μA +25°C VDD = 5.0V 10.5 15 μA +70°C 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. PIC18F2420/2520/4420/4520 DS39631B-page 334 Preliminary © 2007 Microchip Technology Inc. Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD) D022 (ΔIWDT) Watchdog Timer 1.3 7.6 μA -40°C 1.4 8.0 μA +25°C VDD = 2.0V 2.0 8.4 μA +85°C 1.9 11.4 μA -40°C 2.0 12.0 μA +25°C VDD = 3.0V 2.8 12.6 μA +85°C 4.0 14.3 μA -40°C 5.5 15.0 μA +25°C VDD = 5.0V 5.6 15.8 μA +85°C D022A (ΔIBOR) Brown-out Reset(5) 35 52 μA -40°C to +85°C VDD = 3.0V 40 63 μA -40°C to +85°C VDD = 5.0V 40 63 μA -40°C to +85°C VDD = 5.0V Sleep mode, BOREN1:BOREN0 = 10 D022B (ΔILVD) High/Low-Voltage Detect(5) 22 47 μA -40°C to +85°C VDD = 2.0V 25 58 μA -40°C to +85°C VDD = 3.0V 29 69 μA -40°C to +85°C VDD = 5.0V D025 (ΔIOSCB) Timer1 Oscillator 0.01 4.8 μA -10°C 0.01 5.0 μA +25°C VDD = 2.0V 32 kHz on Timer1(4) 0.01 5.3 μA +70°C 0.01 7.6 μA -10°C 0.01 8.0 μA +25°C VDD = 3.0V 32 kHz on Timer1(4) 0.01 8.4 μA +70°C 0.01 9.5 μA -10°C 0.01 10.0 μA +25°C VDD = 5.0V 32 kHz on Timer1(4) 0.01 10.5 μA +70°C D026 (ΔIAD) A/D Converter 1.0 2.0 μA VDD = 2.0V 1.0 2.0 μA VDD = 3.0V A/D on, not converting 1.0 2.0 μA VDD = 5.0V 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial ParamNo. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 335 PIC18F2420/2520/4420/4520 26.3 DC Characteristics: PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Symbol Characteristic Min Max Units Conditions VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer RC3 and RC4 VSS VSS 0.2 VDD 0.3 VDD V V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A D033B D034 OSC1 OSC1 T13CKI VSS VSS VSS 0.2 VDD 0.3 VDD 0.3 VDD V V V RC, EC modes(1) XT, LP modes VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger buffer RC3 and RC4 0.8 VDD 0.7 VDD VDD VDD V V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A D043B D043C D044 OSC1 OSC1 OSC1 T13CKI 0.8 VDD 0.9 VDD 1.6 1.6 VDD VDD VDD VDD V V V V EC mode RC mode(1) XT, LP modes IIL Input Leakage Current(2,3) D060 I/O ports — ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR — ±5 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±5 μA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 μA VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. PIC18F2420/2520/4420/4520 DS39631B-page 336 Preliminary © 2007 Microchip Technology Inc. VOL Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C VOH Output High Voltage(3) D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D092 OSC2/CLKO (RC, RCIO, EC, ECIO modes) VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (in RC mode) — 50 pF To meet the AC Timing Specifications D102 CB SCL, SDA — 400 pF I2C™ Specification 26.3 DC Characteristics: PIC18F2420/2520/4420/4520 (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Symbol Characteristic Min Max Units Conditions Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 337 PIC18F2420/2520/4420/4520 TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Sym Characteristic Min Typ† Max Units Conditions Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP/RE3 pin 9.00 — 13.25 V (Note 3) D113 IDDP Supply Current during Programming — — 10 mA Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C to +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write Cycles before Refresh(2) 1M 10M — E/W -40°C to +85°C Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP port D132A VIW VDD for Externally Timed Erase or Write 4.5 — 5.5 V Using ICSP port D132B VPEW VDD for Self-timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133 TIE ICSP Block Erase Cycle Time — 4 — ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time (externally timed) 1 — — ms VDD > 4.5V D133A TIW Self-timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. PIC18F2420/2520/4420/4520 DS39631B-page 338 Preliminary © 2007 Microchip Technology Inc. TABLE 26-2: COMPARATOR SPECIFICATIONS TABLE 26-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio* 55 — — dB 300 TRESP Response Time(1)* — 150 400 ns PIC18FXXXX 300A — 150 600 ns PIC18LFXXXX, VDD = 2.0V 301 TMC2OV Comparator Mode Change to Output Valid* — — 10 μs * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units Comments D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb Low Range (CVRR = 1) D312 VRUR Unit Resistor Value (R)* — 2k — Ω 310 TSET Settling Time(1)* — — 10 μs * These parameters are characterized but not tested. Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 339 PIC18F2420/2520/4420/4520 FIGURE 26-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS TABLE 26-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VLVD HLVDIF VDD (HLVDIF set by hardware) (HLVDIF can be cleared in software) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Symbol Characteristic Min Typ† Max Units Conditions D420 HLVD Voltage on VDD Transition High-to-Low LVV = 0000 2.12 2.17 2.22 V LVV = 0001 2.18 2.23 2.28 V LVV = 0010 2.31 2.36 2.42 V LVV = 0011 2.38 2.44 2.49 V LVV = 0100 2.54 2.60 2.66 V LVV = 0101 2.72 2.79 2.85 V LVV = 0110 2.82 2.89 2.95 V LVV = 0111 3.05 3.12 3.19 V LVV = 1000 3.31 3.39 3.47 V LVV = 1001 3.46 3.55 3.63 V LVV = 1010 3.63 3.71 3.80 V LVV = 1011 3.81 3.90 3.99 V LVV = 1100 4.01 4.11 4.20 V LVV = 1101 4.23 4.33 4.43 V LVV = 1110 4.48 4.59 4.69 V † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization. PIC18F2420/2520/4420/4520 DS39631B-page 340 Preliminary © 2007 Microchip Technology Inc. 26.4 AC (Timing) Characteristics 26.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition © 2007 Microchip Technology Inc. Preliminary DS39631B-page 341 PIC18F2420/2520/4420/4520 26.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 26-5 apply to all timing specifications unless otherwise noted. Figure 26-4 specifies the load conditions for the timing specifications. TABLE 26-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC FIGURE 26-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Note: Because of space limitations, the generic terms “PIC18FXXXX” and “PIC18LFXXXX” are used throughout this section to refer to the PIC18F2420/2520/4420/4520 and PIC18LF2X1X/4X1X families of devices specifically and only those devices. AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Operating voltage VDD range as described in DC spec Section 26.1 and Section 26.3. LF parts operate for industrial temperatures only. VDD/2 CL RL Pin Pin VSS VSS CL RL = 464Ω CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Load Condition 1 Load Condition 2 PIC18F2420/2520/4420/4520 DS39631B-page 342 Preliminary © 2007 Microchip Technology Inc. 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS OSC1 CLKO Q4 Q1 Q2 Q3 Q4 Q1 1 2 3 3 4 4 Param. No. Symbol Characteristic Min Max Units Conditions 1A FOSC External CLKI Frequency(1) DC 40 MHz EC, ECIO Oscillator mode Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 10 MHz HS + PLL Oscillator mode 5 33 kHz LP Oscillator mode 1 TOSC External CLKI Period(1) 25 — ns EC, ECIO Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 250 10,000 ns XT Oscillator mode 40 100 250 250 ns ns HS Oscillator mode HS + PLL Oscillator mode 30 — μs LP Oscillator mode 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC 3 TOSL, TOSH External Clock in (OSC1) High or Low Time 30 — ns XT Oscillator mode 2.5 — μs LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, TOSF External Clock in (OSC1) Rise or Fall Time — 20 ns XT Oscillator mode — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 343 PIC18F2420/2520/4420/4520 TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) TABLE 26-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F2420/2520/4420/4520 (INDUSTRIAL) PIC18LF2X1X/4X1X (INDUSTRIAL) Param No. Sym Characteristic Min Typ† Max Units Conditions F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only F12 trc PLL Start-up Time (Lock Time) — — 2 ms F13 ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FX42X/X52X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Min Typ Max Units Conditions INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC18LF2X1X/4X1X -2 +/-1 2 % +25°C VDD = 2.7-3.3V -5 — 5 % -10°C to +85°C VDD = 2.7-3.3V -10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3V PIC18FX42X/X52X -2 +/-1 2 % +25°C VDD = 4.5-5.5V -5 — 5 % -10°C to +85°C VDD = 4.5-5.5V -10 +/-1 10 % -40°C to +85°C VDD = 4.5-5.5V INTRC Accuracy @ Freq = 31 kHz(2) PIC18LF2X1X/4X1X 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V PIC18FX42X/X52X 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. 2: INTRC frequency after calibration. 3: Change of INTRC frequency as VDD changes. PIC18F2420/2520/4420/4520 DS39631B-page 344 Preliminary © 2007 Microchip Technology Inc. FIGURE 26-6: CLKO AND I/O TIMING TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS Note: Refer to Figure 26-4 for load conditions. OSC1 CLKO I/O pin (Input) I/O pin (Output) Q4 Q1 Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 Old Value New Value Param No. Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12 TckR CLKO Rise Time — 35 100 ns (Note 1) 13 TckF CLKO Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port In Hold after CLKO ↑ 0 — — ns (Note 1) 17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1 ↑ (Q2 cycle) to Port Input Invalid (I/O in hold time) PIC18FXXXX 100 — — ns 18A PIC18LFXXXX 200 — — ns VDD = 2.0V 19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time) 0 — — ns 20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns 20A PIC18LFXXXX — — 60 ns VDD = 2.0V 21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns 21A PIC18LFXXXX — — 60 ns VDD = 2.0V 22† TINP INT pin High or Low Time TCY — — ns 23† TRBP RB7:RB4 Change INT High or Low Time TCY — — ns 24† TRCP RC7:RC4 Change INT High or Low Time 20 ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 345 PIC18F2420/2520/4420/4520 FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING FIGURE 26-8: BROWN-OUT RESET TIMING TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. No. Symbol Characteristic Min Typ Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period (no postscaler) — 4.00 TBD ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period — 65.5 TBD ms 34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset — 2 — μs 35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005) 36 TIVRST Time for Internal Reference Voltage to become Stable — 20 50 μs 37 TLVD High/Low-Voltage Detect Pulse Width 200 — — μs VDD ≤ VLVD 38 TCSD CPU Start-up Time 5 — 10 μs 39 TIOBST Time for INTOSC to Stabilize — 1 — ms Legend: TBD = To Be Determined VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 33 32 30 31 34 I/O pins 34 Note: Refer to Figure 26-4 for load conditions. VDD BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Internal Reference 36 Reference Voltage Voltage Stable PIC18F2420/2520/4420/4520 DS39631B-page 346 Preliminary © 2007 Microchip Technology Inc. FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Note: Refer to Figure 26-4 for load conditions. 46 47 45 48 41 42 40 T0CKI T1OSO/T13CKI TMR0 or TMR1 Param No. Symbol Characteristic Min Max Units Conditions 40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 Tt0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: 20 ns or (TCY + 40)/N — ns N = prescale value (1, 2, 4,..., 256) 45 Tt1H T13CKI High Time Synchronous, no prescaler 0.5 TCY + 20 — ns Synchronous, with prescaler PIC18FXXXX 10 — ns PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 46 Tt1L T13CKI Low Time Synchronous, no prescaler 0.5 TCY + 5 — ns Synchronous, with prescaler PIC18FXXXX 10 — ns PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 47 Tt1P T13CKI Input Period Synchronous Greater of: 20 ns or (TCY + 40)/N — ns N = prescale value (1, 2, 4, 8) Asynchronous 60 — ns Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 Tcke2tmrI Delay from External T13CKI Clock Edge to Timer Increment 2 TOSC 7 TOSC — © 2007 Microchip Technology Inc. Preliminary DS39631B-page 347 PIC18F2420/2520/4420/4520 FIGURE 26-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Note: Refer to Figure 26-4 for load conditions. CCPx (Capture Mode) 50 51 52 CCPx 53 54 (Compare or PWM Mode) Param No. Symbol Characteristic Min Max Units Conditions 50 TccL CCPx Input Low Time No prescaler 0.5 TCY + 20 — ns With prescaler PIC18FXXXX 10 — ns PIC18LFXXXX 20 — ns VDD = 2.0V 51 TccH CCPx Input High Time No prescaler 0.5 TCY + 20 — ns With prescaler PIC18FXXXX 10 — ns PIC18LFXXXX 20 — ns VDD = 2.0V 52 TccP CCPx Input Period 3 TCY + 40 N — ns N = prescale value (1, 4 or 16) 53 TccR CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 54 TccF CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V PIC18F2420/2520/4420/4520 DS39631B-page 348 Preliminary © 2007 Microchip Technology Inc. FIGURE 26-11: PARALLEL SLAVE PORT TIMING (PIC18F4420/4520) TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4420/4520) Note: Refer to Figure 26-4 for load conditions. RE2/CS RE0/RD RE1/WR RD7:RD0 62 63 64 65 Param. No. Symbol Characteristic Min Max Units Conditions 62 TdtV2wrH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TwrH2dtI WR ↑ or CS ↑ to Data–In Invalid (hold time) PIC18FXXXX 20 — ns PIC18LFXXXX 35 — ns VDD = 2.0V 64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from WR ↑ or CS ↑ — 3 TCY © 2007 Microchip Technology Inc. Preliminary DS39631B-page 349 PIC18F2420/2520/4420/4520 FIGURE 26-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) SS SCK (CKP = 0) SCK (CKP = 1) SDO SDI 70 71 72 73 74 75, 76 79 78 80 78 79 MSb bit 6 - - - - - -1 LSb MSb In bit 6 - - - -1 LSb In Note: Refer to Figure 26-4 for load conditions. Param No. Symbol Characteristic Min Max Units Conditions 70 TssL2scH, TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY — ns 71 TscH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns PIC18LFXXXX — 100 ns VDD = 2.0V Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. PIC18F2420/2520/4420/4520 DS39631B-page 350 Preliminary © 2007 Microchip Technology Inc. FIGURE 26-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO SDI 81 71 72 74 75, 76 78 80 MSb 79 73 MSb In bit 6 - - - - - -1 bit 6 - - - -1 LSb In LSb Note: Refer to Figure 26-4 for load conditions. Param. No. Symbol Characteristic Min Max Units Conditions 71 TscH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns PIC18LFXXXX 100 ns VDD = 2.0V 81 TdoV2scH, TdoV2scL SDO Data Output Setup to SCK Edge TCY — ns Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 351 PIC18F2420/2520/4420/4520 FIGURE 26-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic Min Max Units Conditions 70 TssL2scH, TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY — ns 71 TscH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS↑ to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns PIC18LFXXXX 100 ns VDD = 2.0V 83 TscH2ssH, TscL2ssH SS ↑ after SCK edge 1.5 TCY + 40 — ns Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. SS SCK (CKP = 0) SCK (CKP = 1) SDO 70 71 72 73 74 75, 76 77 79 78 80 78 79 SDI MSb bit 6 - - - - - -1 LSb MSb In bit 6 - - - -1 LSb In 83 Note: Refer to Figure 26-4 for load conditions. PIC18F2420/2520/4420/4520 DS39631B-page 352 Preliminary © 2007 Microchip Technology Inc. FIGURE 26-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min Max Units Conditions 70 TssL2scH, TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY — ns 71 TscH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS↑ to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns PIC18LFXXXX — 100 ns VDD = 2.0V 82 TssL2doV SDO Data Output Valid after SS ↓ Edge PIC18FXXXX — 50 ns PIC18LFXXXX — 100 ns VDD = 2.0V 83 TscH2ssH, TscL2ssH SS ↑ after SCK Edge 1.5 TCY + 40 — ns Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. SS SCK (CKP = 0) SCK (CKP = 1) SDO 70 71 72 82 SDI 74 75, 76 MSb bit 6 - - - - - -1 LSb 77 MSb In bit 6 - - - -1 LSb In 80 83 Note: Refer to Figure 26-4 for load conditions. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 353 PIC18F2420/2520/4420/4520 FIGURE 26-16: I2C BUS START/STOP BITS TIMING TABLE 26-18: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) FIGURE 26-17: I2C BUS DATA TIMING Note: Refer to Figure 26-4 for load conditions. 91 92 93 SCL SDA Start Condition Stop Condition 90 Param. No. Symbol Characteristic Min Max Units Conditions 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — Note: Refer to Figure 26-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 SCL SDA In SDA Out PIC18F2420/2520/4420/4520 DS39631B-page 354 Preliminary © 2007 Microchip Technology Inc. TABLE 26-19: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. Symbol Characteristic Min Max Units Conditions 100 THIGH Clock High Time 100 kHz mode 4.0 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 102 TR SDA and SCL Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — μs After this period, the first 400 kHz mode 0.6 — μs clock pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free before a new transmission can start 400 kHz mode 1.3 — μs D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT ≥ 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification), before the SCL line is released. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 355 PIC18F2420/2520/4420/4520 FIGURE 26-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS TABLE 26-20: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS FIGURE 26-19: MASTER SSP I2C BUS DATA TIMING Note: Refer to Figure 26-4 for load conditions. 91 93 SCL SDA Start Condition Stop Condition 90 92 Param. No. Symbol Characteristic Min Max Units Conditions 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Repeated Start condition Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the first clock pulse is generated Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. Note: Refer to Figure 26-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 SCL SDA In SDA Out PIC18F2420/2520/4420/4520 DS39631B-page 356 Preliminary © 2007 Microchip Technology Inc. TABLE 26-21: MASTER SSP I2C BUS DATA REQUIREMENTS Param. No. Symbol Characteristic Min Max Units Conditions 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL Rise Time 100 kHz mode — 1000 ns CB is specified to be from 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL Fall Time 100 kHz mode — 300 ns CB is specified to be from 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Repeated Start condition 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition Hold Time 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new transmission can start 400 kHz mode 1.3 — ms D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107 ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL line is released. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 357 PIC18F2420/2520/4420/4520 FIGURE 26-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TABLE 26-22: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS FIGURE 26-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TABLE 26-23: USART SYNCHRONOUS RECEIVE REQUIREMENTS 121 121 120 122 RC6/TX/CK RC7/RX/DT pin pin Note: Refer to Figure 26-4 for load conditions. Param No. Symbol Characteristic Min Max Units Conditions 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 Tckrf Clock Out Rise Time and Fall Time (Master mode) PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V 122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V 125 126 RC6/TX/CK RC7/RX/DT pin pin Note: Refer to Figure 26-4 for load conditions. Param. No. Symbol Characteristic Min Max Units Conditions 125 TdtV2ckl SYNC RCV (MASTER & SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TckL2dtl Data Hold after CK ↓ (DT hold time) 15 — ns PIC18F2420/2520/4420/4520 DS39631B-page 358 Preliminary © 2007 Microchip Technology Inc. TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18FX42X/X52X (INDUSTRIAL) PIC18LF2X1X/4X1X (INDUSTRIAL) Param No. Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±1 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range (VREFH – VREFL) 1.8 3 — — — — V V VDD < 3.0V VDD ≥ 3.0V A21 VREFH Reference Voltage High VSS — VREFH V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source — — 2.5 kΩ A50 IREF VREF Input Current(2) — — — — 5 150 μA μA During VAIN acquisition. During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. © 2007 Microchip Technology Inc. Preliminary DS39631B-page 359 PIC18F2420/2520/4420/4520 FIGURE 26-22: A/D CONVERSION TIMING TABLE 26-25: A/D CONVERSION REQUIREMENTS 131 130 132 BSF ADCON0, GO Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA SAMPLING STOPPED DONE NEW_DATA (Note 2) 9 8 7 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . TCY Param No. Symbol Characteristic Min Max Units Conditions 130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μs VDD = 2.0V; TOSC based, VREF full range PIC18FXXXX TBD 1 μs A/D RC mode PIC18LFXXXX TBD 3 μs VDD = 2.0V; A/D RC mode 131 TCNV Conversion Time (not including acquisition time) (Note 2) 11 12 TAD 132 TACQ Acquisition Time (Note 3) 1.4 TBD — — μs μs -40°C to +85°C 0°C ≤ to ≤ +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) TBD TDIS Discharge Time 0.2 — μs Legend: TBD = To Be Determined Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES register may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. PIC18F2420/2520/4420/4520 DS39631B-page 360 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 361 PIC18F2420/2520/4420/4520 27.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. PIC18F2420/2520/4420/4520 DS39631B-page 362 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 363 PIC18F2420/2520/4420/4520 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 28-Lead PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F2520-I/SP 0710017 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F2520-E/SO 0710017 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F4420-I/P 0710017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e3 e3 e3 e3 e3 PIC18F2420/2520/4420/4520 DS39631B-page 364 Preliminary © 2007 Microchip Technology Inc. Package Marking Information (Continued) 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Example PIC18F4420 -I/PT 0710017 XXXXXXXXXX 44-Lead QFN XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F4520 Example -I/ML 0710017 28-Lead QFN XXXXXXXX XXXXXXXX YYWWNNN Example 18F2420 -I/ML 0710017 e3 e3 e3 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 365 PIC18F2420/2520/4420/4520 28.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e .100 BSC Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .050 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 NOTE 1 N 1 2 D E1 eB c E L A2 b e A1 b1 A 3 Microchip Technology Drawing C04-070B PIC18F2420/2520/4420/4520 DS39631B-page 366 Preliminary © 2007 Microchip Technology Inc. 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 1.27 BSC Overall Height A – – 2.65 Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E 10.30 BSC Molded Package Width E1 7.50 BSC Overall Length D 17.90 BSC Chamfer (optional) h 0.25 – 0.75 Foot Length L 0.40 – 1.27 Footprint L1 1.40 REF Foot Angle Top φ 0° – 8° Lead Thickness c 0.18 – 0.33 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° c h h L L1 A2 A1 A NOTE 1 1 2 3 b e E E1 D φ β α N Microchip Technology Drawing C04-052B © 2007 Microchip Technology Inc. Preliminary DS39631B-page 367 PIC18F2420/2520/4420/4520 40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 40 Pitch e .100 BSC Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .590 – .625 Molded Package Width E1 .485 – .580 Overall Length D 1.980 – 2.095 Tip to Seating Plane L .115 – .200 Lead Thickness c .008 – .015 Upper Lead Width b1 .030 – .070 Lower Lead Width b .014 – .023 Overall Row Spacing § eB – – .700 N NOTE 1 E1 D 1 2 3 A A1 b1 b e c eB E L A2 Microchip Technology Drawing C04-016B PIC18F2420/2520/4420/4520 DS39631B-page 368 Preliminary © 2007 Microchip Technology Inc. 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 6.00 BSC Exposed Pad Width E2 3.65 3.70 4.20 Overall Length D 6.00 BSC Exposed Pad Length D2 3.65 3.70 4.20 Contact Width b 0.23 0.30 0.35 Contact Length L 0.50 0.55 0.70 Contact-to-Exposed Pad K 0.20 – – D EXPOSED D2 e b K E2 E L N NOTE 1 1 2 2 1 N A A3 A1 TOP VIEW BOTTOM VIEW PAD Microchip Technology Drawing C04-105B © 2007 Microchip Technology Inc. Preliminary DS39631B-page 369 PIC18F2420/2520/4420/4520 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 44 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 8.00 BSC Exposed Pad Width E2 6.30 6.45 6.80 Overall Length D 8.00 BSC Exposed Pad Length D2 6.30 6.45 6.80 Contact Width b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – D EXPOSED PAD D2 e b K L E2 2 1 N NOTE 1 2 1 E N TOP VIEW BOTTOM VIEW A3 A1 A Microchip Technology Drawing C04-103B PIC18F2420/2520/4420/4520 DS39631B-page 370 Preliminary © 2007 Microchip Technology Inc. 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.30 0.37 0.45 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° A E E1 D D1 e b NOTE 1 NOTE 2 N 1 2 3 c A1 L A2 L1 α φ β Microchip Technology Drawing C04-076B © 2007 Microchip Technology Inc. Preliminary DS39631B-page 371 PIC18F2420/2520/4420/4520 APPENDIX A: REVISION HISTORY Revision A (June 2004) Original data sheet for PIC18F2420/2520/4420/4520 devices. Revision B (January 2007) This revision includes updates to the packaging diagrams. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Features PIC18F2420 PIC18F2520 PIC18F4420 PIC18F4520 Program Memory (Bytes) 16384 32768 16384 32768 Program Memory (Instructions) 8192 16384 8192 16384 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 2 2 1 1 Enhanced Capture/Compare/PWM Modules 0 0 1 1 Parallel Communications (PSP) No No Yes Yes 10-bit Analog-to-Digital Module 10 input channels 10 input channels 13 input channels 13 input channels Packages 28-pin PDIP 28-pin SOIC 28-pin QFN 28-pin PDIP 28-pin SOIC 28-pin QFN 40-pin PDIP 44-pin TQFP 44-pin QFN 40-pin PDIP 44-pin TQFP 44-pin QFN PIC18F2420/2520/4420/4520 DS39631B-page 372 Preliminary © 2007 Microchip Technology Inc. APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available © 2007 Microchip Technology Inc. Preliminary DS39631B-page 373 PIC18F2420/2520/4420/4520 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716. APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration”. This Application Note is available as Literature Number DS00726. PIC18F2420/2520/4420/4520 DS39631B-page 374 Preliminary © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. Preliminary DS39631B-page 375 PIC18F2420/2520/4420/4520 INDEX A A/D ................................................................................... 223 A/D Converter Interrupt, Configuring ....................... 227 Acquisition Requirements ........................................ 228 ADCON0 Register .................................................... 223 ADCON1 Register .................................................... 223 ADCON2 Register .................................................... 223 ADRESH Register ............................................ 223, 226 ADRESL Register .................................................... 223 Analog Port Pins, Configuring .................................. 230 Associated Registers ............................................... 232 Calculating the Minimum Required Acquisition Time .............................................. 228 Configuring the Module ............................................ 227 Conversion Clock (TAD) ........................................... 229 Conversion Status (GO/DONE Bit) .......................... 226 Conversions ............................................................. 231 Converter Characteristics ........................................ 358 Discharge ................................................................. 231 Operation in Power Managed Modes ...................... 230 Selecting and Configuring Acquisition Time ............ 229 Special Event Trigger (CCP) .................................... 232 Special Event Trigger (ECCP) ................................. 148 Use of the CCP2 Trigger .......................................... 232 Absolute Maximum Ratings ............................................. 323 AC (Timing) Characteristics ............................................. 340 Load Conditions for Device Timing Specifications ....................................... 341 Parameter Symbology ............................................. 340 Temperature and Voltage Specifications ................. 341 Timing Conditions .................................................... 341 AC Characteristics Internal RC Accuracy ............................................... 343 Access Bank Mapping with Indexed Literal Offset Mode ................. 72 ACKSTAT ........................................................................ 191 ACKSTAT Status Flag ..................................................... 191 ADCON0 Register ............................................................ 223 GO/DONE Bit ........................................................... 226 ADCON1 Register ............................................................ 223 ADCON2 Register ............................................................ 223 ADDFSR .......................................................................... 310 ADDLW ............................................................................ 273 ADDULNK ........................................................................ 310 ADDWF ............................................................................ 273 ADDWFC ......................................................................... 274 ADRESH Register ............................................................ 223 ADRESL Register .................................................... 223, 226 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 274 ANDWF ............................................................................ 275 Assembler MPASM Assembler .................................................. 317 Auto-Wake-up on Sync Break Character ......................... 214 B Bank Select Register (BSR) ............................................... 59 Baud Rate Generator ....................................................... 187 BC .................................................................................... 275 BCF .................................................................................. 276 BF .................................................................................... 191 BF Status Flag ................................................................. 191 Block Diagrams A/D ........................................................................... 226 Analog Input Model .................................................. 227 Baud Rate Generator .............................................. 187 Capture Mode Operation ......................................... 141 Comparator Analog Input Model .............................. 237 Comparator I/O Operating Modes ........................... 234 Comparator Output .................................................. 236 Comparator Voltage Reference ............................... 240 Compare Mode Operation ....................................... 142 Device Clock .............................................................. 28 Enhanced PWM ....................................................... 149 EUSART Receive .................................................... 213 EUSART Transmit ................................................... 211 External Power-on Reset Circuit (Slow VDD Power-up) ........................................ 43 Fail-Safe Clock Monitor (FSCM) .............................. 261 Generic I/O Port ....................................................... 105 High/Low-Voltage Detect with External Input .......... 244 Interrupt Logic ............................................................ 92 MSSP (I2C Master Mode) ........................................ 185 MSSP (I2C Mode) .................................................... 170 MSSP (SPI Mode) ................................................... 161 On-Chip Reset Circuit ................................................ 41 PIC18F2420/2520 ..................................................... 10 PIC18F4420/4520 ..................................................... 11 PLL (HS Mode) .......................................................... 25 PORTD and PORTE (Parallel Slave Port) ............... 120 PWM Operation (Simplified) .................................... 144 Reads from Flash Program Memory ......................... 77 Single Comparator ................................................... 235 Table Read Operation ............................................... 73 Table Write Operation ............................................... 74 Table Writes to Flash Program Memory .................... 79 Timer0 in 16-Bit Mode ............................................. 124 Timer0 in 8-Bit Mode ............................................... 124 Timer1 ..................................................................... 128 Timer1 (16-Bit Read/Write Mode) ............................ 128 Timer2 ..................................................................... 134 Timer3 ..................................................................... 136 Timer3 (16-Bit Read/Write Mode) ............................ 136 Voltage Reference Output Buffer Example ............. 241 Watchdog Timer ...................................................... 258 BN .................................................................................... 276 BNC ................................................................................. 277 BNN ................................................................................. 277 BNOV .............................................................................. 278 BNZ ................................................................................. 278 BOR. See Brown-out Reset. BOV ................................................................................. 281 BRA ................................................................................. 279 Break Character (12-Bit) Transmit and Receive .............. 216 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ..................................................... 44 Detecting ................................................................... 44 Disabling in Sleep Mode ............................................ 44 Software Enabled ...................................................... 44 BSF .................................................................................. 279 BTFSC ............................................................................. 280 BTFSS ............................................................................. 280 BTG ................................................................................. 281 BZ .................................................................................... 282 PIC18F2420/2520/4420/4520 DS39631B-page 376 Preliminary © 2007 Microchip Technology Inc. C C Compilers MPLAB C17 ............................................................. 318 MPLAB C18 ............................................................. 318 MPLAB C30 ............................................................. 318 CALL ................................................................................ 282 CALLW ............................................................................. 311 Capture (CCP Module) ..................................................... 141 Associated Registers ...............................................143 CCP Pin Configuration ............................................. 141 CCPRxH:CCPRxL Registers ................................... 141 Prescaler .................................................................. 141 Software Interrupt .................................................... 141 Timer1/Timer3 Mode Selection ................................ 141 Capture (ECCP Module) .................................................. 148 Capture/Compare/PWM (CCP) ........................................ 139 Capture Mode. See Capture. CCP Mode and Timer Resources ............................140 CCPRxH Register .................................................... 140 CCPRxL Register ..................................................... 140 Compare Mode. See Compare. Interaction of Two CCP Modules ............................. 140 Module Configuration ...............................................140 Clock Sources .................................................................... 28 Selecting the 31 kHz Source ...................................... 29 Selection Using OSCCON Register ........................... 29 CLRF ................................................................................ 283 CLRWDT .......................................................................... 283 Code Examples 16 x 16 Signed Multiply Routine ................................90 16 x 16 Unsigned Multiply Routine ............................90 8 x 8 Signed Multiply Routine .................................... 89 8 x 8 Unsigned Multiply Routine ................................89 Changing Between Capture Prescalers ................... 141 Computed GOTO Using an Offset Value ................... 56 Data EEPROM Read .................................................85 Data EEPROM Refresh Routine ................................86 Data EEPROM Write .................................................85 Erasing a Flash Program Memory Row ..................... 78 Fast Register Stack .................................................... 56 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 68 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ............................... 131 Initializing PORTA .................................................... 105 Initializing PORTB .................................................... 108 Initializing PORTC .................................................... 111 Initializing PORTD .................................................... 114 Initializing PORTE .................................................... 117 Loading the SSPBUF (SSPSR) Register ................. 164 Reading a Flash Program Memory Word .................. 77 Saving Status, WREG and BSR Registers in RAM ..................................... 103 Writing to Flash Program Memory ....................... 80–81 Code Protection ............................................................... 249 COMF ............................................................................... 284 Comparator ......................................................................233 Analog Input Connection Considerations ................. 237 Associated Registers ...............................................237 Configuration ............................................................ 234 Effects of a Reset ..................................................... 236 Interrupts .................................................................. 236 Operation ................................................................. 235 Operation During Sleep ........................................... 236 Outputs ....................................................................235 Reference ................................................................ 235 External Signal ................................................ 235 Internal Signal .................................................. 235 Response Time ........................................................ 235 Comparator Specifications ............................................... 338 Comparator Voltage Reference ....................................... 239 Accuracy and Error .................................................. 240 Associated Registers ............................................... 241 Configuring .............................................................. 239 Connection Considerations ...................................... 240 Effects of a Reset .................................................... 240 Operation During Sleep ........................................... 240 Compare (CCP Module) .................................................. 142 Associated Registers ............................................... 143 CCPRx Register ...................................................... 142 Pin Configuration ..................................................... 142 Software Interrupt .................................................... 142 Special Event Trigger .............................. 137, 142, 232 Timer1/Timer3 Mode Selection ................................ 142 Compare (ECCP Module) ................................................ 148 Special Event Trigger .............................................. 148 Computed GOTO ............................................................... 56 Configuration Bits ............................................................ 249 Configuration Register Protection .................................... 266 Context Saving During Interrupts ..................................... 103 Conversion Considerations .............................................. 372 CPFSEQ .......................................................................... 284 CPFSGT .......................................................................... 285 CPFSLT ........................................................................... 285 Crystal Oscillator/Ceramic Resonator ................................ 23 D Data Addressing Modes .................................................... 68 Comparing Addressing Modes with the Extended Instruction Set Enabled ..................... 71 Direct ......................................................................... 68 Indexed Literal Offset ................................................ 70 Instructions Affected .......................................... 70 Indirect ....................................................................... 68 Inherent and Literal .................................................... 68 Data EEPROM Code Protection ....................................................... 266 Data EEPROM Memory ..................................................... 83 Associated Registers ................................................. 87 EEADR Register ........................................................ 83 EECON1 and EECON2 Registers ............................. 83 Operation During Code-Protect ................................. 86 Protection Against Spurious Write ............................. 86 Reading ..................................................................... 85 Using ......................................................................... 86 Write Verify ................................................................ 85 Writing ....................................................................... 85 Data Memory ..................................................................... 59 Access Bank .............................................................. 62 and the Extended Instruction Set .............................. 70 Bank Select Register (BSR) ...................................... 59 General Purpose Registers ....................................... 62 Map for PIC18F2420/4420 ........................................ 60 Map for PIC18F2520/4520 ........................................ 61 Special Function Registers ........................................ 63 DAW ................................................................................ 286 DC and AC Characteristics Graphs and Tables .................................................. 361 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 377 PIC18F2420/2520/4420/4520 DC Characteristics ........................................................... 335 Power-Down and Supply Current ............................ 326 Supply Voltage ......................................................... 325 DCFSNZ .......................................................................... 287 DECF ............................................................................... 286 DECFSZ ........................................................................... 287 Demonstration Boards PICDEM 1 ................................................................ 320 PICDEM 17 .............................................................. 321 PICDEM 18R ........................................................... 321 PICDEM 2 Plus ........................................................ 320 PICDEM 3 ................................................................ 320 PICDEM 4 ................................................................ 320 PICDEM LIN ............................................................ 321 PICDEM USB ........................................................... 321 PICDEM.net Internet/Ethernet ................................. 320 Development Support ...................................................... 317 Device Differences ........................................................... 371 Device Overview .................................................................. 7 Details on Individual Family Members ......................... 8 Features (table) ............................................................ 9 New Core Features ...................................................... 7 Other Special Features ................................................ 8 Device Reset Timers .......................................................... 45 Oscillator Start-up Timer (OST) ................................. 45 PLL Lock Time-out ..................................................... 45 Power-up Timer (PWRT) ........................................... 45 Time-out Sequence .................................................... 45 Direct Addressing ............................................................... 69 E Effect on Standard PIC Instructions ................................. 314 Effects of Power Managed Modes on Various Clock Sources ............................................... 31 Electrical Characteristics .................................................. 323 Enhanced Capture/Compare/PWM (ECCP) .................... 147 Associated Registers ............................................... 160 Capture and Compare Modes .................................. 148 Capture Mode. See Capture (ECCP Module). Outputs and Configuration ....................................... 148 Pin Configurations for ECCP1 ................................. 148 PWM Mode. See PWM (ECCP Module). Standard PWM Mode ............................................... 148 Timer Resources ...................................................... 148 Enhanced PWM Mode. See PWM (ECCP Module). Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ................................................ 228 A/D Minimum Charging Time ................................... 228 Errata ................................................................................... 6 EUSART Asynchronous Mode ................................................ 211 12-Bit Break Transmit and Receive ................. 216 Associated Registers, Receive ........................ 214 Associated Registers, Transmit ....................... 212 Auto-Wake-up on Sync Break ......................... 214 Receiver ........................................................... 213 Setting up 9-Bit Mode with Address Detect ........................................ 213 Transmitter ....................................................... 211 Baud Rate Generator Operation in Power Managed Mode ................ 205 Baud Rate Generator (BRG) ................................... 205 Associated Registers ....................................... 206 Auto-Baud Rate Detect .................................... 209 Baud Rate Error, Calculating ........................... 206 Baud Rates, Asynchronous Modes ................. 207 High Baud Rate Select (BRGH Bit) ................. 205 Sampling ......................................................... 205 Synchronous Master Mode ...................................... 217 Associated Registers, Receive ........................ 219 Associated Registers, Transmit ....................... 218 Reception ........................................................ 219 Transmission ................................................... 217 Synchronous Slave Mode ........................................ 220 Associated Registers, Receive ........................ 221 Associated Registers, Transmit ....................... 220 Reception ........................................................ 221 Transmission ................................................... 220 Evaluation and Programming Tools ................................. 321 Extended Instruction Set ADDFSR .................................................................. 310 ADDULNK ............................................................... 310 and Using MPLAB Tools ......................................... 316 CALLW .................................................................... 311 Considerations for Use ............................................ 314 MOVSF .................................................................... 311 MOVSS .................................................................... 312 PUSHL ..................................................................... 312 SUBFSR .................................................................. 313 SUBULNK ................................................................ 313 Syntax ...................................................................... 309 External Clock Input ........................................................... 24 F Fail-Safe Clock Monitor ........................................... 249, 261 Exiting Operation ..................................................... 261 Interrupts in Power Managed Modes ....................... 262 POR or Wake from Sleep ........................................ 262 WDT During Oscillator Failure ................................. 261 Fast Register Stack ........................................................... 56 Firmware Instructions ...................................................... 267 Flash Program Memory ..................................................... 73 Associated Registers ................................................. 81 Control Registers ....................................................... 74 EECON1 and EECON2 ..................................... 74 TABLAT (Table Latch) Register ........................ 76 TBLPTR (Table Pointer) Register ...................... 76 Erase Sequence ........................................................ 78 Erasing ...................................................................... 78 Operation During Code-Protect ................................. 81 Reading ..................................................................... 77 Table Pointer Boundaries Based on Operation ....................... 76 Table Pointer Boundaries .......................................... 76 Table Reads and Table Writes .................................. 73 Write Sequence ......................................................... 79 Writing To .................................................................. 79 Protection Against Spurious Writes ................... 81 Unexpected Termination ................................... 81 Write Verify ........................................................ 81 FSCM. See Fail-Safe Clock Monitor. G General Call Address Support ......................................... 184 GOTO .............................................................................. 288 PIC18F2420/2520/4420/4520 DS39631B-page 378 Preliminary © 2007 Microchip Technology Inc. H Hardware Multiplier ............................................................ 89 Introduction ................................................................ 89 Operation ................................................................... 89 Performance Comparison .......................................... 89 High/Low-Voltage Detect .................................................243 Applications .............................................................. 246 Associated Registers ...............................................247 Characteristics ......................................................... 339 Current Consumption ...............................................245 Effects of a Reset ..................................................... 247 Operation ................................................................. 244 During Sleep .................................................... 247 Setup ........................................................................245 Start-up Time ........................................................... 245 Typical Application ...................................................246 HLVD. See High/Low-Voltage Detect. I I/O Ports ........................................................................... 105 I2C Mode (MSSP) Acknowledge Sequence Timing ............................... 194 Baud Rate Generator ...............................................187 Bus Collision During a Repeated Start Condition .................. 198 During a Stop Condition ................................... 199 Clock Arbitration ....................................................... 188 Clock Stretching ....................................................... 180 10-Bit Slave Receive Mode (SEN = 1) ............. 180 10-Bit Slave Transmit Mode ............................. 180 7-Bit Slave Receive Mode (SEN = 1) ............... 180 7-Bit Slave Transmit Mode ............................... 180 Clock Synchronization and the CKP Bit (SEN = 1) .. 181 Effects of a Reset ..................................................... 195 General Call Address Support ................................. 184 I2C Clock Rate w/BRG ............................................. 187 Master Mode ............................................................ 185 Operation ......................................................... 186 Reception ......................................................... 191 Repeated Start Condition Timing ..................... 190 Start Condition Timing ..................................... 189 Transmission .................................................... 191 Multi-Master Communication, Bus Collision and Arbitration .................................................. 195 Multi-Master Mode ...................................................195 Operation ................................................................. 174 Read/Write Bit Information (R/W Bit) ............... 174, 175 Registers .................................................................. 170 Serial Clock (RC3/SCK/SCL) ................................... 175 Slave Mode .............................................................. 174 Addressing ....................................................... 174 Reception ......................................................... 175 Transmission .................................................... 175 Sleep Operation ....................................................... 195 Stop Condition Timing .............................................. 194 ID Locations ............................................................. 249, 266 INCF ................................................................................. 288 INCFSZ ............................................................................ 289 In-Circuit Debugger .......................................................... 266 In-Circuit Serial Programming (ICSP) ...................... 249, 266 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 314 Indexed Literal Offset Mode ............................................. 314 Indirect Addressing ............................................................ 69 INFSNZ ............................................................................ 289 Initialization Conditions for all Registers ...................... 49–52 Instruction Cycle ................................................................ 57 Clocking Scheme ....................................................... 57 Instruction Flow/Pipelining ................................................. 57 Instruction Set .................................................................. 267 ADDLW .................................................................... 273 ADDWF .................................................................... 273 ADDWF (Indexed Literal Offset Mode) .................... 315 ADDWFC ................................................................. 274 ANDLW .................................................................... 274 ANDWF .................................................................... 275 BC ............................................................................ 275 BCF ......................................................................... 276 BN ............................................................................ 276 BNC ......................................................................... 277 BNN ......................................................................... 277 BNOV ...................................................................... 278 BNZ ......................................................................... 278 BOV ......................................................................... 281 BRA ......................................................................... 279 BSF .......................................................................... 279 BSF (Indexed Literal Offset Mode) .......................... 315 BTFSC ..................................................................... 280 BTFSS ..................................................................... 280 BTG ......................................................................... 281 BZ ............................................................................ 282 CALL ........................................................................ 282 CLRF ....................................................................... 283 CLRWDT ................................................................. 283 COMF ...................................................................... 284 CPFSEQ .................................................................. 284 CPFSGT .................................................................. 285 CPFSLT ................................................................... 285 DAW ........................................................................ 286 DCFSNZ .................................................................. 287 DECF ....................................................................... 286 DECFSZ .................................................................. 287 Extended Instruction Set ......................................... 309 General Format ........................................................ 269 GOTO ...................................................................... 288 INCF ........................................................................ 288 INCFSZ .................................................................... 289 INFSNZ .................................................................... 289 IORLW ..................................................................... 290 IORWF ..................................................................... 290 LFSR ....................................................................... 291 MOVF ...................................................................... 291 MOVFF .................................................................... 292 MOVLB .................................................................... 292 MOVLW ................................................................... 293 MOVWF ................................................................... 293 MULLW .................................................................... 294 MULWF .................................................................... 294 NEGF ....................................................................... 295 NOP ......................................................................... 295 Opcode Field Descriptions ....................................... 268 POP ......................................................................... 296 PUSH ....................................................................... 296 RCALL ..................................................................... 297 RESET ..................................................................... 297 RETFIE .................................................................... 298 RETLW .................................................................... 298 RETURN .................................................................. 299 RLCF ....................................................................... 299 RLNCF ..................................................................... 300 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 379 PIC18F2420/2520/4420/4520 RRCF ....................................................................... 300 RRNCF .................................................................... 301 SETF ........................................................................ 301 SETF (Indexed Literal Offset Mode) ........................ 315 SLEEP ..................................................................... 302 SUBFWB .................................................................. 302 SUBLW .................................................................... 303 SUBWF .................................................................... 303 SUBWFB .................................................................. 304 SWAPF .................................................................... 304 TBLRD ..................................................................... 305 TBLWT ..................................................................... 306 TSTFSZ ................................................................... 307 XORLW .................................................................... 307 XORWF .................................................................... 308 INTCON Registers ....................................................... 93–95 Inter-Integrated Circuit. See I2C. Internal Oscillator Block ..................................................... 26 Adjustment ................................................................. 26 INTIO Modes .............................................................. 26 INTOSC Frequency Drift ............................................ 26 INTOSC Output Frequency ........................................ 26 OSCTUNE Register ................................................... 26 PLL in INTOSC Modes .............................................. 26 Internal RC Oscillator Use with WDT .......................................................... 258 Interrupt Sources ............................................................. 249 A/D Conversion Complete ....................................... 227 Capture Complete (CCP) ......................................... 141 Compare Complete (CCP) ....................................... 142 Interrupt-on-Change (RB7:RB4) .............................. 108 INTn Pin ................................................................... 103 PORTB, Interrupt-on-Change .................................. 103 TMR0 ....................................................................... 103 TMR0 Overflow ........................................................ 125 TMR1 Overflow ........................................................ 127 TMR2 to PR2 Match (PWM) ............................ 144, 149 TMR3 Overflow ................................................ 135, 137 Interrupts ............................................................................ 91 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ......................................................... 108 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 290 IORWF ............................................................................. 290 IPR Registers ................................................................... 100 L LFSR ................................................................................ 291 Low-Voltage ICSP Programming. See Single-Supply ICSP Programming M Master Clear (MCLR) ......................................................... 43 Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ......................................................... 53 Data Memory ............................................................. 59 Program Memory ....................................................... 53 Memory Programming Requirements .............................. 337 Migration from Baseline to Enhanced Devices ................ 372 Migration from High-End to Enhanced Devices ............... 373 Migration from Mid-Range to Enhanced Devices ............ 373 MOVF ............................................................................... 291 MOVFF ............................................................................ 292 MOVLB ............................................................................ 292 MOVLW ........................................................................... 293 MOVSF ............................................................................ 311 MOVSS ............................................................................ 312 MOVWF ........................................................................... 293 MPLAB ASM30 Assembler, Linker, Librarian .................. 318 MPLAB ICD 2 In-Circuit Debugger .................................. 319 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 319 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator ................................... 319 MPLAB Integrated Development Environment Software ............................................. 317 MPLAB PM3 Device Programmer ................................... 319 MPLINK Object Linker/MPLIB Object Librarian ............... 318 MSSP ACK Pulse ....................................................... 174, 175 Control Registers (general) ..................................... 161 I2C Mode. See I2C Mode. Module Overview ..................................................... 161 SPI Master/Slave Connection .................................. 165 SPI Mode. See SPI Mode. SSPBUF Register .................................................... 166 SSPSR Register ...................................................... 166 MULLW ............................................................................ 294 MULWF ............................................................................ 294 N NEGF ............................................................................... 295 NOP ................................................................................. 295 O Oscillator Configuration ..................................................... 23 EC .............................................................................. 23 ECIO .......................................................................... 23 HS .............................................................................. 23 HSPLL ....................................................................... 23 Internal Oscillator Block ............................................. 26 INTIO1 ....................................................................... 23 INTIO2 ....................................................................... 23 LP .............................................................................. 23 RC ............................................................................. 23 RCIO .......................................................................... 23 XT .............................................................................. 23 Oscillator Selection .......................................................... 249 Oscillator Start-up Timer (OST) ................................... 31, 45 Oscillator Switching ........................................................... 28 Oscillator Transitions ......................................................... 29 Oscillator, Timer1 ..................................................... 127, 137 Oscillator, Timer3 ............................................................. 135 P Packaging Information ..................................................... 363 Marking .................................................................... 363 Parallel Slave Port (PSP) ......................................... 114, 120 Associated Registers ............................................... 121 CS (Chip Select) ...................................................... 120 PORTD .................................................................... 120 RD (Read Input) ...................................................... 120 Select (PSPMODE Bit) .................................... 114, 120 WR (Write Input) ...................................................... 120 PICkit 1 Flash Starter Kit ................................................. 321 PICSTART Plus Development Programmer .................... 320 PIE Registers ..................................................................... 98 PIC18F2420/2520/4420/4520 DS39631B-page 380 Preliminary © 2007 Microchip Technology Inc. Pin Functions MCLR/VPP/RE3 .................................................... 12, 16 OSC1/CLKI/RA7 .................................................. 12, 16 OSC2/CLKO/RA6 ................................................ 12, 16 RA0/AN0 .............................................................. 13, 17 RA1/AN1 .............................................................. 13, 17 RA2/AN2/VREF-/CVREF ........................................ 13, 17 RA3/AN3/VREF+ ................................................... 13, 17 RA4/T0CKI/C1OUT .............................................. 13, 17 RA5/AN4/SS/HLVDIN/C2OUT ............................. 13, 17 RB0/INT0/FLT0/AN12 .......................................... 14, 18 RB1/INT1/AN10 ................................................... 14, 18 RB2/INT2/AN8 ..................................................... 14, 18 RB3/AN9/CCP2 ................................................... 14, 18 RB4/KBI0/AN11 ................................................... 14, 18 RB5/KBI1/PGM .................................................... 14, 18 RB6/KBI2/PGC .................................................... 14, 18 RB7/KBI3/PGD .................................................... 14, 18 RC0/T1OSO/T13CKI ........................................... 15, 19 RC1/T1OSI/CCP2 ................................................ 15, 19 RC2/CCP1 ................................................................. 15 RC2/CCP1/P1A ......................................................... 19 RC3/SCK/SCL ..................................................... 15, 19 RC4/SDI/SDA ...................................................... 15, 19 RC5/SDO ............................................................. 15, 19 RC6/TX/CK .......................................................... 15, 19 RC7/RX/DT .......................................................... 15, 19 RD0/PSP0 .................................................................. 20 RD1/PSP1 .................................................................. 20 RD2/PSP2 .................................................................. 20 RD3/PSP3 .................................................................. 20 RD4/PSP4 .................................................................. 20 RD5/PSP5/P1B .......................................................... 20 RD6/PSP6/P1C .......................................................... 20 RD7/PSP7/P1D .......................................................... 20 RE0/RD/AN5 .............................................................. 21 RE1/WR/AN6 ............................................................. 21 RE2/CS/AN7 .............................................................. 21 VDD ....................................................................... 15, 21 VSS ....................................................................... 15, 21 Pinout I/O Descriptions PIC18F2420/2520 ...................................................... 12 PIC18F4420/4520 ...................................................... 16 PIR Registers ..................................................................... 96 PLL Frequency Multiplier ...................................................25 HSPLL Oscillator Mode .............................................. 25 Use with INTOSC ....................................................... 25 POP .................................................................................. 296 POR. See Power-on Reset. PORTA Associated Registers ...............................................107 LATA Register .......................................................... 105 PORTA Register ...................................................... 105 TRISA Register ........................................................ 105 PORTB Associated Registers ...............................................110 LATB Register .......................................................... 108 PORTB Register ...................................................... 108 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ......................................................... 108 TRISB Register ........................................................ 108 PORTC Associated Registers ............................................... 113 LATC Register ......................................................... 111 PORTC Register ...................................................... 111 RC3/SCK/SCL Pin ................................................... 175 TRISC Register ........................................................ 111 PORTD Associated Registers ............................................... 116 LATD Register ......................................................... 114 Parallel Slave Port (PSP) Function .......................... 114 PORTD Register ...................................................... 114 TRISD Register ........................................................ 114 PORTE Associated Registers ............................................... 119 LATE Register ......................................................... 117 PORTE Register ...................................................... 117 PSP Mode Select (PSPMODE Bit) .......................... 114 TRISE Register ........................................................ 117 Power Managed Modes ..................................................... 33 and A/D Operation ................................................... 230 and EUSART Operation .......................................... 205 and Multiple Sleep Commands .................................. 34 and PWM Operation ................................................ 159 and SPI Operation ................................................... 169 Clock Transitions and Status Indicators .................... 34 Effects on Clock Sources ........................................... 31 Entering ..................................................................... 33 Exiting Idle and Sleep Modes .................................... 39 by Interrupt ........................................................ 39 by Reset ............................................................ 39 by WDT Time-out .............................................. 39 Without a Start-up Delay ................................... 40 Idle Modes ................................................................. 37 PRI_IDLE ........................................................... 38 RC_IDLE ........................................................... 39 SEC_IDLE ......................................................... 38 Run Modes ................................................................ 34 PRI_RUN ........................................................... 34 RC_RUN ............................................................ 35 SEC_RUN ......................................................... 34 Selecting .................................................................... 33 Sleep Mode ............................................................... 37 Summary (table) ........................................................ 33 Power-on Reset (POR) ...................................................... 43 Power-up Timer (PWRT) ........................................... 45 Time-out Sequence ................................................... 45 Power-up Delays ............................................................... 31 Power-up Timer (PWRT) ................................................... 31 Prescaler Timer2 ..................................................................... 150 Prescaler, Timer0 ............................................................ 125 Prescaler, Timer2 ............................................................ 145 PRI_IDLE Mode ................................................................. 38 PRI_RUN Mode ................................................................. 34 PRO MATE II Universal Device Programmer .................. 319 Program Counter ............................................................... 54 PCL, PCH and PCU Registers .................................. 54 PCLATH and PCLATU Registers .............................. 54 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 381 PIC18F2420/2520/4420/4520 Program Memory and Extended Instruction Set ..................................... 72 Code Protection ....................................................... 264 Instructions ................................................................. 58 Two-Word .......................................................... 58 Interrupt Vector .......................................................... 53 Look-up Tables .......................................................... 56 Map and Stack (diagram) ........................................... 53 Reset Vector .............................................................. 53 Program Verification and Code Protection ....................... 263 Associated Registers ............................................... 263 Programming, Device Instructions ................................... 267 PSP. See Parallel Slave Port. Pulse-Width Modulation. See PWM (CCP Module) and PWM (ECCP Module). PUSH ............................................................................... 296 PUSH and POP Instructions .............................................. 55 PUSHL ............................................................................. 312 PWM (CCP Module) Associated Registers ............................................... 146 Auto-Shutdown (CCP1 only) .................................... 145 CCPR1H:CCPR1L Registers ................................... 149 Duty Cycle ........................................................ 144, 150 Example Frequencies/Resolutions .................. 145, 150 Period ............................................................... 144, 149 Setup for PWM Operation ........................................ 145 TMR2 to PR2 Match ........................................ 144, 149 PWM (ECCP Module) ...................................................... 149 Direction Change in Full-Bridge Output Mode .................................................... 154 Effects of a Reset ..................................................... 159 Enhanced PWM Auto-Shutdown ............................. 156 Full-Bridge Application Example .............................. 154 Full-Bridge Mode ...................................................... 153 Half-Bridge Mode ..................................................... 152 Half-Bridge Output Mode Applications Example ...................................... 152 Operation in Power Managed Modes ...................... 159 Operation with Fail-Safe Clock Monitor ................... 159 Output Configurations .............................................. 150 Output Relationships (Active-High) .......................... 151 Output Relationships (Active-Low) ........................... 151 Programmable Dead-Band Delay ............................ 156 Setup for PWM Operation ........................................ 159 Start-up Considerations ........................................... 158 Q Q Clock .................................................................... 145, 150 R RAM. See Data Memory. RBIF Bit ............................................................................ 108 RC Oscillator ...................................................................... 25 RCIO Oscillator Mode ................................................ 25 RC_IDLE Mode .................................................................. 39 RC_RUN Mode .................................................................. 35 RCALL ............................................................................. 297 RCON Register Bit Status During Initialization .................................... 48 Register File ....................................................................... 62 Register File Summary ................................................ 64–66 Registers ADCON0 (A/D Control 0) ......................................... 223 ADCON1 (A/D Control 1) ......................................... 224 ADCON2 (A/D Control 2) ......................................... 225 BAUDCON (Baud Rate Control) .............................. 204 CCP1CON (Enhanced Capture/Compare/PWM Control 1) ................. 147 CCPxCON (Standard Capture/Compare/PWM Control) .................... 139 CMCON (Comparator Control) ................................ 233 CONFIG1H (Configuration 1 High) .......................... 250 CONFIG2H (Configuration 2 High) .......................... 252 CONFIG2L (Configuration 2 Low) ........................... 251 CONFIG3H (Configuration 3 High) .......................... 253 CONFIG4L (Configuration 4 Low) ........................... 253 CONFIG5H (Configuration 5 High) .......................... 254 CONFIG5L (Configuration 5 Low) ........................... 254 CONFIG6H (Configuration 6 High) .......................... 255 CONFIG6L (Configuration 6 Low) ........................... 255 CONFIG7H (Configuration 7 High) .......................... 256 CONFIG7L (Configuration 7 Low) ........................... 256 CVRCON (Comparator Voltage Reference Control) .......................................... 239 DEVID1 (Device ID 1) .............................................. 257 DEVID2 (Device ID 2) .............................................. 257 ECCP1AS (ECCP Auto-Shutdown Control) ............ 157 EECON1 (Data EEPROM Control 1) ................... 75, 84 HLVDCON (High/Low-Voltage Detect Control) ....... 243 INTCON (Interrupt Control) ....................................... 93 INTCON2 (Interrupt Control 2) .................................. 94 INTCON3 (Interrupt Control 3) .................................. 95 IPR1 (Peripheral Interrupt Priority 1) ....................... 100 IPR2 (Peripheral Interrupt Priority 2) ....................... 101 OSCCON (Oscillator Control) .................................... 30 OSCTUNE (Oscillator Tuning) ................................... 27 PIE1 (Peripheral Interrupt Enable 1) ......................... 98 PIE2 (Peripheral Interrupt Enable 2) ......................... 99 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 96 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 97 PWM1CON (PWM Configuration) ........................... 156 RCON (Reset Control) ....................................... 42, 102 RCSTA (Receive Status and Control) ..................... 203 SSPCON1 (MSSP Control 1, I2C Mode) ................. 172 SSPCON1 (MSSP Control 1, SPI Mode) ................ 163 SSPCON2 (MSSP Control 2, I2C Mode) ................. 173 SSPSTAT (MSSP Status, I2C Mode) ...................... 171 SSPSTAT (MSSP Status, SPI Mode) ...................... 162 Status ........................................................................ 67 STKPTR (Stack Pointer) ............................................ 55 T0CON (Timer0 Control) ......................................... 123 T1CON (Timer1 Control) ......................................... 127 T2CON (Timer2 Control) ......................................... 133 T3CON (Timer3 Control) ......................................... 135 TRISE (PORTE/PSP Control) ................................. 118 TXSTA (Transmit Status and Control) ..................... 202 WDTCON (Watchdog Timer Control) ...................... 259 RESET ............................................................................. 297 Reset State of Registers .................................................... 48 Resets ....................................................................... 41, 249 Brown-out Reset (BOR) ........................................... 249 Oscillator Start-up Timer (OST) ............................... 249 Power-on Reset (POR) ............................................ 249 Power-up Timer (PWRT) ......................................... 249 PIC18F2420/2520/4420/4520 DS39631B-page 382 Preliminary © 2007 Microchip Technology Inc. RETFIE ............................................................................ 298 RETLW ............................................................................. 298 RETURN .......................................................................... 299 Return Address Stack ........................................................ 54 Return Stack Pointer (STKPTR) ........................................ 55 Revision History ............................................................... 371 RLCF ................................................................................ 299 RLNCF ............................................................................. 300 RRCF ............................................................................... 300 RRNCF ............................................................................. 301 S SCK .................................................................................. 161 SDI ................................................................................... 161 SDO ................................................................................. 161 SEC_IDLE Mode ................................................................ 38 SEC_RUN Mode ................................................................ 34 Serial Clock, SCK ............................................................. 161 Serial Data In (SDI) .......................................................... 161 Serial Data Out (SDO) ..................................................... 161 Serial Peripheral Interface. See SPI Mode. SETF ................................................................................ 301 Single-Supply ICSP Programming. Slave Select (SS) ............................................................. 161 Slave Select Synchronization ........................................... 167 SLEEP .............................................................................. 302 Sleep OSC1 and OSC2 Pin States ...................................... 31 Sleep Mode ........................................................................37 Software Simulator (MPLAB SIM) .................................... 318 Software Simulator (MPLAB SIM30) ................................ 318 Special Event Trigger. See Compare (ECCP Mode). Special Event Trigger. See Compare (ECCP Module). Special Features of the CPU ............................................ 249 Special Function Registers ................................................ 63 Map ............................................................................ 63 SPI Mode (MSSP) Associated Registers ...............................................169 Bus Mode Compatibility ........................................... 169 Effects of a Reset ..................................................... 169 Enabling SPI I/O ...................................................... 165 Master Mode ............................................................ 166 Master/Slave Connection ......................................... 165 Operation ................................................................. 164 Operation in Power Managed Modes ...................... 169 Serial Clock .............................................................. 161 Serial Data In ........................................................... 161 Serial Data Out ........................................................ 161 Slave Mode .............................................................. 167 Slave Select ............................................................. 161 Slave Select Synchronization .................................. 167 SPI Clock ................................................................. 166 Typical Connection .................................................. 165 SS .................................................................................... 161 SSPOV ............................................................................. 191 SSPOV Status Flag .......................................................... 191 SSPSTAT Register R/W Bit ............................................................. 174, 175 Stack Full/Underflow Resets .............................................. 56 Standard Instructions ....................................................... 267 SUBFSR ........................................................................... 313 SUBFWB .......................................................................... 302 SUBLW ............................................................................ 303 SUBULNK ........................................................................ 313 SUBWF ............................................................................ 303 SUBWFB ......................................................................... 304 SWAPF ............................................................................ 304 T Table Pointer Operations (table) ........................................ 76 Table Reads/Table Writes ................................................. 56 TBLRD ............................................................................. 305 TBLWT ............................................................................. 306 Time-out in Various Situations (table) ................................ 45 Timer0 .............................................................................. 123 Associated Registers ............................................... 125 Operation ................................................................. 124 Overflow Interrupt .................................................... 125 Prescaler ................................................................. 125 Prescaler Assignment (PSA Bit) .............................. 125 Prescaler Select (T0PS2:T0PS0 Bits) ..................... 125 Prescaler. See Prescaler, Timer0. Reads and Writes in 16-Bit Mode ............................ 124 Source Edge Select (T0SE Bit) ............................... 124 Source Select (T0CS Bit) ......................................... 124 Switching Prescaler Assignment ............................. 125 Timer1 .............................................................................. 127 16-Bit Read/Write Mode .......................................... 129 Associated Registers ............................................... 131 Interrupt ................................................................... 130 Operation ................................................................. 128 Oscillator .......................................................... 127, 129 Oscillator Layout Considerations ............................. 130 Overflow Interrupt .................................................... 127 Resetting, Using the CCP Special Event Trigger ...................................... 130 Special Event Trigger (ECCP) ................................. 148 TMR1H Register ...................................................... 127 TMR1L Register ....................................................... 127 Use as a Real-Time Clock ....................................... 130 Timer2 .............................................................................. 133 Associated Registers ............................................... 134 Interrupt ................................................................... 134 Operation ................................................................. 133 Output ...................................................................... 134 PR2 Register ................................................... 144, 149 TMR2 to PR2 Match Interrupt .......................... 144, 149 Timer3 .............................................................................. 135 16-Bit Read/Write Mode .......................................... 137 Associated Registers ............................................... 137 Operation ................................................................. 136 Oscillator .......................................................... 135, 137 Overflow Interrupt ............................................ 135, 137 Special Event Trigger (CCP) ................................... 137 TMR3H Register ...................................................... 135 TMR3L Register ....................................................... 135 Timing Diagrams A/D Conversion ........................................................ 359 Acknowledge Sequence .......................................... 194 Asynchronous Reception ......................................... 214 Asynchronous Transmission .................................... 212 Asynchronous Transmission (Back to Back) ........... 212 Automatic Baud Rate Calculation ............................ 210 Auto-Wake-up Bit (WUE) During Normal Operation ............................................ 215 Auto-Wake-up Bit (WUE) During Sleep ................... 215 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 383 PIC18F2420/2520/4420/4520 Baud Rate Generator with Clock Arbitration ............ 188 BRG Overflow Sequence ......................................... 210 BRG Reset Due to SDA Arbitration During Start Condition ..................................... 197 Brown-out Reset (BOR) ........................................... 345 Bus Collision During a Repeated Start Condition (Case 1) .................................. 198 Bus Collision During a Repeated Start Condition (Case 2) .................................. 198 Bus Collision During a Start Condition (SCL = 0) ......................................................... 197 Bus Collision During a Stop Condition (Case 1) ........................................................... 199 Bus Collision During a Stop Condition (Case 2) ........................................................... 199 Bus Collision During Start Condition (SDA only) ....................................................... 196 Bus Collision for Transmit and Acknowledge ........... 195 Capture/Compare/PWM (CCP) ................................ 347 CLKO and I/O .......................................................... 344 Clock Synchronization ............................................. 181 Clock/Instruction Cycle .............................................. 57 Example SPI Master Mode (CKE = 0) ..................... 349 Example SPI Master Mode (CKE = 1) ..................... 350 Example SPI Slave Mode (CKE = 0) ....................... 351 Example SPI Slave Mode (CKE = 1) ....................... 352 External Clock (All Modes except PLL) .................... 342 Fail-Safe Clock Monitor (FSCM) .............................. 262 First Start Bit Timing ................................................ 189 Full-Bridge PWM Output .......................................... 153 Half-Bridge PWM Output ......................................... 152 High/Low-Voltage Detect Characteristics ................ 339 High/Low-Voltage Detect Operation (VDIRMAG = 0) ................................................ 245 High/Low-Voltage Detect Operation (VDIRMAG = 1) ................................................ 246 I2C Bus Data ............................................................ 353 I2C Bus Start/Stop Bits ............................................. 353 I2C Master Mode (7 or 10-Bit Transmission) ........... 192 I2C Master Mode (7-Bit Reception) .......................... 193 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 178 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 183 I2C Slave Mode (10-Bit Transmission) ..................... 179 I2C Slave Mode (7-bit Reception, SEN = 0) ............. 176 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 182 I2C Slave Mode (7-Bit Transmission) ....................... 177 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 184 I2C Stop Condition Receive or Transmit Mode ................................................. 194 Master SSP I2C Bus Data ........................................ 355 Master SSP I2C Bus Start/Stop Bits ........................ 355 Parallel Slave Port (PIC18F4420/4520) ................... 348 Parallel Slave Port (PSP) Read ............................... 121 Parallel Slave Port (PSP) Write ............................... 121 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 158 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 158 PWM Direction Change ........................................... 155 PWM Direction Change at Near 100% Duty Cycle ............................................. 155 PWM Output ............................................................ 144 Repeat Start Condition ............................................ 190 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST), Power-up Timer (PWRT) ................................. 345 Send Break Character Sequence ............................ 216 Slave Synchronization ............................................. 167 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 47 SPI Mode (Master Mode) ........................................ 166 SPI Mode (Slave Mode, CKE = 0) ........................... 168 SPI Mode (Slave Mode, CKE = 1) ........................... 168 Synchronous Reception (Master Mode, SREN) ..................................... 219 Synchronous Transmission ..................................... 217 Synchronous Transmission (Through TXEN) .......... 218 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) .......................................... 47 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 1) ...................... 46 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 2) ...................... 46 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ........... 46 Timer0 and Timer1 External Clock .......................... 346 Transition for Entry to SEC_RUN Mode .................... 35 Transition for Entry to Sleep Mode ............................ 37 Transition for Two-Speed Start-up (INTOSC to HSPLL) ........................................ 260 Transition for Wake from Sleep (HSPLL) .................. 37 Transition from RC_RUN Mode to PRI_RUN Mode ................................................. 36 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) .................................. 35 Transition Timing for Entry to Idle Mode .................... 38 Transition Timing for Wake from Idle to Run Mode ............................................... 38 Transition to RC_RUN Mode ..................................... 36 USART Synchronous Receive (Master/Slave) ................................................. 357 USART Synchronous Transmission (Master/Slave) ................................................. 357 Timing Diagrams and Specifications ............................... 342 A/D Conversion Requirements ................................ 359 Capture/Compare/PWM Requirements ................... 347 CLKO and I/O Requirements ................................... 344 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 349 Example SPI Mode Requirements (Master Mode, CKE = 1) .................................. 350 Example SPI Mode Requirements (Slave Mode, CKE = 0) .................................... 351 Example SPI Mode Requirements (Slave Mode, CKE = 1) .................................... 352 External Clock Requirements .................................. 342 I2C Bus Data Requirements (Slave Mode) .............. 354 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................................... 353 Master SSP I2C Bus Data Requirements ................ 356 Master SSP I2C Bus Start/Stop Bits Requirements .................................................. 355 Parallel Slave Port Requirements (PIC18F4420/4520) ......................................... 348 PIC18F2420/2520/4420/4520 DS39631B-page 384 Preliminary © 2007 Microchip Technology Inc. PLL Clock ................................................................. 343 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ...................................................345 Timer0 and Timer1 External Clock Requirements ......................................... 346 USART Synchronous Receive Requirements .........357 USART Synchronous Transmission Requirements ...................................................357 Top-of-Stack Access .......................................................... 54 TRISE Register PSPMODE Bit .......................................................... 114 TSTFSZ ............................................................................ 307 Two-Speed Start-up ................................................. 249, 260 Two-Word Instructions Example Cases .......................................................... 58 TXSTA Register BRGH Bit ................................................................. 205 V Voltage Reference Specifications .................................... 338 W Watchdog Timer (WDT) ........................................... 249, 258 Associated Registers ............................................... 259 Control Register ....................................................... 258 During Oscillator Failure .......................................... 261 Programming Considerations .................................. 258 WCOL ...................................................... 189, 190, 191, 194 WCOL Status Flag ................................... 189, 190, 191, 194 WWW, On-Line Support ...................................................... 6 X XORLW ............................................................................ 307 XORWF ........................................................................... 308 © 2007 Microchip Technology Inc. Preliminary DS39631B-page 385 PIC18F2420/2520/4420/4520 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support • Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC18F2420/2520/4420/4520 DS39631B-page 386 Preliminary © 2007 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: FAX: (______) _________ - _________ PIC18F2420/2520/4420/4520 DS39631B 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? © 2007 Microchip Technology Inc. Preliminary DS39631B-page 387 PIC18F2420/2520/4420/4520 PIC18F2420/2520/4420/4520 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Temperature Package Pattern Range Device Device PIC18F2420/2520(1), PIC18F4420/4520(1), PIC18F2420/2520T(2), PIC18F4420/4520T(2); VDD range 4.2V to 5.5V PIC18LF2420/2520(1), PIC18LF4420/4520(1), PIC18LF2420/2520T(2), PIC18LF4420/4520T(2); VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package PT = TQFP (Thin Quad Flatpack) SO = SOIC SP = Skinny Plastic DIP P = PDIP ML = QFN Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) Examples: a) PIC18LF4520-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. b) PIC18LF2420-I/SO = Industrial temp., SOIC package, Extended VDD limits. c) PIC18F4420-I/P = Industrial temp., PDIP package, normal VDD limits. Note 1: F = Standard Voltage Range LF = Wide Voltage Range 2: T = in tape and reel TQFP packages only. DS39631B-page 388 © 2007 Microchip Technology Inc. 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A high efficiency 1.5A, 0.2Ω switch is included on the die together with all the control circuitry required to complete a high frequency, current-mode switching regulator. Current-mode control provides fast transient response and excellent loop stability. New design techniques achieve high efficiency at high switching frequencies over a wide operating voltage range. A low dropout internal regulator maintains consistent performance over a wide range of inputs from 24V systems to Li-Ion batteries. An operating supply current of 1mA maintains high efficiency, especially at lower output currents. Shutdown reduces quiescent current to 6μA. Maximum switch current remains constant at all duty cycles. Synchronization allows an external logic level signal to increase the internal oscillator from 1.5MHz to 2MHz. The LT1961 is available in an exposed pad, 8-pin MSOP package. Full cycle-by-cycle switch current limit protection and thermal shutdown are provided. High frequency operation allows the reduction of input and output filtering components and permits the use of chip inductors. ■ DSL Modems ■ Portable Computers ■ Battery-Powered Systems ■ Distributed Power Efficiency vs Load Current 5V to 12V Boost Converter LT1961 VIN VOUT 12V 0.5A* VIN 5V 1961 TA01 6800pF 100pF 6.8k 10k 1% 90.9k UPS120 10μF CERAMIC 2.2μF CERAMIC VSW SHDN FB OPEN OR HIGH = ON SYNC GND VC *MAXIMUM OUTPUT CURRENT IS SUBJECT TO THERMAL DERATING. 6.8μH 2 6 8 3,4 7 5 1 LOAD CURRENT (mA) 0 EFFICIENCY (%) 90 85 80 75 70 65 60 100 200 300 400 1961 TA01a 500 VIN = 5V VOUT = 12V , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Patent Pending 2 LT1961 1961fa ABSOLUTE MAXIMUM RATINGS W W W U Input Voltage .......................................................... 25V Switch Voltage ......................................................... 35V SHDN Pin ............................................................... 25V FB Pin Current ....................................................... 1mA SYNC Pin Current .................................................. 1mA Operating Junction Temperature Range (Note 2) LT1961E, LT1961I ........................... – 40°C to 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C (Note 1) TJMAX = 125°C, θJA = 50°C/W GROUND PAD CONNECTED TO LARGE COPPER AREA 1234 VIN SW GND GND 8765 SYNC VC FB SHDN TOP VIEW MS8E PACKAGE 8-LEAD PLASTIC MSOP PI CO FIGURATIOU U U PARAMETER CONDITION MIN TYP MAX UNITS Recommended Operating Voltage ● 3 25 V Maximum Switch Current Limit ● 1.5 2 3 A Oscillator Frequency 3.3V < VIN < 25V ● 1 1.5 MHz Switch On Voltage Drop ISW = 1.5A ● 310 500 mV VIN Undervoltage Lockout (Note 3) ● 2.47 2.6 2.73 V VIN Supply Current ISW = 0A ● 0.9 1.3 mA VIN Supply Current/ISW ISW = 1.5A 27 mA/A Shutdown Supply Current VSHDN = 0V, VIN = 25V, VSW = 25V 6 20 μA ● 45 μA Feedback Voltage 3V < VIN < 25V, 0.4V < VC < 0.9V 1.182 1.2 1.218 V ● 1.176 1.224 V ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VC = 0.8V, SHDN, SYNC and switch open unless otherwise noted. LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT1961EMS8E#PBF LT1961EMS8E#TRPBF LTQY 8-Lead Plastic MSOP –40°C to 125°C LT1961IMS8E#PBF LT1961IMS8E#TRPBF LTQY 8-Lead Plastic MSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT1961EMS8E LT1961EMS8E#TR LTQY 8-Lead Plastic MSOP –40°C to 125°C LT1961IMS8E LT1961IMS8E#TR LTQY 8-Lead Plastic MSOP –40°C to 125°C ORDER IUFORWATIOU Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3 LT1961 1961fa ELECTRICAL CHARACTERISTICS PARAMETER CONDITION MIN TYP MAX UNITS FB Input Current ● 0 –0.2 –0.4 μA FB to VC Voltage Gain 0.4V < VC < 0.9V 150 350 FB to VC Transconductance ΔIVC = ±10μA ● 500 850 1300 μMho VC Pin Source Current VFB = 1V ● – 85 –120 –165 μA VC Pin Sink Current VFB = 1.4V ● 70 110 165 μA VC Pin to Switch Current Transconductance 2.4 A/V VC Pin Minimum Switching Threshold Duty Cycle = 0% 0.3 V VC Pin 1.5A ISW Threshold 0.9 V Maximum Switch Duty Cycle VC = 1.2V, ISW = 100mA ● 80 90 % VC = 1.2V, ISW = 1A, 25°C ≤ TA ≤ 125°C 75 80 % VC = 1.2V, ISW = 1A, TA ≤ 25°C 70 75 % SHDN Threshold Voltage ● 1.28 1.35 1.42 V SHDN Input Current (Shutting Down) SHDN = 60mV Above Threshold ● –7 –10 –13 μA SHDN Threshold Current Hysteresis SHDN = 100mV Below Threshold 4 7 10 μA SYNC Threshold Voltage 1.5 2.2 V SYNC Input Frequency 1.5 2 MHz SYNC Pin Resistance ISYNC = 1mA 20 kΩ The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VC = 0.8V, SHDN, SYNC and switch open unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT1961E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT1961I is guaranteed over the – 40ºC to 125ºC operating junction temperature range. Note 3: Minimum input voltage is defined as the voltage where the internal regulator enters lockout. Actual minimum input voltage to maintain a regulated output will depend on output voltage and load current. See Applications Information. 4 LT1961 1961fa TYPICAL PERFORMANCE CHARACTERISTICS U W FB vs Temperature Switch On Voltage Drop Oscillator Frequency SHDN Threshold vs Temperature SHDN Supply Current vs VIN SHDN IP Current vs Temperature TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 FB VOLTAGE (V) 1961 G01 1.22 1.21 1.20 1.19 1.18 SWITCH CURRENT (A) 0 0.5 1 1.5 SWITCH VOLTAGE (mV) 1961 G02 400 350 300 250 200 150 100 50 0 125°C 25°C –40°C TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 FREQUENCY (MHz) 1961 G03 1.5 1.4 1.3 1.2 1.1 TA = 25°C TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 SHDN THRESHOLD (V) 1961 G04 1.40 1.38 1.36 1.34 1.32 1.30 VIN (V) 0 5 10 15 20 25 30 VIN CURRENT (μA) 1961 G05 7 6 5 4 3 2 1 0 TA = 25°C SHDN = 0V TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 SHDN INPUT (μA) 1961G06 –12 –10 –8 –6 –4 –2 0 STARTING UP SHUTTING DOWN SHDN Supply Current Input Supply Current Current Limit Foldback SHUTDOWN VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VIN CURRENT (μA) 1961 G07 300 250 200 150 100 50 0 TA = 25°C VIN = 15V INPUT VOLTAGE (V) 0 5 10 15 20 25 30 VIN CURRENT (μA) 1961 G08 1200 1000 800 600 400 200 0 MINIMUM INPUT VOLTAGE TA = 25°C FEEDBACK VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2 SWITCH PEAK CURRENT (A) 1961 G09 2.0 1.5 1.0 0.5 0 FB INPUT CURRENT (μA) 40 30 20 10 0 FB CURRENT SWITCH CURRENT TA = 25°C 5 LT1961 1961fa FB: The feedback pin is used to set output voltage using an external voltage divider that generates 1.2V at the pin with the desired output voltage. If required, the current limit can be reduced during start up when the FB pin is below 0.5V (see the Current Limit Foldback graph in the Typical Performance Characteristics section). An impedance of less than 5kΩ at the FB pin is needed for this feature to operate. VIN: This pin powers the internal circuitry and internal regulator. Keep the external bypass capacitor close to this pin. GND: Short GND pins 3 and 4 and the exposed pad on the PCB. The GND is the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND of the IC. This condition occurs when the load current flows through the metal path between the GND pins and the load ground point. Keep the ground path short between the GND pins and the load and use a ground plane when possible. Keep the path between the input bypass and the GND pins short. The exposed pad should be attached to a large copper area to improve thermal resistance. VSW: The switch pin is the collector of the on-chip power NPN switch and has large currents flowing through it. Keep the traces to the switching components as short as possible to minimize radiation and voltage spikes. SYNC: The sync pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 20% and 80% duty cycle. The synchronizing range is equal to initial operating frequency, up to 2MHz. See Synchronization section in Applications Information for details. When not in use, this pin should be grounded. SHDN: The shutdown pin is used to turn off the regulator and to reduce input drain current to a few microamperes. The 1.35V threshold can function as an accurate undervoltage lockout (UVLO), preventing the regulator from operating until the input voltage has reached a predetermined level. Float or pull high to put the regulator in the operating mode. VC: The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is normally used for frequency compensation, but can do double duty as a current clamp or control loop override. This pin sits at about 0.3V for very light loads and 0.9V at maximum load. PIN FUNCTIONSU U U 6 LT1961 1961fa amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180° shift will occur. The current fed system will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. A comparator connected to the shutdown pin disables the internal regulator, reducing supply current. The LT1961 is a constant frequency, current-mode boost converter. This means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on. When switch current reaches a level set by the inverting input of the comparator, the flip-flop is reset and the switch turns off. Output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. This technique means that the error Figure 1. Block Diagram BLOCK DIAGRAMW – + – + Σ VIN 2.5V BIAS REGULATOR 1.25MHz OSCILLATOR SW FB VC GND GND 1767 F01 SLOPE COMP 0.01Ω INTERNAL VCC CURRENT SENSE AMPLIFIER VOLTAGE GAIN = 40 SYNC SHDN SHUTDOWN COMPARATOR CURRENT COMPARATOR ERROR AMPLIFIER gm = 850μMho RS FLIP-FLOP DRIVER CIRCUITRY S R 0.3V Q1 POWER SWITCH 1.2V – + + – 1.35V 3μA 7μA 1 8 5 7 6 3 4 2 7 LT1961 1961fa APPLICATIONS INFORMATION W U U U FB RESISTOR NETWORK The suggested resistance (R2) from FB to ground is 10k 1%. This reduces the contribution of FB input bias current to output voltage to less than 0.2%. The formula for the resistor (R1) from VOUT to FB is: R R V R A OUT 1 2 12 1 2 2 0 2 = ( − ) − μ . . (. ) defines the pole frequency of the output stage, an X7R or X5R type ceramic, which have good temperature stability, is recommended. Tantalum capacitors are usually chosen for their bulk capacitance properties, useful in high transient load applications. ESR rather than absolute value defines output ripple at 1.25MHz. Values in the 22μF to 100μF range are generally needed to minimize ESR and meet ripple current ratings. Care should be taken to ensure the ripple ratings are not exceeded. Table 1. Surface Mount Solid Tantalum Capacitor ESR and Ripple Current E Case Size ESR (Max, Ω) Ripple Current (A) AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1 AVX TAJ 0.7 to 0.9 0.4 D Case Size AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1 C Case Size AVX TPS 0.2 (typ) 0.5 (typ) INPUT CAPACITOR Unlike the output capacitor, RMS ripple current in the input capacitor is normally low enough that ripple current rating is not an issue. The current waveform is triangular, with an RMS value given by: I V V V L f V RIPPLE RMS IN OUT IN OUT ( )= ( )( − ) ( )( )( ) 0.29 At higher switching frequency, the energy storage requirement of the input capacitor is reduced so values in the range of 1μF to 4.7μF are suitable for most applications. Y5V or similar type ceramics can be used since the absolute value of capacitance is less important and has no significant effect on loop stability. If operation is required close to the minimum input voltage required by either the output or the LT1961, a larger value may be necessary. This is to prevent excessive ripple causing dips below the minimum operating voltage resulting in erratic operation. Figure 2. Feedback Network OUTPUT CAPACITOR Step-up regulators supply current to the output in pulses. The rise and fall times of these pulses are very fast. The output capacitor is required to reduce the voltage ripple this causes. The RMS ripple current can be calculated from: IRIPPLE(RMS) =IOUT (VOUT − VIN) / VIN The LT1961 will operate with both ceramic and tantalum output capacitors. Ceramic capacitors are generally chosen for their small size, very low ESR (effective series resistance), and good high frequency operation, reducing output ripple voltage. Their low ESR removes a useful zero in the loop frequency response, common to tantalum capacitors. To compensate for this, the VC loop compensation pole frequency must typically be reduced by a factor of 10. Typical ceramic output capacitors are in the 1μF to 10μF range. Since the absolute value of capacitance – + 1.2V VSW VC GND 1961 F02 R1 R2 10k OUTPUT ERROR AMPLIFIER FB LT1961 + 8 LT1961 1961fa APPLICATIONS INFORMATION W U U U INDUCTOR CHOICE AND MAXIMUM OUTPUT CURRENT When choosing an inductor, there are 2 conditions that limit the minimum inductance; required output current, and avoidance of subharmonic oscillation. The maximum output current for the LT1961 in a standard boost converter configuration with an infinitely large inductor is: I A V V OUT MAX IN OUT ( ) . • = 1 5 η Where η = converter efficiency (typically 0.87 at high current). As the value of inductance is reduced, ripple current increases and IOUT(MAX) is reduced. The minimum inductance for a required output current is given by: L V V V V f V I V MIN IN OUT IN OUT OUT OUT IN = ⎛ ⎝ ⎜ ⎞ ⎠ ⎟ ( – ) ( ) . – ( )( ) • 2 15 η The second condition, avoidance of subharmonic oscillation, must be met if the operating duty cycle is greater than 50%. The slope compensation circuit within the LT1961 prevents subharmonic oscillation for inductor ripple currents of up to 0.7AP-P, defining the minimum inductor value to be: L V V V V f MIN IN OUT IN OUT = ( – ) 0.7 ( ) These conditions define the absolute minimum inductance. However, it is generally recommended that to prevent excessive output noise, and difficulty in obtaining stability, the ripple current is no more than 40% of the average inductor current. Since inductor ripple is: I V V V V L f P P RIPPLE IN OUT IN OUT − = ( – ) ( )( ) The recommended minimum inductance is: L V V V V I f MIN IN OUT IN OUT OUT = ( ) ( – ) . ( ) ( )( ) 2 0 4 2 The inductor value may need further adjustment for other factors such as output voltage ripple and filtering requirements. Remember also, inductance can drop significantly with DC current and manufacturing tolerance. The inductor must have a rating greater than its peak operating current to prevent saturation resulting in efficiency loss. Peak inductor current is given by: I V I V V V V V L f LPEAK OUT OUT IN IN OUT IN OUT = ( )( ) + − • ( ) η 2 ( )( ) Also, consideration should be given to the DC resistance of the inductor. Inductor resistance contributes directly to the efficiency losses in the overall converter. Suitable inductors are available from Coilcraft, Coiltronics, Dale, Sumida, Toko, Murata, Panasonic and other manufactures. Table 2 PART NUMBER VALUE (uH) ISAT(DC) (Amps) DCR (Ω) HEIGHT (mm) Coiltronics TP1-2R2 2.2 1.3 0.188 1.8 TP2-2R2 2.2 1.5 0.111 2.2 TP3-4R7 4.7 1.5 0.181 2.2 TP4- 100 10 1.5 0.146 3.0 Murata LQH1C1R0M04 1.0 0.51 0.28 1.8 LQH3C1R0M24 1.0 1.0 0.06 2.0 LQH3C2R2M24 2.2 0.79 0.1 2.0 LQH4C1R5M04 1.5 1 0.09 2.6 Sumida CD73- 100 10 1.44 0.080 3.5 CDRH4D18-2R2 2.2 1.32 0.058 1.8 CDRH5D18-6R2 6.2 1.4 0.071 1.8 CDRH5D28-100 10 1.3 0.048 2.8 Coilcraft 1008PS-272M 2.7 1.3 0.14 2.7 LPO1704-222M 2.2 1.6 0.12 1.0 LPO1704-332M 3.3 1.3 0.16 1.0 9 LT1961 1961fa APPLICATIONS INFORMATION W U U U shutdown pin can be used. The threshold voltage of the shutdown pin comparator is 1.35V. A 3μA internal current source defaults the open pin condition to be operating (see Typical Performance Graphs). Current hysteresis is added above the SHDN threshold. This can be used to set voltage hysteresis of the UVLO using the following: R V V A R V V V R A H L H 1 7 2 1 35 1 35 1 3 = − μ = ( − ) + μ . . VH – Turn-on threshold VL – Turn-off threshold Example: switching should not start until the input is above 4.75V and is to stop if the input falls below 3.75V. VH = 4.75V VL = 3.75V R V V A k R V V V k A k 1 4 75 3 75 7 143 2 1 35 4 75 1 35 143 3 50 4 = − μ = = ( − ) + μ = . . . . . . Keep the connections from the resistors to the SHDN pin short and make sure that the interplane or surface capacitance to the switching nodes are minimized. If high resistor values are used, the SHDN pin should be bypassed with a 1nF capacitor to prevent coupling problems from the switch node. CATCH DIODE The suggested catch diode (D1) is a UPS120 or 1N5818 Schottky. It is rated at 1A average forward current and 20V/30V reverse voltage. Typical forward voltage is 0.5V at 1A. The diode conducts current only during switch off time. Peak reverse voltage is equal to regulator output voltage. Average forward current in normal operation is equal to output current. SHUTDOWN AND UNDERVOLTAGE LOCKOUT Figure 4 shows how to add undervoltage lockout (UVLO) to the LT1961. Typically, UVLO is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur. Figure 4. Undervoltage Lockout 1.35V GND INPUT R1 1961 F04 SHDN VCC IN LT1961 3μA C1 R2 7μA An internal comparator will force the part into shutdown below the minimum VIN of 2.6V. This feature can be used to prevent excessive discharge of battery-operated systems. If an adjustable UVLO threshold is required, the 10 LT1961 1961fa SYNCHRONIZATION The SYNC pin, is used to synchronize the internal oscillator to an external signal. The SYNC input must pass from a logic level low, through the maximum synchronization threshold with a duty cycle between 20% and 80%. The input can be driven directly from a logic level output. The synchronizing range is equal to initial operating frequency up to 2MHz. This means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency (1.5MHz), not the typical operating frequency of 1.25MHz. Caution should be used when synchronizing above 1.7MHz because at higher sync frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation. LAYOUT CONSIDERATIONS As with all high frequency switchers, when considering layout, care must be taken to achieve optimal electrical, thermal and noise performance. For maximum efficiency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the APPLICATIONS INFORMATION W U U U high speed switching current path, shown in Figure 5, must be kept as short as possible. This is implemented in the suggested layout of Figure 6. Shortening this path will also reduce the parasitic trace inductance of approximately 25nH/inch. At switch off, this parasitic inductance produces a flyback spike across the LT1961 switch. When operating at higher currents and output voltages, with poor layout, this spike can generate voltages across the LT1961 that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. The VC and FB components should be kept as far away as possible from the switch node. The LT1961 pinout has been designed to aid in this. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation. Board layout also has a significant effect on thermal resistance. The exposed pad is the copper plate that runs under the LT1961 die. This is the best thermal path for heat out of the package. Soldering the pad onto the board will reduce die temperature and increase the power capability of the LT1961. Provide as much copper area as possible around this pad. Adding multiple solder filled feedthroughs under and around the pad to the ground plane will also help. Similar treatment to the catch diode and inductor terminations will reduce any additional heating effects. 1961 F05 VOUT L1 SW GND LT1961 D1 C1 C3 VIN HIGH FREQUENCY SWITCHING PATH LOAD Figure 5. High Speed Switching Path 11 LT1961 1961fa Figure 6. Typical Application and Suggested Layout (Topside Only Shown) LT1961 VIN OUTPUT 12V 0.5A* INPUT 5V C2 6800pF C4 R3 100pF 6.8k R2 10k 1% R1 90.9k D1 UPS120 C1 10μF CERAMIC C3 2.2μF CERAMIC VSW SHDN FB OPEN OR HIGH = ON SYNC GND VC *MAXIMUM OUTPUT CURRENT IS SUBJECT TO THERMAL DERATING. L1 6.8μH VOUT INPUT GND C3 C1 R2 R1 L1 D1 KELVIN SENSE VOUT MINIMIZE LT1961, C1, D1 LOOP KEEP FB AND VC COMPONENTS AWAY FROM HIGH FREQUENCY, HIGH INPUT COMPONENTS PLACE FEEDTHROUGHS AROUND GROUND PIN FOR GOOD THERMAL CONDUCTIVITY LT1961EMS8E GND C4 U1 SOLDER EXPOSED GROUND PAD TO BOARD R3 C2 APPLICATIONS INFORMATION W U U U 12 LT1961 1961fa APPLICATIONS INFORMATION W U U U THERMAL CALCULATIONS Power dissipation in the LT1961 chip comes from four sources: switch DC loss, switch AC loss, drive current, and input quiescent current. The following formulas show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. DC duty cycle V V V I V I V OUT IN OUT SW OUT OUT IN , ( ) ( )( ) = − = Switch loss: PSW = (DC)(ISW)2(RSW)+ 17n(ISW)(VOUT )(f) VIN loss: P V I DC VIN mA V IN SW = + IN ( )( )( ) ( ) 50 1 RSW = Switch resistance (≈ 0.27Ω hot) Example: VIN = 5V, VOUT = 12V and IOUT = 0.5A Total power dissipation = 0.23 + 0.31 + 0.07 + 0.005 = 0.62W Thermal resistance for LT1961 package is influenced by the presence of internal or backside planes. With a full plane under the package, thermal resistance will be about 50°C/W. To calculate die temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: TJ = TA + θJA (PTOT) If a true die temperature is required, a measurement of the SYNC to GND pin resistance can be used. The SYNC pin resistance across temperature must first be calibrated, with no device power, in an oven. The same measurement can then be used in operation to indicate the die temperature. FREQUENCY COMPENSATION Loop frequency compensation is performed on the output of the error amplifier (VC pin) with a series RC network. The main pole is formed by the series capacitor and the output impedance (≈500kΩ) of the error amplifier. The pole falls in the range of 2Hz to 20Hz. The series resistor creates a “zero” at 1kHz to 5kHz, which improves loop stability and transient response. A second capacitor, typically one-tenth the size of the main compensation capacitor, is sometimes used to reduce the switching frequency ripple on the VC pin. VC pin ripple is caused by output voltage ripple attenuated by the output divider and multiplied by the error amplifier. Without the second capacitor, VC pin ripple is: VC Pin Ripple = VRIPPLE = Output ripple (VP–P) gm = Error amplifier transconductance (≈850μmho) RC = Series resistor on VC pin VOUT = DC output voltage 1.2(VRIPPLE)(gm)(RC) (VOUT) To prevent irregular switching, VC pin ripple should be kept below 50mVP–P. Worst-case VC pin ripple occurs at maximum output load current and will also be increased if poor quality (high ESR) output capacitors are used. The addition of a 47pF capacitor on the VC pin reduces switching frequency ripple to only a few millivolts. A low value for RC will also reduce VC pin ripple, but loop phase margin may be inadequate. 13 LT1961 1961fa LT1961 FB VIN VC VIN 5V TO 10V *DALE LPE-4841-100MB GND LT1961 • TA02 S/S VSW P6KE-20A 1N4148 UPS140 UPS140 C1 4.7μF R2 10k 1% R1 115k 1% C2 2.2nF C3 100pF R3 10k –VOUT –15V VOUT 15V C4 47μF C5 47μF ON OFF 2, 3 8, 9 7 T1* 4 10 1 • • • + + + Dual Output Flyback Converter TYPICAL APPLICATIO SU LT1961 VIN GND VIN** 4V TO 9V VC FB LT1961 • TA03 S/S VSW C1 4.7μF 20V C4 2.2nF C5 100pF R1 10k R3 10k 1% R2 31.6k 1% VOUT † 5V C3 47μF 10V ON OFF L1A* 10μH • • L1B* 10μH C2 4.7μF BH ELECTRONICS 511-1012 INPUT VOLTAGE MAY BE GREATER OR LESS THAN OUTPUT VOLTAGE D1 UPS120 VIN 4V 5V 6V 7V 9V IOUT 0.59A 0.65A 0.70A 0.74A 0.80A †MAX IOUT * ** + + 4V-9VIN to 5VOUT SEPIC Converter** 14 LT1961 1961fa LT1961 VIN GND VC FB LT1961 • TA04 S/S VSW L1 4.7μH C1 10μF SINGLE Li-Ion CELL C4 47μF 10V C2 2.2nF C3 100pF R3 10k R2 10k 1% R1 31.6k 1% VOUT 5V D1 UPS120 ON OFF + + + VIN 2.7V 3.3V 3.6V IOUT 0.75A 0.93A 1.0A Single Li-Ion Cell to 5V TYPICAL APPLICATIO SU 15 LT1961 1961fa PACKAGE DESCRIPTIONU Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. MSOP (MS8E) 0307 REV D 0.53 ± 0.152 (.021 ± .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 1 2 3 4 4.90 ± 0.152 (.193 ± .006) 8 8 1 BOTTOM VIEW OF EXPOSED PAD OPTION 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.52 (.0205) REF 1.83 ± 0.102 (.072 ± .004) 2.06 ± 0.102 (.081 ± .004) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 2.083 ± 0.102 (.082 ± .004) 2.794 ± 0.102 (.110 ± .004) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 0.1016 ± 0.0508 (.004 ± .002) MS8E Package 8-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1662 Rev D) 16 LT1961 1961fa PART NUMBER DESCRIPTION COMMENTS LT1308A 600kHz, 2A, Step-Up Regulator 30V Switch, VIN = 1V to 6V, Low Battery Comparator, S8 Package LT1310 4.5MHz, 1.5A Step-Up with Phase Lock Loop 34V Switch, VIN = 2.75V to 18V, VOUT up to 35V, MS10E Package LT1370 High Efficiency DC/DC Converter 42V Switch, 6A, 500kHz Switch, DD-Pak, TO-220 Package LT1371 High Efficiency DC/DC Converter 35V Switch, 3A, 500kHz Switch, DD-Pak, TO-220 Package LT1372/LT1377 500kHz and 1MHz High Efficiency 1.5A Switching Regulators Boost Topology, VIN(MIN) = 2.7V, S8 Package LT1946/LT1946A 1.2MHz/2.7MHz, 1.5A, Monolithic Step-Up Regulator VIN = 2.6V to 16V, VOUT up to 34V, Integrated SS, MS8 Package LTC3400/ 1.2MHz, 600mA, Synchronous Step-Up VIN = 0.85V to 5V, VOUT to 5.5V, Up to 95% Efficiency, LTC3400B ThinSOT Package LTC3401 Single Cell, High Current (1A), Micropower, Synchronous 3MHz VIN = 0.85V to 5V, VOUT to 5.5V, Up to 97% Efficiency Step-Up DC/DC Converter Synchronizable, Oscillator from 100kHz to 3MHz, MS10 Package LTC3402 Single Cell, High Current (2A), Micropower, Synchronous 3MHz VIN = 0.85V to 5V, VOUT to 5.5V, Up to 95% Efficiency Step-Up DC/DC Converter Synchronizable, Oscillator from 100kHz to 3MHz, MS10 Package LTC3405/ 1.5MHz High Efficiency, IOUT = 300mA, Monolithic Synchronous VIN = 2.5V to 5.5V, VOUT to 0.8V, Up to 95% Efficiency, 100% LTC3405A Step-Down Regulator Duty Cycle, IQ = 20μA, ThinSOT Package ThinSOT is a trademark of Linear Technology Corporation. LT 0707 REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2001 RELATED PARTS Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LASER 190Ω 1% 1N4002 0.1μF (ALL) 10k VIN 10μF VC VIN FB GND 2.2μF VIN 12V TO 25V 150Ω MUR405 L2 10μH LT1961 L1 5 4 1 3 2 11 8 HV DIODES 1800pF 10kV 0.01μF 5kV 1800pF 10kV 47k 5W 2.2μF 0.47μF L1 = Q1, Q2 = 0.47μF = HV DIODES = LASER = COILTRONICS CTX02-11128 ZETEX ZTX849 WIMA 3X 0.15μF TYPE MKP-20 SEMTECH-FM-50 HUGHES 3121H-P 10k LT1961 • TA05 VSW Q1 Q2 + + + COILTRONICS (407) 241-7876 U TYPICAL APPLICATIO High Voltage Laser Power Supply LT3757/LT3757A 1 3757afd n Wide Input Voltage Range: 2.9V to 40V n Positive or Negative Output Voltage Programming with a Single Feedback Pin n Current Mode Control Provides Excellent Transient Response n Programmable Operating Frequency (100kHz to 1MHz) with One External Resistor n Synchronizable to an External Clock n Low Shutdown Current < 1μA n Internal 7.2V Low Dropout Voltage Regulator n Programmable Input Undervoltage Lockout with Hysteresis n Programmable Soft-Start n Small 10-Lead DFN (3mm × 3mm) and Thermally Enhanced 10-Pin MSOP Packages Typical Application Description Boost, Flyback, SEPIC and Inverting Controller The LT®3757/LT3757A are wide input range, current mode, DC/DC controllers which are capable of generating either positive or negative output voltages. They can be configured as either a boost, flyback, SEPIC or inverting converter. The LT3757/LT3757A drive a low side external N-channel power MOSFET from an internal regulated 7.2V supply. The fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. The operating frequency of LT3757/LT3757A can be set with an external resistor over a 100kHz to 1MHz range, and can be synchronized to an external clock using the SYNC pin. A low minimum operating supply voltage of 2.9V, and a low shutdown quiescent current of less than 1μA, make the LT3757/LT3757A ideally suited for batteryoperated systems. The LT3757/LT3757A feature soft-start and frequency foldback functions to limit inductor current during start-up and output short-circuit. The LT3757A has improved load transient performance compared to the LT3757. High Efficiency Boost Converter Features Applications n Automotive and Industrial Boost, Flyback, SEPIC and Inverting Converters n Telecom Power Supplies n Portable Electronic Equipment Efficiency SENSE LT3757 VIN VIN 8V TO 16V 10μF 25V X5R VOUT 24V 2A 0.01 41.2k 300kHz GATE FBX GND INTVCC SHDN/UVLO SYNC RT SS VC 200k 43.2k 0.1μF 22k 6.8nF 10μH 3757 TA01a 226k 16.2k 4.7μF 10V X5R 10μF 25V X5R 47μF 35V ×2 + OUTPUT CURRENT (A) 0.001 EFFICIENCY (%) 30 50 40 60 70 80 90 100 0.01 0.1 1 3757 TA01b 10 VIN = 8V VIN = 16V L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks and No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. LT3757/LT3757A 2 3757afd Pin Configuration Absolute Maximum Ratings VIN, SHDN/UVLO (Note 6)..........................................40V INTVCC.....................................................VIN + 0.3V, 20V GATE......................................................... INTVCC + 0.3V SYNC...........................................................................8V VC, SS..........................................................................3V RT.............................................................................1.5V SENSE.....................................................................±0.3V FBX.................................................................. –6V to 6V (Note 1) TOP VIEW DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN 10 9 6 7 8 4 5 3 11 2 1 VIN SHDN/UVLO INTVCC GATE SENSE VC FBX SS RT SYNC TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB 12345 VC FBX SS RT SYNC 10 9876 VIN SHDN/UVLO INTVCC GATE SENSE TOP VIEW MSE PACKAGE 10-LEAD PLASTIC MSOP 11 TJMAX = 150°C, θJA = 40°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3757EDD#PBF LT3757EDD#TRPBF LDYW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3757IDD#PBF LT3757IDD#TRPBF LDYW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3757EMSE#PBF LT3757EMSE#TRPBF LTDYX 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 125°C LT3757IMSE#PBF LT3757IMSE#TRPBF LTDYX 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 125°C LT3757HMSE#PBF LT3757HMSE#TRPBF LTDYX 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 150°C LT3757MPMSE#PBF LT3757MPMSE#TRPBF LTDYX 10-Lead (3mm × 3mm) Plastic MSOP –55°C to 150°C LT3757AEDD#PBF LT3757AEDD#TRPBF LGGR 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3757AIDD#PBF LT3757AIDD#TRPBF LGGR 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3757AEMSE#PBF LT3757AEMSE#TRPBF LTGGM 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 125°C LT3757AIMSE#PBF LT3757AIMSE#TRPBF LTGGM 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 125°C LT3757AHMSE#PBF LT3757AHMSE#TRPBF LTGGM 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 150°C LT3757AMPMSE#PBF LT3757AMPMSE#TRPBF LTGGM 10-Lead (3mm × 3mm) Plastic MSOP –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Operating Temperature Range (Notes 2, 8) LT3757E/LT3757AE............................ –40°C to 125°C LT3757I/LT3757AI.............................. –40°C to 125°C LT3757H/LT3757AH............................ –40°C to 150°C LT3757MP/LT3757AMP...................... –55°C to 150°C Storage Temperature Range DFN..................................................... –65°C to 125°C MSOP................................................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) MSOP................................................................300°C LT3757/LT3757A 3 3757afd E lectrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Range 2.9 40 V VIN Shutdown IQ SHDN/UVLO = 0V SHDN/UVLO = 1.15V 0.1 1 6 μA μA VIN Operating IQ VC = 0.3V, RT = 41.2k 1.6 2.2 mA VIN Operating IQ with Internal LDO Disabled VC = 0.3V, RT = 41.2k, INTVCC = 7.5V 280 400 μA SENSE Current Limit Threshold l 100 110 120 mV SENSE Input Bias Current Current Out of Pin –65 μA Error Amplifier FBX Regulation Voltage (VFBX(REG)) VFBX > 0V (Note 3) VFBX < 0V (Note 3) l l 1.569 –0.816 1.6 –0.80 1.631 –0.784 V V FBX Overvoltage Lockout VFBX > 0V (Note 4) VFBX < 0V (Note 4) 6 7 8 11 10 14 % % FBX Pin Input Current VFBX = 1.6V (Note 3) VFBX = –0.8V (Note 3) –10 70 100 10 nA nA Transconductance gm (ΔIVC/ΔVFBX) (Note 3) 230 μS VC Output Impedance (Note 3) 5 MΩ VFBX Line Regulation [ΔVFBX /(ΔVIN • VFBX(REG))] VFBX > 0V, 2.9V < VIN < 40V (Notes 3, 7) VFBX < 0V, 2.9V < VIN < 40V (Notes 3, 7) 0.002 0.0025 0.056 0.05 %/V %/V VC Current Mode Gain (ΔVVC /ΔVSENSE) 5.5 V/V VC Source Current VFBX = 0V, VC = 1.5V –15 μA VC Sink Current VFBX = 1.7V VFBX = –0.85V 12 11 μA μA Oscillator Switching Frequency RT = 41.2k to GND, VFBX = 1.6V RT = 140k to GND, VFBX = 1.6V RT = 10.5k to GND, VFBX = 1.6V 270 300 100 1000 330 kHz kHz kHz RT Voltage VFBX = 1.6V 1.2 V Minimum Off-Time 220 ns Minimum On-Time 220 ns SYNC Input Low 0.4 V SYNC Input High 1.5 V SS Pull-Up Current SS = 0V, Current Out of Pin –10 μA Low Dropout Regulator INTVCC Regulation Voltage l 7 7.2 7.4 V INTVCC Undervoltage Lockout Threshold Falling INTVCC UVLO Hysteresis 2.6 2.7 0.1 2.8 V V INTVCC Overvoltage Lockout Threshold 16 17.5 V INTVCC Current Limit VIN = 40V VIN = 15V 30 40 95 55 mA mA INTVCC Load Regulation (ΔVINTVCC/ VINTVCC) 0 < IINTVCC < 20mA, VIN = 8V –0.9 –0.5 % INTVCC Line Regulation ΔVINTVCC/(VINTVCC • ΔVIN) 8V < VIN < 40V 0.008 0.03 %/V Dropout Voltage (VIN – VINTVCC) VIN = 6V, IINTVCC = 20mA 400 mV INTVCC Current in Shutdown SHDN/UVLO = 0V, INTVCC = 8V 16 μA LT3757/LT3757A 4 3757afd TEMPERATURE (°C) –75 –50 1580 1585 REGULATED FEEDBACK VOLTAGE (mV) 1590 1605 1600 0 50 75 1595 –25 25 100 125 150 3757 G01 VIN = 40V VIN = 24V VIN = 8V VIN = INTVCC = 2.9V SHDN/UVLO = 1.33V TEMPERATURE (°C) REGULATED FEEDBACK VOLTAGE (mV) –802 –800 –798 –788 –790 –792 –794 –804 –796 3757 G02 –75 –50 –25 0 25 50 75 100 125 150 VIN = 40V VIN = 24V VIN = 8V VIN = INTVCC = 2.9V SHDN/UVLO = 1.33V Typical Performance Characteristics Positive Feedback Voltage vs Temperature, VIN Negative Feedback Voltage vs Temperature, VIN Quiescent Current vs Temperature, VIN TA = 25°C, unless otherwise noted. E lectrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC Voltage to Bypass Internal LDO 7.5 V Logic Inputs SHDN/UVLO Threshold Voltage Falling VIN = INTVCC = 8V l 1.17 1.22 1.27 V SHDN/UVLO Input Low Voltage I(VIN) Drops Below 1μA 0.4 V SHDN/UVLO Pin Bias Current Low SHDN/UVLO = 1.15V 1.7 2 2.5 μA SHDN/UVLO Pin Bias Current High SHDN/UVLO = 1.30V 10 100 nA Gate Driver tr Gate Driver Output Rise Time CL = 3300pF (Note 5), INTVCC = 7.5V 22 ns tf Gate Driver Output Fall Time CL = 3300pF (Note 5), INTVCC = 7.5V 20 ns Gate VOL 0.05 V Gate VOH INTVCC –0.05 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3757E/LT3757AE are guaranteed to meet performance specifications from the 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3757I/LT3757AI are guaranteed over the full –40°C to 125°C operating junction temperature range. The LT3757H/LT3757AH are guaranteed over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. The LT3757MP/LT3757AMP are 100% tested and guaranteed over the full –55°C to 150°C operating junction temperature range. Note 3: The LT3757/LT3757A are tested in a feedback loop which servos VFBX to the reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V. Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOLTAGE) relative to regulated VFBX(REG). Note 5: Rise and fall times are measured at 10% and 90% levels. Note 6: For VIN below 6V, the SHDN/UVLO pin must not exceed VIN. Note 7: SHDN/UVLO = 1.33V when VIN = 2.9V. Note 8: The LT3757/LT3757A include overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.4 QUIESCENT CURRENT (mA) 1.6 1.8 1.5 1.7 3757 G03 VIN = 40V VIN = 24V VIN = INTVCC = 2.9V LT3757/LT3757A 5 3757afd Typical Performance Characteristics Switching Frequency vs Temperature SENSE Current Limit Threshold vs Temperature SENSE Current Limit Threshold vs Duty Cycle SHDN/UVLO Threshold vs Temperature SHDN/UVLO Current vs Voltage SHDN/UVLO Hysteresis Current vs Temperature Dynamic Quiescent Current vs Switching Frequency RT vs Switching Frequency Normalized Switching Frequency vs FBX TA = 25°C, unless otherwise noted. FBX VOLTAGE (V) –0.8 0 NORMALIZED FREQUENCY (%) 20 40 60 80 120 –0.4 0 0.4 0.8 3757 G06 1.2 1.6 100 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 100 SENSE THRESHOLD (mV) 105 110 115 120 3757 G08 DUTY CYCLE (%) 0 95 SENSE THRESHOLD (mV) 105 20 40 60 80 115 100 110 100 3757 G09 SHDN/UVLO VOLTAGE (V) 0 0 SHDN/UVLO CURRENT (μA) 20 10 20 30 40 10 30 40 3757 G11 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.6 ISHDN/UVLO (μA) 1.8 2.0 2.2 2.4 3757 G12 SWITCHING FREQUENCY (KHz) 0 0 IQ(mA) 15 20 35 300 500 600 700 10 5 25 30 100 200 400 800 900 1000 3757 G04 CL = 3300pF SWITCHING FREQUENCY (KHz) 0 10 RT (k) 100 1000 100 200 300 400 500 600 700 800 900 1000 3757 G05 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 270 SWITCHING FREQUENCY (kHz) 280 290 300 310 330 3757 G07 320 RT = 41.2K –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.18 SHDN/UVLO VOLTAGE (V) 1.22 1.24 1.26 1.28 1.20 3757 G10 SHDN/UVLO FALLING SHDN/UVLO RISING LT3757/LT3757A 6 3757afd Typical Performance Characteristics INTVCC Line Regulation INTVCC Dropout Voltage vs Current, Temperature Gate Drive Rise and Fall Time vs INTVCC Typical Start-Up Waveforms INTVCC vs Temperature INTVCC Minimum Output Current vs VIN INTVCC Load Regulation TA = 25°C, unless otherwise noted. Gate Drive Rise and Fall Time vs CL FBX Frequency Foldback Waveforms During Overcurrent –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 7.0 INTVCC (V) 7.1 7.2 7.3 7.4 3757 G13 VIN (V) 0 INTVCC VOLTAGE (V) 35 7.25 7.20 5 10 15 20 25 30 40 7.15 7.10 7.30 3757 G16 CL (nF) 0 TIME (ns) 60 70 80 50 40 5 10 15 20 25 30 10 0 30 90 20 3757 G18 RISE TIME INTVCC = 7.2V FALL TIME INTVCC (V) 3 TIME (ns) 20 25 15 10 6 9 12 15 5 0 30 3757 G19 CL = 3300pF RISE TIME FALL TIME 2ms/DIV VOUT 5V/DIV IL1A + IL1B 5A/DIV 3757 G20 VIN = 12V PAGE 31 CIRCUIT 50μs/DIV PAGE 31 CIRCUIT VOUT 10V/DIV VSW 20V/DIV IL1A + IL1B 5A/DIV 3757 G21 VIN = 12V INTVCC LOAD (mA) 0 6.8 7 7.1 7.2 7.3 20 40 50 60 6.9 10 30 70 3757 G15 INTVCC VOLTAGE (V) VIN = 8V INTVCC LOAD (mA) 0 DROPOUT VOLTAGE (mV) 500 600 300 400 200 5 10 15 20 100 0 700 3757 G17 150°C 125°C 25°C 0°C –55°C 75°C VIN = 6V VIN (V) 0 INTVCC CURRENT (mA) 50 60 70 40 3757 G14 40 30 0 10 5 10 15 20 25 30 35 20 90 80 TJ = 150°C INTVCC = 6V INTVCC = 4.5V LT3757/LT3757A 7 3757afd Pin Functions VC (Pin 1): Error Amplifier Compensation Pin. Used to stabilize the voltage loop with an external RC network. FBX (Pin 2): Positive and Negative Feedback Pin. Receives the feedback voltage from the external resistor divider across the output. Also modulates the frequency during start-up and fault conditions when FBX is close to GND. SS (Pin 3): Soft-Start Pin. This pin modulates compensation pin voltage (VC) clamp. The soft-start interval is set with an external capacitor. The pin has a 10μA (typical) pull-up current source to an internal 2.5V rail. The soft-start pin is reset to GND by an undervoltage condition at SHDN/ UVLO, an INTVCC undervoltage or overvoltage condition or an internal thermal lockout. RT (Pin 4): Switching Frequency Adjustment Pin. Set the frequency using a resistor to GND. Do not leave this pin open. SYNC (Pin 5): Frequency Synchronization Pin. Used to synchronize the switching frequency to an outside clock. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than the SYNC pulse frequency. Tie the SYNC pin to GND if this feature is not used. SYNC is ignored when FBX is close to GND. SENSE (Pin 6): The Current Sense Input for the Control Loop. Kelvin connect this pin to the positive terminal of the switch current sense resistor in the source of the N-channel MOSFET. The negative terminal of the current sense resistor should be connected to GND plane close to the IC. GATE (Pin 7): N-Channel MOSFET Gate Driver Output. Switches between INTVCC and GND. Driven to GND when IC is shut down, during thermal lockout or when INTVCC is above or below the OV or UV thresholds, respectively. INTVCC (Pin 8): Regulated Supply for Internal Loads and Gate Driver. Supplied from VIN and regulated to 7.2V (typical). INTVCC must be bypassed with a minimum of 4.7μF capacitor placed close to pin. INTVCC can be connected directly to VIN, if VIN is less than 17.5V. INTVCC can also be connected to a power supply whose voltage is higher than 7.5V, and lower than VIN, provided that supply does not exceed 17.5V. SHDN/UVLO (Pin 9): Shutdown and Undervoltage Detect Pin. An accurate 1.22V (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 2μA pull-down current. An undervoltage condition resets sort-start. Tie to 0.4V, or less, to disable the device and reduce VIN quiescent current below 1μA. VIN (Pin 10): Input Supply Pin. Must be locally bypassed with a 0.22μF, or larger, capacitor placed close to the pin. Exposed Pad (Pin 11): Ground. This pin also serves as the negative terminal of the current sense resistor. The Exposed Pad must be soldered directly to the local ground plane. LT3757/LT3757A 8 3757afd Block Diagram Figure 1. LT3757 Block Diagram Working as a SEPIC Converter L1 R1 R4 R3 M1 L2 R2 FBX 1.22V 2.5V CDC D1 CIN VOUT COUT2 COUT1 CVCC INTVCC VIN RSENSE VISENSE • + + VIN IS1 2μA 10 8 7 1 9 SHDN/UVLO INTERNAL REGULATOR AND UVLO TSD 165°C A10 Q3 VC VC 17.5V 2.7V UP 2.6V DOWN A8 UVLO IS2 10μA IS3 CC1 CC2 RC DRIVER SLOPE SENSE GND GATE 108mV SR1 + – + – CURRENT LIMIT RAMP GENERATOR 7.2V LDO • + – + – R O S 2.5V G1 RT RT SS CSS SYNC 1.25V 1.25V FBX FBX 1.6V –0.8V + – + – + – 2 3 5 4 + – + – 6 11 RAMP PWM COMPARATOR FREQUENCY FOLDBACK 100kHz-1MHz OSCILLATOR FREQ FOLDBACK FREQ PROG 3757 F01 – ++ Q1 A1 A2 1.72V –0.88V + – + – A11 A12 A3 A4 A5 A6 G5 G2 G6 A7 A9 Q2 D2 R5 8k D3 G4 G3 LT3757/LT3757A 9 3757afd Applications Information Main Control Loop The LT3757 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block Diagram in Figure 1. The start of each oscillator cycle sets the SR latch (SR1) and turns on the external power MOSFET switch M1 through driver G2. The switch current flows through the external current sensing resistor RSENSE and generates a voltage proportional to the switch current. This current sense voltage VISENSE (amplified by A5) is added to a stabilizing slope compensation ramp and the resulting sum (SLOPE) is fed into the positive terminal of the PWM comparator A7. When SLOPE exceeds the level at the negative input of A7 (VC pin), SR1 is reset, turning off the power switch. The level at the negative input of A7 is set by the error amplifier A1 (or A2) and is an amplified version of the difference between the feedback voltage (FBX pin) and the reference voltage (1.6V or –0.8V, depending on the configuration). In this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. The LT3757 has a switch current limit function. The current sense voltage is input to the current limit comparator A6. If the SENSE pin voltage is higher than the sense current limit threshold VSENSE(MAX) (110mV, typical), A6 will reset SR1 and turn off M1 immediately. The LT3757 is capable of generating either positive or negative output voltage with a single FBX pin. It can be configured as a boost, flyback or SEPIC converter to generate positive output voltage, or as an inverting converter to generate negative output voltage. When configured as a SEPIC converter, as shown in Figure 1, the FBX pin is pulled up to the internal bias voltage of 1.6V by a voltage divider (R1 and R2) connected from VOUT to GND. Comparator A2 becomes inactive and comparator A1 performs the inverting amplification from FBX to VC. When the LT3757 is in an inverting configuration, the FBX pin is pulled down to –0.8V by a voltage divider connected from VOUT to GND. Comparator A1 becomes inactive and comparator A2 performs the noninverting amplification from FBX to VC. The LT3757 has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. An overvoltage comparator A11 (with 20mV hysteresis) senses when the FBX pin voltage exceeds the positive regulated voltage (1.6V) by 8% and provides a reset pulse. Similarly, an overvoltage comparator A12 (with 10mV hysteresis) senses when the FBX pin voltage exceeds the negative regulated voltage (–0.8V) by 11% and provides a reset pulse. Both reset pulses are sent to the main RS latch (SR1) through G6 and G5. The power MOSFET switch M1 is actively held off for the duration of an output overvoltage condition. Programming Turn-On and Turn-Off Thresholds with the SHDN/UVLO Pin The SHDN/UVLO pin controls whether the LT3757 is enabled or is in shutdown state. A micropower 1.22V reference, a comparator A10 and a controllable current source IS1 allow the user to accurately program the supply voltage at which the IC turns on and off. The falling value can be accurately set by the resistor dividers R3 and R4. When SHDN/UVLO is above 0.7V, and below the 1.22V threshold, the small pull-down current source IS1 (typical 2μA) is active. The purpose of this current is to allow the user to program the rising hysteresis. The Block Diagram of the comparator and the external resistors is shown in Figure 1. The typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: VVIN,FALLING = 1.22 • (R3 +R4) R4 VVIN,RISING = 2μA •R3+ VIN,FALLING For applications where the SHDN/UVLO pin is only used as a logic input, the SHDN/UVLO pin can be connected directly to the input voltage VIN for always-on operation. LT3757/LT3757A 10 3757afd Applications Information INTVCC Regulator Bypassing and Operation An internal, low dropout (LDO) voltage regulator produces the 7.2V INTVCC supply which powers the gate driver, as shown in Figure 1. If a low input voltage operation is expected (e.g., supplying power from a lithium-ion battery or a 3.3V logic supply), low threshold MOSFETs should be used. The LT3757 contains an undervoltage lockout comparator A8 and an overvoltage lockout comparator A9 for the INTVCC supply. The INTVCC undervoltage (UV) threshold is 2.7V (typical), with 100mV hysteresis, to ensure that the MOSFETs have sufficient gate drive voltage before turning on. The logic circuitry within the LT3757 is also powered from the internal INTVCC supply. The INTVCC overvoltage (OV) threshold is set to be 17.5V (typical) to protect the gate of the power MOSFET. When INTVCC is below the UV threshold, or above the OV threshold, the GATE pin will be forced to GND and the soft-start operation will be triggered. The INTVCC regulator must be bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7μF ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver. In an actual application, most of the IC supply current is used to drive the gate capacitance of the power MOSFET. The on-chip power dissipation can be a significant concern when a large power MOSFET is being driven at a high frequency and the VIN voltage is high. It is important to limit the power dissipation through selection of MOSFET and/ or operating frequency so the LT3757 does not exceed its maximum junction temperature rating. The junction temperature TJ can be estimated using the following equations: TJ = TA + PIC • θJA TA = ambient temperature θJA = junction-to-ambient thermal resistance PIC = IC power consumption = VIN • (IQ + IDRIVE) IQ = VIN operation IQ = 1.6mA IDRIVE = average gate drive current = f • QG f = switching frequency QG = power MOSFET total gate charge The LT3757 uses packages with an Exposed Pad for enhanced thermal conduction. With proper soldering to the Exposed Pad on the underside of the package and a full copper plane underneath the device, thermal resistance (θJA) will be about 43°C/W for the DD package and 40°C/W for the MSE package. For an ambient board temperature of TA = 70°C and maximum junction temperature of 125°C, the maximum IDRIVE (IDRIVE(MAX)) of the DD package can be calculated as: IDRIVE(MAX) = (TJ − TA) (θJA • VIN) −IQ = 1.28W VIN − 1.6mA The LT3757 has an internal INTVCC IDRIVE current limit function to protect the IC from excessive on-chip power dissipation. The IDRIVE current limit decreases as the VIN increases (see the INTVCC Minimum Output Current vs VIN graph in the Typical Performance Characteristics section). If IDRIVE reaches the current limit, INTVCC voltage will fall and may trigger the soft-start. Based on the preceding equation and the INTVCC Minimum Output Current vs VIN graph, the user can calculate the maximum MOSFET gate charge the LT3757 can drive at a given VIN and switch frequency. A plot of the maximum QG vs VIN at different frequencies to guarantee a minimum 4.5V INTVCC is shown in Figure 2. As illustrated in Figure 2, a trade-off between the operating frequency and the size of the power MOSFET may be needed in order to maintain a reliable IC junction temperature. Figure 2. Recommended Maximum QG vs VIN at Different Frequencies to Ensure INTVCC Higher Than 4.5V VIN (V) 0 QG (nC) 200 250 150 100 5 10 15 20 25 30 35 40 50 0 300 3757 F02 300kHz 1MHz LT3757/LT3757A 11 3757afd Applications Information Prior to lowering the operating frequency, however, be sure to check with power MOSFET manufacturers for their most recent low QG, low RDS(ON) devices. Power MOSFET manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. An effective approach to reduce the power consumption of the internal LDO for gate drive is to tie the INTVCC pin to an external voltage source high enough to turn off the internal LDO regulator. If the input voltage VIN does not exceed the absolute maximum rating of both the power MOSFET gate-source voltage (VGS) and the INTVCC overvoltage lockout threshold voltage (17.5V), the INTVCC pin can be shorted directly to the VIN pin. In this condition, the internal LDO will be turned off and the gate driver will be powered directly from the input voltage, VIN. With the INTVCC pin shorted to VIN, however, a small current (around 16μA) will load the INTVCC in shutdown mode. For applications that require the lowest shutdown mode input supply current, do not connect the INTVCC pin to VIN. In SEPIC or flyback applications, the INTVCC pin can be connected to the output voltage VOUT through a blocking diode, as shown in Figure 3, if VOUT meets the following conditions: 1. VOUT < VIN (pin voltage) 2. VOUT < 17.5V 3. VOUT < maximum VGS rating of power MOSFET A resistor RVCC can be connected, as shown in Figure 3, to limit the inrush current from VOUT. Regardless of whether or not the INTVCC pin is connected to an external voltage source, it is always necessary to have the driver circuitry bypassed with a 4.7μF low ESR ceramic capacitor to ground immediately adjacent to the INTVCC and GND pins. Figure 3. Connecting INTVCC to VOUT CVCC 4.7μF VOUT 3757 F03 INTVCC GND LT3757 RVCC DVCC Operating Frequency and Synchronization The choice of operating frequency may be determined by on-chip power dissipation, otherwise it is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing gate drive current and MOSFET and diode switching losses. However, lower frequency operation requires a physically larger inductor. Switching frequency also has implications for loop compensation. The LT3757 uses a constant-frequency architecture that can be programmed over a 100kHz to 1000kHz range with a single external resistor from the RT pin to ground, as shown in Figure 1. The RT pin must have an external resistor to GND for proper operation of the LT3757. A table for selecting the value of RT for a given operating frequency is shown in Table 1. Table 1. Timing Resistor (RT) Value OSCILLATOR FREQUENCY (kHz) RT (kΩ) 100 140 200 63.4 300 41.2 400 30.9 500 24.3 600 19.6 700 16.5 800 14 900 12.1 1000 10.5 The operating frequency of the LT3757 can be synchronized to an external clock source. By providing a digital clock signal into the SYNC pin, the LT3757 will operate at the SYNC clock frequency. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than SYNC pulse frequency. The SYNC pulse should have a minimum pulse width of 200ns. Tie the SYNC pin to GND if this feature is not used. LT3757/LT3757A 12 3757afd Applications Information Duty Cycle Consideration Switching duty cycle is a key variable defining converter operation. As such, its limits must be considered. Minimum on-time is the smallest time duration that the LT3757 is capable of turning on the power MOSFET. This time is generally about 220ns (typical) (see Minimum On-Time in the Electrical Characteristics table). In each switching cycle, the LT3757 keeps the power switch off for at least 220ns (typical) (see Minimum Off-Time in the Electrical Characteristics table). The minimum on-time and minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate: Minimum duty cycle = minimum on-time • frequency Maximum duty cycle = 1 – (minimum off-time • frequency) Programming the Output Voltage The output voltage (VOUT) is set by a resistor divider, as shown in Figure 1. The positive and negative VOUT are set by the following equations: VOUT,POSITIVE = 1.6V • 1+ R2 R1     VOUT,NEGATIVE = –0.8V • 1+ R2 R1     The resistors R1 and R2 are typically chosen so that the error caused by the current flowing into the FBX pin during normal operation is less than 1% (this translates to a maximum value of R1 at about 158k). In the applications where VOUT is pulled up by an external positive power supply, the FBX pin is also pulled up through the R2 and R1 network. Make sure the FBX does not exceed its absolute maximum rating (6V). The R5, D2, and D3 in Figure 1 provide a resistive clamp in the positive direction. To ensure FBX is lower than 6V, choose sufficiently large R1 and R2 to meet the following condition: 6V • 1+ R2 R1    + 3.5V • R2 8kΩ > VOUT(MAX) where VOUT(MAX) is the maximum VOUT that is pulled up by an external power supply. Soft-Start The LT3757 contains several features to limit peak switch currents and output voltage (VOUT) overshoot during start-up or recovery from a fault condition. The primary purpose of these features is to prevent damage to external components or the load. High peak switch currents during start-up may occur in switching regulators. Since VOUT is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. A large surge current may cause inductor saturation or power switch failure. The LT3757 addresses this mechanism with the SS pin. As shown in Figure 1, the SS pin reduces the power MOSFET current by pulling down the VC pin through Q2. In this way the SS allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. The typical start-up waveforms are shown in the Typical Performance Characteristics section. The inductor current IL slewing rate is limited by the soft-start function. Besides start-up, soft-start can also be triggered by the following faults: 1. INTVCC > 17.5V 2. INTVCC < 2.6V 3. Thermal lockout Any of these three faults will cause the LT3757 to stop switching immediately. The SS pin will be discharged by Q3. When all faults are cleared and the SS pin has been discharged below 0.2V, a 10μA current source IS2 starts charging the SS pin, initiating a soft-start operation. The soft-start interval is set by the soft-start capacitor selection according to the equation: TSS =CSS • 1.25V 10μA LT3757/LT3757A 13 3757afd Applications Information FBX Frequency Foldback When VOUT is very low during start-up or a short-circuit fault on the output, the switching regulator must operate at low duty cycles to maintain the power switch current within the current limit range, since the inductor current decay rate is very low during switch off time. The minimum on-time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. So, the switch current will keep increasing through each switch cycle, exceeding the programmed current limit. To prevent the switch peak currents from exceeding the programmed value, the LT3757 contains a frequency foldback function to reduce the switching frequency when the FBX voltage is low (see the Normalized Switching Frequency vs FBX graph in the Typical Performance Characteristics section). The typical frequency foldback waveforms are shown in the Typical Performance Characteristics section. The frequency foldback function prevents IL from exceeding the programmed limits because of the minimum on-time. During frequency foldback, external clock synchronization is disabled to prevent interference with frequency reducing operation. Thermal Lockout If LT3757 die temperature reaches 165°C (typical), the part will go into thermal lockout. The power switch will be turned off. A soft-start operation will be triggered. The part will be enabled again when the die temperature has dropped by 5°C (nominal). Loop Compensation Loop compensation determines the stability and transient performance. The LT3757/LT3757A use current mode control to regulate the output which simplifies loop compensation. The LT3757A improves the no-load to heavy load transient response, when compared to the LT3757. New internal circuits ensure that the transient from not switching to switching at high current can be made in a few cycles. The optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). To compensate the feedback loop of the LT3757/LT3757A, a series resistorcapacitor network is usually connected from the VC pin to GND. Figure 1 shows the typical VC compensation network. For most applications, the capacitor should be in the range of 470pF to 22nF, and the resistor should be in the range of 5k to 50k. A small capacitor is often connected in parallel with the RC compensation network to attenuate the VC voltage ripple induced from the output voltage ripple through the internal error amplifier. The parallel capacitor usually ranges in value from 10pF to 100pF. A practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage and temperature. SENSE Pin Programming For control and protection, the LT3757 measures the power MOSFET current by using a sense resistor (RSENSE) between GND and the MOSFET source. Figure 4 shows a typical waveform of the sense voltage (VSENSE) across the sense resistor. It is important to use Kelvin traces between the SENSE pin and RSENSE, and to place the IC GND as close as possible to the GND terminal of the RSENSE for proper operation. Figure 4. The Sense Voltage During a Switching Cycle 3757 F04 VSENSE(PEAK) ΔVSENSE = χ • VSENSE(MAX) VSENSE DT t S VSENSE(MAX) TS LT3757/LT3757A 14 3757afd Applications Information Due to the current limit function of the SENSE pin, RSENSE should be selected to guarantee that the peak current sense voltage VSENSE(PEAK) during steady state normal operation is lower than the SENSE current limit threshold (see the Electrical Characteristics table). Given a 20% margin, VSENSE(PEAK) is set to be 80mV. Then, the maximum switch ripple current percentage can be calculated using the following equation: c = ΔVSENSE 80mV − 0.5 • ΔVSENSE c is used in subsequent design examples to calculate inductor value. ΔVSENSE is the ripple voltage across RSENSE. The LT3757 switching controller incorporates 100ns timing interval to blank the ringing on the current sense signal immediately after M1 is turned on. This ringing is caused by the parasitic inductance and capacitance of the PCB trace, the sense resistor, the diode, and the MOSFET. The 100ns timing interval is adequate for most of the LT3757 applications. In the applications that have very large and long ringing on the current sense signal, a small RC filter can be added to filter out the excess ringing. Figure 5 shows the RC filter on SENSE pin. It is usually sufficient to choose 22Ω for RFLT and 2.2nF to 10nF for CFLT. Keep RFLT’s resistance low. Remember that there is 65μA (typical) flowing out of the SENSE pin. Adding RFLT will affect the SENSE current limit threshold: VSENSE_ILIM = 108mV – 65μA • RFLT Application Circuits The LT3757 can be configured as different topologies. The first topology to be analyzed will be the boost converter, followed by the flyback, SEPIC and inverting converters. Boost Converter: Switch Duty Cycle and Frequency The LT3757 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. Remember that boost converters are not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply capability. For applications requiring a step-up converter that is short-circuit protected, please refer to the Applications Information section covering SEPIC converters. The conversion ratio as a function of duty cycle is VOUT VIN = 1 1−D in continuous conduction mode (CCM). For a boost converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (VOUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT − VIN(MIN) VOUT Discontinuous conduction mode (DCM) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies and higher switching currents. Figure 5. The RC Filter on SENSE Pin CFLT 3757 F05 LT3757 RFLT RSENSE M1 SENSE GATE GND LT3757/LT3757A 15 3757afd Applications Information Boost Converter: Inductor and Sense Resistor Selection For the boost topology, the maximum average inductor current is: IL(MAX) =IO(MAX) • 1 1−DMAX Then, the ripple current can be calculated by: ΔIL = c •IL(MAX) = c •IO(MAX) • 1 1−DMAX The constant c in the preceding equation represents the percentage peak-to-peak ripple current in the inductor, relative to IL(MAX). The inductor ripple current has a direct effect on the choice of the inductor value. Choosing smaller values of ΔIL requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ΔIL provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses. It is recommended that c fall within the range of 0.2 to 0.6. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: L = VIN(MIN) ΔIL • f •DMAX The peak and RMS inductor current are: IL(PEAK) =IL(MAX) • 1+ c 2     IL(RMS) =IL(MAX) • 1+ c2 12 Based on these equations, the user should choose the inductors having sufficient saturation and RMS current ratings. Set the sense voltage at IL(PEAK) to be the minimum of the SENSE current limit threshold with a 20% margin. The sense resistor value can then be calculated to be: RSENSE = 80mV IL(PEAK) Boost Converter: Power MOSFET Selection Important parameters for the power MOSFET include the drain-source voltage rating (VDS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)), the gate to source and gate to drain charges (QGS and QGD), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RθJC and RθJA). The power MOSFET will see full output voltage, plus a diode forward voltage, and any additional ringing across its drain-to-source during its off-time. It is recommended to choose a MOSFET whose BVDSS is higher than VOUT by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the MOSFET in a boost converter is: PFET = I2 L(MAX) • RDS(ON) • DMAX + 2 • V2 OUT • IL(MAX) • CRSS • f /1A The first term in the preceding equation represents the conduction losses in the device, and the second term, the switching loss. CRSS is the reverse transfer capacitance, which is usually specified in the MOSFET characteristics. For maximum efficiency, RDS(ON) and CRSS should be minimized. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following equation: TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA) TJ must not exceed the MOSFET maximum junction temperature rating. It is recommended to measure the MOSFET temperature in steady state to ensure that absolute maximum ratings are not exceeded. LT3757/LT3757A 16 3757afd Applications Information Figure 6. The Output Ripple Waveform of a Boost Converter VOUT (AC) tON ΔVESR RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) ΔVCOUT 3757 F05 tOFF Boost Converter: Output Diode Selection To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. The average forward current in normal operation is equal to the output current, and the peak current is equal to: ID(PEAK) =IL(PEAK) = 1+ c 2     •IL(MAX) It is recommended that the peak repetitive reverse voltage rating VRRM is higher than VOUT by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA to be used in this equation normally includes the RθJC for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Boost Converter: Output Capacitor Selection Contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. The effect of The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step ΔVESR and the charging/discharging ΔVCOUT. For the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ΔVESR and ΔVCOUT. This percentage ripple will change, depending on the requirements of the application, and the following equations can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: ESRCOUT ≤ 0.01• VOUT ID(PEAK) these three parameters (ESR, ESL and bulk C) on the output voltage ripple waveform for a typical boost converter is illustrated in Figure 6. LT3757/LT3757A 17 3757afd Applications Information For the bulk C component, which also contributes 1% to the total ripple: COUT ≥ IO(MAX) 0.01• VOUT • f The output capacitor in a boost regulator experiences high RMS ripple currents, as shown in Figure 6. The RMS ripple current rating of the output capacitor can be determined using the following equation: IRMS(COUT) ≥IO(MAX) • DMAX 1−DMAX Multiple capacitors are often paralleled to meet ESR requirements. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the required RMS current rating. Additional ceramic capacitors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. Boost Converter: Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current waveform is continuous. The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10μF to 100μF. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost converter is: IRMS(CIN) = 0.3 • ΔIL Flyback Converter Applications The LT3757 can be configured as a flyback converter for the applications where the converters have multiple outputs, high output voltages or isolated outputs. Figure 7 shows a simplified flyback converter. The flyback converter has a very low parts count for multiple outputs, and with prudent selection of turns ratio, can have high output/input voltage conversion ratios with a desirable duty cycle. However, it has low efficiency due to the high peak currents, high peak voltages and consequent power loss. The flyback converter is commonly used for an output power of less than 50W. The flyback converter can be designed to operate either in continuous or discontinuous mode. Compared to continuous mode, discontinuous mode has the advantage of smaller transformer inductances and easy loop compensation, and the disadvantage of higher peak-to-average current and lower efficiency. In the high output voltage applications, the flyback converters can be designed to operate in discontinuous mode to avoid using large transformers. Figure 7. A Simplified Flyback Converter RSENSE NP:NS VIN CIN CSN VSN LP D SUGGESTED RCD SNUBBER ID ISW VDS 3757 F06 GATE GND LT3757 SENSE LS M + – + – RSN DSN – + + COUT + LT3757/LT3757A 18 3757afd Applications Information Flyback Converter: Switch Duty Cycle and Turns Ratio The flyback converter conversion ratio in the continuous mode operation is: VOUT VIN = NS NP • D 1−D where NS/NP is the second to primary turns ratio. Figure 8 shows the waveforms of the flyback converter in discontinuous mode operation. During each switching period TS, three subintervals occur: DTS, D2TS, D3TS. During DTS, M is on, and D is reverse-biased. During D2TS, M is off, and LS is conducting current. Both LP and LS currents are zero during D3TS. The flyback converter conversion ratio in the discontinuous mode operation is: VOUT VIN = NS NP • D D2 According to the preceding equations, the user has relative freedom in selecting the switch duty cycle or turns ratio to suit a given application. The selections of the duty cycle and the turns ratio are somewhat iterative processes, due to the number of variables involved. The user can choose either a duty cycle or a turns ratio as the start point. The following trade-offs should be considered when selecting the switch duty cycle or turns ratio, to optimize the converter performance. A higher duty cycle affects the flyback converter in the following aspects: • Lower MOSFET RMS current ISW(RMS), but higher MOSFET VDS peak voltage • Lower diode peak reverse voltage, but higher diode RMS current ID(RMS) • Higher transformer turns ratio (NP/NS) The choice, D D+D2 = 1 3 (for discontinuous mode operation with a given D3) gives the power MOSFET the lowest power stress (the product of RMS current and peak voltage). However, in the high output voltage applications, a higher duty cycle may be adopted to limit the large peak reverse voltage of the diode. The choice, D D+D2 = 2 3 (for discontinuous mode operation with a given D3) gives the diode the lowest power stress (the product of RMS current and peak voltage). An extreme high or low duty cycle results in high power stress on the MOSFET or diode, and reduces efficiency. It is recommended to choose a duty cycle, D, between 20% and 80%. Figure 8. Waveforms of the Flyback Converter in Discontinuous Mode Operation 3757 F07 ISW VDS ID DTS D2TS D3TS t ISW(MAX) ID(MAX) TS LT3757/LT3757A 19 3757afd Applications Information Flyback Converter: Transformer Design for Discontinuous Mode Operation The transformer design for discontinuous mode of operation is chosen as presented here. According to Figure 8, the minimum D3 (D3MIN) occurs when the converter has the minimum VIN and the maximum output power (POUT). Choose D3MIN to be equal to or higher than 10% to guarantee the converter is always in discontinuous mode operation (choosing higher D3 allows the use of low inductances, but results in a higher switch peak current). The user can choose a DMAX as the start point. Then, the maximum average primary currents can be calculated by the following equation: ILP(MAX) =ISW(MAX) = POUT(MAX) DMAX • VIN(MIN) • h where h is the converter efficiency. If the flyback converter has multiple outputs, POUT(MAX) is the sum of all the output power. The maximum average secondary current is: ILS(MAX) =ID(MAX) = IOUT(MAX) D2 where: D2 = 1 – DMAX – D3 the primary and secondary RMS currents are: ILP(RMS) = 2 •ILP(MAX) • DMAX 3 ILS(RMS) = 2 •ILS(MAX) • D2 3 According to Figure 8, the primary and secondary peak currents are: ILP(PEAK) = ISW(PEAK) = 2 • ILP(MAX) ILS(PEAK) = ID(PEAK) = 2 • ILS(MAX) The primary and second inductor values of the flyback converter transformer can be determined using the following equations: LP = D2 MAX • V2 IN(MIN) • h 2 • POUT(MAX) • f LS = D22 • (VOUT + VD) 2 • IOUT(MAX) • f The primary to second turns ratio is: NP NS = LP LS Flyback Converter: Snubber Design Transformer leakage inductance (on either the primary or secondary) causes a voltage spike to occur after the MOSFET turn-off. This is increasingly prominent at higher load currents, where more stored energy must be dissipated. In some cases a snubber circuit will be required to avoid overvoltage breakdown at the MOSFET’s drain node. There are different snubber circuits, and Application Note 19 is a good reference on snubber design. An RCD snubber is shown in Figure 7. The snubber resistor value (RSN) can be calculated by the following equation: RSN = 2 • V2 SN − VSN • VOUT • NP NS I2 SW(PEAK) •LLK • f LT3757/LT3757A 20 3757afd Applications Information where VSN is the snubber capacitor voltage. A smaller VSN results in a larger snubber loss. A reasonable VSN is 2 to 2.5 times of: VOUT •NP NS LLK is the leakage inductance of the primary winding, which is usually specified in the transformer characteristics. LLK can be obtained by measuring the primary inductance with the secondary windings shorted. The snubber capacitor value (CCN) can be determined using the following equation: CCN = VSN ΔVSN •RCN • f where ΔVSN is the voltage ripple across CCN. A reasonable ΔVSN is 5% to 10% of VSN. The reverse voltage rating of DSN should be higher than the sum of VSN and VIN(MAX). Flyback Converter: Sense Resistor Selection In a flyback converter, when the power switch is turned on, the current flowing through the sense resistor (ISENSE) is: ISENSE = ILP Set the sense voltage at ILP(PEAK) to be the minimum of the SENSE current limit threshold with a 20% margin. The sense resistor value can then be calculated to be: RSENSE = 80mV ILP(PEAK) Flyback Converter: Power MOSFET Selection For the flyback configuration, the MOSFET is selected with a VDC rating high enough to handle the maximum VIN, the reflected secondary voltage and the voltage spike due to the leakage inductance. Approximate the required MOSFET VDC rating using: BVDSS > VDS(PEAK) where: VDS(PEAK) = VIN(MAX) + VSN The power dissipated by the MOSFET in a flyback converter is: PFET = I2 M(RMS) • RDS(ON) + 2 • V2 DS(PEAK) • IL(MAX) • CRSS • f /1A The first term in this equation represents the conduction losses in the device, and the second term, the switching loss. CRSS is the reverse transfer capacitance, which is usually specified in the MOSFET characteristics. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following equation: TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA) TJ must not exceed the MOSFET maximum junction temperature rating. It is recommended to measure the MOSFET temperature in steady state to ensure that absolute maximum ratings are not exceeded. LT3757/LT3757A 21 3757afd Applications Information Flyback Converter: Output Diode Selection The output diode in a flyback converter is subject to large RMS current and peak reverse voltage stresses. A fast switching diode with a low forward drop and a low reverse leakage is desired. Schottky diodes are recommended if the output voltage is below 100V. Approximate the required peak repetitive reverse voltage rating VRRM using: VRRM > NS NP • VIN(MAX) + VOUT The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA to be used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Flyback Converter: Output Capacitor Selection The output capacitor of the flyback converter has a similar operation condition as that of the boost converter. Refer to the Boost Converter: Output Capacitor Selection section for the calculation of COUT and ESRCOUT. The RMS ripple current rating of the output capacitors in discontinuous operation can be determined using the following equation: IRMS(COUT),DISCONTINUOUS ≥ IO(MAX) • 4 − (3 •D2) 3 •D2 Flyback Converter: Input Capacitor Selection The input capacitor in a flyback converter is subject to a large RMS current due to the discontinuous primary current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum RMS current. The RMS ripple current rating of the input capacitors in discontinuous operation can be determined using the following equation: IRMS(CIN),DISCONTINUOUS ≥ POUT(MAX) VIN(MIN) • h • 4 − (3 •DMAX ) 3 •DMAX SEPIC Converter Applications The LT3757 can be configured as a SEPIC (single-ended primary inductance converter), as shown in Figure 1. This topology allows for the input to be higher, equal, or lower than the desired output voltage. The conversion ratio as a function of duty cycle is: VOUT + VD VIN = D 1−D in continuous conduction mode (CCM). In a SEPIC converter, no DC path exists between the input and output. This is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. Compared to the flyback converter, the SEPIC converter has the advantage that both the power MOSFET and the output diode voltages are clamped by the capacitors (CIN, CDC and COUT), therefore, there is less voltage ringing across the power MOSFET and the output diodes. The SEPIC converter requires much smaller input capacitors than those of the flyback converter. This is due to the fact that, in the SEPIC converter, the inductor L1 is in series with the input, and the ripple current flowing through the input capacitor is continuous. LT3757/LT3757A 22 3757afd Applications Information Figure 9. The Switch Current Waveform of the SEPIC Converter 3757 F08 ΔISW = χ • ISW(MAX) ISW DT t S ISW(MAX) TS SEPIC Converter: Switch Duty Cycle and Frequency For a SEPIC converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (VOUT), the input voltage (VIN) and the diode forward voltage (VD). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT + VD VIN(MIN) + VOUT + VD SEPIC Converter: Inductor and Sense Resistor Selection As shown in Figure 1, the SEPIC converter contains two inductors: L1 and L2. L1 and L2 can be independent, but can also be wound on the same core, since identical voltages are applied to L1 and L2 throughout the switching cycle. For the SEPIC topology, the current through L1 is the converter input current. Based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of L1 and L2 are: IL1(MAX) = IIN(MAX) = IO(MAX) • DMAX 1− DMAX IL2(MAX) = IO(MAX) In a SEPIC converter, the switch current is equal to IL1 + IL2 when the power switch is on, therefore, the maximum average switch current is defined as: ISW(MAX) =IL1(MAX) +IL2(MAX) =IO(MAX) • 1 1−DMAX and the peak switch current is: ISW(PEAK) = 1+ c 2     •IO(MAX) • 1 1−DMAX The constant c in the preceding equations represents the percentage peak-to-peak ripple current in the switch, relative to ISW(MAX), as shown in Figure 9. Then, the switch ripple current ΔISW can be calculated by: ΔISW = c • ISW(MAX) The inductor ripple currents ΔIL1 and ΔIL2 are identical: ΔIL1 = ΔIL2 = 0.5 • ΔISW The inductor ripple current has a direct effect on the choice of the inductor value. Choosing smaller values of ΔIL requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ΔIL allows the use of low inductances, but results in higher input current ripple and greater core losses. It is recommended that c falls in the range of 0.2 to 0.4. LT3757/LT3757A 23 3757afd Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value (L1 and L2 are independent) of the SEPIC converter can be determined using the following equation: L1=L2 = VIN(MIN) 0.5 • ΔISW • f •DMAX For most SEPIC applications, the equal inductor values will fall in the range of 1μH to 100μH. By making L1 = L2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2L, due to mutual inductance: L = VIN(MIN) ΔISW • f •DMAX This maintains the same ripple current and energy storage in the inductors. The peak inductor currents are: IL1(PEAK) = IL1(MAX) + 0.5 • ΔIL1 IL2(PEAK) = IL2(MAX) + 0.5 • ΔIL2 The RMS inductor currents are: IL1(RMS) =IL1(MAX) • 1+ c2 L1 12 where: cL1 = ΔIL1 IL1(MAX) IL2(RMS) =IL2(MAX) • 1+ c2 L2 12 where: cL2 = ΔIL2 IL2 (MAX) Based on the preceding equations, the user should choose the inductors having sufficient saturation and RMS current ratings. In a SEPIC converter, when the power switch is turned on, the current flowing through the sense resistor (ISENSE) is the switch current. Set the sense voltage at ISENSE(PEAK) to be the minimum of the SENSE current limit threshold with a 20% margin. The sense resistor value can then be calculated to be: RSENSE = 80mV ISW(PEAK) SEPIC Converter: Power MOSFET Selection For the SEPIC configuration, choose a MOSFET with a VDC rating higher than the sum of the output voltage and input voltage by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the MOSFET in a SEPIC converter is: PFET = I2 SW(MAX) • RDS(ON) • DMAX + 2 • (VIN(MIN) + VOUT)2 • IL(MAX) • CRSS • f /1A The first term in this equation represents the conduction losses in the device, and the second term, the switching loss. CRSS is the reverse transfer capacitance, which is usually specified in the MOSFET characteristics. For maximum efficiency, RDS(ON) and CRSS should be minimized. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following equation: TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA) TJ must not exceed the MOSFET maximum junction temperature rating. It is recommended to measure the MOSFET temperature in steady state to ensure that absolute maximum ratings are not exceeded. Applications Information LT3757/LT3757A 24 3757afd Applications Information Figure 10. A Simplified Inverting Converter RSENSE CDC VIN CIN L1 D1 COUT VOUT 3757 F09 GATE + GND LT3757 SENSE L2 M1 + – + – + SEPIC Converter: Output Diode Selection To maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. The average forward current in normal operation is equal to the output current, and the peak current is equal to: ID(PEAK) = 1+ c 2     •IO(MAX) • 1 1−DMAX It is recommended that the peak repetitive reverse voltage rating VRRM is higher than VOUT + VIN(MAX) by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. SEPIC Converter: Output and Input Capacitor Selection The selections of the output and input capacitors of the SEPIC converter are similar to those of the boost converter. Please refer to the Boost Converter, Output Capacitor Selection and Boost Converter, Input Capacitor Selection sections. SEPIC Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 1) should be larger than the maximum input voltage: VCDC > VIN(MAX) CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the coupling capacitor is determined by the following equation: IRMS(CDC) > IO(MAX) • VOUT + VD VIN(MIN) A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. Inverting Converter Applications The LT3757 can be configured as a dual-inductor inverting topology, as shown in Figure 10. The VOUT to VIN ratio is: VOUT − VD VIN = − D 1−D in continuous conduction mode (CCM). LT3757/LT3757A 25 3757afd Inverting Converter: Switch Duty Cycle and Frequency For an inverting converter operating in CCM, the duty cycle of the main switch can be calculated based on the negative output voltage (VOUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT − VD VOUT − VD − VIN(MIN) Inverting Converter: Inductor, Sense Resistor, Power MOSFET, Output Diode and Input Capacitor Selections The selections of the inductor, sense resistor, power MOSFET, output diode and input capacitor of an inverting converter are similar to those of the SEPIC converter. Please refer to the corresponding SEPIC converter sections. Inverting Converter: Output Capacitor Selection The inverting converter requires much smaller output capacitors than those of the boost, flyback and SEPIC converters for similar output ripples. This is due to the fact that, in the inverting converter, the inductor L2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. The output ripple voltage is produced by the ripple current of L2 flowing through the ESR and bulk capacitance of the output capacitor: ΔVOUT(P–P) = ΔIL2 • ESRCOUT + 1 8 • f •COUT       After specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. The ESR can be minimized by using high quality X5R or X7R dielectric ceramic capacitors. In many applications, ceramic capacitors are sufficient to limit the output voltage ripple. The RMS ripple current rating of the output capacitor needs to be greater than: IRMS(COUT) > 0.3 • ΔIL2 Inverting Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 10) should be larger than the maximum input voltage minus the output voltage (negative voltage): VCDC > VIN(MAX) – VOUT CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the coupling capacitor is determined by the following equation: IRMS(CDC) >IO(MAX) • DMAX 1−DMAX A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. Applications Information LT3757/LT3757A 26 3757afd Applications Information Figure 11. 8V to 16V Input, 24V/2A Output Boost Converter Suggested Layout VIN 3757 F10 VOUT L1 VIAS TO GROUND PLANE C D1 COUT2 OUT1 1 2 8 7 3 4 6 5 M1 CIN R4 RC R1 R2 RSS RT R3 CVCC CC1 CC2 LT3757 1 2 3 4 5 9 10 6 7 8 RS Board Layout The high speed operation of the LT3757 demands careful attention to board layout and component placement. The Exposed Pad of the package is the only GND terminal of the IC, and is important for thermal management of the IC. Therefore, it is crucial to achieve a good electrical and thermal contact between the Exposed Pad and the ground plane of the board. For the LT3757 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC is essential, especially the power paths with higher di/ dt. The following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: • In boost configuration, the high di/dt loop contains the output capacitor, the sensing resistor, the power MOSFET and the Schottky diode. • In flyback configuration, the high di/dt primary loop contains the input capacitor, the primary winding, the power MOSFET and the sensing resistor. The high di/ dt secondary loop contains the output capacitor, the secondary winding and the output diode. • In SEPIC configuration, the high di/dt loop contains the power MOSFET, sense resistor, output capacitor, Schottky diode and the coupling capacitor. • In inverting configuration, the high di/dt loop contains power MOSFET, sense resistor, Schottky diode and the coupling capacitor. LT3757/LT3757A 27 3757afd Table 2. Recommended Component Manufacturers VENDOR COMPONENTS WEB ADDRESS AVX Capacitors avx.com BH Electronics Inductors, Transformers bhelectronics.com Coilcraft Inductors coilcraft.com Cooper Bussmann Inductors bussmann.com Diodes, Inc Diodes diodes.com Fairchild MOSFETs fairchildsemi.com General Semiconductor Diodes generalsemiconductor.com International Rectifier MOSFETs, Diodes irf.com IRC Sense Resistors irctt.com Kemet Capacitors kemet.com Magnetics Inc Toroid Cores mag-inc.com Microsemi Diodes microsemi.com Murata-Erie Inductors, Capacitors murata.co.jp Nichicon Capacitors nichicon.com On Semiconductor Diodes onsemi.com Panasonic Capacitors panasonic.com Sanyo Capacitors sanyo.co.jp Sumida Inductors sumida.com Taiyo Yuden Capacitors t-yuden.com TDK Capacitors, Inductors component.tdk.com Thermalloy Heat Sinks aavidthermalloy.com Tokin Capacitors nec-tokinamerica.com Toko Inductors tokoam.com United Chemi-Con Capacitors chemi-con.com Vishay/Dale Resistors vishay.com Vishay/Siliconix MOSFETs vishay.com Vishay/Sprague Capacitors vishay.com Würth Elektronik Inductors we-online.com Zetex Small-Signal Discretes zetex.com Applications Information Check the stress on the power MOSFET by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the PC board). Beware of inductive ringing, which can exceed the maximum specified voltage rating of the MOSFET. If this ringing cannot be avoided, and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalancherated power MOSFET. The small-signal components should be placed away from high frequency switching nodes. For optimum load regulation and true remote sensing, the top of the output voltage sensing resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LT3757 in order to keep the high impedance FBX node short. Figure 11 shows the suggested layout of the 8V to 16V Input, 24V/2A Output Boost Converter. Recommended Component Manufacturers Some of the recommended component manufacturers are listed in Table 2. LT3757/LT3757A 28 3757afd Typical Applications 3.3V Input, 5V/10A Output Boost Converter Boost Preregulator for Automotive Stop-Start/Idle Efficiency vs Output Current Transient VIN and VOUT Waveforms SENSE LT3757 VIN VIN 3.3V CIN 22μF 6.3V ×2 VOUT 5V 10A 0.004 1W M1 41.2k 300kHz GATE FBX GND INTVCC SHDN/UVLO SYNC RT SS VC 49.9k 34k 0.1μF 6.8k 22nF 2.2nF 22 L1 0.5μH D1 3757 TA02a 34k 1% 15.8k 1% COUT1 150μF 6.3V ×4 COUT2 22μF 6.3V X5R ×4 + CVCC 4.7μF 10V X5R CIN: TAIYO YUDEN JMK325BJ226MM COUT1: PANASONIC EEFUEOJ151R COUT2: TAIYO YUDEN JMK325BJ226MM D1: MBRB2515L L1: VISHAY SILICONIX IHLP-5050FD-01 M1: VISHAY SILICONIX SI4448DY OUTPUT CURRENT (A) EFFICIENCY (%) 3757 TA02b 0.001 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 SENSE LT3757A VIN VIN 3V TO 36V 10μF 50V X5R ×2 VOUT 9VMIN 2A 41.2k 300kHz GATE FBX GND INTVCC SHDN/UVLO SYNC RT SS VC 1M 698k 0.1μF 10k 10nF 4.7μF L1 3.3μH D1 3757 TA03a M1 75k 8m 16.2k C1 10μF 50V ×4 + 10μF 50V X5R L1: COILTRONIX DR127-3R3 M1: VISHAY SILICONIX Si7848BDP D1: VISHAY SILICONIX 50SQ04FN C1: KEMET T495X106K050A 10ms/DIV VOUT 5V/DIV VIN 5V/DIV 0V 3757 TA03b OUTPUT POWER = 10W LT3757/LT3757A 29 3757afd Typical Applications 8V to 16V Input, 24V/2A Output Boost Converter Efficiency vs Output Current Load Step Response at VIN = 12V SENSE LT3757 VIN VIN 8V TO 16V CIN 10μF 25V X5R CVCC 4.7μF 10V X5R VOUT 24V 2A RS 0.01 1W M1 RT 41.2k 300kHz GATE FBX GND INTVCC SHDN/UVLO SYNC RT SS VC R3 200k R4 43.2k CSS 0.1μF CC2 100pF RC 22k CC1 6.8nF L1 10μH D1 3757 TA04a R2 226k 1% R1 16.2k 1% COUT1 47μF 35V ×4 COUT2 10μF 25V X5R + CIN, COUT2: MURATA GRM31CR61E106KA12 COUT1: KEMET T495X476K035AS D1: ON SEMI MBRS340T3G L1: VISHAY SILICONIX IHLP-5050FD-01 10μH M1: VISHAY SILICONIX Si4840BDP OUTPUT CURRENT (A) 0.001 EFFICIENCY (%) 30 50 40 60 70 80 90 100 0.01 0.1 1 3757 TA04b 10 VIN = 8V VIN = 16V 500μs/DIV VOUT 500mV/DIV (AC) 1.6A 0.4A IOUT 1A/DIV 3757 TA04c LT3757/LT3757A 30 3757afd 2ms/DIV VOUT 100V/DIV 3757 TA05b 5μs/DIV VOUT 5V/DIV (AC) VSW 20V/DIV 3757 TA05c Typical Applications High Voltage Flyback Power Supply Start-Up Waveforms Switching Waveforms SENSE LT3757 VIN VSW VIN 5V TO 12V CIN 47μF 16V ×4 INTVCC COUT 68nF ×2 VOUT 350V 10mA 0.02 22 M1 140k 100kHz GATE GND FBX SHDN/UVLO DANGER! HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY SYNC RT SS VC • 105k • 46.4k 0.1μF 220pF 100pF 6.8k 22nF T1 1:10 D1 CIN: MURATA GRM32ER61C476K COUT: TDK C3225X7R2J683K D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES M1: VISHAY SILICONIX Si7850DP T1: TDK DCT15EFD-U44S003 3757 TA05a 1M 1% 1M 1% 1.50M 1% 16.2k 1% 10nF CVCC 47μF 25V X5R 22 LT3757/LT3757A 31 3757afd Typical Applications 5.5V to 36V Input, 12V/2A Output SEPIC Converter Efficiency vs Output Current Load Step Waveforms Start-Up Waveforms Frequency Foldback Waveforms When Output Short-Circuits SENSE LT3757A VIN VIN 5.5V TO 36V CIN1 4.7μF 50V ×2 CDC 4.7μF 50V, X5R, ×2 4.7μF 10V X5R VOUT 12V 2A 0.01 1W M1 41.2k 300kHz GATE FBX GND INTVCC SHDN/UVLO SYNC RT SS CIN2 4.7μF 50V ×2 • • 105k 46.4k 0.1μF 6.8nF 10k L1A IL1B L1B D1 CIN1, CDC: TAIYO YUDEN UMK316BJ475KL CIN2: KEMET T495X475K050AS COUT1: KEMET T495X476K020AS COUT2: TAIYO YUDEN TMK432BJ106MM D1: ON SEMI MBRS360T3G L1A, L1B: COILTRONICS DRQ127-4R7 (*COUPLED INDUCTORS) M1: VISHAY SILICONIX Si7460DP 3757 TA06a 105k 1% 15.8k 1% COUT1 47μF 20V ×4 COUT2 10μF 25V X5R + VSW IL1A VC + 2ms/DIV VOUT 5V/DIV IL1A + IL1B 5A/DIV 3757 TA06d VIN = 12V 50μs/DIV VOUT 10V/DIV VSW 20V/DIV IL1A + IL1B 5A/DIV 3757 TA06e VIN = 12V OUTPUT CURRENT (A) 0.001 20 EFFICIENCY (%) 30 40 50 60 70 80 90 100 0.01 0.1 1 3757 TA06b 10 VIN = 16V VIN = 8V 500μs/DIV VOUT 2V/DIV AC-COUPLED IOUT 2A/DIV 0A 2A 3757 TA06c VIN = 12V LT3757/LT3757A 32 3757afd Typical Applications 5V to 12V Input, ±12V/0.4A Output SEPIC Converter Nonisolated Inverting SLIC Supply SENSE LT3757 VIN VIN 5V TO 12V CIN1 1μF 16V, X5R CIN2 47μF 16V CDC1 4.7μF 16V, X5R CDC2 4.7μF 16V X5R COUT2 4.7μF 16V, X5R ×3 VOUT1 12V 0.4A VOUT2 –12V 0.4A COUT2 4.7μF 16V, X5R ×3 CVCC 4.7μF 10V X5R 0.02 M1 30.9k 400kHz D1, D2: MBRS140T3 T1: COILTRONICS VP1-0076 (*PRIMARY = 4 WINDINGS IN PARALLEL) M1: SILICONIX/VISHAY Si4840BDY GATE FBX GND INTVCC SHDN/UVLO SYNC RT SS + 105k • 46.4k 0.1μF 100pF 22k 6.8nF T1 1,2,3,4 D1 GND 1.05k 1% 158 1% D2 5 6 • • 3757 TA07 VC SENSE LT3757 VIN VIN 5V TO 16V CIN 22μF 25V, X5R ×2 C2 10μF 50V X5R D1 DFLS160 CVCC 4.7μF 10V, X5R C3 22μF 25V X5R C4 22μF 25V X5R COUT 3.3μF 100V GND C5 22μF 25V X5R VOUT1 –24V 200mA VOUT1 –72V 200mA 0.012 0.5W M1 Si7850DP 63.4k 200kHz GATE FBX GND INTVCC SHDN/UVLO SYNC RT SS • • • R2 • 105k R1 46.4k 0.1μF 100pF 15.8k 464k 9.1k 10nF T1 1,2,3 4 D2 DFLS160 5 D3 DFLS160 6 VP5-0155 (PRIMARY = 3 WINDINGS IN PARALLEL) 3757 TA08 VC LT3757/LT3757A 33 3757afd Package Description 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.125 TYP 2.38 ±0.10 (2 SIDES) 5 1 6 10 PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.00 – 0.05 (DD) DFN REV C 0310 0.25 ± 0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 0.50 BSC 0.70 ±0.05 3.55 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER LT3757/LT3757A 34 3757afd Package Description MSOP (MSE) 0911 REV H 0.53 ±0.152 (.021 ±.006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 –0.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 1 2 3 4 5 4.90 ±0.152 (.193 ±.006) 0.497 ±0.076 (.0196 ±.003) REF 10 9 8 10 1 7 6 3.00 ±0.102 (.118 ±.004) (NOTE 3) 3.00 ±0.102 (.118 ±.004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ±0.127 (.035 ±.005) RECOMMENDED SOLDER PAD LAYOUT 1.68 ±0.102 (.066 ±.004) 1.88 ±0.102 (.074 ±.004) 0.50 (.0197) BSC 0.305 ± 0.038 (.0120 ±.0015) TYP BOTTOM VIEW OF EXPOSED PAD OPTION 1.68 (.066) 1.88 (.074) 0.1016 ±0.0508 (.004 ±.002) DETAIL “B” DETAIL “B” CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.05 REF 0.29 REF MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev H) LT3757/LT3757A 35 3757afd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. Revision History REV DATE DESCRIPTION PAGE NUMBER B 3/10 Deleted Bullet from Features and Last Line of Description Updated Entire Page to Add H-Grade and Military Grade Updated Electrical Characteristics Notes and Typical Performance Characteristics for H-Grade and Military Grade Revised TA04a and Replaced TA04c in Typical Applications Updated Related Parts 1 2 4 to 6 30 36 C 5/11 Revised MP-grade temperature range in Absolute Maximum Ratings and Order Information sections Revised Note 2 Revised formula in Applications Information Updated Typical Application drawing TA04a values Revised Typical Application title TA06 2 4 19 30 32 D 07/12 Added LT3757A version Throughout Updated Block Diagram 8 Updated Programming the Output Voltage section 12 Updated Loop Compensation section 13 Added an application circuit in the Typical Applications section 28 Updated the schematic and Load Step Waveforms in the Typical Applications section 31 (Revision history begins at Rev B) LT3757/LT3757A 36 3757afd Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2008 LT 0712 REV D • PRINTED IN USA Related Parts Typical Application PART NUMBER DESCRIPTION COMMENTS LT3758A Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages LT3759 Boost, SEPIC and Inverting Controller 1.6V ≤ VIN ≤ 42V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, MSOP-12E Packages LT3957A Boost, Flyback, SEPIC and Inverting Controller with 5A, 40V Switch 3V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 5mm × 6mm QFN Package LT3958 Boost, Flyback, SEPIC and Inverting Controller with 3.3A, 84V Switch 5V ≤ VIN ≤ 80V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 5mm × 6mm QFN Package LT3573/LT3574/ LT3575 40V Isolated Flyback Converters Monolithic No-Opto Flybacks with Integrated 1.25A/0.65A/2.5A Switch LT3511/LT3512 100V Isolated Flyback Converters Monolithic No-Opto Flybacks with Integrated 240mA/420mA Switch LT3798 Offline Isolated No Opto-Coupler Flyback Controller with Active PFC VIN and VOUT Limited Only by External Components, MSOP-16 Package LT3799/LT3799-1 Offline Isolated Flyback LED Controllers with Active PFC VIN and VOUT Limited Only by External Components, MSOP-16 Package High Efficiency Inverting Power Supply Efficiency vs Output Current OUTPUT CURRENT (A) 0.001 10 EFFICIENCY (%) 20 30 40 50 60 70 80 90 100 0.01 0.1 1 3757 TA09b 10 VIN = 16V VIN = 5V SENSE LT3757 VIN VIN 5V TO 15V CIN 47μF 16V X5R CDC 47μF 25V, X5R VOUT –5V 3A to 5A 0.006 1W M1 Si7848BDP 41.2k 300kHz GATE FBX GND INTVCC SHDN/UVLO SYNC RT SS • R2 • 105k R1 46.4k 0.1μF 9.1k 10nF L1 L2 D1 MBRD835L L1, L2: COILTRONICS DRQ127-3R3 (*COUPLED INDUCTORS) 3757 TA09a 84.5k CVCC 16k 4.7μF 10V X5R COUT 100μF 6.3V, X5R ×2 VC Photoelectric proximity switches HGA Photoelectric proximity switches ener. Photoelectric proximity switches V Photoelectric reflex switches T W 9-2: A Versatile, Complete and Compact Series D A T A S H E E T The W 9-2 series is as versatile as the tasks in automation. The standardized, compact housing model makes it possible to use high-performance sensors that operate reliably even in cramped mounting conditions. All W 9-2 models have red light transmitters as a standard feature. The sensor can be aligned on the object quickly and precisely using the visible light spot. In the models with Teach-In function, the sensor optimizes its sensitivity automatically to the given operating conditions at the push of a button. Depending on the job, the most suitable sensor can be selected from the W 9-2 series. Overview of the sensors: WT 9-2, with adjustable background suppression, max. scanning distance 250 mm, WT 9-2, energetic, max. scanning distance 450 mm, WT 9-2, V model, max. scanning distance 20 mm, WL 9-2, basic model, max. scanning range 4 m, WL 9-2, Teach-In model, max. scanning range 4 m, WL 9-2, focus, max. scanning range 0.4 m. There are multifaceted applications in the targeted main branches thanks to this great variety of products:  Storage and handling engineering  Packaging industry  Electronics industry  Elevator construction. 2 SENSICK WT 9-2 Photoelectric Proximity Switch with Background Suppression Setting options Dimension illustration LED light source, visible red light Background suppression Scanning distance adjustable Switching frequency 1500/s Outputs short-circuit protected Scanning distance 30 ... 250 mm 12 22 40 20 3 3 1.5 1 3 2 3 18.5 10.5 11 4 5 7 Axis of the sender optics Axis of the receiver optics Mounting hole Ø 3.2 mm LED signal strength indicator Plug M 12 or M 8, 4 pin, 2 m connection cable or 120 mm cable with plug M 12, 4 pin Scanning distance adjuster Standard direction of the material to be scanned 1 2 3 4 5 Photoelectric proximity switch 6 7 WT 9-2P130 WT 9-2P430 WT 9-2N130 WT 9-2N430 4 6 Cable receptacles Adapter plate Mounting bracket Accessories Connection type L+ Q Q M brn wht blu blk 4 pin, M 12 WT 9-2P330 WT 9-2P630 WT 9-2P430 WT 9-2N430 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 8 1 L+ Q Q 4 2 3 M brn wht blu blk 4 x 0,14 mm2 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 12 with 120 mm cable WT 9-2P330 WT 9-2P130 WT 9-2N130 WT 9-2P630 Scanning distance adjustable 1) 30 ... 250 mm Scanning range 5 ... 250 mm Supply voltage VS 2) DC 10 ... 30 V Ripple 3) ≤ 5 VPP Current consumption 4) ≤ 40 mA Light source LED, visible red light 5) Light spot diameter 15 x 15 mm at a distance of 200 mm Switching outputs Q and Q– PNP NPN Signal voltage HIGH VS – 2.9 V VS Signal voltage LOW 6) Approx. 0 V ≤ 1.5 V Output current IA max. ≤ 100 mA Response time 7) ≤ 333 μs Switching frequency max. 8) 1500/s Connection technology Connection cable, 2 m Cable, 120 mm, with plug M 12, 4 pin Plug M 12, 4 pin Plug M 8, 4 pin VDE protection class M 12 9) VDE protection class M 8 9) III Protection type IP 67 Protection circuits 10) A, B, C Ambient temperature 11) Operation –40 ... +60 °C Storage –40 ... +75 °C Weight with connection cable 2 m/120 mm Approx. 80 g with equipment plug M 12/M 8, 4 pin Approx. 20 g SENSICK 3 WT 9-2 Scanning distance Ordering information Technical data WT 9-2 P130 P430 N130 N430 P330 P630 1) Object with 90% reflectance (referred to standard white DIN 5033) 2) Limit values 3) Must be within VS tolerances 4) Without load 5) Average service life at room temperature 100,000 h 6) At TU = +25 °C and 100 mA output current 7) With resistive load 8) With light/dark ratio 1:1 9) Withstand voltage 50 V 10) A = supply connections reverse polarity protected B = outputs short-circuit protected C = interference suppression 11) Do not distort cable below 0 °C Type WT 9-2P130 WT 9-2P430 WT 9-2N130 WT 9-2N430 WT 9-2P330 WT 9-2P630 Order no. 1 018 293 1 018 295 1 018 294 1 018 296 1 019 026 1 019 272 (mm) 50 100 150 200 250 30 15 20 25 10 0 5 % of scanning distance 1 3 2 WT 9-2 HGA 90%/90% 18%/90% 6%/90% Scanning range on gray, white background, Black = 6% reflectance 1 Scanning range on black ), white background, 2 White = 90% reflectance Scanning range on white, white background, Gray = 18% reflectance 3 0(mm) 50 100 150 200 250 3 1 2 Operating distance 30 150 30 220 30 250 4 SENSICK WT 9-2 Photoelectric Proximity Switch, Energetic, Teach-In Setting options Dimension illustration Red-light emitter LED as alignment aid Scanning distance adjustable Switching frequency 800/s Outputs short-circuit protected Teach-In Scanning distance 18 ... 450 mm 12 22 40 20 3 3 1.5 1 3 2 3 25.55 6.5 11 4 5 Axis of the receiver optics Axis of the sender optics Mounting hole Ø 3.2 mm LED signal strength indicator Plug M 12 or M 8, 4 pin, 2 m connection cable or 120 mm cable with plug M 12, 4 pin Scanning distance adjuster, teachable 1 2 3 4 5 Photoelectric proximity switch 6 WT 9-2P151 WT 9-2P451 WT 9-2N151 WT 9-2N451 4 6 Cable receptacles Adapter plate Mounting bracket Accessories Connection type L+ Q Q M brn wht blu blk 4 pin, M 12 WT 9-2P351 WT 9-2P651 WT 9-2P451 WT 9-2N451 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 8 1 L+ Q Q 4 2 3 M brn wht blu blk 4 x 0,14 mm2 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 12 with 120 mm cable WT 9-2P351 WT 9-2P151 WT 9-2N151 WT 9-2P651 SENSICK 5 Scanning distance adjustable 1) 10 ... 450 mm Supply voltage VS 2) DC 10 ... 30 V Ripple 3) ≤ 5 VPP Current consumption 4) ≤ 30 mA Light source LED, visible red light 5) Light spot diameter 80 x 80 mm at a distance of 500 mm Switching outputs Q and Q– PNP NPN Signal voltage HIGH VS – 2.9 V VS Signal voltage LOW6) Approx. 0 V ≤ 2.9 V Output current IA max. ≤ 100 mA Response time 7) ≤ 625 μs Switching frequency max. 8) 800/s Connection technology Connection cable, 2 m Cable, 120 mm, with plug M 12, 4 pin Plug M 12, 4 pin Plug M 8, 4 pin VDE protection class M 12 9) VDE protection class M 8 9) III Protection type IP 67 Protection circuits 10) A, B, C Ambient temperature 11) Operation –40 ... +60 °C Storage –40 ... +75 °C Weight with connection cable 2 m/120 mm Approx. 80 g with equipment plug M 12/M 8, 4 pin Approx. 20 g WT 9-2 Scanning distance Ordering information Technical data WT 9-2 P151 P451 N151 N451 P351 P651 1) Object with 90% reflectance (referred to standard white DIN 5033) 2) Limit values 3) Must be within VS tolerances 4) Without load 5) Average service life at room temperature 50,000 h 6) At TU = +25 °C and 100 mA output current 7) With resistive load 8) With light/dark ratio 1:1 9) Withstand voltage 50 V 10) A = supply connections reverse polarity protected B = outputs short-circuit protected C = interference suppression 11) Do not distort cable below 0 °C Type WT 9-2P151 WT 9-2P451 WT 9-2N151 WT 9-2N451 WT 9-2P351 WT 9-2P651 Order no. 1 018 297 1 018 299 1 018 298 1 018 300 1 019 027 1 019 273 (mm) 100 200 1000 10 100 1 300 400 500 Function reserve Operating distance Limiting scanning distance WT 9-2 energetic 3 90% 2 18% 1 6% Programming via Teach-In button. Simple programming: Position object in the beam and push the button: finished; LED confirms the Teach-In procedure. Teach-In values can be stored. Teach-In function Two operating modes: Default setting: short Teach-In time (< 8 s); for standard applications; approx. double reserve via switching threshold; LED lights continuously. Precise setting: long Teach-In time (> 8 s); for precise applications; small switching hysteresis; LED blinks. Scanning range on white, 90 % reflectance Scanning range on gray, 18% reflectance 1 Scanning range on black, 6% reflectance 2 3 0(mm) 100 200 300 400 500 1 2 3 Operating distance Limiting scanning distance 10 180 220 10/100 130 10 350 450 6 SENSICK WT 9-2 Photoelectric Proximity Switch, V-type, Teach-In Setting options Dimension illustration Red-light emitter LED as alignment aid Scanning distance adjustable Switching frequency 800/s Outputs short-circuit protected Teach-In Scanning distance 10 ... 20 mm 12 22 40 20 3 3 1.5 1 3 2 3 26.45 4.7 11 4 5 Axis of the receiver optics Axis of the receiver optics Mounting hole Ø 3.2 mm LED signal strength indicator Plug M 12 or M 8, 4 pin, 2 m connection cable or 120 mm cable with plug M 12, 4 pin Scanning distance adjuster, teachable 1 2 3 4 5 Photoelectric proximity switch 6 WT 9-2P141 WT 9-2P441 WT 9-2N141 WT 9-2N441 4 6 Cable receptacles Adapter plate Mounting bracket Accessories Connection type L+ Q Q M brn wht blu blk 4 pin, M 12 WT 9-2P341 WT 9-2P641 WT 9-2P441 WT 9-2N441 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 8 1 L+ Q Q 4 2 3 M brn wht blu blk 4 x 0,14 mm2 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 12 with 120 mm cable WT 9-2P341 WT 9-2P141 WT 9-2N141 WT 9-2P641 SENSICK 7 Scanning distance adjustable 1) 10 ... 20 mm Supply voltage VS 2) DC 10 ... 30 V Ripple 3) ≤ 5 VPP Current consumption 4) ≤ 30 mA Light source LED, visible red light 5) Light spot diameter 3 mm at a distance of 20 mm Switching outputs Q and Q– PNP NPN Signal voltage HIGH VS – 2.9 V VS Signal voltage LOW6) Approx. 0 V ≤ 2.9 V Output current IA max. ≤ 100 mA Response time 7) ≤ 625 μs Switching frequency max. 8) 800/s Connection technology Connection cable, 2 m Cable, 120 mm, with plug M 12, 4 pin Plug M 12, 4 pin Plug M 8, 4 pin VDE protection class M 12 9) VDE protection class M 8 9) III Protection type IP 67 Protection circuits 10) A, B, C Ambient temperature 11) Operation –40 ... +60 °C Storage –40 ... +75 °C Weight with connection cable 2 m/120 mm Approx. 80 g with equipment plug M 12/M 8, 4 pin Approx. 20 g WT 9-2 Scanning distance Ordering information Technical data WT 9-2 P141 P441 N141 N441 P341 P641 1) Object with 90% reflectance (referred to standard white DIN 5033) 2) Limit values 3) Must be within VS tolerances 4) Without load 5) Average service life at room temperature 100,000 h 6) At TU = +25 °C and 100 mA output current 7) With resistive load 8) With light/dark ratio 1:1 9) Withstand voltage 50 V 10) A = supply connections reverse polarity protected B = outputs short-circuit protected C = interference suppression 11) Do not distort cable below 0 °C Type WT 9-2P141 WT 9-2P441 WT 9-2N141 WT 9-2N441 WT 9-2P341 WT 9-2P641 Order no. 1 018 301 1 018 303 1 018 302 1 018 304 1 019 274 1 019 275 Programming via Teach-In button. Simple programming: Position object in the beam and push the button: finished; LED confirms the Teach-In procedure. Teach-In values can be stored. Teach-In function Two operating modes: Default setting: short Teach-In time (< 8 s); for standard applications; approx. double reserve via switching threshold; LED lights continuously. Precise setting: long Teach-In time (> 8 s); for precise applications; small switching hysteresis; LED blinks. (mm) 4 1 10 100 8 12 16 20 24 28 Function reserve 1 3 2 6% 18% 90% Operating distance WT 9-2 0(mm) 10 20 30 1 2 3 Scanning distance 10 22 10 20 10 24 Scanning range on white, 90 % reflectance Scanning range on gray, 18% reflectance 1 Scanning range on black, 6% reflectance 2 3 8 SENSICK WL 9-2 Photoelectric Reflex Switch, Standard Without setting options Dimension illustration Red-light emitter LED as alignment aid Switching frequency 800/s Outputs short-circuit protected Scanning range 0 ... 4 m 12 22 40 20 3 3 1.5 1 2 2 29.5 11 3 4 Middle of optic axis Mounting hole Ø 3.2 mm LED signal strength indicator Plug M 12 or M 8, 4 pin, 2 m connection cable or 120 mm cable with plug M 12, 4 pin 1 2 3 4 Photoelectric reflex switch WL 9-2P130 WL 9-2P430 WL 9-2N130 WL 9-2N430 3 Cable receptacles Adapter plate Mounting bracket Reflectors Accessories Connection type L+ Q Q M brn wht blu blk 4 pin, M 12 WT 9-2P330 WT 9-2P630 WT 9-2P430 WT 9-2N430 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 8 1 L+ Q Q 4 2 3 M brn wht blu blk 4 x 0,14 mm2 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 12 with 120 mm cable WT 9-2P330 WT 9-2P130 WT 9-2N130 WT 9-2P630 SENSICK 9 Scanning range typ. max./on reflector 4 m/PL 80 A Supply voltage VS 1) DC 10 ... 30 V Ripple 2) ≤ 5 VPP Current consumption 3) ≤ 30 mA Light source LED, visible red light 4) Angle of dispersion 2.5° Light spot diameter 120 x 120 mm at a distance of 3 m Switching outputs Q and Q– PNP NPN Signal voltage HIGH VS – 2.9 V VS Signal voltage LOW5) Approx. 0 V ≤ 2.9 V Output current IA max. ≤ 100 mA Response time 6) ≤ 625 μs Max. switching frequency 7) 800/s Connection technology Connection cable, 2 m Cable, 120 mm, with plug M 12, 4 pin Plug M 12, 4 pin Plug M 8, 4 pin VDE protection class M 12 8) VDE protection class M 8 8) III Protection type IP 67 Protection circuits 9) A, B, C Ambient temperature 10) Operation –40 ... +60 °C Storage –40 ... +75 °C Weight with connection cable 2 m/120 mm Approx. 80 g with equipment plug M 12/M 8, 4 pin Approx. 20 g WL 9-2 Scanning range Ordering information Technical data WL 9-2 P130 P430 N130 N430 P330 P630 1) Limit values 2) Must be within VS tolerances 3) Without load 4) Average service life at room temperature 100,000 h 5) At TU = +25 °C and 100 mA output current 6) With resistive load 7) With light/dark ratio 1:1 8) Withstand voltage 50 V 19) A = supply connections reverse polarity protected B = outputs short-circuit protected C = interference suppression 10) Do not distort cable below 0 °C Type WL 9-2P130 WL 9-2P430 WL 9-2N130 WL 9-2N430 WL 9-2P330 WL 9-2P630 Order no. 1 018 281 1 018 283 1 018 282 1 018 284 1 019 024 1 019 268 (m) 1 2 3 4 5 100 10 1 Function reserve 1 3 2 Operating range WL 9-2 Limiting scanning range 0(m) 1 2 3 4 5 1 2 3 Operating range Scanning range typ. max. 0 3.0 4.0 0 2.0 3.0 0 0.6/1.0 Reflective tape 0 ... 0.6 m Diamond Grade* 3 2 PL 40 A 0 ... 2 m 1 PL 80 A 0 ... 3 m Reflector type Operating range * 100 x 100 mm2 10 SENSICK WL 9-2 Photoelectric Reflex Switch, Standard, Teach-In Setting options Dimension illustration Red-light emitter LED as alignment aid Switching frequency 800/s Outputs short-circuit protected Teach-In Scanning range 0 ... 4 m 12 22 40 20 3 3 1.5 1 2 2 29.5 11 3 4 Middle of optic axis Mounting hole Ø 3.2 mm LED signal strength indicator Plug M 12 or M 8, 4 pin, 2 m connection cable or 120 mm cable with plug M 12, 4 pin Sensitivity control, teachable 1 2 3 4 5 Photoelectric reflex switch WL 9-2P131 WL 9-2P431 WL 9-2N131 WL 9-2N431 3 5 Cable receptacles Adapter plate Mounting bracket Reflectors Accessories Connection type L+ Q Q M brn wht blu blk 4 pin, M 12 WT 9-2P331 WT 9-2P631 WT 9-2P431 WT 9-2N431 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 8 1 L+ Q Q 4 2 3 M brn wht blu blk 4 x 0,14 mm2 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 12 with 120 mm cable WT 9-2P331 WT 9-2P131 WT 9-2N131 WT 9-2P631 SENSICK 11 Scanning range typ. max./on reflector 4 m/PL 80 A Supply voltage VS 1) DC 10 ... 30 V Ripple 2) ≤ 5 VPP Current consumption 3) ≤ 30 mA Light source LED, visible red light 4) Angle of dispersion 2.5° Light spot diameter 120 x 120 mm at a distance of 3 m Switching outputs Q and Q– PNP NPN Signal voltage HIGH VS – 2.9 V VS Signal voltage LOW5) Approx. 0 V ≤ 2.9 V Output current IA max. ≤ 100 mA Response time 6) ≤ 625 μs Max. switching frequency 7) 800/s Connection technology Connection cable, 2 m Cable, 120 mm, with plug M 12, 4 pin Plug M 12, 4 pin Plug M 8, 4 pin VDE protection class M 12 8) VDE protection class M 8 8) III Protection type IP 67 Protection circuits 9) A, B, C Ambient temperature 10) Operation –40 ... +60 °C Storage –40 ... +75 °C Weight with connection cable 2 m/120 mm Approx. 80 g with equipment plug M 12/M 8, 4 pin Approx. 20 g WL 9-2 Scanning range Ordering information Technical data WL 9-2 P131 P431 N131 N431 P331 P631 1) Limit values 2) Must be within VS tolerances 3) Without load 4) Average service life at room temperature 100,000 h 5) At TU = +25 °C and 100 mA output current 6) With resistive load 7) With light/dark ratio 1:1 8) Withstand voltage 50 V 19) A = supply connections reverse polarity protected B = outputs short-circuit protected C = interference suppreasion 10) Do not distort cable below 0 °C Type WL 9-2P131 WL 9-2P431 WL 9-2N131 WL 9-2N431 WL 9-2P331 WL 9-2P631 Order no. 1 018 285 1 018 287 1 018 286 1 018 288 1 019 025 1 019 269 Programming via Teach-In button. Simple programming: Position reflector in the beam and push the button: finished; LED confirms the Teach-In procedure. Teach-In values can be stored. Teach-In function Two operating modes: Default setting: short Teach-In time (< 8 s); for standard applications; approx. double reserve via switching threshold; LED lights continuously. Precise setting: long Teach-In time (> 8 s); for precise applications; small switching hysteresis; LED blinks. (m) 1 2 3 4 5 100 10 1 Function reserve 1 3 2 Operating range WL 9-2 Limiting scanning range 0(m) 1 2 3 4 5 1 2 3 Operating range Scanning range typ. max. 0 3.0 4.0 0 2.0 3.0 0 0.6/1.0 Reflective tape 0 ... 0.6 m Diamond Grade* 3 2 PL 40 A 0 ... 2 m 1 PL 80 A 0 ... 3 m Reflector type Operating range * 100 x 100 mm2 12 SENSICK WL 9-2 Photoelectric Reflex Switch, Focus 35 mm, Teach-In Setting options Dimension illustration LED light source, visible red light Sensitivity adjustment using the Teach-In method Switching frequency 800/s Outputs short-circuit protected Scanning range 0 ... 0.4 m 12 22 40 20 3 3 1.5 1 2 2 29.5 11 3 4 Middle of optic axis Mounting hole Ø 3.2 mm LED signal strength indicator Plug M 12 or M 8, 4 pin, 2 m connection cable or 120 mm cable with plug M 12, 4 pin Sensitivity control, teachable 1 2 3 4 5 Photoelectric reflex switch WL 9-2P121 WL 9-2P421 WL 9-2N121 WL 9-2N421 3 5 Cable receptacles Adapter plate Mounting bracket Reflectors Accessories Connection type L+ Q Q M brn wht blu blk 4 pin, M 12 WT 9-2P321 WT 9-2P621 WT 9-2P421 WT 9-2N421 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 8 1 L+ Q Q 4 2 3 M brn wht blu blk 4 x 0,14 mm2 1 L+ Q Q 4 2 3 M brn wht blu blk 4 pin, M 12 with 120 mm cable WT 9-2P321 WT 9-2P121 WT 9-2N121 WT 9-2P621 SENSICK 13 Scanning range typ. max./on reflector 0.4 m/PL 80 A Supply voltage VS 1) DC 10 ... 30 V Ripple 2) ≤ 5 VPP Current consumption 3) ≤ 30 mA Light source LED, visible red light 4) Light spot diameter 1.5 x 1.5 mm at a distance of 35 mm Switching outputs Q and Q– PNP NPN Signal voltage HIGH VS – 2.9 V VS Signal voltage LOW5) Approx. 0 V ≤ 2.9 V Output current IA max. ≤ 100 mA Response time 6) ≤ 625 μs Max. switching frequency 7) 800/s Connection technology Connection cable, 2 m Cable, 120 mm, with plug M 12, 4 pin Plug M 12, 4 pin Plug M 8, 4 pin VDE protection class M 12 8) VDE protection class M 8 8) III Protection type IP 67 Protection circuits 9) A, B, C Ambient temperature 10) Operation –40 ... +60 °C Storage –40 ... +75 °C Weight with connection cable 2 m/120 mm Approx. 80 g with equipment plug M 12/M 8, 4 pin Approx. 20 g WL 9-2 Scanning range Ordering information Technical data WL 9-2 P121 P421 N121 N421 P321 P621 1) Limit values 2) Must be within VS tolerances 3) Without load 4) Average service life at room temperature 100,000 h 5) At TU = +25 °C and 100 mA output current 6) With resistive load 7) With light/dark ratio 1:1 8) Withstand voltage 50 V 19) A = supply connections reverse polarity protected B = outputs short-circuit protected C = interference suppression 10) Do not distort cable below 0 °C Type WL 9-2P121 WL 9-2P421 WL 9-2N121 WL 9-2N421 WL 9-2P321 WL 9-2P621 Order no. 1 018 289 1 018 291 1 018 290 1 018 292 1 019 270 1 019 271 Programming via Teach-In button. Simple programming: Position reflector in the beam and push the button: finished; LED confirms the Teach-In procedure. Teach-In values can be stored. Teach-In function Two operating modes: Default setting: short Teach-In time (< 8 s); for standard applications; approx. double reserve via switching threshold; LED lights continuously. Precise setting: long Teach-In time (> 8 s); for precise applications; small switching hysteresis; LED blinks. (m) 0.1 0.2 0.3 0.4 0.5 0.6 100 10 1 Function reserve Limiting scanning range Operating range WL 9-2 2 1 3 0(m) 0.1 0.2 0.3 0.4 0.5 1 2 3 Operating range Limiting scanning range 0 0.3 0.4 0 0.2 0.3 0 0,.1 0.2 Reflective tape 0 ... 0.25 m Diamond Grade* 3 2 PL 40 A 0 ... 0.3 m 1 PL 80 A 0 ... 0.5 m Reflector type Operating range * 100 x 100 mm2 14 Accessoires SENSICK Dimension illustrations of reflectors Reflector 20 x 40 mm Order no. 1 012 719 Type PL 20 A Reflector 30 x 50 mm Order no. 1 002 314 Type PL 30 A 15 18 38 ø8 ø4.6 50 60 4.2 7.3 3.4 ø4.5 ø8 71 82 29.8 7.2 Reflector 40 x 60 mm Order no. 1 012 720 Type PL 40 A Reflector hexagonal, SW 48 mm Order no. 1 000 132 Type PL 50 A 34 38 7.8 40.2 52 56.6 59.8 ø8.5 ø4.5 8 78 68 59 Reflector 80 x 80 mm Order no. 1 003 865 Type PL 80 A Reflector ø 83 mm, center hole mounting Order no. 5 304 549 Type C 110 84 68 71 84 4.5 8 8.5 2.5 ø4.8 83 9 Also available as heatable model: Continuous heating: PL 50HK, Order no. 1 001 545 Regulated heating: PL 50HS, Order no. 1 009 871 Reflective tape fabricated sheet 749 x 914 mm Order no. 4 019 634 5 304 334 Type REF-DG-K REF-DG Dimension illustrations and ordering information 15 Accessoires SENSICK Contact assignments according to EN 50044 DC coding Dimension illustrations of cable receptacles Cable receptacles M 12, 4 pin, straight Order no. 6 007 302 Cable lengths – 5 ø18 M12x1 54 5 ø10.5 ø8.8 1.5 12 M12x1 14.5 27 25.5 42 Rmin 571) Rmin 571) 38.3 12 45° M12x1 26.5 14.5 12 1.5 ø8.8 ø10.5 Pin assignments Pin 1 = brown Pin 2 = white Pin 3 = blue Pin 4 = black 3 2 4 1 Pins 4 Type DOS-1204-G Cable receptacles M 12, 4 pin, angled Order no. 6 007 303 Cable lengths – 36 25 5 14.8 M12x1 ø18 36 5 20.5 Pins 4 Type DOS-1204-W Cable receptacles M 12, 4 pin, straight Pins 4 4 4 Type DOS-1204-G02M DOS-1204-G05M DOS-1204-G10M Order no. 6 009 382 6 009 866 6 010 543 Cable lengths 2 m 5 m 10 m Cable receptacles M 12, 4 pin, angled Pins 4 4 4 Type DOS-1204-W02M DOS-1204-W05M DOS-1204-W10M Order no. 6 009 383 6 009 867 6 010 541 Cable lengths 2 m 5 m 10 m Can be self-made for cables Ø 4.5 to 6.5 mm 1) Minimum bending radius with dynamic use Can be self-made for cables Ø 4.5 to 6.5 mm 1) Minimum bending radius with dynamic use Dimension illustrations and ordering information 16 Accessoires SENSICK Dimension illustrations and ordering information ø 11.6 M 8x1 38.4 Cable diameter max. 5.0 mm 28.0 ø 11.6 M 8x1 12.5 Cable diameter max. 5.0 mm SENSICK circular screwing system, M 8 plug, 4 pin, enclosure rating IP 67 M 8 cable receptacle, 4 pin, straight Type DOS-0804-G Order no. 6 009 974 M 8 cable receptacles, 4 pin, angled Type DOS-0804-W Order no. 6 009 975 2/wht 1/brn 4/blk 3/blu ø 10 30.5 Rmin1) M 8x1 3/blu 6 26 M 8x1 16.5 ø 10 Rmin1) 1/brn 4/blk 2/wht M 8 cable receptacle, 4 pin, straight M 8 cable receptacles, 4 pin, angled Cable diameter 5 mm, 4 x 0.25 mm2, PVC coating Cable diameter 5 mm, 4 x 0.25 mm2, PVC coating Cable length 2 m 5 m 10 m Type DOL-0804-G02M DOL-0804-G05M DOL-0804-G10M Order no. 6 009 870 6 009 872 6 010 754 Cable length 2 m 5 m 10 m Type DOL-0804-W02M DOL-0804-W05M DOL-0804-W10M Order no. 6 009 871 6 009 873 6 010 755 1) Minimum bending radius with dynamic use Rmin= 20x cable diameter SENSICK 17 Dimension illustration adapter plate Adapter plate Order no. 4 033 145 Type BEF-AP-W9 22 63.25 1 8.25 5 3.25 20 3 M 3 ø 3.2 Dimension illustration mounting bracket Mounting bracket Order no. 4 033 146 Type BEF-WN-W9-2 44 1 4 4 3.5 5 6 14.8 12 6.4 8 14.8 16 17 17 Accessoires Dimension illustrations and ordering information 8 008 988.0700 HJS • SM • Printed in Germany • We reserve the right to make changes Contact: Au s t r a l i a Phone +61 3 94 97 41 00 0 08 33 48 02 – toll free Fax +61 3 94 97 11 87 Au s t r i a Phone +43 2 23 66 22 88-0 Fax +43 2 23 66 22 88-5 Bel g i u m / Luxembourg Phone +32 24 66 55 66 Fax +32 24 63 35 07 Br a z i l Phone +55 11 55 61 26 83 Fax +55 11 5 35 41 53 C h i n a / Ho n g Kong Phone +8 52 27 63 69 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SICK AG • Industrial Sensors • Sebastian-Kneipp-Straße 1 • D-79183 Waldkirch Phone +49/76 81/2 02-0 • Fax +49/76 81/2 02-36 09 • www.sick.de 1. Product profile 1.1 General description The BGA7124 MMIC is a one-stage amplifier, available in a low-cost leadless surface-mount package. It delivers 25 dBm output power at 1 dB gain compression and superior performance up to 2700 MHz. Its power saving features include easy quiescent current adjustment enabling class-AB operation and logic-level shutdown control to reduce the supply current to 4 μA. 1.2 Features and benefits 􀂄 400 MHz to 2700 MHz frequency operating range 􀂄 16 dB small signal gain at 2 GHz 􀂄 25 dBm output power at 1 dB gain compression 􀂄 Integrated active biasing 􀂄 External matching allows broad application optimization of the electrical performance 􀂄 3.3 V or 5 V single supply operation 􀂄 All pins ESD protected 1.3 Applications 1.4 Quick reference data [1] The supply current is adjustable; see Section 8.1 “Supply current adjustment”. [2] Operation outside this range is possible but not guaranteed. [3] PL = 11 dBm per tone; spacing = 1 MHz. BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier Rev. 3 — 9 September 2010 Product data sheet 􀂄 Wireless infrastructure (base station, repeater, backhaul systems) 􀂄 E-metering 􀂄 Broadband CPE/MoCA 􀂄 Satellite Master Antenna TV (SMATV) 􀂄 Industrial applications 􀂄 WLAN/ISM/RFID Table 1. Quick reference data Input and output impedances matched to 50 Ω, SHDN = HIGH (shutdown disabled). Typical values at VCC = 5 V; ICC = 130 mA; Tcase = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICC supply current VCC = 5.0 V [1] 50 - 170 mA f frequency [2] 400 - 2700 MHz Gp power gain f = 2140 MHz 14.5 16 17.5 dB PL(1dB) output power at 1 dB gain compression f = 2140 MHz 23.5 24.5 - dBm IP3O output third-order intercept point f = 2140 MHz [3] 34.5 37.5 - dBm BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 2 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 2. Pinning information 2.1 Pinning 2.2 Pin description [1] This pin is DC-coupled and requires an external DC-blocking capacitor. [2] RF decoupled. [3] The center metal base of the SOT908-1 also functions as heatsink for the power amplifier. 3. Ordering information Fig 1. HVSON8 package pin configuration 014aab046 VCC(BIAS) VCC(RF) SHDN VCC(RF) RF_IN ICQ_ADJ GND PAD n.c. Transparent top view 4 5 3 6 2 7 1 8 terminal 1 index area BGA7124 n.c. Table 2. Pin description Symbol Pin Description n.c. 1, 4 not connected VCC(RF) 2, 3 RF output for the power amplifier and DC supply input for the RF transistor collector [1] VCC(BIAS) 5 bias supply voltage [2] SHDN 6 shutdown control function enabled/disabled RF_IN 7 RF input for the power amplifier [1] ICQ_ADJ 8 quiescent collector current adjustment controlled by an external resistor GND GND pad RF and DC ground[3] Table 3. Ordering information Type number Package Name Description Version BGA7124 HVSON8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 × 3 × 0.85 mm SOT908-1 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 3 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 4. Functional diagram 5. Shutdown control Fig 2. Functional diagram BANDGAP INPUT MATCH OUTPUT MATCH BIAS ENABLE V/I CONVERTER RF_OUT GND R1 R2 RF_IN SHDN VCC ICQ_ADJ 6 7 5 8 2, 3 014aab047 VCC(BIAS) VCC(RF) Table 4. Shutdown control settings Mode Mode description Function description Pin SHDN Vctrl(sd) (V) Ictrl(sd) (μA) Min Max Min Max Idle medium power MMIC fully off; minimal supply current shutdown control enabled 0 0 0.7 - 2 TX medium power MMIC transmit mode shutdown control disabled 1 2.5 VCC(BIAS)- 9 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 4 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 6. Limiting values [1] See Figure 3 for safe operating area. [2] The supply current is adjustable; see Section 8.1 “Supply current adjustment”. [3] If Vctrl(sd) exceeds VCC(BIAS), the internal ESD circuit can be damaged. To prevent this, it is recommended that the Ictrl(sd) is limited to 20 mA. If the SHDN function is not used, the SHDN pin should be connected to the VCC(BIAS) pin. Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC(RF) RF supply voltage [1]- 6.0 V VCC(BIAS) bias supply voltage [1]- 6.0 V ICC supply current [1][2] 50 200 mA Vctrl(sd) shutdown control voltage [3] 0.0 VCC(BIAS) V Pi(RF) RF input power - 20 dBm Tcase case temperature −40 +85 °C Tj junction temperature - 150 °C VESD electrostatic discharge voltage Human Body Model (HBM); According JEDEC standard 22-A114E - 2000 V Charged Device Model (CDM); According JEDEC standard 22-C101B - 500 V Exceeding the safe operating area limits may cause serious damage to the product. The impact on ICC due to the spread of the external ICQ resistor (R2) should be taken into account. The product-spread on ICC should be taken into account (see Section 8 “Static characteristics”). Fig 3. BGA7124 DC safe operating area VCC(RF) (V) 2 3 4 5 6 7 014aab048 150 100 200 250 ICC (mA) 50 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 5 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 7. Thermal characteristics [1] defined as thermal resistance from junction to GND paddle. 8. Static characteristics [1] The supply current is adjustable; see Section 8.1 “Supply current adjustment”. [2] See Section 12 “Application information”. 8.1 Supply current adjustment The supply current can be adjusted by changing the value of external ICQ resistor (R2); (see Figure 4). Table 6. Thermal characteristics Symbol Parameter Conditions Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Tcase = 85 °C; VCC = 5 V; ICC = 130 mA [1] 32 - K/W Table 7. Characteristics Input and output impedances matched to 50 Ω, pin SHDN = HIGH (shutdown disabled). Typical values at VCC = 3.3 V or VCC = 5 V; Tcase = 25°C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICC supply current VCC = 3.3 V [1] 50 - 200 mA R1 = 0 Ω; R2 = 1330 Ω [2] 115 130 145 mA R1 = 2.2 Ω; R2 = 1070 Ω [2] 135 160 185 mA VCC = 5.0 V [1] 50 - 170 mA R1 = 0 Ω; R2 = 1960 Ω [2] 110 130 150 mA R1 = 2.2 Ω; R2 = 1650 Ω [2] 125 150 175 mA during shutdown; pin SHDN = LOW (shutdown enabled) - 4 6 μA BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 6 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 9. Dynamic characteristics a. 5 V supply voltage. b. 3.3 V supply voltage Fig 4. Supply current as a function of the value of R2 VCC = 5 V; R1 = 0 R2 (kΩ) 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 014aab049 90 130 170 ICC (mA) 50 VCC = 3.3 V; R1 = 0 R2 (kΩ) 0.9 1.4 1.9 2.4 2.9 3.4 014aab050 110 140 80 170 200 ICC (mA) 50 Table 8. Characteristics at VCC = 5 V Input and output impedances matched to 50 Ω, pin SHDN = HIGH (shutdown disabled). Typical values at VCC = 5 V; ICC = 130 mA; Tcase = 25°C; see Section 12 “Application information”; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit f frequency [1] 400 - 2700 MHz Gp power gain for small signals f = 940 MHz - 22.7 - dB f = 1960 MHz - 16.4 - dB f = 2140 MHz 14.5 16.0 17.5 dB f = 2445 MHz [2] - 14.2 - dB PL(1dB) output power at 1 dB gain compression f = 940 MHz - 25.0 - dBm f = 1960 MHz - 24.5 - dBm f = 2140 MHz 23.5 24.5 - dBm f = 2445 MHz [2] - 23.5 - dBm IP3O output third-order intercept point f = 940 MHz [3] - 38.5 - dBm f = 1960 MHz [3] - 38.0 - dBm f = 2140 MHz [3] 34.5 37.5 - dBm f = 2445 MHz [2][3] - 36.0 - dBm NF noise figure f = 940 MHz [4]- 5.2 - dB f = 1960 MHz [4]- 4.6 - dB f = 2140 MHz [4]- 4.8 6.5 dB f = 2445 MHz [2][4]- 5.4 - dB BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 7 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier [1] Operation outside this range is possible but not guaranteed. [2] ICC = 150 mA; see Section 12 “Application information”. [3] PL = 11 dBm per tone; spacing = 1 MHz. [4] Defined at Pi = −40 dBm; small signal conditions. RLin input return loss f = 940 MHz - −15 - dB f = 1960 MHz - −11 - dB f = 2140 MHz - −17 - dB f = 2445 MHz [2] - −13 - dB RLout output return loss f = 940 MHz - −8 - dB f = 1960 MHz - −12 - dB f = 2140 MHz - −15 - dB f = 2445 MHz [2] - −25 - dB Table 8. Characteristics at VCC = 5 V …continued Input and output impedances matched to 50 Ω, pin SHDN = HIGH (shutdown disabled). Typical values at VCC = 5 V; ICC = 130 mA; Tcase = 25°C; see Section 12 “Application information”; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 8 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier [1] Operation outside this range is possible but not guaranteed. [2] ICC = 160 mA; see Section 12 “Application information”. [3] PL= 11 dBm per tone; spacing = 1 MHz. [4] Defined at Pi = −40 dBm; small signal conditions. Table 9. Characteristics at VCC = 3.3 V Input and output impedances matched to 50 Ω, pin SHDN = HIGH (shutdown disabled). Typical values at VCC = 3.3 V; ICC = 130 mA; Tcase = 25°C, see Section 12 “Application information”; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit f frequency [1] 400 - 2700 MHz Gp power gain for small signals f = 940 MHz - 22.5 - dB f = 2445 MHz [2]- 13.8 - dB PL(1dB) output power at 1 dB gain compression f = 940 MHz - 23.5 - dBm f = 2445 MHz [2]- 22.0 - dBm IP3O output third-order intercept point f = 940 MHz [3]- 36.4 - dBm f = 2445 MHz [2][3]- 35.2 - dBm NF noise figure f = 940 MHz [4]- 5.5 - dB f = 2445 MHz [2][4]- 5.5 - dB RLin input return loss f = 940 MHz - −15 - dB f = 2445 MHz [2] - −10 - dB RLout output return loss f = 940 MHz - −9 - dB f = 2445 MHz [2] - −25 - dB BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 9 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 9.1 Scattering parameters Table 10. Scattering parameters at 5 V, MMIC only VCC = 5 V; ICC = 130mA; Tcase = 25°C. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) 400 0.85 161.56 22.94 82.35 0.01 17.02 0.46 −156.50 500 0.90 159.44 11.82 82.58 0.01 27.08 0.63 176.13 600 0.90 152.15 9.98 73.86 0.01 24.10 0.64 169.61 700 0.89 145.75 8.59 66.00 0.01 21.41 0.64 164.34 800 0.88 139.33 7.55 58.86 0.02 18.47 0.65 159.29 900 0.87 133.19 6.74 51.66 0.02 14.00 0.65 154.44 1000 0.87 127.07 6.14 45.11 0.02 11.25 0.65 149.58 1100 0.87 120.67 5.61 38.20 0.02 7.99 0.65 144.25 1200 0.87 114.18 5.19 31.60 0.02 4.20 0.64 139.60 1300 0.86 107.68 4.82 25.08 0.02 0.31 0.64 134.85 1400 0.86 100.86 4.51 18.49 0.02 −4.01 0.63 130.13 1500 0.86 94.14 4.23 11.74 0.02 −8.65 0.63 125.02 1600 0.86 87.48 3.99 5.25 0.03 −13.15 0.63 120.13 1700 0.86 80.83 3.77 −1.50 0.03 −18.16 0.62 114.98 1800 0.86 74.14 3.56 −8.13 0.03 −23.28 0.62 109.78 1900 0.86 67.39 3.37 −14.94 0.03 −28.54 0.62 104.46 2000 0.86 60.70 3.19 −21.68 0.03 −33.68 0.63 99.01 2100 0.86 53.97 3.02 −28.68 0.03 −39.37 0.63 93.58 2200 0.86 47.78 2.85 −35.14 0.03 −44.84 0.63 88.17 2300 0.86 41.57 2.69 −41.70 0.03 −50.27 0.64 83.06 2400 0.86 35.43 2.54 −48.11 0.03 −55.62 0.64 78.10 2500 0.86 29.74 2.39 −54.19 0.04 −60.71 0.65 73.31 2600 0.86 24.79 2.27 −60.06 0.04 −65.48 0.65 68.64 2700 0.85 19.58 2.15 −66.14 0.04 −70.66 0.66 64.16 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 10 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 10. Reliability information 11. Moisture sensitivity Table 11. Scattering parameters at 3.3 V, MMIC only VCC = 3.3 V; ICC = 130mA; Tcase = 25°C. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) 400 0.84 161.94 21.25 73.81 0.01 17.66 0.57 −154.41 500 0.91 159.25 11.56 79.01 0.01 28.15 0.65 178.05 600 0.90 151.98 9.67 70.71 0.01 24.80 0.66 171.32 700 0.90 145.57 8.29 63.37 0.01 21.89 0.66 165.59 800 0.89 139.18 7.26 56.54 0.02 19.04 0.66 160.37 900 0.88 132.87 6.48 49.74 0.02 15.35 0.66 155.28 1000 0.88 126.78 5.90 43.30 0.02 11.89 0.66 150.23 1100 0.87 120.46 5.39 36.53 0.02 8.33 0.66 144.88 1200 0.87 113.94 4.97 30.05 0.02 4.50 0.65 140.03 1300 0.87 107.48 4.62 23.62 0.02 0.35 0.65 135.35 1400 0.87 100.69 4.32 17.15 0.02 −3.92 0.64 130.48 1500 0.86 93.93 4.05 10.48 0.02 −8.62 0.64 125.46 1600 0.86 87.28 3.81 4.05 0.03 −13.28 0.64 120.31 1700 0.86 80.71 3.61 −2.66 0.03 −18.26 0.64 115.13 1800 0.86 74.00 3.40 −9.21 0.03 −23.51 0.64 109.99 1900 0.86 67.27 3.22 −15.97 0.03 −28.87 0.63 104.66 2000 0.86 60.64 3.05 −22.71 0.03 −34.22 0.64 99.36 2100 0.86 53.84 2.89 −29.68 0.03 −39.95 0.64 93.93 2200 0.86 47.60 2.72 −36.12 0.03 −45.44 0.64 88.55 2300 0.86 41.43 2.57 −42.66 0.03 −51.06 0.65 83.38 2400 0.86 35.35 2.42 −49.01 0.04 −56.53 0.65 78.44 2500 0.85 29.64 2.28 −55.12 0.04 −61.72 0.66 73.56 2600 0.85 24.72 2.16 −60.91 0.04 −66.76 0.66 68.80 2700 0.85 19.59 2.04 −66.91 0.04 −71.84 0.67 64.30 Table 12. Reliability Life test Conditions Intrinsic failure rate HTOL According JESD85; confidence level 60 %; Tj = 55 °C; activation energy = 0.7 eV; acceleration factor determined according Arrhenius 4 Table 13. Moisture sensitivity level Test methodology Class JESD-22-A113 1 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 11 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 12. Application information 12.1 5 V applications 12.1.1 920 MHz to 960 MHz See Table 14 for a list of components. PCB board specification: Rogers RO4003C; Height = 0.508 mm; εr = 3.38; Copper thickness = 35 μm. Fig 5. 5 V/130 mA application schematic; 920 MHz to 960 MHz C3 C10 C4 C6 C8 C9 C7 R1 R2 ICQ_ADJ SHDN enable L1 L2 C2 MSL1 C1 MSL2 MSL3 MSL5 MSL6 MSL7 MSL8 RF_IN J1 J3 J2 RF_OUT BGA7124 50 Ω 50 Ω VCC C5 014aab051 V MSL4 CC(RF) VCC(BIAS) (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 6. Output power at 1 dB gain compression as a function of frequency Fig 7. Power gain as a function of frequency f (GHz) 0.92 0.93 0.94 0.95 0.96 014aab052 24 26 22 28 30 PL(1dB) (dBm) 20 (1) (2) (3) f (GHz) 0.92 0.93 0.94 0.95 0.96 014aab053 22 24 20 26 28 Gp (dB) 18 (1) (2) (3) BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 12 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier Tcase = 25 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 8. Input return loss, output return loss and isolation as a function of frequency Fig 9. Output third-order intercept point as a function of frequency RLout RLin ISL f (GHz) 0.92 0.93 0.94 0.95 0.96 014aab054 −20 −10 0 RLin, RLout, ISL (dB) −30 f (GHz) 0.92 0.93 0.94 0.95 0.96 014aab055 38 40 42 IP3O (dBm) 36 (1) (3) (2) See Table 14 for a list of components. Fig 10. 5 V/130 mA application reference board; 920 MHz to 960 MHz J3 GND VCC GND n.c. enable GND C9 C10 C8 C6 C4 C5 L2 C1 C3 R2 C2 L1 C7 R1 MSL6 MSL7 MSL4 MSL5 MSL1 MSL3 MSL8 MSL2 J1 J I HG F E D C B A 1 2 3 4 5 6 7 8 910 11 12 13 RF in J2 RF out 014aab056 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 13 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier [1] MSL1 to MSL8 dimensions specified as Width (W), Spacing (S) and Length (L). Table 14. 5 V/130 mA application list of components; 920 MHz to 960 MHz See Figure 5 and Figure 10 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks C1, C6 capacitor 68 pF DC blocking Murata GRM1885C1H680JA01D C2, C3 capacitor 3.3 pF input match Murata GRM1885C1H3R3CZ01D C4 capacitor 3.9 pF output match Murata GRM1885C1H3R9CZ01D C5 capacitor 1.0 pF output match Murata GRM1885C1H1R0CZ01D C7 capacitor 68 pF RF decoupling Murata GRM1885C1H680JA01D C8 capacitor 100 nF DC decoupling AVX 0603YC104KAT2A C9 capacitor 10 μF DC decoupling AVX 1206ZG106ZAT2A C10 capacitor 12 pF noise decoupling Murata GRM1555C1H120JZ01D J1, J2 RF connector SMA Emerson Network Power 142-0701-841 J3 DC connector 6-pins MOLEX L1 inductor 2.2 nH output match Tyco electronics 36501J2N2JTDG L2 inductor 22 nH DC feed Tyco electronics 36501J022JTDG MSL1[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm input match MSL2[1] micro stripline 1.14 mm × 0.8 mm × 2.95 mm input match MSL3[1] micro stripline 1.14 mm × 0.8 mm × 7.75 mm input match MSL4[1] micro stripline 1.14 mm × 0.8 mm × 23.4 mm output match MSL5[1] micro stripline 1.14 mm × 0.8 mm × 2.2 mm output match MSL6[1] micro stripline 1.14 mm × 0.8 mm × 3.15 mm output match MSL7[1] micro stripline 1.14 mm × 0.8 mm × 2.3 mm output match MSL8[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm output match R1 resistor 0 Ω Multicomp MC 0.063W 0603 0R R2 resistor (trimmer) 2 kΩ bias adjustment Bourns 3214W-1-202E BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 14 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 12.1.2 1930 MHz to 1990 MHz See Table 15 for a list of components. PCB board specification: Rogers RO4003C; Height = 0.508 mm; εr = 3.38; Copper thickness = 35 μm. Fig 11. 5 V/130 mA application schematic; 1930 MHz to 1990 MHz C3 C4 C6 C7 C5 R1 R2 ICQ_ADJ SHDN enable L1 C2 MSL1 C1 MSL2 MSL4 MSL5 MSL6 RF_IN RF_OUT BGA7124 50 Ω 50 Ω VCC 014aab057 MSL3 VCC(BIAS) VCC(RF) J1 J3 J2 (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 12. Output power at 1 dB gain compression as a function of frequency Fig 13. Power gain as a function of frequency 014aab058 f (GHz) 1.93 1.95 1.97 1.99 24 26 22 28 30 PL(1dB) (dBm) 20 (1) (2) (3) 014aab059 f (GHz) 1.93 1.95 1.97 1.99 14 16 12 18 20 Gp (dB) 10 (1) (2) (3) BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 15 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier Tcase = 25 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 14. Input return loss, output return loss and isolation as a function of frequency Fig 15. Output third-order intercept point as a function of frequency RLout RLin ISL f (GHz) 1.93 1.95 1.97 1.99 014aab060 −20 −10 0 RLin, RLout, ISL (dB) −30 f (GHz) 1.93 1.95 1.97 1.99 014aab061 36 38 40 34 IP3O (dBm) (2) (1) (3) See Table 15 for a list of components. Fig 16. 5 V/130 mA application reference board; 1930 MHz to 1990 MHz J3 GND VCC GND n.c. enable GND C7 C6 C4 C2 C3 C1 R2 L1 C5 R1 MSL6 MSL4 MSL5 MSL1 MSL2 MSL3 J1 J I HG F E D C B A 1 2 3 4 5 6 7 8 910 11 12 13 RF in J2 RF out 014aab062 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 16 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier [1] MSL1 to MSL6 dimensions specified as Width (W), Spacing (S) and Length (L). 12.1.3 2110 MHz to 2170 MHz Table 15. 5 V/130 mA application list of components; 1930 MHz to 1990 MHz See Figure 11 and Figure 16 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks C1, C4 capacitor 15 pF DC blocking Murata GRM1885C1H150JA01D C2 capacitor 2.2 pF input match Murata GRM1885C1H2R2CZ01D C3 capacitor 1.2 pF output match Murata GRM1885C1H1R2CZ01D C5 capacitor 15 pF RF decoupling Murata GRM1885C1H150JA01D C6 capacitor 100 nF DC decoupling AVX 0603YC104KAT2A C7 capacitor 10 μF DC decoupling AVX 1206ZG106ZAT2A J1, J2 RF connector SMA Emerson Network Power 142-0701-841 J3 DC connector 6-pins MOLEX L1 inductor 22 nH DC feed Tyco electronics 36501J022JTDG MSL1[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm input match MSL2[1] micro stripline 1.14 mm × 0.8 mm × 10.8 mm input match MSL3[1] micro stripline 1.14 mm × 0.8 mm × 5.8 mm output match MSL4[1] micro stripline 1.14 mm × 0.8 mm × 2.2 mm output match MSL5[1] micro stripline 1.14 mm × 0.8 mm × 3.7 mm output match MSL6[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm output match R1 resistor 0 Ω Multicomp MC 0.063W 0603 0R R2 resistor (trimmer) 2 kΩ bias adjustment Bourns 3214W-1-202E See Table 16 for a list of components. PCB board specification: Rogers RO4003C; Height = 0.508 mm; εr = 3.38; Copper thickness = 35 μm. Fig 17. 5 V/130 mA application schematic; 2110 MHz to 2170 MHz RF_OUT C3 C4 C6 C7 C5 R1 R2 ICQ_ADJ SHDN enable L1 C2 MSL1 C1 MSL2 MSL4 MSL5 MSL6 RF_IN BGA7124 50 Ω 50 Ω VCC 014aab063 MSL3 VCC(BIAS) VCC(RF) J1 J3 J2 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 17 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 18. Output power at 1 dB gain compression as a function of frequency Fig 19. Power gain as a function of frequency 014aab064 f (GHz) 2.11 2.13 2.15 2.17 24 26 22 28 30 PL(1dB) (dBm) 20 (1) (2) (3) 014aab065 f (GHz) 2.11 2.13 2.15 2.17 14 16 12 18 20 Gp (dB) 10 (1) (2) (3) Tcase = 25 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 20. Input return loss, output return loss and isolation as a function of frequency Fig 21. Output third-order intercept point as a function of frequency RLout RLin ISL f (GHz) 2.11 2.13 2.15 2.17 014aab066 −20 −10 0 RLin, RLout, ISL (dB) −30 (3) (2) (1) f (GHz) 2.11 2.13 2.15 2.17 014aab067 36 38 40 IP3O (dBm) 34 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 18 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier See Table 16 for a list of components. Fig 22. 5 V/130 mA application reference board; 2110 MHz to 2170 MHz J3 GND VCC GND n.c. enable GND C7 C6 C4 C2 C3 C1 R2 L1 C5 R1 MSL6 MSL4 MSL5 MSL1 MSL2 MSL3 J1 J I HG F E D C B A 1 2 3 4 5 6 7 8 910 11 12 13 RF in J2 RF out 014aab068 Table 16. 5 V/130 mA application list of components; 2110 MHz to 2170 MHz See Figure 17 and Figure 22 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks C1, C4 capacitor 15 pF DC blocking Murata GRM1885C1H150JA01D C2 capacitor 2.7 pF input match Murata GRM1885C1H2R7CZ01D C3 capacitor 1.5 pF output match Murata GRM1885C1H1R5CZ01D C5 capacitor 15 pF RF decoupling Murata GRM1885C1H150JA01D C6 capacitor 100 nF DC decoupling AVX 0603YC104KAT2A C7 capacitor 10 μF DC decoupling AVX 1206ZG106ZAT2A J1, J2 RF connector SMA Emerson Network Power 142-0701-841 J3 DC connector 6-pins MOLEX L1 inductor 22 nH DC feed Tyco electronics 36501J022JTDG MSL1[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm input match MSL2[1] micro stripline 1.14 mm × 0.8 mm × 10.8 mm input match MSL3[1] micro stripline 1.14 mm × 0.8 mm × 5.8 mm output match MSL4[1] micro stripline 1.14 mm × 0.8 mm × 2.5 mm output match MSL5[1] micro stripline 1.14 mm × 0.8 mm × 3.5 mm output match BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 19 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier [1] MSL1 to MSL6 dimensions specified as Width (W), Spacing (S) and Length (L). 12.1.4 2405 MHz to 2485 MHz MSL6[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm output match R1 resistor 0 Ω Multicomp MC 0.063W 0603 0R R2 resistor (trimmer) 2 kΩ bias adjustment Bourns 3214W-1-202E Table 16. 5 V/130 mA application list of components; 2110 MHz to 2170 MHz …continued See Figure 17 and Figure 22 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks See Table 17 for a list of components. PCB board specification: Rogers RO4003C; Height = 0.508 mm; εr = 3.38; Copper thickness = 35 μm. Fig 23. 5 V/130 mA application schematic; 2405 MHz to 2485 MHz C3 C4 C5 C7 C8 C6 R1 R2 ICQ_ADJ SHDN enable L1 C2 MSL1 C1 MSL2 MSL3 MSL4 MSL5 RF_IN RF_OUT BGA7124 50 Ω 50 Ω VCC 014aab069 VCC(BIAS) VCC(RF) J1 J3 J2 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 20 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 24. Output power at 1 dB gain compression as a function of frequency Fig 25. Power gain as a function of frequency (3) (2) (1) f (GHz) 2.405 2.425 2.445 2.465 2.485 014aab070 20 22 18 24 26 PL(1dB) (dBm) 16 (3) (2) (1) f (GHz) 2.405 2.425 2.445 2.465 2.485 014aab071 14 16 12 18 20 Gp (dB) 10 Tcase = 25 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 26. Input return loss, output return loss and isolation as a function of frequency Fig 27. Output third-order intercept point as a function of frequency RLout RLin ISL f (GHz) 2.405 2.425 2.445 2.465 2.485 014aab072 −20 −10 0 RLin, RLout, ISL (dB) −30 f (GHz) 2.405 2.425 2.445 2.465 2.485 014aab073 34 36 38 32 IP3O (dBm) (1) (2) (3) BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 21 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier See Table 17 for a list of components. Fig 28. 5 V/130 mA application reference board; 2405 MHz to 2485 MHz J3 GND VCC GND n.c. enable GND C8 C7 C5 C2 C3 C4 C1 R2 L1 C6 R1 MSL1 MSL2 MSL3 MSL4 MSL5 J1 J I HG F E D C B A 1 2 3 4 5 6 7 8 910 11 12 13 RF in J2 RF out 014aab074 Table 17. 5 V/130 mA application list of components; 2405 MHz to 2485 MHz See Figure 23 and Figure 28 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks C1, C5 capacitor 12 pF DC blocking Murata GRM1885C1H120JA01D C2 capacitor 2.2 pF input match Murata GRM1885C1H2R2CZ01D C3 capacitor 0.82 pF output match Murata GRM1885C1HR82CZ01D C4 capacitor 0.68 pF output match Murata GRM1885C1HR68CZ01D C6 capacitor 12 pF RF decoupling Murata GRM1885C1H120JA01D C7 capacitor 100 nF DC decoupling AVX 0603YC104KAT2A C8 capacitor 10 μF DC decoupling AVX 1206ZG106ZAT2A J1, J2 RF connector SMA Emerson Network Power 142-0701-841 J3 DC connector 6-pins MOLEX L1 inductor 22 nH DC feed Tyco electronics 36501J022JTDG MSL1[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm input match MSL2[1] micro stripline 1.14 mm × 0.8 mm × 10.8 mm input match MSL3[1] micro stripline 1.14 mm × 0.8 mm × 7.3 mm output match MSL4[1] micro stripline 1.14 mm × 0.8 mm × 4.3 mm output match BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 22 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier [1] MSL1 to MSL5 dimensions specified as Width (W), Spacing (S) and Length (L). 12.2 3.3 V applications 12.2.1 920 MHz to 960 MHz MSL5[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm output match R1 resistor 2.2 Ω Multicomp MC 0.063W 0603 2R2 R2 resistor (trimmer) 2 kΩ bias adjustment Bourns 3214W-1-202E Table 17. 5 V/130 mA application list of components; 2405 MHz to 2485 MHz …continued See Figure 23 and Figure 28 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks See Table 18 for a list of components. PCB board specification: Rogers RO4003C; Height = 0.508 mm; εr = 3.38; Copper thickness = 35 μm. Fig 29. 3.3 V/130 mA application schematic; 920 MHz to 960 MHz C3 C4 C6 C8 C9 C7 R1 R2 ICQ_ADJ SHDN enable L1 L2 C2 MSL1 C1 MSL2 MSL3 RF_IN MSL4 MSL5 MSL6 MSL7 MSL8 RF_OUT BGA7124 50 Ω 50 Ω VCC C5 014aab075 VCC(BIAS) VCC(RF) J1 J3 J2 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 23 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 30. Output power at 1 dB gain compression as a function of frequency Fig 31. Power gain as a function of frequency f (GHz) 0.92 0.93 0.94 0.95 0.96 014aab076 24 26 22 28 30 PL(1dB) (dBm) 20 (1) (2) (3) f (GHz) 0.92 0.93 0.94 0.95 0.96 014aab077 22 24 20 26 28 Gp (dB) 18 (1) (2) (3) Tcase = 25 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 32. Input return loss, output return loss and isolation as a function of frequency Fig 33. Output third-order intercept point as a function of frequency RLout RLin ISL f (GHz) 0.92 0.93 0.94 0.95 0.96 014aab078 −20 −10 0 RLin, RLout, ISL (dB) −30 f (GHz) 0.92 0.93 0.94 0.95 0.96 014aab079 36 38 40 IP3O (dBm) 34 (1) (3) (2) BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 24 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier See Table 18 for a list of components. Fig 34. 3.3 V/130 mA application reference board; 920 MHz to 960 MHz J3 GND VCC GND n.c. enable GND C9 C8 C6 C2 C3 C4 C5 C1 R2 L2 L1 C7 R1 MSL1 MSL3 MSL8 MSL2 MSL4 MSL6 MSL7 MSL5 J1 J I HG F E D C B A 1 2 3 4 5 6 7 8 910 11 12 13 RF in J2 RF out 014aab080 Table 18. 3.3 V/130 mA application list of components; 920 MHz to 960 MHz See Figure 29 and Figure 34 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks C1, C6 capacitor 68 pF DC blocking Murata GRM1885C1H680JA01D C2, C3 capacitor 3.3 pF input match Murata GRM1885C1H3R3CZ01D C4 capacitor 3.9 pF output match Murata GRM1885C1H3R9CZ01D C5 capacitor 1.0 pF output match Murata GRM1885C1H1R0CZ01D C7 capacitor 68 pF RF decoupling Murata GRM1885C1H680JA01D C8 capacitor 100 nF DC decoupling AVX 0603YC104KAT2A C9 capacitor 10 μF DC decoupling AVX 1206ZG106ZAT2A J1, J2 RF connector SMA Emerson Network Power 142-0701-841 J3 DC connector 6-pins MOLEX L1 inductor 2.2 nH output match Tyco electronics 36501J2N2JTDG L2 inductor 22 nH DC feed Tyco electronics 36501J022JTDG MSL1[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm input match MSL2[1] micro stripline 1.14 mm × 0.8 mm × 2.95 mm input match MSL3[1] micro stripline 1.14 mm × 0.8 mm × 7.75 mm input match MSL4[1] micro stripline 1.14 mm × 0.8 mm × 23.4 mm output match MSL5[1] micro stripline 1.14 mm × 0.8 mm × 2.2 mm output match BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 25 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier [1] MSL1 to MSL8 dimensions specified as Width (W), Spacing (S) and Length (L). 12.2.2 2405 MHz to 2485 MHz MSL6[1] micro stripline 1.14 mm × 0.8 mm × 2.4 mm output match MSL7[1] micro stripline 1.14 mm × 0.8 mm × 2.3 mm output match MSL8[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm output match R1 resistor 0 Ω Multicomp MC 0.063W 0603 0R R2 resistor (trimmer) 2 kΩ bias adjustment Bourns 3214W-1-202E Table 18. 3.3 V/130 mA application list of components; 920 MHz to 960 MHz …continued See Figure 29 and Figure 34 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks See Table 19 for a list of components. PCB board specification: Rogers RO4003C; Height = 0.508 mm; εr = 3.38; Copper thickness = 35 μm Fig 35. 3.3 V/130 mA application schematic; 2405 MHz to 2485 MHz RF_OUT C3 C5 C7 C8 C6 R1 R2 ICQ_ADJ SHDN enable L1 C2 MSL1 C1 MSL2 MSL3 MSL4 MSL5 RF_IN BGA7124 50 Ω 50 Ω VCC C4 014aab081 VCC(BIAS) VCC(RF) J1 J3 J2 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 26 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 36. Output power at 1 dB gain compression as a function of frequency Fig 37. Power gain as a function of frequency f (GHz) 2.405 2.425 2.445 2.465 2.485 014aab082 20 22 18 24 26 PL(1dB) (dBm) 16 (3) (1) (2) f (GHz) 2.405 2.425 2.445 2.465 2.485 014aab083 14 16 12 18 20 Gp (dB) 10 (1) (2) (3) Tcase = 25 °C. (1) Tcase = −40 °C. (2) Tcase = 25 °C. (3) Tcase = 85 °C. Fig 38. Input return loss, output return loss and isolation as a function of frequency Fig 39. Output third-order intercept point as a function of frequency RLout RLin ISL f (GHz) 2.405 2.425 2.445 2.465 2.485 014aab084 −20 −10 0 RLin, RLout, ISL (dB) −30 (2) (1) (3) f (GHz) 2.405 2.425 2.445 2.465 2.485 014aab085 34 36 38 IP3O (dBm) 32 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 27 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier See Table 19 for a list of components. Fig 40. 3.3 V/130 mA application reference board; 2405 MHz to 2485 MHz J3 GND VCC GND n.c. enable GND C8 C7 C5 C2 C3 C4 C1 R2 L1 C6 R1 MSL1 MSL2 MSL3 MSL4 MSL5 J1 J I HG F E D C B A 1 2 3 4 5 6 7 8 910 11 12 13 RF in J2 RF out 014aab086 Table 19. 3.3 V/130 mA application list of components; 2405 MHz to 2485 MHz See Figure 35 and Figure 40 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks C1, C5 capacitor 12 pF DC blocking Murata GRM1885C1H120JA01D C2 capacitor 2.2 pF input match Murata GRM1885C1H2R2CZ01D C3 capacitor 0.82 pF output match Murata GRM1885C1HR82CZ01D C4 capacitor 0.68 pF output match Murata GRM1885C1HR68CZ01D C6 capacitor 12 pF RF decoupling Murata GRM1885C1H120JA01D C7 capacitor 100 nF DC decoupling AVX 0603YC104KAT2A C8 capacitor 10 μF DC decoupling AVX 1206ZG106ZAT2A J1, J2 RF connector SMA Emerson Network Power 142-0701-841 J3 DC connector 6-pins MOLEX L1 inductor 22 nH DC feed Tyco electronics 36501J022JTDG MSL1[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm input match MSL2[1] micro stripline 1.14 mm × 0.8 mm × 10.8 mm input match MSL3[1] micro stripline 1.14 mm × 0.8 mm × 7.3 mm output match MSL4[1] micro stripline 1.14 mm × 0.8 mm × 4.3 mm output match BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 28 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier [1] MSL1 to MSL5 dimensions specified as Width (W), Spacing (S) and Length (L). 12.3 PCB stack MSL5[1] micro stripline 1.14 mm × 0.8 mm × 10.95 mm output match R1 resistor 2.2 Ω Multicomp MC 0.063W 0603 2R2 R2 resistor (trimmer) 2 kΩ bias adjustment Bourns 3214W-1-202E Table 19. 3.3 V/130 mA application list of components; 2405 MHz to 2485 MHz …continued See Figure 35 and Figure 40 for component layout. Printed-Circuit Board (PCB): Rogers RO4003C stack; height = 0.508 mm; copper plating thickness = 35 μm. Component Description Value Function Remarks (1) Pre-pregnated RO4003Cdielectric constant εr = 3.38 Fig 41. PCB stack through via RF and analog ground RF and analog routing analog routing RF and analog ground 35 μm (1 oz.) copper + 0.3 μm gold plating RO4003C, 0.51 mm (20 mil) 35 μm (1 oz.) copper (1) 0.2 mm (8 mil) FR4, 0.15 mm (6 mil) 35 μm (1 oz.) copper 35 μm (1 oz.) copper 014aab087 BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 29 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 13. Package outline Fig 42. Package outline SOT908-1 (HVSON8) 1 0.2 0.5 0.05 0.00 UNIT A1 b D(1) Eh e y 1.5 e1 OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.1 2.9 c Dh 1.65 1.35 y1 3.1 2.9 2.25 1.95 0.3 0.2 0.05 0.1 DIMENSIONS (mm are the original dimensions) SOT908-1 MO-229 E(1) 0.5 0.3 L 0.1 v 0.05 w SOT908-1 HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm A(1) max. 05-09-26 05-10-05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. X terminal 1 index area D B A E detail X A A1 c C y1 C y exposed tie bar (4×) exposed tie bar (4×) b terminal 1 index area e1 e v M C A B w M C Eh Dh L 1 4 8 5 0 1 2 mm scale BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 30 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 14. Abbreviations 15. Revision history Table 20. Abbreviations Acronym Description CPE Customer-Premises Equipment DC Direct Current ESD ElectroStatic Discharge HTOL High Temperature Operating Life ISM Industrial, Scientific and Medical MMIC Monolithic Microwave Integrated Circuit MoCA Multimedia over Coax Alliance RFID Radio Frequency IDentification SMA SubMiniature version A TX Transmit WLAN Wireless Local Area Network Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes BGA7124 v.3 20100909 Product data sheet - BGA7124 v.2 Modifications: • Figure 5 on page 11: MSL symbols have been corrected. • Figure 11 on page 14: MSL symbols have been corrected. • Figure 17 on page 16: MSL symbols have been corrected. • Figure 23 on page 19: MSL symbols have been corrected. • Figure 29 on page 22: MSL symbols have been corrected. • Figure 35 on page 25: MSL symbols have been corrected. BGA7124 v.2 20100623 Product data sheet - BGA7124 v.1 BGA7124 v.1 20100421 Product data sheet - - BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 31 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier 16. Legal information 16.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. BGA7124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 9 September 2010 32 of 33 NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors BGA7124 400 MHz to 2700 MHz 0.25 W high linearity silicon amplifier © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 September 2010 Document identifier: BGA7124 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 Shutdown control . . . . . . . . . . . . . . . . . . . . . . . 3 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Thermal characteristics . . . . . . . . . . . . . . . . . . 5 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 8.1 Supply current adjustment . . . . . . . . . . . . . . . . 5 9 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 9.1 Scattering parameters . . . . . . . . . . . . . . . . . . . 9 10 Reliability information . . . . . . . . . . . . . . . . . . . 10 11 Moisture sensitivity . . . . . . . . . . . . . . . . . . . . . 10 12 Application information. . . . . . . . . . . . . . . . . . 11 12.1 5 V applications . . . . . . . . . . . . . . . . . . . . . . . 11 12.1.1 920 MHz to 960 MHz . . . . . . . . . . . . . . . . . . . 11 12.1.2 1930 MHz to 1990 MHz . . . . . . . . . . . . . . . . . 14 12.1.3 2110 MHz to 2170 MHz . . . . . . . . . . . . . . . . . 16 12.1.4 2405 MHz to 2485 MHz . . . . . . . . . . . . . . . . . 19 12.2 3.3 V applications . . . . . . . . . . . . . . . . . . . . . . 22 12.2.1 920 MHz to 960 MHz . . . . . . . . . . . . . . . . . . . 22 12.2.2 2405 MHz to 2485 MHz . . . . . . . . . . . . . . . . . 25 12.3 PCB stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 30 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 30 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17 Contact information. . . . . . . . . . . . . . . . . . . . . 32 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 12-Bit Serial Daisy-Chain CMOS D/A Converter DAC8143 FUNCTIONAL BLOCK DIAGRAM INPUT 12-BIT SHIFT REGISTER DAC REGISTER 12-BIT D/A CONVERTER DAC8143 LOAD IN OUT CLK VDD RFB IOUT1 IOUT2 AGND SRO DGND SRI STB2 STB3 STB4 STB1 LD2 LD1 VREF CLR ADDRESS BUS ADDRESS DECODER STROBE LOAD SRI SRO DAC8143 STROBE LOAD SRI SRO DAC8143 STROBE LOAD SRI SRO DAC8143 STROBE LOAD SRI SRO DAC8143 WR DBX mP Figure 1. Multiple DAC8143s with Three-Wire Interface FEATURES Fast, Flexible, Microprocessor Interfacing in Serially Controlled Systems Buffered Digital Output Pin for Daisy-Chaining Multiple DACs Minimizes Address-Decoding in Multiple DAC Systems—Three-Wire Interface for Any Number of DACs One Data Line One CLK Line One Load Line Improved Resistance to ESD –408C to +858C for the Extended Industrial Temperature Range APPLICATIONS Multiple-Channel Data Acquisition Systems Process Control and Industrial Automation Test Equipment Remote Microprocessor-Controlled Systems GENERAL INFORMATION The DAC8143 is a 12-bit serial-input daisy-chain CMOS D/A converter that features serial data input and buffered serial data output. It was designed for multiple serial DAC systems, where serially daisy-chaining one DAC after another is greatly simplified. The DAC8143 also minimizes address decoding lines enabling simpler logic interfacing. It allows three-wire interface for any number of DACs: one data line, one CLK line and one load line. Serial data in the input register (MSB first) is sequentially clocked out to the SRO pin as the new data word (MSB first) is simultaneously clocked in from the SRI pin. The strobe inputs are used to clock in/out data on the rising or falling (user selected) strobe edges (STB1, STB2, STB3, STB4). When the shift register’s data has been updated, the new data word is transferred to the DAC register with use of LD1 and LD2 inputs. Separate LOAD control inputs allow simultaneous output updating of multiple DACs. An asynchronous CLEAR input resets the DAC register without altering data in the input register. Improved linearity and gain error performance permits reduced circuit parts count through the elimination of trimming components. Fast interface timing reduces timing design considerations while minimizing microprocessor wait states. The DAC8143 is available in plastic packages that are compatible with autoinsertion equipment. Plastic packaged devices come in the extended industrial temperature range of –40°C to +85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACY Resolution N 12 Bits Nonlinearity INL ±1 LSB Differential Nonlinearity1 DNL ±1 LSB Gain Error2 GFSE ±2 LSB Gain Tempco (DGain/DTemp)3 TCGFS ±5 ppm/°C Power Supply Rejection Ratio (DGain/DVDD) PSRR DVDD = ±5% ±0.0006 ±0.002 %/% Output Leakage Current4 ILKG TA = +25°C ±5 nA TA = Full Temperature Range ±25 nA Zero Scale Error5, 6 IZSE TA = +25°C ±0.002 ±0.03 LSB TA = Full Temperature Range ±0.01 ±0.15 LSB Input Resistance7 RIN VREF Pin 7 11 15 kW AC PERFORMANCE Output Current Settling Time3, 8 tS 0.380 1 ms AC Feedthrough Error (VREF to IOUT1)3, 9 FT VREF = 20 V p-p @ f = 10 kHz, TA = +25°C 2.0 mV p-p Digital-to-Analog Glitch Energy3, 10 Q VREF = 0 V, IOUT Load = 100 W, CEXT = 13 pF 20 nVs Total Harmonic Distortion3 THD VREF = 6 V rms @ 1 kHz DAC Register Loaded with All 1s –92 dB Output Noise Voltage Density3, 11 en 10 Hz to 100 kHz Between RFB and IOUT 13 nV/ÖHz DIGITAL INPUTS/OUTPUT Digital Input HIGH VIH 2.4 V Digital Input LOW VIL 0.8 V Input Leakage Current12 IIN VIN = 0 V to +5 V ±1 mA Input Capacitance CIN VIN = 0 V 8 pF Digital Output High VOH IOH = –200 mA 4 V Digital Output Low VOL IOL = 1.6 mA 0.4 V ANALOG OUTPUTS Output Capacitance3 COUT1 Digital Inputs = All 1s 90 pF COUT2 Digital Inputs = All 0s 90 pF Output Capacitance3 COUT1 Digital Inputs = All 0s 60 pF COUT2 Digital Inputs = All 1s 60 pF TIMING CHARACTERISTICS3 Serial Input to Strobe Setup Times tDS1 STB1 Used as the Strobe 50 ns (tSTB = 80 ns) tDS2 STB2 Used as the Strobe 20 ns tDS3 STB3 Used as the Strobe TA = +25°C 10 ns TA = Full Temperature Range 20 ns tDS4 STB4 Used as the Strobe 20 ns tDH1 STB1 Used as the Strobe TA = +25°C 40 ns TA = Full Temperature Range 50 ns tDH2 STB2 Used as the Strobe TA = +25°C 50 ns TA = Full Temperature Range 60 ns Serial Input to Strobe Hold Times (tSTB = 80 ns) tDH3 STB3 Used as the Strobe 80 ns tDH4 STB4 Used as the Strobe 80 ns –2– REV. C (@ VDD = +5 V; VREF = +10 V; VOUT1 = VOUT2 = VAGND = VDGND = 0 V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.) DAC8143–SPECIFICATIONS ELECTRICAL CHARACTERISTICS DAC8143 Parameter Symbol Conditions Min Typ Max Units STB to SRO Propagation Delay13 tPD TA = +25°C 220 ns TA = Full Temperature Range 300 ns SRI Data Pulsewidth tSRI 100 ns STB1 Pulsewidth (STB1 = 80 ns)14 tSTB1 80 ns STB2 Pulsewidth (STB2 = 100 ns)14 tSTB2 80 ns STB3 Pulsewidth (STB3 = 80 ns)14 tSTB3 80 ns STB4 Pulsewidth (STB4 = 80 ns)14 tSTB4 80 ns Load Pulsewidth tLD1, tLD2 TA = +25°C 140 ns TA = Full Temperature Range 180 ns LSB Strobe into Input Register to Load DAC Register Time tASB 0 ns CLR Pulsewidth tCLR 80 ns POWER SUPPLY Supply Voltage VDD 4.75 5 5.25 V Supply Current IDD All Digital Inputs = VIH or VIL 2 mA All Digital Inputs = 0 V or VDD 0.1 mA Power Dissipation PD Digital Inputs = 0 V or VDD 0.5 mW 5 V ´ 0.1 mA Digital Inputs = VIH or VIL 10 mW 5 V ´ 2 mA NOTES 11All grades are monotonic to 12 bits over temperature. 12Using internal feedback resistor. 13Guaranteed by design and not tested. 14Applies to IOUT1; all digital inputs = VIL, VREF = +10 V; specification also applies for IOUT2 when all digital inputs = VIH. 15VREF = +10 V, all digital inputs = 0 V. 16Calculated from worst case RREF: IZSE (in LSBs) = (RREF ´ ILKG ´ 4096) /VREF. 17Absolute temperature coefficient is less than +300 ppm/°C. 18IOUT, Load = 100 W. CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to 1/2 LSB: tS = propagation delay (tPD) +9 t, where t equals measured time constant of the final RC decay. 19All digital inputs = 0 V. 10VREF = 0 V, all digital inputs = 0 V to VDD or VDD to 0 V. 11Calculations from en = Ö4K TRB where: K = Boltzmann constant, J/KR = resistance W T = resistor temperature, K B = bandwidth, Hz 12Digital inputs are CMOS gates; IIN typically 1 nA at +25°C. 13Measured from active strobe edge (STB) to new data output at SRO; CL = 50 pF. 14Minimum low time pulsewidth for STB1, STB2, and STB4, and minimum high time pulsewidth for STB3. Specifications subject to change without notice. (@ VDD = +5 V; VREF = +10 V; VOUT1 = V0UT2 = VAGND = VDGND = 0 V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.) DAC8143 REV. C –3– DAC8143 –4– REV. C PIN CONNECTIONS 16-Lead Epoxy Plastic DIP 16-Lead SOIC TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IOUT1 RFB DAC8143 IOUT2 VREF AGND VDD STB1 CLR LD1 DGND SRO STB4 SRI STB3 STB2 LD2 ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V VRFB to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Digital Input Voltage Range . . . . . . . . . . . . . . . –0.3 V to VDD Output Voltage (Pin 1, Pin 2) . . . . . . . . . . . . . . –0.3 V to VDD Operating Temperature Range FP/FS Versions . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C Package Type uJA* uJC Units 16-Lead Plastic DIP 76 33 °C/W 16-Lead SOIC 92 27 °C/W *qJA is specified for worst case mounting conditions, i.e., qJA is specified for device in socket for P-DIP package; qJA is specified for device soldered to printed circuit board for SOIC package. CAUTION 1. Do not apply voltage higher than VDD or less than DGND potential on any terminal except VREF (Pin 15) and RFB (Pin 16). 2. The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper antistatic handling procedures. 4. Absolute Maximum Ratings apply to packaged devices. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. ORDERING GUIDE Gain Temperature Package Package Model Nonlinearity Error Range Descriptions Options DAC8143FP ±1 LSB ±2 LSB –40°C to +85°C 16-Lead Plastic DIP N-16 DAC8143FS ±1 LSB ±2 LSB –40°C to +85°C 16-Lead SOIC R-16W Die Size: 99 ´ 107 mil, 10,543 sq. mils. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8143 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE DAC8143 REV. C –5– 10 FREQUENCY – Hz THD – dB –90 0.032 THD – % 0.010 –85 –80 –75 –70 –95 0.018 0.0056 0.0032 0.0018 100 1k 10k 100k VIN = 5V rms OUTPUT OP AMP: OP-42 Figure 3. Multiplying Mode Total Harmonic Distortion vs. Frequency Typical Performance Characteristics– ALL BITS ON 100 FREQUENCY – Hz B10 0 ATTENUATION – dB (MSB) B11 B9 B8 B7 B6 B5 B4 B3 B2 B1 (LSB) B0 DATA BITS "ON" (ALL OTHER DATA BITS "OFF") 1k 10k 100k 1M 10M 12 24 36 48 60 72 84 96 108 Figure 2. Multiplying Mode Frequency Response vs. Digital Code 3 0 VIN – Volts IDD – mA 2 1 0 1 2 3 4 5 Figure 4. Supply Current vs. Logic Input Voltage 4 1 VDD – Volts THRESHOLD VOLTAGE – Volts 3 2 0 1 2.4 –0.8 3 5 7 9 11 13 15 17 Figure 7. Logic Threshold Voltage vs. Supply Voltage 0.5 0 DIGITAL INPUT CODE – Decimal LINEARITY ERROR – LSB 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 512 1024 1536 2048 2560 3072 3584 4095 Figure 5. Linearity Error vs. Digital Code 0.5 2 VREF – Volts DNL – LSB 4 6 8 10 0.25 0 –0.25 –0.5 Figure 8. DNL Error vs. Reference Voltage 0.5 2 VREF – Volts INL – LSB 4 6 8 10 0.25 0 –0.25 –0.5 Figure 6. Linearity Error vs. Reference Voltage 40 0 SRO – VOLTAGE OUT – Volts SINK 30 20 10 0 –10 –20 –30 –40 1 2 3 4 5 SOURCE OUTPUT CURRENT – mA TA = +258C LOGIC 1 LOGIC 0 Figure 9. Digital Output Voltage vs. Output Current DAC8143 –6– REV. C DEFINITION OF SPECIFICATIONS RESOLUTION The resolution of a DAC is the number of states (2n) into which the full-scale range (FSR) is divided (or resolved), where “n” is equal to the number of bits. SETTLING TIME Time required for the analog output of the DAC to settle to within 1/2 LSB of its final value for a given digital input stimulus; i.e., zero to full-scale. GAIN Ratio of the DAC’s external operational amplifier output voltage to the VREF input voltage when all digital inputs are HIGH. FEEDTHROUGH ERROR Error caused by capacitive coupling from VREF to output. Feedthrough error limits are specified with all switches off. OUTPUT CAPACITANCE Capacitance from IOUT1 to ground. OUTPUT LEAKAGE CURRENT Current appearing at IOUT1 when all digital inputs are LOW, or at IOUT2 terminal when all inputs are HIGH. GENERAL CIRCUIT INFORMATION The DAC8143 is a 12-bit serial-input, buffered serial-output, multiplying CMOS D/A converter. It has an R-2R resistor ladder network, a 12-bit input shift register, 12-bit DAC register, control logic circuitry, and a buffered digital output stage. The control logic forms an interface in which serial data is loaded, under microprocessor control, into the input shift register and then transferred, in parallel, to the DAC register. In addition, buffered serial output data is present at the SRO pin when input data is loaded into the input register. This buffered data follows the digital input data (SRI) by 12 clock cycles and is available for daisy-chaining additional DACs. An asynchronous CLEAR function allows resetting the DAC register to a zero code (0000 0000 0000) without altering data stored in the registers. A simplified circuit of the DAC8143 is shown in Figure 10. An inversed R-2R ladder network consisting of silicon-chrome, thin-film resistors, and twelve pairs of NMOS current-steering switches. These switches steer binarily weighted currents into either IOUT1 or IOUT2. Switching current to IOUT1 or IOUT2 yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resistance at VREF equal to R (typically 11 kW). The VREF input may be driven by any reference voltage or current, ac or dc, that is within the limits stated in the Absolute Maximum Ratings chart. The twelve output current-steering switches are in series with the R-2R resistor ladder, and therefore, can introduce bit errors. It was essential to design these switches such that the switch “ON” resistance be binarily scaled so that the voltage drop across each switch remains constant. If, for example, Switch 1 of Figure 10 was designed with an “ON” resistance of 10 W, Switch 2 for 20 W, etc., a constant 5 mV drop would then be maintained across each switch. To further ensure accuracy across the full temperature range, permanently “ON” MOS switches were included in series with the feedback resistor and the R-2R ladder’s terminating resistor. The Simplified DAC Circuit, Figure 10, shows the location of these switches. These series switches are equivalently scaled to two times Switch 1 (MSB) and top Switch 12 (LSB) to maintain constant relative voltage drops with varying temperature. During any testing of the resistor ladder or RFEEDBACK (such as incoming inspection), VDD must be present to turn “ON” these series switches. VREF RFEEDBACK IOUT2 IOUT1 10kV 10kV 10kV 20kV 20kV 20kV 20kV 20kV S1 S2 S3 S12 10kV BIT 1 (MSB) BIT 2 BIT 3 BIT 12 (LSB) DIGITAL INPUTS (SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH") * * *THESE SWITCHES PERMANENTLY "ON" Figure 10. Simplified DAC Circuit DAC8143 REV. C –7– ESD PROTECTION The DAC8143 digital inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 11 shows the input protection diodes. High voltage static charges applied to the digital inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs well below dangerous levels during static discharge conditions. VDD DTL/TTL/CMOS INPUTS Figure 11. Digital Input Protection EQUIVALENT CIRCUIT ANALYSIS Figures 12 and 13 show equivalent circuits for the DAC8143’s internal DAC with all bits LOW and HIGH, respectively. The reference current is switched to IOUT2 when all data bits are LOW, and to IOUT1 when all bits are HIGH. The ILEAKAGE current source is the combination of surface and junction leakages to the substrate. The 1/4096 current source represents the constant 1-bit current drain through the ladder’s terminating resistor. Output capacitance is dependent upon the digital input code. This is because the capacitance of a MOS transistor changes with applied gate voltage. This output capacitance varies between the low and high values. RFEEDBACK IOUT1 IOUT2 R = 10kV ILEAKAGE 60pF 1/4096 ILEAKAGE 90pF R = 10kV IREF VREF Figure 12. Equivalent Circuit (All Inputs LOW) IOUT2 ILEAKAGE 60pF RFEEDBACK IOUT1 R = 10kV 1/4096 ILEAKAGE 90pF R = 10kV IREF VREF Figure 13. Equivalent Circuit (All Inputs HIGH) DYNAMIC PERFORMANCE ANALOG OUTPUT IMPEDANCE The output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT1 terminal, varies between 11 kW (the feedback resistor alone when all digital input are LOW) and 7.5 kW (the feedback resistor in parallel with approximately 30 kW of the R-2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be affected by these variations. The gain and phase stability of the output amplifier, board layout, and power supply decoupling will all affect the dynamic performance of the DAC8143. The use of a small compensation capacitor may be required when high speed operational amplifiers are used. It may be connected across the amplifier’s feedback resistor to provide the necessary phase compensation to critically damp the output. The considerations when using high speed amplifiers are: 1. Phase compensation (see Figures 16 and 17). 2. Power supply decoupling at the device socket and use of proper grounding techniques. OUTPUT AMPLIFIER CONSIDERATIONS When using high speed op amps, a small feedback capacitor (typically 5 pF–30 pF) should be used across the amplifiers to minimize overshoot and ringing. For low speed or static applications, ac specifications of the amplifier are not very critical. In high speed applications, slew rate, settling time, openloop gain and gain/phase margin specifications of the amplifier should be selected for the desired performance. It has already been noted that an offset can be caused by including the usual bias current compensation resistor in the amplifier’s noninverting input terminal. This resistor should not be used. Instead, the amplifier should have a bias current that is low over the temperature range of interest. Static accuracy is affected by the variation in the DAC’s output resistance. This variation is best illustrated by using the circuit of Figure 14 and the equation: VERROR = VOS 1+RFB RO æ è ç ö ø ÷ VOS VREF R R R ETC RFB R2 R2 R2 OP-77 Figure 14. Simplified Circuit DAC8143 –8– REV. C Where RO is a function of the digital code, and: RO = 10 kW for more than four bits of Logic 1, RO = 30 kW for any single bit of Logic 1. Therefore, the offset gain varies as follows: at code 0011 1111 1111, VERROR1 = VOS 1+10 kW 10 kW æ è ç ö ø ÷ = 2 VOS at code 0100 0000 0000, VERROR2 = VOS 1+10 kW 30 kW æ è ç ö ø ÷ = 4/3 VOS The error difference is 2/3 VOS. Since one LSB has a weight (for VREF = +10 V) of 2.4 mV for the DAC8143, it is clearly important that VOS be minimized, using either the amplifier’s pulling pins, an external pulling network, or by selection of an amplifier with inherently low VOS. Amplifiers with sufficiently low VOS include OP77, OP97, OP07, OP27, and OP42. INTERFACE LOGIC OPERATION The microprocessor interface of the DAC8143 has been designed with multiple STROBE and LOAD inputs to maximize interfacing options. Control signals decoding may be done on chip or with the use of external decoding circuitry (see Figure 21). Serial data is clocked into the input register and buffered output stage with STB1, STB2, or STB4. The strobe inputs are active on the rising edge. STB3 may be used with a falling edge clock data. WORD N –1 WORD N WORD N –2 WORD N –1 WORD N BIT 2 BIT 11 BIT 12 LSB BIT 1 MSB BIT 12 LSB BIT 1 BIT 2 SRI MSB BIT 1 BIT 2 MSB BIT 1 MSB BIT 2 BIT 12 LSB BIT 1 LSB tDS1, tDS2, tDS3, tDS4 SRO tDH1, tDH2, tDH3, tDH4 tPD tSTB1 tSTB2 tSTB3 tSTB4 tSTB1 tSTB2 tSTB3 tSTB4 * STROBE (STB1, STB2, STB4) 1 2 12 1 2 tLD1 tLD2 tSR1 11 12 tASB LD1 AND LD2 LOAD NEW 12-BIT WORD INTO INPUT REGISTER AND SHIFT OUT PREVIOUS WORD LOAD INPUT REGISTER'S DATA INTO DAC REGISTER NOTES: * STROBE WAVEFORM IS INVERTED IF STB3 IS USED TO STROBE SERIAL DATA BITS INTO INPUT REGISTER. ** DATA IS STROBED INTO AND OUT OF THE INPUT SHIFT REGISTER MSB FIRST. Figure 15. Timing Diagram Serial data output (SRO) follows the serial data input (SRI) by 12 clocked bits. Holding any STROBE input at its selected state (i.e., STB1, STB2 or STB4 at logic HIGH or STB3 at logic LOW) will act to prevent any further data input. When a new data word has been entered into the input register, it is transferred to the DAC register by asserting both LOAD inputs. The CLR input allows asynchronous resetting of the DAC register to 0000 0000 0000. This reset does not affect data held in the input registers. While in unipolar mode, a CLEAR will result in the analog output going to 0 V. In bipolar mode, the output will go to –VREF. INTERFACE INPUT DESCRIPTION STB1 (Pin 4), STB2 (Pin 8), STB4 (Pin 11)—Input Register and Buffered Output Strobe. Inputs Active on Rising Edge. Selected to load serial data into input register and buffered output stage. See Table I for details. STB3 (Pin 10)—Input Register and Buffered Output Strobe Input. Active on Falling Edge. Selected to load serial data into input register and buffered output stage. See Table I for details. LD1 (Pin 5), LD2 (Pin 9)—Load DAC Register Inputs. Active Low. Selected together to load contents of input register into DAC register. CLR (Pin 13)—Clear Input. Active Low. Asynchronous. When LOW, 12-bit DAC register is forced to a zero code (0000 0000 0000) regardless of other interface inputs. DAC8143 REV. C –9– Table I. Truth Table DAC8143 Logic Inputs Input Register/ Digital Output Control Inputs DAC Register Control Inputs STB4 STB3 STB2 STB1 CLR LD2 LD1 DAC8143 Operation Notes 0 1 0 g X X X 0 1 g 0 X X X Serial Data Bit Loaded from SRI 0 f 0 0 X X X into Input Register and Digital Output 2, 3 g 1 0 0 X X X (SRO Pin) after 12 Clocked Bits. 1 X X X X 0 X X No Operation (Input Register and SRO) 3 X X 1 X X X X 1 Reset DAC Register to Zero Code 0 X X (Code: 0000 0000 0000) 1, 3 (Asynchronous Operation) 1 1 X No Operation (DAC Register and SRO) 3 1 X 1 1 0 0 Load DAC Register with the Contents 3 of Input Register NOTES 1CLR = 0 asynchronously resets DAC Register to 0000 0000 0000, but has no effect on Input Register. 2Serial data is loaded into Input Register MSB first, on edges shown. g is positive edge, f is negative edge. 30 = Logic LOW, 1 = Logic HIGH, X = Don’t Care. APPLICATIONS INFORMATION UNIPOLAR OPERATION (2-QUADRANT) The circuit shown in Figures 16 and 17 may be used with an ac or dc reference voltage. The circuit’s output will range between 0 V and +10(4095/4096) V depending upon the digital input code. The relationship between the digital input and the analog output is shown in Table II. The VREF voltage range is the maximum input voltage range of the op amp or ±25 V, whichever is lowest. Table II. Unipolar Code Table Digital Input Nominal Analog Output (VOUT as Shown MSB LSB in Figures 16 and 17) 1 1 1 1 1 1 1 1 1 1 1 1 –VREF 4095 4096 æ è ç ö ø ÷ 1 0 0 0 0 0 0 0 0 0 0 1 –VREF 2049 4096 æèöø 1 0 0 0 0 0 0 0 0 0 0 0 –VREF 2048 4096 æè öø = – VREF 2 0 1 1 1 1 1 1 1 1 1 1 1 –VREF 2047 4096 æè öø 0 0 0 0 0 0 0 0 0 0 0 1 –VREF 1 4096 æè öø 0 0 0 0 0 0 0 0 0 0 0 0 –VREF 0 4096 æè öø = 0 NOTES 1Nominal full scale for the circuits of Figures 16 and 17 is given by FS = –VREF 4095 4096 æ è ç ö ø ÷ . 2Nominal LSB magnitude for the circuits of Figures 16 and 17 is given by LSB = VREF 1 4096 æ è ç ö ø ÷ or VREF(2–n). OP-77 +5V VREF VDD RFEEDBACK IOUT1 IOUT2 AGND DGND SRO (BUFFERED DIGITAL DATA OUT) 15pF +15V –15V VOUT 7 6 4 3 2 15 14 13 4, 5 8–11 7 1 2 3 6 12 CONTROL DAC8143 INPUTS SRI (SERIAL DATA IN) VREF –10V CLR Figure 16. Unipolar Operation with High Accuracy Op Amp (2-Quadrant) OP-42 +5V VREF VDD RFEEDBACK IOUT1 IOUT2 AGND DGND SRO (BUFFERED DIGITAL DATA OUT) 15pF +15V –15V VOUT 7 6 4 3 2 15 14 13 4, 5 8–11 7 1 2 3 6 12 CONTROL DAC8143 INPUTS SRI (SERIAL DATA IN) VREF –10V R2 50V R1 100V CLR Figure 17. Unipolar Operation with Fast Op Amp and Gain Error Trimming (2-Quadrant) DAC8143 –10– REV. C In many applications, the DAC8143’s zero scale error and low gain error, permit the elimination of external trimming components without adverse effects on circuit performance. For applications requiring a tighter gain error than 0.024% at 25°C for the top grade part, or 0.048% for the lower grade part, the circuit in Figure 17 may be used. Gain error may be trimmed by adjusting R1. The DAC register must first be loaded with all 1s. R1 is then adjusted until VOUT = –VREF (4095/4096). In the case of an adjustable VREF, R1 and RFEEDBACK may be omitted, with VREF adjusted to yield the desired full-scale output. BIPOLAR OPERATION (4-QUADRANT) Figure 18 details a suggested circuit for bipolar, or offset binary, operation. Table III shows the digital input-to-analog output relationship. The circuit uses offset binary coding. Twos complement code can be converted to offset binary by software inversion of the MSB or by the addition of an external inverter to the MSB input. Resistor R3, R4 and R5 must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient match. Mismatching between R3 and R4 causes offset and full-scale error. Calibration is performed by loading the DAC register with 1000 0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be omitted by adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full scale can be adjusted by loading the DAC register with 1111 1111 1111 and adjusting either the amplitude of VREF or the value of R5 until the desired VOUT is achieved. Table III. Bipolar (Offset Binary) Code Table Digital Input Nominal Analog Output MSB LSB (VOUT as Shown in Figure 18) 1 1 1 1 1 1 1 1 1 1 1 1 +VREF 2047 2048 æè öø 1 0 0 0 0 0 0 0 0 0 0 1 +VREF 1 2048 æè öø 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 –VREF 1 2048 æè öø 0 0 0 0 0 0 0 0 0 0 0 1 –VREF 2047 2048 æè öø 0 0 0 0 0 0 0 0 0 0 0 0 –VREF 2048 2048 æè öø NOTES 1Nominal full scale for the circuits of Figure 18 is given by FS = VREF 2047 2048 æè öø . 2Nominal LSB magnitude for the circuits of Figure 18 is given by LSB = VREF 1 2048 æè öø . DAISY-CHAINING DAC8143s Many applications use multiple serial input DACs that use numerous interconnecting lines for address decoding and data lines. In addition, they use some type of buffering to reduce loading on the bus. The DAC8143 is ideal for just such an application. It not only reduces the number of interconnecting lines, but also reduces bus loading. The DAC8143 can be daisychained with only three lines: one data line, one CLK line and one load line, see Figure 19. VOUT 1/2 OP200 +5V R2 50V 12 15 7 R1 100V SERIAL DATA INPUT VIN 14 15 1 2 3 8-11 4, 5 13 6 DGND VREF SRI CONTROL BITS SRO CONTROL INPUTS FROM SYSTEM RESET BUFFERED SERIAL DATA OUT VDD RFB AGND IOUT2 IOUT1 DAC8143 C1 10-33pF COMMON GROUND R3 A1 10kV R4 20kV R5 20kV 1/2 OP200 A2 CLR Figure 18. Bipolar Operation (4-Quadrant, Offset Binary) DAC8143 REV. C –11– ANALOG/DIGITAL DIVISION The transfer function for the DAC8143 connect in the multiplying mode as shown in Figures 16 and 17 is: VO = –VIN A1 21 + A2 22 + A3 23 + ... A12 212 æ è ç ö ø ÷ where AX assumes a value of 1 for an “ON” bit and 0 for an “OFF” bit. The transfer function is modified when the DAC is connected in the feedback of an operational amplifier as shown in Figure 20 and is: VO = –VIN A1 21 + A2 22 + A3 23 + ... A12 212 æ è ççç ö ø ÷÷÷ The above transfer function is the division of an analog voltage (VREF) by a digital word. The amplifier goes to the rails with all bits “OFF” since division by zero is infinity. With all bits “ON” the gain is 1 (±1 LSB). The gain becomes 4096 with the LSB, Bit 12, “ON”. BUFFERED DIGITAL DATA OUT +5V SRO VREF RFB VDD IOUT1 DAC8143 AGND 3 2 12 DGND 15 6 16 14 1 3 2 6 VIN VOUT 4 13 DIGITAL INPUTS OP-42 + – Figure 20. Analog/Digital Divider APPLICATION TIPS In most applications, linearity depends on the potential of IOUT1, IOUT2, and AGND (Pins 1, 2 and 3) being exactly equal to each other. In most applications, the DAC is connected to an external op amp with its noninverting input tied to ground (see Figures 16 and 17). The amplifier selected should have a low input bias current and low drift over temperature. The amplifier’s input offset voltage should be nulled to less than ±200 mV (less than 10% of 1 LSB). The operational amplifier’s noninverting input should have a minimum resistance connection to ground; the usual bias current compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a varying output error. All grounded pins should tie to a single common ground point, avoiding ground loops. The VDD power supply should have a low noise level with no transients greater than +17 V. It is recommended that the digital inputs be taken to ground or VDD via a high value (1 MW) resistor; this will prevent the accumulation of static charge if the PC card is disconnected from the system. Peak supply current flows as the digital input pass through the transition region (see Figure 4). The supply current decreases as the input voltage approaches the supply rails (VDD or DGND), i.e., rapidly slewing logic signals that settle very near the supply rails will minimize supply current. INTERFACING TO THE MC6800 As shown in Figure 21, the DAC8143 may be interfaced to the 6800 by successively executing memory WRITE instruction while manipulating the data between WRITEs, so that each WRITE presents the next bit. In this example, the most significant bits are found in memory locations 0000 and 0001. The four MSBs are found in the lower half of 0000, the eight LSBs in 0001. The data is taken from the DB7 line. The serial data loading is triggered by STB4 which is asserted by a decoded memory WRITE to a memory location, R/W, and F2. A WRITE to another address location transfers data from input register to DAC register. STB1 DAC8143* SRI SRO LD2 LD1 STB3 STB2 STB4 CLR 74LS138 ADDRESS DECODER E1 A0 A2 E3 E2 A0 A15 R/W DB0 DB7 MC6800 16-BIT ADDRESS BUS 8-BIT DATA BUS +5V FROM SYSTEM RESET *ANALOG CIRCUITRY OMITTED FOR SIMPLICITY f2 Figure 21. DAC8143—MC6800 Interface ADDRESS DECODER STROBE LOAD DAC8143 SRI SRO ADDRESS BUS STROBE LOAD DAC8143 SRI SRO STROBE LOAD DAC8143 SRI SRO STROBE LOAD DAC8143 SRI SRO DBX mP WR Figure 19. Multiple DAC8143s with Three-Wire Interface DAC8143 –12– REV. C DAC8143 INTERFACE TO THE 8085 The DAC8143’s interface to the 8085 microprocessor is shown in Figure 22. Note that the microprocessor’s SOD line is used to present data serially to the DAC. Data is strobed into the DAC8143 by executing memory write instructions. The strobe 2 input is generated by decoding an address location and WR. Data is loaded into the DAC register with a memory write instruction to another address location. Serial data supplied to the DAC8143 must be present in the right-justified format in registers H and L of the microprocessor. STB1 DAC8143* SRI SRO LD2 LD1 STB3 STB2 STB4 CLR 74LS138 ADDRESS DECODER E1 A0 A2 E3 E2 WR ALE SOD 8085 ADDRESS BUS (16) DATA +5V FROM SYSTEM RESET *ANALOG CIRCUITRY OMITTED FOR SIMPLICITY +5V A0–A15 8212 (8) (8)AD0–7 Figure 22. DAC8143—8085 Interface DAC8143 INTERFACE TO THE 68000 Figure 23 shows the DAC8143 configured to the 68000 microprocessor. Serial data input is similar to that of the 6800 in Figure 21. STB1 DAC8143 SRI LD2 LD1 STB3 STB4 CLR ADDRESS DECODER A1 A23 AS DB15 DB0 68000mP ADDRESS BUS DATA BUS FROM SYSTEM RESET CS VMA VPA UDS +5V 1/4 74HC125 + STB2 Figure 23. DAC8143 to 68000 mP Interface OUTLINE DIMENSIONS Dimensions are shown in inches and (mm). 16-Lead Plastic DIP (N-16) 16 1 8 9 PIN 1 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) MIN 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 16-Lead SOIC (R-16W) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.050 (1.27) BSC 16 9 1 8 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 0.4133 (10.50) 0.3977 (10.00) 0.0125 (0.32) 0.0091 (0.23) 88 08 0.0291 (0.74) 0.0098 (0.25)3 458 0.0500 (1.27) 0.0157 (0.40) PRINTED IN U.S.A. C3114c–2–3/99 Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual - ADC FEATURES HIGH RESOLUTION - ADCs 2 Independent ADCs (16- and 24-Bit Resolution) Factory-Calibrated (Field Calibration Not Required) Output Settles in 1 Conversion Cycle (Single Conversion Mode) Programmable Gain Front End Simultaneous Sampling and Conversion of 2 Signal Sources Separate Reference Inputs for Each Channel Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz Update Rate ISOURCE Select™ 24-Bit No Missing Codes—Main ADC 13-Bit p-p Resolution @ 20 Hz, 20 mV Range 18-Bit p-p Resolution @ 20 Hz, 2.56 V Range INTERFACE 3-Wire Serial SPI®, QSPI™, MICROWIRE™, and DSP Compatible Schmitt Trigger on SCLK POWER Specified for Single 3 V and 5 V Operation Normal: 1.5 mA Typ @ 3 V Power-Down: 10 A (32 kHz Crystal Running) ON-CHIP FUNCTIONS Rail-Rail Input Buffer and PGA 4-Bit Digital I/O Port On-Chip Temperature Sensor Dual Switchable Excitation Current Sources Low-Side Power Switches Reference Detect Circuit APPLICATIONS Sensor Measurement Temperature Measurement Pressure Measurement Weigh Scales Portable Instrumentation 4 to 20 mA Transmitters GENERAL DESCRIPTION The AD7719 is a complete analog front end for low frequency measurement applications. It contains two high resolution Σ-Δ ADCs, switchable matched excitation current sources, low-side power switches, digital I/O port, and temperature sensor. The 24-bit main channel with PGA accepts fully differential, unipolar, and bipolar input signal ranges from 1.024 × REFIN1/128 to 1.024 × REFIN1. Signals can be converted directly from a transducer without the need for signal conditioning. The 16-bit auxiliary channel has an input signal range of REFIN2 or REFIN2/2. The device operates from a 32 kHz crystal with an on-chip PLL generating the required internal operating frequency. The output data rate from the part is software programmable. The peak-to-peak resolution from the part varies with the programmed gain and output data rate. The part operates from a single 3 V or 5 V supply. When operating from 3 V supplies, the power dissipation for the part is 4.5 mW with both ADCs enabled and 2.85 mW with only the main ADC enabled in unbuffered mode. The AD7719 is housed in 28-lead SOIC and TSSOP packages. FUNCTIONAL BLOCK DIAGRAM MUX AVDD IEXC1 200A IEXC2 200A AVDD AGND MUX1 BUF PGA TEMP SENSOR I/O PORT AVDD MAIN CHANNEL 24-BIT - ADC AUXILIARY CHANNEL 16-BIT - ADC REFERENCE DETECT OSC. AND PLL SERIAL INTERFACE AND CONTROL LOGIC DVDD DGND IOUT1 IOUT2 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AVDD AGND REFIN2 PWRGND P1/SW1 P2/SW2 P3 P4 DOUT DIN SCLK CS RDY RESET REFIN1(+) REFIN1(–) XTAL1 XTAL2 AD7719 MUX2 REV. A AD7719 –2– FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 7 DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9 TYPICAL PERFORMANCE CHARACTERISTICS . . . . 11 DUAL-CHANNEL ADC CIRCUIT INFORMATION . . . 12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Main Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Auxiliary Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Both Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MAIN AND AUXILIARY ADC NOISE PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Communications Register (A3, A2, A1, A0 = 0, 0, 0, 0) . . . . . . . . . . . . . . . . . . . . 19 Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On Reset = 0x00) . . . . . . . . . . . . . . . . . . . . . . . 20 Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On Reset = 0x00) . . . . . . . . . . . . . . . . . . . . . . . 21 Operating Characteristics when Addressing the Mode and Control Registers . . . . . . . . . . . . . . . . . . . . . 22 Main ADC Control Register (AD0CON): (A3, A2, A1, A0 = 0, 0, 1, 0; Power-On Reset = 0x07) . . . . . . . . . . . . . . . . . . . . . . . 22 Aux ADC Control Registers (AD1CON): (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 0x01) . . . . . . . . . . . . . . . . . . . . . . . 23 Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On Reset = 0x45) . . . . . . . . . . . . . . . . . . . . . . . 24 I/O and Current Source Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On Reset = 0x0000) . . . . . . . . . . . . . . . . . . . . . 24 Main ADC Data Result Registers (DATA0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On Reset = 0x00 0000) . . . . . . . . . . . . . . . . . . . 26 Aux ADC Data Result Registers (DATA1): (A3, A2, A1, A0 = 0, 1, 1, 0; Power-On Reset = 0x0000) . . . . . . . . . . . . . . . . . . . . . 26 Main ADC Offset Calibration Coefficient Registers (OF0): (A3, A2, A1, A0 = 1, 0, 0, 0; Power-On Reset = 0x80 0000) . . . . . . . . . . . . . . . . . . . 26 Aux ADC Offset Calibration Coefficient Registers (OF1): (A3, A2, A1, A0 = 1, 0, 0, 1; Power-On Reset = 0x8000) . . . . . . . . . . . . . . . . . . . . . 26 Main ADC Gain Calibration Coefficient Registers (GNO): (A3, A2, A1, A0 = 1, 0, 1, 0; Power-On Reset = 0x5X XXX5) . . . . . . . . . . . . . . . . . 26 Aux ADC Gain Calibration Coefficient Registers (GN1): (A3, A2, A1, A0 = 1, 0, 1, 1; Power-On Reset = 0x59XX) . . . . . . . . . . . . . . . . . . . . . 26 ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On Reset = 0x0X) . . . . . . . . . . . . . . . . . . . . . . . 26 User Nonprogrammable Test Registers . . . . . . . . . . . . . . 26 CONFIGURING THE AD7719 . . . . . . . . . . . . . . . . . . . . . 27 MICROCOMPUTER/MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AD7719-to-68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 29 AD7719-to-8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 29 AD7719-to-ADSP-2103/ADSP-2105 Interface . . . . . . . . 30 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 30 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 32 Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . 32 Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ADC Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 36 3-Wire RTD Configurations . . . . . . . . . . . . . . . . . . . . . . 37 Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 39 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TABLE OF CONTENTS REV. A –3– AD7719 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN to TMAX, unless otherwise noted.) Parameter AD7719B Unit Test Conditions ADC CHANNEL SPECIFICATION Output Update Rate 5.4 Hz min Both Channels Synchronized 105 Hz max 0.732 ms Increments MAIN CHANNEL No Missing Codes2 24 Bits min 20 Hz Update Rate Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate 18 Bits p-p ±2.56 V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables II to V Integral Nonlinearity ±10 ppm of FSR max Typically 2 ppm. Offset Error3 ±3 μV typ Offset Error Drift vs. Temperature4 ±10 nV/°C typ Full-Scale Error5, 6, 7 ±10 μV typ At the Calibrated Conditions Gain Drift vs. Temperature4 ±0.5 ppm/°C typ Power Supply Rejection (PSR) 80 dB min Input Range = ±2.56 V, 100 dB typ. 110 dB typ on ±20 mV Range ANALOG INPUTS Differential Input Voltage Ranges ±1.024 × REFIN1/GAIN V nom REFIN1 = REFIN1(+) – REFIN1(–) GAIN = 1 to 128. ADC Range Matching ±2 μV typ Input Voltage = 19 mV on All Ranges Absolute AIN Voltage Limits AGND + 100 mV V min BUF = 0; Buffered Mode of Operation AVDD – 100 mV V max Analog Input Current2 BUF = 0 DC Input Current ±1 nA max DC Input Current Drift ±5 pA /°C typ Absolute AIN Voltage Limits AGND – 30 mV V min BUF = 1; Unbuffered mode of operation. AVDD + 30 mV V max Analog Input Current BUF = 1. Unbuffered Mode of Operation. DC Input Current ±125 nA/V typ Input Current Varies with Input Voltage DC Input Current Drift ±2 pA/V/°C typ Normal-Mode Rejection2, 8 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, 16.65 Hz Update Rate, SF = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate, SF = 68 Common-Mode Rejection @ DC 90 dB min Input Range = ±2.56 V, AIN = 1 V. 100 dB typ. 110 dB typ on ±20 mV Range @ 50 Hz2 100 dB min 50 Hz ± 1 Hz, Range = ±2.56 V, AIN = 1 V @ 60 Hz2 100 dB min 60 Hz ± 1 Hz, Range = ±2.56 V, AIN = 1 V REFERENCE INPUT (REFIN1) REFIN1 Voltage 2.5 V nom REFIN1 = REFIN1(+) – REFIN1(–) REFIN1 Voltage Range2 1 V min AVDD V max REFIN1 Common-Mode Range AGND – 30 mV V min AVDD + 30 mV V max Reference DC Input Current 0.5 μA/V typ Reference DC Input Current Drift ±0.01 nA/V/°C typ Normal-Mode Rejection2, 8 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF = 68 Common-Mode Rejection @ DC 110 dB typ Input Range = ±2.56 V, AIN = 1 V @ 50 Hz 110 dB typ 50 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V @ 60 Hz 110 dB typ 60 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V Reference Detect Levels 0.3 V min NOXREF Bit Active if VREF < 0.3 V 0.65 V max NOXREF Bit Inactive if VREF > 0.65 V AUXILIARY CHANNEL No Missing Codes2 16 Bits min Resolution 16 Bits p-p ±2.5 V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables VI and VIII Integral Nonlinearity ±15 ppm of FSR max FSR REFIN Gain = 2 × 1.024 1 –SPECIFICATIONS1 REV. A AD7719 –4– Parameter AD7719B Unit Test Conditions AUXILIARY CHANNEL (continued) Offset Error3 ±3 μV typ Selected Channel = AIN5/AIN6 Offset Error Drift vs. Temperature4 ±10 nV/°C typ Full-Scale Error6, 7 ±0.75 LSB typ Gain Drift vs. Temperature4 0.5 ppm/°C typ Negative Full-Scale Error ±1 LSB typ Power Supply Rejection (PSR) 70 dB min AIN = 1 V Input Range = ±2.5 V, Typically 80 dB ANALOG INPUTS Differential Input Voltage Ranges ±REFIN2 V nom ARN = 1 ±REFIN2/2 V nom ARN = 0 Absolute AIN Voltage Limits AGND – 30 mV V min Unbuffered Input AVDD + 30 mV V max Analog Input Current DC Input Current ±125 nA/V typ Input Current Varies with Input Voltage DC Input Current Drift ±2 pA/V/°C typ Normal-Mode Rejection2, 8 @ 50 Hz 100 dB min 50 Hz ±1 Hz, SF = 82 @ 60 Hz 100 dB min 60 Hz ±1 Hz, SF = 68 Common-Mode Rejection @ DC 85 dB min Input Range = ±2.5 V, AIN = 1 V @ 50 Hz2 90 dB min 50 Hz ±1 Hz, Range = 2.5 V, AIN = 1 V @ 60 Hz2 90 dB min 60 Hz ±1 Hz, Range = 2.5 V, AIN = 1 V REFERENCE INPUT (REFIN2) With Respect to AGND REFIN2 Voltage 2.5 V nom REFIN2 Range2 1 V min AVDD V max Reference DC Input Current2 0.2 μA/V typ Reference DC Input Current Drift 0.003 nA/V/°C typ EXCITATION CURRENT SOURCES (IEXC1 and IEXC2) Output Current 200 μA nom Initial Tolerance at 25°C ±10 % typ Drift 200 ppm/°C typ Initial Current Matching at 25°C ±1 % typ Matching between IEXC1 and IEXC2 No Load Drift Matching 20 ppm/°C typ Line Regulation (AVDD) 2.1 μA/V max AVDD = 5 V ± 5%. Typically 1.25 μA/V Load Regulation 300 nA/V typ Output Compliance AVDD – 0.6 V max AGND – 30 mV V min LOW-SIDE POWER SWITCHES (SW1, SW2) RON 5 Ω max AVDD = 5 V. Typically 3 Ω 7 Ω max AVDD = 3 V. Typically 4.5 Ω Allowable Current2 20 mA max Continuous Current per Switch TEMPERATURE SENSOR Accuracy See TPC 5 °C typ TRANSDUCER BURNOUT AIN(+) Current –100 nA typ AIN(–) Current 100 nA typ Initial Tolerance @ 25°C ±15 % typ Drift 0.03 %/°C typ SYSTEM CALIBRATION2, 9 Full-Scale Calibration Limit 1.05 × FS10 V max Zero-Scale Calibration Limit –1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max REV. A –5– AD7719 Parameter AD7719B Unit Test Conditions LOGIC INPUTS All Inputs Except SCLK and XTAL12 VINL, Input Low Voltage 0.8 V max DVDD = 5 V 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.0 V min DVDD = 3 V or 5 V SCLK Only (Schmitt-Triggered Input)2 VT(+) 1.4/2 V min/V max DVDD = 5 V VT(–) 0.8/1.4 V min/V max DVDD = 5 V VT(+) – VT(–) 0.3/0.85 V min/V max DVDD = 5 V VT(+) 0.95/2 V min/V max DVDD = 3 V VT(–) 0.4/1.1 V min/V max DVDD = 3 V VT(+) – VT(–) 0.3/0.85 V min/V max DVDD = 3 V XTAL1 Only2 VINL, Input Low Voltage 0.8 V max DVDD = 5 V VINH, Input High Voltage 3.5 V min DVDD = 5 V VINL, Input Low Voltage 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.5 V min DVDD = 3 V Input Currents ±10 μA max VIN = DVDD –70 μA max VIN = DGND, Typically –40 μA at 5 V and –20 μA at 3 V Input Capacitance2 10 pF typ All Digital Inputs LOGIC OUTPUTS (Excluding XTAL2) VOH, Output High Voltage2 DVDD – 0.6 V min DVDD = 3 V, ISOURCE = 100 μA VOL, Output Low Voltage2 0.4 V max DVDD = 3 V, ISINK = 100 μA VOH, Output High Voltage2 4 V min DVDD = 5 V, ISOURCE = 200 μA VOL, Output Low Voltage 2 0.4 V max DVDD = 5 V, ISINK = 1.6 mA Floating-State Leakage Current ±10 μA max Floating-State Output Capacitance ±10 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode I/O PORT11 I/O Port Voltages Are with Respect to AVDD and AGND VINL, Input Low Voltage2 0.8 V max AVDD = 5 V 0.4 V max AVDD = 3 V VINH, Input High Voltage2 2.0 V min AVDD = 3 V or 5 V Input Currents ±10 μA max VIN = AVDD –70 μA max VIN = AGND, Typically –40 μA at AVDD = 5 V and –20 μA at AVDD = 3 V Input Capacitance 10 pF typ All Digital Inputs VOH, Output High Voltage2 AVDD – 0.6 V min AVDD = 3 V, ISOURCE = 100 μA VOL, Output Low Voltage2 0.4 V max AVDD = 3 V, ISINK = 100 μA VOH, Output High Voltage2 4 V min AVDD = 5 V, ISOURCE = 200 μA VOL, Output Low Voltage2 0.4 V max AVDD = 5 V, ISINK = 1.6 mA Floating-State Output Leakage Current ±10 μA max Floating-State Output Capacitance ±10 pF typ START-UP TIME From Power-On 300 ms typ From Idle Mode 1 ms typ From Power-Down Mode 1 ms typ Osc. Active in Power-Down 300 ms typ Osc. Powered Down POWER REQUIREMENTS Power Supply Voltages AVDD – AGND 2.7/3.6 V min/max AVDD = 3 V nom 4.75/5.25 V min/max AVDD = 5 V nom DVDD – DGND 2.7/3.6 V min/max DVDD = 3 V nom 4.75/5.25 V min DVDD = 5 V nom Power Supply Currents DIDD Current (Normal Mode)12 0.6 mA max DVDD = 3 V, 0.5 mA typ 0.75 mA max DVDD = 5 V, 0.6 mA typ REV. A AD7719 –6– Parameter AD7719B Unit Test Conditions Power Supply Currents (Continued) AIDD Current (Main ADC) 1.1 mA max AVDD = 3 V or 5 V, Buffered Mode, 0.85 mA typ 0.55 mA max AVDD = 3 V or 5 V, Unbuffered Mode, 0.45 mA typ AIDD Current (Aux ADC) 0.3 mA max AVDD = 3 V or 5 V, 0.25 mA typ AIDD Current (Main and Aux ADC) 1.25 mA max AVDD = 3 V or 5 V, Main ADC Buffered, 1 mA typ DIDD (ADC Disable Mode)13 0.35 mA max DVDD = 3 V, 0.25 mA typ 0.4 mA max DVDD = 5 V, 0.3 mA typ AIDD (ADC Disable Mode) 0.15 mA max AVDD = 3 V or 5 V DIDD (Power-Down Mode) 10 μA max DVDD = 3 V, 32.768 kHz Osc. Running 2 μA max DVDD = 3 V, Oscillator Powered Down 30 μA max DVDD = 5 V, 32.768 kHz Osc. Running 8 μA max DVDD = 5 V, Oscillator Powered Down AIDD (Power-Down Mode) 1 μA max AVDD = 3 V or 5 V NOTES 1Temperature range –40°C to +85°C. 2Guaranteed by design and/or characterization data on production release. 3System zero calibration will remove this error. 4A calibration at any temperature will remove this drift error. 5The main ADC is factory-calibrated with AVDD = DVDD = 4 V, TA = 25°C, REFIN1(+) – REFIN1(–) = 2.5 V. If the user power supplies or temperature conditions are significantly different from these, internal full-scale calibration will restore this error to the published specification. System calibration can be used to reduce this error to the order of the noise. Full-scale error applies to both positive and negative full scale. 6A system full-scale calibration will remove this error. 7A typical gain error of ±10 μV results following a user self-calibration. 8Simultaneous 50 Hz and 60 Hz rejection is achieved using 19.8 Hz (SF = 69) update rate. Normal mode rejection in this case is 60 dB min. 9After a calibration if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s. 10FS = Full-Scale Input. FS = 1.024 × REFIN1/Gain on the main ADC, where REFIN1 = REFIN1(+) – REFIN1(–). FS = REFIN2 on the aux ADC when ARN = 1 in the aux ADC control register (AD1CON) and REFIN2/2 on the aux ADC when ARN = 0. 11 Input and output levels on the I/O Port are with respect to AVDD and AGND. 12Normal mode refers to the case where both main and aux ADCs are running. 13ADC disable is entered by setting both the AD0EN and AD1EN bits in the main and aux ADC control registers to a 0 and setting the mode bits (MD2, MD1, MD0) in the mode register to non-0. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C, unless otherwise noted.) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND2. . . . . . . . . . . . . . . . . . . –20 mV to +20 mV PWRGND to AGND . . . . . . . . . . . . . . . . –20 mV to +20 mV AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V Analog Input Voltage to AGND . . . . –0.3 V to AVDD +0.3 V Reference Input Voltage to AGND . . –0.3 V to AVDD +0.3 V Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . 30 mA Digital Input Voltage to DGND . . . . –0.3 V to DVDD +0.3 V Digital Output Voltage to DGND . . . –0.3 V to DVDD +0.3 V Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C SOIC Package θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 71.4°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 23°C/W TSSOP Package θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 97.9°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 14°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AGND and DGND are connected internally within the AD7719. ORDERING GUIDE Model Temperature Range Package Description Package Option AD7719BR –40°C to +85°C SOIC R-28 AD7719BRU –40°C to +85°C TSSOP RU-28 EVAL-AD7719EB Evaluation Board REV. A –7– AD7719 TIMING CHARACTERISTICS1, 2 Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments t1 32.768 kHz typ Crystal Oscillator Frequency t2 50 ns min RESET Pulsewidth Read Operation t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t5 4 0 ns min SCLK Active Edge to Data Valid Delay3 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t5A 4, 5 0 ns min CS Falling Edge to Data Valid Delay3 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 t9 6 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with t R = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2See Figures 2 and 3. 3SCLK active edge is falling edge of SCLK. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 5This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after a read of both ADCs. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. Specifications subject to change without notice. (AVDD = 2.7 V to 3.6 V or AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 3.6 V or DVDD = 4.75 V to 5.25 V; AGND = DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.) ISINK (1.6mA WITH DVDD = 5V 100A WITH DVDD = 3V) 1.6V ISOURCE (200A WITH DVDD = 5V 100A WITH DVDD = 3V) TO OUTPUT PIN 50pF Figure 1. Load Circuit for Timing Characterization CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7719 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A AD7719 –8– DIGITAL INTERFACE As previously outlined, the AD7719’s programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the part’s serial interface; read access to the on-chip registers is also provided by this interface. All communications to the part must start with a write operation to the Communications register. After power-on or RESET, the device expects a write to its Communications register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the Communications register followed by a write to the selected register. A read operation from any other register on the part (including the output data register) starts with a write operation to the Communications register followed by a read operation from the selected register. The AD7719’s serial interface consists of five signals: CS, SCLK, DIN, DOUT, and RDY. The DIN line is used for transferring data into the on-chip registers while the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The RDY line is used as a status signal to indicate when data is ready to be read from the AD7719’s data register. RDY goes low when a new data-word is available in the output register of either the main or aux ADCs. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select the device. It can be used to decode the AD7719 in systems where a number of parts are connected to the serial bus. Figures 2 and 3 show timing diagrams for interfacing to the AD7719 with CS used to decode the part. Figure 3 is for a read operation from the AD7719’s output shift register while Figure 2 shows a write operation to the input shift register. It is possible to read the same data twice from the output register even though the RDY line returns high after the first read operation. Care must be taken, however, to ensure that the read operations have been completed before the next output update is about to take place. The AD7719 serial interface can operate in 3-wire mode by tying the CS input low. In this case, the SCLK, DIN, and DOUT lines are used to communicate with the AD7719, and the status of RDY bits (RDY0 and RDY1) can be obtained by interrogating the STATUS register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK idles high between data transfers. The AD7719 can also be operated with CS used as a frame synchronization signal. This scheme is suitable for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS since CS would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers provided the timing numbers are obeyed. t12 t13 t14 t15 t11 t16 MSB LSB CS SCLK DIN Figure 2. Write Cycle Timing Diagram t5 t5A t4 t6 t3 t9 MSB LSB CS SCLK t8 t10 t7 t6 DOUT RDY Figure 3. Read Cycle Timing Diagram REV. A AD7719 –9– PIN CONFIGURATION 14 13 12 11 10 17 16 15 19 18 20 28 27 26 25 24 23 22 21 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) AD7719 IOUT1 DGND DVDD XTAL2 XTAL1 IOUT2 AVDD AGND RDY DOUT REFIN1(–) DIN REFIN1(+) AIN1 AIN2 AIN3 AIN4 RESET SCLK CS AIN5 AIN6 REFIN2 P4 P1/SW1 P3 P2/SW2 PWRGND PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 IOUT1 Output for Internal 200 μA Excitation Current Source. Current source IEXC1 and/or IEXC2 can be switched to this output. 2 IOUT2 Output for Internal 200 μA Excitation Current Source. Current source IEXC1 and/or IEXC2 can be switched to this output. 3 AVDD Analog Supply Voltage. 4 AGND Analog Ground. 5 REFIN1(–) Negative Reference Input for Main ADC Channel. This reference input can lie anywhere between AGND and AVDD – 1 V. 6 REFIN1(+) Positive Reference Input for Main ADC Channel. REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage (REFIN1(+) – REFIN1(–)) is 2.5 V, but the part is functional with a reference range from 1 V to AVDD. 7 AIN1 Analog Input. AIN1 is dedicated to the main channel. 8 AIN2 Analog Input. AIN2 is dedicated to the main channel. 9 AIN3 Analog Input. AIN3 can be multiplexed to either the main or auxiliary channel. 10 AIN4 Analog Input. AIN4 can be multiplexed to either the main or auxiliary channel. 11 AIN5 Analog Input. AIN5 is dedicated to the auxiliary channel and is referenced to AIN6 or AGND. 12 AIN6 Analog Input. AIN6 is dedicated to the auxiliary channel. It forms a differential input pair with AIN5 in fully differential input mode or is referenced to AGND in pseudodifferential mode. 13 REFIN2 Single-Ended Reference Input for Auxiliary Channel. The nominal input reference is 2.5 V. The auxiliary channel will function with an input reference range from 1 V to AVDD. 14 P4 General-Purpose I/O Bit. The input and output voltage levels are referenced to AVDD and AGND. 15 P3 General-Purpose I/O Bit. The input and output voltage levels are referenced to AVDD and AGND. The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series of 1s on the DIN input. If a logic 1 is written to the AD7719 DIN line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in 3-wire systems, if the interface gets lost, either via a software error or by some glitch in the system, it can be reset back to a known state. This state returns the interface to where the AD7719 is expecting a write operation to its Communications register. This operation resets the contents of all registers to their power-on reset values. Some microprocessor or microcontroller serial interfaces have a single serial data line. In this case, it is possible to connect the AD7719’s DATA OUT and DATA IN lines together and connect them to the single data line of the processor. A 10 kΩ pull-up resistor should be used on this single data line. In this case, if the interface gets lost, because the read and write operations share the same line, the procedure to reset it to a known state is somewhat different than previously described. It requires a read operation of 24 serial clocks followed by a write operation where a logic 1 is written for at least 32 serial clock cycles to ensure that the serial interface is back in a known state. REV. A AD7719 –10– PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Function 16 P2/SW2 Dual-Purpose Pin. It can act as a general-purpose output (P2) bit referenced between AVDD and AGND or as a low-side power switch (SW2) to PWRGND. 17 PWRGND Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to AGND. 18 P1/SW1 Dual-Purpose Pin. It can act as a general-purpose output (P1) bit referenced between AVDD and AGND or as a low-side power switch (SW1) to PWRGND. 19 RESET Digital Input Used to Reset the ADC to Its Power-On Reset Status. This pin has a weak pull-up internally to DVDD. 20 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7719 in smaller batches of data. A weak pull-up to DVDD is provided on the SCLK input. 21 CS Chip Select Input. This is an active low logic input used to select the AD7719. CS can be used to select the AD7719 in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the AD7719 to be operated in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. A weak pull-up to DVDD is provided on the CS input. 22 RDY RDY is a logic low status output from the AD7719. RDY is low if either the main ADC or auxiliary ADC channel has valid data in its data register. This output returns high on completion of a read operation from the data register. If data is not read, RDY will return high prior to the next update, indicating to the user that a read operation should not be initiated. The RDY pin also returns low following the completion of a calibration cycle. The RDY pin is effectively the digital NOR function of the RDY0 and RDY1 bits in the Status register. If one of the ADCs is disabled, the RDY pin reflects the active ADC. RDY does not return high after a calibration until the mode bits are written to, enabling a new conversion or calibration. Since the RDY pin provides information on both the main and aux ADCs, when either the main or aux ADC is disabled, it is recommended to immediately read its data register to ensure that its RDY bit goes inactive and releases the RDY pin to indicate output data updates on the remaining active ADC. 23 DOUT Serial Data Output Accessing the Output Shift Register of the AD7719. The output shift register can contain data from any of the on-chip data, calibration, or control registers. 24 DIN Serial Data Input Accessing the Input Shift Register on the AD7719. Data in this shift register is transferred to the calibration or control registers within the ADC depending on the selection bits of the Communications register. A weak pull-up to DVDD is provided on the DIN input. 25 DGND Ground Reference Point for the Digital Circuitry. 26 DVDD Digital Supply Voltage, 3 V or 5 V Nominal. 27 XTAL2 Output from the 32 kHz Crystal Oscillator Inverter. 28 XTAL1 Input to the 32 kHz Crystal Oscillator Inverter. REV. A AD7719 –11– Typical Performance Characteristics– READING NO. 8389600 8389400 8388000 0 100 1000 CODE READ 200 300 8389200 400 500 600 700 800 900 8389000 8388800 8388600 8388400 8388200 AVDD = DVDD = 5V INPUT RANGE = 20mV REFIN1(+)–REFIN1(–) = 2.5V UPDATE RATE = 19.79Hz MAIN ADC IN BUFFERED MODE RMS NOISE = 0.58V rms TA = 25C VREF = 2.5V TPC 1. Typical Noise Plot on ±20 mV Input Range with 19.79 Hz Update Rate 8 7 0 8388039 8388721 8388687 8388657 8388615 8388579 8388547 8388499 8388449 8388382 8388754 8389110 8389033 8388985 8388941 8388906 8388874 8388841 8388805 8388779 6 5 4 3 2 1 9 TPC 2. Noise Distribution Histogram 2.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 1.5 1.0 0.5 3.0 VREF (V) RMS NOISE (V) 20mV RANGE 2.56V RANGE AVDD = DVDD = 5V VREF = 2.5V INPUT RANGE = 2.56V UPDATE RATE = 19.79Hz TA = 25C TPC 3. RMS Noise vs. Reference Input 16 0 10 20 30 40 50 60 70 80 90 100 24 22 20 18 26 UPDATE RATE (Hz) NO MISSING CODES (Min) 110 TPC 4. No-Missing-Codes Performance TEMPERATURE SENSOR ( C) 1400 1200 0 10 20 30 40 50 HITS 800 600 400 200 1000 THE AMBIENT TEMPERATURE VARIES FROM 25C TO 30C WHILE RECORDING THE DATA FROM THE DEVICES. TPC 5. Temperature Sensor Accuracy MAIN CAL ACC. @ 4V (V) 1200 0 –20 –10 0 10 20 HITS 800 600 400 200 1000 –30 TPC 6. Full-Scale Error Distribution REV. A AD7719 –12– DUAL-CHANNEL ADC CIRCUIT INFORMATION Overview The AD7719 incorporates two independent Σ-Δ ADC channels (main and auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, pressure transducer, or temperature measurement applications. Main Channel This channel is intended to convert the primary sensor input. This channel can be operated in buffered or unbuffered mode, and can be programmed to have one of eight input voltage ranges from ±20 mV to ±2.56 V. This channel can be configured as either two fully differential inputs (AIN1/AIN2 and AIN3/AIN4) or three pseudodifferential input channels (AIN1/AIN4, AIN2/ AIN4, and AIN3/AIN4). Buffering the input channel means that the part can accommodate significant source impedances on the analog input and that R, C filtering (for noise rejection or RFI reduction) can be placed on the analog inputs if required. Operating in unbuffered mode leads to lower power consumption in low power applications, but care must be exercised in unbuffered mode because source impedances can introduce gain errors. The main ADC also features sensor burnout currents that can be switched on and off. These currents can be used to check that a transducer is still operational before attempting to take measurements. The ADC employs a Σ-Δ conversion technique to realize up to 24 bits of no-missing-codes performance. The Σ-Δ modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. A Sinc3 programmable low-pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A chopping scheme is also employed to minimize ADC channel offset errors. A block diagram of the main ADC input channel is shown in Figure 4. The sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal. The integrator in the modulator shapes the quantization noise (which results from the analog-to-digital conversion) so that the noise is pushed toward one-half of the modulator frequency. The output of the Σ-Δ modulator feeds directly into the digital filter. The digital filter then band-limits the response to a frequency significantly lower than one-half of the modulator frequency. In this manner, the 1-bit output of the comparator is translated into a band-limited, low noise output from the AD7719 ADC. The AD7719 filter is a low-pass, Sinc3, or (SIN(x)/x)3 filter whose primary function is to remove the quantization noise introduced at the modulator. The cutoff frequency and decimated output data rate of the filter are programmable via the SF word loaded to the filter register. A chopping scheme is employed where the complete signal chain is chopped, resulting in excellent dc offset and offset drift specifications, and is extremely beneficial in applications where drift, noise rejection, and optimum EMI rejection are important factors. With chopping, the ADC repeatedly reverses its inputs. The decimated digital output words from the Sinc3 filters therefore have a positive offset and negative offset term included. As a result, a final summing stage is included so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data register. Auxiliary Channel The Auxiliary (Aux) channel is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This channel is unbuffered and has an input range of ±REFIN2 or ±REFIN2/2, determined by the ARN bit in the auxiliary ADC control register (AD1CON). AIN3 and AIN4 can be multiplexed into the auxiliary channel as single-ended inputs with respect to AGND, while AIN5 and AIN6 can operate as a differential input pair. With AIN6 tied to AGND, AIN5 can be operated as an additional single-ended input. A block diagram of the auxiliary ADC channel is shown in Figure 5. SINC3 FILTER MUX BUF PGA MOD0 ANALOG XOR INPUT DIGITAL OUTPUT 1 8  SF  3 ( ) 3  (8  SF )  12 AIN + VOS AIN – VOS fCHOP fIN fMOD fCHOP fADC - Figure 4. Main ADC Channel Block Diagram OSCILLATOR AVDD = DVDD = 5V TA = 25C TIME BASE = 100ms/DIV TRACE 1 = TRACE 2 = 2V/DIV VDD TPC 7. Typical Oscillator Power-Up REV. A AD7719 –13– Both Channels The operation of the aux channel is identical to the main channel with the exception that there is no PGA on the aux channel. The input chopping is incorporated into the input multiplexer while the output chopping is accomplished by an XOR gate at the output of the modulator. The chopped modulator bit stream is applied to a Sinc3 filter. The programming of the Sinc3 decimation factor is restricted to an 8-bit register SF; the actual decimation factor is the register value times 8. The decimated output rate from the Sinc3 filter (and the ADC conversion rate) will therefore be f SF ADC = × fMOD ×       × 1 3 1 8 where: fADC is the ADC update rate. SF is the decimal equivalent of the word loaded to the filter register. fMOD is the modulator sampling rate of 32.768 kHz. Programming the filter register determines the update rate for both the main and aux ADC. Both ADCs operate with the same update rate. The chop rate of the channel is half the output data rate. The frequency response of the filter H (f) is as follows: 1 8 8 1 2 2 3 SF SF f f f f f f f f MOD MOD OUT × OUT × × × × ×       × × × × ×       sin ( / ) sin ( / ) sin ( / ) sin ( / ) π π π π where: fMOD = 32,768 Hz SF = value programmed into SF SFR. fOUT = fMOD/(SF × 8 × 3) The following shows plots of the filter frequency response for the SF words shown in Table I. The overall frequency response is the product of a Sinc3 and a sinc response. There are Sinc3 notches at integer multiples of 3 × fADC and there are sinc notches SINC3 FILTER MUX - MOD1 ANALOG XOR INPUT DIGITAL OUTPUT 3  (8  SF )  12 AIN + VOS AIN – VOS fCHOP fMOD fCHOP fADC 1 8  SF  3 ( ) Figure 5. Auxiliary ADC Channel Block Diagram at odd integer multiples of fADC/2. The 3 dB frequency for all values of SF obeys the following equation: f (3 dB) = 0.24 × fADC The signal chain is chopped as shown in Figures 4 and 5. The chop frequency is f f CHOP =  ADC      2 As shown in the block diagram, the Sinc3 filter outputs alternately contain +VOS and –VOS, where VOS is the respective channel offset. This offset is removed by performing a running average of 2. This average by 2 means that the settling time to any change in programming of the ADC will be twice the normal conversion time, while an asynchronous step change on the analog input will not be fully reflected until the third subsequent output. t f SETTLE t ADC = ADC       = × 2 2 The allowable range for SF is 13 to 255, with a default of 69 (0x45). The corresponding conversion rates, conversion times, and settling times are tabulated in Table I. Note that the conversion time increases by 0.732 ms for each increment in SF. Table I. ADC Conversion and Settling Times for Various SF Words SF Data Update Rate Settling Time Word fADC (Hz) tSETTLE (ms) 13 105.3 19.04 69 (Default) 19.79 101.07 255 5.35 373.54 Normal mode rejection is the major function of the digital filter on the AD7719. The normal mode 50 Hz ± 1 Hz rejection with an SF word of 82 is typically –100 dB. The 60 Hz ± 1 Hz rejection with SF = 68 is typically –100 dB. Simultaneous 50 Hz and 60 Hz rejection of better than 60 dB is achieved with an SF of 69. Choosing an SF word of 69 places notches at both 50 Hz and 60 Hz. Figures 6 to 9 show the filter rejection for a selection of SF words. REV. A AD7719 –14– MAIN AND AUXILIARY ADC NOISE PERFORMANCE Tables II to VII show the output rms noise and output peak-topeak resolution in bits (rounded to the nearest 0.5 LSB) for a selection of output update rates on both the main and auxiliary ADCs. The numbers are typical and are generated at a differential input voltage of 0 V. The output update rate is selected via the SF7 to SF0 bits in the Filter register. It is important to note that the peak-to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges, the rms noise numbers will be the same as the bipolar range, but the peak-to-peak resolution is now based on half the signal range, which effectively means losing one bit of resolution. FREQUENCY (Hz) 0 –140 –200 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 ATTENUATION (dB) –20 –120 –160 –180 –60 –100 –40 –80 SF = 13 OUTPUT DATA RATE = 105Hz INPUT BANDWIDTH = 25.2Hz FIRST NOTCH = 52.5Hz 50Hz REJECTION = –23.6dB, 50Hz  1Hz REJECTION = –20.5dB 60Hz REJECTION = –14.6dB, 60Hz  1Hz REJECTION = –13.6dB Figure 6. Filter Profile with SF = 13 FREQUENCY (Hz) 0 –80 –160 0 10 100 ATTENUATION (dB) 20 30 40 50 60 70 80 90 –20 –40 –120 –140 –60 –100 SF = 82 OUTPUT DATA RATE = 16.65Hz INPUT BANDWIDTH = 4Hz 50Hz REJECTION = –171dB, 50Hz  1Hz REJECTION = –100dB 60Hz REJECTION = –58dB, 60Hz  1Hz REJECTION = –53dB Figure 7. Filter Profile with SF = 82 FREQUENCY (Hz) 0 –80 –160 0 10 100 ATTENUATION (dB) 20 30 40 50 60 70 80 90 –20 –40 –120 –140 –60 –100 SF = 69 OUTPUT DATA RATE = 19.8Hz INPUT BANDWIDTH = 4.74Hz FIRST NOTCH = 9.9Hz 50Hz REJECTION = –66dB, 50Hz  1Hz REJECTION = –60dB 60Hz REJECTION = –117dB, 60Hz  1Hz REJECTION = –94dB Figure 8. Filter Profile with Default SF = 69 Giving Filter Notches at Both 50 Hz and 60 Hz FREQUENCY (Hz) 0 –80 –160 0 10 100 ATTENUATION (dB) 20 30 40 50 60 70 80 90 –20 –40 –120 –140 –60 –100 SF = 255 OUTPUT DATA RATE = 5.35Hz INPUT BANDWIDTH = 1.28Hz 50Hz REJECTION = –93dB, 50Hz  1Hz REJECTION = –93dB 60Hz REJECTION = –74dB, 60Hz  1Hz REJECTION = –68dB Figure 9. Filter Profile with SF = 255 REV. A AD7719 –15– Table II. Typical Output RMS Noise vs. Input Range and Update Rate for Main ADC (Buffered Mode) Output RMS Noise in V SF Data Update Input Range Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 Table III. Peak-to-Peak Resolution vs. Input Range and Update Rate for Main ADC (Buffered Mode) Peak-to-Peak Resolution in Bits SF Data Update Input Range Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13 14 15 16 17 17.5 18 18.5 255 5.35 14 15 16 17 18 18.5 18.8 19.2 Table IV. Typical Output RMS Noise vs. Input Range and Update Rate for Main ADC (Unbuffered Mode) Output RMS Noise in V SF Data Update Input Range Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 105.3 1.27 1.27 1.35 1.48 2.95 3.82 5.69 10.2 69 19.79 0.52 0.56 0.56 0.56 0.56 0.82 1.21 2.00 255 5.35 0.30 0.30 0.32 0.32 0.32 0.44 0.71 1.10 Table V. Peak-to-Peak Resolution vs. Input Range and Update Rate for Main ADC (Unbuffered Mode) Peak-to-Peak Resolution in Bits SF Data Update Input Range Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13 14 15 16 17 17.5 18 18.5 255 5.35 14 15 16 17 18 18.5 19 19.5 Table VI. Typical Output RMS Noise vs. Update Rate for Auxiliary ADC (Unbuffered Mode) SF Data Update Input Range Word Rate (Hz) 2.5 V 13 105.3 10.75 μV 69 19.79 2.00 μV 255 5.35 1.15 μV Table VII. Peak-to-Peak Resolution vs. Update Rate for Auxiliary ADC (Unbuffered Mode) SF Data Update Input Range Word Rate (Hz) 2.5 V 13 105.3 16 Bits 69 19.79 16 Bits 255 5.35 16 Bits REV. A AD7719 –16– DOUT FILTER REGISTER DIN DOUT TEST REGISTER DIN DOUT ID REGISTER DOUT AUX ADC GAIN REGISTER DIN ADC STATUS REGISTER DOUT DOUT MODE REGISTER DIN DOUT MAIN ADC CONTROL REGISTER DIN DOUT AUX ADC CONTROL REGISTER DIN DOUT I/O CONTROL REGISTER DIN DOUT MAIN ADC GAIN REGISTER DIN DOUT AUX ADC OFFSET REGISTER DIN DOUT MAIN ADC OFFSET REGISTER DIN DOUT AUX ADC DATA REGISTER DOUT MAIN ADC DATA REGISTER WEN R/W 0 0 A3 A2 A1 A0 COMMUNICATIONS REGISTER DOUT DIN REGISTER SELECT DECODER Figure 10. On-Chip Registers ON-CHIP REGISTERS Both the main and auxiliary ADC channels are controlled and configured via a number of on-chip registers as shown in Figure 10 and described in more detail in the following pages. In the following descriptions, SET implies a logic 1 state and CLEARED implies a logic 0 state, unless otherwise stated. REV. A AD7719 –17– Table VIII. Registers—Quick Reference Guide Power-On/Reset Register Name Type Size Default Value Function Communications Write Only 8 Bits Not Applicable All operations to other registers are initiated through the Communications register. This controls whether subsequent operations are read or write operations and also selects the register for that subsequent operation. Status Register Read Only 8 Bits 0x00 Provides status information on conversions, calibrations, error conditions, and the validity of the reference voltage. Mode Register Read/Write 8 Bits 0x00 Controls functions such as mode of operation, channel configuration, and oscillator operation in power-down. Main ADC (AD0CON) Control Register Read/Write 8 Bits 0x07 This register is used to enable the main ADC and to configure the main ADC for range, channel selection, 16-/24-bit operation, and unipolar or bipolar operation. Aux ADC (AD1CON) Control Register Read/Write 8 Bits 0x01 This register is used to enable the aux ADC and to configure the Aux ADC for range, channel selection, unipolar or bipolar operation, and input range. I/O (IOCON) Control Register Read/Write 16 Bits 0x0000 This register is used to control and configure the various excitation and burnout current source options available on-chip along with controlling the I/O port. Filter Register Read/Write 8 Bits 0x45 This register determines the amount of averaging performed by the sinc filter and consequently determines the data update rate of the AD7719. The filter register determines the update rate for both the main and aux ADCs. MSB LSB RDY0 RDY1 CAL NOREF ERR0 ERR1 0 LOCK MSB LSB SF7 SF6 SF5 SF4 SF3 SF2 SF1 SF0 MSB PSW2 PSW1 0 BO I2PIN I1PIN I2EN I1EN LSB P4DIR P3DIR P2EN P1EN P4DAT P3DAT P2DAT P1DAT MSB LSB WEN R/W 0 0 A3 A2 A1 A0 MSB LSB 0 BUF 0 CHCON OSCPD MD2 MD1 MD0 MSB LSB AD0EN WL CH1 CH0 U/B RN2 RN1 RN0 MSB LSB AD1EN ACH2 ACH1 ACH0 U/B 0 0 ARN REV. A AD7719 –18– Power-On/Reset Register Name Type Size Default Value Function Main ADC (DATA0) Data Register Read Only 16 Bits or 24 Bits 0x00 0000 Provides the most up-to-date conversion result from the main ADC. Main ADC data register length can be programmed to be 16-bit or 24-bit. Aux ADC (DATA1) Data Register Read Only 16 Bits 0x0000 Provides the most up-to-date conversion result from the auxiliary ADC. Aux ADC data register length is 16 bits. Main ADC Offset Register Read/Write 24 Bits 0x80 0000 Contains a 24-bit word that is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. There are three offset registers on the part and these are associated with input channel pairs as outlined in the AD0CON register. Main ADC Gain Register Read/Write 24 Bits 0x5X XXX5 Contains a 24-bit word that is the gain calibration coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. There are three Gain registers on the part, which are associated with input channel pairs as outlined in the AD0CON register. Aux ADC Offset Register Read/Write 16 Bits 0x8000 Contains a 16-bit word that is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. Aux ADC Gain Register Read/Write 24 Bits 0x59XX Contains a 16-bit word that is the gain calibration coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. ID Register Read 8 Bits 0x0X Contains an 8-bit byte that is the identifier for the part. Test Registers Read/Write 16 Bits 0x0000 Controls the test modes of the part, which are used when testing the part. The user is advised not to change the contents of these registers. REV. A AD7719 –19– CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN (0) R/W (0) 0 (0) 0 (0) A3 (0) A2 (0) A1 (0) A0 (0) Table IX. Communications Register Bit Designations Bit Bit Location Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communications register. CR6 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. CR5 Zero A 0 must be written to this bit position to ensure correct operation of the AD7719. CR4 Zero A 0 must be written to this bit position to ensure correct operation of the AD7719. CR3–CR0 A3–A0 Register Address Bits. These address bits are used to select which of the AD7719’s registers is being accessed during this serial interface communication. A3 is the MSB of the three selection bits. Communications Register (A3, A2, A1, A0 = 0, 0, 2, 0) The Communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications register. The data written to the Communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications register. This is the default state of the interface, and on power-up or after a RESET, the AD7719 is in this default state waiting for a write operation to the Communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the AD7719 to this default state by resetting the part. Table IX outlines the bit designations for the Communications register. CR0 through CR7 indicate the bit location, with CR denoting that the bits are in the Communications register. CR7 denotes the first bit of the data stream. Table X. Register Selection Table A3 A2 A1 A0 Register 0 0 0 0 Communications Register during a Write Operation 0 0 0 0 Status Register during a Read Operation 0 0 0 1 Mode Register 0 0 1 0 Main ADC Control Register (AD0CON) 0 0 1 1 Aux ADC Control Register (AD1CON) 0 1 0 0 Filter Register 0 1 0 1 Main ADC Data Register 0 1 1 0 Aux ADC Data Register 0 1 1 1 I/O Control Register 1 0 0 0 Main ADC Offset Calibration Register 1 0 0 1 Aux ADC Offset Calibration Register 1 0 1 0 Main ADC Gain Calibration Register 1 0 1 1 Aux ADC Gain Calibration Register 1 1 0 0 Test 1 Register 1 1 0 1 Test 2 Register 1 1 1 0 Undefined 1 1 1 1 ID Register REV. A AD7719 –20– Table XI. Status Register Bit Designations Bit Bit Location Name Description SR7 RDY0 Ready Bit for Main ADC. Set when data is written to main ADC data registers or on completion of calibration cycle. The RDY0 bit is cleared automatically after the main ADC data register has been read or after a period of time before the data register is updated with a new conversion result. This bit is also cleared by a write to the mode bits to indicate a conversion or calibration. SR6 RDY1 Ready Bit for Aux ADC. Set when data is written to aux ADC data registers or on completion of calibration cycle. The RDY1 bit is cleared automatically after the aux ADC data register has been read or a period of time before the data register is updated with a new conversion result. This bit is also cleared by a write to the mode bits to indicate a conversion or calibration. SR5 CAL Calibration Status Bit. Set to indicate completion of calibration. It is set at the same time that the RDY0 and/or RDY1 bits are set high. Cleared by a write to the mode bits to start another ADC conversion or calibration. SR4 NOXREF No External Reference Bit. (Only active if main ADC is active and applies to REFIN1 only.) Set to indicate that one or both of the REFIN1 pins is floating or the applied voltage is below a specified threshold. When Set, conversion results are clamped to all 1s. Cleared to indicate valid reference applied between REFIN1(+) and REFIN1(–). SR3 ERR0 Main ADC Error Bit. Set to indicate that the result written to the main ADC data registers has been clamped to all 0s or all 1s. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Error sources include Overrange, Underrange, and NOXREF. Cleared by a write to the mode bits to initiate a conversion or calibration. SR2 ERR1 Aux ADC Error Bit. Set to indicate that the result written to the Aux ADC data registers has been clamped to all 0s or all 1s. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Error sources include Overrange, Underrange, and NOXREF. Cleared by a write to the mode bits to initiate a conversion or calibration. SR1 0 Reserved for Future Use. SR0 LOCK PLL Lock Status Bit. Set if the PLL has locked onto the 32 kHz crystal oscillator clock. If the user is worried about exact sampling frequencies, for example, the LOCK bit should be interrogated and the result discarded if the LOCK bit is 0. Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On Reset = 0x00) The ADC Status register is an 8-bit read-only register. To access the ADC Status register, the user must write to the Communications register selecting the next operation to be a read and loading bits A3 to A0 with 0, 0, 0, 0. Table XI outlines the bit designations for the Status register. SR0 through SR7 indicate the bit location, with SR denoting that the bits are in the Status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY0 (0) RDY1 (0) CAL (0) NOXREF (0) ERR0 (0) ERR1 (0) (0) LOCK (0) REV. A AD7719 –21– Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On Reset = 0x00) The Mode register is an 8-bit register from which data can be read or to which data can be written. This register configures the operating modes of the AD7719. Table XII outlines the bit designations for the Mode register. MR7 through MR0 indicate the bit location, with MR denoting the bits are in the Mode register. MR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Table XII. MODE Register Bit Designations Bit Bit Location Name Description MR7 0 Reserved for Future Use. MR6 BUF Configures the main ADC for buffered or unbuffered mode of operation. If set, the main ADC operates in unbuffered mode, lowering the power consumption of the AD7719. If cleared, the Main ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. MR5 0 Reserved for Future Use. MR4 CHCON Channel Configure Bit. If this bit is set, the main ADC operates with three pseudodifferential input channels and the aux ADC does not have AIN3/AIN4 as an input option. If cleared, the main ADC operates with two fully differential input channels and the aux channel operates as one fully differential input and two single-ended inputs or as three single-ended inputs. MR3 OSCPD Oscillator Power-Down Bit. If this bit is set, placing the AD7719 in standby mode will stop the crystal oscillator, reducing the power drawn by the AD7719 to a minimum. The oscillator will require 300 ms to begin oscillating when the ADC is taken out of standby mode. If this bit is cleared, the oscillator is not shut off when the ADC is put into standby mode and will not require the 300 ms start-up time when the ADC is taken out of standby. MR2–MR0 MD2–MD0 Main and Aux ADC Mode Bits. These bits select the operational mode of the enabled ADC as follows: MD2 MD1 MD0 Description 0 0 0 Power-Down Mode (Power-On Default). The current sources, power switches, and PLL are shut off in Power-Down mode. 0 0 1 Idle Mode. In Idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. 0 1 0 Single Conversion Mode. In Single Conversion mode, a single conversion is performed on the enabled channels. On completion of the conversion, the ADC data registers are updated, the relevant flags in the STATUS register are written, and idle mode is entered with the MD2–MD0 being written accordingly to 001. 0 1 1 Continuous Conversion. In continuous conversion mode, the ADC data registers are regularly updated at the selected update rate (see Filter register). 1 0 0 Internal Zero-Scale Calibration. Internal short automatically connected to the enabled channel(s). Returns to Idle mode (001) when complete. 1 0 1 Internal Full-Scale Calibration. External VREF is connected automatically to the ADC input for this calibration. Returns to idle mode when complete. 1 1 0 System Zero-Scale Calibration. User should connect system zero-scale input to the channel input pins as selected by the CH1/CH0 and ACH1/ACH0 bits in the control registers. 1 1 1 System Full-Scale Calibration. User should connect system full-scale input to the channel input pins as selected by the CH1/CH0 and ACH1/ACH0 bits in the control registers. MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 0 (0) BUF (0) 0 (0) CHCON (0) OSCPD (0) MD2 (0) MD1 (0) MD0 (0) REV. A AD7719 –22– Operating Characteristics when Addressing the Mode and Control Registers 1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3.) 2. If AD0CON is written when AD0EN = 1, or if AD0EN is changed from 0 to 1, both ADCs are also immediately reset. In other words, the main ADC is given priority over the aux ADC and any change requested on main is immediately responded to. 3. On the other hand, if AD1CON is written to, only the aux ADC is reset. For example, if the main ADC is continuously converting when the aux ADC change or enable occurs, the main ADC continues undisturbed. Rather than allow the aux ADC to operate with a phase difference from the main ADC, the aux ADC will fall into step with the outputs of the main ADC. The result is that the first conversion time for the aux channel will be delayed up to three outputs while the aux ADC update rate is synchronized to the main ADC. 4. Once the MODE has been written with a calibration mode, the RDY0/1 bits (STATUS) are immediately reset and the calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in STATUS are written, and the MD2–0 bits are reset to 001 to indicate the ADC is back in Idle mode. 5. Any calibration request of the aux ADC while the temperature sensor is selected will fail to complete. 6. Calibrations are performed with the maximum allowable SF value. SF register is reset to user configuration after calibration. Main ADC Control Register (AD0CON): (A3, A2, A1, A0 = 0, 0, 1, 0; Power-On Reset = 0x07) The main ADC control register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the main ADC for range, channel selection, 16-/24-bit operation, and unipolar or bipolar coding. Table XIII outlines the bit designations for the main ADC control register. AD0CON7 through AD0CON0 indicate the bit location, AD0CON denoting the bits are in the main ADC control register. AD0CON7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Table XIII. Main ADC Control Register (AD0CON) Bit Designations Bit Location Bit Name Description AD0CON7 AD0EN Main ADC Enable Bit. Set by user to enable the main ADC. When set, the main ADC operates according to the MD bits in the mode register. Cleared by the user to power down the Main ADC. AD0CON6 WL 16-/24-Bit Operating Mode. Set by user to enable 16-bit mode. The conversion results from the main ADC will be rounded to 16 bits and the main ADC data register will be 16 bits wide. Cleared by user to enable 24-bit mode. The conversion results from the main ADC will be rounded to 24 bits and the main ADC data register will be 24 bits wide. AD0CON5 CH1 Main ADC Channel Selection Bits. AD0CON4 CH0 Written by the user to select the differential input pairs used by the main ADC as follows: (Note: The CHCON bit resides in the Mode register.) CHCON CH1 CH0 Positive Input Negative Input Calibration Register Pair 0 0 0 AIN1 AIN2 0 0 0 1 AIN3 AIN4 1 0 1 0 AIN2 AIN2 0 0 1 1 AIN3 AIN2 1 1 0 0 AIN1 AIN4 0 1 0 1 AIN3 AIN4 1 1 1 0 AIN4 AIN4 0 1 1 1 AIN2 AIN4 2 AD0CON3 U/B Main ADC Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 0x00 0000 output and a full-scale differential input will result in 0xFF FFFF output when operated in 24-bit mode. Cleared by user to enable bipolar coding, Negative full-scale differential input will result in an output code of 0x00 0000, zero differential input will result in an output code of 0x80 0000, and a Positive full-scale differential input will result in an output code of 0xFF FFFF. AD0CON7 AD0CON6 AD0CON5 AD0CON4 AD0CON3 AD0CON2 AD0CON1 AD0CON0 AD0EN (0) WL (0) CH1 (0) CH0 (0) U/B (0) RN2 (1) RN1 (1) RN0 (1) REV. A AD7719 –23– Table XIII. Main ADC Control Register (AD0CON) Bit Designations (continued) Bit Location Bit Name Description AD0CON2 RN2 Main ADC Range Bits. AD0CON1 RN1 Written by the user to select the main ADC input range as follows. AD0CON0 RN0 RN2 RN1 RN0 Selected Main ADC Input Range (VREF = 2.5 V) 0 0 0 ±20 mV 0 0 1 ±40 mV 0 1 0 ±80 mV 0 1 1 ±160 mV 1 0 0 ±320 mV 1 0 1 ±640 mV 1 1 0 ±1.28 V 1 1 1 ±2.56 V Aux ADC Control Registers (AD1CON): (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 0x00) The aux ADC control register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the aux ADC for range, channel selection, and unipolar or bipolar coding. Table XIV outlines the bit designations for the aux ADC control register. AD1CON7 through AD1CON0 indicate the bit location, with AD1CON denoting that the bits are in the aux ADC control register. AD1CON7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Table XIV. Aux ADC Control Register (AD1CON) Bit Designations Bit Location Bit Name Description AD1CON7 AD1EN Aux ADC Enable Bit. Set by user to enable the Aux ADC. When set, the aux ADC operates according to the MD bits in the mode register. Cleared by the user to power down the aux ADC. AD1CON6 ACH2 Aux ADC Channel Selection Bits. AD1CON5 ACH1 Written by the user to select the active input channels used by the aux ADC as follows: AD1CON4 ACH0 CHCON ACH2 ACH1 ACH0 Positive Input Negative Input 0 0 0 0 AIN3 AGND 0 0 0 1 AIN4 AGND 0 0 1 0 AIN5 AIN6 0 0 1 1 Temp Sensor (Temp Sensor Routed to the ADC Inputs) 0 1 0 0 AGND AGND (Internal Short) 1 0 0 0 AIN5 AGND 1 0 0 1 AIN6 AGND 1 0 1 0 AIN5 AIN6 1 0 1 1 Temp Sensor (Temp Sensor Routed to the ADC Inputs) 1 1 0 0 AGND AGND (Internal Short) X 1 0 1 Not Defined X 1 1 0 Not Defined X 1 1 1 Not Defined AD1CON3 U/B Aux ADC Unipolar/Bipolar Selection Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 0x0000 output. Cleared by user to enable bipolar coding, zero differential input will result in 0x8000 output. AD1CON2 0 Must be zero for specified operation. AD1CON1 0 Must be zero for specified operation. AD1CON0 ARN Auxiliary Channel Input Range Bit. When set by the user, the input range is ±REFIN2. When cleared by the user, the input range is ±REFIN2/2. NOTES 1. When the temperature sensor is selected, the AD7719 automatically selects its internal reference. The temperature sensor is not factory calibrated. Temp sensor is suitable for relative temperature measurements. The temperature sensor yields conversion results where a conversion result of 0x8000 equates to typically 0°C. 2. A 1°C change in temperature will normally result in a 256 LSB change in the AD1 data register (ADC conversion result). AD1CON7 AD1CON6 AD1CON5 AD1CON4 AD1CON3 AD1CON2 AD1CON1 AD1CON0 AD1EN (0) ACH2 (0) ACH1 (0) ACH0 (0) U/B (0) 0 (0) 0 (0) ARN (1) REV. A AD7719 –24– FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 SF7 (0) SF6 (1) SF5 (0) SF4 (0) SF3 (0) SF2 (1) SF1 (0) SF0 (1) IOCON15 IOCON14 IOCON13 IOCON12 IOCON11 IOCON10 IOCON9 IOCON8 PSW2 (0) PSW1 (0) 0 (0) BO (0) I2PIN (0) I1PIN (1) I2EN (0) I1EN (0) IOCON7 IOCON6 IOCON5 IOCON4 IOCON3 IOCON2 IOCON1 IOCON0 P4DIR (0) P3DIR (0) P2EN (0) P1EN (0) P4DAT (0) P3DAT (0) P2DAT (0) P1DAT (0) Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On Reset = 0x45) The Filter register is an 8-bit register from which data can be read or to which data can be written. This register determines the amount of averaging performed by the sinc filter. Table XV outlines the bit designations for the Filter register. FR7 through FR0 indicate the bit location, with FR denoting that the bits are in the Filter register. FR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. The number in this register is used to set the decimation factor and thus the output update rate for the main and aux ADCs. The filter register cannot be written to by the user while either ADC is active. The update rate is used for both main and aux ADCs and is calculated as follows: f SF ADC = × fMOD × × 1 3 1 8 where: fADC = ADC output update rate fMOD = Modulator clock frequency = 32.768 kHz (main and aux ADC) SF = Decimal value written to SF register The allowable range for SF is 13dec to 255dec. Examples of SF values and corresponding conversion rate (fADC) and time (tADC) are shown in Table XV. It should also be noted that both ADC input channels are chopped to minimize offset errors. This means that the time for a single conversion or the time to the first conversion result is 2 × tADC. Table XV. Update Rate vs. SF WORD SF (dec) SF (Hex) fADC (Hz) tADC (ms) 13 0D 105.3 9.52 69 45 19.79 50.34 255 FF 5.35 186.77 I/O and Current Source Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On Reset = 0x0000) The IOCON register is a 16-bit register from which data can be read or to which data can be written. This register is used to control and configure the various excitation and burnout current source options available on-chip along with controlling the I/O port. Table XVI outlines the bit designations for this register. IOCON15 through IOCON0 indicate the bit location, with IOCON denoting that the bits are in the I/O and Current Source control register. IOCON15 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. A write to the IOCON register has immediate effect and does not reset the ADCs. Thus if a current source is switched while the ADC is converting, the user will have to wait for the full settling time of the filter before getting a fully settled output. Since the ADC is chopped, this equates to three outputs. REV. A AD7719 –25– Table XVI. IOCON (I/O and Current Source Control Register) Bit Designations Bit Bit Location Name Description IOCON15 PSW2 Power Switch 2 Control Bit. Set by user to enable power switch P2 to PWRGND. Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches are open. IOCON14 PSW1 Power Switch 1 Control Bit. Set by user to enable power switch P1 to PWRGND. Cleared by user to enable use as a standard I/O pin. When ADC is in standby mode, the power switches are open. IOCON13 0 This bit must be zero for correct operation. IOCON12 BO Burnout Current Enable Bit. Set by user to enable the 100 nA current sources in the main ADC signal path. A 100 nA current source is applied to the positive input leg while a 100 nA sink is applied to the negative input. Cleared by user to disable both transducer burnout current sources. IOCON11 I2PIN IEXE2, 200 μA Current Source Direction Bit. Set by user to enable IEXC2 current source to IOUT1. Cleared by user to enable IEXC2 current source to IOUT2. IOCON10 I1PIN IEXE1, 200 μA Current Source Direction Bit. Set by user to enable IEXC1 current source to IOUT2. Cleared by user to enable IEXC1 current source to IOUT1. IOCON9 I2EN IEXC2 Current Source Enable Bit. Set by user to turn on the IEXC2 excitation current source. Cleared by user to turn off the IEXC2 excitation current source. IOCON8 I1EN IEXC1 Current Source Enable Bit. Set by user to turn on the IEXC1 excitation current source. Cleared by user to turn off the IEXC1 excitation current source. IOCON7 P4DIR P4, I/O Direction Control Bit. Set by user to enable P4 as an output. Cleared by user to enable P4 as an input. There are weak active pull-ups internally when enabled as an input. IOCON6 P3DIR P3, I/O Direction Control Bit. Set by user to enable P3 as an output. Cleared by user to enable P3 as an input. There are weak active pull-ups internally when enabled as an input. IOCON5 P2EN P2 Digital Output Enable Bit. Set by user to enable P2 as a regular digital output pin. Cleared by user to three-state P2 output. PSW2 takes precedence over P2EN. IOCON4 P1EN P1 Digital Output Enable Bit. Set by user to enable P1 as a regular digital output pin. Cleared by user to three-state P1 output. PSW1 takes precedence over P1EN. IOCON3 P4DAT Digital I/O Port Data Bits. IOCON2 P3DAT The readback values of these bits indicate the status of their respective pin when the I/O port is active as IOCON1 P2DAT an input. IOCON0 P1DAT The values written to these data bits appear at the output port when the I/O bits are enabled as outputs. P2 and P1 are outputs only, so reading P2DAT and P1DAT will return what was last written to these bits. REV. A AD7719 –26– Main ADC Data Result Registers (DATA0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On Reset = 0x00 0000) The conversion results for the main ADC channel are stored in the main ADC data register (DATA0). This register is either 16 or 24 bits wide, depending on the status of the WL bit in the main ADC control register (AD0CON). This is a read-only register. On completion of a read from this register, the RDY0 bit in the status register is cleared. Aux ADC Data Result Registers (DATA1): (A3, A2, A1, A0 = 0, 1, 1, 0; Power-On Reset = 0x0000) The conversion results for the aux ADC channel are stored in the aux ADC data register (DATA1). This register is 16 bits wide and is a read-only register. On completion of a read from this register, the RDY1 bit in the status register is cleared. Main ADC Offset Calibration Coefficient Registers (OF0): (A3, A2, A1, A0 = 1, 0, 0, 0; Power-On Reset = 0x80 0000) The offset calibration registers hold the 24-bit data offset calibration coefficient for the main ADC. There are three registers associated with the main ADC channel. In fully differential operating mode, there are two input channels and a register is dedicated to each input. When operating in pseudodifferential mode, the main ADC can be configured for three input channels and there is a dedicated register for each pseudodifferential input. These registers have a power-on reset value of 0x80 0000. The channel bits, in association with the communication register address for the OF0 register, allow access to these registers. These registers are read/write registers. The calibration registers can only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001 or both AD0EN and AD1EN bits in the control registers are cleared). Reading of the calibration registers does not clear the RDY0 bit. Aux ADC Offset Calibration Coefficient Registers (OF1): (A3, A2, A1, A0 = 1, 0, 0, 1; Power-On Reset = 0x8000) The offset calibration register OF1 holds the 16-bit data offset calibration coefficient for the aux ADC. This register has a poweron- reset value of 0x8000. The channel bits, in association with the communication register address for the OF1 register, allow access to these registers. These registers are read/write registers. The calibration registers can only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001 or both AD0EN and AD1EN bits in the control registers are cleared). Reading of the calibration registers does not clear the RDY1 bit. Main ADC Gain Calibration Coefficient Registers (GNO): (A3, A2, A1, A0 = 1, 0, 1, 0; Power-On Reset = 0x5X XXX5) The gain calibration registers hold the 24-bit data gain calibration coefficient for the main ADC. These registers are configured at power-on with factory calculated internal full-scale calibration coefficients. Every device will have different coefficients. However, these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the Mode register. There are three gain calibration registers associated with the main ADC channel. In fully differential operating mode, there are two input channels and a register is dedicated to each input. When operating in pseudodifferential mode, the main ADC can be configured for three input channels and there is a dedicated register for each pseudodifferential input. These registers are read/write registers. The calibration registers can only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001 or both AD0EN and AD1EN bits in the control registers are cleared). Reading of the calibration registers does not clear the RDY1 bit. Aux ADC Gain Calibration Coefficient Registers (GN1): (A3, A2, A1, A0 = 1, 0, 1, 1; Power-On Reset = 0x59XX) The gain calibration register GN1 holds the 16-bit data gain calibration coefficient for the aux ADC. This register is configured at power-on with factory calculated internal zero-scale calibration coefficients. Every device will have different coefficients. However, these coefficients will be automatically overwritten if an internal or system zero-scale calibration is initiated by the user via the MD2–0 bits in the Mode register. These registers are read/write registers. The calibration registers can only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001 or both AD0EN and AD1EN bits in the control registers are cleared). Reading of the calibration registers does not clear the RDY1 bit. ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On Reset = 0x0X) This register is a read-only 8-bit register. The contents are used to determine the die revision of the AD7719. Table XVII indicates the bit locations. User Nonprogrammable Test Registers The AD7719 contains two test registers. The bits in this test register control the test modes of the AD7719, which are used for the testing of the device. The user is advised not to change the contents of these registers. Table XVII. ID Register Bit Designations ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0 0 0 0 X X X X REV. A AD7719 –27– CONFIGURING THE AD7719 All user-accessible registers on the AD7719 are accessed via the serial interface. Communication with any of these registers is initiated by first writing to the Communications register. Figure 11 outlines a flow diagram of the sequence used to configure all registers after a power-up or reset on the AD7719. The flowchart shows two methods of determining when it is valid to read the data register or determine when a calibration cycle is complete. The first method is hardware polling of the RDY pin and the second method involves software interrogation of bits in the status and mode registers. The flowchart details all the necessary programming steps required to initialize the ADC and read data from the main and aux channel following a power-on or reset. The steps can be broken down as follows: 1. Configure and initialize the microcontroller or microprocessor serial port. 2. Initialize the AD7719 by configuring the following registers: a) IOCON to configure the current sources and digital I/O port. b) FILTER to configure the update rate for both channels. c) AD1CON to enable the aux channel, select the analog input, select unipolar or bipolar operation and input range. d) AD0CON to enable the main ADC channel and select 16-/24-bit mode, analog input range, and either unipolar or bipolar operation. e) MODE to configure the operating mode. Operating mode consists of calibration or conversion. All of these operations consist of a write to the communications register to specify the next operation as a write to a specified register. Data is then written to this register. When each sequence is complete, the ADC defaults to waiting for another write to the Communications register to specify the next operation. 3. When the operating mode is selected, the user needs to determine when it is valid to read the data in conversion mode or when the calibration is complete in calibration mode. This is accomplished either by polling the RDY pin (hardware polling) or by interrogating the bits in either the Status or Mode registers (software polling). Both are shown in Figure 11. It is assumed that both the main and aux ADCs are being used and calibration is required. If the AD7719 is operated at the factory-calibrated conditions, a field calibration will not be required and these steps can be bypassed. MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7719’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. The flowchart of Figure 11 outlines the sequence that should be followed when interfacing a microcontroller or microprocessor to the AD7719. Figures 12, 13, and 14 show some typical interface circuits. The serial interface on the AD7719 is capable of operating from just three wires and is compatible with SPI interface protocols. The 3-wire operation makes the part ideal for isolated systems where minimizing the number of interface lines minimizes the number of opto-isolators required in the system. The serial clock input is a Schmitt-triggered input to accommodate slow edges from optocouplers. The rise and fall times of other digital inputs to the AD7719 should be no longer than 1 μs. Most of the registers on the AD7719 are 8-bit registers, which facilitates easy interfacing to the 8-bit serial ports of microcontrollers. The main channel data register (AD0) on the AD7719 can be either 16 or 24 bits, the aux ADC data register (AD1) is 16 bits wide and the offset and gain registers are 24-bit registers, but data transfers to these registers can consist of multiple 8-bit transfers to the serial port of the microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these processors, such as the ADSP-2105, have the facility to program the amount of cycles in a serial transfer. This allows the user to tailor the number of bits in any transfer to match the register length of the required register in the AD7719. Even though some of the registers on the AD7719 are only eight bits in length, communicating with two of these registers in successive write operations can be handled as a single 16-bit data transfer, if required. For example, if the Filter register is to be updated, the processor must first write to the Communications register (saying that the next operation is a write to the Filter register) and then write eight bits to the Setup register. If required, this can all be done in a single 16-bit transfer because once the eight serial clocks of the write operation to the Communications register have been completed, the part immediately sets itself up for a write operation to the Setup register. REV. A AD7719 –28– START POWER-ON/RESET FOR AD7719 CONFIGURE AND INITIALIZE C/P SERIAL PORT WRITE TO THE COMMUNICATIONS REGISTER SELECTING NEXT OPERATION TO BE A WRITE TO THE IOCON REGISTER WRITE TO THE IOCON REGISTER TO CONFIGURE THE CURRENT SOURCES, DIGITAL I/O PORT, AND POWER SWITCHES WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE FILTER REGISTER WRITE TO FILTER REGISTER CONFIRMING THE REQUIRED UPDATE RATE WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE AUX CHANNEL ADC CONTROL REGISTER (AD1CON) WRITE TO AD1CON REGISTER ENABLING THE AUX ADC, SELECT THE INPUT CHANNEL BIPOLAR/ UNIPOLAR OPERATION AND INPUT RANGE WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MAIN CHANNEL ADC CONTROL REGISTER (AD0CON) WRITE TO AD1CON REGISTER ENABLING THE MAIN ADC, SELECT THE INPUT CHANNEL, WORD LENGTH, BIPOLAR/UNIPOLAR OPERATION, AND INPUT RANGE WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO MODE REGISTER SELECTING FULL-SCALE CALIBRATION HARDWARE POLLING SOFTWARE POLLING HARDWARE POLLING POLL RDY PIN RDY LOW? NO YES WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO MODE REGISTER SELECTING ZERO-SCALE CALIBRATION POLL RDY PIN RDY LOW? NO YES WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO MODE REGISTER SELECTING CONTINUOUS CONVERSION MODE WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE MAIN ADC DATA REGISTER (AD0) POLL RDY PIN RDY LOW? NO YES READ FROM DATA REGISTER (AD0) POLL RDY PIN RDY LOW? NO YES WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE AUX ADC DATA REGISTER (AD1) READ FROM DATA REGISTER (AD0) SOFTWARE POLLING WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE MODE REGISTER READ FROM MODE REGISTER MD BITS = 001? NO YES WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO MODE REGISTER SELECTING FULL-SCALE CALIBRATION WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE MODE REGISTER READ FROM MODE REGISTER MD BITS = 001? NO YES WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO MODE REGISTER SELECTING CONTINUOUS CONVERSION MODE WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO MODE REGISTER SELECTING CONTINUOUS CONVERSION MODE WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ OF STATUS REGISTER READ STATUS REGISTER RDY0 = 1? NO YES WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ OF THE MAIN ADC DATA REGISTER (AD0) READ AD0 WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ OF STATUS REGISTER READ STATUS REGISTER RDY1 = 1? NO YES WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ OF THE AUX ADC DATA REGISTER (AD1) READ AD1 Figure 11. Flowchart for Initializing, Calibrating, and Reading Data from the AD7719 Main and Aux Channels REV. A AD7719 –29– AD7719-to-68HC11 Interface Figure 12 shows an interface between the AD7719 and the 68HC11 microcontroller. The diagram shows the minimum (3-wire) interface with CS on the AD7719 hardwired low. In this scheme, the RDY bits of the Status register are monitored to determine when the Data register is updated. RDY0 indicates the status of the main ADC channel while RDY1 indicates the status of the aux channel. An alternative scheme, which increases the number of interface lines to four, is to monitor the RDY output line from the AD7719. The monitoring of the RDY line can be done in two ways. First, RDY can be connected to one of the 68HC11’s port bits (such as PC0), which is configured as an input. This port bit is then polled to determine the status of RDY. The second scheme is to use an interrupt driven system, in which case the RDY output is connected to the IRQ input of the 68HC11. For interfaces that require control of the CS input on the AD7719, one of the port bits of the 68HC11 (such as PC1) that is configured as an output, can be used to drive the CS input. The 68HC11 is configured in the master mode with its CPOL bit set to a logic 1 and its CPHA bit set to a logic 1. When the 68HC11 is configured like this, its SCLK line idles high between data transfers. The AD7719 is not capable of full duplex operation. If the AD7719 is configured for a write operation, no data appears on the DOUT lines even when the SCLK input is active. Similarly, if the AD7719 is configured for a read operation, data presented to the part on the DIN line is ignored even when SCLK is active. 68HC11 AD7719 VDD SS SCK MISO MOSI RESET SCLK CS DIN DOUT VDD Figure 12. AD7719-to-68HC11 Interface AD7719-to-8xC51 Interface An interface circuit between the AD7719 and the 8xC51 microcontroller is shown in Figure 13. The diagram shows the minimum number of interface connections with CS on the AD7719 hardwired low. In the case of the 8xC51 interface, the minimum number of interconnects is just two. In this scheme, the RDY bits of the Status register are monitored to determine when the Data register is updated. The alternative scheme, which increases the number of interface lines to three, is to monitor the RDY output line from the AD7719. The monitoring of the RDY line can be done in two ways. First, RDY can be connected to one of the 8xC51’s port bits (such as P1.0) that is configured as an input. This port bit is then polled to determine the status of RDY. DVDD 8xC51 AD7719 P3.0 P3.1 RESET SCLK CS DVDD 10k DIN DOUT Figure 13. AD7719-to-8XC51 Interface The second scheme is to use an interrupt-driven system, in which case the RDY output is connected to the INT1 input of the 8xC51. For interfaces that require control of the CS input on the AD7719, one of the port bits of the 8xC51 (such as P1.1) that is configured as an output can be used to drive the CS input. The 8xC51 is configured in its Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DOUT and DIN pins of the AD7719 should be connected together with a 10 kΩ pull-up resistor. The serial clock on the 8xC51 idles high between data transfers. The 8xC51 outputs the LSB first in a write operation, while the AD7719 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the AD7719 outputs the MSB first during a read operation while the 8xC51 expects the LSB first. Therefore, the data read into the serial buffer needs to be rearranged before the correct data word from the AD7719 is available in the accumulator. REV. A AD7719 –30– AD7719-to-ADSP-2103/ADSP-2105 Interface Figure 14 shows an interface between the AD7719 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the RDY bits of the Status register are again monitored to determine when the Data register is updated. The alternative scheme is to use an interrupt-driven system, in which case the RDY output is connected to the IRQ2 input of the ADSP-2103/ ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 is set up for alternate framing mode. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The CS for the AD7719 is active when either the RFS or TFS outputs from the ADSP-2103/ ADSP-2105 are active. The serial clock rate on the ADSP-2103/ ADSP-2105 should be limited to 3 MHz to ensure correct operation with the AD7719. RESET DVDD CS AD7719 SCLK SCLK DT DR RFS TFS ADSP-2103 / ADSP-2105 DIN DOUT Figure 14. AD7719-to-ADSP-2103/ADSP-2105 Interface CIRCUIT DESCRIPTION The AD7719 is a Σ-Δ A/D converter incorporating two independent Σ-Δ A/D converters with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in weigh scale, pressure, temperature, industrial control, or process control applications. The main ADC is intended to convert the primary sensor input. The main ADC employs a Σ-Δ conversion technique to realize up to 24 bits of no-missing-codes performance. The Σ-Δ modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. A Sinc3 programmable low-pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A Chopping scheme is also employed to minimize ADC offset and offset and gain drift errors. The analog input to the main ADC can be operated in buffered or unbuffered mode and can be programmed for one of eight input ranges from ±20 mV to ±2.56 V. The input channels can be configured for either fully differential inputs or pseudodifferential input channels via the CH1 and CH0 bits in the main ADC control register (AD0CON) and the CHCON bit in the mode register. When configured for buffered mode (BUF = 0), the input channels are internally buffered, allowing the part to handle significant source impedances on the analog input, allowing R/C filtering (for noise rejection or RFI reduction) to be placed on the analog inputs if required. When operating in unbuffered mode, care has to be exercised when selecting front end source impedances so as not to introduce gain errors. On-chip burnout currents are available and can be used to check that a transducer on the selected channel is still operational before attempting to take measurements. The second or auxiliary ADC is intended to convert secondary inputs such as those from a cold junction diode or thermistor. This ADC is unbuffered and has a fixed input range of 0 V to REFIN2 (ARN bit = 1) or 0 to REFIN2/2 (ARN bit = 0). Again, this ADC can be configured for differential or pseudodifferential inputs via the ACH2, ACH1, and ACH0 bits in the auxiliary ADC control register (AD1CON). The auxiliary ADC is specified for 16-bit performance and, since its analog inputs are unbuffered, care must be exercised when placing filtering on the front end to avoid introducing gain errors into the measurement system. The basic connection diagram for the AD7719 is shown in Figure 15. This shows both the AVDD and DVDD pins of the AD7719 being driven from the analog 5 V supply. Some applications will have AVDD and DVDD driven from separate supplies. AVDD and DVDD can be operated independently of each other, allowing the device to be operated with 5 V analog supply and 3 V digital supply or vice versa. An AD780/REF195 precision 2.5 V reference provides the reference source for the part. A quartz crystal or ceramic resonator provides the 32 kHz master clock source for the part. In some cases, it will be necessary to connect capacitors on the crystal or resonator to ensure that it does not oscillate at overtones of its fundamental operating frequency. The values of capacitors will vary depending on the manufacturer’s specifications. AD780/ REF195 XTAL1 XTAL2 RECEIVE (READ) P1/SW1 P2/SW2 P3 P4 0.1F 10F ANALOG 5V SUPPLY GND VIN VOUT PWRGND AGND DGND 10F 0.1F 0.1F AVDD DVDD IOUT1 IOUT2 AIN1 AIN2 AIN3 AIN4 AIN5 REFIN2 REFIN1(+) REFIN1(–) AIN6 RESET CS DOUT DIN SCLK 5V CHIP SELECT SERIAL DATA (WRITE) SERIAL CLOCK 32kHz CRYSTAL ANALOG 5V SUPPLY AD7719 Figure 15. Basic Connection Diagram REV. A AD7719 –31– Analog Input Channels The main ADC has four associated analog input pins (labeled AIN1 to AIN4) that can be configured as two fully differential input channels or three pseudodifferential input channels. Channel selection bits CH1 and CH0 in the ADC0CON register, along with the CHCON bit of the mode register, detail the different configurations. The auxiliary ADC has four external input pins (labeled AIN3 to AIN6) as well as an internal connection to the internal on-chip temperature sensor. Channel selection bits ACH2, ACH1, and ACH0 in the ADC1CON register, along with the CHCON bit in the mode register, detail the various configurations on these input channels. Two input multiplexers (MUX1 and MUX2) switch the selected input channel to the on-chip buffer amplifier in the case of the main ADC when operated in buffered mode, and directly to the Σ-Δ modulator input in the case of the auxiliary ADC and when the main ADC is operated in unbuffered mode. When the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the ADC. Figure 16 shows the analog input channel configurations available to the user when the CHCON bit in the mode register is set to a zero. In this case, the main ADC can be configured as one or two fully differential input channels (AIN1/AIN2 and AIN3/AIN4) and the aux can be configured as two single-ended inputs with respect to AGND (AIN3/AGND and AIN4/AGND) and one fully differential input AIN5/AIN6). The aux can also be configured as three single-ended inputs with respect to AGND (AIN3/AGND, AIN4/AGND, and AIN5/AGND) by tying AIN6 externally to AGND. The temp sensor is available as an internal connection. SINGLEENDED INPUT SINGLEENDED INPUT FULLY DIFFERENTIAL FULLY DIFFERENTIAL FULLY DIFFERENTIAL AIN(+) AIN(–) AIN(+) AIN(–) AIN1 AIN2 AIN3 AIN4 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN3 AIN4 AGND MUX1 (MAIN ADC) (AUX ADC) AIN5 AIN6 MAIN CHANNEL AUX CHANNEL MUX2 Figure 16. Input Channel Configurations with CHCON = 0 Figure 17 shows the analog input channel configurations available to the user when the CHCON bit in the mode register is set to 1. In this case, the main ADC is configured as three pseudodifferential input channels (AIN1/AIN4, AIN2/AIN4, and AIN3/AIN4) and the aux can be configured as two single-ended inputs with respect to AGND (AIN5/AGND and AIN6/AGND) and one fully differential input (AIN5/AIN6). The temp sensor is available as an internal connection. SINGLEENDED INPUT FULLY DIFFERENTIAL AIN(+) AIN(–) AIN(+) AIN(–) AIN1 AIN2 AIN3 AIN4 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN3 AIN4 AGND MUX1 (MAIN ADC) (AUX ADC) AIN5 AIN6 SINGLEENDED INPUT AIN3/AIN4 AIN2/AIN4 AIN1/AIN4 MUX2 MAIN CHANNEL AUX CHANNEL PSEUDODIFFERENTIAL INPUT PSEUDODIFFERENTIAL INPUT Figure 17. Input Channel Configurations with CHCON = 1 In buffered mode (BUF = 0), the output of the main ADC multiplexer feeds into a high impedance input stage of the buffer amplifier. As a result, the main ADC inputs can handle significant source impedances and are tailored for direct connection to external resistive-type sensors like strain gages or resistance temperature detectors (RTDs). The auxiliary ADC and the main ADC when operated with BUF = 1, however, are unbuffered, resulting in higher analog input current. It should be noted that these unbuffered input paths provide a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause dc gain errors, depending on the output impedance of the source that is driving the ADC inputs. Table XVIII and XIX show the allowable external resistance/capacitance values for unbuffered mode such that no gain error at the 16- and 20-bit level, respectively, is introduced. The absolute input voltage range on the main ADC when operated in buffered mode is restricted to a range between AGND + 100 mV and AVDD – 100 mV. Care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded; otherwise there will be a degradation in linearity and noise performance. REV. A AD7719 –32– The absolute input voltage range on the auxiliary ADC and the main ADC in unbuffered mode includes the range between AGND – 30 mV to AVDD + 30 mV as a result of being unbuffered. The negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to AGND. Programmable Gain Amplifier The output from the buffer on the main ADC is applied to the input of the on-chip programmable gain amplifier (PGA). The PGA can be programmed through eight different unipolar and bipolar ranges. The PGA gain range is programmed via the range bits in the ADC0CON register. With an external 2.5 V reference applied, the unipolar ranges are 0 mV to 20 mV, 0 mV to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 mV to 640 mV, 0 V to 1.28 V and 0 V to 2.56 V while bipolar ranges are ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV, ±1.28 V, and ±2.56 V. These are the ranges that should appear at the input to the on-chip PGA. The ADC range matching specification of 2 μV (typ) across all ranges means that calibration need only be carried out on a single range and does not have to be repeated when the PGA range is changed. This is a significant advantage when compared with similar ADCs available on the market. Typical matching across ranges is shown in Figure 18. Here, the primary ADC is configured in fully differential, bipolar mode with an external 2.5 V reference, while an analog input voltage of just greater than 19 mV is forced on its analog inputs. The ADC continuously converts the dc voltage at an update rate of 5.35 Hz, i.e., SF = 0xFF. In total, 800 conversion results are gathered. The first 100 results are gathered with the primary ADC operating in the ±20 mV range. The ADC range is then switched to ±40 mV and 100 more results are gathered; this continues until the last 100 samples are gathered with the ADC configured in the ±2.5 V range. From Figure 18, the variation in the sample mean through each range, i.e., the range matching, is seen to be on the order of 2 μV. The auxiliary ADC does not incorporate an eight range PGA. The aux ADC operates at a gain of 1 or a gain of 2 as determined by the ARN bit in the AD1CON register. 0 100 200 300 400 500 600 700 800 SAMPLE COUNT ADC INPUT VOLTAGE ( mV) 19.372 19.371 19.370 19.369 19.368 19.367 19.366 19.365 19.364 ADC RANGE 20mV 40mV 80mV 160mV 320mV 640mV 1.28V 2.56V Figure 18. Main ADC Range Matching Bipolar/Unipolar Configuration The analog inputs on the AD7719 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges do not imply that the part can handle negative voltages with respect to system AGND. Unipolar and bipolar signals on the AIN(+) input on the main ADC are referenced to the voltage on the respective AIN(–) input. AIN(+) and AIN(–) refer to the signals seen by the modulator that come from the output of the multiplexer, as shown in Figures 16 and 17. For example, if AIN(–) is 2.5 V and the main ADC is configured for an analog input range of 0 mV to 20 mV, the input voltage range on the AIN(+) input is 2.5 V to 2.52 V. If AIN(–) is 2.5 V and the AD7719 is configured for an analog input range of ±1.28 V, the analog input range on the AIN(+) input is 1.22 V to 3.78 V (i.e., 2.5 V ± 1.28 V). Bipolar or unipolar options are chosen by programming the main and auxiliary U/B bit in the ADC0CON and ADC1CON registers, respectively. This programs the relevant ADC for either unipolar or bipolar operation. Programming for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. Table XVIII. Max Resistance for No 16-Bit Gain Error (Unbuffered Mode) External Capacitance Gain 0 pF 50 pF 100 pF 500 pF 1000 pF 5000 pF 1 111.3K 27.8K 16.7K 4.5K 2.58K 700 2 53.7K 13.5K 8.1K 2.2K 1.26K 360 4 25.4K 6.4K 3.9K 1.0K 600 170 8–128 10.7K 2.9K 1.7K 480 270 75 Table XIX. Max Resistance for No 20-Bit Gain Error (Unbuffered Mode) External Capacitance Gain 0 pF 50 pF 100 pF 500 pF 1000 pF 5000 pF 1 84.9K 21.1K 12.5K 3.2K 1.77K 440 2 42.0K 10.4K 6.1K 1.6K 880 220 4 20.5K 5.0K 2.9K 790K 430 110 8–128 8.8K 2.3K 1.3K 370 195 50 REV. A AD7719 –33– Data Output Coding When the ADC is configured for unipolar operation, the output coding is natural (straight) binary with a zero differential input voltage resulting in a code of 000 . . . 000, a midscale voltage resulting in a code of 100 . . . 000, and a full-scale input voltage resulting in a code of 111 . . . 111. The output code for any analog input voltage on the main ADC can be represented as follows: Code AIN GAIN N V = ( × × 2 ) (1.024 × REF ) Where AIN is the analog input voltage, GAIN is the PGA gain, i.e., 1 on the 2.56 V range and 128 on the 20 mV range, and N = 16 in 16-bit mode and N = 24 in 24-bit mode of operation. The output code for any analog input voltage on the aux ADC can be represented as follows: Code AIN GAIN N V = ( × × 2 ) REF Where AIN is the analog input voltage, GAIN is 1 or 2, determined by the ARN bit in the aux ADC control register, i.e., 1 on the VREF range and 2 on the VREF/2 range, and N = 16. When an ADC is configured for bipolar operation, the coding is offset binary with a negative full-scale voltage resulting in a code of 000 . . . 000, a zero differential voltage resulting in a code of 100 . . . 000, and a positive full-scale voltage resulting in a code of 111 . . . 111. The output code from the main ADC for any analog input voltage can be represented as follows: Code N AIN GAIN V = 2 × [( × (1 024 × REF )) + 1] –1 . Where AIN is the analog input voltage, GAIN is the PGA gain, i.e., 1 on the ±2.56 V range and 128 on the ±20 mV range, N = 16 in 16-bit mode, and N = 24 in 24-bit mode of operation. The output code from the aux ADC for any analog input voltage can be represented as follows: Code N AIN GAIN V = 2 × [( × REF ) + 1] –1 Where AIN is the analog input voltage, GAIN is 1 or 2, determined by the ARN bit in the aux ADC control register, i.e., 1 on the ±VREF range, 2 on the ±VREF/2 range, and N = 16. Burnout Currents The main ADC on the AD7719 contains two 100 nA constant current generators, one sourcing current from AVDD to AIN(+), and one sinking current from AIN(–) to AGND. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the Burnout Current Enable (BO) bit in the IOCON register. These currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel. Once the burnout currents are turned on, they will flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. If the resultant voltage measured is full-scale, the user needs to verify why this is the case. A full-scale reading could mean that the front end sensor is open circuit; it could also mean that the front end sensor is overloaded and is justified in outputting full-scale, or that the reference may be absent and the NOXREF bit is set, thus clamping the data to all 1s. When reading all 1s from the output, the user needs to check these three cases before making a judgment. If the voltage measured is 0 V, it may indicate that the transducer has short circuited. For normal operation, these burnout currents are turned off by writing a 0 to the BO bit in the IOCON register. The current sources work over the normal absolute input voltage range specifications with buffers on. Excitation Currents The AD7719 also contains two matched, software configurable 200 μA constant current sources. Both source current from AVDD that is directed to either the IOUT1 or IOUT2 pins of the device. These current sources are controlled via bits in the IOCON register. The configuration bits enable the current sources and can be configured to source 200 μA individually to both pins or a combination of both currents, i.e., 400 μA to either of the selected output pins. These current sources can be used to excite external resistive bridge or RTD sensors. Crystal Oscillator The AD7719 is intended for use with a 32.768 kHz watch crystal. A PLL internally locks onto a multiple of this frequency to provide a stable 4.194304 MHz clock for the ADC. The modulator sample rate is the same as the crystal oscillator frequency. The start-up time associated with 32 kHz crystals is typically 300 ms. The OSPD bit in the mode register can be used to prevent the oscillator from powering down when the AD7719 is placed in power-down mode. This avoids having to wait 300 ms after exiting power-down to start a conversion at the expense of raising the power-down current. Reference Input The AD7719 has a fully differential reference input capability for the main channel while the auxiliary channel accepts only a single-ended reference. On the main channel, the reference inputs REFIN1(+) and REFIN1(–) provide a differential reference input capability. The common-mode range for these differential inputs is from AGND to AVDD. The reference input is unbuffered, and therefore excessive R-C source impedances will introduce gain errors. The nominal reference voltage, VREF, (REFIN1(+) – REFIN1(–), for specified operation is 2.5 V, but the AD7719 is functional with reference voltages from 1 V to AVDD. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source will be removed as the application is ratiometric. If the AD7719 is used in a nonratiometric application, a low noise reference should be used. Recommended reference voltage sources for the AD7719 include the AD780, REF43, and REF192. It should also be noted that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source that is driving the reference inputs. Reference voltage sources like those recommended (e.g., AD780) will typically have low output impedances and are therefore tolerant to having decoupling capacitors on the REFIN1(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor, as shown in Figure 19, will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN1(+) and REFIN1(–) pins would not be recommended in this type of circuit configuration. The auxiliary channel conversion results are based on the voltage applied to REFIN2. This is a single-ended reference input specified for 2.5 V operation but functional with input voltages from 1 V to AVDD. REV. A AD7719 –34– Reference Detect The AD7719 includes on-chip circuitry to detect if the part has a valid reference on the main ADC for conversions or calibrations. If the voltage between the external REFIN1(+) and REFIN1(–) pins goes below 0.3 V or either the REFIN1(+) or REFIN1(–) inputs are open circuit, the AD7719 detects that it no longer has a valid reference. In this case, the NOXREF bit of the Status register is set to 1. If the AD7719 is performing normal conversions and the NOXREF bit becomes active, the conversion results revert to all 1s. Therefore, it is not necessary to continuously monitor the status of the NOXREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC data register is all 1s. If the AD7719 is performing either an offset or gain calibration and the NOXREF bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the ERR0 bit in the Status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR0 bit should be checked at the end of the calibration cycle. Reset Input The RESET input on the AD7719 resets all the logic, the digital filter, and the analog modulator while all on-chip registers are reset to their default state. RDY is driven high and the AD7719 ignores all communications to any of its registers while the RESET input is low. When the RESET input returns high, the AD7719 operates with its default setup conditions and it is necessary to set up all registers and carry out a system calibration if required after a RESET command. Power-Down Mode Loading 0, 0, 0 to the MD2, MD1, MD0 bits in the ADC mode register places the AD7719 in device power-down mode. Device power-down mode is the default condition for the AD7719 on power-up. Individual ADCs (main or auxiliary) can be put in power-down mode using the AD0EN in the main ADC control register (AD0CON) to power off the main ADC or the AD1EN in the auxiliary ADC control register (AD1CON) to power off the auxiliary ADC. The AD7719 retains the contents of all its on-chip registers (including the data register) while in powerdown or ADC disable mode. The device power-down mode does not affect the digital interface, and it does affect the status of the RDY pin. Putting the AD7719 into power-down or idle mode will reset the RDY line high. Placing the part in power-down mode reduces the total current (AIDD + DIDD) to 31 μA max when the part is operated at 5 V and the oscillator is allowed to run during power-down mode. With the oscillator shuts down, the total IDD is 3 μA max at 3 V and 9 μA max at 5 V. Idle Mode The AD7719 also contains an idle mode. The ADC defaults to this mode on completion of a calibration sequence and on the completion of a conversion when operating in single conversion mode. In idle mode, the power consumption of the AD7719 is not reduced below the normal mode dissipation. ADC Disable Mode This mode is entered by setting both the AD0EN and AD1EN bits in the main and max ADC control registers to 0 and setting the Mode bits (MD2, MD1, MD0) in the Mode register to non-0. In this mode, the internal PLL is enabled and the user can activate the current sources and power switches, but the power consumption of the ADC is reduced as both ADCs are disabled. In this mode, the AIDD is reduced to 0.15 mA and the DIDD is reduced to 0.35 mA max at 3 V and to 0.4 mA max with DVDD = 5 V. Calibration The AD7719 provides four calibration modes that can be programmed via the mode bits in the mode register. One of the major benefits of the AD7719 is that it is factory-calibrated as part of the final test process with the generated coefficients stored within the ADC. At power-on, the factory gain calibration coefficients are automatically loaded to the gain calibration registers on the AD7719. Each ADC (primary and auxiliary) has dedicated calibration register pairs as outlined in the AD0CON and AD1CON register descriptions. Given that the ADC is factory-calibrated and a chopping scheme is employed that gives excellent offset and drift performance, it is envisaged that in the majority of applications the user will not need to perform any field calibrations. However, the factory calibration values in the ADC calibration registers will be overwritten if any one of the four calibration options are initiated. Even though an internal offset calibration mode is described below, it should be recognized that both ADCs are chopped. This chopping scheme inherently minimizes offset and means that an internal offset calibration should never be required. Also, because factory 25°C gain calibration coefficients are automatically present at power-on, an internal full-scale calibration will only be required if the part is being operated at temperatures significantly different from 25°C or away from the calibration conditions. The AD7719 offers internal or system calibration facilities. For full calibration to occur on the selected ADC, the calibration logic must record the modulator output for two different input conditions. These are zero-scale and fullscale points derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. The result of the zero-scale calibration conversion is stored in the offset calibration registers for the appropriate ADC. The result of the full-scale calibration conversion is stored in the gain calibration registers for the appropriate ADC. With these readings, the calibration logic can calculate the offset and the gain slope for the input-to-output transfer function of the converter. During an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected to the ADC input pins internally to the device. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the external ADC pins before the calibration mode is initiated. In this way, external ADC errors are taken into account and minimized as a result of system calibration. It should also be noted that to optimize calibration accuracy, all AD7719 ADC calibrations are automatically carried out at the slowest update rate. REV. A AD7719 –35– Internally in the AD7719, the coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration coefficient is subtracted from the result prior to the multiplication by the gain coefficient. From an operational point of view, a calibration should be treated like another ADC conversion. A zero-scale calibration (if required) should always be carried out before a full-scale calibration. System software should monitor the relevant ADC RDY0/1 bit in the Status register to determine end of calibration via a polling sequence or interrupt driven routine. Grounding and Layout Since the analog inputs and reference input on the main ADC are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies to the AD7719 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The AD7719 can be operated with 5 V analog and 3 V digital supplies, or vice versa. The digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided these noise sources do not saturate the analog modulator. As a result, the AD7719 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7719 is so high, and the noise levels from the AD7719 are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7719 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Although the AD7719 has separate pins for analog and digital ground, the AGND and DGND pins are tied together within the device via the substrate. The user must not tie these pins external to separate ground planes unless the ground planes are connected together near the AD7719. In systems where the AGND and DGND are connected somewhere else in the system, i.e., the system power supply, they should not be connected again at the AD7719 as a ground loop will result. In these situations, it is recommended that the AD7719’s AGND and DGND pins be tied to the AGND plane. In any layout, it is important that the user keep in mind the flow of currents in the system, ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout. The PWRGND pin is tied internally to AGND on the AD7719. The PWRGND pad internally has a resistance of less then 50mΩ to the PWRGND pin, while the resistance back to the AGND pad is >3 Ω. This means that 19.5 mA of the maximum specified current (20 mA) will flow to PWRGND with the remaining 0.5 mA flowing to AGND. PWRGND and AGND should be tied together at the AD7719 and it is important to minimize the resistance on the ground return lines. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7719 to prevent noise coupling. The power supply lines to the AD7719 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. All analog supplies should be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to AGND. To achieve the best from these decoupling components, they have to be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 μF ceramic capacitors to DGND. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD7719, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling capacitors between the AVDD pin of the AD7719 and AGND, and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7719 and DGND. APPLICATIONS The AD7719 provides a low cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a Σ-Δ architecture, it makes the part more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. Given the architecture used in the AD7719, where the signal chain is chopped and the device is factory-calibrated at final test, field calibration can be avoided due to the extremely low offset and gain drifts exhibited by this converter. It also provides a programmable gain amplifier, a digital filter, and system calibration options. Thus, it provides far more system-level functionality than off-the-shelf integrating ADCs without the disadvantage of having to supply a high quality integrating capacitor. In addition, using the AD7719 in a system allows the system designer to achieve a much higher level of resolution because noise performance of the AD7719 is significantly better than that of integrating ADCs. The on-chip PGA allows the AD7719 to handle an analog input voltage range as low as 10 mV full-scale with VREF = 1.25 V. The differential inputs of the part allow this analog input range to have an absolute value anywhere between AGND + 100 mV and AVDD – 100 mV. It allows the user to connect the transducer directly to the input of the AD7719. The programmable gain front end on the AD7719 allows the part to handle unipolar analog input ranges from 0 mV to 20 mV to 0 V to 2.5 V and bipolar inputs of ±20 mV to ±2.5 V. Because the part operates from a single supply, these bipolar ranges are with respect to a biased-up differential input. Another key advantage of the AD7719 is that it contains two Σ-Δ converters operating in parallel; thus the user does not need to interrupt the main channel when a secondary measurement on a different variable needs to be performed. REV. A AD7719 –36– Pressure Measurement One typical application of the AD7719 is pressure measurement. Figure 19 shows the AD7719 used with a pressure transducer, the BP01 from Sensym. The pressure transducer is arranged in a bridge network and gives a differential output voltage between its OUT(+) and OUT(–) terminals. With rated full-scale pressure (in this case 300 mmHg) on the transducer, the differential output voltage is 3 mV/V of the input voltage (i.e., the voltage between its IN(+) and IN(–) terminals). Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 15 mV. The excitation voltage for the bridge can be used to directly provide the reference for the ADC as the reference input range includes the supplies. Alternatively, a suitable resistor divider can be implemented that allows the full dynamic range of the input to be utilized in these application. This implementation is fully ratiometric, so variations in the excitation voltage do not introduce errors in the system. Choosing resistor values of 20 kΩ and 12 kΩ as per Figure 19 give a 1.875 V reference voltage for the AD7719 when the excitation voltage is 5 V. AD7719 IN+ OUT+ OUT– IN– 20k 12k EXCITATION VOLTAGE = 5V AVDD DVDD AIN1 AIN2 REFIN1(+) P1 PWRGND DGND AGND REFIN2(–) Figure 19. Pressure Measurement Using AD7719 Using the part with a programmed gain of 128 results in the full-scale input span of the AD7719 being 15 mV, which corresponds with the output span from the transducer. A second key advantage to using the AD7719 in transducer based applications is that the on-chip low-side power switch can be fully utilized in low power applications. The low-side power switch is connected in series with the cold side of the bridge. In normal operation, the switch is closed and measurements can be taken from the bridge. In applications where power is of concern, the AD7719 can be put in low power mode, substantially reducing the power burned in the application. In addition to this, the power switch can be opened while in low power mode thus avoiding the unnecessary burning of power in the front end transducer. When the AD7719 is taken back out of power-down and the power switch is closed, the user should ensure that the front end circuitry is fully settled before attempting a read from the AD7719. The circuit in Figure 20 shows a method that utilizes all three pseudodifferential input channels on the AD7719 main channel to temperature-compensate a pressure transducer. 5V OUT(+) OUT(–) IN(–) IN(+) I1 I2 PRESSURE BRIDGE XTAL1 XTAL2 IOUT1 6.25k AVDD REFIN(+) REFIN(–) AIN2 AIN1 AIN3 AIN4 AGND AD7719 250 Figure 20. Temperature-Compensating a Pressure Transducer In this application, pseudodifferential input channel AIN1/AIN4 is used to measure the bridge output while pseudodifferential channels AIN2/AIN4 and AIN3/AIN4 measure the voltage across the bridge. The voltage measured across the bridge will vary proportionally with temperature, and the delta in this voltage can be used to temperature-compensate the output of the pressure bridge. Temperature Measurement The AD7719 is also useful in temperature measurement applications; Figure 21 shows an RTD temperature measurement application. In this application, the transducer is an RTD (resistive temperature device), a PT100. The arrangement is a 4-lead RTD configuration. There are voltage drops across the lead resistances RL1 and RL4, but these simply shift the common-mode voltage. There is no voltage drop across lead resistances RL2 and RL3 as the input current to the AD7719 is very low, looking into a high input impedance buffer. RCM is included to shift the analog input voltage to ensure that it lies within the common-mode range (AGND + 100 mV to AVDD – 100 mV) of the ADC. In the application shown, the on-chip 200 μA current source provides the excitation current for the PT100 and also generates the reference voltage for the AD7719 via the 12.5 kΩ resistor. Variations in the excitation current do not affect the circuit as both the input voltage and the reference voltage vary ratiometrically with the excitation current. However, the 12.5 kΩ resistor must have a low temperature coefficient to avoid errors in the reference voltage over temperature. REV. A AD7719 –37– REFIN(–) IOUT1 5V 12.5k AVDD AIN2 AIN1 AD7719 REFIN(+) CONTROLLER IOUT2 DVDD DGND AGND PWRGND DRDY SCLK DIN DOUT CS XTAL1 XTAL2 RL1 RREF RL2 RL3 RL4 RCM RTD 200A Figure 21. 4-Wire RTD Temperature Measurement Using the AD7719 Figure 22 shows a further enhancement to the circuit shown in Figure 21. Generally, dc excitation has been accepted as the normal method of exciting resistive-based sensors like RTDs (resistance temperature detectors) in temperature measurement applications. With dc excitation, the excitation current through the sensor must be large enough so that the smallest temperature/resistance change to be measured results in a voltage change that is larger than the system noise, offset, and drift of the system. The purpose of switching the excitation source is to eliminate dc-induced errors. DC errors (EMF1 and EMF2) due to parasitic thermocouples produced by differential metal connections (solder and copper track) within the circuit are also eliminated when using this switching arrangement. This excitation is a form of synchronous detection where the sensor is excited with an alternating excitation source and the ADC only measures information in the same phase as the excitation source. REFIN(–) IOUT1 IOUT2 AVDD AIN2 AIN1 AIN3 AIN4 AD7719 REFIN(+) MUX1 RREF A A BUF AND PGA 200A I1 EMF1 RESISTIVE TRANSDUCER EMF2 Figure 22. Low Resistance Measurement AD7719 The switched polarity current source is developed using the on-chip current sources and external phase control switches (A and A) driven from the controller. During the conversion process, the AD7719 takes two conversion results, one on each phase. During Phase 1, the on-chip current source is directed to IOUT1 and flows top to bottom through the sensor and switch controlled by A. In Phase 2, the current source is directed to IOUT2 and flows in the opposite direction through the sensor and through switch controlled by A. In all cases, the current flows in the same direction through the reference resistor to develop the reference voltage for the ADC. All measurements are ratiometrically derived. The results of both conversions are combined within the microcontroller to produce one output measurement representing the resistance or temperature of the transducer. For example, if the RTD output during Phase 1 is 10 mV, a 1 mV circuit-induced dc error exists due to parasitic thermocouples, and the ADC measures 11 mV. During the second phase, the excitation current is reversed and the ADC measures –10 mV from the RTD and again sees 1 mV dc error, giving an ADC output of –9 mV during this phase. These measurements are processed in the controller (11 mV – (–9 mV)/2 = 10 mV), thus removing the dc-induced errors within the system. In the circuit shown in Figure 22, the resistance measurement is made using ratiometric techniques. Resistor RREF, which develops the ADC reference, must be stable over temperature to prevent reference-induced errors in the measurement output. 3-Wire RTD Configurations To fully optimize a 3-wire RTD configuration, two identically matched current sources are required. The AD7719, which contains two well-matched current sources, is ideally suited to these applications. One possible 3-wire configuration using the AD7719 is outlined in Figure 23. REFIN(–) IOUT1 DGND AGND 5V 12.5k AVDD AIN2 AIN1 AD7719 RL3 RCM REFIN(+) CONTROLLER IOUT2 DVDD DRDY SCLK DIN DOUT CS XTAL1 XTAL2 RL2 RTD 200A 200A RL1 Figure 23. 3-Wire RTD Configuration Using the AD7719 REV. A AD7719 –38– In this 3-wire configuration, the lead resistances will result in errors if only one current source is used because the 200 μA will flow through RL1, developing a voltage error between AIN1 and AIN2. In the scheme outlined below, the second RTD current source is used to compensate for the error introduced by the 200 μA flowing through RL1. The second RTD current flows through RL2. Assuming RL1 and RL2 are equal (the leads would normally be of the same material and of equal length), and IOUT1 and IOUT2 match, the error voltage across RL2 equals the error voltage across RL1, and no error voltage is developed between AIN1 and AIN2. Twice the voltage is developed across RL3, but since this is a common-mode voltage, it will not introduce errors. RCM is included so the current flowing through the combination of RL3 and RCM develops enough voltage that the analog input voltage seen by the AD7719 is within the common-mode range of the ADC. The reference voltage for the AD7719 is also generated using one of these matched current sources. This reference voltage is developed across the 12.5 kΩ resistor as shown, and applied to the differential reference inputs of the AD7719. This scheme ensures that the analog input voltage span remains ratiometric to the reference voltage. Any errors in the analog input voltage due to the temperature drift of the RTD current source is compensated for by the variation in the reference voltage. The typical drift matching between the two RTD current sources is less than 1 ppm/°C. The voltage on either IOUT pin can go to within 0.6 V of the AVDD supply. Smart Transmitters Smart transmitters are another key design-in area for the AD7719. The dual Σ-Δ converter, single-supply operation, 3-wire interface capabilities, and small package size are all of benefit in smart transmitters. Here, the entire smart transmitter must operate from the 4 to 20 mA loop. Tolerances in the loop mean that the amount of current available to power the transmitter is as low as 3.5 mA. Figure 24 shows a block diagram of a smart transmitter, which includes the AD7719. Not shown in Figure 24 is the isolated power source required to power the front end. The advantages of the AD7719 in these applications is the dual-channel operation, meaning that the user does not have to interrupt the main channel when measuring secondary variables, and therefore does not have the latency associated with the settling times of the digital filter. The fact that the AD7719 is factory-calibrated means that in the majority of applications, the user will not have to perform any field calibration given the excellent offset and gain drift performance of the device as a result of the signal chain chopping employed in the signal chain. MICROCONTROLLER REF OUT2 REF IN 10F 0.1F DVDD AVDD AIN1 AIN2 CS DOUT SCLK DIN DGND AGND AIN5 AIN5 COM REFIN2 REFIN(+) REFIN(–) 0.1F REF OUT1 CLOCK LATCH DATA 4.7F COM C1 C2 C3 VCC GND AD7719 AD421 BOOST VCC LV 0.01F 1k 1000pF LOOP POWER 10F 3.3V 1.25V DN25D 0.01F LOOP RTN COMP DRIVE MAIN VARIABLES SECONDARY VARIABLES AIN3 AIN4 Figure 24. Smart Transmitter Employing the AD7719 REV. A AD7719 –39– OUTLINE DIMENSIONS 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AE 0.32 (0.0126) 0.23 (0.0091) 8 0 0.75 (0.0295) 0.25 (0.0098)  45 1.27 (0.0500) 0.40 (0.0157) SEATING PLANE 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) BSC 28 15 1 14 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) COPLANARITY 0.10 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 4.50 4.40 4.30 28 15 1 14 9.80 9.70 9.60 6.40 BSC PIN 1 SEATING PLANE 0.15 0.05 0.30 0.19 0.65 BSC 1.20 MAX 0.20 0.09 0.75 0.60 0.45 8 0 COMPLIANT TO JEDEC STANDARDS MS-153AE COPLANARITY 0.10 –40– C02460–0–4/03(A) REV. A AD7719 Revision History Location Page 4/03—Data Sheet changed from REV. 0 to REV. A. Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input Preamp Ladder Attenuator Output Amp Common Mode Control Bandwidth Limiting Circuitry Aux Amp Overvoltage Clamp GND 5,8 VCC 3,4 VCM_Aux 16 Serial Peripheral Interface 12 VDD Hi Gain or Low Gain 10 Step 2 dB/Step +IN -IN 6 7 10 9 11 SDIO CS SCLK 13 VCM 15 14 1 2 -OUT Aux +OUT Aux -OUT +OUT AUXILIARY OUTPUT MAIN OUT 72µ$'&¶ LMH6518 50: 50: 50: 50: Overvoltage Clamp Overvoltage Clamp LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 LMH6518 900 MHz, Digitally Controlled, Variable Gain Amplifier Check for Samples: LMH6518 1FEATURES DESCRIPTION The LMH6518 is a digitally controlled variable gain 2• Gain Range 40 dB • Gain Step Size 2 dB amplifier whose total gain can be varied from −1.16 dB to 38.8 dB for a 40 dB range in 2 dB steps. The • Combined Gain Resolution with −3 dB bandwidth is 900 MHz at all gains. Gain Gsample/Second ADC’s 8.5 mdB accuracy at each setting is typically 0.1 dB. When • Min Gain −1.16 dB used in conjunction with a Texas Instruments • Max Gain 38.8 dB Gsample/second (Gsps) ADC with adjustable full scale (FS) range, the LMH6518 gain adjustment will • −3 dB BW 900 MHz accommodate full scale input signals from 6.8 mVPP • Rise/Fall Time <500 ps to 920 mVPP to get 700 mVPP nominal at the ADC • Recovery Time <5 ns input. The Auxiliary output (“+OUT Aux” and “−OUT Aux”) follows the Main output and is intended for use • Propagation Delay Variation 100 ps in Oscilloscope trigger function circuitry but may have • HD2 @ 100 MHz −50 dBc other uses in other applications. • HD3 @ 100 MHz −53 dBc The LMH6518 gain is programmed via a SPI-1 • Input-Referred Noise (Max Gain) 0.98 nV/√Hz compatible serial bus. A signal path combined gain • Over-Voltage Clamps for Fast Recovery resolution of 8.5 mdB can be achieved when the LMH6518’s gain and the Gsps ADC’s FS input are • Power Consumption — Auxiliary Turned Off both manipulated. Inputs and outputs are DC- 1.1W0.75W coupled. The outputs are differential with individual Common Mode (CM) voltage control (for Main and APPLICATIONS Auxiliary outputs) and have a selectable bandwidth • Oscilloscope Programmable Gain Amplifier limiting circuitry (common to both Main and Auxiliary) of 20, 100, 200, 350, 650, 750 MHz or full bandwidth. • Differential ADC Drivers • High Frequency Single-Ended Input to Differential Conversion • Precision Gain Control Applications • Medical Applications • RF/IF Applications Functional Block Diagram 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1)(2) ESD Tolerance (3) Human Body Model 2000V Machine Model 200V Charge Device Model 1000V Supply Voltage VCC (5V nominal) 5.5V VDD (3.3V nominal) 3.6V Differential Input ±1V Input Common Mode Voltage 1V to 4V VCM and VCM_Aux 2V SPI Inputs 3.6V Maximum Junction Temperature 150°C Storage Temperature Range −65°C to 150°C Soldering Information Infrared or Convection (20 sec.) 235°C Wave Soldering (10 sec.) 260°C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. (3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Operating Ratings (1) Supply Voltage VCC = 5V (±5%) VDD = 3.3V (±5%) Temperature Range −40°C to 85°C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables. Thermal Properties Temperature Range (1) −40°C to 85°C Junction-to-Ambient Thermal Resistance (θJA), WQFN (1) 40°C/W (1) The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow. Package should be soldered unto a 6.8 mm2 copper area as shown in the “recommended land pattern” shown in the package drawing. Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for abbreviations used in the datasheet. Boldface limits apply at the temperature extremes. (1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. (2) “Full Power” setting is with Auxiliary output turned on. 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for abbreviations used in the datasheet. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Min(3) Typ(4) Max(3) Units Dynamic Performance LSBW −3 dB Bandwidth All Gains 900 MHz Peaking Peaking All Gains 1 dB GF_0.1 dB ±0.1 dB Gain Flatness All Gains 150 MHz GF_1 dB ±1 dB Gain Flatness All Gains 400 MHz TRS Rise Time 460 ps TRL Fall Time 450 OS Overshoot Main Output 9 % ts_1 Settling Time Main Output, ±0.5% 10 ns ts_2 Main Output, ±0.05% 14 t_recover Recovery Time(5) All Gains <5 ns PD Propagation Delay VOUT = 0.7 VPP, All Gains 1.2 ns PD_VAR Propagation Delay Variation Gain Varied 100 ps Noise, Distortion, and RF Specifications en_1 Input Noise Spectral Density Max Gain, 10 MHz 0.98 nV/√Hz en_2 Preamp LG and 0 dB Ladder, 4.1 10 MHz eno_1 RMS Output Noise Max Gain, 100 Hz to 400 MHz 1.7 mV eno_2 Preamp LG, 0 dB Ladder, 100 Hz 940 μV to 400 MHz NF_1 Noise Figure Max Gain, RS = 50Ω each Input, 3.8 10 MHz dB NF_2 Preamp LG, 0 dB Ladder, RS = 50Ω 13.5 each Input, 10 MHz HD2/ HD3_1 2nd/ 3rd Harmonic Distortion(6) Main Output, 100 MHz, All Gains −50/ −53 HD2/ HD3_2 Auxiliary Output, 100 MHz, All Gains −48/ −50 dBc HD2/ HD3_3 Main Output, 250 MHz, All Gains −44/ −50 HD2/ HD3_4 Auxiliary Output, 250 MHz, All Gains −42/ −42 IMD3 Intermodulation Distortion (6) f = 250 MHz, Main output −65 dBc OIP3_1 Intermodulation Intercept (6) Main Output, 250 MHz 26 dBm P_1dB_main −1 dB Compression Main Output, 250 MHz, 0 dB Ladder 1.8 Main Output, 250 MHz, 20 dB Ladder 1.0 P_1dB_aux Auxiliary Output, 250 MHz, 1.65 VPP 0 dB Ladder Auxiliary Output, 250 MHz, 1.0 20 dB Ladder Gain Parameters AV_DIFF_MAX Max Gain 38.1 38.8 39.5 dB AV_DIFF_MIN Min Gain −1.91 −1.16 −0.40 dB (3) Limits are 100% production tested at 25°C unless otherwise specified. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. (4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. (5) Recovery time” is the slower of the Main and Auxiliary outputs. Output swing of 700 mVPP shifted up or down by 50% (0.35V) by introducing an offset. Measured values correspond to the time it takes to return to within ±1% of 0.7 VPP (±7 mV). (6) Distortion data taken under single ended input condition. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMH6518 LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for abbreviations used in the datasheet. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Min(3) Typ(4) Max(3) Units Gain_Step Gain Step Size All Gains including Preamp Step 1.8 2 2.2 dB Gain Step Size with ADC (See ADC FS Adjusted 8.5 mdB Applications Information) Gain_Range Gain Range 39 40 41 dB TC_AV_DIFF Gain Temp Coefficient (7) All Gains −0.8 mdB/°C Gain_ACC Absolute Gain Accuracy Compared to theoretical from 0.75 — +0.75 dB Max Gain in 2 dB steps Matching Gain_match Gain Matching Main/Auxiliary All Gains ±0.1 ±0.2 dB BW_match −3 dB Bandwidth Matching All Gains 5 % Main/Auxiliary RT_match Rise Time Matching Main/ Auxiliary All Gains 5 % PD_match Propagation Delay Matching All Gains 100 ps Main/Auxiliary Analog I/O CMRR_1 CM Rejection Ratio (see Table 1) Preamp HG, 0 dB Ladder, 1.9V < 45 86 CMVR < 3.1V dB CMRR_2 Preamp LG, 0 dB Ladder, 1.9V < 40 55 CMVR < 3.1V CMVR_1 Input Common Mode Voltage Range Preamp HG, All Ladder Steps, CMRR 1.9 — 3.1 ≥ 45 dB V CMVR_2 Preamp LG, All Ladder Steps, CMRR 1.9 — 3.1 ≥ 40 dB |ΔVO_CM|ΔI_CM| All Gains, 2V < CMVR < 3V −60 −100 dB CMRR_CM CM Rejection Ratio relative to VCM (see Preamp LG, 0 dB 101 dB Table 1) Zin_diff Differential Input Impedance All Gains 150||1.5 Z KΩ || in_CM CM Input impedance Preamp HG 420||1.7 pF Preamp LG 900||1.7 FSOUT1 Full Scale Voltage Swing Main Output, THD @ 100 MHz ≤ 770(8) 800 −40 dBc, All Gains FSOUT2 Main Output, Clamped, 0 dB Ladder 1800 1960 FSOUT3 Auxiliary Output, THD @ 100 MHz ≤ 770(8) 800 mVPP −40 dBc All Gains FSOUT4 Auxiliary Output, Clamped,0 dB 1600 1760 Ladder VOUT_MAX1 Voltage range at each output pin Main Output, All gains, VCM = 1.2V 0.5 1.8 V (clamped) OUT_MAX2 Auxiliary Output, All Gains, 0.8 2.2 VCM = 1.2V V VOUT_MAX3 Main Output, All Gains, VCM = 1.45V 2.05 VOUT_MAX4 Auxiliary output, All gains, 2.45 VCM = 1.45V ZOUT_DIFF Differential Output Impedance All Gains 92 100 108 Ω VOOS Output Offset Voltage All Gains ±15 ±40 mV VOOS_shift1 Output Offset Voltage Shift Preamp LG to Preamp HG 13.7 mV VOOS_shift2 All Gains, Excluding Preamp Step 12.7 (7) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. (8) Specified by design. 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 vO_CM vOUT 250 MHz, 'VO_CM 'VOUT DC, LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for abbreviations used in the datasheet. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Min(3) Typ(4) Max(3) Units TCVOOS Output Offset Voltage Drift(9) Preamp HG, 0 dB Ladder −24 μV/°C Preamp LG, 0 dB Ladder −7 IB Input Bias Current(10) +40 +100 +140 μA VOCM Output CM Voltage Range All Gains 0.95 1.20 1.45 V VOS_CM Output CM Offset Voltage All Gains ±15 ±30 mV TC_VOS_CM CM Offset Voltage Temp Coefficient All Gains +55 μV/°C BAL_Error_DC Output Gain Balance Error −78 dB BAL_Error_AC −45 PB Phase Balance Error (See Table 1) 250 MHz ±0.8 deg PSRR Differential Power Supply Rejection(see Preamp HG, 0 dB Ladder −60 −87 Table 1) dB Preamp LG, 0 dB Ladder −50 −70 PSRR_CM CM Power Supply Rejection(see Preamp LG, 0 dB −55 −71 dB Table 1) VCM_I VCM Input Bias Current(11) All Gains ±1 ±10 ±20 nA VCM_AUX_I VCM_AUX Input Bias Current(11) All Gains ±1 ±10 ±20 (9) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. (10) Positive current is current flowing into the device. (11) Positive current is current flowing into the device. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMH6518 LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for abbreviations used in the datasheet. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Min(3) Typ(4) Max(3) Units Digital I/O & Timing VIH Input Logic High VDD-0.6 V VIL Input Logic Low 0.5 V VOH Output Logic High VDD V VOL Output Logic Low 0 V RHi_Z Output Resistance High Impedance Mode 5 MΩ I_in Input Bias Current <1 μA FSCLK SCLK Rate 10 MHz FSCLK_DT SCLK Duty Cyle 45 50 55 % TS SDIO Setup Time 25 ns TH SDIO Hold Time 25 ns TCES CS Enable Setup Time From CS asserted to rising edge of 25 ns SCLK tCDS CS Disable Setup Time From CS de-asserted to rising edge 25 ns of SCLK TIAG Inter-Acess Gap 3 Cycles of SCLK Power Requirements IS1 Supply Current VCC 195 210 225 230 mA IS1_off VCC Aux off 150 165 170 IDD VDD 180 350 400 μA Bandwidth Limiting Filter Specifications Filter Parameter Condition Min Typ Max Units 20 MHz Pass Band Tolerance (All Gains) −3 dB Bandwidth −0, +20 % 100 MHz Pass Band Tolerance (All Gains) −3 dB Bandwidth −0, +20 % 200 MHz Pass Band Tolerance (All Gains) −3 dB Bandwidth −0, +20 % 350 MHz Pass Band Tolerance (Preamp LG, 0 dB −3 dB Bandwidth ±10 Ladder) % Pass Band Tolerance (All Gains) ±25 650 MHz Pass Band Tolerance (Preamp LG, 0 dB −3 dB Bandwidth ±10 Ladder) % Pass Band Tolerance (All Gains) ±25 750 MHz Pass Band Tolerance (Preamp LG, 0 dB −3 dB Bandwidth ±10 Ladder) % Pass Band Tolerance (All Gains) ±25 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 'VO_CM 'VOUT LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Table 1. Definition of Terms and Specifications 1. AV_CM (dB) Change in output offset voltage (ΔVOOS) with respect to the change in input common mode voltage (ΔVI_CM) 2. AV_DIFF (dB) Gain with 100Ω differential load 3. CM Common Mode 4. CMRR (dB) Common Mode rejection defined as: AV_DIFF (dB) - AV_CM (dB) 5. CMRR_CM Common Mode rejection relative to VCM defined as: ΔVOOS /ΔVCM 6. HG Preamp High Gain 7. Ladder Ladder Attenuator setting (0-20 dB) 8. LG Preamp Low Gain 9. Max Gain Gain = 38.8 dB 10. Min Gain Gain = −1.16 dB 11. +Out Positive Main Output 12. −Out Negative Main Output 13. +Out Aux Positive Auxiliary Output 14. −Out Aux Negative Auxiliary Output 15. PB Phase Balance defined as the phase difference between the complimentary outputs relative to 180° 16. PSRR Input referred VOOS shift divided by change in VCC 17. PSRR_CM Output common mode voltage change (ΔVO_CM) with respect to VCC voltage change (ΔVCC) 18. VCM Input pin voltage that sets Main output CM 19. VCM_Aux Input pin voltage that sets Auxiliary output CM 20. VI_CM Input CM voltage (average of +IN and −IN) 21. ΔVIN (V) Differential voltage across device inputs 22. VOOS DC offset voltage. Differential output voltage measured with inputs shorted together to VCC/2 23. VO_CM Output common mode voltage (DC average of V+OUT and V−OUT) 24. VOS_CM CM offset voltage: VO_CM - VCM 25. ΔVO_CM Variation in output common mode voltage (VO_CM) 26. Balance Error. Measure of the output swing balance of “+OUT” and “−OUT”, as reflected on the output common mode voltage (VO_CM), relative to the differential output swing (VOUT). Calculated as output common mode voltage change (ΔVO_CM) divided by the output differential voltage change (ΔVOUT, which is nominally around 700 mVPP) 27. ΔVOUT Change in differential output voltage (Corrected for DC offset (VOOS)) Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMH6518 -OUT AUX 16 15 14 13 10 11 12 8 7 6 5 4 3 2 1 CS SDIO SCLK VDD VCM -OUT +OUT VCM_AUX +OUT AUX VCC VCC GND +IN -IN GND 9 LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com PIN OUT Pin Out Function P1 = +OUT Aux Auxiliary positive output P2 = −OUT Aux Auxiliary negative output P3 = VCC (5V) Analog power supply P4 = VCC (5V) Analog power supply P5 = GND Ground, electrically connected to the WQFN heat sink P6 = +IN Positive Input P7 = −IN Negative Input P8 = GND Ground, electrically connected to the WQFN heat sink P9 = CS SPI interface, Chip Select, Active low P10 = SDIO SPI interface, Serial Data Input/Output P11 = SCLK SPI interface, Clock P12 = VDD (3.3V) Digital power supply P13 = VCM Input from ADC to control main output CM P14 = −OUT Main negative output P15 = +OUT Main positive output P16 = VCM_Aux Input to control auxiliary output CM Connection Diagram Figure 1. 16-Pin-Top View See Package Number RGH0016A 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 1 10 100 1G FREQUENCY (MHz) -25 -20 -15 -10 -5 0 5 NORMALIZED GAIN (dB) Full BW 750 MHz 650 MHz 350 MHz 200 MHz 100 MHz 20 MHz Response (HG, 0 dB) VOUT = 0.1 VPP 10 100 1G FREQUENCY (MHz) -6 -5 -4 -3 -2 -1 0 1 2 3 NORMALIZED GAIN (dB) Full BW HG, 0 dB LG, 0 dB HG, 20 dB LG, 20 dB 1 10 100 1G FREQUENCY (MHz) -25 -20 -15 -10 -5 0 5 NORMALIZED GAIN (dB) Full BW 750 MHz 650 MHz 350 MHz 200 MHz 100 MHz 20 MHz Response (HG, 0 dB) 1 10 100 1G FREQUENCY (MHz) -25 -20 -15 -10 -5 0 5 NORMALIZED GAIN (dB) Full BW 750 MHz 650 MHz 350 MHz 200 MHz 100 MHz 20 MHz Response (LG, 0 dB) VOUT = 0.1 VPP 1 10 100 1G FREQUENCY (MHz) -25 -20 -15 -10 -5 0 5 NORMALIZED GAIN (dB) Full BW 750 MHz 650 MHz 350 MHz 200 MHz 100 MHz 20 MHz Response (LG, 0 dB) 1 10 100 1G FREQUENCY (MHz) -300 -250 -200 -150 -100 -50 0 PHASE (°) Full BW 20 MHz 750 MHz 100 MHz 200 MHz 350 MHz 650 MHz Phase (LG, 0 dB) LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Typical Performance Characteristics Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). Response (LG, 0 dB) Phase (LG, 0 dB) Figure 2. Figure 3. Response (HG, 0 dB) Small Signal Response (LG, 0 dB) Figure 4. Figure 5. Response vs. Small Signal Response (HG, 0 dB) Gain Figure 6. Figure 7. (1) “Full Power” setting is with Auxiliary output turned on. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMH6518 0 2 4 6 8 10 12 14 16 18 20 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 NORMALIZED GAIN (dB) FREQUENCY (MHz) All Gains 20 MHz Filter 0 50 100 150 200 250 300 FREQUENCY (MHz) -180 -130 -80 -30 20 PHASE (°) HG, 0 dB, 10 dB, 20 dB LG, 0 dB, 10 dB, 20 dB 20 MHz Filter 10 100 1G FREQUENCY (MHz) -6 -5 -4 -3 -2 -1 0 1 2 NORMALIZED GAIN (dB) 85°C, HG 25°C, HG 85°C, LG 25°C, LG -40°C, HG -40°C, LG 10 dB Ladder 10 100 1G FREQUENCY (MHz) -6 -5 -4 -3 -2 -1 0 1 2 NORMALIZED GAIN (dB) -350 -300 -250 -200 -150 -100 -50 0 50 PHASE (°) Phase Gain Aux, HG Main, LG Aux, HG Main, HG Main, LG Aux, LG 10 dB Ladder 0 200 400 600 800 1000 -300 -250 -200 -150 -100 -50 0 PHASE (°) FREQUENCY (MHz) Full BW LG, 0 dB LG, 20 dB HG, 0 dB HG, 20 dB 10 100 1G FREQUENCY (MHz) -6 -5 -4 -3 -2 -1 0 1 2 NORMALIZED GAIN (dB) 85°C, HG 85°C, LG 25°C, HG 25°C, LG -40°C, HG -40°C, LG 10 dB Ladder LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). Phase vs. Gain Response Over Temperature Figure 8. Figure 9. Main vs. Auxiliary Response Over Temperature Auxiliary Response Figure 10. Figure 11. Response Phase vs. vs. Gain Gain Figure 12. Figure 13. 10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 0 2 4 6 8 10 12 14 16 18 20 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 LADDER ATTENUATION (dB) INPUT REFERRED (nV/ Hz) 0 20 40 60 80 100 OUTPUT REFERRED (nV/ Hz) Input Referred Output Referred f = 10 MHz Preamp HG INPUT REFERRED (nV/ Hz) OUTPUT REFERRED (nV/ Hz) 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 LADDER ATTENUATION (dB) 0 5 10 15 20 25 30 35 40 45 Input Referred Output Referred f = 10 MHz Preamp LG 1 10 100 1000 FREQUENCY (MHz) -15 -10 -5 0 5 10 15 PHASE (°) 0 3 6 9 12 15 18 GROUP DELAY (ns) Linear Phase Deviation Group Delay 1 10 100 1G FREQUENCY (MHz) -90 -80 -70 -60 -50 -40 -30 -20 -10 GAIN (dB) Phase Gain LG, 0 dB -7 -6 -5 -4 -3 -2 -1 0 1 PHASE (°) 10 100 1G -6 -5 -4 -3 -2 -1 0 1 NORMALIZED GAIN (dB) FREQUENCY (MHz) 650 MHz Filter LG, 0 dB HG, 20 dB HG, 0 dB LG, 20 dB 0 200 400 600 800 1000 -300 -250 -200 -150 -100 -50 0 PHASE (°) FREQUENCY (MHz) 650 MHz Filter LG, 0 dB LG, 20 dB HG, 0 dB HG, 20 dB LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). Response Phase vs. vs. Gain Gain Figure 14. Figure 15. Balance Error Linear Phase Deviation and Group Delay Figure 16. Figure 17. Noise Noise vs. vs. Ladder Attenuation Ladder Attenuation Figure 18. Figure 19. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LMH6518 0 4 8 12 16 20 -30 -35 -40 -45 -50 -55 -60 -65 -70 HD (dBc) LADDER ATTENUATION (dB) 500 MHz 10 MHz 100 MHz 20 MHz 250 MHz 50 MHz HG 0 4 8 12 16 20 -50 -55 -60 -65 -70 -75 -80 -85 HD (dBc) LADDER ATTENUATION (dB) LG 10 MHz 20 MHz 50 MHz 100 MHz 250 MHz 500 MHz 1 100 10k 1M FREQUENCY (kHz) 1 10 100 10 1k 100k CURRENT NOISE (pA/ Hz) LG HG 0 4 8 12 16 20 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 HD (dBc) LADDER ATTENUATION (dB) 10 MHz 20 MHz 500 MHz 100 MHz 250 MHz 50 MHz LG 0 5 10 15 20 0 2 4 8 6 10 12 14 16 18 20 22 24 26 28 LADDER ATTENUATION (dB) NOISE FIGURE (dB) f = 10 MHz RS = 50: on each input Preamp HG Preamp LG 1 100 10k 1M FREQUENCY (kHz) 0 1 10 1000 10 1k 100k 100 VOLTAGE NOISE (nV/ Hz) HG, 20 dB LG, 0 dB HG, 0 dB LG, 20 dB LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). Noise Figure Input Voltage Noise vs. vs. Gain Frequency Figure 20. Figure 21. Input Current Noise HD2 vs. vs. Frequency Ladder Attenuation Figure 22. Figure 23. HD3 HD2 vs. vs. Ladder Attenuation Ladder Attenuation Figure 24. Figure 25. 12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 LADDER ATTENUATION (dB) 0 4 8 12 16 -2 2 6 10 14 18 42 GAIN (dB) 20 22 26 30 34 38 HG -40°C to 85°C LG -40°C HG 0 4 8 12 16 20 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 GAIN ACCURACY (dB) LADDER ATTENUATION (dB) Relative to HG/0 dB @ 25°C LG -40°C 25°C 85°C 25°C 85°C -7 -6 -5 -4 -3 -2 -1 0 -65 -67 -69 -71 -73 -75 -77 -79 -81 -83 -85 HARMONIC DISTORTION (dBc) OUTPUT POWER (dBFS) HG, 10 dB 65 MHz HD2 HD3 0 4 8 12 16 20 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 HARMONIC DISTORTION (dBc) LADDER ATTENUATION (dB) LG, 65 MHz Aux HD3 HD2 Aux Main 0 4 8 12 16 20 -50 -55 -60 -65 -70 -75 -80 -85 HARMONIC DISTORTION (dBc) LADDER ATTENUATION (dB) HG, 65 MHz HD3 HD2 Main Aux Aux 0 4 8 12 16 20 -50 -55 -60 -65 -70 -75 HD (dBc) LADDER ATTENUATION (dB) 10 MHz 20 MHz 50 MHz 100 MHz 250 MHz 500 MHz HG LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). HD3 vs. Ladder Attenuation Main and Auxiliary Distortion Comparison Figure 26. Figure 27. Distortion vs. Main and Auxiliary Distortion Comparison Output Power Figure 28. Figure 29. Gain Gain Accuracy vs. vs. Ladder Attenuation Ladder Attenuation Figure 30. Figure 31. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LMH6518 1.5 5 2.5 3 3.5 -50 -40 -30 -20 -10 0 10 20 VOOS (mV) VI_CM LG, 0 dB LG, 20 dB HG, 0 dB HG, 20 dB 85°C 0 4 8 12 16 20 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VOUT (VPP) LADDER ATTENUATION (dB) LG HG Aux, HG Aux, LG f = 250 MHz RL = 100 1.5 5 2.5 3 3.5 -50 -40 -30 -20 -10 0 10 20 VOOS (mV) VI_CM LG, 0 dB LG, 20 dB HG, 0 dB HG, 20 dB -40°C 1.5 5 2.5 3 3.5 -50 -40 -30 -20 -10 0 10 20 VOOS (mV) VI_CM LG, 0 dB LG, 20 dB HG, 0 dB HG, 20 dB 25°C -40°C 0 4 8 12 16 20 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 GAIN ACCURACY (dB) LADDER ATTENUATION (dB) Relative to HG/0 dB @ 25°C LG -40°C 25°C 85°C 25°C 85°C HG 0 4 8 12 16 20 -0.094 -0.093 -0.092 -0.091 -0.09 -0.089 -0.088 GAIN (dB) LADDER ATTENUATION (dB) HG LG Aux Gain ± Main Gain LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). Auxiliary Gain Accuracy Gain Matching vs. vs. Ladder Attenuation Ladder Attenuation Figure 32. Figure 33. AV_CM AV_CM Figure 34. Figure 35. −1 dB Compression vs. AV_CM Ladder Attenuation Figure 36. Figure 37. 14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 HG -40°C LG 0 4 8 12 16 20 -20 -15 -10 -5 0 5 10 15 20 VOOS (mV) LADDER ATTENUATION (dB) 85°C 25°C -40°C LG 0 4 8 12 16 20 -20 -15 -10 -5 0 5 10 15 20 VOOS (mV) LADDER ATTENUATION (dB) 85°C 25°C HG TIME (1 ns/DIV) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 VOUT (V) HI to LO LO to HI HI to LO LO to HI Input = 0.2V/DIV LG, 20 dB Output Input TIME (1 ns/DIV) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 VOUT (V) HI to LO LO to HI HI to LO LO to HI Input = 2 mV/DIV HG, 0 dB Output Input TIME (1 ns/DIV) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 VOUT (V) HI to LO HI to LO LO to HI LO to HI Input = 20 mV/DIV LG, 0 dB Output Input TIME (1 ns/DIV) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 VOUT (V) HI to LO LO to HI HI to LO LO to HI Input = 20 mV/DIV HG, 20 dB Output Input LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). Step Response Step Response Figure 38. Figure 39. Step Response Step Response Figure 40. Figure 41. Output Offset Voltage (Typical Unit 1) Output Offset Voltage (Typical Unit 2) Figure 42. Figure 43. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LMH6518 85°C 1.5 2 2.5 3 3.5 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 INPUT BIAS CURRENT (mA) VI_CM (V) 25°C -40°C 85°C 4.5 4.7 4.9 5.1 5.3 5.5 1000 1200 1400 1600 1800 2000 2200 2400 AUXILIARY VOLTAGE (mV) VCC (V) 25°C -40°C RL = 100: VCM_Aux = 1.2V No CM Load +OUT Aux and -OUT Aux 4.5 4.7 4.9 5.1 5.3 5.5 195 200 205 210 215 220 225 ICC (mA) VCC (V) -40°C 85°C 25°C 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) 0.1 0.12 0.14 0.16 0.18 0.2 0.22 IDD (mA) 85°C 25°C -40°C 85°C -40°C LG 0 4 8 12 16 20 -20 -15 -10 -5 0 5 10 15 20 VOOS (mV) LADDER ATTENUATION (dB) 25°C HG 0.7 0.9 1.1 1.3 1.5 1.7 -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 VOS_CM (mV) VCM (V) 85°C 25°C -40°C LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). VOS_CM vs. Output Offset Voltage (Typical Unit 3) VCM Figure 44. Figure 45. Supply Current Supply Current vs. vs. Supply Voltage Supply Voltage Figure 46. Figure 47. Input Bias Current vs. Input CM Auxiliary Output Voltage (Hi-Z Mode) Figure 48. Figure 49. 16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 0 100 200 300 400 500 TIME (ns) -1.5 -1.0 -0.5 0 0.5 1.0 1.5 ERROR (%) 0 dB Ladder Attenuation 50% Overdrive Preamp HG or LG -10 -6 -2 2 6 10 600 800 1000 1200 1400 1600 1800 OUTPUT VOLTAGE (V) DELTA-VIN (mV) +OUT -OUT -40°C 85°C 25°C -40°C 25°C, 85°C Main or Auxiliary Output HG, 0 dB -100 -60 -20 20 60 100 800 900 1000 1100 1200 1300 1400 1500 1600 OUTPUT VOLTAGE (V) DELTA-VIN (mV) +OUT -OUT -40°C 25°C, 85°C 25°C, 85°C -40°C Main or Auxiliary Output HG, 20 dB -100 -60 -20 20 60 100 600 800 1000 1200 1400 1600 1800 OUTPUT VOLTAGE (V) DELTA-VIN (mV) +OUT -OUT -40°C 85°C 25°C -40°C 25°C, 85°C Main or Auxiliary Output LG, 0 dB -1 -0.6 -0.2 0.2 0.6 1 800 900 1000 1100 1200 1300 1400 1500 1600 OUTPUT VOLTAGE (V) DELTA-VIN (V) +OUT 25°C, 85°C -OUT -40°C 25°C, 85°C -40°C Main or Auxiliary Output LG, 20 dB -5 0 5 10 15 20 25 30 35 40 -10 -5 0 5 10 15 20 25 ERROR from NOMINAL FILTER BW (%) GAIN (dB) LG HG 350 MHz 650 MHz 750 MHz 750 MHz 350 MHz 650 MHz LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). Filter BW Output vs. vs. Gain Input Figure 50. Figure 51. Output Output vs. vs. Input Input Figure 52. Figure 53. Output vs. Input Overdrive Recovery Time (Return to Zero) Figure 54. Figure 55. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LMH6518 0 100 200 300 400 500 TIME (ns) -1.5 -1.0 -0.5 0 0.5 1.0 1.5 ERROR (%) 20 dB Ladder Attenuation 50% Overdrive Preamp HG or LG LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full Power setting (1). Overdrive Recovery Time (Return to Zero) Figure 56. 18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 ) to +1.41 dB 700 mV (= 20 x log 805 mV ) 700 mV (= 20 x log 595 mV = 8.5 mdB 0.56 ± 2 x 512 0.84 ± 0.56 0.56 + 2 x 512 0.84 ± 0.56 ¨ ¨ © § ¨ ¨ © § ¨ ¨ © § ¨ ¨ © § Gain Resolution = 20 log = 42.6 dB) 920 mVPP (20 x log 6.8 mVPP Ladder Attenuator 10 Steps, 2 dB/ Step 0 to -20 dB Pre-amp 10 dB or 30 dB Output Amp 8.86 dB +Out -Out +In -In 50: 50: LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION AND DYNAMIC RANGE IN OSCILLOSCOPE APPLICATIONS Here is a block diagram of the LMH6518’s Main Output signal path: Figure 57. LMH6518 Signal Path Block Diagram The Auxiliary output (not shown) uses another but similar Output Amp that taps into the Ladder Attenuator output. In this document, Preamp gain of 30 dB is referred to as “Preamp HG” (High Gain) and Preamp gain of 10 dB as “Preamp LG” (Low Gain). The LMH6518’s 2 dB/step gain resolution and 40 dB adjustment range (from −1.16 dB to 38.8 dB) allows this device to be used with the TI GSample/second ADCs which have Full Scale, FS, adjustment (through their Extended Control Mode or ECM) to provide near-continuous variability (8.5 mdB resolution) to cover a 42.6 dB (1) FS input range. The Texas Instruments GSample/second ECM control allows the ADC FS to be set using the ADC SPI bus. The ADC FS voltage range is from 560 mV to 840 mV with 9 bits of FS voltage control. The ADC ECM gain resolution can be calculated as follows: (2) The recommended ADC FS operating range is, however, narrower and it is from 595 mV to 805 mV with 700 mVPP as the mid-point. Raising the value of ADC FS voltage is tantamount to reducing the signal path gain to accommodate a larger input and vice versa, thus providing a method of gain fine-adjust. The ADC ECM gain adjustment is −1.21 dB (3) Because the ADC FS fine-adjust range of 2.62 dB (= 1.41 dB + 1.21 dB) is larger than the LMH6518’s 2 dB/step resolution, there is always at least one LMH6518 gain setting to accommodate any FS signal from 6.8 mVPP to 920 mVPP, at the LMH6518 input, with 0.62 dB (= 2.62-2) overlap. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LMH6518 (20 x log = 3.5 dB) 200 MHz 450 MHz Attenuation (dB) = 20 x log FSMAX (VPP) 800 mVPP Maximum LMH6518 FS Input = 0.7 VPP 10 (-1.16 ± 1.21) dB 20 = 920 mVPP Minimum LMH6518 FS Input = 0.7 VPP 10 (38.8 + 1.41) dB 20 = 6.8 mVPP LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Assuming a nominal 0.7VPP output, the LMH6518’s minimum FS input swing is limited by the maximum signal path gain possible and vice versa: (4) (or 8 mVPP with no ADC fine adjust) (5) (or 800 mVPP with no ADC FS adjust) To accommodate a higher FS input, an additional attenuator is needed before the LMH6518. This front-end attenuator is shown in the Figure 62 with its details shown in Figure 71. The highest minimum attenuation level is determined by the largest FS input signal (FSmax): (6) So, to accommodate 80 VPP, 40 dB minimum attenuation is needed before the LMH6518. In a typical oscilloscope application, the voltage range encountered is from 1 mV/DIV to 10 V/DIV with 8 vertical divisions visible on the screen. One of the primary concerns in a digital oscilloscope is SNR which translates to display trace width/ thickness. Typically, oscilloscope manufacturers need the noise level to be low enough so that the “no-input” visible trace width is less than 1% of FS. Experience has shown that this corresponds to a minimum SNR of 52 dB. The factors that influence SNR are: • Scope front end noise (Front-end attenuator + scope probe Hi-Z buffer which is discussed later in this document and shown in Figure 62) • LMH6518 • ADC LMH6518 related SNR factors are: • Bandwidth • Preamp used (Preamp High Gain or Low Gain) • Ladder Attenuation • Signal level SNR increases with the inverse square root of the bandwidth. So, reducing bandwidth from 450 MHz to 200 MHz, for example, improves SNR by 3.5 dB (7) The other factors listed above, preamp and ladder attenuation, depend on the signal level and also impact SNR. The combined effect of these factors is summarized in Figure 58 where SNR is plotted as a function of the LMH6518 FS input voltage (assuming scope bandwidth of 200 MHz) and not including the ADC and the front end noise: 20 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 100x (= ) 80 VPP 0.8 VPP ) 0.8 VPP 24 mVPP (= 20 x log 0.001 1 INPUT FS (V) 38 46 54 62 SNR (dBFS) 0.01 0.1 58 50 42 40 44 48 52 56 60 6 14 18 10 2 0 4 8 12 16 20 LADDER ATTENUATION (dB) Preamp HG Preamp LG 200 MHz Filter 22 -2 LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Figure 58. LMH6518 SNR & Ladder Attenuation used vs. Input As can be seen from Figure 58, SNR of at least 52 dB is maintained for FS inputs above 24 mVPP (3 mV/DIV on a scope) assuming the LMH6518’s internal 200 MHz filter is enabled. Most oscilloscope manufacturers relax the SNR specifications to 40 dB for the highest gain (lowest scope voltage setting). From Figure 58, LMH6518’s minimum SNR is 43.5 dB, thereby meeting the relaxed SNR specification for the lower range of scope front panel voltages. In Figure 58, the step-change in SNR near Input FS of 90 mVPP is the transition point from Preamp LG to Preamp HG with a subsequent 3 dB difference due to the Preamp HG/ 20 dB ladder attenuation’s lower output noise compared to Preamp LG/ 2 dB ladder attenuation’s noise. Judicious choice of front end attenuators can ensure that the 52 dB SNR specification is maintained for scope FS inputs ≥ 24 mVPP by confining the LMH6518 gain range to the lower 30.5 dB (8) from the total range of 40 dB (= 38.8 - (−1.16)) possible. Here is an example: To cover the range of 1 mV/DIV to 10 V/DIV (80 dB range), here is a configuration which affords good SNR: Table 2. Oscilloscope Example Including Front-End Attenuators Row Scope FS Input “S”, Scope Vertical Preamp Ladder Attenuation “A”, Front-end Minimum SNR (dB) (VPP) Scale (V/DIV) Range (dB) attenuation (V/V) with 200 MHz filter 1 8m-24m 1m-3m HG 0-10 1 44 2 24m-80m 3m-10m HG 10-20 1 52.0 3 80m-0.8 10m-0.1 LG 0-20 1 53.4 4 0.8-8 0.1-1 LG 0-20 10 53.4 5 8-80 1-10 LG 0-20 100 53.4 In Table 2, the highest FS input in Row 5, Column 2 (80 VPP), and the LMH6518’s highest FS input allowed (0.8 VPP) set the (9) front-end attenuator value. The 100x attenuator will allow high SNR operation to 30.5 dB down, as explained earlier, or 2.4 VPP at scope input. In that same table, Rows 1-3 with no front-end attenuation (1x) cover the scope FS input range from 8 mVPP-800 mVPP. That leaves the scope FS input range of 0.8 VPP-2.4 VPP. If the 100x attenuator were used for the entire scope FS range of 0.8 VPP-80 VPP, SNR would dip below 52 dB for a portion of that range. Another attenuation level is thus required to maintain the SNR specification requirement of 52 dB. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LMH6518 x 1.05 x 1020 G FSE = S x 8 A 10 110 mV oK = -21.6 + 20 x log = 17.57 dB K = 20 x log = 0.95 x 700 mVPP 8 x S(V/div) A -21.6 + 20 x log A S(V/div) LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com One possible attenuation partitioning is to select the additional attenuator value to cover a 20 dB range above 0.8 VPP FS (to 8 VPP) with the 100x attenuator covering the remaining 20 dB range from 8 VPP to 80 VPP. Mapping 8 VPP FS scope input to 0.8 VPP at LMH6518 input means the additional attenuator is 10x, as shown in Table 2, Row 4. The remaining scope input range of 8 VPP-80 VPP would then be covered by the 100x front-end attenuator derived earlier. The entire scope input range is now covered with SNR maintained about 52 dB for scope FS input ≥ 24 mVPP, as shown in Table 2. SETTINGS AND ADC SPI CODE (ECM) Covering the range from 1 mV/DIV to 10 V/DIV requires the following to be adjusted within the digital oscilloscope: • Front-End Attenuator • LMH6518 Preamp • LMH6518 Ladder Attenuation • ADC FS Value (ECM) The LMH6518 Product Folder contains a spreadsheet which allows one to calculate the front-end attenuator, LMH6518 Preamp gain (HG or LG) and ladder attenuation, and ADC FS setting based on the scope vertical scale (S in V/DIV). Here is the step by step procedure that explains the operations performed by the said spreadsheet based on the scope vertical scale setting (S in V/div) and front-end attenuation “A” (from Table 2). A numerical example is also worked out for more clarification: 1. Determine the required signal path gain, K: (10) assuming the full scale signal occupies 95% of the 0.7 VPP FS (for 5% overhead) which occupies 8 vertical scope divisions). Required condition: −2.37 dB ≤ K ≤ 40.3 dB Example: With S = 110 mV/DIV, Table 2 shows that A = 10 V/V: (11) 2. Determine the LMH6518 gain, G: – G is the closest LMH6518 gain, to the value of K where: – G = (38.8 – 2n)dB; n = 0, 1, 2, …, 20 – For this example, the closest G to K = 17.57 dB is 16.8 dB (with n = 11). The next LMH6518 gain, 18.8 dB (with n = 10) would be incorrect as 16.8 is closer. If 18.8 dB were mistakenly chosen, the ADC FS setting would be out of range. – Therefore: G = 16.8 dB 3. Determine Preamp (HG or LG) & Ladder Attenuation: – If G ≥ 18.8 dB → Preamp is HG and Ladder Attenuation = 38.8 - G – If G < 18.8 dB → Preamp is LG and Ladder Attenuation = 18.8 - G – For this example, with G = 16.8 → Preamp LG and Ladder Attenuation = 2 dB (= 18.8-16.8). 4. Determine the required ADC FS voltage, FSE: (12) 22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 ECM (ratio) = 0.6393 - 0.56 0.28 = 0.283 ECM (ratio) = FSE - 0.56 0.28 16.8 FSE = = 639.3 mV S x 8 10 x 1.05 x 1020 LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 The “1.05” factor is to add 5% FS overhead margin to avoid ADC overdrive. (13) Required condition: 0.56V ≤ FSE ≤ 0.84V Recommend condition: 0.595V ≤ FSE ≤ 0.805V for optimum ADC FS 5. Determine the ADC ECM code ratio: where • 0.28V= (0.84-0.56)V • 0.56V is the lower end of the ADC FS adjustability • For this example: (14) – Required condition: 0 ≤ ECM (ratio) ≤ 1 6. Determine the ECM binary code to be sent on ADC SPI bus: – Convert the ECM value represented by the ratio calculated above, to binary: – ECM (binary) = DEC2BIN{ECM(ratio)* 511, 9} – Where “DEC2BIN” is a spreadsheet function which converts the decimal ECM ratio, from step 5 above, multiplied by 511 distinct levels, into binary 9 bits. NOTE The Web based spreadsheet computes ECM without the use of “DEC2BIN” function to ease usage by all spreadsheet users who may not have this function installed. – For this example: ECM (binary) = DEC2BIN(0.283*511, 9) = 010010000. This would be the number to be sent to the ADC on the SPI bus to program the ADC to the proper FS voltage. INPUT/OUTPUT CONSIDERATIONS The LMH6518’s ideal Input/Output Conditions, considered individually, are listed below: Table 3. LMH6518's Ideal Input/Output Conditions Impedance from Common Mode Differential Input Load Impedance (Ω) Differential Output Common Mode each input to Input (V) (VPP) (V) Output (V) ground (Ω) ≤50 1.5 to 3.1 <0.8 100 (differential)/ 50 <0.77 0.95-1.45 (single ended) In addition to the individual conditions listed in Table 3, the Input/Output terminal conditions should match differentially (i.e. +IN to −IN and +OUT to −OUT), as well, for best performance. The input is differential but can be driven single-ended as long as the conditions of Table 3 are met and there is good matching between the driven and the undriven inputs from DC to the highest frequency of interest. If not, there could be a settling time impact among other possible performance degradations. The datasheet specifications are with single-ended input, unless specified. Here is the recommended bench-test schematic to drive one input and to bias the other input with good matching in mind: Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: LMH6518 LMH6518 -IN +IN R 63.4 2 W R 82.5 3 W J1 Input (from 50W source) (Ground Referenced) +5V R 76.8 5 W R 76.8 4 W R 63.4 1 W V (-3.3V) EE LMH6518 -IN +IN C1 1 nF R1 100: R3 24.9: R2 R5 49.9: 200: R4 200: J1 Input (from 50: source) (2.5V CM) +5V C2 1 nF LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Figure 59. Recommended Single-Ended Bench-Test Input Drive from 50Ω Source With the schematic of Figure 59, each LMH6518 input sees 25Ω to ground at the higher frequencies when the capacitors look like shorts. This impedance increases to 125Ω at DC for both inputs, thereby preserving the required matching at any frequency. This configuration, using properly selected R’s and C’s, allows four times less biasing power dissipation than when the undriven input is biased with an effective 25Ω from the LMH6518 input to ground. It is possible to drive the LMH6518 input from a ground referenced 50Ω source by providing level shift circuitry on the driven input. Figure 60 shows a circuit where ½ the input signal reaches the LMH6518 input while the negative supply voltage (VEE) ensures that the 50Ω source at J1 does not experience any biasing current while providing 50Ω termination to the source. The driven input (+IN) is biased to 2.5V (VCC/2): Figure 60. LMH6518 Driven by a Ground Referenced Source In the schematic of Figure 60, the equivalent impedance from each LMH6518 input to ground is around 38Ω. This configuration’s power consumption of ∼0.5W (in R1 - R5) is higher than that of Figure 59 because of additional power dissipated to perform the level shifting. Additional 50Ω attenuators can be placed between J1 and R2/R3 junction in Figure 60 in order to accommodate higher input voltages. It is also possible to shift the LMH6518 output common mode level using a level shift approach similar to that of Figure 60. The circuit in Figure 61 shows an implementation where the LMH6518’s nominal 1.2V CM output, set by a 1.2V on VCM input from the Gsample/s ADC, is shifted lower for proper interface to different ADC's which require VCM = 0V and have high input impedance: 24 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 50: 50: VOUT -5V R1 0.35 VPP, 0V DC +5V Vx R2 +5V -5V R3 R3 131.3: R1 172.7: R2 41.4: 0.7 VPP, 1.2V DC 0.43 VPP, 1.2V DC +OUT -OUT To ADC LMH6518 LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Figure 61. Output CM Shift Scheme With the scheme of Figure 61, Vx is kept at 1.2V, by proper selection of external resistor values, so that the LMH6518 outputs are not CM-loaded. As was the case with input level shifting, this output level shifting also consumes additional power (0.58W). Output Swing, Clamping, and Operation Beyond Full Scale One of the major concerns in interfacing to low voltage ADC’s (such as the Gsample/s ADC’s that the LMH6518 is intended to drive) is ensuring that the ADC input is not violated with excessive drive. For this reason, plus the very important requirement of an oscilloscope to recover quickly and gracefully from an overdrive condition, the LMH6518 is fitted with three overvoltage clamps; one at the Preamp output and one at Main and Auxiliary outputs each. The Preamp clamp is responsible for preventing the Preamp from saturation (to minimize recovery time) with large ladder attenuation when Preamp output swing is at its highest. On the other hand, the output clamps, perform this function when the Ladder attenuation is lower and hence the output amplifier is closer to saturation, and prolonged recovery, if not properly clamped. The combination of these clamps results in Figure 51, Figure 52, Figure 53, and Figure 54 where it is possible to observe where output limiting starts due to the clamp action. LMH6518 owes its fast recovery time (< 5 ns) from 50% overdrive to the said clamps. Figure 51, Figure 52, Figure 53, and Figure 54, in Typical Performance Characteristics, can be used to determine the LMH6518 linear swing beyond full scale. This information sets the overdrive limit for both oscilloscope waveform capture and for signal triggering. The Preamp clamp is set tighter than the output clamp, evidenced by lower output swing with 20 dB Ladder attenuation than with 0 dB. With high ladder attenuation (20 dB) defining the limit, the graphs show that the “+Out” and “−Out” difference of 0.4V is well inside the clamp range, thereby ensuring 0.8 VPP of unhindered output swing. This corresponds to an overdrive capability of approximately ±7% beyond full scale. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: LMH6518 Switch > J1 Oscilloscope Input 900 k: 90 k: 50: 10 k: LNA FPGA or MPU DAC +IN -IN SPI +OUT -OUT VCM +OUT Aux -OUT Aux VCM_Aux LMH6518 U1 Trigger Circuit +IN 1 -IN 1 VCMO Gsample/sec 8-Bit ADC SPI (Full Scale Voltage Control) Attenuation = 100x Channel 1 JFET Lo-Noise Amp Attenuation = 1x Attenuation = 10x Fine Gain Adjust VCC Hi-Z/50: Switch Attenuator Block VCC 200: 1 nF 200: LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Here is a block diagram for how the LMH6518 is used in an oscilloscope: Figure 62. Digital Oscilloscope Front-End From Figure 62, the signal path consists of the input impedance switch, the attenuator switch, Low Noise Amplifier (LNA, JFET amplifier) to drive the LMH6518 input (+IN), and the DAC to provide offset adjust. The LNA must have the following characteristics: • Set U1’s common mode level to VCC/2 (∼2.5V) • Very low drift (1 mV shift at LNA output could translate into 88 mV shift at LMH6518 output at max gain, or ∼13% of FS). • Low output impedance (≤ 50Ω) to drive U1, for good settling behavior • Low Noise (<0.98 nV/√Hz) to reduce the impact on the LMH6518 Noise Figure. Note that Figure 62 does not show the necessary capacitors across the resistors in the front-end attenuators (see Figure 71). These capacitors provide frequency response compensation and limit the noise contribution from the resistors so that they do not impact the signal path noise. For more information about front-end attenuator design, including frequency compensation, see REFERENCE for additional resources. • Gain of 1 V/V (or very close to 1 V/V) • Excellent frequency response flatness from DC to > 500-800 MHz to not impact the time domain performance The undriven input (−IN) is biased to VCC/2 using a voltage driver. The impedance driving the LMH6518’s −IN should be closely matched to the LNA’s output impedance for good settling time performance. APPENDIX A shows one possible implementation of the LNA buffer along with performance data. When the LMH6518’s Auxiliary output is not used, it is possible to disable this output using SPI-1 (see LOGIC FUNCTIONS for SPI register map). Electrical Characteristics shows that by doing so, device power dissipation decreases by the reduction in supply current of about 60 mA. As can be seen in Figure 63, in the absence of heavy common loading, the Auxiliary output will be at a voltage close to 1.7V (VCC = 5V). With higher supply voltages, the Auxiliary voltage will also increase and it is important to make sure any circuitry tied to this output is capable of handling the 2.3V possible under VCC worst case condition of 5.5V. 26 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 85°C 4.5 4.7 4.9 5.1 5.3 5.5 1000 1200 1400 1600 1800 2000 2200 2400 AUXILIARY VOLTAGE (mV) VCC (V) 25°C -40°C RL = 100: VCM_Aux = 1.2V No CM Load +OUT Aux and -OUT Aux LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Figure 63. Auxiliary Output Voltage as a Function of VCC LOGIC FUNCTIONS The following LMH6518 functions are controlled using the SPI-1 compatible bus: • Filters (20, 100, 200, 350, 650, 750 MHz or full bandwidth) • Power Mode (Full Power or Auxiliary Hi-Z (high impedance) • Preamp (HG or LG) • Attenuation Ladder (0-20 dB, 10 states) • LMH6518 state “Write” or “Read” back The SPI-1 bus uses 3.3V logic. “SDIO” is the serial digital input-output which can write to the LMH6518 or read back from it. “SCLK” is the bus clock with chip select function controlled by “CS” SPI-1 PIN DESCRIPTIONS Pin Name Type Function and Connection CS Input Serial Chip Select: While this signal is asserted SCLK is used to accept serial data present on SDIO and to source serial data on SDIO. When this signal is de-asserted, SDIO is ignored and SDIO is in TRI-STATE mode. SCLK Input Serial Clock: Serial data are shifted into and out of the device synchronous with this clock signal. SCLK transitions with CS de-asserted are ignored. SCLK to be stopped when not needed to minimize digital crosstalk. SDIO Input-Output Serial Data-In or Data-out: Serial data are shifted into the device (8 bit Command and 16 bit Data) on this pin while CS signal is asserted during Write operation. Serial data are shifted out of the device on this pin during a read operation while CS signal is asserted. At other times, and after one complete Access Cycle (24 bits, see Figure 64 and Figure 65), this input is ignored. This output is in TRI-STATE mode when CS is deasserted. This pin is bi-directional. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LMH6518 SCLK Valid SDIO Data Tsu Th SCLK Valid Data Valid Data Tod SDIO Inter-Access Gap XXX 0 X X X X X X X XXX C7 C6 C5 C4 C3 C2 C1 C0 1 2 3 4 Command Field Data Field 16 bits LMH6518 Bus in Tri-State MSB LSB DI5 D1 D0 8 9 24 25 Single Access Cycle SCLK LMH6518 Bus in Tri-State SDIO CS Inter-Access Gap XXX 1 X X X X X X X XXX C7 C6 C5 C4 C3 C2 C1 C0 1 2 Command Field Data Field MSB 16 bits LSB D15 D1 D0 8 9 24 25 Single Access Cycle SCLK LMH6518 Bus in Tri-State SDIO CS 3 4 LMH6518 Bus in Tri-State LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Figure 64. Serial Interface Protocol- Read Operation Figure 65. Serial Interface Protocol- Write Operation Figure 66. Read Timing Figure 67. Write Timing 28 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Table 4. Data Field Filter Pre-amp Ladder Attenuation D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) X 0 0 0 0 0=Full Power 0 See Table 6 0 0=LG See Table 7 1=Aux Hi-Z 1=HG NOTE Bits D5, D9, D11-D14 must be “0”. Otherwise, device operation is undefined and specifications are not ensured. Table 5. Default Power-On Reset Condition Filter Pre-amp Ladder Attenuation D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Table 6. Filer Selection Data Field Filter Filter BW D8 D7 D6 (MHz) 0 0 0 Full 0 0 1 20 0 1 0 100 0 1 1 200 1 0 0 350 1 0 1 650 1 1 0 750 1 1 1 Unallowed NOTE All filters are low pass single pole roll-off and operate on both Main and Auxiliary outputs. These filters are intended as signal path bandwidth and/ or noise limiting. Table 7. Ladder Attenuation Data Field Ladder Attenuation Ladder Attenuation (dB) D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 −2 0 0 1 0 −4 0 0 1 1 −6 0 1 0 0 −8 0 1 0 1 −10 0 1 1 0 −12 0 1 1 1 −14 1 0 0 0 −16 1 0 0 1 −18 1 0 1 0 −20 1 0 1 1 Unallowed 1 1 0 0 Unallowed 1 1 0 1 Unallowed 1 1 1 0 Unallowed Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: LMH6518 x 100°C = 1.45 mV {5.9 LSB) PV (9.5 mV + 50 °C ) 2.5V (= 210 LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Table 7. Ladder Attenuation Data Field (continued) Ladder Attenuation Ladder Attenuation (dB) 1 1 1 1 Unallowed NOTE An “Unallowed” SPI-1 state may result in undefined operation where device behavior is not ensured. OSCILLOSCOPE TRIGGER APPLICATIONS With the Auxiliary output of the LMH6518 offering a second output that follows the Main one (except for a slightly reduced distortion performance), the oscilloscope trigger function can be implemented by tapping this output. The “VCM_Aux” input of the LMH6518 allows the Auxiliary common mode to be set. The trigger function can be physically located at a distance from the main signal path, if need be, by taking advantage of the differential Auxiliary output and rejecting any board related common mode interference pick-up at the receive end. If Trigger circuitry is physically close to the LMH6518, the circuit diagram shown in Figure 68 allows operation using only one of two Auxiliary outputs. The unused output does need to be terminated properly using R1, R11 combination. U3 (DAC101C085) generates a 0- 2.5V trigger level, with 2.4 mV resolution (15) or 0.7% (= 2.4 mV x 100/0.35 VPP) of FS, which is compared to the LMH6518 “+Out Aux” by using an ultra-fast comparator, U2 (LMH7220). U2’s complimentary LVDS output is terminated in the required 100Ω load (R10), for best performance, where the LVDS Trigger output is available. The LMH7220’s offset voltage (±9.5 mV) and offset voltage drift (±50 μV/°C) error will be 5.9 LSB (16) of the Trigger DAC (U3). The offset voltage related portion of this error can be nulled-out, if necessary, during the oscilloscope initial calibration. To do so, the LMH6518 input is terminated properly with no input applied and U3 output is adjusted around VCM_Aux voltage (1.2V ±10 mV) while looking for U2’s output transition. U3’s output, relative to VCM_Aux at transition corresponds to U2’s offset error which can be factored into the Trigger readings and thus eliminated, leaving only the Offset voltage temperature drift component (= 2 LSB). 30 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 (= 50 mV x 100) 0.7V 2 U1 LMH6518 +5V 3,4 5,8 16 +5V VCM_Aux R3 3.83 k: 1% R4 1.20 k: 1% 1 2 +OUT Aux -OUT Aux R11 237: R12 237: R1 75: R2 75: - + U2 LMH7220 U3 DAC101 C085 U4 LP3985 10 bit DAC (I 2 C) SDA SCL +5V 2.5V VA VOUT VREF 0-2.5V R10 100: Trigger Output (LVDS) 2 3 4 5 +5V 6 1 +5V LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 Figure 68. Single-Ended Trigger from LMH6518 Auxiliary Output U2’s minimum Toggle Rate specification of 750 Mb/s with ±50 mV overdrive allow the oscilloscope to trigger on repetitive waveforms well above the 500 MHz oscilloscope bandwidth applications, when the input signal is at least 14.3% of FS swing (17) The worst case single event minimum discernable pulse width is set by the LMH7220’s propagation delay specification of 3.63 ns (20 mV overdrive). Both the Main and the Auxiliary outputs can recover gracefully and quickly from a 50% overdrive condition as tabulated in Electrical Characteristics under overdrive Recovery Time. Overdrive conditions beyond 50%, however, could result in longer recovery times due to the interaction between an internal clamp and the common mode feedback loop that sets the output common mode voltage. This may have an impact on both the displayed waveform and the oscilloscope Trigger. The result could be a loss of Trigger pulse and/or visual distortion of the displayed waveform. To avoid this scenario, the oscilloscope should detect an excessive overdrive and go into trigger-loss mode. Done this way, the oscilloscope display would show the last waveform that did not violate the overdrive condition. Preferably there would be a visual indicator on the screen that alerts the user of the situation so that he can correct the excessive condition to return to normal display. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: LMH6518 R14 R14 + R21 1 + R5 R1 || R2 Gain (DC) = ¨ ¨ © § ¨ ¨ © § #1 V/V Scope Input Input Attenuators Not Shown C6 5 pF R21 678 k: R14 322 k: - + ½ U1 LMV842 C7 20 nF C3 100 nF R22 1 M: R15 678 k: R11 322 k: LMH6518 +IN Q0 BFQ67 J8 MMBF5486 R20 500: J10 MMBF5486 R16 20: - + ½ U1 LMV842 -5V +5V LMH6518 -IN R5 +5V 500 k: R1 500 k: R3 500 k: R4 500 k: R0 500 k: R9 200: R6 200: -10V +10V R2 Adjust R2 for gain matching between DC and AC C0 1 nF C5 1 nF R17 100: R49 15: R50 15: Offset Control DAC R8 0: LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com APPENDIX A Here is the schematic drawing for a possible implementation of the LNA buffer shown in Figure 62: Figure 69. JFET LNA Implementation CIRCUIT OPERATION This circuit uses an N-Channel JFET (J10) in Source-Follower configuration, to buffer the input signal, with J8 acting as a constant current source. This buffer presents a fixed input impedance (1 MΩ||10 pF) with a gain close to 1 V/V. The signal path is AC coupled through C7 with DC (and low frequency) at LMH6518 +IN maintained through the action of U1. NPN transistor Q0 is an emitter follower which isolates the buffer from the load (LMH6518 input and board traces). The undriven input of the LMH6518, −IN, is biased to 2.5V by R6, R9 voltage divider. The Lower ½ of U1 inverts this voltage and the upper ½ of U1 compares it to the combination of the driven output level at LMH6518 +IN and the scaled version of scope input at R14, R21 junction, and adjusts J10 Gate accordingly to set the LMH6518 +IN. This control loop has a frequency response that covers DC to a few Hz, limited by the roll-off capacitor C3 and R15 combination (1st order approximation). DC and low frequency gain is given by: (18) With the values in Figure 69 → R2 ≈ 452 kΩ: 32 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 R21 R14 = R15 R11 LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 For a flat frequency response, the DC (low frequency) gain needs to be lowered to match the less-than-1 V/V AC (high frequency) path gain through the JFETs. This can be done by increasing the value of R2. By choosing the values of R15 and R11 so that (19) the frequency response at J10 Gate (and consequently the output) will remain flat when C7 starts to conduct. Offset correction is done by varying the voltage at R4, using a DAC or equivalent as shown, in order to shift the LMH6518 +IN voltage relative to −IN. The result is a circuit which shifts the ground referenced scope input to 2.5V (VCC/2) CM with adjustable offset and without any JFET or BJT related offsets. Note that the front-end attenuator (not shown) lower leg resistance should be increased for proper divider-ratio to account for the 1 MΩ shunt due to the series combination of R21 and R14. For example, a 10:1 front-end attenuator could be formed by a series 900 kΩ and a shunt 111 kΩ for a scope BNC input impedance of 1 MΩ (= 900K + (111K || 1M)). Table 8 lists other possible JFET candidates that fall in the range of speed (ft) and low noise needed: Table 8. Suitable JFET Candidates Specifications Company Part Number VP (V) Idss gm (mS) Input C noise (1) Break Calculated ft (mA) (pF) (nV/RtHz) down (V) (MHz) Interfet IF140 −2.2 10 5.5 2.3 4 −20 380 Interfet IF142 −2.2 10 5.5 2.3 4 −25 380 Interfet 2N5397/8 −2.5 13 8 5 2.5 −25 254 Interfet 2N5911/2 −2.5 13 8 5 2.5 254 Interfet J308/9/10 −2.3 21 17 5.8 −25 466 Philips BF513 -3 15 10 5 318 Fairchild MMBF5486 −4 14 7 4 2.5 −25 278 Vishay Siliconix SST441 −3.5 13 6 3.5 4 −35 272 (1) Noise data at ∼ Idss/2 The LNA noise could degrade the scope’s SNR if it is comparable to the input referred noise of the LMH6518. LNA noise is influenced by the following operating conditions: a. JFET equivalent input noise b. BJT Base current Reducing either “a” or “b” above, or both, reduces noise. One way to reduce “a” is to increase R8 (currently set to 0Ω). This will reduce the noise impact of J8 but requires a JFET which has a higher Idss rating in order to maintain the operating current of J10 so that J10’s noise contribution is minimized. Reducing the BJT Base current can be accomplished with increasing R20 at the expenses of higher rise/fall times. A higher β will also reduce the Base current (keep in mind that β and ft at the operating Collector current is what matters). Figure 70 shows the impact of the JFET buffer noise on SNR, compared to SNR in Figure 58, assuming either 3 nV/√Hz or 1.5 nV/√Hz buffer noise for comparison: Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: LMH6518 R1 900 k: C5 2-5 pF R2 111 k: C1 8 pF C2 65 pF R3 990 k: C6 2-5 pF R4 10.1 k: C3 8 pF C4 780 pF 10:1 100:1 R_LNA 1 M: C_LNA 10 pF JFET LNA 1:1 10:1 100:1 1:1 -2 2 6 10 14 18 22 26 30 34 38 0 2 4 6 8 10 12 SNR IMPACT (dB) GAIN (dB) 42 LNA Noise = 1.5 nV/ LNA Noise = 3 nV/ Hz Hz LMH6518 SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com Figure 70. LNA Buffer SNR Impact ATTENUATOR DESIGN Figure 71 shows a front-end attenuator designed to work with the JFET LNA of Figure 69. Figure 71. Front End Attenuator for Figure 69 JFET LNA R_LNA” and “C_LNA” are the input impedance components of the JFET LNA. The 10:1 and 100:1 attenuators bottom resistors (R2 and R4) are adjusted higher to compensate for the LNA’s 1 MΩ input impedance, compared to the case where a high-input-impedance LNA is used. The two switches used on the input and output of the attenuator block must be low capacitance, high isolation switches in order to reduce any speed or crosstalk impact. C1-C4 provide the proper frequency response (and step response) by creating “zeros” that flatten the response for wide-band operation. For the 10:1 attenuator, R1C1 = R2C2. The same applies to the 100:1 attenuator. The shunt capacitors C1-C4 have a very important other benefit in that they roll-off the resistor thermal noise at a low frequency (low pass response, −3 dB down at ∼20 kHz) thereby eliminating any significant noise contribution from the attenuation resistors. Otherwise, the channel noise would be dominated by the attenuator resistor thermal noise. C2 and C6 trimmer capacitors can be adjusted to match the input capacitance regardless of attenuator used. REFERENCE 1. Wideband amplifiers by Peter Staric and Erik Margan, published by Springer in 2006. (Section 5.2). 34 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6518 LMH6518 www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013 REVISION HISTORY Hooman: Corrected PSRR condition from "HG" to "LG" per CMS C1305178. Changes from Revision A (March 2013) to Revision B Page • Changed layout of National Data Sheet to TI format .......................................................................................................... 34 Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: LMH6518 PACKAGE OPTION ADDENDUM www.ti.com 24-Jul-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMH6518SQ/NOPB ACTIVE WQFN RGH 16 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L6518SQ LMH6518SQE/NOPB ACTIVE WQFN RGH 16 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L6518SQ LMH6518SQX/NOPB ACTIVE WQFN RGH 16 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L6518SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LMH6518SQ/NOPB WQFN RGH 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LMH6518SQE/NOPB WQFN RGH 16 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LMH6518SQX/NOPB WQFN RGH 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6518SQ/NOPB WQFN RGH 16 1000 213.0 191.0 55.0 LMH6518SQE/NOPB WQFN RGH 16 250 213.0 191.0 55.0 LMH6518SQX/NOPB WQFN RGH 16 4500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 Pack Materials-Page 2 MECHANICAL DATA RGH0016A www.ti.com SQA16A (Rev A) IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Packaged in TO-220AB, TO-220FPAB, D2PAK and I2PAK. DESCRIPTION TO-220AB STPS10H100CT A1 A2 K Symbol Parameter Value Unit VRRM Repetitive peak reverse voltage 100 V IF(RMS) RMS forward current 10 A IF(AV) Average forward current d = 0.5 TO-220AB D2PAK / I2PAK Tc = 165°C per diode per device 5 10 A TO-220FPAB Tc = 160°C IFSM Surge non repetitive forward current tp = 10 ms sinusoidal 180 A IRRM Repetitive peak reverse current tp = 2 μs square F = 1kHz 1 A PARM Repetitive peak avalanche power tp = 1μs Tj = 25°C 7200 W Tstg Storage temperature range - 65 to + 175 °C Tj Maximum operating junction temperature * 175 °C dV/dt Critical rate of rise of reverse voltage 10000 V/μs ABSOLUTE RATINGS (limiting values, per diode) A1 A2 K A1 A2 K D2PAK STPS10H100CG K A1 A2 K I2PAK STPS10H100CR * : dPtot dTj Rth j a < - 1 ( ) thermal runaway condition for a diode on its own heatsink A1 A2 K TO-220FPAB STPS10H100CFP STPS10H100CT/CG/CR/CFP 2/7 Symbol Parameter Value Unit Rth (j-c) Junction to case D2PAK / I2PAK TO-220AB Per diode 2.2 °C/W Total 1.3 Rth (c) Coupling 0.3 Rth (j-c) Junction to case TO-220FPAB Per diode 4.5 °C/W Total 3.5 Rth (c) Coupling 2.5 When the diodes 1 and 2 are used simultaneously : D Tj(diode 1) = P(diode1) x Rth(j-c)(Per diode) + P(diode 2) x Rth(c) THERMAL RESISTANCES Symbol Parameter Tests conditions Min. Typ. Max. Unit IR * Reverse leakage current Tj = 25°C VR = VRRM 3.5 μA Tj = 125°C 1.3 4.5 mA VF ** Forward voltage drop Tj = 25°C IF = 5 A 0.73 V Tj = 125°C 0.57 0.61 Tj = 25°C IF = 10 A 0.85 Tj = 125°C 0.66 0.71 Pulse test : * tp = 5 ms, d < 2% ** tp = 380 μs, d < 2% To evaluate the maximum conduction losses use the following equation : P = 0.51 x IF(AV) + 0.02 x IF 2 (RMS) STATIC ELECTRICAL CHARACTERISTICS (per diode) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 PF(av)(W) IF(av) (A) T d=tp/T tp d = 0.2 d = 0.5 d = 1 d = 0.05 d = 0.1 Fig. 1: Average forward power dissipation versus average forward current (per diode). 0 25 50 75 100 125 150 175 0 1 2 3 4 5 6 Tamb(°C) IF(av)(A) Rth(j-a)=Rth(j-c) Rth(j-a)=15°C/W D²PAK/I²PAK/TO-220AB TO-220FPAB Fig. 2: Average forward current versus ambient temperature (d=0.5, per diode). STPS10H100CT/CG/CR/CFP 3/7 1E-3 1E-2 1E-1 1E+0 0 20 40 60 80 100 120 IM(A) Tc=50°C Tc=75°C Tc=125°C t(s) IM t d=0.5 Fig. 5-1: Non repetitive surge peak forward current versus overload duration (maximum values, per diode) 1E-3 1E-2 1E-1 1E+0 0.0 0.2 0.4 0.6 0.8 1.0 Zth(j-c)/Rth(j-c) tp(s) T d=tp/T tp Single pulse d = 0.1 d = 0.2 d = 0.5 Fig. 6-1: Relative variation of thermal impedance junction to case versus pulse duration (per diode). 1E-3 1E-2 1E-1 1E+0 0 10 20 30 40 50 60 70 80 t(s) IM(A) Tc=50°C Tc=75°C Tc=125°C IM t d=0.5 Fig. 5-2: Non repetitive surge peak forward current versus overload duration (maximum values, per diode)(TO-220FPAB) 1E-3 1E-2 1E-1 1E+0 1E+1 0.0 0.2 0.4 0.6 0.8 1.0 tp(s) Zth(j-c)/Rth(j-c) T d=tp/T tp Single pulse d = 0.1 d = 0.2 d = 0.5 Fig. 6-2: Relative variation of thermal impedance junction to case versus pulse duration (per diode).(TO-220FPAB) 0 0.2 0.4 0.6 0.8 1 1.2 0 25 50 75 100 125 150 Tj(°C) P (t) P (25°C) ARM p ARM Fig. 4: Normalized avalanche power derating versus junction temperature. 0.001 0.01 0.01 0.1 1 0.1 10 100 1000 1 tp(μs) P (t) P (1μs) ARM p ARM Fig. 3: Normalized avalanche power derating versus pulse duration. STPS10H100CT/CG/CR/CFP 4/7 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.1 1.0 10.0 100.0 IFM(A) Tj=125°C Typical values Tj=125°C Tj=25°C Tj=150°C Typical values VFM(V) Fig. 9: Forward voltage drop versus forward current (maximum values, per diode). 0 2 4 6 8 10 12 14 16 18 20 0 10 20 30 40 50 60 70 80 Rth(j-a) (°C/W) S(Cu) (cm²) Fig. 10: Thermal resistance junction to ambient versus copper surface under tab (Epoxy printed circuit board FR4, copper thickness: 35μm) 0 10 20 30 40 50 60 70 80 90 100 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 IR(μA) Tj=125°C Tj=25°C Tj=150°C Tj=100°C VR(V) Fig. 7: Reverse leakage current versus reverse voltage applied (typical values, per diode). 1 2 5 10 20 50 100 10 100 1000 C(pF) F=1MHz Tj=25°C VR(V) Fig. 8: Junction capacitance versus reverse voltage applied (typical values, per diode). 5/7 STPS10H100CT/CG/CR/CFP PACKAGE MECHANICAL DATA D2PAK A C2 D R A2 M V2 C A1 G L L3 L2 B B2 E * * FLAT ZONE NO LESS THAN 2mm REF. DIMENSIONS Millimeters Inches Min. Max. Min. Max. A 4.40 4.60 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.70 0.93 0.027 0.037 B2 1.14 1.70 0.045 0.067 C 0.45 0.60 0.017 0.024 C2 1.23 1.36 0.048 0.054 D 8.95 9.35 0.352 0.368 E 10.00 10.40 0.393 0.409 G 4.88 5.28 0.192 0.208 L 15.00 15.85 0.590 0.624 L2 1.27 1.40 0.050 0.055 L3 1.40 1.75 0.055 0.069 M 2.40 3.20 0.094 0.126 R 0.40 typ. 0.016 typ. V2 0° 8° 0° 8° FOOT PRINT in millimeters 8.90 3.70 1.30 5.08 16.90 10.30 6/7 STPS10H100CT/CG/CR/CFP PACKAGE MECHANICAL DATA I2PAK e D L L1 L2 b1 b b2 E A c2 A1 c REF. DIMENSIONS Millimeters Inches Min. Max. Min. Max. A 4.40 4.60 0.173 0.181 A1 2.49 2.69 0.098 0.106 b 0.70 0.93 0.028 0.037 b1 1.14 1.17 0.044 0.046 b2 1.14 1.17 0.044 0.046 c 0.45 0.60 0.018 0.024 c2 1.23 1.36 0.048 0.054 D 8.95 9.35 0.352 0.368 e 2.40 2.70 0.094 0.106 E 10.0 10.4 0.394 0.409 L 13.1 13.6 0.516 0.535 L1 3.48 3.78 0.137 0.149 L2 1.27 1.40 0.050 0.055 PACKAGE MECHANICAL DATA TO-220FPAB H L3 L2 L4 L6 G G1 F F1 L5 D E L7 A B Dia F2 REF. DIMENSIONS Millimeters Inches Min. Max. Min. Max. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.70 0.018 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.70 0.045 0.067 F2 1.15 1.70 0.045 0.067 G 4.95 5.20 0.195 0.205 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 Typ. 0.63 Typ. L3 28.6 30.6 1.126 1.205 L4 9.8 10.6 0.386 0.417 L5 2.9 3.6 0.114 0.142 L6 15.9 16.4 0.626 0.646 L7 9.00 9.30 0.354 0.366 Dia. 3.00 3.20 0.118 0.126 7/7 STPS10H100CT/CG/CR/CFP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com Ordering type Marking Package Weight Base qty Delivery mode STPS10H100CT STPS10H100CT TO-220AB 2.20g 50 Tube STPS10H100CFP STPS10H100CFP TO-220FPAB 2.0 g 50 Tube STPS10H100CG STPS10H100CG D2PAK 1.48g 50 Tube STPS10H100CG-TR STPS10H100CG D2PAK 1.48g 1000 Tape and reel STPS10H100CR STPS10H100CR I2PAK 1.49g 50 Tube n Epoxy meets UL94,V0 PACKAGE MECHANICAL DATA TO-220AB A C D L7 Dia L5 L6 L9 L4 F H2 G G1 L2 F2 F1 E M REF. DIMENSIONS Millimeters Inches Min. Max. Min. Max. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.066 F2 1.14 1.70 0.044 0.066 G 4.95 5.15 0.194 0.202 G1 2.40 2.70 0.094 0.106 H2 10 10.40 0.393 0.409 L2 16.4 typ. 0.645 typ. L4 13 14 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.20 6.60 0.244 0.259 L9 3.50 3.93 0.137 0.154 M 2.6 typ. 0.102 typ. Diam. 3.75 3.85 0.147 0.151 n Cooling method: C. n Recommended torque value: 0.55 m.N n Maximum torque value 0.70 m.N  LM19 www.ti.com SNIS122E –MAY 2001–REVISED MARCH 2013 LM19 2.4V, 10μA, TO-92 Temperature Sensor Check for Samples: LM19 1FEATURES DESCRIPTION The LM19 is a precision analog output CMOS 2• Rated for Full −55°C to +130°C Range integrated-circuit temperature sensor that operates • Available in a TO-92 Package over a −55°C to +130°C temperature range. The • Predictable Curvature Error power supply operating range is +2.4 V to +5.5 V. • Suitable for Remote Applications The transfer function of LM19 is predominately linear, • UL Recognized Component yet has a slight predictable parabolic curvature. The accuracy of the LM19 when specified to a parabolic transfer function is ±2.5°C at an ambient temperature APPLICATIONS of +30°C. The temperature error increases linearly • Cellular Phones and reaches a maximum of ±3.8°C at the • Computers temperature range extremes. The temperature range is affected by the power supply voltage. At a power • Power Supply Modules supply voltage of 2.7 V to 5.5 V the temperature • Battery Management range extremes are +130°C and −55°C. Decreasing • FAX Machines the power supply voltage to 2.4 V changes the negative extreme to −30°C, while the positive • Printers remains at +130°C. • HVAC The LM19's quiescent current is less than 10 μA. • Disk Drives Therefore, self-heating is less than 0.02°C in still air. • Appliances Shutdown capability for the LM19 is intrinsic because its inherent low power consumption allows it to be KEY SPECIFICATIONS powered directly from the output of many logic gates or does not necessitate shutdown at all. • Accuracy at +30°C ±2.5 °C (max) • Accuracy at +130°C & −55°C ±3.5 to ±3.8 °C (max) • Power Supply Voltage Range +2.4V to +5.5V • Current Drain 10 μA (max) • Nonlinearity ±0.4 % (typ) • Output Impedance 160 Ω (max) • Load Regulation – 0μA < IL< +16 μA 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2001–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LM19 SNIS122E –MAY 2001–REVISED MARCH 2013 www.ti.com Typical Application Output Voltage vs Temperature VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 or where: T is temperature, and VO is the measured output voltage of the LM19. Figure 1. Full-Range Celsius (Centigrade) Temperature Sensor (−55°C to +130°C) Operating from a Single Li-Ion Battery Cell Temperature (T) Typical VO +130°C +303 mV +100°C +675 mV +80°C +919 mV +30°C +1515 mV +25°C +1574 mV 0°C +1863.9 mV −30°C +2205 mV −40°C +2318 mV −55°C +2485 mV Connection Diagram Figure 2. TO-92 Package Number LP These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM19 LM19 www.ti.com SNIS122E –MAY 2001–REVISED MARCH 2013 Absolute Maximum Ratings(1) Supply Voltage +6.5V to −0.2V Output Voltage (V+ + 0.6 V) to −0.6 V Output Current 10 mA Input Current at any pin(2) 5 mA Storage Temperature −65°C to +150°C Maximum Junction Temperature (TJMAX) +150°C ESD Susceptibility(3) Human Body Model 2500 V Machine Model 250 V Lead Temperature TO-92 Package Soldering (3 seconds dwell) +240°C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V+), the current at that pin should be limited to 5 mA. (3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Operating Ratings(1) Specified Temperature Range TMIN ≤ TA ≤ TMAX 2.4 V ≤ V+≤ 2.7 V −30°C ≤ TA ≤ +130°C 2.7 V ≤ V+≤ 5.5 V −55°C ≤ TA ≤ +130°C Supply Voltage Range (V+) +2.4 V to +5.5 V Thermal Resistance, θJA (2) TO-92 150°C/W (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) The junction to ambient thermal resistance (θJA) is specified without a heat sink in still air. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM19 LM19 SNIS122E –MAY 2001–REVISED MARCH 2013 www.ti.com Electrical Characteristics Unless otherwise noted, these specifications apply for V+ = +2.7 VDC. Boldface limits apply for TA = TJ = TMIN to TMAX ; all other limits TA = TJ = 25°C; Unless otherwise noted. Parameter Conditions Typical(1) LM19C Units Limits(2) (Limit) Temperature to Voltage Error TA = +25°C to +30°C ±2.5 °C (max) VO = (−3.88×10−6×T2) TA = +130°C ±3.5 °C (max) + (−1.15×10−2×T) + 1.8639V(3) TA = +125°C ±3.5 °C (max) TA = +100°C ±3.2 °C (max) TA = +85°C ±3.1 °C (max) TA = +80°C ±3.0 °C (max) TA = 0°C ±2.9 °C (max) TA = −30°C ±3.3 °C (min) TA = −40°C ±3.5 °C (max) TA = −55°C ±3.8 °C (max) Output Voltage at 0°C +1.8639 V Variance from Curve ±1.0 °C Non-Linearity(4) −20°C ≤ TA ≤ +80°C ±0.4 % Sensor Gain (Temperature Sensitivity −30°C ≤ TA ≤ +100°C −11.77 −11.0 mV/°C (min) or Average Slope) to equation: −12.6 mV/°C (max) VO=−11.77 mV/°C×T+1.860V Output Impedance 0 μA ≤ IL ≤ +16 μA(5) (6) 160 Ω (max) Load Regulation(7) 0 μA ≤ IL ≤ +16 μA(5) (6) −2.5 mV (max) Line Regulation(8) +2. 4 V ≤ V+ ≤ +5.0V +3.7 mV/V (max) +5.0 V ≤ V+ ≤ +5.5 V +11 mV (max) Quiescent Current +2. 4 V ≤ V+ ≤ +5.0V 4.5 7 μA (max) +5.0V ≤ V+ ≤ +5.5V 4.5 9 μA (max) +2. 4 V ≤ V+ ≤ +5.0V 4.5 10 μA (max) Change of Quiescent Current +2. 4 V ≤ V+ ≤ +5.5V +0.7 μA Temperature Coefficient of Quiescent −11 nA/°C Current Shutdown Current V+ ≤ +0.8 V 0.02 μA (1) Typicals are at TJ = TA = 25°C and represent most likely parametric norm. (2) Limits are ensured to AOQL (Average Outgoing Quality Level). (3) Accuracy is defined as the error between the measured and calculated output voltage at the specified conditions of voltage, current, and temperature (expressed in°C). (4) Non-Linearity is defined as the deviation of the calculated output-voltage-versus-temperature curve from the best-fit straight line, over the temperature range specified. (5) Negative currents are flowing into the LM19. Positive currents are flowing out of the LM19. Using this convention the LM19 can at most sink −1 μA and source +16 μA. (6) Load regulation or output impedance specifications apply over the supply voltage range of +2.4V to +5.5V. (7) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output due to heating effects can be computed by multiplying the internal dissipation by the thermal resistance. (8) Line regulation is calculated by subtracting the output voltage at the highest supply input voltage from the output voltage at the lowest supply input voltage. 4 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM19 MAX Limit MIN Limit Typical -100 -50 0 50 100 150 -5 -4 -3 -2 -1 0 1 2 3 4 5 ERROR ( ºC) TEMPERATURE (ºC) LM19 www.ti.com SNIS122E –MAY 2001–REVISED MARCH 2013 Typical Performance Characteristics Temperature Error vs. Temperature Thermal Response in Still Air LM19 TRANSFER FUNCTION The LM19's transfer function can be described in different ways with varying levels of precision. A simple linear transfer function, with good accuracy near 25°C, is VO= −11.69 mV/°C × T + 1.8663 V (1) Over the full operating temperature range of −55°C to +130°C, best accuracy can be obtained by using the parabolic transfer function VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 (2) solving for T: (3) A linear transfer function can be used over a limited temperature range by calculating a slope and offset that give best results over that range. A linear transfer function can be calculated from the parabolic transfer function of the LM19. The slope of the linear transfer function can be calculated using the following equation: m = −7.76 × 10−6× T − 0.0115 where • T is the middle of the temperature range of interest and m is in V/°C. (4) For example for the temperature range of Tmin = −30 to Tmax = +100°C: T = 35°C and m = −11.77 mV/°C The offset of the linear transfer function can be calculated using the following equation: b = (VOP(Tmax) + VOP(T) − m × (Tmax+T))/2 where • VOP(Tmax) is the calculated output voltage at Tmax using the parabolic transfer function for VO. • VOP(T) is the calculated output voltage at T using the parabolic transfer function for VO. (5) Using this procedure the best fit linear transfer function for many popular temperature ranges was calculated in Table 1. As shown in Table 1 the error that is introduced by the linear transfer function increases with wider temperature ranges. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM19 LM19 SNIS122E –MAY 2001–REVISED MARCH 2013 www.ti.com Table 1. First Order Equations Optimized For Different Temperature Ranges Temperature Range Linear Equation Maximum Deviation of Linear Equation from T VO= Parabolic Equation (°C) min (°C) Tmax (°C) −55 +130 −11.79 mV/°C × T + 1.8528 V ±1.41 −40 +110 −11.77 mV/°C × T + 1.8577 V ±0.93 −30 +100 −11.77 mV/°C × T + 1.8605 V ±0.70 -40 +85 −11.67 mV/°C × T + 1.8583 V ±0.65 −10 +65 −11.71 mV/°C × T + 1.8641 V ±0.23 +35 +45 −11.81 mV/°C × T + 1.8701 V ±0.004 +20 +30 −11.69 mV/°C × T + 1.8663 V ±0.004 Mounting The LM19 can be applied easily in the same way as other integrated-circuit temperature sensors. It can be glued or cemented to a surface. The temperature that the LM19 is sensing will be within about +0.02°C of the surface temperature to which the LM19's leads are attached. This presumes that the ambient air temperature is almost the same as the surface temperature; if the air temperature were much higher or lower than the surface temperature, the actual temperature measured would be at an intermediate temperature between the surface temperature and the air temperature. To ensure good thermal conductivity the backside of the LM19 die is directly attached to the GND pin. The tempertures of the lands and traces to the other leads of the LM19 will also affect the temperature that is being sensed. Alternatively, the LM19 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or screwed into a threaded hole in a tank. As with any IC, the LM19 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold temperatures where condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often used to ensure that moisture cannot corrode the LM19 or its connections. The thermal resistance junction to ambient (θJA) is the parameter used to calculate the rise of a device junction temperature due to its power dissipation. For the LM19 the equation used to calculate the rise in the die temperature is as follows: TJ = TA + θJA [(V+ IQ) + (V+ − VO) IL] where • IQ is the quiescent current and ILis the load current on the output. (6) Since the LM19's junction temperature is the actual temperature being measured care should be taken to minimize the load current that the LM19 is required to drive. Table 2 summarizes the rise in die temperature of the LM19 without any loading, and the thermal resistance for different conditions. Table 2. Temperature Rise of LM19 Due to Self-Heating and Thermal Resistance (θJA) TO-92 TO-92 no heat sink small heat fin θJA TJ − TA θJA TJ − TA (°C/W) (°C) (°C/W) (°C) Still air 150 TBD TBD TBD Moving air TBD TBD TBD TBD 6 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM19 LM19 www.ti.com SNIS122E –MAY 2001–REVISED MARCH 2013 Capacitive Loads The LM19 handles capacitive loading well. Without any precautions, the LM19 can drive any capacitive load less than 300 pF as shown in Figure 3. Over the specified temperature range the LM19 has a maximum output impedance of 160 Ω. In an extremely noisy environment it may be necessary to add some filtering to minimize noise pickup. It is recommended that 0.1 μF be added from V+ to GND to bypass the power supply voltage, as shown in Figure 4. In a noisy environment it may even be necessary to add a capacitor from the output to ground with a series resistor as shown in Figure 4. A 1 μF output capacitor with the 160 Ω maximum output impedance and a 200 Ω series resistor will form a 442 Hz lowpass filter. Since the thermal time constant of the LM19 is much slower, the overall response time of the LM19 will not be significantly affected. Figure 3. LM19 No Decoupling Required for Capacitive Loads Less than 300 pF Table 3. LM19 with Filter for Noisy Environment and Capacitive Loading greater than 300 pF R (Ω) C (μF) 200 1 470 0.1 680 0.01 1 k 0.001 Either placement of resistor as shown above is just as effective. Figure 4. LM19 with Filter for Noisy Environment and Capacitive Loading greater than 300 pF Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM19 4.1V R1 R3 R2 LM4040 U3 0.1 PF R4 VOUT V+ VT VTemp + - U1 V+ LM19 U2 (High = overtemp alarm) VT1 VT2 VTEMP VOUT VT1 = R1 + R2||R3 (4.1)R2 VT2 = R2 + R1||R3 (4.1)R2||R3 LM7211 LM19 SNIS122E –MAY 2001–REVISED MARCH 2013 www.ti.com Applications Circuits Figure 5. Centigrade Thermostat Figure 6. Conserving Power Dissipation with Shutdown Figure 7. Suggested Connection to a Sampling Analog to Digital Converter Input Stage Most CMOS ADCs found in ASICs have a sampled data comparator input structure that is notorious for causing grief to analog output devices such as the LM19 and many op amps. The cause of this grief is the requirement of instantaneous charge of the input sampling capacitor in the ADC. This requirement is easily accommodated by the addition of a capacitor. Since not all ADCs have identical input stages, the charge requirements will vary necessitating a different value of compensating capacitor. This ADC is shown as an example only. If a digital output temperature is required please refer to devices such as the LM74. 8 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM19 LM19 www.ti.com SNIS122E –MAY 2001–REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E Page • Changed layout of National Data Sheet to TI format ............................................................................................................ 8 Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM19 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM19CIZ/LFT4 ACTIVE TO-92 LP 3 2000 Green (RoHS & no Sb/Br) SN | CU SN N / A for Pkg Type LM19 CIZ LM19CIZ/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS & no Sb/Br) SN | CU SN N / A for Pkg Type -55 to 130 LM19 CIZ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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DS22003B-page 1 MCP3421 Features • 18-bit ΔΣ ADC in a SOT-23-6 package • Differential input operation • Self calibration of Internal Offset and Gain per each conversion • On-board Voltage Reference: - Accuracy: 2.048V ± 0.05% - Drift: 5 ppm/°C • On-board Programmable Gain Amplifier (PGA): - Gains of 1,2,4 or 8 • On-board Oscillator • INL: 10 ppm of FSR (FSR = 4.096V/PGA) • Programmable Data Rate Options: - 3.75 SPS (18 bits) - 15 SPS (16 bits) - 60 SPS (14 bits) - 240 SPS (12 bits) • One-Shot or Continuous Conversion Options • Low current consumption: - 145 μA typical (VDD= 3V, Continuous Conversion) - 39 μA typical (VDD= 3V, One-Shot Conversion with 1 SPS) • Supports I2C Serial Interface: - Standard, Fast and High Speed Modes • Single Supply Operation: 2.7V to 5.5V • Extended Temperature Range: -40°C to 125°C Typical Applications • Portable Instrumentation • Weigh Scales and Fuel Gauges • Temperature Sensing with RTD, Thermistor, and Thermocouple • Bridge Sensing for Pressure, Strain, and Force. Package Types Description The MCP3421 is a single channel low-noise, high accuracy ΔΣ A/D converter with differential inputs and up to 18 bits of resolution in a small SOT-23-6 package. The on-board precision 2.048V reference voltage enables an input range of ±2.048V differentially (Δ voltage = 4.096V). The device uses a two-wire I2C compatible serial interface and operates from a single 2.7V to 5.5V power supply. The MCP3421 device performs conversion at rates of 3.75, 15, 60, or 240 samples per second (SPS) depending on the user controllable configuration bit settings using the two-wire I2C serial interface. This device has an on-board programmable gain amplifier (PGA). The user can select the PGA gain of x1, x2, x4, or x8 before the analog-to-digital conversion takes place. This allows the MCP3421 device to convert a smaller input signal with high resolution. The device has two conversion modes: (a) Continuous mode and (b) One-Shot mode. In One-Shot mode, the device enters a low current standby mode automatically after one conversion. This reduces current consumption greatly during idle periods. The MCP3421 device can be used for various high accuracy analog-to-digital data conversion applications where design simplicity, low power, and small footprint are major considerations. Block Diagram 1 2 3 4 5 VIN+ 6 VSS SCL VINVDD SDA SOT-23-6 Top View VSS VDD VIN+ VINSCL SDA Voltage Reference Clock (2.048V) I2C Interface Gain = 1, 2, 4, or 8 VREF ΔΣ ADC PGA Converter Oscillator 18-Bit Analog-to-Digital Converter with I2C Interface and On-Board Reference MCP3421 DS22003B-page 2 © 2006 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD...................................................................................7.0V All inputs and outputs w.r.t VSS ............... –0.3V to VDD+0.3V Differential Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current .................................Continuous Current at Input Pins ....................................................±2 mA Current at Output and Supply Pins ............................±10 mA Storage Temperature.....................................-65°C to +150°C Ambient Temp. with power applied ...............-55°C to +125°C ESD protection on all pins ................ ≥ 6 kV HBM, ≥ 400V MM Maximum Junction Temperature (TJ) ..........................+150°C †Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range. Parameters Sym Min Typ Max Units Conditions Analog Inputs Differential Input Range — ±2.048/PGA — V VIN = VIN+ - VINCommon- Mode Voltage Range (absolute) (Note 1) VSS-0.3 — VDD+0.3 V Differential Input Impedance (Note 2) ZIND (f) — 2.25/PGA — MΩ During normal mode operation Common Mode input Impedance ZINC (f) — 25 — MΩ PGA = 1, 2, 4, 8 System Performance Resolution and No Missing Codes (Note 8) 12 — — Bits DR = 240 SPS 14 — — Bits DR = 60 SPS 16 — — Bits DR = 15 SPS 18 — — Bits DR = 3.75 SPS Data Rate (Note 3) DR 176 240 328 SPS S1,S0 = ‘00’, (12 bits mode) 44 60 82 SPS S1,S0 = ‘01’, (14 bits mode) 11 15 20.5 SPS S1,S0 = ‘10’, (16 bits mode) 2.75 3.75 5.1 SPS S1,S0 = ‘11’, (18 bits mode) Output Noise — 1.5 — μVRMS TA = 25°C, DR = 3.75 SPS, PGA = 1, VIN = 0 Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. 2: This input impedance is due to 3.2 pF internal input sampling capacitor. 3: The total conversion speed includes auto-calibration of offset and gain. 4: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 5: Includes all errors from on-board PGA and VREF. 6: Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA. 7: This parameter is ensured by characterization and not 100% tested. 8: This parameter is ensured by design and not 100% tested. © 2006 Microchip Technology Inc. DS22003B-page 3 MCP3421 Integral Nonlinearity (Note 4) INL — 10 35 ppm of FSR DR = 3.75 SPS (Note 6) Internal Reference Voltage VREF — 2.048 — V Gain Error (Note 5) — 0.05 0.35 % PGA = 1, DR = 3.75 SPS PGA Gain Error Match (Note 5) — 0.1 — % Between any 2 PGA gains Gain Error Drift (Note 5) — 5 40 ppm/°C PGA=1, DR=3.75 SPS Offset Error VOS — 15 40 μV Tested at PGA = 1 VDD = 5.0V and DR = 3.75 SPS Offset Drift vs. Temperature — 50 — nV/°C VDD = 5.0V Common-Mode Rejection — 105 — dB at DC and PGA =1, — 110 — dB at DC and PGA =8, TA = +25°C Gain vs. VDD — 5 — ppm/V TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 Power Supply Rejection at DC — 100 — dB TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 Power Requirements Voltage Range VDD 2.7 — 5.5 V Supply Current during Conversion IDDA — 155 190 μA VDD = 5.0V — 145 — μA VDD = 3.0V Supply Current during Standby Mode IDDS — 0.1 0.5 μA I2C Digital Inputs and Digital Outputs High level input voltage VIH 0.7 VDD — VDD V Low level input voltage VIL — — 0.3VDD V Low level output voltage VOL — — 0.4 V IOL = 3 mA, VDD = +5.0V Hysteresis of Schmitt Trigger for inputs (Note 7) VHYST 0.05VDD — — V fSCL = 100 kHz Supply Current when I2C bus line is active IDDB — — 10 μA Input Leakage Current IILH — — 1 μA VIH = 5.5V IILL -1 — — μA VIL = GND Pin Capacitance and I2C Bus Capacitance Pin capacitance CPIN — — 10 pF I2C Bus Capacitance Cb — — 400 pF Thermal Characteristics Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range. Parameters Sym Min Typ Max Units Conditions Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. 2: This input impedance is due to 3.2 pF internal input sampling capacitor. 3: The total conversion speed includes auto-calibration of offset and gain. 4: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 5: Includes all errors from on-board PGA and VREF. 6: Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA. 7: This parameter is ensured by characterization and not 100% tested. 8: This parameter is ensured by design and not 100% tested. MCP3421 DS22003B-page 4 © 2006 Microchip Technology Inc. 2.0 TYPICAL PERFORMANCE CURVES Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. FIGURE 2-1: INL vs. Supply Voltage (VDD). FIGURE 2-2: INL vs. Temperature. FIGURE 2-3: Offset Error vs. Temperature. FIGURE 2-4: Noise vs. Input Voltage. FIGURE 2-5: Total Error vs. Input Voltage. FIGURE 2-6: Gain Error vs. Temperature. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. .000 .001 .002 .003 .004 .005 2.5 3 3.5 4 4.5 5 5.5 VDD (V) PGA = 1 PGA = 2 PGA = 8 PGA = 4 Integral Nonlinearity (% of FSR) 0 0.001 0.002 0.003 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) Integral Nonlinearity (% of FSR) VDD = 5 V VDD = 2.7V PGA = 1 -20 -15 -10 -5 0 5 10 15 20 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Offset Error (μV) VDD = 5V PGA = 1 PGA = 2 PGA = 4 PGA = 8 0.0 2.5 5.0 7.5 10.0 -100 -75 -50 -25 0 25 50 75 100 Input Voltage (% of Full-Scale) Noise (μV, rms) PGA = 1 PGA = 2 PGA = 8 PGA = 4 TA = +25°C VDD = 5V -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 -100 -75 -50 -25 0 25 50 75 100 Input Voltage (% of Full-Scale) Total Error (mV) PGA = 1 PGA = 2 PGA = 8 PGA = 4 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Gain Error (% of FSR) VDD = 5.0V PGA = 1 PGA = 2 PGA = 8 PGA = 4 © 2006 Microchip Technology Inc. DS22003B-page 5 MCP3421 Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. FIGURE 2-7: IDDA vs. Temperature. FIGURE 2-8: IDDS vs. Temperature. FIGURE 2-9: IDDB vs. Temperature. FIGURE 2-10: OSC Drift vs. Temperature. FIGURE 2-11: Frequency Response. 100 120 140 160 180 200 220 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) IDDA (μA) VDD = 5V VDD = 2.7V 0 100 200 300 400 500 600 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) IDDS (nA) VDD = 2.7V VDD = 5V 0 1 2 3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) IDDB (􀁐A) VDD = 5V VDD = 4.5V VDD = 3.3V VDD = 2.7V -1 0 1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Oscillator Drift (%) VDD = 5.0V VDD = 2.7V Data Rate = 3.75 SPS -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.1 1 10 100 1000 10000 Input Signal Frequency (Hz) Magnitude (dB) 0.1 1 10 100 1k 10k MCP3421 DS22003B-page 6 © 2006 Microchip Technology Inc. 3.0 PIN DESCRIPTIONS TABLE 3-1: PIN FUNCTION TABLE 3.1 Analog Inputs (VIN+, VIN-) VIN+ and VIN- are differential signal input pins. The MCP3421 device accepts a fully differential analog input signal which is connected on the VIN+ and VINinput pins. The differential voltage that is converted is defined by VIN = (VIN+ - VIN-) where VIN+ is the voltage applied at the VIN+ pin and VIN- is the voltage applied at the VIN- pin. The input signal level is amplified by the programmable gain amplifier (PGA) before the conversion. The differential input voltage should not exceed an absolute of (2* VREF/PGA) for accurate measurement, where VREF is the internal reference voltage (2.048V) and PGA is the PGA gain setting. The converter output code will saturate if the input range exceeds (2* VREF/PGA). The absolute voltage range on each of the differential input pins is from VSS-0.3V to VDD+0.3V. Any voltage above or below this range will cause leakage currents through the Electrostatic Discharge (ESD) diodes at the input pins. This ESD current can cause unexpected performance of the device. The common mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in Section 1.0 “Electrical Characteristics” and Section 4.0 “Description of Device Operation”. 3.2 Supply Voltage (VDD, VSS) VDD is the power supply pin for the device. This pin requires an appropriate bypass capacitor of about 0.1 μF (ceramic) to ground. An additional 10 μF capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in some application boards. The supply voltage (VDD) must be maintained in the 2.7V to 5.5V range for specified operation. VSS is the ground pin and the current return path of the device. The user must connect the VSS pin to a ground plane through a low impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.3 Serial Clock Pin (SCL) SCL is the serial clock pin of the I2C interface. The MCP3421 acts only as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the MCP3421 occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SCL pin. Refer to Section 5.3 “I2C Serial Communications” for more details of I2C Serial Interface communication. 3.4 Serial Data Pin (SDA) SDA is the serial data pin of the I2C interface. The SDA pin is used for input and output data. In read mode, the conversion result is read from the SDA pin (output). In write mode, the device configuration bits are written (input) though the SDA pin. The SDA pin is an opendrain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SDA pin. Except for start and stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 5.3 “I2C Serial Communications” for more details of I2C Serial Interface communication. Pin No Sym Function 1 VIN+ Non-Inverting Analog Input Pin 2 VSS Ground Pin 3 SCL Serial Clock Input Pin of the I2C Interface 4 SDA Bidirectional Serial Data Pin of the I2C Interface 5 VDD Positive Supply Voltage Pin 6 VIN- Inverting Analog Input Pin © 2006 Microchip Technology Inc. DS22003B-page 7 MCP3421 4.0 DESCRIPTION OF DEVICE OPERATION 4.1 General Overview The MCP3421 is a low-power, 18-Bit Delta-Sigma A/D converter with an I2C serial interface. The device contains an on-board voltage reference (2.048V), programmable gain amplifier (PGA), and internal oscillator. The user can select 12, 14, 16, or 18 bit conversion by setting the configuration register bits. The device can be operated in Continuous Conversion or One-Shot Conversion mode. In the Continuous Conversion mode, the device converts the inputs continuously. While in the One-Shot Conversion mode, the device converts the input one time and stays in the low-power standby mode until it receives another command for a new conversion. During the standby mode, the device consumes less than 0.1 μA typical. 4.2 Power-On-Reset (POR) The device contains an internal Power-On-Reset (POR) circuit that monitors power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. The POR has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. A 0.1 μF decoupling capacitor should be mounted as close as possible to the VDD pin for additional transient immunity. The threshold voltage is set at 2.2V with a tolerance of approximately ±5%. If the supply voltage falls below this threshold, the device will be held in a reset condition. The typical hysteresis value is approximately 200 mV. The POR circuit is shut-down during the low-power standby mode. Once a power-up event has occurred, the device requires additional delay time (approximately 300 μs) before a conversion can take place. During this time, all internal analog circuitries are settled before the first conversion occurs. Figure 4-1 illustrates the conditions for power-up and power-down events under typical start-up conditions. When the device powers up, it automatically resets and sets the configuration bits to default settings. The default configuration bit conditions are a PGA gain of 1 V/V and a conversion speed of 240 SPS in Continuous Conversion mode. When the device receives an I2C General Call Reset command, it performs an internal reset similar to a Power-On-Reset event. FIGURE 4-1: POR Operation. 4.3 Internal Voltage Reference The device contains an on-board 2.048V voltage reference. This reference voltage is for internal use only and not directly measurable. The specifications of the reference voltage are part of the device’s gain and drift specifications. Therefore, there is no separate specification for the on-board reference. 4.4 Analog Input Channel The differential analog input channel has a switched capacitor structure. The internal sampling capacitor (3.2 pF) is charged and discharged to process a conversion. The charging and discharging of the input sampling capacitor creates dynamic input currents at the VIN+ and VIN- input pins, which is inversely proportional to the internal sampling capacitor and internal frequency. The current is also a function of the differential input voltages. Care must be taken in setting the common-mode voltage and input voltage ranges so that the input limits do not exceed the ranges specified in Section 1.0 “Electrical Characteristics”. 4.5 Digital Output Code The digital output code produced by the MCP3421 is a function of PGA gain, input signal, and internal reference voltage. In a fixed setting, the digital output code is proportional to the voltage difference between the two analog inputs. The output data format is a binary two’s complement. With this code scheme, the MSB can be considered a sign indicator. When the MSB is a logic ‘0’, it indicates a positive value. When the MSB is a logic ‘1’, it indicates a negative value. The following is an example of the output code: (a) for a negative full-scale input voltage: 100...000 (b) for a zero differential input voltage: 000...000 (c) for a positive full-scale input voltage: 011...111. The MSB is always transmitted first through the serial port. The number of data bits for each conversion is 18, 16, 14, or 12 bits depending on the conversion mode selection. VDD 2.2V 2.0V 300 μS Reset Start-up Normal Operation Reset Time MCP3421 DS22003B-page 8 © 2006 Microchip Technology Inc. The output codes will not roll-over if the input voltage exceeds the maximum input range. In this case, the code will be locked at 0111...11 for all voltages greater than +(VREF - 1 LSB) and 1000...00 for voltages less than -VREF. Table 4-2 shows an example of output codes of various input levels using 18 bit conversion mode. Table 4-3 shows an example of minimum and maximum codes for each data rate option. The output code is given by: EQUATION 4-1: The LSB of the code is given by: EQUATION 4-2: TABLE 4-1: LSB SIZE OF VARIOUS BIT CONVERSION MODES TABLE 4-2: EXAMPLE OF OUTPUT CODE FOR 18 BITS TABLE 4-3: MINIMUM AND MAXIMUM CODES 4.6 Self-Calibration The device performs a self-calibration of offset and gain for each conversion. This provides reliable conversion results from conversion-to-conversion over variations in temperature as well as power supply fluctuations. 4.7 Input Impedance The MCP3421 uses a switched-capacitor input stage using a 3.2 pF sampling capacitor. This capacitor is switched (charged and discharged) at a rate of the sampling frequency that is generated by the on-board clock. The differential mode impedance varies with the PGA settings. The typical differential input impedance during a normal mode operation is given by: Since the sampling capacitor is only switching to the input pins during a conversion process, the above input impedance is only valid during conversion periods. In a low power standby mode, the above impedance is not presented at the input pins. Therefore, only a leakage current due to ESD diode is presented at the input pins. The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can increase the system performance errors such as offset, gain, and integral nonlinearity (INL) errors. Ideally, the input source impedance should be zero. This can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms. Bit Resolutions LSB (V) 12 bits 1 mV 14 bits 250 μV 16 bits 62.5 μV 18 bits 15.625 μV Input Voltage (V) Digital Code ≥ VREF 011111111111111111 VREF - 1 LSB 011111111111111111 2 LSB 000000000000000010 1 LSB 000000000000000001 0 000000000000000000 -1 LSB 111111111111111111 -2 LSB 111111111111111110 - VREF 100000000000000000 < -VREF 100000000000000000 Output Code (Max Code + 1) (VIN+ – VIN-) 2.048V = × -------------------------------------- LSB 2 × 2.048V 2N = -------------------------- Where: N = the number of bits Number of Bits Data Rate Minimum Code Maximum Code 12 240 SPS -2048 2047 14 60 SPS -8192 8191 16 15 SPS -32768 32767 18 3.75 SPS -131072 131071 Note: Maximum n-bit code = 2n-1 - 1 Minimum n-bit code = -1 x 2n-1 ZIN(f) = 2.25 MΩ/PGA © 2006 Microchip Technology Inc. DS22003B-page 9 MCP3421 4.8 Aliasing and Anti-aliasing Filter Aliasing occurs when the input signal contains timevarying signal components with frequency greater than half the sample rate. In the aliasing conditions, the device can output unexpected output codes. For applications that are operating in electrical noise environments, the time-varying signal noise or high frequency interference components can be easily added to the input signals and cause aliasing. Although the MCP3421 device has an internal first order sinc filter, its’ filter response may not give enough attenuation to all aliasing signal components. To avoid the aliasing, an external anti-aliasing filter, which can be accomplished with a simple RC low-pass filter, is typically used at the input pins. The low-pass filter cuts off the high frequency noise components and provides a band-limited input signal to the MCP3421 input pins. MCP3421 DS22003B-page 10 © 2006 Microchip Technology Inc. 5.0 USING THE MCP3421 DEVICE 5.1 Operating Modes The user operates the device by setting up the device configuration register and reads the conversion data using serial I2C interface commands. The MCP3421 operates in two modes: (a) Continuous Conversion Mode or (b) One-Shot Conversion Mode (single conversion). The selection is made by setting the O/C bit in the Configuration Register. Refer to Section 5.2 “Configuration Register” for more information. 5.1.1 CONTINUOUS CONVERSION MODE (O/C BIT = 1) The MCP3421 device performs a Continuous Conversion if the O/C bit is set to logic “high”. Once the conversion is completed, the result is placed at the output data register. The device immediately begins another conversion and overwrites the output data register with the most recent data. The device also clears the data ready flag (RDY bit = 0) when the conversion is completed. The device sets the ready flag bit (RDY bit = 1), if the latest conversion result has been read by the Master. 5.1.2 ONE-SHOT CONVERSION MODE (O/C BIT = 0) Once the One-Shot Conversion (single conversion) Mode is selected, the device performs a conversion, updates the Output Data register, clears the data ready flag (RDY = 0), and then enters a low power standby mode. A new One-Shot Conversion is started again when the device receives a new write command with RDY = 1. This One-Shot Conversion Mode is recommended for low power operating applications. During the low current standby mode, the device consumes less than 1 μA typical. For example, if user collects 18 bit conversion data once a second in One-Shot Conversion mode, the device draws only about one fourth of its total operating current. In this example, the device consumes approximately 39 μA (= ~145 μA/3.75 SPS), if the device performs only one conversion per second (1 SPS) in 18-bit conversion mode with 3V power supply. © 2006 Microchip Technology Inc. DS22003B-page 11 MCP3421 5.2 Configuration Register The MCP3421 has an 8-bit wide configuration register to select for: PGA gain, conversion rate, and conversion mode. This register allows the user to change the operating condition of the device and check the status of the device operation. The user can rewrite the configuration byte any time during the device operation. Register 5-1 shows the configuration register bits. REGISTER 5-1: CONFIGURATION REGISTER R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 RDY C1 C0 O/C S1 S0 G1 G0 1 * 0 * 0 * 1 * 0 * 0 * 0 * 0 * bit 7 bit 0 * Default Configuration after Power-On Reset Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDY: Ready Bit This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated with a new conversion. In One-Shot Conversion mode, writing this bit to “1” initiates a new conversion. Reading RDY bit with the read command: 1 = Output register has not been updated. 0 = Output register has been updated with the latest conversion data. Writing RDY bit with the write command: Continuous Conversion mode: No effect One-Shot Conversion mode: 1 = Initiate a new conversion. 0 = No effect. bit 6-5 C1-C0: Channel Selection Bits These are the Channel Selection bits, but not used in the MCP3421 device. bit 4 O/C: Conversion Mode Bit 1 = Continuous Conversion Mode. Once this bit is selected, the device performs data conversions continuously. 0 = One-Shot Conversion Mode. The device performs a single conversion and enters a low power standby mode until it receives another write/read command. bit 3-2 S1-S0: Sample Rate Selection Bit 00 = 240 SPS (12 bits), 01 = 60 SPS (14 bits), 10 = 15 SPS (16 bits), 11 = 3.75 SPS (18 bits) bit 1-0 G1-G0: PGA Gain Selector Bits 00 = 1 V/V, 01 = 2 V/V, 10 = 4 V/V, 11 = 8 V/V MCP3421 DS22003B-page 12 © 2006 Microchip Technology Inc. In read mode, the RDY bit in the configuration byte indicates the state of the conversion: (a) RDY = 1 indicates that the data bytes that have just been read were not updated from the previous conversion. (b) RDY = 0 indicates that the data bytes that have just been read were updated. If the configuration byte is read repeatedly by clocking continuously after the first read (i.e., after the 5th byte in the 18-bit conversion mode), the state of the RDY bit indicates whether the device is ready with new conversion data. See Figure 5-2. For example, RDY = 0 means new conversion data is ready for reading. In this case, the user can send a stop bit to exit the current read operation and send a new read command to read out updated conversion data. See Figures 5-2 and 5-3 for reading conversion data. The user can rewrite the configuration byte any time for a new setting. Tables 5-1 and 5-2 show the examples of the configuration bit operation. 5.3 I2C Serial Communications The MCP3421 device communicates with Master (microcontroller) through a serial I2C (Inter-Integrated Circuit) interface and supports standard (100 kbits/sec), fast (400 kbits/sec) and high-speed (3.4 Mbits/sec) modes. The serial I2C is a bidirectional 2-wire data bus communication protocol using opendrain SCL and SDA lines. The MCP3421 can only be addressed as a slave. Once addressed, it can receive configuration bits or transmit the latest conversion results. The serial clock pin (SCL) is an input only and the serial data pin (SDA) is bidirectional. An example of a hardware connection diagram is shown in Figure 6-1. The Master starts communication by sending a START bit and terminates the communication by sending a STOP bit. The first byte after the START bit is always the address byte of the device, which includes the device code, the address bits, and the R/W bit. The device code for the MCP3421 device is 1101. The address bits (A2, A1, A0) are pre-programmed at the factory. In general, the address bits are specified by the customer when they order the device. The three address bits are programmed to “000” at the factory, if they are not specified by the customer. Figure 5-1 shows the details of the MCP3421 address byte. During a low power standby mode, SDA and SCL pins remain at a floating condition. More details of the I2C bus characteristic is described in Section 5.6 “I2C Bus Characteristics”. 5.3.1 DEVICE ADDRESSING The address byte is the first byte received following the START condition from the Master device. The MCP3421 device code is 1101. The device code is followed by three address bits (A2, A1, A0) which are programmed at the factory. The three address bits allow up to eight MCP3421 devices on the same data bus line. The (R/W) bit determines if the Master device wants to read the conversion data or write to the Configuration register. If the (R/W) bit is set (read mode), the MCP3421 outputs the conversion data in the following clocks. If the (R/W) bit is cleared (write mode), the MCP3421 expects a configuration byte in the following clocks. When the MCP3421 receives the correct address byte, it outputs an acknowledge bit after the R/W bit. Figure 5-1 shows the MCP3421 address byte. See Figures 5-2 and 5-3 for the read and write operations of the device. TABLE 5-1: CONFIGURATION BITS FOR WRITING R/W O/C RDY Operation 0 0 0 No effect if all other bits remain the same - operation continues with the previous settings 0 0 1 Initiate One-Shot Conversion 0 1 0 Initiate Continuous Conversion 0 1 1 Initiate Continuous Conversion TABLE 5-2: CONFIGURATION BITS FOR READING R/W O/C RDY Operation 1 0 0 New conversion data in One- Shot conversion mode has been just read. The RDY bit remains low until set by a new write command. 1 0 1 One-Shot Conversion is in progress, The conversion data is not updated yet. The RDY bit stays high. 1 1 0 New conversion data in Continuous Conversion mode has been just read. The RDY bit changes to high after this read. 1 1 1 The conversion data in Continuous Conversion mode was already read. The latest conversion data is not ready. The RDY bit stays high until a new conversion is completed. © 2006 Microchip Technology Inc. DS22003B-page 13 MCP3421 FIGURE 5-1: MCP3421 Address Byte. 5.3.2 READING DATA FROM THE DEVICE When the Master sends a read command (R/W = 1), the MCP3421 outputs the conversion data bytes and configuration byte. Each byte consists of 8 bits with one acknowledge (ACK) bit. The ACK bit after the address byte is issued by the MCP3421 and the ACK bits after each conversion data bytes are issued by the Master. When the device is configured for 18-bit conversion mode, the device outputs three data bytes followed by a configuration byte. The first 7 data bits in the first data byte are the MSB of the conversion data. The user can ignore the first 6 data bits, and take the 7th data bit (D17) as the MSB of the conversion data. The LSB of the 3rd data byte is the LSB of the conversion data (D0). If the device is configured for 12, 14, or 16 bit-mode, the device outputs two data bytes followed by a configuration byte. In 16 bit-conversion mode, the MSB of the first data byte is the MSB (D15) of the conversion data. In 14-bit conversion mode, the first two bits in the first data byte can be ignored (they are the MSB of the conversion data), and the 3rd bit (D13) is the MSB of the conversion data. In 12-bit conversion mode, the first four bits can be ignored (they are the MSB of the conversion data), and the 5th bit (D11) of the byte represents the MSB of the conversion data. Table 5-3 shows an example of the conversion data output of each conversion mode. The configuration byte follows the output data byte. The device outputs the configuration byte as long as the SCL pulses are received. The device terminates the current outputs when it receives a Not-Acknowledge (NAK), a repeated start or a stop bit at any time during the output bit stream. It is not required to read the configuration byte. However, the user may read the configuration byte to check the RDY bit condition to confirm whether the just received data bytes are updated conversion data. The user may continuously send clock (SCL) to repeatedly read the configuration bytes to check the RDY bit status. Figures 5-2 and 5-3 show the timing diagrams of the reading. 5.3.3 WRITING A CONFIGURATION BYTE TO THE DEVICE When the Master sends an address byte with the R/W bit low (R/W = 0), the MCP3421 expects one configuration byte following the address. Any byte sent after this second byte will be ignored. The user can change the operating mode of the device by writing the configuration register bits. If the device receives a write command with a new configuration setting, the device immediately begins a new conversion and updates the conversion data. Start bit Read/Write bit Address Byte R/W ACK 1 1 0 1 X X X Device Code Address Bits (Note 1) Address Acknowledge bit Address Note 1: Specified by customer and programmed at the factory. If not specified by the customer, programmed to ‘000’. TABLE 5-3: EXAMPLE OF CONVERSION DATA OUTPUT OF EACH CONVERSION MODE Conversion Mode Conversion Data Output 18-bits MMMMMMMD16 (1st data byte) - D15 ~ D8 (2nd data byte) - D7 ~ D0 (3rd data byte) - Configuration byte 16-bits MD14~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte 14-bits MMMD12~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte 12-bits MMMMMD10D9D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte Note: M is MSB of the data byte. MCP3421 DS22003B-page 14 © 2006 Microchip Technology Inc. FIGURE 5-2: Timing Diagram For Reading From The MCP3421 With 18-Bit Mode. 1 9 1 9 1 9 1 9 1 9 1 9 1 1 0 1 A2 A1 A0 D ACK by RDY O/C MCP3421 7 Start Bit by R/W Master Repeat of D17 (MSB) 2nd Byte Upper Data Byte (Data on Clocks 1-6th can be ignored) ACK by Master ACK by Master ACK by Master ACK by Master 17 D 16 D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C1 C0 S1 S0 G1 G0 1st Byte MCP3421 Address Byte 3rd Byte Middle Data Byte 4th Byte Lower Data Byte 5th Byte Configuration Byte (Optional) C1 C0 S1 S0 G1 G0 NAK by Master Stop Bit by Master (Optional) Nth Repeated Byte: Configuration Byte Note: – MCP3421 device code is 1101. – Address Bits A2- A0 = 000 are programmed at the factory unless customer requests specific codes. – Stop bit or NAK bit can be issued any time during reading. – Data bits on clocks 1 - 6th in 2nd byte are repeated MSB and can be ignored. SCL SDA RDY O/C © 2006 Microchip Technology Inc. DS22003B-page 15 MCP3421 FIGURE 5-3: Timing Diagram For Reading From The MCP3421 With 12-Bit to 16-Bit Modes. 1 1 0 1 A2 A1 A0 ACK by MCP3421 Start Bit by Master 2nd Byte Middle Data Byte ACK by Master ACK by Master ACK by Master D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C1 C0 S1 S0 G1 G0 1st Byte MCP3421 Address Byte 3rd Byte Lower Data Byte 4th Byte Configuration Byte (Optional) C1 C0 S1 S0 G1 G0 NAK by Master Stop Bit by Master (Optional) Nth Repeated Byte: Configuration Byte Note: – MCP3421 device code is 1101. – Address Bits A2- A0 = 000 are programmed at the factory unless customer requests specific codes. – Stop bit or NAK bit can be issued any time during reading. – In 14 - bit mode: D15 and D14 are repeated MSB and can be ignored. – In 12 - bit mode: D15 - D12 are repeated MSB and can be ignored. 1 9 1 9 1 9 1 9 SCL SDA 1 9 R/W RDY O/C RDY O/C MCP3421 DS22003B-page 16 © 2006 Microchip Technology Inc. FIGURE 5-4: Timing Diagram For Writing To The MCP3421. 5.4 General Call The MCP3421 acknowledges the general call address (0x00 in the first byte). The meaning of the general call address is always specified in the second byte. Refer to Figure 5-5. The MCP3421 supports the following general calls: 5.4.1 GENERAL CALL RESET The general call reset occurs if the second byte is ‘00000110’ (06h). At the acknowledgement of this byte, the device will abort current conversion and perform an internal reset similar to a power-on-reset (POR). 5.4.2 GENERAL CALL CONVERSION The general call conversion occurs if the second byte is ‘00001000’ (08h). All devices on the bus initiate a conversion simultaneously. For the MCP3421 device, the configuration will be set to the One-Shot Conversion mode and a single conversion will be performed. The PGA and data rate settings are unchanged with this general call. FIGURE 5-5: General Call Address Format. For more information on the general call, or other I2C modes, please refer to the Phillips I2C specification. 1 9 1 9 Stop Bit by 1 1 0 1 A2 A1 A0 R/W ACK by MCP3421 RDY C1 C0 O/C S1 S0 G1 G0 1st Byte: 2nd Byte: Master ACK by MCP3421 MCP3421 Address Byte Configuration Byte Start Bit by Master with Write command Note: – Stop bit can be issued any time during writing. – MCP3421 device code is 1101. – Address Bits A2- A0 = 000 are programmed at factory unless customer requests different codes. SCL SDA Note: The I2C specification does not allow to use “00000000” (00h) in the second byte. LSB First Byte ACK 0 0 0 0 0 0 0 0 A x x x x x x x x A (General Call Address) Second Byte ACK © 2006 Microchip Technology Inc. DS22003B-page 17 MCP3421 5.5 High-Speed (HS) Mode The I2C specification requires that a high-speed mode device must be ‘activated’ to operate in high-speed mode. This is done by sending a special address byte of 00001XXX following the START bit. The XXX bits are unique to the High-Speed (HS) mode Master. This byte is referred to as the High-Speed (HS) Master Mode Code (HSMMC). The MCP3421 device does not acknowledge this byte. However, upon receiving this code, the MCP3421 switches on its HS mode filters and communicates up to 3.4 MHz on SDA and SCL. The device will switch out of the HS mode on the next STOP condition. For more information on the HS mode, or other I2C modes, please refer to the Phillips I2C specification. 5.6 I2C Bus Characteristics The I2C specification defines the following bus protocol: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined using Figure 5-6. 5.6.1 BUS NOT BUSY (A) Both data and clock lines remain HIGH. 5.6.2 START DATA TRANSFER (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 5.6.3 STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations can be ended with a STOP condition. 5.6.4 DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. 5.6.5 ACKNOWLEDGE The Master (microcontroller) and the slave (MCP3421) use an acknowledge pulse as a hand shake of communication for each byte. The ninth clock pulse of each byte is used for the acknowledgement. The acknowledgement is achieved by pulling-down the SDA line “LOW” during the 9th clock pulse. The clock pulse is always provided by the Master (microcontroller) and the acknowledgement is issued by the receiving device of the byte (Note: The transmitting device must release the SDA line (“HIGH”) during the acknowledge pulse.). For example, the slave (MCP3421) issues the acknowledgement (bring down the SDA line “LOW”) after the end of each receiving byte, and the master (microcontroller) issues the acknowledgement when it reads data from the Slave (MCP3421). When the MCP3421 is addressed, it generates an acknowledge after receiving each byte successfully. The Master device (microcontroller) must provide an extra clock pulse (9th pulse of each byte) for the acknowledgement from the MCP3421 (slave). The MCP3421 (slave) pulls-down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. During reads, the Master (microcontroller) can terminate the current read operation by not providing an acknowledge bit on the last byte that has been clocked out from the MCP3421. In this case, the MCP3421 releases the SDA line to allow the master (microcontroller) to generate a STOP or repeated START condition. FIGURE 5-6: Data Transfer Sequence on the Serial Bus. SCL SDA (A) (B) (D) (D) (C) (A) START CONDITION ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION MCP3421 DS22003B-page 18 © 2006 Microchip Technology Inc. TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V, +3.3V or +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. Parameters Sym Min Typ Max Units Conditions Standard Mode Clock frequency fSCL 0 — 100 kHz Clock high time THIGH 4000 — — ns Clock low time TLOW 4700 — — ns SDA and SCL rise time (Note 1) TR — — 1000 ns From VIL to VIH SDA and SCL fall time (Note 1) TF — — 300 ns From VIH to VIL START condition hold time THD:STA 4000 — — ns After this period, the first clock pulse is generated. Repeated START condition setup time TSU:STA 4700 — — ns Only relevant for repeated Start condition Data hold time (Note 3) THD:DAT 0 — 3450 ns Data input setup time TSU:DAT 250 — — ns STOP condition setup time TSU:STO 4000 — — ns STOP condition hold time THD:STD 4000 — — ns Output valid from clock (Notes 2 and 3) TAA 0 — 3750 ns Bus free time TBUF 4700 — — ns Time between START and STOP conditions. Fast Mode Clock frequency TSCL 0 — 400 kHz Clock high time THIGH 600 — — ns Clock low time TLOW 1300 — — ns SDA and SCL rise time (Note 1) TR 20 + 0.1Cb — 300 ns From VIL to VIH SDA and SCL fall time (Note 1) TF 20 + 0.1Cb — 300 ns From VIH to VIL START condition hold time THD:STA 600 — — ns After this period, the first clock pulse is generated Repeated START condition setup time TSU:STA 600 — — ns Only relevant for repeated Start condition Data hold time (Note 4) THD:DAT 0 — 900 ns Data input setup time TSU:DAT 100 — — ns STOP condition setup time TSU:STO 600 — — ns STOP condition hold time THD:STD 600 — — ns Output valid from clock (Notes 2 and 3) TAA 0 — 1200 ns Bus free time TBUF 1300 — — ns Time between START and STOP conditions. Input filter spike suppression (Note 5) TSP 0 — 50 ns SDA and SCL pins Note 1: This parameter is ensured by characterization and not 100% tested. 2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). 3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. 4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. 5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode. © 2006 Microchip Technology Inc. DS22003B-page 19 MCP3421 High Speed Mode Clock frequency fSCL 0 — 3.4 1.7 MHz MHz Cb = 100 pF Cb = 400 pF Clock high time THIGH 60 120 — — ns ns Cb = 100 pF Cb = 400 pF Clock low time TLOW 160 320 — — ns Cb = 100 pF Cb = 400 pF SCL rise time (Note 1) TR — — 40 80 ns From VIL to VIH,Cb = 100 pF Cb = 400 pF SCL fall time (Note 1) TF — — 40 80 ns From VIH to VIL,Cb = 100 pF Cb = 400 pF SDA rise time (Note 1) TR: DAT — — 80 160 ns From VIL to VIH,Cb = 100 pF Cb = 400 pF SDA fall time (Note 1) TF: DATA — — 80 160 ns From VIH to VIL,Cb = 100 pF Cb = 400 pF START condition hold time THD:STA 160 — — ns After this period, the first clock pulse is generated Repeated START condition setup time TSU:STA 160 — — ns Only relevant for repeated Start condition Data hold time (Note 4) THD:DAT 00 — 70 150 ns Cb = 100 pF Cb = 400 pF Data input setup time TSU:DAT 10 — — ns STOP condition setup time TSU:STO 160 — — ns STOP condition hold time THD:STD 160 — — ns Output valid from clock (Notes 2 and 3) TAA — — 150 310 ns Cb = 100 pF Cb = 400 pF Bus free time TBUF 160 — — ns Time between START and STOP conditions. Input filter spike suppression (Note 5) TSP 0 — 10 ns SDA and SCL pins TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V, +3.3V or +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. Parameters Sym Min Typ Max Units Conditions Note 1: This parameter is ensured by characterization and not 100% tested. 2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). 3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. 4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. 5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode. MCP3421 DS22003B-page 20 © 2006 Microchip Technology Inc. FIGURE 5-7: I2C Bus Timing Data. TF SCL SDA TSU:STA TSP THD:STA TLOW THIGH THD:DAT TAA TSU:DAT TR TSU:STO TBUF © 2006 Microchip Technology Inc. DS22003B-page 21 MCP3421 6.0 BASIC APPLICATION CONFIGURATION The MCP3421 device can be used for various precision analog-to-digital converter applications. The device operates with very simple connections to the application circuit. The following sections discuss the examples of the device connections and applications. 6.1 Connecting to the Application Circuits 6.1.1 INPUT VOLTAGE RANGE The fully differential input signals can be connected to the VIN+ and VIN- input pins. The input range should be within absolute common mode input voltage range: VSS - 0.3V to VDD + 0.3V. Outside this limit, the ESD protection diode at the input pin begins to conduct and the error due to input leakage current increases rapidly. Within this limit, the differential input VIN (= VIN+ - VIN-) is boosted by the PGA before a conversion takes place. The MCP3421 can not accept negative input voltages on the input pins. Figures 6-1 and 6-2 show typical connection examples for differential inputs and a singleended input, respectively. For the single-ended input, the input signal is applied to one of the input pins (typically connected to the VIN+ pin) while the other input pin (typically VIN- pin) is grounded. The input signal range of the single-ended configuration is from 0V to 2.048V. All device characteristics hold for the single-ended configuration, but this configuration loses one bit resolution because the input can only stand in positive half scale. Refer to Section 1.0 “Electrical Characteristics”. 6.1.2 BYPASS CAPACITORS ON VDD PIN For accurate measurement, the application circuit needs a clean supply voltage and must block any noise signal to the MCP3421 device. Figure 6-1 shows an example of using two bypass capacitors (a 10 μF tantalum capacitor and a 0.1 μF ceramic capacitor) in parallel on the VDD line. These capacitors are helpful to filter out any high frequency noises on the VDD line and also provide the momentary bursts of extra currents when the device needs from the supply. These capacitors should be placed as close to the VDD pin as possible (within one inch). If the application circuit has separate digital and analog power supplies, the VDD and VSS of the MCP3421 should reside on the analog plane. 6.1.3 CONNECTING TO I2C BUS USING PULL-UP RESISTORS The SCL and SDA pins of the MCP3421 are open-drain configurations. These pins require a pull-up resistor as shown in Figure 6-1. The value of these pull-up resistors depends on the operating speed (standard, fast, and high speed) and loading capacitance of the I2C bus line. Higher value of pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus. Therefore, it can limit the bus operating speed. The lower value of resistor, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long bus line or high number of devices connected to the bus, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1 kΩ and 10 kΩ ranges for standard and fast modes, and less than 1 kΩ for high speed mode in high loading capacitance environments. FIGURE 6-1: Typical Connection Example for Differential Inputs. FIGURE 6-2: Typical Connection Example for Single-Ended Input. The number of devices connected to the bus is limited only by the maximum bus capacitance of 400 pF. The bus loading capacitance affects on the bus operating speed. For example, the highest bus operating speed for the 400 pF bus capacitance is 1.7 MHz, and 3.4 MHz for 100 pF. Figure 6-3 shows an example of multiple device connections. MCP3421 VIN+ VINVSS VDD 1 2 3 4 5 6 SCL SDL 0.1 μF 10 μF R R Input Signals VDD VDD TO MCU Note: R is the pull-up resistor. (MASTER) MCP3421 VIN+ VINVSS VDD 1 2 3 4 5 6 SCL SDL 0.1 μF 10 μF R R Input Signals VDD VDD TO MCU Note: R is the pull-up resistor. (MASTER) MCP3421 DS22003B-page 22 © 2006 Microchip Technology Inc. FIGURE 6-3: Example of Multiple Device Connection on I2C Bus. 6.2 Device Connection Test The user can test the presence of the MCP3421 on the I2C bus line without performing an input data conversion. This test can be achieved by checking an acknowledge response from the MCP3421 after sending a read or write command. Here is an example using Figure 6-4: (a) Set the R/W bit “HIGH” in the address byte. (b) The MCP3421 will then acknowledge by pulling SDA bus LOW during the ACK clock and then release the bus back to the I2C Master. (c) A STOP or repeated START bit can then be issued from the Master and I2C communication can continue. FIGURE 6-4: I2C Bus Connection Test. 6.3 Application Examples The MCP3421 device can be used in a broad range of sensor and data acquisition applications. Figure 6-5, shows an example of interfacing with a bridge sensor for pressure measurement. FIGURE 6-5: Example of Pressure Measurement. In this circuit example, the sensor full scale range is ±7.5 mV with a common mode input voltage of VDD / 2. This configuration will provide a full 14-bit resolution across the sensor output range. The alternative circuit for this amount of accuracy would involve an analog gain stage prior to a 16-bit ADC. Figure 6-6 shows an example of temperature measurement using a thermistor. This example can achieve a linear response over a 50°C temperature range. This can be implemented using a standard resistor with 1% tolerance in series with the thermistor. The value of the resistor is selected to be equal to the thermistor value at the mid-point of the desired temperature range. FIGURE 6-6: Example of Temperature Measurement. SDASCL (24LC01) Microcontroller EEPROM MCP3421 (TC74) Temperature Sensor (PIC16F876) SCL 1 2 3 4 5 6 7 8 9 SDA 1 1 0 1 A2 A1 A0 1 Start Bit Address Byte Device bits Address bits R/W Start Bit MCP3421 ACK Response NPP301 MCP3421 VIN+ VINVSS VDD 1 2 3 4 5 6 SCL SDL 0.1 μF 10 μF R R VDD VDD TO MCU (MASTER) VDD 10 kΩ Resistor 10 kΩ Thermistor MCP3421 VIN+ VINVSS VDD 1 2 3 4 5 6 SCL SDL 0.1 μF 10 μF R R VDD VDD TO MCU (MASTER) VDD © 2006 Microchip Technology Inc. DS22003B-page 23 MCP3421 7.0 PACKAGING INFORMATION 7.1 Package Marking Information Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e3 e3 2 5 3 1 4 6 6-Lead SOT-23 XXNN 2 5 3 1 4 6 Example CA25 MCP3421 DS22003B-page 24 © 2006 Microchip Technology Inc. 6-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 1 D B n E E1 L c β φ α A A2 A1 p1 Mold Draft Angle Bottom β 0 5 10 0 5 10 Mold Draft Angle Top α 0 5 10 0 5 10 Lead Width B .014 .017 .020 0.35 0.43 0.50 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Foot Angle φ 0 5 10 0 5 10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Overall Length D .110 .116 .122 2.80 2.95 3.10 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Width E .102 .110 .118 2.60 2.80 3.00 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Overall Height A .035 .046 .057 0.90 1.18 1.45 Outside lead pitch p1 .075 BSC 1.90 BSC Pitch p .038 BSC 0.95 BSC Number of Pins n 6 6 Dimension Limits MIN NOM MAX MIN NOM MAX Units INCHES* MILLIMETERS Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. Notes: JEITA (formerly EIAJ) equivalent: SC-74A * Controlling Parameter Drawing No. C04-120 BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M Revised 09-12-05 © 2006 Microchip Technology Inc. DS22003B-page 27 MCP3421 APPENDIX A: REVISION HISTORY Revision B (December 2006) • Changes to Electrical Characteristics tables • Added characterization data • Changes to I2C Serial Timing Specification table • Change to Figure 5-7. Revision A (August 2006) • Original Release of this Document. MCP3421 DS22003B-page 28 © 2006 Microchip Technology Inc. NOTES: © 2006 Microchip Technology Inc. DS22003B-page 29 MCP3421 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: MCP3421T: Single Channel ΔΣ A/D Converter (Tape and Reel) Address Options: XX A2 A1 A0 A0 * = 0 0 0 A1 = 0 0 1 A2 = 0 1 0 A3 = 0 1 1 A4 = 1 0 0 A5 = 1 0 1 A6 = 1 1 0 A7 = 1 1 1 * Default option. Contact Microchip factory for other address options Temperature Range: E = -40°C to +125°C Package: OT = Plastic Small Outline Transistor (SOT-23-6), 6-lead Examples: a) MCP3421A0T-E/OT: Tape and Reel, Single Channel ΔΣ A/D Converter, SOT-23-6 package. PART NO. XX X Address Temperature Range Device /XX Package Options MCP3421 DS22003B-page 30 © 2006 Microchip Technology Inc. NOTES: © 2006 Microchip Technology Inc. DS22003B-page 31 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS22003B-page 32 © 2006 Microchip Technology Inc. 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DS22003B-page 1 MCP3421 Features • 18-bit ΔΣ ADC in a SOT-23-6 package • Differential input operation • Self calibration of Internal Offset and Gain per each conversion • On-board Voltage Reference: - Accuracy: 2.048V ± 0.05% - Drift: 5 ppm/°C • On-board Programmable Gain Amplifier (PGA): - Gains of 1,2,4 or 8 • On-board Oscillator • INL: 10 ppm of FSR (FSR = 4.096V/PGA) • Programmable Data Rate Options: - 3.75 SPS (18 bits) - 15 SPS (16 bits) - 60 SPS (14 bits) - 240 SPS (12 bits) • One-Shot or Continuous Conversion Options • Low current consumption: - 145 μA typical (VDD= 3V, Continuous Conversion) - 39 μA typical (VDD= 3V, One-Shot Conversion with 1 SPS) • Supports I2C Serial Interface: - Standard, Fast and High Speed Modes • Single Supply Operation: 2.7V to 5.5V • Extended Temperature Range: -40°C to 125°C Typical Applications • Portable Instrumentation • Weigh Scales and Fuel Gauges • Temperature Sensing with RTD, Thermistor, and Thermocouple • Bridge Sensing for Pressure, Strain, and Force. Package Types Description The MCP3421 is a single channel low-noise, high accuracy ΔΣ A/D converter with differential inputs and up to 18 bits of resolution in a small SOT-23-6 package. The on-board precision 2.048V reference voltage enables an input range of ±2.048V differentially (Δ voltage = 4.096V). The device uses a two-wire I2C compatible serial interface and operates from a single 2.7V to 5.5V power supply. The MCP3421 device performs conversion at rates of 3.75, 15, 60, or 240 samples per second (SPS) depending on the user controllable configuration bit settings using the two-wire I2C serial interface. This device has an on-board programmable gain amplifier (PGA). The user can select the PGA gain of x1, x2, x4, or x8 before the analog-to-digital conversion takes place. This allows the MCP3421 device to convert a smaller input signal with high resolution. The device has two conversion modes: (a) Continuous mode and (b) One-Shot mode. In One-Shot mode, the device enters a low current standby mode automatically after one conversion. This reduces current consumption greatly during idle periods. The MCP3421 device can be used for various high accuracy analog-to-digital data conversion applications where design simplicity, low power, and small footprint are major considerations. Block Diagram 1 2 3 4 5 VIN+ 6 VSS SCL VINVDD SDA SOT-23-6 Top View VSS VDD VIN+ VINSCL SDA Voltage Reference Clock (2.048V) I2C Interface Gain = 1, 2, 4, or 8 VREF ΔΣ ADC PGA Converter Oscillator 18-Bit Analog-to-Digital Converter with I2C Interface and On-Board Reference MCP3421 DS22003B-page 2 © 2006 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD...................................................................................7.0V All inputs and outputs w.r.t VSS ............... –0.3V to VDD+0.3V Differential Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current .................................Continuous Current at Input Pins ....................................................±2 mA Current at Output and Supply Pins ............................±10 mA Storage Temperature.....................................-65°C to +150°C Ambient Temp. with power applied ...............-55°C to +125°C ESD protection on all pins ................ ≥ 6 kV HBM, ≥ 400V MM Maximum Junction Temperature (TJ) ..........................+150°C †Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range. Parameters Sym Min Typ Max Units Conditions Analog Inputs Differential Input Range — ±2.048/PGA — V VIN = VIN+ - VINCommon- Mode Voltage Range (absolute) (Note 1) VSS-0.3 — VDD+0.3 V Differential Input Impedance (Note 2) ZIND (f) — 2.25/PGA — MΩ During normal mode operation Common Mode input Impedance ZINC (f) — 25 — MΩ PGA = 1, 2, 4, 8 System Performance Resolution and No Missing Codes (Note 8) 12 — — Bits DR = 240 SPS 14 — — Bits DR = 60 SPS 16 — — Bits DR = 15 SPS 18 — — Bits DR = 3.75 SPS Data Rate (Note 3) DR 176 240 328 SPS S1,S0 = ‘00’, (12 bits mode) 44 60 82 SPS S1,S0 = ‘01’, (14 bits mode) 11 15 20.5 SPS S1,S0 = ‘10’, (16 bits mode) 2.75 3.75 5.1 SPS S1,S0 = ‘11’, (18 bits mode) Output Noise — 1.5 — μVRMS TA = 25°C, DR = 3.75 SPS, PGA = 1, VIN = 0 Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. 2: This input impedance is due to 3.2 pF internal input sampling capacitor. 3: The total conversion speed includes auto-calibration of offset and gain. 4: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 5: Includes all errors from on-board PGA and VREF. 6: Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA. 7: This parameter is ensured by characterization and not 100% tested. 8: This parameter is ensured by design and not 100% tested. © 2006 Microchip Technology Inc. DS22003B-page 3 MCP3421 Integral Nonlinearity (Note 4) INL — 10 35 ppm of FSR DR = 3.75 SPS (Note 6) Internal Reference Voltage VREF — 2.048 — V Gain Error (Note 5) — 0.05 0.35 % PGA = 1, DR = 3.75 SPS PGA Gain Error Match (Note 5) — 0.1 — % Between any 2 PGA gains Gain Error Drift (Note 5) — 5 40 ppm/°C PGA=1, DR=3.75 SPS Offset Error VOS — 15 40 μV Tested at PGA = 1 VDD = 5.0V and DR = 3.75 SPS Offset Drift vs. Temperature — 50 — nV/°C VDD = 5.0V Common-Mode Rejection — 105 — dB at DC and PGA =1, — 110 — dB at DC and PGA =8, TA = +25°C Gain vs. VDD — 5 — ppm/V TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 Power Supply Rejection at DC — 100 — dB TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 Power Requirements Voltage Range VDD 2.7 — 5.5 V Supply Current during Conversion IDDA — 155 190 μA VDD = 5.0V — 145 — μA VDD = 3.0V Supply Current during Standby Mode IDDS — 0.1 0.5 μA I2C Digital Inputs and Digital Outputs High level input voltage VIH 0.7 VDD — VDD V Low level input voltage VIL — — 0.3VDD V Low level output voltage VOL — — 0.4 V IOL = 3 mA, VDD = +5.0V Hysteresis of Schmitt Trigger for inputs (Note 7) VHYST 0.05VDD — — V fSCL = 100 kHz Supply Current when I2C bus line is active IDDB — — 10 μA Input Leakage Current IILH — — 1 μA VIH = 5.5V IILL -1 — — μA VIL = GND Pin Capacitance and I2C Bus Capacitance Pin capacitance CPIN — — 10 pF I2C Bus Capacitance Cb — — 400 pF Thermal Characteristics Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range. Parameters Sym Min Typ Max Units Conditions Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. 2: This input impedance is due to 3.2 pF internal input sampling capacitor. 3: The total conversion speed includes auto-calibration of offset and gain. 4: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 5: Includes all errors from on-board PGA and VREF. 6: Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA. 7: This parameter is ensured by characterization and not 100% tested. 8: This parameter is ensured by design and not 100% tested. MCP3421 DS22003B-page 4 © 2006 Microchip Technology Inc. 2.0 TYPICAL PERFORMANCE CURVES Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. FIGURE 2-1: INL vs. Supply Voltage (VDD). FIGURE 2-2: INL vs. Temperature. FIGURE 2-3: Offset Error vs. Temperature. FIGURE 2-4: Noise vs. Input Voltage. FIGURE 2-5: Total Error vs. Input Voltage. FIGURE 2-6: Gain Error vs. Temperature. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. .000 .001 .002 .003 .004 .005 2.5 3 3.5 4 4.5 5 5.5 VDD (V) PGA = 1 PGA = 2 PGA = 8 PGA = 4 Integral Nonlinearity (% of FSR) 0 0.001 0.002 0.003 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) Integral Nonlinearity (% of FSR) VDD = 5 V VDD = 2.7V PGA = 1 -20 -15 -10 -5 0 5 10 15 20 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Offset Error (μV) VDD = 5V PGA = 1 PGA = 2 PGA = 4 PGA = 8 0.0 2.5 5.0 7.5 10.0 -100 -75 -50 -25 0 25 50 75 100 Input Voltage (% of Full-Scale) Noise (μV, rms) PGA = 1 PGA = 2 PGA = 8 PGA = 4 TA = +25°C VDD = 5V -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 -100 -75 -50 -25 0 25 50 75 100 Input Voltage (% of Full-Scale) Total Error (mV) PGA = 1 PGA = 2 PGA = 8 PGA = 4 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Gain Error (% of FSR) VDD = 5.0V PGA = 1 PGA = 2 PGA = 8 PGA = 4 © 2006 Microchip Technology Inc. DS22003B-page 5 MCP3421 Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. FIGURE 2-7: IDDA vs. Temperature. FIGURE 2-8: IDDS vs. Temperature. FIGURE 2-9: IDDB vs. Temperature. FIGURE 2-10: OSC Drift vs. Temperature. FIGURE 2-11: Frequency Response. 100 120 140 160 180 200 220 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) IDDA (μA) VDD = 5V VDD = 2.7V 0 100 200 300 400 500 600 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) IDDS (nA) VDD = 2.7V VDD = 5V 0 1 2 3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) IDDB (􀁐A) VDD = 5V VDD = 4.5V VDD = 3.3V VDD = 2.7V -1 0 1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Oscillator Drift (%) VDD = 5.0V VDD = 2.7V Data Rate = 3.75 SPS -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.1 1 10 100 1000 10000 Input Signal Frequency (Hz) Magnitude (dB) 0.1 1 10 100 1k 10k MCP3421 DS22003B-page 6 © 2006 Microchip Technology Inc. 3.0 PIN DESCRIPTIONS TABLE 3-1: PIN FUNCTION TABLE 3.1 Analog Inputs (VIN+, VIN-) VIN+ and VIN- are differential signal input pins. The MCP3421 device accepts a fully differential analog input signal which is connected on the VIN+ and VINinput pins. The differential voltage that is converted is defined by VIN = (VIN+ - VIN-) where VIN+ is the voltage applied at the VIN+ pin and VIN- is the voltage applied at the VIN- pin. The input signal level is amplified by the programmable gain amplifier (PGA) before the conversion. The differential input voltage should not exceed an absolute of (2* VREF/PGA) for accurate measurement, where VREF is the internal reference voltage (2.048V) and PGA is the PGA gain setting. The converter output code will saturate if the input range exceeds (2* VREF/PGA). The absolute voltage range on each of the differential input pins is from VSS-0.3V to VDD+0.3V. Any voltage above or below this range will cause leakage currents through the Electrostatic Discharge (ESD) diodes at the input pins. This ESD current can cause unexpected performance of the device. The common mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in Section 1.0 “Electrical Characteristics” and Section 4.0 “Description of Device Operation”. 3.2 Supply Voltage (VDD, VSS) VDD is the power supply pin for the device. This pin requires an appropriate bypass capacitor of about 0.1 μF (ceramic) to ground. An additional 10 μF capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in some application boards. The supply voltage (VDD) must be maintained in the 2.7V to 5.5V range for specified operation. VSS is the ground pin and the current return path of the device. The user must connect the VSS pin to a ground plane through a low impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.3 Serial Clock Pin (SCL) SCL is the serial clock pin of the I2C interface. The MCP3421 acts only as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the MCP3421 occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SCL pin. Refer to Section 5.3 “I2C Serial Communications” for more details of I2C Serial Interface communication. 3.4 Serial Data Pin (SDA) SDA is the serial data pin of the I2C interface. The SDA pin is used for input and output data. In read mode, the conversion result is read from the SDA pin (output). In write mode, the device configuration bits are written (input) though the SDA pin. The SDA pin is an opendrain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SDA pin. Except for start and stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 5.3 “I2C Serial Communications” for more details of I2C Serial Interface communication. Pin No Sym Function 1 VIN+ Non-Inverting Analog Input Pin 2 VSS Ground Pin 3 SCL Serial Clock Input Pin of the I2C Interface 4 SDA Bidirectional Serial Data Pin of the I2C Interface 5 VDD Positive Supply Voltage Pin 6 VIN- Inverting Analog Input Pin © 2006 Microchip Technology Inc. DS22003B-page 7 MCP3421 4.0 DESCRIPTION OF DEVICE OPERATION 4.1 General Overview The MCP3421 is a low-power, 18-Bit Delta-Sigma A/D converter with an I2C serial interface. The device contains an on-board voltage reference (2.048V), programmable gain amplifier (PGA), and internal oscillator. The user can select 12, 14, 16, or 18 bit conversion by setting the configuration register bits. The device can be operated in Continuous Conversion or One-Shot Conversion mode. In the Continuous Conversion mode, the device converts the inputs continuously. While in the One-Shot Conversion mode, the device converts the input one time and stays in the low-power standby mode until it receives another command for a new conversion. During the standby mode, the device consumes less than 0.1 μA typical. 4.2 Power-On-Reset (POR) The device contains an internal Power-On-Reset (POR) circuit that monitors power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. The POR has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. A 0.1 μF decoupling capacitor should be mounted as close as possible to the VDD pin for additional transient immunity. The threshold voltage is set at 2.2V with a tolerance of approximately ±5%. If the supply voltage falls below this threshold, the device will be held in a reset condition. The typical hysteresis value is approximately 200 mV. The POR circuit is shut-down during the low-power standby mode. Once a power-up event has occurred, the device requires additional delay time (approximately 300 μs) before a conversion can take place. During this time, all internal analog circuitries are settled before the first conversion occurs. Figure 4-1 illustrates the conditions for power-up and power-down events under typical start-up conditions. When the device powers up, it automatically resets and sets the configuration bits to default settings. The default configuration bit conditions are a PGA gain of 1 V/V and a conversion speed of 240 SPS in Continuous Conversion mode. When the device receives an I2C General Call Reset command, it performs an internal reset similar to a Power-On-Reset event. FIGURE 4-1: POR Operation. 4.3 Internal Voltage Reference The device contains an on-board 2.048V voltage reference. This reference voltage is for internal use only and not directly measurable. The specifications of the reference voltage are part of the device’s gain and drift specifications. Therefore, there is no separate specification for the on-board reference. 4.4 Analog Input Channel The differential analog input channel has a switched capacitor structure. The internal sampling capacitor (3.2 pF) is charged and discharged to process a conversion. The charging and discharging of the input sampling capacitor creates dynamic input currents at the VIN+ and VIN- input pins, which is inversely proportional to the internal sampling capacitor and internal frequency. The current is also a function of the differential input voltages. Care must be taken in setting the common-mode voltage and input voltage ranges so that the input limits do not exceed the ranges specified in Section 1.0 “Electrical Characteristics”. 4.5 Digital Output Code The digital output code produced by the MCP3421 is a function of PGA gain, input signal, and internal reference voltage. In a fixed setting, the digital output code is proportional to the voltage difference between the two analog inputs. The output data format is a binary two’s complement. With this code scheme, the MSB can be considered a sign indicator. When the MSB is a logic ‘0’, it indicates a positive value. When the MSB is a logic ‘1’, it indicates a negative value. The following is an example of the output code: (a) for a negative full-scale input voltage: 100...000 (b) for a zero differential input voltage: 000...000 (c) for a positive full-scale input voltage: 011...111. The MSB is always transmitted first through the serial port. The number of data bits for each conversion is 18, 16, 14, or 12 bits depending on the conversion mode selection. VDD 2.2V 2.0V 300 μS Reset Start-up Normal Operation Reset Time MCP3421 DS22003B-page 8 © 2006 Microchip Technology Inc. The output codes will not roll-over if the input voltage exceeds the maximum input range. In this case, the code will be locked at 0111...11 for all voltages greater than +(VREF - 1 LSB) and 1000...00 for voltages less than -VREF. Table 4-2 shows an example of output codes of various input levels using 18 bit conversion mode. Table 4-3 shows an example of minimum and maximum codes for each data rate option. The output code is given by: EQUATION 4-1: The LSB of the code is given by: EQUATION 4-2: TABLE 4-1: LSB SIZE OF VARIOUS BIT CONVERSION MODES TABLE 4-2: EXAMPLE OF OUTPUT CODE FOR 18 BITS TABLE 4-3: MINIMUM AND MAXIMUM CODES 4.6 Self-Calibration The device performs a self-calibration of offset and gain for each conversion. This provides reliable conversion results from conversion-to-conversion over variations in temperature as well as power supply fluctuations. 4.7 Input Impedance The MCP3421 uses a switched-capacitor input stage using a 3.2 pF sampling capacitor. This capacitor is switched (charged and discharged) at a rate of the sampling frequency that is generated by the on-board clock. The differential mode impedance varies with the PGA settings. The typical differential input impedance during a normal mode operation is given by: Since the sampling capacitor is only switching to the input pins during a conversion process, the above input impedance is only valid during conversion periods. In a low power standby mode, the above impedance is not presented at the input pins. Therefore, only a leakage current due to ESD diode is presented at the input pins. The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can increase the system performance errors such as offset, gain, and integral nonlinearity (INL) errors. Ideally, the input source impedance should be zero. This can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms. Bit Resolutions LSB (V) 12 bits 1 mV 14 bits 250 μV 16 bits 62.5 μV 18 bits 15.625 μV Input Voltage (V) Digital Code ≥ VREF 011111111111111111 VREF - 1 LSB 011111111111111111 2 LSB 000000000000000010 1 LSB 000000000000000001 0 000000000000000000 -1 LSB 111111111111111111 -2 LSB 111111111111111110 - VREF 100000000000000000 < -VREF 100000000000000000 Output Code (Max Code + 1) (VIN+ – VIN-) 2.048V = × -------------------------------------- LSB 2 × 2.048V 2N = -------------------------- Where: N = the number of bits Number of Bits Data Rate Minimum Code Maximum Code 12 240 SPS -2048 2047 14 60 SPS -8192 8191 16 15 SPS -32768 32767 18 3.75 SPS -131072 131071 Note: Maximum n-bit code = 2n-1 - 1 Minimum n-bit code = -1 x 2n-1 ZIN(f) = 2.25 MΩ/PGA © 2006 Microchip Technology Inc. DS22003B-page 9 MCP3421 4.8 Aliasing and Anti-aliasing Filter Aliasing occurs when the input signal contains timevarying signal components with frequency greater than half the sample rate. In the aliasing conditions, the device can output unexpected output codes. For applications that are operating in electrical noise environments, the time-varying signal noise or high frequency interference components can be easily added to the input signals and cause aliasing. Although the MCP3421 device has an internal first order sinc filter, its’ filter response may not give enough attenuation to all aliasing signal components. To avoid the aliasing, an external anti-aliasing filter, which can be accomplished with a simple RC low-pass filter, is typically used at the input pins. The low-pass filter cuts off the high frequency noise components and provides a band-limited input signal to the MCP3421 input pins. MCP3421 DS22003B-page 10 © 2006 Microchip Technology Inc. 5.0 USING THE MCP3421 DEVICE 5.1 Operating Modes The user operates the device by setting up the device configuration register and reads the conversion data using serial I2C interface commands. The MCP3421 operates in two modes: (a) Continuous Conversion Mode or (b) One-Shot Conversion Mode (single conversion). The selection is made by setting the O/C bit in the Configuration Register. Refer to Section 5.2 “Configuration Register” for more information. 5.1.1 CONTINUOUS CONVERSION MODE (O/C BIT = 1) The MCP3421 device performs a Continuous Conversion if the O/C bit is set to logic “high”. Once the conversion is completed, the result is placed at the output data register. The device immediately begins another conversion and overwrites the output data register with the most recent data. The device also clears the data ready flag (RDY bit = 0) when the conversion is completed. The device sets the ready flag bit (RDY bit = 1), if the latest conversion result has been read by the Master. 5.1.2 ONE-SHOT CONVERSION MODE (O/C BIT = 0) Once the One-Shot Conversion (single conversion) Mode is selected, the device performs a conversion, updates the Output Data register, clears the data ready flag (RDY = 0), and then enters a low power standby mode. A new One-Shot Conversion is started again when the device receives a new write command with RDY = 1. This One-Shot Conversion Mode is recommended for low power operating applications. During the low current standby mode, the device consumes less than 1 μA typical. For example, if user collects 18 bit conversion data once a second in One-Shot Conversion mode, the device draws only about one fourth of its total operating current. In this example, the device consumes approximately 39 μA (= ~145 μA/3.75 SPS), if the device performs only one conversion per second (1 SPS) in 18-bit conversion mode with 3V power supply. © 2006 Microchip Technology Inc. DS22003B-page 11 MCP3421 5.2 Configuration Register The MCP3421 has an 8-bit wide configuration register to select for: PGA gain, conversion rate, and conversion mode. This register allows the user to change the operating condition of the device and check the status of the device operation. The user can rewrite the configuration byte any time during the device operation. Register 5-1 shows the configuration register bits. REGISTER 5-1: CONFIGURATION REGISTER R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 RDY C1 C0 O/C S1 S0 G1 G0 1 * 0 * 0 * 1 * 0 * 0 * 0 * 0 * bit 7 bit 0 * Default Configuration after Power-On Reset Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDY: Ready Bit This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated with a new conversion. In One-Shot Conversion mode, writing this bit to “1” initiates a new conversion. Reading RDY bit with the read command: 1 = Output register has not been updated. 0 = Output register has been updated with the latest conversion data. Writing RDY bit with the write command: Continuous Conversion mode: No effect One-Shot Conversion mode: 1 = Initiate a new conversion. 0 = No effect. bit 6-5 C1-C0: Channel Selection Bits These are the Channel Selection bits, but not used in the MCP3421 device. bit 4 O/C: Conversion Mode Bit 1 = Continuous Conversion Mode. Once this bit is selected, the device performs data conversions continuously. 0 = One-Shot Conversion Mode. The device performs a single conversion and enters a low power standby mode until it receives another write/read command. bit 3-2 S1-S0: Sample Rate Selection Bit 00 = 240 SPS (12 bits), 01 = 60 SPS (14 bits), 10 = 15 SPS (16 bits), 11 = 3.75 SPS (18 bits) bit 1-0 G1-G0: PGA Gain Selector Bits 00 = 1 V/V, 01 = 2 V/V, 10 = 4 V/V, 11 = 8 V/V MCP3421 DS22003B-page 12 © 2006 Microchip Technology Inc. In read mode, the RDY bit in the configuration byte indicates the state of the conversion: (a) RDY = 1 indicates that the data bytes that have just been read were not updated from the previous conversion. (b) RDY = 0 indicates that the data bytes that have just been read were updated. If the configuration byte is read repeatedly by clocking continuously after the first read (i.e., after the 5th byte in the 18-bit conversion mode), the state of the RDY bit indicates whether the device is ready with new conversion data. See Figure 5-2. For example, RDY = 0 means new conversion data is ready for reading. In this case, the user can send a stop bit to exit the current read operation and send a new read command to read out updated conversion data. See Figures 5-2 and 5-3 for reading conversion data. The user can rewrite the configuration byte any time for a new setting. Tables 5-1 and 5-2 show the examples of the configuration bit operation. 5.3 I2C Serial Communications The MCP3421 device communicates with Master (microcontroller) through a serial I2C (Inter-Integrated Circuit) interface and supports standard (100 kbits/sec), fast (400 kbits/sec) and high-speed (3.4 Mbits/sec) modes. The serial I2C is a bidirectional 2-wire data bus communication protocol using opendrain SCL and SDA lines. The MCP3421 can only be addressed as a slave. Once addressed, it can receive configuration bits or transmit the latest conversion results. The serial clock pin (SCL) is an input only and the serial data pin (SDA) is bidirectional. An example of a hardware connection diagram is shown in Figure 6-1. The Master starts communication by sending a START bit and terminates the communication by sending a STOP bit. The first byte after the START bit is always the address byte of the device, which includes the device code, the address bits, and the R/W bit. The device code for the MCP3421 device is 1101. The address bits (A2, A1, A0) are pre-programmed at the factory. In general, the address bits are specified by the customer when they order the device. The three address bits are programmed to “000” at the factory, if they are not specified by the customer. Figure 5-1 shows the details of the MCP3421 address byte. During a low power standby mode, SDA and SCL pins remain at a floating condition. More details of the I2C bus characteristic is described in Section 5.6 “I2C Bus Characteristics”. 5.3.1 DEVICE ADDRESSING The address byte is the first byte received following the START condition from the Master device. The MCP3421 device code is 1101. The device code is followed by three address bits (A2, A1, A0) which are programmed at the factory. The three address bits allow up to eight MCP3421 devices on the same data bus line. The (R/W) bit determines if the Master device wants to read the conversion data or write to the Configuration register. If the (R/W) bit is set (read mode), the MCP3421 outputs the conversion data in the following clocks. If the (R/W) bit is cleared (write mode), the MCP3421 expects a configuration byte in the following clocks. When the MCP3421 receives the correct address byte, it outputs an acknowledge bit after the R/W bit. Figure 5-1 shows the MCP3421 address byte. See Figures 5-2 and 5-3 for the read and write operations of the device. TABLE 5-1: CONFIGURATION BITS FOR WRITING R/W O/C RDY Operation 0 0 0 No effect if all other bits remain the same - operation continues with the previous settings 0 0 1 Initiate One-Shot Conversion 0 1 0 Initiate Continuous Conversion 0 1 1 Initiate Continuous Conversion TABLE 5-2: CONFIGURATION BITS FOR READING R/W O/C RDY Operation 1 0 0 New conversion data in One- Shot conversion mode has been just read. The RDY bit remains low until set by a new write command. 1 0 1 One-Shot Conversion is in progress, The conversion data is not updated yet. The RDY bit stays high. 1 1 0 New conversion data in Continuous Conversion mode has been just read. The RDY bit changes to high after this read. 1 1 1 The conversion data in Continuous Conversion mode was already read. The latest conversion data is not ready. The RDY bit stays high until a new conversion is completed. © 2006 Microchip Technology Inc. DS22003B-page 13 MCP3421 FIGURE 5-1: MCP3421 Address Byte. 5.3.2 READING DATA FROM THE DEVICE When the Master sends a read command (R/W = 1), the MCP3421 outputs the conversion data bytes and configuration byte. Each byte consists of 8 bits with one acknowledge (ACK) bit. The ACK bit after the address byte is issued by the MCP3421 and the ACK bits after each conversion data bytes are issued by the Master. When the device is configured for 18-bit conversion mode, the device outputs three data bytes followed by a configuration byte. The first 7 data bits in the first data byte are the MSB of the conversion data. The user can ignore the first 6 data bits, and take the 7th data bit (D17) as the MSB of the conversion data. The LSB of the 3rd data byte is the LSB of the conversion data (D0). If the device is configured for 12, 14, or 16 bit-mode, the device outputs two data bytes followed by a configuration byte. In 16 bit-conversion mode, the MSB of the first data byte is the MSB (D15) of the conversion data. In 14-bit conversion mode, the first two bits in the first data byte can be ignored (they are the MSB of the conversion data), and the 3rd bit (D13) is the MSB of the conversion data. In 12-bit conversion mode, the first four bits can be ignored (they are the MSB of the conversion data), and the 5th bit (D11) of the byte represents the MSB of the conversion data. Table 5-3 shows an example of the conversion data output of each conversion mode. The configuration byte follows the output data byte. The device outputs the configuration byte as long as the SCL pulses are received. The device terminates the current outputs when it receives a Not-Acknowledge (NAK), a repeated start or a stop bit at any time during the output bit stream. It is not required to read the configuration byte. However, the user may read the configuration byte to check the RDY bit condition to confirm whether the just received data bytes are updated conversion data. The user may continuously send clock (SCL) to repeatedly read the configuration bytes to check the RDY bit status. Figures 5-2 and 5-3 show the timing diagrams of the reading. 5.3.3 WRITING A CONFIGURATION BYTE TO THE DEVICE When the Master sends an address byte with the R/W bit low (R/W = 0), the MCP3421 expects one configuration byte following the address. Any byte sent after this second byte will be ignored. The user can change the operating mode of the device by writing the configuration register bits. If the device receives a write command with a new configuration setting, the device immediately begins a new conversion and updates the conversion data. Start bit Read/Write bit Address Byte R/W ACK 1 1 0 1 X X X Device Code Address Bits (Note 1) Address Acknowledge bit Address Note 1: Specified by customer and programmed at the factory. If not specified by the customer, programmed to ‘000’. TABLE 5-3: EXAMPLE OF CONVERSION DATA OUTPUT OF EACH CONVERSION MODE Conversion Mode Conversion Data Output 18-bits MMMMMMMD16 (1st data byte) - D15 ~ D8 (2nd data byte) - D7 ~ D0 (3rd data byte) - Configuration byte 16-bits MD14~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte 14-bits MMMD12~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte 12-bits MMMMMD10D9D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte Note: M is MSB of the data byte. MCP3421 DS22003B-page 14 © 2006 Microchip Technology Inc. FIGURE 5-2: Timing Diagram For Reading From The MCP3421 With 18-Bit Mode. 1 9 1 9 1 9 1 9 1 9 1 9 1 1 0 1 A2 A1 A0 D ACK by RDY O/C MCP3421 7 Start Bit by R/W Master Repeat of D17 (MSB) 2nd Byte Upper Data Byte (Data on Clocks 1-6th can be ignored) ACK by Master ACK by Master ACK by Master ACK by Master 17 D 16 D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C1 C0 S1 S0 G1 G0 1st Byte MCP3421 Address Byte 3rd Byte Middle Data Byte 4th Byte Lower Data Byte 5th Byte Configuration Byte (Optional) C1 C0 S1 S0 G1 G0 NAK by Master Stop Bit by Master (Optional) Nth Repeated Byte: Configuration Byte Note: – MCP3421 device code is 1101. – Address Bits A2- A0 = 000 are programmed at the factory unless customer requests specific codes. – Stop bit or NAK bit can be issued any time during reading. – Data bits on clocks 1 - 6th in 2nd byte are repeated MSB and can be ignored. SCL SDA RDY O/C © 2006 Microchip Technology Inc. DS22003B-page 15 MCP3421 FIGURE 5-3: Timing Diagram For Reading From The MCP3421 With 12-Bit to 16-Bit Modes. 1 1 0 1 A2 A1 A0 ACK by MCP3421 Start Bit by Master 2nd Byte Middle Data Byte ACK by Master ACK by Master ACK by Master D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C1 C0 S1 S0 G1 G0 1st Byte MCP3421 Address Byte 3rd Byte Lower Data Byte 4th Byte Configuration Byte (Optional) C1 C0 S1 S0 G1 G0 NAK by Master Stop Bit by Master (Optional) Nth Repeated Byte: Configuration Byte Note: – MCP3421 device code is 1101. – Address Bits A2- A0 = 000 are programmed at the factory unless customer requests specific codes. – Stop bit or NAK bit can be issued any time during reading. – In 14 - bit mode: D15 and D14 are repeated MSB and can be ignored. – In 12 - bit mode: D15 - D12 are repeated MSB and can be ignored. 1 9 1 9 1 9 1 9 SCL SDA 1 9 R/W RDY O/C RDY O/C MCP3421 DS22003B-page 16 © 2006 Microchip Technology Inc. FIGURE 5-4: Timing Diagram For Writing To The MCP3421. 5.4 General Call The MCP3421 acknowledges the general call address (0x00 in the first byte). The meaning of the general call address is always specified in the second byte. Refer to Figure 5-5. The MCP3421 supports the following general calls: 5.4.1 GENERAL CALL RESET The general call reset occurs if the second byte is ‘00000110’ (06h). At the acknowledgement of this byte, the device will abort current conversion and perform an internal reset similar to a power-on-reset (POR). 5.4.2 GENERAL CALL CONVERSION The general call conversion occurs if the second byte is ‘00001000’ (08h). All devices on the bus initiate a conversion simultaneously. For the MCP3421 device, the configuration will be set to the One-Shot Conversion mode and a single conversion will be performed. The PGA and data rate settings are unchanged with this general call. FIGURE 5-5: General Call Address Format. For more information on the general call, or other I2C modes, please refer to the Phillips I2C specification. 1 9 1 9 Stop Bit by 1 1 0 1 A2 A1 A0 R/W ACK by MCP3421 RDY C1 C0 O/C S1 S0 G1 G0 1st Byte: 2nd Byte: Master ACK by MCP3421 MCP3421 Address Byte Configuration Byte Start Bit by Master with Write command Note: – Stop bit can be issued any time during writing. – MCP3421 device code is 1101. – Address Bits A2- A0 = 000 are programmed at factory unless customer requests different codes. SCL SDA Note: The I2C specification does not allow to use “00000000” (00h) in the second byte. LSB First Byte ACK 0 0 0 0 0 0 0 0 A x x x x x x x x A (General Call Address) Second Byte ACK © 2006 Microchip Technology Inc. DS22003B-page 17 MCP3421 5.5 High-Speed (HS) Mode The I2C specification requires that a high-speed mode device must be ‘activated’ to operate in high-speed mode. This is done by sending a special address byte of 00001XXX following the START bit. The XXX bits are unique to the High-Speed (HS) mode Master. This byte is referred to as the High-Speed (HS) Master Mode Code (HSMMC). The MCP3421 device does not acknowledge this byte. However, upon receiving this code, the MCP3421 switches on its HS mode filters and communicates up to 3.4 MHz on SDA and SCL. The device will switch out of the HS mode on the next STOP condition. For more information on the HS mode, or other I2C modes, please refer to the Phillips I2C specification. 5.6 I2C Bus Characteristics The I2C specification defines the following bus protocol: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined using Figure 5-6. 5.6.1 BUS NOT BUSY (A) Both data and clock lines remain HIGH. 5.6.2 START DATA TRANSFER (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 5.6.3 STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations can be ended with a STOP condition. 5.6.4 DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. 5.6.5 ACKNOWLEDGE The Master (microcontroller) and the slave (MCP3421) use an acknowledge pulse as a hand shake of communication for each byte. The ninth clock pulse of each byte is used for the acknowledgement. The acknowledgement is achieved by pulling-down the SDA line “LOW” during the 9th clock pulse. The clock pulse is always provided by the Master (microcontroller) and the acknowledgement is issued by the receiving device of the byte (Note: The transmitting device must release the SDA line (“HIGH”) during the acknowledge pulse.). For example, the slave (MCP3421) issues the acknowledgement (bring down the SDA line “LOW”) after the end of each receiving byte, and the master (microcontroller) issues the acknowledgement when it reads data from the Slave (MCP3421). When the MCP3421 is addressed, it generates an acknowledge after receiving each byte successfully. The Master device (microcontroller) must provide an extra clock pulse (9th pulse of each byte) for the acknowledgement from the MCP3421 (slave). The MCP3421 (slave) pulls-down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. During reads, the Master (microcontroller) can terminate the current read operation by not providing an acknowledge bit on the last byte that has been clocked out from the MCP3421. In this case, the MCP3421 releases the SDA line to allow the master (microcontroller) to generate a STOP or repeated START condition. FIGURE 5-6: Data Transfer Sequence on the Serial Bus. SCL SDA (A) (B) (D) (D) (C) (A) START CONDITION ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION MCP3421 DS22003B-page 18 © 2006 Microchip Technology Inc. TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V, +3.3V or +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. Parameters Sym Min Typ Max Units Conditions Standard Mode Clock frequency fSCL 0 — 100 kHz Clock high time THIGH 4000 — — ns Clock low time TLOW 4700 — — ns SDA and SCL rise time (Note 1) TR — — 1000 ns From VIL to VIH SDA and SCL fall time (Note 1) TF — — 300 ns From VIH to VIL START condition hold time THD:STA 4000 — — ns After this period, the first clock pulse is generated. Repeated START condition setup time TSU:STA 4700 — — ns Only relevant for repeated Start condition Data hold time (Note 3) THD:DAT 0 — 3450 ns Data input setup time TSU:DAT 250 — — ns STOP condition setup time TSU:STO 4000 — — ns STOP condition hold time THD:STD 4000 — — ns Output valid from clock (Notes 2 and 3) TAA 0 — 3750 ns Bus free time TBUF 4700 — — ns Time between START and STOP conditions. Fast Mode Clock frequency TSCL 0 — 400 kHz Clock high time THIGH 600 — — ns Clock low time TLOW 1300 — — ns SDA and SCL rise time (Note 1) TR 20 + 0.1Cb — 300 ns From VIL to VIH SDA and SCL fall time (Note 1) TF 20 + 0.1Cb — 300 ns From VIH to VIL START condition hold time THD:STA 600 — — ns After this period, the first clock pulse is generated Repeated START condition setup time TSU:STA 600 — — ns Only relevant for repeated Start condition Data hold time (Note 4) THD:DAT 0 — 900 ns Data input setup time TSU:DAT 100 — — ns STOP condition setup time TSU:STO 600 — — ns STOP condition hold time THD:STD 600 — — ns Output valid from clock (Notes 2 and 3) TAA 0 — 1200 ns Bus free time TBUF 1300 — — ns Time between START and STOP conditions. Input filter spike suppression (Note 5) TSP 0 — 50 ns SDA and SCL pins Note 1: This parameter is ensured by characterization and not 100% tested. 2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). 3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. 4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. 5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode. © 2006 Microchip Technology Inc. DS22003B-page 19 MCP3421 High Speed Mode Clock frequency fSCL 0 — 3.4 1.7 MHz MHz Cb = 100 pF Cb = 400 pF Clock high time THIGH 60 120 — — ns ns Cb = 100 pF Cb = 400 pF Clock low time TLOW 160 320 — — ns Cb = 100 pF Cb = 400 pF SCL rise time (Note 1) TR — — 40 80 ns From VIL to VIH,Cb = 100 pF Cb = 400 pF SCL fall time (Note 1) TF — — 40 80 ns From VIH to VIL,Cb = 100 pF Cb = 400 pF SDA rise time (Note 1) TR: DAT — — 80 160 ns From VIL to VIH,Cb = 100 pF Cb = 400 pF SDA fall time (Note 1) TF: DATA — — 80 160 ns From VIH to VIL,Cb = 100 pF Cb = 400 pF START condition hold time THD:STA 160 — — ns After this period, the first clock pulse is generated Repeated START condition setup time TSU:STA 160 — — ns Only relevant for repeated Start condition Data hold time (Note 4) THD:DAT 00 — 70 150 ns Cb = 100 pF Cb = 400 pF Data input setup time TSU:DAT 10 — — ns STOP condition setup time TSU:STO 160 — — ns STOP condition hold time THD:STD 160 — — ns Output valid from clock (Notes 2 and 3) TAA — — 150 310 ns Cb = 100 pF Cb = 400 pF Bus free time TBUF 160 — — ns Time between START and STOP conditions. Input filter spike suppression (Note 5) TSP 0 — 10 ns SDA and SCL pins TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V, +3.3V or +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. Parameters Sym Min Typ Max Units Conditions Note 1: This parameter is ensured by characterization and not 100% tested. 2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). 3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. 4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. 5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode. MCP3421 DS22003B-page 20 © 2006 Microchip Technology Inc. FIGURE 5-7: I2C Bus Timing Data. TF SCL SDA TSU:STA TSP THD:STA TLOW THIGH THD:DAT TAA TSU:DAT TR TSU:STO TBUF © 2006 Microchip Technology Inc. DS22003B-page 21 MCP3421 6.0 BASIC APPLICATION CONFIGURATION The MCP3421 device can be used for various precision analog-to-digital converter applications. The device operates with very simple connections to the application circuit. The following sections discuss the examples of the device connections and applications. 6.1 Connecting to the Application Circuits 6.1.1 INPUT VOLTAGE RANGE The fully differential input signals can be connected to the VIN+ and VIN- input pins. The input range should be within absolute common mode input voltage range: VSS - 0.3V to VDD + 0.3V. Outside this limit, the ESD protection diode at the input pin begins to conduct and the error due to input leakage current increases rapidly. Within this limit, the differential input VIN (= VIN+ - VIN-) is boosted by the PGA before a conversion takes place. The MCP3421 can not accept negative input voltages on the input pins. Figures 6-1 and 6-2 show typical connection examples for differential inputs and a singleended input, respectively. For the single-ended input, the input signal is applied to one of the input pins (typically connected to the VIN+ pin) while the other input pin (typically VIN- pin) is grounded. The input signal range of the single-ended configuration is from 0V to 2.048V. All device characteristics hold for the single-ended configuration, but this configuration loses one bit resolution because the input can only stand in positive half scale. Refer to Section 1.0 “Electrical Characteristics”. 6.1.2 BYPASS CAPACITORS ON VDD PIN For accurate measurement, the application circuit needs a clean supply voltage and must block any noise signal to the MCP3421 device. Figure 6-1 shows an example of using two bypass capacitors (a 10 μF tantalum capacitor and a 0.1 μF ceramic capacitor) in parallel on the VDD line. These capacitors are helpful to filter out any high frequency noises on the VDD line and also provide the momentary bursts of extra currents when the device needs from the supply. These capacitors should be placed as close to the VDD pin as possible (within one inch). If the application circuit has separate digital and analog power supplies, the VDD and VSS of the MCP3421 should reside on the analog plane. 6.1.3 CONNECTING TO I2C BUS USING PULL-UP RESISTORS The SCL and SDA pins of the MCP3421 are open-drain configurations. These pins require a pull-up resistor as shown in Figure 6-1. The value of these pull-up resistors depends on the operating speed (standard, fast, and high speed) and loading capacitance of the I2C bus line. Higher value of pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus. Therefore, it can limit the bus operating speed. The lower value of resistor, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long bus line or high number of devices connected to the bus, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1 kΩ and 10 kΩ ranges for standard and fast modes, and less than 1 kΩ for high speed mode in high loading capacitance environments. FIGURE 6-1: Typical Connection Example for Differential Inputs. FIGURE 6-2: Typical Connection Example for Single-Ended Input. The number of devices connected to the bus is limited only by the maximum bus capacitance of 400 pF. The bus loading capacitance affects on the bus operating speed. For example, the highest bus operating speed for the 400 pF bus capacitance is 1.7 MHz, and 3.4 MHz for 100 pF. Figure 6-3 shows an example of multiple device connections. MCP3421 VIN+ VINVSS VDD 1 2 3 4 5 6 SCL SDL 0.1 μF 10 μF R R Input Signals VDD VDD TO MCU Note: R is the pull-up resistor. (MASTER) MCP3421 VIN+ VINVSS VDD 1 2 3 4 5 6 SCL SDL 0.1 μF 10 μF R R Input Signals VDD VDD TO MCU Note: R is the pull-up resistor. (MASTER) MCP3421 DS22003B-page 22 © 2006 Microchip Technology Inc. FIGURE 6-3: Example of Multiple Device Connection on I2C Bus. 6.2 Device Connection Test The user can test the presence of the MCP3421 on the I2C bus line without performing an input data conversion. This test can be achieved by checking an acknowledge response from the MCP3421 after sending a read or write command. Here is an example using Figure 6-4: (a) Set the R/W bit “HIGH” in the address byte. (b) The MCP3421 will then acknowledge by pulling SDA bus LOW during the ACK clock and then release the bus back to the I2C Master. (c) A STOP or repeated START bit can then be issued from the Master and I2C communication can continue. FIGURE 6-4: I2C Bus Connection Test. 6.3 Application Examples The MCP3421 device can be used in a broad range of sensor and data acquisition applications. Figure 6-5, shows an example of interfacing with a bridge sensor for pressure measurement. FIGURE 6-5: Example of Pressure Measurement. In this circuit example, the sensor full scale range is ±7.5 mV with a common mode input voltage of VDD / 2. This configuration will provide a full 14-bit resolution across the sensor output range. The alternative circuit for this amount of accuracy would involve an analog gain stage prior to a 16-bit ADC. Figure 6-6 shows an example of temperature measurement using a thermistor. This example can achieve a linear response over a 50°C temperature range. This can be implemented using a standard resistor with 1% tolerance in series with the thermistor. The value of the resistor is selected to be equal to the thermistor value at the mid-point of the desired temperature range. FIGURE 6-6: Example of Temperature Measurement. SDASCL (24LC01) Microcontroller EEPROM MCP3421 (TC74) Temperature Sensor (PIC16F876) SCL 1 2 3 4 5 6 7 8 9 SDA 1 1 0 1 A2 A1 A0 1 Start Bit Address Byte Device bits Address bits R/W Start Bit MCP3421 ACK Response NPP301 MCP3421 VIN+ VINVSS VDD 1 2 3 4 5 6 SCL SDL 0.1 μF 10 μF R R VDD VDD TO MCU (MASTER) VDD 10 kΩ Resistor 10 kΩ Thermistor MCP3421 VIN+ VINVSS VDD 1 2 3 4 5 6 SCL SDL 0.1 μF 10 μF R R VDD VDD TO MCU (MASTER) VDD © 2006 Microchip Technology Inc. DS22003B-page 23 MCP3421 7.0 PACKAGING INFORMATION 7.1 Package Marking Information Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e3 e3 2 5 3 1 4 6 6-Lead SOT-23 XXNN 2 5 3 1 4 6 Example CA25 MCP3421 DS22003B-page 24 © 2006 Microchip Technology Inc. 6-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 1 D B n E E1 L c β φ α A A2 A1 p1 Mold Draft Angle Bottom β 0 5 10 0 5 10 Mold Draft Angle Top α 0 5 10 0 5 10 Lead Width B .014 .017 .020 0.35 0.43 0.50 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Foot Angle φ 0 5 10 0 5 10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Overall Length D .110 .116 .122 2.80 2.95 3.10 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Width E .102 .110 .118 2.60 2.80 3.00 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Overall Height A .035 .046 .057 0.90 1.18 1.45 Outside lead pitch p1 .075 BSC 1.90 BSC Pitch p .038 BSC 0.95 BSC Number of Pins n 6 6 Dimension Limits MIN NOM MAX MIN NOM MAX Units INCHES* MILLIMETERS Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. Notes: JEITA (formerly EIAJ) equivalent: SC-74A * Controlling Parameter Drawing No. C04-120 BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M Revised 09-12-05 © 2006 Microchip Technology Inc. DS22003B-page 27 MCP3421 APPENDIX A: REVISION HISTORY Revision B (December 2006) • Changes to Electrical Characteristics tables • Added characterization data • Changes to I2C Serial Timing Specification table • Change to Figure 5-7. Revision A (August 2006) • Original Release of this Document. MCP3421 DS22003B-page 28 © 2006 Microchip Technology Inc. NOTES: © 2006 Microchip Technology Inc. DS22003B-page 29 MCP3421 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: MCP3421T: Single Channel ΔΣ A/D Converter (Tape and Reel) Address Options: XX A2 A1 A0 A0 * = 0 0 0 A1 = 0 0 1 A2 = 0 1 0 A3 = 0 1 1 A4 = 1 0 0 A5 = 1 0 1 A6 = 1 1 0 A7 = 1 1 1 * Default option. Contact Microchip factory for other address options Temperature Range: E = -40°C to +125°C Package: OT = Plastic Small Outline Transistor (SOT-23-6), 6-lead Examples: a) MCP3421A0T-E/OT: Tape and Reel, Single Channel ΔΣ A/D Converter, SOT-23-6 package. PART NO. XX X Address Temperature Range Device /XX Package Options MCP3421 DS22003B-page 30 © 2006 Microchip Technology Inc. NOTES: © 2006 Microchip Technology Inc. DS22003B-page 31 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS22003B-page 32 © 2006 Microchip Technology Inc. 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5.5V for ATtiny26L – 4.5V - 5.5V for ATtiny26 • Speed Grades – 0 - 8 MHz for ATtiny26L – 0 - 16 MHz for ATtiny26 • Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L – Active 16 MHz, 5V and 25°C: Typ 15 mA – Active 1 MHz, 3V and 25°C: 0.70 mA – Idle Mode 1 MHz, 3V and 25°C: 0.18 mA – Power-down Mode: < 1 μA 8-bit Microcontroller with 2K Bytes Flash ATtiny26 ATtiny26L Summary 1477KS–AVR–08/10 2 1477KS–AVR–08/10 ATtiny26(L) Pin Configuration Note: The bottom pad under the QFN/MLF package should be soldered to ground. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (MOSI/DI/SDA/OC1A) PB0 (MISO/DO/OC1A) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC GND (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (AREF) GND AVCC PA4 (ADC3) PA5 (ADC4) PA6 (ADC5/AIN0) PA7 (ADC6/AIN1) PDIP/SOIC 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 MLF Top View NC (OC1B) PB3 NC VCC GND NC (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 NC PA2 (ADC2) PA3 (AREF) GND NC NC AVCC PA4 (ADC3) NC (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 NC (ADC6/AIN1) PA7 (ADC5/AIN0) PA6 (ADC4) PA5 NC PB2 (SCK/SCL/OC1B) PB1 (MISO/DO/OC1A) PB0 (MOSI/DI/SDA/OC1A) NC NC NC PA0 (ADC0) PA1 (ADC1) 3 1477KS–AVR–08/10 ATtiny26(L) Description The ATtiny26(L) is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny26(L) achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny26(L) has a high precision ADC with up to 11 single ended channels and 8 differential channels. Seven differential channels have an optional gain of 20x. Four out of the seven differential channels, which have the optional gain, can be used at the same time. The ATtiny26(L) also has a high frequency 8-bit PWM module with two independent outputs. Two of the PWM outputs have inverted non-overlapping output pins ideal for synchronous rectification. The Universal Serial Interface of the ATtiny26(L) allows efficient software implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features allow for highly integrated battery charger and lighting ballast applications, low-end thermostats, and firedetectors, among other applications. The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and external interrupts, programmable Watchdog Timer, 11-channel, 10-bit Analog to Digital Converter with two differential voltage input gain stages, and four software selectable power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters and interrupt system to continue functioning. The ATtiny26(L) also has a dedicated ADC Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode, only the ADC is functioning. The Power-down mode saves the register contents but freezes the oscillators, disabling all other chip functions until the next interrupt or hardware reset. The Standby mode is the same as the Power-down mode, but external oscillators are enabled. The wakeup or interrupt on pin change features enable the ATtiny26(L) to be highly responsive to external events, still featuring the lowest power consumption while in the Power-down mode. The device is manufactured using Atmel’s high density non-volatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny26(L) is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny26(L) AVR is supported with a full suite of program and system development tools including: Macro assemblers, program debugger/simulators, In-circuit emulators, and evaluation kits. 4 1477KS–AVR–08/10 ATtiny26(L) Block Diagram Figure 1. The ATtiny26(L) Block Diagram WATCHDOG TIMER MCU CONTROL REGISTER UNIVERSAL SERIAL INTERFACE TIMER/ COUNTER0 DATA DIR. REG.PORT A DATA REGISTER PORT A PROGRAMMING LOGIC TIMING AND CONTROL TIMER/ COUNTER1 MCU STATUS REGISTER PORT A DRIVERS PA0-PA7 VCC GND + - ANALOG COMPARATOR 8-BIT DATA BUS ADC ISP INTERFACE INTERRUPT UNIT EEPROM INTERNAL OSCILLATOR OSCILLATORS CALIBRATED OSCILLATOR INTERNAL DATA DIR. REG.PORT B DATA REGISTER PORT B PORT B DRIVERS PB0-PB7 PROGRAM COUNTER STACK POINTER PROGRAM FLASH SRAM GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER INSTRUCTION DECODER STATUS REGISTER Z Y X ALU CONTROL LINES AVCC 5 1477KS–AVR–08/10 ATtiny26(L) Pin Descriptions VCC Digital supply voltage pin. GND Digital ground pin. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. See page 94 for details on operating of the ADC. Port A (PA7..PA0) Port A is an 8-bit general purpose I/O port. PA7..PA0 are all I/O pins that can provide internal pull-ups (selected for each bit). Port A has alternate functions as analog inputs for the ADC and analog comparator and pin change interrupt as described in “Alternate Port Functions” on page 46. Port B (PB7..PB0) Port B is an 8-bit general purpose I/O port. PB6..0 are all I/O pins that can provide internal pullups (selected for each bit). PB7 is an I/O pin if not used as the reset. To use pin PB7 as an I/O pin, instead of RESET pin, program (“0”) RSTDISBL Fuse. Port B has alternate functions for the ADC, clocking, timer counters, USI, SPI programming, and pin change interrupt as described in “Alternate Port Functions” on page 46. An External Reset is generated by a low level on the PB7/RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. 6 1477KS–AVR–08/10 ATtiny26(L) General Information Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 7 1477KS–AVR–08/10 ATtiny26(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG I T H S V N Z C 10 $3E ($5E) Reserved $3D ($5D) SP SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11 $3C ($5C) Reserved $3B ($5B) GIMSK - INT0 PCIE1 PCIE0 - - - - 58 $3A ($5A) GIFR - INTF0 PCIF - - - - - 59 $39 ($59) TIMSK - OCIE1A OCIE1B - - TOIE1 TOIE0 - 59 $38 ($58) TIFR - OCF1A OCF1B - - TOV1 TOV0 - 60 $37 ($57) Reserved $36 ($56) Reserved $35 ($55) MCUCR - PUD SE SM1 SM0 - ISC01 ISC00 37 $34 ($54) MCUSR - - - - WDRF BORF EXTRF PORF 36 $33 ($53) TCCR0 - - - - PSR0 CS02 CS01 CS00 66 $32 ($52) TCNT0 Timer/Counter0 (8-Bit) 67 $31 ($51) OSCCAL Oscillator Calibration Register 29 $30 ($50) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM1A PWM1B 70 $2F ($4F) TCCR1B CTC1 PSR1 - - CS13 CS12 CS11 CS10 71 $2E ($4E) TCNT1 Timer/Counter1 (8-Bit) 72 $2D ($4D) OCR1A Timer/Counter1 Output Compare Register A (8-Bit) 72 $2C ($4C) OCR1B Timer/Counter1 Output Compare Register B (8-Bit) 73 $2B ($4B) OCR1C Timer/Counter1 Output Compare Register C (8-Bit) 73 $2A ($4A) Reserved $29 ($49) PLLCSR - - - - - PCKE PLLE PLOCK $28 ($48) Reserved $27 ($47) Reserved $26 ($46) Reserved $25 ($45) Reserved $24 ($44) Reserved $23 ($43) Reserved $22 ($42) Reserved $21 ($41) WDTCR - - - WDCE WDE WDP2 WDP1 WDP0 78 $20 ($40) Reserved $1F ($3F) Reserved $1E ($3E) EEAR - EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 18 $1D ($3D) EEDR EEPROM Data Register (8-Bit) 19 $1C ($3C) EECR - - - - EERIE EEMWE EEWE EERE 19 $1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 $1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 $19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 $18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 $17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 $16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 $15 ($35) Reserved $14 ($34) Reserved $13 ($33) Reserved $12 ($32) Reserved $11 ($31) Reserved $10 ($30) Reserved $0F ($2F) USIDR Universal Serial Interface Data Register (8-Bit) 81 $0E ($2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 81 $0D ($2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 82 $0C ($2C) Reserved $0B ($2)B Reserved $0A ($2A) Reserved $09 ($29) Reserved $08 ($28) ACSR ACD ACBG ACO ACI ACIE ACME ACIS1 ACIS0 91 $07 ($27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 101 $06 ($26) ADCSR ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 103 $05 ($25) ADCH ADC Data Register High Byte 104 $04 ($24) ADCL ADC Data Register Low Byte 104 … Reserved $00 ($20) Reserved 8 1477KS–AVR–08/10 ATtiny26(L) Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl, K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry Two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl, K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,H 1 SBR Rd, K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd, K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← $FF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← Z None 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd, Rr Compare Rd - Rr Z,N,V,C,H 1 CPC Rd, Rr Compare with Carry Rd - Rr - C Z,N,V,C,H 1 CPI Rd, K Compare Register with Immediate Rd - K Z,N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b) = 0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b) = 1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V = 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less than Zero, Signed if (N ⊕ V = 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half-carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half-carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T-flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T-flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move between Registers Rd ← Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-inc. Rd ← (X), X ← X + 1 None 2 LD Rd, -X Load Indirect and Pre-dec. X ← X - 1, Rd ← (X) None 2 9 1477KS–AVR–08/10 ATtiny26(L) LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, -Y Load Indirect and Pre-dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-inc. Rd ← (Z), Z ← Z + 1 None 2 LD Rd, -Z Load Indirect and Pre-dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-inc. (X) ← Rr, X ← X + 1 None 2 ST -X, Rr Store Indirect and Pre-dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-inc. (Y) ← Rr, Y ← Y + 1 None 2 ST -Y, Rr Store Indirect and Pre-dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q, Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left through Carry Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7) Z,C,N,V 1 ROR Rd Rotate Right through Carry Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit Load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Two’s Complement Overflow V ← 1 V 1 CLV Clear Two’s Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half-carry Flag in SREG H ← 1 H 1 CLH Clear Half-carry Flag in SREG H ← 0 H 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks 10 1477KS–AVR–08/10 ATtiny26(L) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Code Indicators: – U: matte tin – R: tape & reel Ordering Information Speed (MHz) Power Supply (V) Ordering Code(2) Package(2) Operational Range 8 2.7 - 5.5 ATtiny26L-8PU ATtiny26L-8SU ATtiny26L-8SUR ATtiny26L-8MU ATtiny26L-8MUR 20P3 20S 20S 32M1-A 32M1-A Industrial (-40°C to +85°C)(1) 16 4.5 - 5.5 ATtiny26-16PU ATtiny26-16SU ATtiny26-16SUR ATtiny26-16MU ATtiny26-16MUR 20P3 20S 20S 32M1-A 32M1-A Industrial (-40°C to +85°C)(1) Package Type 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 11 1477KS–AVR–08/10 ATtiny26(L) Packaging Information 20P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) 20P3 C 1/12/04 PIN 1 E1 A1 B E B1 C L SEATING PLANE A D e eB eC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 5.334 A1 0.381 – – D 25.493 – 25.984 Note 2 E 7.620 – 8.255 E1 6.096 – 7.112 Note 2 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 12 1477KS–AVR–08/10 ATtiny26(L) 20S 13 1477KS–AVR–08/10 ATtiny26(L) 32M1-A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 32M1-A E 5/25/06 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D1 D E1 E b e A3 A2 A1 A D2 E2 0.08 C L 1 2 3 P P 0 1 2 3 A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 0.20 REF b 0.18 0.23 0.30 D D1 D2 2.95 3.10 3.25 4.90 5.00 5.10 4.70 4.75 4.80 4.70 4.75 4.80 4.90 5.00 5.10 E E1 E2 2.95 3.10 3.25 e 0.50 BSC L 0.30 0.40 0.50 P – – 0.60 – – 12o Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. TOP VIEW SIDE VIEW BOTTOM VIEW 0 Pin 1 ID Pin #1 Notch (0.20 R) K 0.20 – – K K 14 1477KS–AVR–08/10 ATtiny26(L) Errata The revision letter refers to the revision of the device. ATtiny26 Rev. B/C/D • First Analog Comparator conversion may be delayed 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable the Analog Comparator before the first conversion. 15 1477KS–AVR–08/10 ATtiny26(L) Datasheet Revision History Please note that the referring page numbers in this section refer to the complete document. Rev. 1477K-08/10 Added tape and reel part numbers in “Ordering Information” on page 171. Removed text “Not recommended for new design” from cover page. Updated last page. Rev. 1477J-06/07 1. “Not recommended for new design” Rev. 1477I-05/06 1. Updated “Errata” on page 175 Rev. 1477H-04/06 1. Updated typos. 2. Added “Resources” on page 6. 3. Updated features in “System Control and Reset” on page 32. 4. Updated “Prescaling and Conversion Timing” on page 96. 5. Updated algorithm for “Enter Programming Mode” on page 112. Rev. 1477G-03/05 1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”. 2. Updated “Electrical Characteristics” on page 126 3. Updated “Ordering Information” on page 171 Rev. 1477F-12/04 1. Updated Table 16 on page 33, Table 9 on page 28, and Table 29 on page 57. 2. Added Table 20 on page 40. 3. Added “Changing Channel or Reference Selection” on page 98. 4. Updated “Offset Compensation Schemes” on page 105. 5. Updated “Electrical Characteristics” on page 126. 6. Updated package information for “20P3” on page 172. 7. Rearranged some sections in the datasheet. Rev. 1477E-10/03 1. Removed Preliminary references. 2. Updated “Features” on page 1. 3. Removed SSOP package reference from “Pin Configuration” on page 2. 4. Updated VRST and tRST in Table 16 on page 33. 5. Updated “Calibrated Internal RC Oscillator” on page 29. 16 1477KS–AVR–08/10 ATtiny26(L) 6. Updated DC Characteristics for VOL, IIL, IIH, ICC Power Down and VACIO in “Electrical Characteristics” on page 126. 7. Updated VINT, INL and Gain Error in “ADC Characteristics” on page 129 and page 130. Fixed typo in “Absolute Accuracy” on page 130. 8. Added Figure 106 in “Pin Driver Strength” on page 146, Figure 120, Figure 121 and Figure 122 in “BOD Thresholds and Analog Comparator Offset” on page 155. Updated Figure 117 and Figure 118. 9. Removed LPM Rd, Z+ from “Instruction Set Summary” on page 169. This instruction is not supported in ATtiny26. Rev. 1477D-05/03 1. Updated “Packaging Information” on page 172. 2. Removed ADHSM from “ADC Characteristics” on page 129. 3. Added section “EEPROM Write During Power-down Sleep Mode” on page 20. 4. Added section “Default Clock Source” on page 26. 5. Corrected PLL Lock value in the “Bit 0 – PLOCK: PLL Lock Detector” on page 73. 6. Added information about conversion time when selecting differential channels on page 97. 7. Corrected {DDxn, PORTxn} value on page 42. 8. Added section “Unconnected Pins” on page 46. 9. Added note for RSTDISBL Fuse in Table 50 on page 108. 10. Corrected DATA value in Figure 61 on page 116. 11. Added WD_FUSE period in Table 60 on page 123. 12. Updated “ADC Characteristics” on page 129 and added Table 66, “ADC Characteristics, Differential Channels, TA = -40°C to +85°C,” on page 130. 13. Updated “ATtiny26 Typical Characteristics” on page 131. 14. Added LPM Rd, Z and LPM Rd, Z+ in “Instruction Set Summary” on page 169. Rev. 1477C-09/02 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. Rev. 1477B-04/02 1. Removed all references to Power Save sleep mode in the section “System Clock and Clock Options” on page 23. 2. Updated the section “Analog to Digital Converter” on page 94 with more details on how to read the conversion result for both differential and single-ended conversion. 3. Updated “Ordering Information” on page 171 and added QFN/MLF package information. Rev. 1477A-03/02 1. Initial version. 17 1477KS–AVR–08/10 ATtiny26(L) 1477KS–AVR–08/10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en- Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support Enter Product Line E-mail Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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Un design innovant pour une utilisation efficace et confortable  Un boîtier léger et compact et une interface utilisateur conviviale  Un afficheur d’une dimension et d’une lisibilité inégalées  Une calibration 100% numérique pour une précision et un coût maîtrisés  Des versions entièrement programmables respectant la norme SCPI  Nouvelle technologie d’affichage intelligent (Smart Persistence Oscilloscope)  Des atouts qui séduiront l’Enseignement et l’Industrie Si intelligents que vous pouvez les choisir pour leurs courbes ! Série MTX COMPACT « Une gamme complète et performante d’instruments de laboratoire » MTX 3252 MTX 3352 MTX 3354 MTX 3240 MTX 3250 MTX 3250 Multimètre-Analyseur MTX 3240 Générateur BF-Mesureur MTX 3252 - MTX 3352 - MTX 3354 Oscilloscopes-Analyseurs Tout comme le générateur de la même famille, le multimètre MTX est un appareil surdoué, multifonction. Grâce à son analyse du signal il évite à l’utilisateur la mise en oeuvre d’autres instruments (oscilloscope par exemple), pour contrôler la validité des mesures réalisées. Impossible de commettre les, si fréquentes et souvent ignorées, erreurs dues à un facteur de crête trop élevé. En effet, le MTX 3250 mesure en permanence les crêtes rapides à 500 μs et vous alerte en cas d’anomalie. Mieux encore, en validant alors le “Mode AUTO PEAK”, le multimètre commutera automatiquement sur une gamme adaptée à la nature du signal mesuré. L’affichage du facteur de crête vous permettra aussi d’établir un premier diagnostic qualitatif sur vos signaux. Le MTX 3250, c’est encore la rationalisation de l’investissement réalisé, puisqu’il est également fréquencemètre, thermomètre et même enregistreur, vous évitant ainsi l’achat d’un instrument d’usage ponctuel. Ainsi, pour les enregistrements en laboratoire jusqu’à 4 voies et 12 paramètres, la version “acquisition de données” et son logiciel PC associé rendront un service performant à partir d’un instrument polyvalent. La température est directement mesurée à partir de Pt 100 ou Pt 1000, de même que la fréquence, jusqu’à 1 MHz, avec période et rapport cyclique. Et pour mieux répondre à vos attentes dans le cadre de systèmes automatisés, cet instrument existe en version programmable à 100 % via une liaison optique RS232 à 57600 bauds, compatible SCPI. Un multimètre à la pointe des modes 50 000 points 500 mV - 500 mV - 600 V 500 μA - 500 mA & 10 A 5 μA – 500 mA & 10A 500 Ω - 50 MΩ 170 x 270 x 190 mm optique RS232 LCD 50 x 140 mm 500 V & 0,5%L + 3D 0,2%L + 3D 0,5%L + 3D 0,1%L + 3D Masse : 2,3 kg 57 600 bauds Rétro-éclairage 1000 V (50 000 pts) 10 kHz Aff. triple 0,08%L+3D 100 kHz CARACTÉRISTIQUES : Affichage Gammes et Gammes et Gammes et Gammes et Gammes et Dimensions Interface précision précision VAC de base précision IDC de base précision IAC précision de base H x L x P MTX 3250-P de base VDC Bande passante Bande passante Ohm MTX 3250-A  Autres mesures : test continuité, test diode capacités 50 nF – 50 mF, fréquence 1 Hz - 1 MHz, rapport cyclique 0,01% à 100%, température - 200 à + 800°C, pt 100 et pt 1000.  Fonction PEAK HOLD : Pk+/ -500 μs sur I & V, facteur de crête  Fonctions complémentaires : SURV = MIN/MAX datés / MATH = dB, dBm, ax+b / OFFSET (Offset, nul, delta%) / Data HOLD & Auto HOLD  Fonction supplémentaire sur MTX 3250-P : PRINT, cadence 0,5 s à 10 h, horloge et calendrier, pilotage RS232 optique  Fonction supplémentaire sur MTX 3250-A : DATA LOGGER avec 1500 mesures stockées, 1 ou 3 valeurs simultanées. Normes : sécurité selon IEC 61010-1, 2001 et CEM selon NF 61326-1, 1998 Garantie : 3 ans Le multimètre MTX 3250 est fourni avec 1 câble d’alimentation secteur, 1 jeu de cordons de mesure, une notice de fonctionnement et une présentation interactive de l’instrument sur CD-Rom. Pour commander MTX3250 Multimètre de Table 50 000 pts MTX3250-P Multimètre de Table 50 000 pts + RS232 Fourni avec un cordon de liaison optique RS232, un manuel de programmation et les drivers Labwindows / Labview sur CD-Rom. MTX3250-A Multimètre de Table 50 000 pts + Acquisition Fourni avec un cordon de liaison optique RS232, un manuel de programmation, les drivers Labwindows / Labview et le logiciel d’acquisition de données SX-DMM sur CD-Rom. Tout commence avec une connexion réduite à 3 bornes qui limite erreurs et manipulations, permettant un “AUTORANGING” courant complet de 50 μA à 20 A. Le MTX 3250 offre ensuite, grâce à son affichage triple, les combinaisons de mesures qui répondent simplement et efficacement à vos applications courantes, comme, par exemple, la mesure de bande passante (affichage de l’atténuation en dB et de la fréquence). Accessoires et informations pour commander Pour la maîtrise métrologique, le “Mode SPEC” calcule et affiche les incertitudes de l’instrument en fonction des gammes et de la valeur mesurée Le Mode offre la lecture directe de la grandeur mesurée, ainsi que l’unité physique correspondante Le “Mode Surveillance” enregistre les minima et les maxima afin de piéger et de dater vos défauts L’association fonctionnelle Le “Mode RELATIF” exprimé en absolu, pourcentage ou dB (ratio), permet une exploitation directe MTX 3250 : multimètre-analyseur intégré Asservissement et affichage de la fréquence Contrôle et affichage de l’AMPLITUDE VCC (crête/crête) et de l’OFFSET VDC Contrôle et affichage du rapport cyclique Le MTX 3240 c’est aussi la rationalisation de l’investissement réalisé, puisqu’il est aussi un fréquencemètre 100 MHz (Cat. I, 300 V), vous évitant ainsi l’achat d’un instrument d’usage souvent ponctuel. Et pour répondre enfin de manière économique à vos attentes dans le cadre de systèmes automatisés, ce générateur existe en version programmable à 100 % via une liaison rapide, compatible SCPI. Sa technologie permet à chacun de bénéficier de fonctions nouvelles, indispensables : Réglage de la fréquence, garantie stable au digit près, et accélérateur intelligent avec changement de gammes automatique pour la fréquence Changement de gammes automatique optimisé pour l’amplitude “LEVEL et OFFSET” Rapport cyclique réglable sans variation ni division de la fréquence Fonction “LOGIC” pour une réponse simple et rapide à la génération de signaux logiques à seuils directement ajustables Un générateur robuste, avec des sorties protégées 60 VDC / 40 VAC L’association fonctionnelle MTX 3240 : générateur-mesureur autonome Un générateur doté de caractéristiques innovantes LCD 50 x 140 mm 0,1 Hz à 5,1 MHz Sinus, carré, 1) Principale : LIN ou LOG 0,1 Hz à 100 MHz 115 V - 230 V - 170x270x190 mm optique Afficheur principal 7 gammes + triangle, jusqu’à 20 VCC CONTINU, Précision : 0,05 % 240 V Masse : 2,8 kg RS232 20 mm réglage fin au digit impulsion, circuit ouvert, 1 : 50 Min Entrée 300 V, Cat. I 50 / 60 Hz 4 grandeurs près + accélérateur rampe, TTL, gamme automatique De 10 ms à 10 s Sensibilité 300 V, Cat.II simultanées Précision : 0,05 % LOGIC 2) TTL Interne ou externe automatique Distorsion Protection : overload < 0,5 % 60 VDC / 40 VAC CARACTÉRISTIQUES : Affichage Gamme Formes Sorties Balayage Fréquencemètre Alimentation Dimensions Interface de fréquence de signaux externe H x L x P (MTX 3240-P) Normes : sécurité selon IEC 61010-1, 2001 et CEM selon NF 61326-1, 1998 Garantie : 3 ans Le générateur MTX 3240 est fourni avec un câble d’alimentation secteur, une notice de fonctionnement et une présentation interactive de l’instrument sur CD-Rom. Pour commander MTX3240 Générateur de Fonctions 5,1 MHz MTX3240-P Générateur de Fonctions 5,1 MHz + RS232 Fourni avec un cordon de liaison optique RS232, un manuel de programmation et les drivers Labwindows / Labview sur CD-Rom. Accessoires et informations pour commander Autre apport de l’innovation pour l’utilisateur : une fonctionnalité complète pour l’investissement réalisé. En effet, l’association fonctionnelle du MX 3240 permet sa mise en oeuvre autonome, ce qui évite, par exemple, l’utilisation systématique d’un oscilloscope ou d‘un multimètre, simplement pour en contrôler les réglages. MTX 3240 avec fréquencemètre intégré Interface Homme-Machine, la simplicité au service de la performance L’instrument peut être piloté par la souris ou le clavier Les réglages sont simplifiés et conviviaux grâce aux 21 touches d’accès direct de la face avant et à l’environnement « Windows-Like » Une aide en ligne détaillée et en 5 langues est disponible à tout moment grâce à la touche Léger, compact et pourvu d'une poignée, il dispose d’un « Pack Terrain » qui permet la mise en oeuvre de l ‘oscilloscope sans le sortir de sa sacoche Affichage Des curseurs peuvent être placés à tout moment sur les signaux pour réaliser des mesures précises Grâce à une profondeur mémoire de 50.000 points, le zoom de trace horizontal, « Winzoom », peut aller jusqu’à un facteur x100 en affichant des vrais points acquis . Une dynamique verticale exceptionnelle de 2,5 mV à 100 V par div. La fonction « full trace » permet de diviser l’écran en deux afin d’optimiser la lisibilité des courbes Affichage jusqu’à 4 courbes à l’écran et possibilité d’établir des comparaisons entre deux courbes. Pour plus de simplicité et un gain de temps conséquent, l’utilisateur peut sélectionner et afficher 2 mesures automatiques parmi 19. MTX 3252, MTX 3352 et MTX 3354 : Oscilloscopes – analyseurs 2 ou 4 voies, de 60 à 150 MHz ! Experts en communication Équipés d’une liaison RS232, de l’interface Centronics et d’une liaison USB indispensables à la communication vers un PC ou une imprimante Gestion à distance grâce à la liaison Ethernet et au serveur HTML présent dans chaque instrument Des fonctions complexes d’analyse sont accessibles en mode « avancé » , elles sont masquées en mode « standard » dans un soucis de simplification. Enregistrement, une mémoire infinie …, Les oscilloscopes de la gamme MTX COMPACT disposent d’un écran LCD couleur 5"7 avec rétro éclairage pour une excellente précision de lecture Le choix est large puisque MTX COMPACT propose trois appareils de 2 et 4 voies de bande passante 60 MHz, 100 MHz ou 150 MHz qui séduiront aussi bien l'Enseignement Technique que l’Industrie Le déclenchement dispose de 5 modes différents : Pulse, déclenchement sur largeur d'impulsion, Retard, déclenchement sur fronts avec retardateur, TV, déclenchement sur un signal TV, Comptage, déclenchement sur font avec comptage d'événements et Secteur, déclenchement sur le front ascendant ou descendant de la tension réseau 50/60 Hz Outre ces multiples modes de paramétrage, le Holdoff est disponible sur la majorité de ces fonctions de déclenchement , technologie d’affichage de type « analogique » qui permet de faire apparaître les évolutions du signal (modulations, jitters etc.) et les phénomènes uniques (transitoires, glitchs, etc.) La profondeur mémoire de 50.000 points est une référence dans cette catégorie d’oscilloscopes Durée d’enregistrement et fréquence d’échantillonnage 20 fois plus élevées qu’un oscilloscope traditionnel Les oscilloscopes de la gamme MTX COMPACT dispose d’une résolution exceptionnelle de 100 Gé/s en mode répétitif et 200 Mé/s en mode monocoup, ce qui permet d’avoir des calibres de base de temps allant de 200 s/div à 1ns/div. Enregistrement de courbes et rappel à l’écran Possibilité de sauvegarder des fichiers dans l’instrument, de les imprimer ou de les exporter vers un PC en vue d’une exploitation ultérieure dans les applications « Windows » (rapports, tableurs, impression, images …) Les traces et les fichiers enregistrés sont horodatés Les fichiers sont générés dans des formats standards : .gif, .pcl, .txt, .bmp, .eps, .prn, etc. Des instruments intégrés pour un « outil global » L’ensemble des oscilloscopes sont pourvus de la fonction analyse FFT temps réel et multivoie du signal Pour les utilisateurs du domaine de l’Electrotechnique, nous proposons en option l’analyse d’harmoniques multivoies 31 rangs Enfin, pour tous ceux qui doivent surveiller dans le temps les variations de phénomènes physiques ou mécaniques , un enregistreur numérique rapide est intégrable dans l’instrument, sous forme d’un module software MTX 3252, MTX 3352 et MTX 3354 : Oscilloscopes – analyseurs 2 ou 4 voies, de 60 à 150 MHz ! Ergonomie La technologie " " permet de faire persister les acquisitions pendant une durée paramétrée pour observer un cumul de traces. L’intensité lumineuse ou la couleur, affectée au point à l’écran, va décroître si celui-ci n’est pas renouvelé lors d’une nouvelle acquisition. L’acquisition se fait donc en trois dimensions : - le temps - l’amplitude - l’occurrence Grâce à sa profondeur mémoire de 50.000 points, l’oscilloscope acquiert et traite l’information en parallèle. Le nombre d’acquisitions à la seconde peut-être multiplié par un facteur supérieur à 1000, ainsi le temps mort entre deux acquisitions est considérablement réduit. Représentation à l’écran des 50.000 points acquis par un système de compression intelligente. L’occurrence apporte une dimension statistique à la répartition des échantillons. La couleur ou l’intensité lumineuse met en évidence les irrégularités du signal. Durées d’affichage des points acquis : 100ms, 200ms, 500ms, 1s, 2s, 5s, 10s et infini. , Smart Persistence Oscilloscope : L’outil indispensable de visualisation intelligente ! La technologie SPO La nouvelle génération d’oscilloscopes MTX COMPACT est dotée de l'affichage " " (Smart Persistence Oscilloscope) qui permet, comme en analogique, de faire apparaître les évolutions du signal dans le temps, les jitters, les modulations et les phénomènes instables. Par ailleurs, ce mode d’affichage permet aussi la mise en évidence des phénomènes uniques tels que les transitoires ou les glitchs. Acquisition Traitement rapide Affichage Parallèle N acquisitions = 1 affichage Modulation AM ou FM Évènements uniques ou transitoires Caractérisation du bruit Signal vidéo Applications - MTX3354E-C : oscilloscope numérique 4x150MHz, couleur, Ethernet - MTX3354E-CK : MTX3354E-C + SX-METRO/P - MTX3252BE-C : oscilloscope numérique 2x60MHz, couleur, Ethernet - MTX3352BE-C : oscilloscope numérique 2x100MHz, couleur, Ethernet - MTX3252BED : MTX3252BE-C + sonde différentielle MTX1032-B - MTX3352BED : MTX3352BE-C + sonde différentielle MTX1032-C Pour commander MTX 3252, MTX 3352 & MTX 3354 : Oscilloscopes – analyseurs 60, 100 et 150 MHz Interface Homme-Machine Affichage LCD couleur 5” 7 (115x86mm) - LCD monochrome ou couleur 5” 7 (115x86mm) 320 x 240 + rétro éclairage CCFL - 320 x 240 + rétro éclairage CCFL Nombre de courbes à l’écran 4 courbes + 4 références Commandes 21 touches de raccourcis directs + 1 encodeur + 1 touche « aide » Menu « Windows-like » - 100% des commandes accessibles via la souris Choix des langues par le menu (FRA/ANG/ESP/ITA/ALL) Déviation Verticale Bande passante 150 MHz 100 MHz 60 MHz (limiteur de BP 15 MHz (limiteur de BP (limiteur de BP 1,5 MHz et 5 kHz) 15 MHz) 15 MHz) Nombre voies 4 voies classe 1 – Cat. II 300 V 2 voies classe 1 – Cat. II 300 V Sensibilité 2,5 mV – 100 V/div + expansion verticale 2,5 mV – 100 V/div "Winzoom" jusqu'à un facteur 10 + expansion verticale « Winzoom » (sensibilité maximum 250 μV/div) jusqu’à un facteur 10 Temps de montée < 3 ns < 3,5 ns Déviation Horizontale Vitesse de balayage 1 ns à 200 s/div - winzoom graphique jusqu'à un facteur 100 Déclenchement Modes Auto, Normal, Monocoup, Auto 50% Types Front, Largeur d’impulsion, Retard, Comptage d’évènements, Compteur de lignes TV, Hold-off Sources CH1, CH2, CH3, CH4, Secteur CH1, CH2, EXT et Secteur Mémoire Numérique Échantillonnage maxi. Répétitif = 100 Gé/s Monocoup = 200 Mé/s (2 voies), convertisseur 9 bits Profondeur mémoire 50.000 points – 4 références + 16 courbes de 50 kpts Modes d’affichage Glitch, Enveloppe, Moyennage, XY Numérique SPO (Smart Persistence Oscilloscope) Durée 100 ms, 200 ms, 500 ms, 1 s, 2 s, 5 s 100 s et Infini Représentation Monochrome ou couleur Vitesse d’acquisition 50 kwaveform/s max. par voie – 19 Mé traités par s et par voie Mode Enregistreur Cadence d’acquisition De 40 μs à 54 μs d’intervalle d’échantillonnage (2 s à 31 jours d’enregistrement) Exploitation Horodatage direct, conversion et unités des grandeurs physiques, mesures par curseurs et recherche d’événement, fichiers exploitables sur tableur standard Mode Analyseur d’Harmoniques Étendue d’analyse 31 rangs simultanément sur 1 à 4 voies Exploitation Affichage permanent : valeur RMS totale THD – Rang sélectionné : %F, phase, freq, Vrms Interface RS232, Centronics, USB, Ethernet avec serveur HTML Caractéristiques Générales Boîtier 210 x 177 x 200 – 2,5 Kg – IP30 Alimentation 100 à 240 VAC – 47 à 63 Hz Sécurité IEC 1010-1 (2001) – Surtension de l’alimentation CAT II 240 V – Surtension des entrées de mesure CAT II 300V CEM NF EN 61326-1 07/97 + A1 10/98 CARACTÉRISTIQUES : MTX 3354 MTX 3352 MTX 3252 AD.COM- Code : 906210055 - Ed.5 - 09/2007 - Caractéristiques sous réserve de modifications liées à l’évolution de la technologie L’efficacité s’affiche avec élégance Le design moderne et séduisant des appareils de la famille MTX permet, grâce à une forte compacité, leur parfaite intégration dans votre cadre de travail. Posés directement sur la paillasse, l’espace libéré devant eux est déjà très appréciable, de plus, leur hauteur est calculée pour pouvoir les glisser sans peine sous les demi-étagères. Leur faible profondeur et leur largeur standard vous permettent aussi de les placer sur ces mêmes demi-étagères ou de les poser sur un autre instrument. Le déplacement et le transport sont très aisés grâce à leur poignée intégrée et à leur légèreté. Une architecture et des formes avantageuses qui vous font gagner de la place Même à distance ou dans des conditions d’éclairage difficiles (soleil, néons), les mesures sont parfaitement lisibles, grâce notamment à un afficheur négatif de grandes dimensions (50 x 140 mm), à un rétro-éclairage à matrice de leds ajustable, ainsi qu’à une hauteur exceptionnelle de 20 mm de l’afficheur principal (MTX 3240 et MTX 3250). Monochrome ou couleur, l’écran LCD réglable et orientable des MTX 3252 et MTX 3352 vous garantira, lui aussi, une lisibilité en toutes circonstances. Les zones fonctionnelles de l’ensemble des MTX Compact sont vastes, cohérentes et hiérarchisées, et les connexions mesure facilement accessibles, puisque situées en façade. Sur le générateur et le multimètre, la sélection des fonctions primaires s’établit directement au moyen de touches avec leds de validation intégrées. Un encodeur performant permet de réaliser efficacement les réglages et des touches contextuelles en bord d’écran indiquent clairement la configuration. Pour les oscilloscopes, en plus des accès directs aux fonctions essentielles par clavier et aux réglages par encodeur, le pilotage via la souris, sous environnement “Windows-like”, est totalement innovant dans cette catégorie d’appareil. Une technologie de leader, l’innovation jusqu’au bout des doigts Une lisibilité privilégiée, une Interface Homme-Machine conviviale (I.H.M.) Les qualités des MTX ne se limitent pas à leur physique. Ces instruments ont une tête bien faite, grâce notamment à leurs micro-processeurs 16 ou 32 bits de dernière génération, aux logiciels téléchargeables et à la calibration 100% numérique. Du point de vue de la sécurité, une protection électronique réarmable a permis la suppression du fusible secteur sur certains modèles. Tous les modèles de la famille MTX Compact peuvent disposer d’interfaces de communication performantes et du langage standard SCPI. Même le clavier de sélection est à la pointe de la technologie grâce à ses contacts à microswitches qui assurent une durabilité exceptionnelle de plus de 100 000 manoeuvres. Les touches bénéficient, quant à elles, d’une gravure laser inaltérable. Avec la famille MTX Compact, Metrix permet à chaque professionnel d’accéder à des Instruments “de haute couture”, dont vous ne pourrez plus vous passer Pour informations et commandes FRANCE Chauvin-Arnoux 190, rue Championnet 75876 PARIS Cedex 18 Tél : (33) 01 44 85 44 58 Fax : (33) 01 46 27 07 48 info@metrix.fr www.metrix.fr SUISSE Chauvin Arnoux AG Einsiedlerstraße 535 - 8810 HORGEN Tél : 01/727 75 55 Fax : 01/727 75 56 info@chauvin-arnoux.ch www.chauvin-arnoux.ch MOYEN-ORIENT Chauvin Arnoux Middle East Ain El Zalka, Immeuble Zalka 686 ZALKA (Beyrouth) Tél : +961 1 890 425 Fax : +961 1 890 424 camie@chauvin-arnoux.com www.chauvin-arnoux.com Cube 3D Printer 2nd generation ® User Guide See inside for use and safety information. Table of Contents Introduction 2 Important safety information EN 3 DE 4 ES 5 FR 6 IT 7 DU 8 DA 9 JP . 10 Cube 3D Printer features . 11 MTX 3250 Mull tt iimètt rre de Tablle 50 000 ptts mull tt ii ffonctt iion Multimètre-Analyseur MTX : la précision et le contrôle... ! • Très vaste affichage triple 50 000 pts pour une meilleure efficacité • Précision de base 0,08%, bande-passante 100 kHz • 3 bornes de mesure et «AUTORANGING» complet en courant • Fonction « SPEC » permettant de visualiser directement les incertitudes • Avec le mode « AUTOPEAK » plus de limitation du facteur de crête • Mesures fréquentielles jusqu’à 1 MHz, de la période et du rapport cyclique • Mesures de température à partir de sondes Pt 100 / Pt 1000 • Mode «MATH» pour une lecture directe (conversion & unité physique) • Un modèle programmable via RS232 selon protocole SCPI • Un modèle « Acquisition de données » avec enregistreur horodaté MTX Compactt Caractéristiques techniques MTX 3250 Tensions DC, AC et AC+DC Gammes 500 mV 5 V 50 V 500 V 600 V Résolution 10 μV 100 μV 1 mV 10 mV 100 mV Précision DC 0,08% L+3D 0,08% L+3D 0,08% L+3D 0,1% L+3D 0,1% L+3D Bande passante AC / AC+DC 40 Hz à 100 kHz/DC à 100 kHz Précision de base AC et AC+DC 0,5% L+30D (0,5% L+40D/gamme 500 mV) pour DC à 1 kHz Impédance d’entrée 10 MΩ/1 GΩ 11 MΩ 10 MΩ 10 MΩ 10 MΩ Protection / Surcharge admissible Protection réarmable 600 Vrms permanents/1000 VDC ou 700 VAC (1min max.) Courants DC, AC et AC+DC Gammes 500 μA 5 mA 50 mA 500 mA 10A Résolution 10 nA 100 nA 1 μA 10 μA 1mA Précision DC 0,2% L+5D 0,2% L+3D 0,2% L+3D 0,2% L+5D 0,5% L+5D Bande passante AC / AC+DC 40 Hz à 10 kHz/DC à 10 kHz Précision de base AC et AC+DC 0,5% L+30D (2,5% L+30D/gamme 10A) pour DC à 1 kHz Protection / Surcharge admissible Fusible HPC 10 A, 600 V/50 kA/20 ADC ou 20 Arms (30 s max.) Mesures Fréquentielles Fréquence (tension ou courant) Plage de mesure 1 Hz à 1 MHz - 7 gammes de 5,0000 Hz à 1,0000 MHz - Précision 0,03% L+2D jusqu’à 50 kHz Rapport Cyclique Résolution 0,01% - Période du signal de 10 μs à 0,8 s Résistances & Continuité Gammes 500 Ω 5 kΩ 50 kΩ 500 kΩ 5 MΩ 50 MΩ Résolution 10 mΩ 100 mΩ 1 Ω 10 Ω 100 Ω 1 kΩ Précision de base 0,1% L+5 D 0,1% L+3 D 0,1% L+3 D 0,1% L+3 D 0,5% L+3 D 1% L+5 D Protection Protection réarmable 600 Vrms Détection en continuité sonore Gamme 500 Ω - Seuil 10 Ω à 15 Ω - Temps de réponse 1ms Test de diode Mesures de tension de diode De 0 à 4,5 V - Précision 0,2% L+3D - courant de mesure 1 mA env. - Protection réarmable 600 Vrms Capacités Performances 7 Gammes de 50,00 nF à 50,00 mF - Précision de base 1%L+ 3D - Temps de mesure 1 s jusqu’à 50 μF Protection Protection réarmable 600 Vrms Température ( sondes Pt 100 / Pt 1000 ) Performances Plage de mesure –125,0 °C à +800,0 °C - Précision 0,5 °C (de –125 °C à 75 °C) - Protection réarmable 600 Vrms Autres Mesures Capture de pics rapides >500 μs Valide sur toutes les gammes - Erreur additionnelle en Tension 3% L+10D, en Courant 4% L+10D Mesure en dBm Résolution 0,01 dBm - Référence ajustable de 1 Ω à 9999 Ω - Protection réarmable 600 Vrms Puissance Résistive U2/R ou R I2 Résolution 100 μW - Référence ajustable de 1 Ω à 9999 Ω - Protection réarmable 600 Vrms Autres fonctions Fonction AUTOPEAK Surveillance permanente du facteur de crête (FC) et gestion automatique des gammes pour respecter le FC spécifié Fonction SPEC Calcul de la tolérance de mesure sous forme x% L+x D ou Min et Max sur les afficheurs 2 et 3 Fonction HOLD & AUTOHOLD Maintien manuel de l’affichage (HOLD) ou automatique sur mesure stable (AUTOHOLD) Fonction REL / fonction dB Mode triple affichage : valeur relative, valeur absolue, écart en % / écart en dB Fonction SURV Surveillance et mémorisation automatique des «MIN» et «MAX» avec horodatage des événements Fonction MATH Mise à l’échelle et à l’unité pour les grandeurs physiques (fonction y = Ax+B et unité définissables) Fonction STORE Acquisition de données (jusqu’à 3 mesures à la fois) - Cadence 0,5 s à 10 h - 10 mémoires & env. 1500 mesures Fonction PRINT Envoi direct sur imprimante série des mesures horodatées - Cadence 0,5 s à 10 h * choix de l’utilisateur à la mise sous tension Caractéristiques générales MTX 3250 Affichage Affichage triple 50 000 points - Dimensions utiles : 130 x 50 mm - Hauteur des chiffres 20 mm et 10 mm Cadence de Mesure 2 mesures par seconde (mode 50 000 pts) Rétroéclairage Affichage positif rétroéclairé par matrice de LED’s - Contraste réglable Température Référence 23°C ±5° (après 1 heure de chauffe) - Fonctionnement 0°C à +45°C - Stockage -20°C à +70°C Humidité Relative < 80 % à 40°C CEM / Sécurité Emission et immunité selon NF EN 61326-1, 1998 / IEC 61010, 2001 Alimentation Secteur 230 V ±10% ou 110 V ±10% (50 Hz – 60 Hz) - Cat.II/300V Alimentation Batterie (Option) Accumulateur 9,6 V - Autonomie 10 à 12 H environ (suivant les fonctions) Interface RS232 Optique (Option) Trame : 8 bits de données, 1 bit de stop, pas de parité - Vitesses sélectionnables 9600 & 57600 bauds Boîtier ABS V0 - Dimensions H/L/P : 170 x 270 x 195 mm - Masse : 2,8 kg - Indice de protection IP30 Caractéristiques sous réserve de modifications liées à l’évolution de la technologie 190, rue Championnet 75876 PARIS cedex 18 Tél. : 01 44 85 44 58 Fax : 01 46 27 07 48 Filiale suisse : Einsiedlerstrasse 535 8810 HORGEN Tél. : 01 / 727 75 55 - Fax : 01 / 727 75 56 Agences : Lille 03 20 55 96 41 Lyon 04 72 65 77 60 Nancy 03 83 92 19 21 Nantes 02 40 84 01 16 Paris 01 44 85 45 70 Rennes 02 99 22 80 80 Toulouse 05 62 74 50 30 Code : 906210045 - Ed.1-03/02 MTX 3250 : Multimètre 50 000 pts multifonction Pour commander : Etat de livraison : 1multimètre de table MTX 3250, 1 câble d’alimentation secteur, 1 jeu de cordons de mesure et 1 notice de fonctionnement. MTX3250 : Multimètre de table 50 000 pts MTX 3250 MTX3250-P : Multimètre de table 50 000 pts MTX 3250 + RS232 MTX3250-A : Multimètre de table 50 000 pts MTX 3250 + acquisitionAt a glance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Requirements for your Cube . 13 Unpacking and setting up your Cube 14 Link your Cube to your Cubify account 15 Unlock your Cube 16 Download and install Cube Software for Windows 16 Download and install Cube Software for Mac OSX . 17 Download your free creations 17 Cubify Software overview 18 WI-FI set-up . 20 Non-wireless computer set-up (without WI-FI options) 20 Update Cube firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Setting Print Jet gap 21 Material Cartridge installation 22 Printing preparation . 23 Printing your first creation 24-25 Replacing Material Cartridge . 26 Cloud printing from Cubify.com . 27 Finishing your creation 27 Maintaining your Cube . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Print Pad leveling instructions . 29 Thank you for purchasing the “Cube®” 3D Printer. This printer is portable with a plug and print design that enables everybody in the family to express their creativity like never before. With ten different material colors to choose from, enjoy the freedom to print in your true colors or to mix it up.Cube 3D Printers ready-to-print technology provides a new dimension to your imagination and helps you share your creations with others in the Cubify community at Cubify.com. At Cubify.com you can: • Upload your creations for sale • Purchase creations from others • Get your creations 3D printed and shipped to you • Buy the Cube 3D Printer and Cube Cartridges • Engage with other creative partners COPYRIGHT INFORMATION © 2013 by 3D Systems, Inc. All rights reserved. This document is subject to change without notice. This document is copyrighted and contains proprietary information that is the property of 3D Systems, Inc. Cubify, Cube, and the 3D Systems logo are registered trademarks of 3D Systems, Inc. Use of the Cubify.com website constitutes acceptance of its Terms of Service and Privacy Policy. FCC NOTICE This equipment has been tested and found to comply with the limits for a class “B” digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at their expense. WARRANTY 3D Systems warrants that the Cube 3D Printer will be free from defects in materials and workmanship, during the applicable warranty period, when used under the normal conditions described in the documentation provided to you, including this user’s guide. 3D Systems will promptly repair or replace the Cube 3D Printer, if required, to make it free of defects during the warranty period. This warranty excludes (i) normal consumable or expendable parts (such as Material Cartridges, Print Pads, and CubeStick), (ii) repairs required during the warranty period because of abnormal use or conditions (such as riots, floods, misuse, neglect or improper service by anyone except 3D Systems or its authorized service provider), and (iii) repairs required during the warranty period because of the use of non-integrated, non-approved or non-licensed materials in the Cube 3D Printer. The warranty period for the Cube 3D Printer is ninety (90) days and shall start on the date your Cube 3D printer is activated. For consumers who are covered by consumer protection laws or regulations in their country of residence, the benefits conferred by our ninety (90) day warranty are in addition to, and operate concurrently with, all rights and remedies conveyed by such consumers protection laws and regulations, including but not limited to these additional rights. THIS WARRANTY IS THE ONLY WARRANTY PROVIDED FOR THE CUBE 3D PRINTER. TO THE MAXIMUM EXTENT PERMITTED BY LAW, 3D SYSTEMS EXPRESSLY DISCLAIMS ALL OTHER WARRANTIES FOR THE CUBE 3D PRINTER AND EACH OF ITS COMPONENTS, WHETHER THOSE WARRANTIES ARE EXPRESS, IMPLIED OR STATUTORY INCLUDING WARRANTIES OF MERCHANTABILITY AND FITNESS FOR INTENDED OR PARTICULAR PURPOSES. LIMITATION OF LIABILITY 3D SYSTEMS WILL NOT BE RESPONSIBLE FOR CONSEQUENTIAL, EXEMPLARY OR INCIDENTAL DAMAGES (SUCH AS LOSS OF PROFIT OR EMPLOYEE’S TIME) REGARDLESS OF THE REASON. IN NO EVENT SHALL THE LIABILITY AND/OR OBLIGATIONS OF 3D SYSTEMS ARISING OUT OF THE PURCHASE, LEASE, LICENSE AND/OR USE OF THE EQUIPMENT BY YOU OR OTHERS EXCEED THE PURCHASE PRICE OF THE CUBE 3D PRINTER. 2 1 INTRODUCTION SAFETY SYMBOLS AND DEFINITIONS SAFETY GUIDELINES • Follow all safety rules in this section and observe all cautions and warnings in this guide. • Do not modify any safety features or make modifications to the Cube. Doing so is prohibited and voids warranty. • Use of print materials, or 3D prints other than 3D Systems print materials and genuine 3D Systems components may void warranty. • Adult supervision is required; observe children closely and intervene as necessary to prevent potential safety problems and ensure the Cube’s appropriate use. Ensure small 3D prints are not accessible to young children. These 3D prints are potential choking hazards for young children. • When the Cube is operating, the print tip on the Print Jet becomes hot; avoid touching this area until it has cooled down. • Do not change color of material during printing; doing so may damage the Cube. ! Hot Surface Hazard: A hot surface is accessible in the vicinity of this sign or at the Print Jet; avoid contact. Hot surfaces can cause severe burns. Caution: Indicates something may happen that could cause loss of data, damage to equipment, or could cause personal injury. Caution: Indicates a pinch point hazard that could cause person injury. 3 2 IMPORTANT SAFETY INFORMATION (EN) SICHERHEITSSYMBOLE UND DEFINITIONEN SICHERHEITSHINWEISE • Befolgen Sie alle Sicherheitsvorschriften in diesem Abschnitt und beachten Sie alle Vorsichtsmaßnahmen und Warnhinweise in diesem Handbuch. • Modifizieren Sie keine Sicherheitsmerkmale und nehmen Sie keine Änderungen am Cube-Drucker vor. Dies ist verboten und kann zum Erlöschen der Gewährleistung führen. • Die Verwendung von Druckmaterialien oder 3D-Drucken, die keine Originalteile von 3D Systems sind, kann zum Erlöschen der Gewährleistung führen. • Die Beaufsichtigung durch Erwachsene ist erforderlich; beobachten Sie Kinder genau und greifen Sie gegebenenfalls ein, um mögliche Sicherheitsprobleme zu vermeiden und um sicherzustellen, dass der Cube-Drucker ordnungsgemäß verwendet wird. Stellen Sie sicher, dass kleine 3D-Drucke für kleine Kinder nicht zugänglich sind. Diese 3D-Drucke bergen eine mögliche Erstickungsgefahr für kleine Kinder. • Wenn der Cube-Drucker in Betrieb ist, wird die Druckdüse am Print Jet heiß; vermeiden Sie es, diesen Bereich zu berühren, bis er abgekühlt ist. • Verändern Sie während des Druckens nicht die Farbe des Materials; dadurch kann der Cube-Drucker beschädigt werden. ! Gefahr durch heiße Oberflächen: Eine heiße Oberfläche ist in der Nähe dieses Zeichens oder am Print Jet zugänglich; vermeiden Sie jeglichen Kontakt. Heiße Oberflächen können schwere Verbrennungen verursachen. Achtung: Weist darauf hin, dass etwas passieren kann, was zum Verlust von Daten, zu Schäden an den Geräten oder zu Körperverletzungen führen könnte. Achtung: Weist auf eine Einklemmgefahr hin, die zu Körperverletzungen führen könnte. 4 2A WICHTIGE SICHERHEITSINFORMATIONEN (DE) SÍMBOLOS Y DEFINICIONES DE SEGURIDAD PAUTAS DE SEGURIDAD • Siga todas las normas de seguridad de esta sección y esté atento a todas las precauciones y advertencias en esta guía. • No modifique ninguna medida de seguridad ni realice modificaciones a la impresora Cube. Hacerlo está prohibido y anula la garantía. • El uso de materiales de impresión o de piezas impresas en 3D que no sean componentes auténticos de 3D Systems puede anular la garantía. • Se requiere la supervisión de un adulto; observe a los niños de cerca e intervenga cada vez que sea necesario para prevenir cualquier posible problema de seguridad y asegurar el uso adecuado de la impresora Cube. Asegúrese de que las piezas pequeñas impresas en 3D no estén al alcance de niños pequeños. Estas piezas impresas en 3D representan un posible peligro de asfixia para los niños pequeños. • Cuando la impresora Cube está funcionando, la punta de impresión se calienta; evite tocar esta área hasta que se haya enfriado. • No cambie el color de los materiales durante la impresión; esto puede dañar la impresora Cube. ! Peligro de superficie caliente: Una superficie caliente se encuentra cerca de esta señal o en la impresora; evite el contacto con esta. Las superficies calientes pueden causar quemaduras graves. Precaución: Indica que algo puede ocurrir y causar una pérdida de datos, daños al equipo o lesiones. Precaución: Indica un peligro de punto de pellizco que podría causar lesiones a una persona. 5 2B INFORMACIÓN IMPORTANTE SOBRE SEGURIDAD (ES) SYMBOLES DE SÉCURITÉ ET DÉFINITIONS CONSIGNES DE SÉCURITÉ • Suivez toutes les consignes de sécurité de cette section et respectez tous les messages d’avertissement du présent manuel. • Ne pas modifier les dispositifs de sécurité ou apporter des modifications au Cube. Cela est interdit et annule la garantie. • L’utilisation de matériaux d’impression ou d’imprimés en 3D autres que les composants 3D Systems d’origine peut entraîner l’annulation de la garantie. • La supervision d’un adulte est requise ; surveillez les enfants en restant à proximité et intervenez si nécessaire pour éviter tout problème de sécurité potentiel et garantir la bonne utilisation du Cube. Assurez-vous que les petits imprimés en 3D restent hors de portée des jeunes enfants. Ces imprimés en 3D présentent un risque d’étouffement pour les jeunes enfants. • Lorsque le Cube fonctionne, l’extrémité de l’imprimante peut chauffer ; évitez de toucher cette zone jusqu’à ce qu’elle est refroidie. • Ne pas modifier la couleur du matériau pendant l’impression ; cela peut endommager le Cube. ! Surface chaude: Une surface chaude est présente à proximité de ce symbole ou sur l’imprimante ; évitez de la toucher. Les surfaces chaudes peuvent causer de graves brûlures. Attention: Indique que quelque chose pourrait occasionner une perte des données, des dommages sur l’équipement ou des blessures. Attention: Indique un risque de pincement qui pourrait occasionner une blessure. 6 2C INFORMATIONS IMPORTANTES RELATIVES À LA SÉCURITÉ (FR) SIMBOLI E DEFINIZIONI DI SICUREZZA LINEE GUIDA DI SICUREZZA • Attenersi a tutte le norme di sicurezza contenute in questa sezione e rispettare le avvertenze e le precauzioni indicate nella guida. • Non alterare le caratteristiche di sicurezza né apportare modifiche a Cube. Queste operazioni sono vietate e determinano l’annullamento della garanzia. • L’utilizzo di materiali di stampa o di componenti di stampa 3D non originali di 3D Systems può comportare l’annullamento della garanzia. • È richiesta la supervisione di un adulto; tenere sotto stretta sorveglianza i bambini e, in caso di necessità, intervenire per evitare eventuali problemi di sicurezza e per garantire l’uso appropriato di Cube. Assicurarsi che i bambini non possano raggiungere i componenti più piccoli delle stampe 3D, poiché questi potrebbero costituire un pericolo di soffocamento. • Durante l’attività di Cube, la puntina di stampa del getto d’inchiostro si riscalda; evitare il contatto con quest’area fino al completo raffreddamento. • Non modificare il colore del materiale durante la stampa; quest’operazione potrebbe causare danni a Cube. ! Pericolo di superficie calda: In prossimità di questo simbolo o del getto d’inchiostro è presente una superficie calda; evitare il contatto. Le superfici calde possono causare ustioni gravi. Attenzione: Segnala che un determinato evento potrebbe causare la perdita di dati, danni all’impianto o lesioni personali. Attenzione: Segnala la presenza di una zona ad alto rischio che potrebbe causare lesioni personali. 7 2D INFORMAZIONI IMPORTANTI SULLA SICUREZZA (IT) VEILIGHEIDSSYMBOLEN EN DEFINITIES VEILIGHEIDSVOORSCHRIFTEN • Volg alle veiligheidsvoorschriften in dit gedeelte en neem alle opmerkingen en waarschuwingen in deze handleiding in acht. • Breng geen wijzigingen aan de veiligheidsvoorzieningen of de Cube aan. Dit is verboden en de garantie komt hierdoor te vervallen. • Door gebruik van printmaterialen of 3D-prints anders dan originele 3D Systems-onderdelen kan de garantie komen te vervallen. • Oezicht door een volwassene is vereist; houd kinderen nauwlettend in het oog en grijp zo nodig in om mogelijke veiligheidsproblemen te voorkomen en het juiste gebruik van de Cube te verzekeren. Zorg dat jonge kinderen niet bij kleine 3D-prints kunnen komen. Deze 3D-prints houden potentieel verstikkingsgevaar in voor jonge kinderen. • Wanneer de Cube in werking is, wordt de printtip op de Print Jet heet. Raak dit oppervlak niet aan totdat het is afgekoeld. • Wijzig de kleur van het materiaal niet tijdens het printen, anders kan de Cube worden beschadigd. ! Gevaar voor hete oppervlakken: Er is een toegankelijk heet oppervlak in de nabijheid van dit waarschuwingsteken of bij de Print Jet. Niet aanraken. Hete oppervlakken kunnen ernstige brandwonden veroorzaken. Let op: Duidt op iets wat kan gebeuren dat verlies van gegevens, beschadiging van de apparatuur of lichamelijk letsel kan veroorzaken. Let op: Duidt op een gevaarlijk knelpunt dat lichamelijk letsel kan veroorzaken. 8 2E BELANGRIJKE VEILIGHEIDSINFORMATIE (DU) SIKKERHEDSSYMBOLER OG -DEFINITIONER SIKKERHEDSRETNINGSLINIER • Følg alle sikkerhedsreglerne i denne sektion og overhold forsigtighedsregler og advarsler i denne vejledning. • Sikkerhedsfeatures må ikke modificeres og der må ikke foretages andre modifikationer til Cube. Det er forbudt at gøre det og det vil ugyldiggøre garantien. • Brugen af andre printmaterialer eller 3D prints end de ægte 3D Systems komponenter kan ugyldiggøre garantien. • Det er påkrævet at en voksen holder opsyn; hold nøje øje med børn og træd ind hvis det er nødvendigt for at undgå potentielle sikkerhedsproblemer og at sikre at Cube bruges rigtigt. Sørg for at små børn ikke har adgang til små 3D prints. Disse 3D prints kan udgøre en kvælningsfare for små børn. • Når Cube er i drift bliver spidsen på printaggregatet varm, så dette område må ikke røres før det er kølet af. • Materialets farve må ikke ændres under trykning; det kan beskadige Cube. ! Fare for varm overflade: Der findes en varm overflade i nærheden af dette skilt eller ved printaggregatet; undgå kontakt. Varme overflader kan forårsage alvorlige forbrændinger. Forsigtig: Viser at der kunne ske noget som kan resultere i datatab, beskadigelse af udstyr eller personskade. Forsigtig: Viser at der findes en knusefare, som kan forårsage personskade. 9 2F VIGTIG SIKKERHEDSINFORMATION (DA) 安全関連シンボルと定義 SIK 安全ガイドライン • 本項の安全ルールのすべてに従い、また本書のすべての要注意および警告事項を守ってください。 • 安全機能を修正したり、Cube に改変を加えたりしないでください。そうすることは禁じられており、保証は無効になります。 • 純正 3D Systems コンポーネント以外のプリント材料や 3D プリントの使用は、保証を無効にする場合があります。 • 大人の監視が必要です。子供が使用している時には身近で見守り、安全上の問題を未然に防ぎ、Cube が適切に使用されるよう、必要に応じて介入するようにしてください。小型の 3D プリントが幼児の手に届くことのないようにしてください。これらの 3D プリントは幼児にとっては、のどを詰まらせる危険物となります。 • Cube が動作中は、プリントジェット上のプリントチップが熱くなります。その部分が冷めるまでは、触れないようにしてください。 • プリント中に材料の色を変更しないでください。そうすると Cube を損傷させることがあります。 ! 高熱面の危険: このシンボルサインの近くまたはプリントジェット部には表面が高熱となっている部分があります。触れないように注意してください。高熱面で火傷することになります。 要注意: データの喪失、機器の損傷、または人身傷害を引き起こすような何かが起こる場合もあることを示します。 要注意: 人身傷害を引き起こす可能性のある危険個所を示します。 10 2G 安全に関する重要情報 (JP) The Print Jet print tip heats the material and produces a thin flowing material of plastic creating layers that adhere to the Print Pad. After each layer is produced, the Print Pad lowers so that a new layer can be drawn on top of the last. This process continues until the last layer on the top of the creation is jetted. CUBE 3D PRINTER FEATURES • Material Cartridge • Durable, ABS & PLA Plastic • 25 free 3D print creations • USB & WI-FI connectivity CUBE 3D PRINTER PROPERTIES Technology: Plastic Jet Printing (PJP) Print Jets: Single jet Max. Creation Size: 5.5” x 5.5” x 5.5” (140 x 140 x 140 mm) Material: Tough recyclable plastic Layer Thickness: 10 mil | 0.01 inches 250 microns | 0.25 mm Supports: Fully automated; easy to peel off Cartridge: 1 Cartridge prints 13 to 14 mid-sized creations Material Colors: See Cubify.com for color choices 11 3 CUBE 3D PRINTER FEATURES A Cube Tube B Print Jet C Print Pad D Operator’s Touchscreen F Material Cartridge G Fuse H Power Cord Connection I USB Port* J USB Connection** E ON/OFF Push-Button Power Switch & Menu Function RIGHT SIDE *For firmware update only. **For loading Cube build files only. A B C D E F BACK G H I J 12 4 AT A GLANCE WEIGHT & DIMENSIONS • Weight (without cartridge): 4.3 kg (9.5 lbs.) SOFTWARE • Complimentary software for Windows and Mac OSX. This application converts your 3D model into layered slices (G-code), ready for printing on your machine. MINIMUM HARDWARE REQUIREMENTS • A PC with these minimum requirements will be required to run the Cubify Software • Processor: Multi-core processor - 2 GHz or faster per core • System RAM: 2 GB • Screen Resolution: 1024x768 WINDOWS REQUIREMENTS • Cubify Software runs on 32 and 64-bit Operating Systems • Windows XP Professional or Home Edition with Service Pack 3 • Windows 7 • Windows is required for ad-hoc WiFi Print Job submission. NOTE: Ad-Hoc WI-FI connection will not connect to Windows XP operating systems • If not already installed, the Cubify Software installer will automatically install the Microsoft .NET 4.0 Framework WIRELESS OPTIONS • 802.11b/g with: WLAN Infrastructure or Ad hoc Mode. NON-WIRELESS OPTION • USB Memory Stick, to transfer print files (supplied with the Cube) MAC OSX REQUIREMENTS • Cubify Software runs on Mac OSX 10.8 ELECTRICAL REQUIREMENTS • Outlet requirements: 100-240 Volts, at 50/60 Hz. • Cube electrical rating: 24V DC, 3.75 amp. MATERIAL STORAGE • All polymers degrade with time. The following conditions ensure the material remains high quality: • Do not unpack until material is needed. • Store at room temperature: 16-29° C (60 - 85° F) OPERATING ENVIRONMENT • Room Temperature: 16-29° C (60 - 85° F) • Nozzle- 280°C (536°F) • Print Pad- 66-77° C (150-170°F) 13 11.25” (28.6 cm) 8” (20.3 cm) 8” (20.3 cm) 8” (20.3 cm) 8” (20.3 cm) 10” (25.4 cm) 13” (33 cm) 5 REQUIREMENTS FOR YOUR CUBE WALL Print Pad USB Cable** Cube Tube USB Stick Quick Start Guide CubeStick™ Unclog Tool*** The Cube Power Supply Material Cartridge* Power Cord cubify.com *Neon green included **For downloading firmware ***For unclogging filament in Print Jet SETTING UP YOUR CUBE 1. Remove the white plastic inserts from each side of the box by pinching the tabs in and bending the inserts out. Pull to remove both from the box. Lift top of carton up and remove. 2. Lift foam from the top of Cube. Remove foam from the midsection and below the plate by gently pulling out from the front. Remove Cube from box. 3. Lift foam that Cube was sitting on to access power supply and other accessories. 4. Remove the Print Pad from the foam under the Cube and set it aside. 5. Plug round connector of power supply into the back of the Cube. 6. Plug power cord into power supply, then into outlet or power strip. 14 6 UNPACKING AND SETTING UP YOUR CUBE Creating an account on Cubify.com is easy and gives you access to all of the great designs and collections that will drive and inspire your creativity. Once you have set up an account you will be able to activate your Cube by entering your Cube’s individual serial number in the designated bar under the Activate My Cube tab. An activation code will then be sent to the email account you used to register. This code will be used to unlock your Cube so that you can get your 3D printing underway. NOTE: If you do not receive an activation code email, please check your spam filter settings. 1. Go to Cubify.com and log in to your account or click Sign Up to create an account. 2. Click on Activate My Cube from My Cubify drop down menu. 3. Enter your 12-character serial number (digits and letters found on the back of your Cube), then click Activate. 4. Your Cube’s serial number is now activated on Cubify.com and your Cube will be assigned to your Cubify account. Your activation code will be displayed, and also sent to you in an e-mail along with links to help you get started creating. Make sure the email doesn’t get caught in your spam filter! 5. Using the links from your activation code email, or the My Cubes section in your account, you can download: • The Cube Software, which turns your 3D models into a file that the Cube can print. The software must be installed on your computer. Your Cube won’t print without it! • 25 free, ready-to-print 3D files created by top artists and designers (also on your USB stick) • Cube 3D Printer User Guide (also on your USB stick) • Material Safety Data Sheets 6. Now it is time to unlock your Cube so you can begin creating. NOTE: If you use a PC, you need Microsoft® Windows® 7 or XP (SP3+). If you use a Mac, you need Mac OSX 10.8+ 15 7 LINK YOUR CUBE TO YOUR CUBIFY ACCOUNT Once you’ve linked your Cube to your Cubify account, you can activate your Cube to start printing! 1. Your activation code to unlock your Cube will appear on the “Congratulations” screen after you activate your Cube in your Cubify account. A copy of the code should also be sent to your email. 2. Make sure your Cube is plugged in. Press the button on the front panel to turn it on. It may take a few seconds for it to warm up. 3. Tap on the touchscreen to view the Unlock Cube screen. 4. Enter your activation code and then tap on the check box to unlock your Cube. Your Cube will automatically transition to the main menu touchscreen and is now unlocked and ready to create! Download the Cube Software and experiment with it to create your own designs. 1. To download Cube Software, go to My Cubify and click on My Accounts. Click on My Downloads and select Cube software on the menu page. 2. Click on Setup.exe in the Cube Client.zip. The next screen will ask you if you would like to open this file. Click Yes. 3. The Cubify Setup Wizard will guide you through the steps to install the software on your computer. Click Next to launch the Setup Wizard. • It is necessary to download the Cube software in order to be able to import .stl or .creation files and convert them to .cube files. • The .cube file is a machine-specific file type that is coded for the Cube to read and print. 16 8 UNLOCK YOUR CUBE 9 DOWNLOAD AND INSTALL CUBE SOFTWARE FOR WINDOWS Download the Cube Software and experiment with it to create your own designs. 1. In the menu, Click on Download Cube Software. Double click on the zip file and the Cubify Mac installer.dmg will appear. 2. Double click Cubify Mac Installer dmg, to make a new window open. Drag to install into the Applications folder. 3. If the “Drag to install” window did not open, locate the Cubify driver in your device panel. Click on Cubify to download software. NOTE: Safari users will not have to unzip the dmg; it unzips as it downloads. • It is necessary to download the Cube software in order to be able to import .stl or .creation files and convert them to .cube files. • The .cube file is a machine-specific file type that is coded for the Cube to read and print. Follow these simple steps to access your 25 free creations: 1. Click on Download Free Creations to start your immediate download. 2. Click Extract in the Creation zip file and extract it to your computer. There are a couple of file types involved in 3D printing with your Cube: • .stl file: A 3-dimensional solid computer-aided design (CAD) file that defines the geometry to be printed. This is the typical file type output of a 3D design program or software tool. • .creation file: These files represent the pre-made 3D models that are optimized for your Cube and available on Cubify for download. Simply import your .creation file into the Cube software and click Build to prepare your creation for print. • .cube file: This is the machine code read by the Cube 3D Printer that enables it to build your print. 17 10 DOWNLOAD AND INSTALL CUBE SOFTWARE FOR MAC OSX 11 DOWNLOAD YOUR FREE CREATIONS Cubify Software allows you manipulate your design before sending it to the Cube for printing. It simulates the Cube’s Print Pad so you can orient, scale, re-size and rotate the 3D print to get the best result when printing. Become familiar with the software and understand the functions before starting your first print. IMPORT Select your creation file. CENTER Center your creation on the Print Pad; multiple items are auto-positioned. BUILD Creates the Cube file by adding support structures; the slicing process will prepare your creation. PRINT Transfers your creation to the Cube. HEAL Fix your creation. ORIENT & SCALE Rotate the X, Y, Z axis; move creation back & forth or side to side; increase or decrease your creation. These icons permit you to view your creation in various view points. After selecting a particular view, place your cursor on the part and hold the mouse button down; rotate the Print Pad to view different angles of the part. Isometric Right Left Front Back Top Bottom COLOR* Select your background and model color. SAVE Saves your creation without printing. UNLOAD Deletes your creation from the Cube software. CONFIGURE Connect your computer and the Cube via WI-FI using the USB cable. Also, download firmware upgrades. SETTINGS Choose your print size; turn rafts & supports ON or OFF. MODEL INFO Displays your creation information. * The color you select will not affect the color of your printed creation 18 12 CUBIFY SOFTWARE OVERVIEW SET UP A COMPUTER (AD HOC) NETWORK An ad hoc network is a temporary connection to your Cube through your computer or wireless smart phone. Ad hoc networks can only be wireless, so you must have a wireless network adapter installed in your computer to setup or join an ad hoc network. NOTE: Ad hoc will not connect to operating systems running Windows XP. 1. Tap on Setup in the main menu and scroll until you come to the WI-FI Setup screen. 2. Tap WI-FI Setup. 3. Tap on Ad Hoc in the menu screen. The next screen will show Ad Hoc mode enabled meaning it is ready to connect to your computer. 4. Open your Internet Access located in your Network Settings. NOTE: Always select your Cube from your network settings before opening Cube Software. 5. Select your Cube on the menu. Click on Connect. This may take a few minutes. 7. Open your Cube software and click on “Configure” and select your Cube from the menu. Click on “Connect;” once connected, you may begin to print your creation. 19 13 WI-FI SETUP SET UP A COMPUTER (WLAN) NETWORK WLAN (wireless local area network) allow easy establishment of a secure wireless network. WLAN connection will allow you to connect to your printer through the Cube Software. 1. Tap on Setup in the main menu and scroll until you come to the WI-FI Setup. 2. Tap on WI-FI Setup. 3. Tap on WLAN in the menu screen. “Acquiring networks” screen appears, meaning it is searching for available networks to connect to the printer. 4. Tap the on the touch screen to select your network. If your network is password protected, enter your password and tap on “OK.” 5. After your WI-FI is set up, if needed, the WI-FI firmware may update to the latest version if the latest firmware is not installed. NOTE: This will only occur when you are connecting to the network for the first time and if the WI-FI firmware needs updating. Once it is updated, the network will be successfully connected. 6. If the WI-FI firmware update was necessary, you may get one of two responses: (1) Network connected update successful; (2) Network connected... Update not successful. NOTE: If WiFi firmware update reported unsuccessful, the WLAN WiFi connection should still work. The WiFi firmware will try again with next connection attempt. 7. Click the function button to take you back to the main menu before printing 8. Open your Cube software and click on “Configure” and select your Cube from the menu. Click on “Connect;” once connected, you may begin to print your creation. 9. Open your Internet Access located on your computer’s taskbar. 10. Scroll and select the network on the menu. Click on Connect. This may take a few minutes. If you are not connected to a network, you can download your creations from your computer and save them to your USB Memory Stick for printing. • When printing with the USB Memory Stick, the file must be in the main folder located on the memory stick. If it is put into another folder it cannot be accessed from Cube screen. • Install your USB Memory Stick into your computer’s USB connection and save your creation to your USB Memory Stick. • When you are ready to print your creation, install your memory stick into the Cube’s USB connection and print your creations. 1. Tap on Setup on the Cube touch screen and scroll to Update Firmware. 2. If your USB Memory Stick is connected to the Cube, please remove the memory stick, (the screen will display the directions to do this). Tap the NEXT arrow on the display; locate the USB cable and connect the cable to the Cube USB port located on the back of the Cube (again, these instructions will be displayed on the screen). Connect the other end of cable to your computer’s USB port. NOTE: Never leave the USB cable connected except when upgrading the firmware. 3. Tap the NEXT arrow. SETTINGS SAVED will be displayed at the top of the screen. You will have 6 seconds to press and hold the control button until firmware loader appears on the screen. If the button is released before the firmware screen appears, the screen will go blank. Repeat Step 1 to restart the update firmware process. 4. Continue to hold button until Settings Saved and then Cube Firmware Loader appears on the touch screen. You are now in the correct mode to update your firmware. NOTE: Even though the update is unsuccessful, WLAN WI-FI should still work, To try again, simply reconnect to the network, 5. Open Cubify Software and click the Configure icon; click on Load New Cube Firmware. Once you see the pop-up message Firmware Updated Successfully, click OK. 6. Disconnect the USB cable from your Cube and computer; unplug the Cube power cord. Plug power cord back in and press the Cube power button; a message will display on the touchscreen “Setting restored,” click on the check mark to save settings. This does not change your previous settings that you have made. Your new firmware is now installed. 14 NON-WIRELESS COMPUTER SETUP 15 UPDATE CUBE FIRMWARE SWITCHING FROM AD-HOC TO WLAN CONNECTION (OR VICE VERSA) 1. Close out Cube Software. 2. Disconnect the Cube’s wireless connection through the Internet Access menu on your operating system. 3. Now follow steps for WLAN / ad-hoc set up. 4. Re-open your software after your Cube successfully connects to WLAN / ad-hoc. There must be an appropriate distance between the print tip and the Print Pad to make sure the first printed layer sticks properly. When the Cube is operating, the print tip on the Print Jet nozzle becomes hot; avoid touching this area until it has cooled down. 1. Make sure the textured side of the Print Pad is facing upwards. Place the magnetic side of the print pad onto the magnetic print plate. 2. Press Set Up on your Cube’s touchscreen and tap Next until Set Gap appears. 3. Select Set Gap. The Print Jet and Print Pad will move into position to set the gap. Place a standard piece of paper between the print tip and Print Pad. If the paper cannot slide between the tip and pad, tap the down arrow on the touchscreen until you can slide the paper between the tip and pad. 4. Press the Z up key to move the Print Pad toward the print tip until the paper is tight between the Print Pad and print tip. Tap the down key until the paper slides back and forth with no resistance. 5. Tap the check mark to save this setting to the printer’s memory. If the setting is saved, the “Gap” value will be applied for each subsequent print. If you wish to cancel this setting, tap the X box. 6. If you have any trouble printing after the gap setting has been saved, you can use this procedure at any time to change the gap. 7. Once the gap has been set, tap PREV to start the Load Cartridge process. ! 21 16 SETTING PRINT JET GAP 1. Use scissors to remove the cartridge from its packaging. 2. Tap Setup on your Cube’s touchscreen, select Load Cartridge, and press Next. 3. Remove the thumbscrew from the side of the Material Cartridge and remove the blue tape from the material. Save the screw to reinstall into cartridge if material was not fully used during printing. This will prevent filament from unravelling during storage. Press Next to begin cartridge installation. Do not pull out plastic until the thumbscrew is removed from the cartridge. Failure to remove the thumbscrew will damage the cartridge. 7. Filament will then be drawn into the Print Jet until a small amount comes out of the heated tip at the bottom. Carefully dispose of the filament without touching the hot print tip. Press Next. (If nothing comes out of the print tip, remove the plastic from the top of the Print Jet and repeat these installation steps.) WARNING: PRINT TIP BECOMES EXTREMELY HOT DURING SET-UP AND OPERATION. DO NOT TOUCH PRINT TIP. 8. Insert Cube Tube (the clear tube that’s already around the filament at the top) into the Print Jet. Press Next and your cartridge is loaded and ready to go! 4. Tilt cartridge so that bottom of cartridge is resting on cartridge holder. 5. Slide cartridge in the holder ensuring that top of cartridge feeder is seated into the Cube feeder. Do not slide cartridge without tilting, doing so can cause damage to t he Cube Feeder. 6. Insert the filament coming from the tube into the hole at the top of the Print Jet. Press Next, and continue to push filament into the Print Jet until it feeds through on its own. ! ! 22 17 MATERIAL CARTRIDGE INSTALLATION NOTE: CubeStick must be applied to the Print Pad every time you start a new creation. CAUTION: Do not use any adhesive other than the CubeStick. Doing so can damage your print tip and the Print Pad. Make sure you use the 2nd generation CubeStick for your 2nd generation Cube. WARNING: APPLY ADHESIVE JUST PRIOR TO STARTING A PRINT. ADHESIVE WILL DRY IF YOU WAIT TO START A PRINT AFTER APPLICATION. ADHESIVE SHOULD STILL BE WET AT START OF PRINT. 1. Find the CubeStick in the original packaging. 2. Remove Print Pad from the Cube. Apply a thin, even coat of adhesive on the entire top surface of the Print Pad. (Don’t over-apply!) Check the Print Pad after applying the adhesive to make sure there aren’t any gaps where the adhesive was not applied. If you find any gaps, apply adhesive to those areas. Never put glue on side with magnet. 3. Replace CubeStick cap after use. 4. Place Print Pad on the Print Pad platform. ! ! 23 18 PRINTING PREPARATION NOTE: Your Cube will have printed test creations before leaving the factory. These test creations may have been printed in a different material color than you are using. Therefore, a small amount of material may be remaining in the Print Jet. The start of your first creation may have some of this material color until it transitions over to your material color. WARNING: PRINT JET NOZZLE TIP BECOMES EXTREMELY HOT DURING SET-UP AND OPERATION. DO NOT TOUCH NOZZLE. Do not change color of material or cartridge during printing; doing so may damage the Cube. To get started printing your first creation; the creation files that were downloaded when you activated your account or a .stl file will need to be converted to a .Cube file. This is the machine code file that the Cube printer will read to build your creation. WI-FI CONNECTION if you wished to connect to WI-FI via Ad hoc or WLAN connection, please refer to Section 14: WI-FI Set-Up and follow the step by step instructions. Then resume these instructions and follow the steps below to connect to your Cube. These steps apply to both Ad Hoc and WLAN connections. 1. Open Cube Software and click on Configure. Click on your Cube model in the dialog box and click on Connect. Your computer is now connected to your Cube. 2. Click on Import and select a file from the creation files that you downloaded from Cubify.com or a .stl file. The creation that you selected will appear on Print Pad. The software’s Print Pad is a simulation of your Cube Print Pad. 3. In the software you can orient, scale, and manipulate your creation to ensure that you obtain the optimum printing results. Refer to Section 13: Cubify Software Overview to understand the different functions your software provides. 4. To prepare your creation file for printing, click on Build and save your creation as a .cube file. PRINTING WITH WI-FI CONNECTION 1. If have a WI-FI connection, click on Print and select the Cube file saved from your creation file; click on Open to send your file to the Cube. 2. On the Cube touchscreen, finger tap check box to start the build file or tap the X box to cancel. 3. The Cube will begin the heating process; this will take a few minutes. During the heating process, the print tip and the Print Pad will reach the temperatures that have been preset by the manufacturer. Once these temperatures are reached, your creation will begin to print. NOTE: During printing operation, please do not place a cover over your Cube. The Cube generates heat during printing and if covered, it can cause damage to the Cube. ! 24 19 PRINTING YOUR FIRST CREATION PRINTING YOUR FIRST CREATION (continued) PRINTING FROM THE USB MEMORY STICK 1. If you are using your USB Memory Stick to download your Cube file, please install the USB Memory Stick into the USB port on your computer. Open the file folder where your Cube file is located and save it on the USB Memory Stick. Remove memory stick and install it into the Cube’s USB port. 2. Tap Print on the touchscreen and use left or right arrows until you see your Cube file displayed. 3. Tap on your .cube file; the print touchscreen will appear showing the total time it will take to print your creation and the time left to complete it during printing. It also shows the maximum height of your creation and the current height while printing. 4. The Cube will begin the heating process that will take a few minutes. During the heating process, the print tip and the Print Pad will reach the temperatures that have been preset by the manufacturer. Once these temperatures are reached, your creation will begin to print. Once the creation is finished printing, your touch screen will display Print Finished, press the check box to confirm. Wait until the Print Pad is completely cool before removing your print. WARNING: PRINT JET NOZZLE TIP BECOMES EXTREMELY HOT DURING SET-UP AND OPERATION. DO NOT TOUCH NOZZLE. Do not change color of material or cartridge during printing; doing so may damage the Cube. ABORTING YOUR PRINT To abort your creation during warm up or printing, finger tap the STOP button on touchscreen. The next screen will read Are you sure you want to abort the print? Finger tap the check box to abort or tap the X box to cancel. Wait until the print tip completely cools before touching. ! 25 Do not change color of material or cartridge during printing; doing so may damage the Cube. 1. After being instructed by the touchscreen, pull Cube Tube away from top of Print Jet. Do not pull the material out until the touch screen instructs you to do so. 2. Pull material out of Print Jet and press Next. NOTE: After the material is pulled out from the print jet, material debris may be visible at the print tip that could clog the tip. Using the unclog tool, insert the tool’s point into the Print Jet; if debris is present, it will protrude from the print tip. 3. Tilt cartridge down to clear Cube feeder and remove cartridge from cube; remove the Cube Tube from material. Replace thumb screw into cartridge to hold the unused material in place. Refer to Step 18: Material Cartridge Installation for instructions on how to install your new cartridge. 26 20 REPLACING MATERIAL CARTRIDGE ! 1. Click on My Cubify and select My Account. 2. Click on My Downloads. 3. If you would like to download a file to save on your computer or print using Cube software, click on DOWNLOAD. The file will download to the Cube software on your computer to save your creation. 4. Your file can download directly to your Cube by clicking on PRINT ON MY CUBE; the Select Cube Printer screen will appear and will search for available Cube printers on your network. 5. If a Cube was not discovered in your network, you can either save the .cube file to your computer or connect through an ad hoc network (refer to PRINTING WITH WI-FI CONNECTION, page 25). 6. If a Cube is discovered in your network, you have a choice of printing now or decline printing. If you select print now, your print will start printing on the Cube you selected in the network. REMOVING YOUR CREATION FROM THE PRINT PAD • Place the Print Pad with your creation in a container (not supplied) filled with regular warm tap water and let it soak approximately five minutes or until your creation eases free from the Print Pad. Clean and dry the Print Pad before reuse. • To clean your Print Pad, rinse under tap water and dry with a lint-free wipe. REMOVING RAFTS AND SUPPORTS (IF REQUIRED) • Use small pliers to remove supports and rafts. In places where the supports are inside your creation and are hard to get to, use small wire snips (not provided) to remove the supports. 27 21 CLOUD PRINTING FORM CUBIFY.COM 22 FINISHING FIRST CREATION CLEANING THE EXTERIOR • Clean the Cube’s exterior with a lint free cloth and water. Dampen the cloth with water and wipe the outer surfaces of any debris that is visible. CLEANING THE PRINT PAD • Submerge the Print Pad in a container filled with warm tap water. Please do not use well water; it contains certain minerals that may make your creation difficult to remove from the Print Pad. • Rinse pad under tap water and dry using a lint free wipe. CLEANING THE PRINT TIP • Using the small pliers, pull away any plastic debris away from the Print Jet tip (if the debris is stubborn, the Print Jet may need to be heated to make the debris soft enough to remove). CLEANING THE TOUCHSCREEN WARNING: PRINT JET NOZZLE TIP BECOMES EXTREMELY HOT DURING SET-UP AND OPERATION. DO NOT TOUCH NOZZLE. • Wipe the touchscreen with the soft, lint-free cloth. Do not spray cleaners on the touchscreen. 4 AMP FUSE REPLACEMENT CAUTION: Before replacing the fuse, switch Cube’s power off and unplug power cord. 1. 4 Amp, 250 V fast blow fuse is located on the back left side of your Cube. 2. Using a flat screwdriver, turn screwdriver counterclockwise to remove fuse from the fuse holder. 3. Using a flat screwdriver, turn screwdriver clockwise to install new fuse into the fuse holder. After new fuse is installed, plug power cord into outlet and switch power on. ! ! 28 23 MAINTAINING YOUR CUBE Your Print Pad may become un-leveled when transporting your Cube. If this occurs, please follow these instructions to level your Print Pad for optimum creation experience. The Print Pad pad can be leveled with the two adjusting bolts located underneath the front and back of the pad. 1. Press the power button on the Cube control panel. 2. Ensure Print Pad is properly installed on print plate. 3. Finger tap SETUP on the touchscreen and scroll through the menu until LEVEL PLATE appears. Press LEVEL PLATE; the Print Pad will move up to Print Jet tip. 4. Using the Up arrow, raise the Print Pad to the Print Jet tip until the tip is near the Print Pad but not touching it. 5. Touch the “clockwise” and “counter-clockwise” buttons to automatically move the Print Jet around the four corners of the Print Pad. During each movement along the sides of the Print Pad, observe any gaps between the pad and the Print Jet. If there are gaps on one side of Print Pad and the Print Jet tip is barely touching the Print Pad on the other side, the Print Pad pad is not level. NOTE: Please refer to the FRONT TO BACK or SIDE TO SIDE instructions on how to turn the adjusting knob bolts to level the pad properly. 6. Place a standard sheet of paper between the Print Jet tip and the Print Pad where the adjustment needs to be made. If the paper cannot slide between the Print Jet tip and Print Pad, tap the down arrow key on touchscreen. ROLL SIDE TO SIDE If the gap between the Print Pad and Print Jet tip is at the right or left side, adjust the pad using the rear adjusting knob bolt (B). If the gap is too low, the pad is too low and will need to be moved up. 1. If the pad needs to be moved up, turn the front adjusting knob bolt (A) clockwise to loosen and then turn the rear adjusting knob bolt (B) clockwise. To move the pad down, turn the rear adjusting knob bolt (B) counterclockwise. 2. While adjusting, slide the paper between the Print Jet tip and Print Pad where the adjustment was needed; the paper should slide back and forth with no resistance. If resistance is felt, the pad is too high. Please repeat the adjustment. 3. Once adjustments are made, tighten the adjusting knob bolts. TILT FRONT TO BACK If the gap between the Print Pad and Print Jet tip is at the front or back of pad, adjust the pad using the rear adjusting knob bolt (B). If the gap appears on the side, the pad is too low and will need to be moved up. 1. If the pad needs to be moved up, turn the front adjusting knob bolt (A) clockwise to loosen and then turn the back adjusting knob bolt (B) clockwise. To move the pad down, turn the rear adjusting knob bolt (B) counterclockwise. 2. While adjusting, slide the paper between the Print Jet tip and Print Pad where the adjustment was needed; the paper should slide back and forth with no resistance. If resistance is felt, the pad is too high. Please repeat the adjustment. 3. Once adjustments are made, tighten the adjusting knob bolts. NOTE: After the print jet is adjusted, you will need to reset the print jet gap; please refer to Section 16: Setting Print Jet Gap. A B 29 24 PRINT PAD LEVELING INSTRUCTIONS 3D Systems, Inc. 333 Three D Systems Circle | Rock Hill, SC | 29730 Cubify.com ©2013 3D Systems, Inc. All rights reserved. The 3D Systems logo, Cube and Cubify are registered trademarks of 3D Systems, Inc. pn 350341-01, Rev. C This document was generated on 01/08/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 43375-1001 Status: Active Overview: Sabre™ Power Connector Description: Sabre™ Crimp Terminal, Female, Double 18 AWG, 4.57mm Max. Insulation Diameter, Reel Packaged, Tin (Sn) Plated Brass Contact with TPA Documents: Drawing (PDF) Product Literature (PDF) RoHS Certificate of Compliance (PDF) General Product Family Crimp Terminals Series 43375 Application Power Comments For double crimping of 18 AWG wire in a side-by-side orientation. Terminal mates to 3.18mm wide x 0.51mm ) thick flat blade PC tab. Allows 44441 receptacle housings to comply with the UL1977 finger proof access requirement Crimp Quality Equipment Yes MolexKits Yes Overview Sabre™ Power Connector Product Literature Order No 987650-5662 Product Name Sabre™ UPC 800754365994 Physical Durability (mating cycles max) 25 Gender Female Material - Metal Brass Material - Plating Mating Tin Material - Plating Termination Tin Net Weight 0.360/g Packaging Type Reel Plating min - Mating 0.508μm Plating min - Termination 0.508μm Termination Interface: Style Crimp or Compression Wire Insulation Diameter 4.57mm max. Wire Size AWG 14, 16, 18+18 Wire Size mm² N/A Electrical Current - Maximum per Contact 18A Voltage - Maximum 600V Material Info Reference - Drawing Numbers Product Specification RPSX-44441-001 Sales Drawing SD-43375-1001 Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 43375Series Mates With 43178 Male Crimp Terminals Use With 44441 Receptacle Housings Application Tooling | FAQ Tooling specifications and manuals are found by selecting the products below. Crimp Height Specifications are then contained in the Application Tooling Specification document. Global Description Product # Manual Extraction Tool 0638130500 Terminator Die - Doubles 0638405200 Hand Crimp Tool for Flat Blade Crimp Terminal 0638117300 Extraction Tool 0638132700 Mini-Mac™ Applicator 0638916100 Mini-Mac™ Applicator, For Narrow Insulation Crimp 0638917000 This document was generated on 01/08/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION This document was generated on 01/22/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 43031-0002 Status: Active Overview: Micro-Fit 3.0™ Connectors Description: Micro-Fit 3.0™ Crimp Terminal, Male, with Gold (Au) Plated Tin/Brass Alloy Contact, 20-24 AWG, Reel Documents: Drawing (PDF) RoHS Certificate of Compliance (PDF) Product Specification PS-43045 (PDF) Product Literature (PDF) Test Summary TS-43045-002 (PDF) General Product Family Crimp Terminals Series 43031 Application Power Crimp Quality Equipment Yes Overview Micro-Fit 3.0™ Connectors Packaging Alternative 43031-0008 (Loose) Product Literature Order No 987650-5984 Product Name Micro-Fit 3.0™ UPC 800754369411 Physical Gender Male Material - Metal Phosphor Bronze Material - Plating Mating Gold Material - Plating Termination Tin Net Weight 0.061/g Packaging Type Reel Plating min - Mating 0.381μm Plating min - Termination 2.540μm Termination Interface: Style Crimp or Compression Wire Insulation Diameter 1.85mm max. Wire Size AWG 20, 22, 24 Wire Size mm² N/A Material Info Reference - Drawing Numbers Product Specification PS-43045, RPS-43045-003, RPS-43045-004 Sales Drawing SD-43031-**** Test Summary TS-43045-002 Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 43031Series Mates With 43030 Application Tooling | FAQ Tooling specifications and manuals are found by selecting the products below. Crimp Height Specifications are then contained in the Application Tooling Specification document. Global Description Product # Extraction Tool 0011030043 Insertion Tool for Crimp Terminal 0638120800 Hand Crimp Tool 0638190000 FineAdjust™ Applicator for Insulation OD 1.30-1.85mm - 20-24 AWG 0639004500 FineAdjust™ Applicator for 0639018800 Insulation OD 1.10-1.30mm - 20-24 AWG FineAdjust™ Applicator for Insulation OD 0.91-1.09mm - 20-24 AWG 0639018900 T2 Terminator™ for insulation OD 1.30-1.85mm - 20-24 AWG 0639104500 T2 Terminator™ for insulation OD 1.10-1.30mm - 20-24 AWG 0639118800 T2 Terminator™ for insulation OD 0.91-1.09mm - 20-24 AWG 0639118900 This document was generated on 01/22/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION This document was generated on 04/14/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 39-28-8060 Status: Active Overview: Mini-Fit Jr.™ Power Connectors Description: Mini-Fit® Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 6 Circuits, PA Polyamide Nylon 6/6 94V-0, Tin (Sn) Plating, without Drain Holes Documents: 3D Model Packaging Specification PK-5566-003 (PDF) Drawing (PDF) Test Summary TS-5556-002 (PDF) Product Specification PS-5556-001 (PDF) RoHS Certificate of Compliance (PDF) Agency Certification CSA LR19980 UL E29179 General Product Family PCB Headers Series 5566 Application Power, Wire-to-Board Comments The 5566 header should be used with standard Mini- Fit® female terminals. If increased amperage of up to 13A per circuit is needed, please consider using the Mini-Fit® Plus HCS family 45750 terminals with 46015 headers; . See Molex Product specification PS-5666-001 for current de-rating information. Overview Mini-Fit Jr.™ Power Connectors Product Name Mini-Fit Jr.™ UPC 800753580732 Physical Breakaway No Circuits (Loaded) 6 Circuits (maximum) 6 Color - Resin Natural Durability (mating cycles max) 30 First Mate / Last Break No Flammability 94V-0 Glow-Wire Compliant No Guide to Mating Part No Keying to Mating Part None Lock to Mating Part Yes Material - Metal Brass Material - Plating Mating Tin Material - Plating Termination Tin Material - Resin Nylon Net Weight 1.778/g Number of Rows 2 Orientation Vertical PC Tail Length 3.50mm PCB Locator Yes PCB Retention None PCB Thickness - Recommended 1.60mm Packaging Type Bag Pitch - Mating Interface 4.20mm Pitch - Termination Interface 4.20mm Polarized to Mating Part Yes Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 5566Series Mates With 5557 Mini-Fit Jr.™ Receptacle Housing Polarized to PCB Yes Shrouded Fully Stackable No Surface Mount Compatible (SMC) No Temperature Range - Operating -40°C to +105°C Termination Interface: Style Through Hole Electrical Current - Maximum per Contact 9A Voltage - Maximum 600V Solder Process Data Duration at Max. Process Temperature (seconds) 5 Lead-free Process Capability Wave Capable (TH only) Max. Cycles at Max. Process Temperature 1 Process Temperature max. C 260 Material Info Old Part Number 5566-06A-210 Reference - Drawing Numbers Packaging Specification PK-5566-003 Product Specification PS-5556-001, RPS-5557-036, RPS-5557-058 Sales Drawing SD-5566-002 Test Summary TS-5556-002 This document was generated on 04/14/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION 1. General description The UHF EPCglobal Generation 2 standard allows the commercialized provision of mass adoption of UHF RFID technology for passive smart tags and labels. Main fields of applications are supply chain management and logistics for worldwide use with special consideration of European, US and Chinese frequencies to ensure that operating distances of several meters can be realized. The G2X is a dedicated chip for passive, intelligent tags and labels supporting the EPCglobal Class 1 Generation 2 UHF RFID standard. It is especially suited for applications where operating distances of several meters and high anti-collision rates are required. The G2X is a product out of the NXP Semiconductors UCODE product family. The entire UCODE product family offers anti-collision and collision arbitration functionality. This allows a reader to simultaneously operate multiple labels / tags within its antenna field. A UCODE G2X based label/ tag requires no external power supply. Its contact-less interface generates the power supply via the antenna circuit by propagative energy transmission from the interrogator (reader), while the system clock is generated by an on-chip oscillator. Data transmitted from interrogator to label/tag is demodulated by the interface, and it also modulates the interrogator’s electromagnetic field for data transmission from label/tag to interrogator. A label/tag can be operated without the need for line of sight or battery, as long as it is connected to a dedicated antenna for the targeted frequency range. When the label/tag is within the interrogator’s operating range, the high-speed wireless interface allows data transmission in both directions. In addition to the EPC specifications the G2X offers an integrated EAS (Electronic Article Surveillance) feature and read protection of the memory content. On top of the specification of the G2XL the G2XM offers 512-bit of user memory. SL3ICS1002/1202 UCODE G2XM and G2XL Rev. 3.8 — 11 November 2013 139038 Product data sheet COMPANY PUBLIC 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 2 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 2. Features and benefits 2.1 Key features  512-bit user memory (G2XM only)  240-bit of EPC memory  64-bit tag identifier (TID) including 32-bit unique serial number  Memory read protection  EAS (Electronic Article Surveillance) command  Calibrate command  32-bit kill password to permanently disable the tag  32-bit access password to allow a transition into the secured transmission state  Broad international operating frequency: from 840 MHz to 960 MHz  Long read/write ranges due to extremely low power design  Reliable operation of multiple tags due to advanced anti-collision  Forward link: 40-160 kbit/s  Return link: 40-640 kbit/s 2.2 Key benefits  High sensitivity provides long read range  Low Q-factor for consistent performance on different materials  Improved interference suppression for reliable operation in multi-reader environment  Large input capacitance for ease of assembly and high assembly yield  Highly advanced anti-collision resulting in highest identification speed  Reliable and robust RFID technology suitable for dense reader and noisy environments 2.3 Custom commands  EAS Alarm Enables the UHF RFID tag to be used as EAS tag without the need for a backend data base.  Read Protect Protects all memory content including CRC16 from unauthorized reading.  Calibrate Activates permanent back-scatter in order to evaluate the tag-to-reader performance. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 3 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 3. Applications  Supply chain management  Item level tagging  Asset management  Container identification  Pallet and case tracking  Product authentication Outside above mentioned applications, please contact NXP Semiconductors for support. 4. Ordering information Table 1. Ordering information G2XM Type number Package Name Description Version SL3ICS1002FUG/V7AF Wafer Bumped die on sawn wafer - SL3S1002FTB1 XSON3 plastic extremely thin small outline package;3 terminals; body 1 x 1.45 x 0,5 mm SOT1122 Table 2. Ordering information G2XL Type number Package Name Description Version SL3ICS1202FUG/V7AF Wafer Bumped die on sawn wafer - SL3S1202FTB1 XSON3 plastic extremely thin small outline package;3 terminals; body 1 x 1.45 x 0,5 mm SOT1122 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 4 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 5. Block diagram The SL3ICS1002/1202 IC consists of three major blocks: - Analog RF Interface - Digital Controller - EEPROM The analog part provides stable supply voltage and demodulates data received from the reader for being processed by the digital part. Further, the modulation transistor of the analog part transmits data back to the reader. The digital section includes the state machines, processes the protocol and handles communication with the EEPROM, which contains the EPC and the user data. Fig 1. Block diagram of G2X IC 001aai335 MOD DEMOD VREG VDD data in data out R/W ANALOG RF INTERFACE PAD PAD RECT DIGITAL CONTROL ANTENNA ANTICOLLISION READ/WRITE CONTROL ACCESS CONTROL EEPROM INTERFACE CONTROL RF INTERFACE CONTROL EEPROM MEMORY SEQUENCER CHARGE PUMP 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 5 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 6. Wafer layout and pinning information 6.1 Wafer layout (1) X-scribe line width: 56.4 m (2) Y-scribe line width: 56.4 m (3) Chip step, x-length: 488.0 m (4) Chip step, y-length: 470,0 m (5) Bump to bump distance X (TP1 - RFN): 351,0 m (6) Bump to bump distance Y (RFN - RFP): 333,0 m (7) Distance bump to metal sealring X: 40,3 m (8) Distance bump to metal sealring Y: 40,3 m Bump size X x Y: 60 m x 60 m Fig 2. Wafer layout and pinning information not to scale! 001aai346 (1) (7) (2) (8) (5) (6) (4) (3) Y X TP2 TP1 RFN RFP 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 6 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 7. Package outline Fig 3. Package outline SOT1122 Outline References version European projection Issue date IEC JEDEC JEITA SOT1122 MO-252 sot1122_po Unit mm max nom min 0.50 0.04 0.55 0.425 0.30 0.25 0.22 0.35 0.30 0.27 A(1) Dimensions Notes 1. Dimension A is including plating thickness. 2. Can be visible in some manufacturing processes. SOT1122 A1 D 1.50 1.45 1.40 1.05 1.00 0.95 E e e1 0.55 0.50 0.47 0.45 0.40 0.37 b b1 L L1 09-10-09 XSON3: plastic extremely thin small outline package; no leads; 3 terminals; body 1 x 1.45 x 0.5 mm D E e1 e A1 b1 L1 L e1 0 1 2 mm scale 3 1 2 b 4× (2) 4× (2) A pin 1 indication type code terminal 1 index area 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 7 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 3. Pin description of SOT1122 Symbol Pin Description RFP 1 Ungrouded antenna connector RFN 2 Grounded antenna connector n.c. 3 not connected Table 4. SOT1122 Marking Type Type code (Marking) Comment SL3S1202FTB1 UL UCODE G2XL SL3S1002FTB1 UM UCODE G2XM 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 8 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 8. Mechanical specification 8.1 Wafer specification See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**”. 8.1.1 Wafer • Designation: each wafer is scribed with batch number and wafer number • Diameter: 200 mm (8”) • Thickness: 150 m ± 15 m • Number of pads 4 • Pad location: non diagonal/ placed in chip corners • Distance pad to pad RFN-RFP 333.0 μm • Distance pad to pad TP1-RFN: 351.0 μm • Process: CMOS 0.14 μm • Batch size: 25 wafers • Dies per wafer: 120.000 8.1.2 Wafer backside • Material: Si • Treatment: ground and stress release • Roughness: Ra max. 0.5 m, Rt max. 5 m 8.1.3 Chip dimensions • Die size without scribe: 0.414 mm x 0.432 mm = 0.178 mm2 • Scribe line width: x-dimension:56.4 m (width is measured on top metal layer) y-dimension: 56.4 m (width is measured on top metal layer) 8.1.4 Passivation on front • Type Sandwich structure • Material: PE-Nitride (on top) • Thickness: 1.75 m total thickness of passivation 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 9 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 8.1.5 Au bump • Bump material: > 99.9% pure Au • Bump hardness: 35 – 80 HV 0.005 • Bump shear strength: > 70 MPa • Bump height: 18 m • Bump height uniformity: – within a die: ± 2 m – within a wafer: ± 3 m – wafer to wafer: ± 4 m • Bump flatness: ± 1.5 m • Bump size: – RFP, RFN 60 x 60 m – TP1, TP2 60 x 60 m – Bump size variation: ± 5 m • Under bump metallization: sputtered TiW 8.1.6 Fail die identification No inkdots are applied to the wafer. Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of mechanical/visual inspection. See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**” 8.1.7 Map file distribution See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**” 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 10 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 9. Limiting values [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. [3] For ESD measurement, the die chip has been mounted into a CDIP20 package. Table 5. Limiting values[1][2] In accordance with the Absolute Maximum Rating System (IEC 60134) Voltages are referenced to RFN Symbol Parameter Conditions Min Max Unit Die Tstg storage temperature range -55 +125 C Toper operating temperature -40 +85 C VESD electrostatic discharge voltage Human body model [3] - 2 kV SOT1122 Tstg storage temperature range -55 +125 C Ptot total power dissipation - 30 mW Toper operating temperature -40 +85 C VESD electrostatic discharge voltage Human body model - 2 kV 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 11 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 10. Characteristics 10.1 Wafer characteristics [1] Power to process a Query command [2] Measured with a 50  source impedance [3] At minimum operating power [4] Values measured for a 40 kHz phase reserval command under matched conditions 10.2 Package characteristics [1] Measured with network analyzer at 915 MHz; values at 0.5 dBm after peakmax of on-set of die, measured in the center of the pads. Table 6. Wafer characteristics Symbol Parameter Conditions Min Typ Max Unit Memory characteristics tRET EEPROM data retention Tamb  55 C 50 - - year NWE EEPROM write endurance Tamb  55 C 100000 - - cycle Interface characteristics Ptot total power dissipation - 30 mW foper operating frequency 840 - 960 MHz Pmin minimum operating power supply [1][2] - -15 - dBm Ci input capacitance (parallel) [3] - 0.88 - pF Q quality factor (Im (Zchip) / Re (Zchip)) [3] - 9 - - Z impedance (915 MHz) - 22 - j195 -  - modulated jammer suppression 1.0 MHz [4] - - 4 - dB - unmodulated jammer suppression 1.0 MHz [4] - - 4 - dB Table 7. Package interface characteristics Symbol Parameter Conditions Min Typ Max Unit Interface characteristics SOT1122 Ci input capacitance (parallel) [1] - 1.02 - pF Z SOT1122 impedance (915 MHz) - 18.6 - j171.2 -  139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 12 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 11. Packing information 11.1 Wafer See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**”. 11.2 SOT1122 Part orientation T1. For details please refer to http://www.standardics.nxp.com/packaging/packing/pdf/sot886.t1.t4.pdf. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 13 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 12. Functional description 12.1 Power transfer The interrogator provides an RF field that powers the tag, equipped with a UCODE G2X. The antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the G2X on the tag. The RF field, which is oscillating on the operating frequency provided by the interrogator, is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC. The antenna that is attached to the chip may use a DC connection between the two antenna pads. Therefore the G2X also enables loop antenna design. Possible examples of supported antenna structures can be found in the reference antenna design guide. 12.2 Data transfer 12.2.1 Reader to G2X Link An interrogator transmits information to the UCODE G2X by modulating an RF signal in the 840 MHz - 960 MHz frequency range. The G2X receives both information and operating energy from this RF signal. Tags are passive, meaning that they receive all of their operating energy from the interrogator's RF waveform. An interrogator is using a fixed modulation and data rate for the duration of at least an inventory round. It communicates to the G2X by modulating an RF carrier using DSB-ASK, SSB-ASK or PR-ASK with PIE encoding. For further details refer to Section 17, Ref. 1, section 6.3.1.2. Interrogator-to-tag (R=>T) communications. 12.2.2 G2X to reader Link An interrogator receives information from the UCODE G2X by transmitting a continuous-wave RF signal to the tag; the G2X responds by modulating the reflection coefficient of its antenna, thereby generating modulated sidebands used to backscatter an information signal to the interrogator. The system is a reader talks first (RTF) system, meaning that a G2X modulates its antenna reflection coefficient with an information signal only after being directed by the interrogator. G2X backscatter is a combination of ASK and PSK modulation depending on the tuning and bias point. The backscattered data is either modulated with FM0 baseband or Miller sub carrier. For further details refer to Section 17, Ref. 1, section 6.3.1.3. tag-to-interrogator (T=>R) communications. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 14 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 12.3 Operating distances RFID tags based on the UCODE G2X silicon may achieve maximum operating distances according the following formula: (1) (2) [1] CEPT/ETSI regulations [CEPT1], [ETSI1]. [2] New CEPT/ETSI regulations. [ETSI3]. [3] FCC 47 part 15 regulation [FCC1]. [4] These read distances are maximum values for general tags and labels. Practical usable values may be lower due to damping by object materials and environmental conditions. A special tag antenna design can help achieve higher values. The typical write range is > 50% of the read range. Table 8. Symbol description Symbol Description Unit Ptag minimum required RF power for the tag W Gtag gain of the tag antenna - EIRP transmitted RF power m  wavelength m Rmax maximum achieved operating distance for a /2-dipole m  loss factor assumed to be 0.5 considering matching and package losses - R distance m Table 9. Operating distances for UCODE G2X based tags and labels in released frequency bands Frequency range Region Available power Calculated read distance single antenna [4] Unit 868.4 to 868.65 MHz (UHF) Europe [1] 0.5 W ERP 3.6 m 865.5 to 867.6 MHz (UHF) Europe [2] 2 W ERP 7.1 m 902 to 928 MHz (UHF) America [3] 4 W EIRP 7.5 m Ptag EIRP Gtag  4R ----------  2 =    Rmax EIRP  Gtag  2 42Ptag = ---------------------------------------   139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 15 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 12.4 Air interface standards The G2X is certified according EPCglobal 1.0.9 and fully supports all parts of the "Specification for RFID Air Interface EPCglobal, EPCTM Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz - 960 MHz, Version 1.1.0". EPCglobal compliance and interoperability certification 􀀚􀀖􀀑􀀒􀀒􀀑􀀒􀀓􀀗􀀑􀀑􀀑􀀑􀀑􀀑􀀖􀀔􀀘 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 16 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 13. Physical layer and signaling 13.1 Reader to G2X communication 13.1.1 Physical layer For interrogator-to-G2X link modulation refer to Section 17, Ref. 1, annex H.1 Baseband waveforms, modulated RF, and detected waveforms. 13.1.2 Modulation An interrogator sends information to one or more G2X by modulating an RF carrier using double-sideband amplitude shift keying (DSB-ASK), single-sideband amplitude shift keying (SSB-ASK) or phase-reversal amplitude shift keying (PR-ASK) using a pulse-interval encoding (PIE) format. The G2X receives the operating energy from this same modulated RF carrier. Section 17, Ref. 1: Annex H, as well as chapter 6.3.1.2.2. The G2X is capable of demodulating all three modulation types. 13.1.3 Data encoding The R=>T link is using PIE. For the definition of the therefore relevant reference time interval for interrogator-to-chip signaling (Tari) refer to Section 17, Ref. 1, chapter 6.3.1.2.3. The Tari is specified as the duration of a data-0. 13.1.4 Data rates Interrogators shall communicate using Tari values between 6.25 s and 25 s, inclusive. For interrogator compliance evaluation the preferred Tari values of 6.25 s, 12.5 s or 25 s should be used. For further details refer to Section 17, Ref. 1, chapter 6.3.1.2.4. 13.1.5 RF envelope for R=>T A specification of the relevant RF envelope parameters can be found in Section 17, Ref. 1, chapter 6.3.1.2.5. 13.1.6 Interrogator power-up/down waveform For a specification of the interrogator power-up and power-down RF envelope and waveform parameters refer to Section 17, Ref. 1, chapters 6.3.1.2.6 and 6.3.1.2.7. 13.1.7 Preamble and frame-sync An interrogator shall begin all R=>T signaling with either a preamble or a frame-sync. A preamble shall precede a Query command and denotes the start of an inventory round. For a definition and explanation of the relevant R=>T preamble and frame-sync refer to Section 17, Ref. 1, chapter 6.3.1.2.8. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 17 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 13.2 G2X to reader communication An interrogator receives information from a G2X by transmitting an unmodulated RF carrier and listening for a backscattered reply. The G2X backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. For further details refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.1 Modulation The UCODE G2X communicates information by backscatter-modulating the amplitude and/or phase of the RF carrier. Interrogators shall be capable of demodulating either demodulation type. 13.2.2 Data encoding The encoding format, selected in response to interrogator commands, is either FM0 baseband or Miller-modulated subaltern. The interrogator commands the encoding choice 13.2.2.1 FM0 baseband FM0 inverts the baseband phase at every symbol boundary; a data-0 has an additional mid-symbol phase inversion. For details on FM0 and generator state diagram, FM0 symbols and sequences and how FM0 transmissions should be terminated refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.2.2 FM0 Preamble T=>R FM0 signaling begin with one of two defined preambles, depending on the value of the TRext bit specified in the Query command that initiated the inventory round. For further details refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.2.3 Miller-modulated sub carrier Baseband Miller inverts its phase between two data-0s in sequence. Baseband Miller also places a phase inversion in the middle of a data-1 symbol. For details on Miller-modulated sub carrier, generator state diagram, sub carrier sequences and terminating sub carrier transmissions refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.2.4 Miller sub carrier preamble T=>R sub carrier signaling begins with one of the two defined preambles. The choice depends on the value of the TRext bit specified in the Query command that initiated the inventory round. For further details refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.3 Data rates The G2X IC supports tag to interrogator data rates and link frequencies as specified in Section 17, Ref. 1, chapter 6.3.1.3. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 18 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 13.3 Link timing For the interrogator interacting with a UCODE G2X equipped tag population exact link and response timing requirements must be fulfilled, which can be found in Section 17, Ref. 1, chapter 6.3.1.6. 13.3.1 Regeneration time The regeneration time is the time required if a G2X is to demodulate the interrogator signal, measured from the last falling edge of the last bit of the G2X response to the first falling edge of the interrogator transmission. This time is referred to as T2 and can vary between 3.0 Tpri and 20 Tpri. For a more detailed description refer to Section 17, Ref. 1, chapter 6.3.1.6. 13.3.2 Start-up time For a detailed description refer to Section 17, Ref. 1, chapter 6.3.1.3.4. 13.3.3 Persistence time An interrogator chooses one of four sessions and inventories tags within that session (denoted S0, S1, S2, and S3). The interrogator and associated UCODE G2X population operate in one and only one session for the duration of an inventory round (defined above). For each session, a corresponding inventoried flag is maintained. Sessions allow tags to keep track of their inventoried status separately for each of four possible time-interleaved inventory processes, using an independent inventoried flag for each process. Two or more interrogators can use sessions to independently inventory a common UCODE G2X chip population. A session flag indicates whether a G2X may respond to an interrogator. G2X chips maintain a separate inventoried flag for each of four sessions; each flag has symmetric A and B values. Within any given session, interrogators typically inventory tags from A to B followed by a re-inventory of tags from B back to A (or vice versa). Additionally, the G2X has implemented a selected flag, SL, which an interrogator may assert or deassert using a Select command. For a description of Inventoried flags S0 – S3 refer to Section 17, Ref. 1 chapter 6.3.2.2 and for a description of the Selected flag refer to Section 17, Ref. 1, chapter 6.3.2.3. For tag flags and respective persistence time refer to Section 17, Ref. 1, table 6.14. 13.4 Bit and byte ordering The transmission order for all R=>T and T=>R communications respects the following conventions: • within each message, the most-significant word is transmitted first, and • within each word, the most-significant bit (MSB) is transmitted first, whereas one word is composed of 16 bits. To represent memory addresses and mask lengths EBV-8 values are used. An extensible bit vector (EBV) is a data structure with an extensible data range. For a more detailed explanation refer to Section 17, Ref. 1, Annex A. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 19 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 13.5 Data integrity The G2X ignores invalid commands. In general, "invalid" means a command that (1) is incorrect given the current the G2X state, (2) is unsupported by the G2X, (3) has incorrect parameters, (4) has a CRC error, (5) specifies an incorrect session, or (6) is in any other way not recognized or not executable by the G2X. The actual definition of "invalid" is state-specific and defined, for each G2X state, in n Section 17, Ref. 1 Annex B and Annex C. All UCODE G2X backscatter error codes are summarized in Section 17, Ref. 1 Error codes, Annex I. For a detailed description of the individual backscatter error situations which are command specific please refer to the Section 17, Ref. 1 individual command description section 6.3.2.10. 13.6 CRC A CRC-16 is a cyclic-redundancy check that an interrogator uses when protecting certain R=>T commands, and the G2X uses when protecting certain backscattered T=>R sequences. To generate a CRC-16 an interrogator or the G2X first generates the CRC-16 precursor shown in Section 17, Ref. 1 Table 6.11, then take the ones-complement of the generated precursor to form the CRC-16. For a detailed description of the CRC-16 generation and handling rules refer to Section 17, Ref. 1, chapter 6.3.2.1. The CRC-5 is only used to protect the Query command (out of the mandatory command set). It is calculated out of X5 + X3 + 1. For a more detailed CRC-5 description refer to Section 17, Ref. 1, table 6.12. For exemplary schematic diagrams for CRC-5 and CRC-16 encoder/decoder refer to Section 17, Ref. 1, Annex F. For a CRC calculation example refer to Section 15.1, Table 27 and Table 28. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 20 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14. TAG selection, inventory and access This section contains all information including commands by which a reader selects, inventories, and accesses a G2X population An interrogator manages UCODE G2X equipped tag populations using three basic operations. Each of these operations comprises one or more commands. The operations are defined as follows Select: The process by which an interrogator selects a tag population for inventory and access. Interrogators may use one or more Select commands to select a particular tag population prior to inventory. Inventory: The process by which an interrogator identifies UCODE G2X equipped tags. An interrogator begins an inventory round by transmitting a Query command in one of four sessions. One or more G2X may reply. The interrogator detects a single G2X reply and requests the PC, EPC, and CRC-16 from the chip. An inventory round operates in one and only one session at a time. For an example of an interrogator inventorying and accessing a single G2X refer to Section 17, Ref. 1, Annex E. Access: The process by which an interrogator transacts with (reads from or writes to) individual G2X. An individual G2X must be uniquely identified prior to access. Access comprises multiple commands, some of which employ one-time-pad based cover-coding of the R=>T link. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 21 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.1 G2X Memory For the general memory layout according to the standard Section 17, Ref. 1, refer to Figure 6.17. The tag memory is logically subdivided into four distinct banks. In accordance to the standard Section 17, Ref. 1, section 6.3.2.1. The tag memory of the SL3ICS1002 G2XM is organized in following 4 memory sections: The logical address of all memory banks begin at zero (00h). Table 10. G2X memory sections Name Size Bank Reserved memory (32 bit ACCESS and 32 bit KILL password) 64 bit 00b EPC (excluding 16 bit CRC-16 and 16 bit PC) 240 bit 01b TID (including unique 32 bit serial number) 64 bit 10b User memory (G2XM only) 512 bit 11b Fig 4. G2X TID memory structure Serial Number Model Number Mask-Designer Identifier Class Identifier TID 0 31 0 11 0 11 0 7 3Fh 20h 1Fh 14h 13h 08h 07h 00h 0 6 0 4 1Fh 19h 18h 14h Version Number Sub Version Number 00000001h to FFFFFFFFh 006h E2h Whenever the 32 bit serial is exceeded the sub version is incremented by 1 Addresses 3Fh 00h Addresses Addresses Bits Bits LS Byte LSBit MSBit LSBit MSBit MS Byte LSBit MSBit LSBit MSBit 0000010b 00000b Sub Version Nr Version (Silicon) Nr Model Nr. Mask ID UCode EPC G2XM 00000b 0000011b 003h 006h UCode EPC G2XL 00000b 0000100b 004h 006h 002h 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 22 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.1.1 Memory map [1] This is the initial memory content when delivered by NXP Semiconductors [2] G2XL: HEX 3005 FB63 AC1F 3841 EC88 0467 G2XM: HEX 3005 FB63 AC1F 3681 EC88 0468 [3] only G2XM Table 11. Memory map Bank address Memory address Type Content Initial [1] Remark Bank 00 00h – 1Fh Reserved kill password: refer to Section 17, Ref. 1, chapter 6.3.2.1.1 all 00h unlocked memory 20h – 3Fh Reserved access password: refer to Section 17, Ref. 1, chapter 6.3.2.1.1 all 00h unlocked memory Bank 01 00h – 0Fh EPC CRC-16: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 memory mapped calculated CRC 10h – 14h EPC Backscatter length: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 00110b unlocked memory 15h EPC Reserved for future use: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 0b unlocked memory 16h EPC Reserved for future use: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 0b hardwired to 0 17h –1Fh EPC Numbering system indicator: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 00h unlocked memory 20h - 10Fh EPC EPC: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 [2] unlocked memory Bank 10 00h – 07h TID allocation class identifier: refer to Section 17, Ref. 1, chapter 6.3.2.1.3 1110 0010b locked memory 08h – 13h TID tag mask designer identifier: refer to Section 17, Ref. 1, chapter 6.3.2.1.3 0000 0000 0110b locked memory 14h – 1Fh TID tag model number: refer to Section 17, Ref. 1, chapter 6.3.2.1.3 TMNR locked memory 20h – 3Fh TID serial number: refer to [Section 17, Ref. 1, chapter 6.3.2.1.3 SNR locked memory Bank 11[3] 00h – 1FFh User user memory: refer to [Section 17, Ref. 1, chapter 6.3.2.1.4 undefined unlocked memory 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 23 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.1.1.1 User memory (only G2XM) The User Memory bank contains a sequential block of 512 bits (32 words of 16 bit) ranging from address 00h to 1Fh. The user memory can be accessed via Select, Read or Write command and it may be write locked, permanently write locked, unlocked or permanently unlocked. In addition reading of not only of the User Memory but of the whole memory including EPC and TID can be protected by using the custom ReadProtect command. 14.1.1.2 Special behavior of user memory address 1Fh WRITE or SELECT of user memory address 1Fh will falsely set an error flag. This will affect the subsequent READ or SELECT. The following commands will falsely set an internal error flag (without actually causing an error): 1) WRITE to user memory with WordPtr=1Fh 2) SELECT to user memory with compare mask ending at bitaddress 1FFh (e.g. Pointer=1FEh, length=1 or Pointer=1FDh, length=2 …) Note: The error flag is set independent of the chip state (also chips in the e.g. Ready state are affected). The falsely set error flag will affect the following sub sequential commands: A) READ command with WordCount=0 falsely responds with "memory overrun" error B) SELECT command with Length<>0  falsely assumes non existing memory location The behavior can be avoided with: • Turning off the RF carrier to reset the chip (This is what readers typically do!). • Using the READ command with WordCount<>0. • Sending other command prior to READ or SELECT (e.g. WRITE to address<>1Fh, ReqRN) or executing READ or SELECT two times. Remark: The WRITE operation itself is not affected by this problem i.e. data is written properly! With commercially available readers this behavior is typically not observed. 14.1.1.3 Supported EPC types The EPC types are defined in the EPC Tag Standards document from EPCglobal. These standards define completely that portion of EPC tag data that is standardized, including how that data is encoded on the EPC tag itself (i.e. the EPC Tag Encodings), as well as how it is encoded for use in the information systems layers of the EPC Systems Network (i.e. the EPC URI or Uniform Resource Identifier Encodings). The EPC Tag Encodings include a Header field followed by one or more Value Fields. The Header field indicates the length of the Values Fields and contains a numbering system identifier (NSI). The Value Fields contain a unique EPC Identifier and optional Filter Value when the latter is judged to be important to encode on the tag itself. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 24 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.2 Sessions, selected and inventoried flags Session, Selected and Inventory Flags are according the EPCglobal standard. For a description refer to Section 17, Ref. 1, section 6.3.2.3. 14.2.1 G2X States and slot counter For a description refer to Section 17, Ref. 1, section 6.3.2.4. 14.2.2 G2X State Diagram The tag state are according the EPCglobal standard please refer to: Section 17, Ref. 1, section 6.3.2.4 Tag states and slot counter. A detailed tag state diagram is shown in Section 17, Ref. 1, figure 6.19. Refer also to Section 17, Ref. 1, Annex B for the associated state-transition tables and to Section 17, Ref. 1, Annex C for the associated command-response tables. 14.3 Managing tag populations For a detailed description on how to manage an UCODE G2X tag populations refer to Section 17, Ref. 1, chapter 6.3.2.6. 14.4 Selecting tag populations For a detailed description of the UCODE G2X tag population selection process refer to Section 17, Ref. 1, section 6.3.2.7. 14.5 Inventorying tag populations For a detailed description on accessing individual tags based on the UCODE G2X refer to Section 17, Ref. 1, section 6.3.2.8. 14.6 Accessing individual tags For a detailed description on accessing individual tags based on the UCODE G2X refer to Section 17, Ref. 1, section 6.3.2.9. An example inventory and access of a single UCODE G2X tag is shown in Section 17, Ref. 1, Annex E.1. 14.7 Interrogator commands and tag replies For a detailed description refer to Section 17, Ref. 1, section 6.3.2.10. 14.7.1 Commands An overview of interrogator to tag commands is located in Section 17, Ref. 1, Table 6.16. Note that all mandatory commands are implemented on the G2X according to the standard. Additionally the optional command Access is supported by the G2X (for details refer to Section 14.11 “Optional Access Command”). Besides also custom commands are implemented on the G2X (for details refer to Section 14.12 “Custom Commands”. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 25 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.7.2 State transition tables The G2X responses to interrogator commands are defined by State Annex B transition tables in Section 17, Ref. 1. Following states are implemented on the G2X: • Ready, for a description refer to Section 17, Ref. 1, Annex B.1. • Arbitrate, for a description refer to Section 17, Ref. 1, Annex B.2. • Reply, for a description refer to Section 17, Ref. 1, Annex B.3. • Acknowledged, for a description refer to Section 17, Ref. 1, Annex B.4. • Open, for a description refer to Section 17, Ref. 1, Annex B.5. • Secured, for a description refer to Section 17, Ref. 1, Annex B.6. • Killed, for a description refer to Section 17, Ref. 1, Annex B.7. 14.7.3 Command response tables The G2X responses to interrogator commands are described in following Annex C sections of Section 17, Ref. 1: • Power-up, for a description refer to Section 17, Ref. 1, Annex C.1. • Query, for a description refer to Section 17, Ref. 1, Annex C.2. • QueryRep, for a description refer to Section 17, Ref. 1, Annex C.3. • QueryAdjust, for a description refer to Section 17, Ref. 1, Annex C.4. • ACK, for a description refer to Section 17, Ref. 1, Annex C.5. • NAK, for a description refer to Section 17, Ref. 1, Annex C.6. • Req_RN, for a description refer to Section 17, Ref. 1, Annex C.7. • Select, for a description refer to Section 17, Ref. 1, Annex C.8. • Read, for a description refer to Section 17, Ref. 1, Annex C.9. • Write, for a description refer to Section 17, Ref. 1, Annex C.10. • Kill, for a description refer to Section 17, Ref. 1, Annex C.11. • Lock, for a description refer to Section 17, Ref. 1, Annex C.12. • Access, for a description refer to Section 17, Ref. 1, Annex C.13. • T2 time-out, for a description refer to Section 17, Ref. 1, Annex C.17. • Invalid command, for a description refer to Section 17, Ref. 1, Annex C.18. 14.7.4 Example data-flow exchange For data flow-exchange examples refer to Section 17, Ref. 1, Annex K: • K.1 Overview of the data-flow exchange • K.2 Tag memory contents and lock-field values • K.3 Data-flow exchange and command sequence 14.8 Mandatory Select Commands Select commands select a particular UCODE G2X tag population based on user-defined criteria. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 26 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.8.1 Select For a detailed description of the mandatory Select command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9 Mandatory Inventory Commands Inventory commands are used to run the collision arbitration protocol. 14.9.1 Query For a detailed description of the mandatory Query command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9.2 QueryAdjust For a detailed description of the mandatory QueryAdjust command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9.3 QueryRep For a detailed description of the mandatory QueryRep command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9.4 ACK For a detailed description of the mandatory ACK command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9.5 NAK For a detailed description of the mandatory NAK command refer to Section 17, Ref. 1, section 6.3.2.10. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 27 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.10 Mandatory Access Commands Access commands are used to read or write data from or to the G2X memory. For a detailed description of the mandatory Access command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.1 REQ_RN Access commands are used to read or write data from or to the G2X memory. For a detailed description of the mandatory Access command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.2 READ For a detailed description of the mandatory Req_RN command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.3 WRITE For a detailed description of the mandatory Write command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.4 KILL For a detailed description of the mandatory Kill command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.5 LOCK For a detailed description of the mandatory Lock command refer to Section 17, Ref. 1, section 6.3.2.10. 14.11 Optional Access Command 14.11.1 Access For a detailed description of the optional Access command refer to Section 17, Ref. 1, section 6.3.2.10. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 28 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12 Custom Commands 14.12.1 ReadProtect The G2X ReadProtect custom command enables reliable read protection of the entire G2X memory. Executing ReadProtect from the Secured state will set the ReadProtect-bit to '1'. With the ReadProtect-Bit set the G2X will continue to work unaffected but fail its content. Following commands will be disabled: Read, Write, Kill, Lock, Access, ReadProtect, ChangeEAS, EAS Alarm and Calibrate. The G2X will only react upon an anticollision with Select, Query, QueryRep, QueryAdjust, ACK (no truncated reply), NAK, ReqRN but reply with zeros as EPC and CRC-16 content (except PC/password). ACK will return zeros except for the PC. The read protection can be removed by executing Reset ReadProtect. The ReadProtect-Bit will than be cleared. Devices whose access password is zero will ignore the command. A frame-sync must be prepended the command. After sending the ReadProtect command an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's ReadProtect command and the backscattered reply. An interrogator may observe three possible responses after sending a ReadProtect, depending on the success or failure of the operation: • ReadProtect succeeds: After completing the ReadProtect the G2X shall backscatter the reply shown in Table 14 comprising a header (a 0-bit), the tag's handle, and a CRC-16 calculated over the 0-bit and handle. Immediately after this reply the G2X will render itself to this ReadProtect mode. If the interrogator observes this reply within 20 ms then the ReadProtect completed successfully. • The G2X encounters an error: The G2X will backscatter an error code during the CW period rather than the reply shown in the EPCglobal Spec (see Annex I for error-code definitions and for the reply format). • ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2X is still in the interrogation zone, and may re-initiate the ReadProtect command. The G2X reply to the ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. Table 12. ReadProtect command Command RN CRC-16 # of bits 16 16 16 description 11100000 00000001 handle - 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 29 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 13. G2X reply to a successful ReadProtect procedure Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 14. ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open all - open secured valid handle & invalid access password – arbitrate valid handle & valid non zero access password Backscatter handle, when done secured invalid handle – secured killed all – killed 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 30 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12.2 Reset ReadProtect Reset ReadProtect allows an interrogator to resets the ReadProtect-bit and re-enables reading of the G2X memory content according the EPCglobal specification. The G2X will execute Reset ReadProtect from the Open or Secured states. If a G2X in the Open or Secured states receives a Reset ReadProtect with a valid CRC-16 and a valid handle but an incorrect access password, it will not reply and transit to the Arbitrate state. If a G2X in the Open or Secured states receives a Reset ReadProtect with a valid CRC-16 and a valid handle but the ReadProtect-Bit is not set ('0'), it will not change the ReadProtect-Bit but backscatter the reply shown in Table 17. If a G2X in the Open or Secured receives a Reset ReadProtect with a valid CRC-16 but an invalid handle, or it receives a Reset ReadProtect before which the immediately preceding command was not a Req_RN, it will ignore the Reset ReadProtect and remain in its current state. A frame-sync must be prepended the Reset ReadProtect command. After sending a Reset ReadProtect an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's Reset ReadProtect command and the G2X backscattered reply. An interrogator may observe three possible responses after sending a Reset ReadProtect, depending on the success or failure of the operation: • Write succeeds: After completing the Reset ReadProtect a G2X will backscatter the reply shown in Table 17 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the Reset ReadProtect completed successfully. • The G2X encounters an error: The G2X will backscatter an error code during the CW period rather than the reply shown in Table 17 (see EPCglobal Spec for error-code definitions and for the reply format). • Write does not succeed: If the interrogator does not observe a reply within 20 ms then the Reset ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2X is still in the interrogation zone, and may reissue the Reset ReadProtect command. The G2X reply to the Reset ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a G2X will reply as if TRext=1 regardless of the TRext value in the Query that initiated the round. The Reset ReadProtect command is structured as following: • 16 bit command • Password: 32 bit Access-Password XOR with 2 times current RN16 • 16 bit handle • CRC-16 calculate over the first command-code bit to the last handle bit 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 31 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 15. Reset ReadProtect command Command Password RN CRC-16 # of bits 16 32 16 16 description 11100000 00000010 (access password)  2*RN16 handle - Table 16. G2X reply to a successful Reset ReadProtect command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 17. Reset ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open ReadProtect bit is set, valid handle & valid access password Backscatter handle, when done open ReadProtect bit is set, valid handle & invalid access password – arbitrate ReadProtect bit is set, invalid handle – open ReadProtect bit is reset – open secured ReadProtect bit is set, valid handle & valid access password Backscatter handle, when done secured ReadProtect bit is set, valid handle & invalid access password – arbitrate ReadProtect bit is set, invalid handle – secured ReadProtect bit is reset – secured killed all – killed 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 32 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12.3 ChangeEAS A G2X equipped RFID tag can be enhanced by a stand-alone operating EAS alarm feature. With an EAS-Alarm bit set to '1' the tag will reply to an EAS_Alarm command by backscattering a 64 bit alarm code without the need of a Select or Query. The EAS is a built-in solution so no connection to a backend database is required. As it is a custom command no Select or Query is required to detect the EAS state enabling fast, reliable and offline article surveillance. ChangeEAS can be executed from the Secured state only. The command will be ignored if the Access Password is zero, the command will also be ignored with an invalid CRC-16 or an invalid handle, the G2X will than remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A frame-sync must be prepended the command. The G2X reply to a successful ChangeEAS will use the extended preamble, as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. After sending a ChangeEAS an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeEAS command and the G2X backscattered reply. An interrogator may observe three possible responses after sending a ChangeEAS, depending on the success or failure of the operation • Write succeeds: After completing the ChangeEAS a G2X will backscatter the reply shown in Table 20 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the ChangeEAS completed successfully. • The G2X encounters an error: The G2X will backscatter an error code during the CW period rather than the reply shown in Table 20 (see EPCglobal Spec for error-code definitions and for the reply format). • Write does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeEAS did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2X is still in the interrogator's field, and may reissue the ChangeEAS command. Upon receiving a valid ChangeEAS command a G2X will perform the commanded set/reset operation of the EAS_Alarm-Bit. If EAS-Bit is set, the EAS_Alarm command will be available after the next power up and reply the 64 bit EAS code upon execution. Otherwise the EAS_Alarm command will be ignored. Table 18. ChangeEAS command Command ChangeEas RN CRC-16 # of bits 16 1 16 16 description 11100000 00000011 1 ... set EAS system bit 0 ... reset EAS system bit handle 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 33 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 19. G2X reply to a successful ChangeEAS command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 20. ChangeEAS command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open all – open secured valid handle Backscatter handle, when done secured invalid handle – secured killed all – killed Starting State Condition Response Next State 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 34 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12.4 EAS_Alarm EAS_Alarm is a custom command causing the G2X to immediately backscatter an EAS-Alarmcode, when EAS ALARM bit is set without any delay caused by Select, Query and without the need for a backend database. The EAS feature of the G2X is available after enabling it by sending a ChangeEAS command described in Section 14.12.3 “ChangeEAS”. With an EAS-Alarm bit set to '1' the G2X will reply to an EAS_Alarm command by backscattering a fixed 64 bit alarm code. A G2X will reply to an EAS_Alarm command from the ready state only. If the EAS-Alarm bit is reset ('0') by sending a ChangeEAS command in the password protected Secure state the G2X will not reply to an EAS_Alarm command. The EAS_Alarm command is structured as following: • 16 bit command • 16 bit inverted command • DR (TRcal divide ratio) sets the T=>R link frequency as described in EPCglobal Spec. 6.3.1.2.8 and Table 6.9. • M (cycles per symbol) sets the T=>R data rate and modulation format as shown in EPCglobal Spec. Table 6.10. • TRext chooses whether the T=>R preamble is prepended with a pilot tone as described in EPCglobal Spec. 6.3.1.3. A preamble must be prepended the EAS_Alarm command according EPCglobal Spec, 6.3.1.2.8. Upon receiving an EAS_Alarm command the tag loads the CRC5 register with 01001b and backscatters the 64 bit alarm code accordingly. The reader is now able to calculate the CRC5 over the backscattered 64 bits received to verify the received code. Table 21. EAS_Alarm command Command Inv_Command DR M TRext CRC-16 # of bits 16 16 1 2 1 16 description 11100000 00000100 00011111 11111011 0: DR=8 1: DR=64/3 00: M=1 01: M=2 10: M=4 11: M=8 0: No pilot tone 1: Use pilot tone - Table 22. G2X reply to a successful EAS_Alarm command Header EAS Code # of bits 1 64 description 0 CRC5 (MSB) 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 35 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 23. Eas_Alarm command-response table Starting State Condition Response Next State ready EAS-bit is set and non-zero access password Backscatter Alarm code ready arbitrate, reply, acknowledged EAS-bit is set and non-zero access password – arbitrate open EAS-bit is set and non-zero access password open secured EAS-bit is set and non-zero access password secured killed EAS-bit is set and non-zero access password – killed 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 36 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12.5 Calibrate After execution of the custom Calibrate command the G2X will continuously backscatter the user memory content in an infinite loop. The G2XL will continuously backscatter zeros. This command can be used for frequency spectrum measurements. Calibrate can only be executed from the Secure state with an non-zero Access Password set otherwise the command will be ignored. The Calibrate command includes a CRC-16 calculated over the whole command, the handle and a prepended frame-sync. [1] G2XM [2] G2XL Table 24. Calibrate command Command RN16 CRC-16 # of bits 16 16 16 description 11100000 00000101 handle - Table 25. G2X reply to a successful Calibrate command Header Infinite repeat # of bits 1 512 (looped) description 0 User memory data[1] zeros[2] Table 26. Calibrate command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate secured nonzero access password Backscatter infinite _ access password is zero – secured killed all – killed 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 37 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 15. Support information 15.1 CRC Calculation EXAMPLE Old RN = 3D5Bh Table 27. Practical example of CRC calculation for a 'Req_RN' command by the reader CRC Calculated @ Reader Cmd Code for Req_RN F F F F 1 F F F E 1 F F F C 0 E F D 9 0 C F 9 3 0 8 F 0 7 0 0 E 2 F 0 1 C 5 E 1 2 8 9 9 First Byte of RN 0 5 1 3 A 0 A 2 7 4 1 4 4 E 8 1 9 9 F 1 1 3 3 E 2 1 7 7 E 5 0 E F C A 1 D F 9 4 Second Byte of RN 0 A F 0 9 1 5 E 1 2 0 B C 2 4 1 7 8 4 8 1 E 0 B 1 0 D 1 4 3 1 A 2 8 6 1 4 5 0 C -> ones complement: B A F 3 => Command-Sequence: C1 3D 5B BA F3 hex 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 38 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 28. Practical example of CRC calculation for a 'Req_RN' command by the reader CRC Calculated @ Tag Cmd Code for Req_RN F F F F 1 F F F E 1 F F F C 0 E F D 9 0 C F 9 3 0 8 F 0 7 0 0 E 2 F 0 1 C 5 E 1 2 8 9 9 First Byte of RN 0 5 1 3 A 0 A 2 7 4 1 4 4 E 8 1 9 9 F 1 1 3 3 E 2 1 7 7 E 5 0 E F C A 1 D F 9 4 Second Byte of RN 0 A F 0 9 1 5 E 1 2 0 B C 2 4 1 7 8 4 8 1 E 0 B 1 0 D 1 4 3 1 A 2 8 6 1 4 5 0 C First Byte of CRC 1 9 A 3 9 0 2 4 5 3 1 5 8 8 7 1 A 1 2 F 1 4 2 5 E 0 8 4 B C 1 0 9 7 8 0 1 2 F 0 Second Byte of CRC 1 3 5 C 1 1 7 B A 3 1 E 7 6 7 1 C E C E 0 8 D B D 0 0 B 5 B 1 0 6 9 7 1 1 D 0 F -> Residue OK 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 39 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 16. Abbreviations Table 29. Abbreviations Acronym Description CRC Cyclic redundancy check CW Continuos wave EEPROM Electrically Erasable Programmable Read Only Memory EPC Electronic Product Code (containing Header, Domain Manager, Object Class and Serial Number) FM0 Bi phase space modulation G2 Generation 2 HBM Human Body Model IC Integrated Circuit LSB Least Significant Byte/Bit MSB Most Significant Byte/Bit NRZ Non-Return to Zero coding RF Radio Frequency RTF Reader Talks First Tari Type A Reference Interval (ISO 18000-6) UHF Ultra High Frequency Xxb Value in binary notation xxhex Value in hexadecimal notation 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 40 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 17. References [1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0 (December 17, 2005) [2] EPCglobal: EPC Tag Data Standards [3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft) [4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference (draft) [5] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 1 – Technical characteristics and test methods [6] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive [7] [CEPT1]: CEPT REC 70-03 Annex 1 [8] [ETSI1]: ETSI EN 330 220-1, 2 [9] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1: Technical characteristics and test methods. [10] [FCC1]: FCC 47 Part 15 Section 247 [11] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International Standards [12] ISO/IEC 3309: Information technology – Telecommunications and information exchange between systems – High-level data link control (HDLC) procedures – Frame structure [13] ISO/IEC 15961: Information technology, Automatic identification and data capture – Radio frequency identification (RFID) for item management – Data protocol: application interface [14] ISO/IEC 15962: Information technology, Automatic identification and data capture techniques – Radio frequency identification (RFID) for item management – Data protocol: data encoding rules and logical memory functions [15] ISO/IEC 15963: Information technology — Radio frequency identification for item management — Unique identification for RF tags [16] ISO/IEC 18000-1: Information technology — Radio frequency identification for item management — Part 1: Reference architecture and definition of parameters to be standardized [17] ISO/IEC 18000-6: Information technology automatic identification and data capture techniques — Radio frequency identification for item management air interface — Part 6: Parameters for air interface communications at 860–960 MHz [18] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary – Part 3: radio-frequency identification (RFID) 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 41 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL [19] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15: Radio-frequency devices, U.S. Federal Communications Commission. [20] Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**1 1. ** ... document version number 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 42 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 18. Revision history Table 30. Revision history Document ID Release date Data sheet status Change notice Supersedes SL3ICS1002_1202 v.3.8 20131111 Product data sheet - SL3ICS1002_1202 v.3.7 Modifications: • Update of the delivery form (TSSOP package due to DOD removed) SL3ICS1002_1202 v.3.7 20121009 Product data sheet - 139036 Modifications: • Update of the delivery form 139036 20110310 Product data sheet 139035 Modifications: • Table 4 “TSSOP8 Marking”: added • Section 14.1.1.2 “Special behavior of user memory address 1Fh”: added 139035 20091102 Product data sheet 139034 Modifications: • Type SOT1122 added • Figure 2 “Wafer layout and pinning information”: correction of drawing 139034 20090721 Product data sheet 139033 Modifications: • Table 11 “TSSOP8 characteristics” andTable 7 “Package interface characteristics” :removed “Memory characteristics” 139033 20090605 Product data sheet - 139032 139132 Modifications: • This data sheet is a combination of data sheets SL3ICS1002 and SL3ICS1202 • New type FCS2 Aluminum, SOT1040AB2 added • Section 8.1.6 “Fail die identification”: added • Section 11 “Packing information”: edited 139032 20080716 Product data sheet 139031 Modifications: • rephrasing of Section 2 “Features and benefits” on page 2 • added “calibrate command” in Section 2 “Features and benefits” on page 2 • redesign of Figure 1 “Block diagram of G2X IC” on page 4 • merging of Fig. 2 Pinning and Fig. 3 Wafer layout - see Figure 2 “Wafer layout and pinning information” on page 5 • added type “FCS2 Polymer Strap - SOT1040AA1” in Section 4 “Ordering information”, Section 6 “Wafer layout and pinning information”, Section 7 “Package outline”, Section 8 “Mechanical specification”, Section 9 “Limiting values”, Section 10 “Characteristics” • added Section 11 “Handling information for Flip Chip Strap (FCS2, SOT1040)” on page 19 • added Section 11 “Packing information” on page 12 • added Table 8 “Symbol description” on page 14 • correction of Table 11 “Memory map” on page 22 • removed “ongoing” in 32 bit ongoing in Section 2.1 and Table 10 “G2X memory sections” 139031 20080428 Product data sheet 139030 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 43 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Modifications: • update of Table 1 “Ordering information” on page 3 • added Section 7 “Package outline” on page 6 • added Section 8.1.7 “Map file distribution” on page 9 • added Table 9 “Limiting values TSSOP8 [1][2]” on page 14 • added room temperature in Table 11 “Memory characteristics” on page 15 • added Section 10.2 “TSSOP8 characteristics” on page 17 • update of the “EPCglobal compliance and interoperability certification” in Section 12.4 “Air interface standards” on page 15 • correction of “(excluding 16 bit CRC-16 and 16 bit PC) in Table 10 “G2X memory sections” on page 21 • correction of Initials in “tag mask designer” in Table 11 “Memory map” on page 22 • removed the sentence “The ChangeEAS custom command will toggle the state of the EAS-Alarm bit located in the EEprom” in Section 14.12.3 “ChangeEAS” on page 32. • added description of ChangeEAS in Table 18 “ChangeEAS command” on page 32 139030 20071221 Product data sheet - 139011 Modifications: • change of product status • general update 139011 20070910 Objective data sheet - 139010 Modifications: • removed double section Change EAS, EAS Alarm, Chapter 12.11.7 • changed “Reader” to “Tag” 139010 20070612 Objective data sheet - - • initial version Table 30. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 44 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 19. Legal information 19.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 45 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. UCODE — is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 46 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 21. Tables Table 1. Ordering information G2XM . . . . . . . . . . . . . . . .3 Table 2. Ordering information G2XL. . . . . . . . . . . . . . . . .3 Table 3. Pin description of SOT1122 . . . . . . . . . . . . . . . .7 Table 4. SOT1122 Marking. . . . . . . . . . . . . . . . . . . . . . . .7 Table 5. Limiting values[1][2] . . . . . . . . . . . . . . . . . . . . . .10 Table 6. Wafer characteristics . . . . . . . . . . . . . . . . . . . . 11 Table 7. Package interface characteristics. . . . . . . . . . . 11 Table 8. Symbol description . . . . . . . . . . . . . . . . . . . . . .14 Table 9. Operating distances for UCODE G2X based tags and labels in released frequency bands . .14 Table 10. G2X memory sections . . . . . . . . . . . . . . . . . . .21 Table 11. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 12. ReadProtect command. . . . . . . . . . . . . . . . . . .28 Table 13. G2X reply to a successful ReadProtect procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 14. ReadProtect command-response table . . . . . .29 Table 15. Reset ReadProtect command . . . . . . . . . . . . .31 Table 16. G2X reply to a successful Reset ReadProtect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 17. Reset ReadProtect command-response table 31 Table 18. ChangeEAS command . . . . . . . . . . . . . . . . . . 32 Table 19. G2X reply to a successful ChangeEAS command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 20. ChangeEAS command-response table . . . . . . 33 Table 21. EAS_Alarm command . . . . . . . . . . . . . . . . . . . 34 Table 22. G2X reply to a successful EAS_Alarm command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. Eas_Alarm command-response table. . . . . . . 35 Table 24. Calibrate command . . . . . . . . . . . . . . . . . . . . . 36 Table 25. G2X reply to a successful Calibrate command 36 Table 26. Calibrate command-response table . . . . . . . . . 36 Table 27. Practical example of CRC calculation for a 'Req_RN' command by the reader . . . . . . . . . 37 Table 28. Practical example of CRC calculation for a 'Req_RN' command by the reader. . . . . . . . . . 38 Table 29. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 30. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 42 22. Figures Fig 1. Block diagram of G2X IC . . . . . . . . . . . . . . . . . . . .4 Fig 2. Wafer layout and pinning information . . . . . . . . . .5 Fig 3. Package outline SOT1122 . . . . . . . . . . . . . . . . . . .6 Fig 4. G2X TID memory structure . . . . . . . . . . . . . . . . .21 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 47 of 48 continued >> NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Custom commands. . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Wafer layout and pinning information . . . . . . . 5 6.1 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Mechanical specification . . . . . . . . . . . . . . . . . 8 8.1 Wafer specification . . . . . . . . . . . . . . . . . . . . . . 8 8.1.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.2 Wafer backside . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.3 Chip dimensions . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.4 Passivation on front . . . . . . . . . . . . . . . . . . . . . 8 8.1.5 Au bump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.1.6 Fail die identification . . . . . . . . . . . . . . . . . . . . 9 8.1.7 Map file distribution. . . . . . . . . . . . . . . . . . . . . . 9 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 11 10.1 Wafer characteristics . . . . . . . . . . . . . . . . . . . 11 10.2 Package characteristics . . . . . . . . . . . . . . . . . 11 11 Packing information . . . . . . . . . . . . . . . . . . . . 12 11.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 11.2 SOT1122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 Functional description . . . . . . . . . . . . . . . . . . 13 12.1 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . 13 12.2 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12.2.1 Reader to G2X Link . . . . . . . . . . . . . . . . . . . . 13 12.2.2 G2X to reader Link . . . . . . . . . . . . . . . . . . . . . 13 12.3 Operating distances . . . . . . . . . . . . . . . . . . . . 14 12.4 Air interface standards . . . . . . . . . . . . . . . . . . 15 13 Physical layer and signaling. . . . . . . . . . . . . . 16 13.1 Reader to G2X communication . . . . . . . . . . . 16 13.1.1 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.1.2 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.1.3 Data encoding. . . . . . . . . . . . . . . . . . . . . . . . . 16 13.1.4 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.1.5 RF envelope for R=>T . . . . . . . . . . . . . . . . . . 16 13.1.6 Interrogator power-up/down waveform. . . . . . 16 13.1.7 Preamble and frame-sync . . . . . . . . . . . . . . . 16 13.2 G2X to reader communication . . . . . . . . . . . . 17 13.2.1 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.2.2 Data encoding . . . . . . . . . . . . . . . . . . . . . . . . 17 13.2.2.1 FM0 baseband . . . . . . . . . . . . . . . . . . . . . . . . 17 13.2.2.2 FM0 Preamble . . . . . . . . . . . . . . . . . . . . . . . . 17 13.2.2.3 Miller-modulated sub carrier . . . . . . . . . . . . . 17 13.2.2.4 Miller sub carrier preamble . . . . . . . . . . . . . . 17 13.2.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3 Link timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.3.1 Regeneration time . . . . . . . . . . . . . . . . . . . . . 18 13.3.2 Start-up time. . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.3.3 Persistence time . . . . . . . . . . . . . . . . . . . . . . 18 13.4 Bit and byte ordering . . . . . . . . . . . . . . . . . . . 18 13.5 Data integrity . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.6 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14 TAG selection, inventory and access . . . . . . 20 14.1 G2X Memory . . . . . . . . . . . . . . . . . . . . . . . . . 21 14.1.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . 22 14.1.1.1 User memory (only G2XM) . . . . . . . . . . . . . . 23 14.1.1.2 Special behavior of user memory address 1Fh 23 14.1.1.3 Supported EPC types . . . . . . . . . . . . . . . . . . 23 14.2 Sessions, selected and inventoried flags. . . . 24 14.2.1 G2X States and slot counter . . . . . . . . . . . . . 24 14.2.2 G2X State Diagram . . . . . . . . . . . . . . . . . . . . 24 14.3 Managing tag populations . . . . . . . . . . . . . . . 24 14.4 Selecting tag populations. . . . . . . . . . . . . . . . 24 14.5 Inventorying tag populations . . . . . . . . . . . . . 24 14.6 Accessing individual tags. . . . . . . . . . . . . . . . 24 14.7 Interrogator commands and tag replies . . . . . 24 14.7.1 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.7.2 State transition tables. . . . . . . . . . . . . . . . . . . 25 14.7.3 Command response tables . . . . . . . . . . . . . . 25 14.7.4 Example data-flow exchange. . . . . . . . . . . . . 25 14.8 Mandatory Select Commands . . . . . . . . . . . . 25 14.8.1 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9 Mandatory Inventory Commands. . . . . . . . . . 26 14.9.1 Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9.2 QueryAdjust . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9.3 QueryRep. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9.4 ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9.5 NAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.10 Mandatory Access Commands . . . . . . . . . . . 27 14.10.1 REQ_RN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.10.2 READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.10.3 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.10.4 KILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.10.5 LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.11 Optional Access Command . . . . . . . . . . . . . . 27 14.11.1 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.12 Custom Commands . . . . . . . . . . . . . . . . . . . . 28 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 November 2013 139038 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 14.12.1 ReadProtect . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.12.2 Reset ReadProtect . . . . . . . . . . . . . . . . . . . . . 30 14.12.3 ChangeEAS . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.12.4 EAS_Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14.12.5 Calibrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15 Support information . . . . . . . . . . . . . . . . . . . . 37 15.1 CRC Calculation EXAMPLE . . . . . . . . . . . . . . 37 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 39 17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 42 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 44 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 44 19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 45 20 Contact information. . . . . . . . . . . . . . . . . . . . . 45 21 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 22 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1. General description The LPC11U3x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11U3x operate at CPU frequencies of up to 50 MHz. Equipped with a highly flexible and configurable full-speed USB 2.0 device controller, the LPC11U3x brings unparalleled design flexibility and seamless integration to today’s demanding connectivity solutions. The peripheral complement of the LPC11U3x includes up to 128 kB of flash memory, up to 12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 USART with support for synchronous mode and smart card interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up to 54 general purpose I/O pins. The I/O Handler is a software library-supported hardware engine that can be used to add performance, connectivity and flexibility to system designs. It is available on the LPC11U37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART, I2C, and I2S with no or very low additional CPU load and can off-load the CPU by performing processing-intensive functions like DMA transfers in hardware. Software libraries for multiple I/O Handler applications are available on http://www.LPCware.com. For additional documentation related to the LPC11U3x parts, see Section 15 “References”. 2. Features and benefits  System:  ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.  ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).  Non-Maskable Interrupt (NMI) input selectable from several input sources.  System tick timer.  Memory:  Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase (256 byte) access.  4 kB on-chip EEPROM data memory; byte erasable and byte programmable; on-chip API support.  Up to 12 kB SRAM data memory. LPC11U3x 32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up to 12 kB SRAM and 4 kB EEPROM; USB device; USART Rev. 2.2 — 11 March 2014 Product data sheet LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 2 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller  16 kB boot ROM.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.  ROM-based USB drivers. Flash updates via USB supported.  ROM-based 32-bit integer division routines.  Debug options:  Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan Description Language).  Serial Wire Debug.  Digital peripherals:  Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode.  Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.  Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  High-current source output driver (20 mA) on one pin.  High-current sink driver (20 mA) on true open-drain pins.  Four general purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs.  Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal low-power WatchDog Oscillator (WDO).  Analog peripherals:  10-bit ADC with input multiplexing among eight pins.  Serial interfaces:  USB 2.0 full-speed device controller.  USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS-485/9-bit mode and synchronous mode. USART supports an asynchronous smart card interface (ISO 7816-3).  Two SSP controllers with FIFO and multi-protocol capabilities.  I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.  I/O Handler for hardware emulation of serial interfaces and DMA; supported through software libraries. (LPC11U37HFBD64/401 only.)  Clock generation:  Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).  12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as a system clock.  Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output.  PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources.  A second, dedicated PLL is provided for USB.  Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator.  Power control: LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 3 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller  Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes.  Power profiles residing in boot ROM provide optimized performance and minimized power consumption for any given application through one simple function call.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Processor wake-up from Deep-sleep and Power-down modes via reset, selectable GPIO pins, watchdog interrupt, or USB port activity.  Processor wake-up from Deep power-down mode using one special function pin.  Power-On Reset (POR).  Brownout detect with up to four separate thresholds for interrupt and forced reset.  Unique device serial number for identification.  Single 3.3 V power supply (1.8 V to 3.6 V).  Temperature range 40 C to +85 C.  Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages. 3. Applications 4. Ordering information  Consumer peripherals  Handheld scanners  Medical  USB audio devices  Industrial control Table 1. Ordering information Type number Package Name Description Version LPC11U34FHN33/311 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC11U34FBD48/311 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U34FHN33/421 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC11U34FBD48/421 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U35FHN33/401 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC11U35FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U35FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2 LPC11U35FHI33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC11U35FET48/501 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5  4.5  0.7 mm SOT1155-2 LPC11U36FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U36FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 4 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 4.1 Ordering options [1] For general-purpose use. [2] For I/O Handler use only. LPC11U37FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U37HFBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2 LPC11U37FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2 Table 1. Ordering information …continued Type number Package Name Description Version Table 2. Ordering options Type number Flash in kB EEPROM in kB SRAM0 in kB USB SRAM in kB SRAM1 in kB Total SRAM in kB[1] I/O Handler USART I2C-bus FM+ SSP USB device ADC channels GPIO pins LPC11U34FHN33/311 40 4 8 - - 8 no 1 1 2 1 8 26 LPC11U34FBD48/311 40 4 8 - - 8 no 1 1 2 1 8 40 LPC11U34FHN33/421 48 4 8 2 - 10 no 1 1 2 1 8 26 LPC11U34FBD48/421 48 4 8 2 - 10 no 1 1 2 1 8 40 LPC11U35FHN33/401 64 4 8 2 - 10 no 1 1 2 1 8 26 LPC11U35FBD48/401 64 4 8 2 - 10 no 1 1 2 1 8 40 LPC11U35FBD64/401 64 4 8 2 - 10 no 1 1 2 1 8 54 LPC11U35FHI33/501 64 4 8 2 2[1] 12 no 1 1 2 1 8 26 LPC11U35FET48/501 64 4 8 2 2[1] 12 no 1 1 2 1 8 40 LPC11U36FBD48/401 96 4 8 2 - 10 no 1 1 2 1 8 40 LPC11U36FBD64/401 96 4 8 2 - 10 no 1 1 2 1 8 54 LPC11U37FBD48/401 128 4 8 2 - 10 no 1 1 2 1 8 40 LPC11U37HFBD64/401 128 4 8 2 2[2] 10 yes 1 1 2 1 8 54 LPC11U37FBD64/501 128 4 8 2 2[1] 12 no 1 1 2 1 8 54 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 5 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 5. Block diagram (1) Not available on HVQFN33 packages. (2) CT16B0_CAP1, CT16B1_CAP1 available on LQFP64 packages only; CT32B0_CAP1 available on TFBGA48, LQFP48, and LQFP64 packages only; CT32B1_CAP1 available in TFBGA48/LQFP64 packages only. (3) LPC11U37HFBD64/401 only. Fig 1. Block diagram SRAM 8/10/12 kB ARM CORTEX-M0 TEST/DEBUG INTERFACE FLASH 40/48/64/96/128 kB HIGH-SPEED GPIO AHB TO APB BRIDGE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS RESET SWD, JTAG LPC11U3x slave slave master slave slave ROM 16 kB slave AHB-LITE BUS GPIO ports 0/1 I/O IOH_[20:0] HANDLER(3) CLKOUT IRC, WDO SYSTEM OSCILLATOR POR PLL0 USB PLL BOD 10-bit ADC USART/ SMARTCARD INTERFACE AD[7:0] RXD TXD CTS, RTS, DTR SCLK GPIO INTERRUPTS 32-bit COUNTER/TIMER 0 CT32B0_MAT[3:0] CT32B0_CAP[1:0](2) 32-bit COUNTER/TIMER 1 CT32B1_MAT[3:0] CT32B1_CAP[1:0](2) DCD, DSR(1), RI(1) 16-bit COUNTER/TIMER 1 WINDOWED WATCHDOG TIMER GPIO GROUP0 INTERRUPTS CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 0 CT16B0_MAT[2:0] CT16B0_CAP[1:0](2) CT16B1_CAP[1:0](2) GPIO pins GPIO pins GPIO pins GPIO GROUP1 INTERRUPTS system bus SSP0 SCK0, SSEL0, MISO0, MOSI0 SSP1 SCK1, SSEL1, MISO1, MOSI1 I2C-BUS IOCON SYSTEM CONTROL PMU SCL, SDA XTALIN XTALOUT USB DEVICE CONTROLLER USB_DP USB_DM USB_VBUS USB_FTOGGLE, USB_CONNECT 002aag345 master slave EEPROM 4 kB LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 6 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 6.1 Pinning For parts LPC11U34FHN33/311, LPC11U34FHN33/421, LPC11U35FHN33/401, LPC11U35FHI33/501 Fig 2. Pin configuration (HVQFN33) 002aag809 Transparent top view PIO0_8/MISO0/CT16B0_MAT0 PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_9/MOSI0/CT16B0_MAT1 VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2 XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1 XTALIN TDI/PIO0_11/AD0/CT32B0_MAT3 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0 RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1 PIO0_3/USB_VBUS PIO0_4/SCL PIO0_5/SDA PIO0_21/CT16B1_MAT0/MOSI1 USB_DM USB_DP PIO0_6/USB_CONNECT/SCK0 PIO0_7/CTS PIO0_19/TXD/CT32B0_MAT1 PIO0_18/RXD/CT32B0_MAT0 PIO0_17/RTS/CT32B0_CAP0/SCLK VDD PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_23/AD7 PIO0_16/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO0_15/AD4/CT32B1_MAT2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 VSS LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 7 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 3. Pin configuration (TFBGA48) 002aag810 LPC11U35FET48/501 Transparent top view H G F D B E C A 1 2 3 4 5 6 7 8 ball A1 index area LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 8 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 4. Pin configuration (LQFP48) LPC11U34FBD48/311 LPC11U34FBD48/421 LPC11U35FBD48/401 LPC11U36FBD48/401 LPC11U37FBD48/401 PIO1_25/CT32B0_MAT1 PIO1_13/DTR/CT16B0_MAT0/TXD PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1 RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0 VSS TDI/PIO0_11/AD0/CT32B0_MAT3 XTALIN PIO1_29/SCK0/CT32B0_CAP1 XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1 VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_20/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0 PIO1_26/CT32B0_MAT2/RXD PIO1_21/DCD/MISO1 PIO1_27/CT32B0_MAT3/TXD PIO1_31 PIO1_20/DSR/SCK1 PIO1_16/RI/CT16B0_CAP0 PIO0_3/USB_VBUS PIO0_19/TXD/CT32B0_MAT1 PIO0_4/SCL PIO0_18/RXD/CT32B0_MAT0 PIO0_5/SDA PIO0_17/RTS/CT32B0_CAP0/SCLK PIO0_21/CT16B1_MAT0/MOSI1 VDD PIO1_23/CT16B1_MAT1/SSEL1 PIO1_15/DCD/CT16B0_MAT2/SCK1 USB_DM PIO0_23/AD7 USB_DP VSS PIO1_24/CT32B0_MAT0 PIO0_16/AD5/CT32B1_MAT3/WAKEUP PIO0_6/USB_CONNECT/SCK0 SWDIO/PIO0_15/AD4/CT32B1_MAT2 PIO0_7/CTS PIO1_28/CT32B0_CAP0/SCLK PIO1_22/RI/MOSI1 PIO1_14/DSR/CT16B0_MAT1/RXD 002aag811 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 24 37 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 9 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller See Table 3 for the full pin name. Fig 5. Pin configuration (LQFP64) LPC11U35FBD64/401 LPC11U36FBD64/401 LPC11U37HFBD64/401 LPC11U37FBD64/501 PIO1_0 VDD PIO1_25 PIO1_13 PIO1_19 TRST/PIO0_14 RESET/PIO0_0 TDO/PIO0_13 PIO0_1 TMS/PIO0_12 PIO1_7 PIO1_11 VSS TDI/PIO0_11 XTALIN PIO1_29 XTALOUT PIO0_22 VDD PIO1_8 PIO0_20 SWCLK/PIO0_10 PIO1_10 PIO0_9 PIO0_2 PIO0_8 PIO1_26 PIO1_21 PIO1_27 PIO1_2 PIO1_4 VDD PIO1_1 PIO1_6 PIO1_20 PIO1_16 PIO0_3 PIO0_19 PIO0_4 PIO0_18 PIO0_5 PIO0_17 PIO0_21 PIO1_12 PIO1_17 VDD PIO1_23 PIO1_15 USB_DM PIO0_23 USB_DP PIO1_9 PIO1_24 VSS PIO1_18 PIO0_16 PIO0_6 SWDIO/PIO0_15 PIO0_7 PIO1_22 PIO1_28 PIO1_3 PIO1_5 PIO1_14 002aag812 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 10 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and PIO0_5. Every port pin has a corresponding IOCON register for programming the digital or analog function, the pull-up/pull-down configuration, the repeater, and the open-drain modes. The USART, counter/timer, and SSP functions are available on more than one port pin. Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description RESET/PIO0_0 2 C1 3 4 [2] I; PU I RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. This pin also serves as the debug select input. LOW level selects the JTAG boundary scan. HIGH level selects the ARM SWD debug mode. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. - I/O PIO0_0 — General purpose digital input/output pin. PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE 3 C2 4 5 [3] I; PU I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration. - O CLKOUT — Clockout pin. - O CT32B0_MAT2 — Match output 2 for 32-bit timer 0. - O USB_FTOGGLE — USB 1 ms Start-of-Frame signal. PIO0_2/SSEL0/ CT16B0_CAP0/IOH_0 8 F1 10 13 [3] I; PU I/O PIO0_2 — General purpose digital input/output pin. - I/O SSEL0 — Slave select for SSP0. - I CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. - I/O IOH_0 — I/O Handler input/output 0. LPC11U37HFBD64/401 only. PIO0_3/USB_VBUS/ IOH_1 9 H2 14 19 [3] I; PU I/O PIO0_3 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. A HIGH level during reset starts the USB device enumeration. - I USB_VBUS — Monitors the presence of USB bus power. - I/O IOH_1 — I/O Handler input/output 1. LPC11U37HFBD64/401 only. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 11 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller PIO0_4/SCL/IOH_2 10 G3 15 20 [4] I; IA I/O PIO0_4 — General purpose digital input/output pin (open-drain). - I/O SCL — I2C-bus clock input/output (open-drain). High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. - I/O IOH_2 — I/O Handler input/output 2. LPC11U37HFBD64/401 only. PIO0_5/SDA/IOH_3 11 H3 16 21 [4] I; IA I/O PIO0_5 — General purpose digital input/output pin (open-drain). - I/O SDA — I2C-bus data input/output (open-drain). High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. - I/O IOH_3 — I/O Handler input/output 3. LPC11U37HFBD64/401 only. PIO0_6/USB_CONNECT/ SCK0/IOH_4 15 H6 22 29 [3] I; PU I/O PIO0_6 — General purpose digital input/output pin. - O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. - I/O SCK0 — Serial clock for SSP0. - I/O IOH_4 — I/O Handler input/output 4. LPC11U37HFBD64/401 only. PIO0_7/CTS/IOH_5 16 G7 23 30 [5] I; PU I/O PIO0_7 — General purpose digital input/output pin (high-current output driver). - I CTS — Clear To Send input for USART. - I/O IOH_5 — I/O Handler input/output 5. (LPC11U37HFBD64/401 only.) PIO0_8/MISO0/ CT16B0_MAT0/R/IOH_6 17 F8 27 36 [3] I; PU I/O PIO0_8 — General purpose digital input/output pin. - I/O MISO0 — Master In Slave Out for SSP0. - O CT16B0_MAT0 — Match output 0 for 16-bit timer 0. - - Reserved. - I/O IOH_6 — I/O Handler input/output 6. (LPC11U37HFBD64/401 only.) PIO0_9/MOSI0/ CT16B0_MAT1/R/IOH_7 18 F7 28 37 [3] I; PU I/O PIO0_9 — General purpose digital input/output pin. - I/O MOSI0 — Master Out Slave In for SSP0. - O CT16B0_MAT1 — Match output 1 for 16-bit timer 0. - - Reserved. - I/O IOH_7 — I/O Handler input/output 7. (LPC11U37HFBD64/401 only.) Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 12 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller SWCLK/PIO0_10/SCK0/ CT16B0_MAT2 19 E7 29 38 [3] I; PU I SWCLK — Serial wire clock and test clock TCK for JTAG interface. - I/O PIO0_10 — General purpose digital input/output pin. - O SCK0 — Serial clock for SSP0. - O CT16B0_MAT2 — Match output 2 for 16-bit timer 0. TDI/PIO0_11/AD0/ CT32B0_MAT3 21 D8 32 42 [6] I; PU I TDI — Test Data In for JTAG interface. - I/O PIO0_11 — General purpose digital input/output pin. - I AD0 — A/D converter, input 0. - O CT32B0_MAT3 — Match output 3 for 32-bit timer 0. TMS/PIO0_12/AD1/ CT32B1_CAP0 22 C7 33 44 [6] I; PU I TMS — Test Mode Select for JTAG interface. - I/O PIO_12 — General purpose digital input/output pin. - I AD1 — A/D converter, input 1. - I CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. TDO/PIO0_13/AD2/ CT32B1_MAT0 23 C8 34 45 [6] I; PU O TDO — Test Data Out for JTAG interface. - I/O PIO0_13 — General purpose digital input/output pin. - I AD2 — A/D converter, input 2. - O CT32B1_MAT0 — Match output 0 for 32-bit timer 1. TRST/PIO0_14/AD3/ CT32B1_MAT1 24 B7 35 46 [6] I; PU I TRST — Test Reset for JTAG interface. - I/O PIO0_14 — General purpose digital input/output pin. - I AD3 — A/D converter, input 3. - O CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO0_15/AD4/ CT32B1_MAT2 25 B6 39 52 [6] I; PU I/O SWDIO — Serial wire debug input/output. - I/O PIO0_15 — General purpose digital input/output pin. - I AD4 — A/D converter, input 4. - O CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO0_16/AD5/ CT32B1_MAT3/IOH_8/ WAKEUP 26 A6 40 53 [6] I; PU I/O PIO0_16 — General purpose digital input/output pin. - I AD5 — A/D converter, input 5. - O CT32B1_MAT3 — Match output 3 for 32-bit timer 1. - I/O IOH_8 — I/O Handler input/output 8. (LPC11U37HFBD64/401 only.) - I WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode, then pull LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 13 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller PIO0_17/RTS/ CT32B0_CAP0/SCLK 30 A3 45 60 [3] I; PU I/O PIO0_17 — General purpose digital input/output pin. - O RTS — Request To Send output for USART. - I CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. - I/O SCLK — Serial clock input/output for USART in synchronous mode. PIO0_18/RXD/ CT32B0_MAT0 31 B3 46 61 [3] I; PU I/O PIO0_18 — General purpose digital input/output pin. - I RXD — Receiver input for USART. Used in UART ISP mode. - O CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO0_19/TXD/ CT32B0_MAT1 32 B2 47 62 [3] I; PU I/O PIO0_19 — General purpose digital input/output pin. - O TXD — Transmitter output for USART. Used in UART ISP mode. - O CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO0_20/CT16B1_CAP0 7 F2 9 11 [3] I; PU I/O PIO0_20 — General purpose digital input/output pin. - I CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO0_21/CT16B1_MAT0/ MOSI1 12 G4 17 22 [3] I; PU I/O PIO0_21 — General purpose digital input/output pin. - O CT16B1_MAT0 — Match output 0 for 16-bit timer 1. - I/O MOSI1 — Master Out Slave In for SSP1. PIO0_22/AD6/ CT16B1_MAT1/MISO1 20 E8 30 40 [6] I; PU I/O PIO0_22 — General purpose digital input/output pin. - I AD6 — A/D converter, input 6. - O CT16B1_MAT1 — Match output 1 for 16-bit timer 1. - I/O MISO1 — Master In Slave Out for SSP1. PIO0_23/AD7/IOH_9 27 A5 42 56 [6] I; PU I/O PIO0_23 — General purpose digital input/output pin. - I AD7 — A/D converter, input 7. - I/O IOH_9 — I/O Handler input/output 9. (LPC11U37HFBD64/401 only.) PIO1_0/CT32B1_MAT0/ IOH_10 - - - 1 [3] I; PU I/O PIO1_0 — General purpose digital input/output pin. - O CT32B1_MAT0 — Match output 0 for 32-bit timer 1. - I/O IOH_10 — I/O Handler input/output 10. (LPC11U37HFBD64/401 only.) PIO1_1/CT32B1_MAT1/ IOH_11 - - - 17 [3] I; PU I/O PIO1_1 — General purpose digital input/output pin. - O CT32B1_MAT1 — Match output 1 for 32-bit timer 1. - I/O IOH_11 — I/O Handler input/output 11. (LPC11U37HFBD64/401 only.) PIO1_2/CT32B1_MAT2/ IOH_12 - - - 34 [3] I; PU I/O PIO1_2 — General purpose digital input/output pin. - O CT32B1_MAT2 — Match output 2 for 32-bit timer 1. - I/O IOH_12 — I/O Handler input/output 12. (LPC11U37HFBD64/401 only.) Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 14 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller PIO1_3/CT32B1_MAT3/ IOH_13 - - - 50 [3] I; PU I/O PIO1_3 — General purpose digital input/output pin. - O CT32B1_MAT3 — Match output 3 for 32-bit timer 1. - I/O IOH_13 — I/O Handler input/output 13. (LPC11U37HFBD64/401 only.) PIO1_4/CT32B1_CAP0/ IOH_14 - - - 16 [3] I; PU I/O PIO1_4 — General purpose digital input/output pin. - I CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. - I/O IOH_14 — I/O Handler input/output 14. (LPC11U37HFBD64/401 only.) PIO1_5/CT32B1_CAP1 /IOH_15 - H8 - 32 [3] I; PU I/O PIO1_5 — General purpose digital input/output pin. - I CT32B1_CAP1 — Capture input 1 for 32-bit timer 1. - I/O IOH_15 — I/O Handler input/output 15. (LPC11U37HFBD64/401 only.) PIO1_6/IOH_16 - - - 64 [3] I; PU I/O PIO1_6 — General purpose digital input/output pin. - I/O IOH_16 — I/O Handler input/output 16. (LPC11U37HFBD64/401 only.) PIO1_7/IOH_17 - - - 6 [3] I; PU I/O PIO1_7 — General purpose digital input/output pin. - I/O IOH_17 — I/O Handler input/output 17. (LPC11U37HFBD64/401 only.) PIO1_8/IOH_18 - - - 39 [3] I; PU I/O PIO1_8 — General purpose digital input/output pin. - I/O IOH_18 — I/O Handler input/output 18. (LPC11U37HFBD64/401 only.) PIO1_9 - - - 55 [3] I; PU I/O PIO1_9 — General purpose digital input/output pin. PIO1_10 - - - 12 [3] I; PU I/O PIO1_10 — General purpose digital input/output pin. PIO1_11 - - - 43 [3] I; PU I/O PIO1_11 — General purpose digital input/output pin. PIO1_12 - - - 59 [3] I; PU I/O PIO1_12 — General purpose digital input/output pin. PIO1_13/DTR/ CT16B0_MAT0/TXD - B8 36 47 [3] I; PU I/O PIO1_13 — General purpose digital input/output pin. - O DTR — Data Terminal Ready output for USART. - O CT16B0_MAT0 — Match output 0 for 16-bit timer 0. - O TXD — Transmitter output for USART. PIO1_14/DSR/ CT16B0_MAT1/RXD - A8 37 49 [3] I; PU I/O PIO1_14 — General purpose digital input/output pin. - I DSR — Data Set Ready input for USART. - O CT16B0_MAT1 — Match output 1 for 16-bit timer 0. - I RXD — Receiver input for USART. PIO1_15/DCD/ CT16B0_MAT2/SCK1 28 A4 43 57 [3] I; PU I/O PIO1_15 — General purpose digital input/output pin. I DCD — Data Carrier Detect input for USART. - O CT16B0_MAT2 — Match output 2 for 16-bit timer 0. - I/O SCK1 — Serial clock for SSP1. Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 15 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller PIO1_16/RI/ CT16B0_CAP0 - A2 48 63 [3] I; PU I/O PIO1_16 — General purpose digital input/output pin. - I RI — Ring Indicator input for USART. - I CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO1_17/CT16B0_CAP1/ RXD - - - 23 [3] I; PU I/O PIO1_17 — General purpose digital input/output pin. - I CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. - I RXD — Receiver input for USART. PIO1_18/CT16B1_CAP1/ TXD - - - 28 [3] I; PU I/O PIO1_18 — General purpose digital input/output pin. - I CT16B1_CAP1 — Capture input 1 for 16-bit timer 1. - O TXD — Transmitter output for USART. PIO1_19/DTR/SSEL1 1 B1 2 3 [3] I; PU I/O PIO1_19 — General purpose digital input/output pin. - O DTR — Data Terminal Ready output for USART. - I/O SSEL1 — Slave select for SSP1. PIO1_20/DSR/SCK1 - H1 13 18 [3] I; PU I/O PIO1_20 — General purpose digital input/output pin. - I DSR — Data Set Ready input for USART. - I/O SCK1 — Serial clock for SSP1. PIO1_21/DCD/MISO1 - G8 26 35 [3] I; PU I/O PIO1_21 — General purpose digital input/output pin. - I DCD — Data Carrier Detect input for USART. - I/O MISO1 — Master In Slave Out for SSP1. PIO1_22/RI/MOSI1 - A7 38 51 [3] I; PU I/O PIO1_22 — General purpose digital input/output pin. - I RI — Ring Indicator input for USART. - I/O MOSI1 — Master Out Slave In for SSP1. PIO1_23/CT16B1_MAT1/ SSEL1 - H4 18 24 [3] I; PU I/O PIO1_23 — General purpose digital input/output pin. - O CT16B1_MAT1 — Match output 1 for 16-bit timer 1. - I/O SSEL1 — Slave select for SSP1. PIO1_24/CT32B0_MAT0 - G6 21 27 [3] I; PU I/O PIO1_24 — General purpose digital input/output pin. - O CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_25/CT32B0_MAT1 - A1 1 2 [3] I; PU I/O PIO1_25 — General purpose digital input/output pin. - O CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_26/CT32B0_MAT2/ RXD/IOH_19 - G2 11 14 [3] I; PU I/O PIO1_26 — General purpose digital input/output pin. - O CT32B0_MAT2 — Match output 2 for 32-bit timer 0. - I RXD — Receiver input for USART. - I/O IOH_19 — I/O Handler input/output 19. (LPC11U37HFBD64/401 only.) PIO1_27/CT32B0_MAT3/ TXD/IOH_20 - G1 12 15 [3] I; PU I/O PIO1_27 — General purpose digital input/output pin. - O CT32B0_MAT3 — Match output 3 for 32-bit timer 0. - O TXD — Transmitter output for USART. - I/O IOH_20 — I/O Handler input/output 20. (LPC11U37HFBD64/401 only.) Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 16 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled; F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 32 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31). [4] I2C-bus pin compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31); includes high-current output driver. [6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 31); includes digital input glitch filter. [7] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [8] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). Leave XTALOUT floating. PIO1_28/CT32B0_CAP0/ SCLK - H7 24 31 [3] I; PU I/O PIO1_28 — General purpose digital input/output pin. - I CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. - I/O SCLK — Serial clock input/output for USART in synchronous mode. PIO1_29/SCK0/ CT32B0_CAP1 - D7 31 41 [3] I; PU I/O PIO1_29 — General purpose digital input/output pin. - I/O SCK0 — Serial clock for SSP0. - I CT32B0_CAP1 — Capture input 1 for 32-bit timer 0. PIO1_31 - - 25 - [3] I; PU I/O PIO1_31 — General purpose digital input/output pin. USB_DM 13 G5 19 25 [7] F - USB_DM — USB bidirectional D line. USB_DP 14 H5 20 26 [7] F - USB_DP — USB bidirectional D+ line. XTALIN 4 D1 6 8 [8] - - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5 E1 7 9 [8] - - Output from the oscillator amplifier. VDD 6; 29 B4; E2 8; 44 10; 33; 48; 58 - - Supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. VSS 33 B5; D2 5; 41 7; 54 - - Ground. Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 17 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 On-chip flash programming memory The LPC11U3x contain up to 128 kB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages. Individual pages can be erased using the IAP erase page command. 7.2 EEPROM The LPC11U3x contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM data memory. The EEPROM can be programmed using In-Application Programming (IAP) via the on-chip boot loader software. 7.3 SRAM The LPC11U3x contain a total of 8 kB, 10 kB, or 12 kB on-chip static RAM memory. On the LPC11U37HFBD64/401, the 2 kB SRAM1 region at location 0x2000 0000 to 0x2000 07FFF is used for the I/O Handler software library. Do not use this memory location for data or other user code. 7.4 On-chip ROM The on-chip ROM contains the boot loader and the following Application Programming Interfaces (APIs): • In-System Programming (ISP) and In-Application Programming (IAP) support for flash including IAP erase page command. • IAP support for EEPROM • USB API • Power profiles for configuring power consumption and PLL settings • 32-bit integer division routines 7.5 Memory map The LPC11U3x incorporates several distinct memory regions, shown in the following figures. Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This addressing scheme allows simplifying the address decoding for each peripheral. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 18 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.6.1 Features • Controls system exceptions and peripheral interrupts. • In the LPC11U3x, the NVIC supports 24 vectored interrupts. Fig 6. LPC11U3x memory map APB peripherals 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4004 C000 0x4005 8000 0x4005 C000 0x4006 0000 0x4006 4000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 0x4000 0000 WWDT 32-bit counter/timer 0 32-bit counter/timer 1 ADC USART/SMART CARD PMU I2C-bus 20 - 21 reserved 10 - 13 reserved reserved reserved 25 - 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0 GB 0x0000 0000 0.5 GB 4 GB 1 GB 0x1000 0000 0x1FFF 0000 0x1FFF 4000 0x2000 0000 0x5000 0000 0x5000 4000 0xFFFF FFFF reserved reserved reserved 2 kB USB RAM (LPC11U34/421 LPC11U35/401/501 LPC11U36/401/501 LPC11U37/401/501, LPC11U37H/401) reserved 0x4000 0000 0x4008 0000 0x4008 4000 APB peripherals USB GPIO 0x2000 4000 0x2000 4800 0x1000 2000 8 kB SRAM0 (LPC11U3x) LPC11U3x 0x0000 A000 40 kB on-chip flash (LPC11U34/311) 0x0000 C000 48 kB on-chip flash (LPC11U34/421) 0x0001 0000 64 kB on-chip flash (LPC11U35) 0x0001 8000 96 kB on-chip flash (LPC11U36) 0x0002 0000 128 kB on-chip flash (LPC11U37/7H) 16 kB boot ROM 0x0000 0000 0x0000 00C0 active interrupt vectors 002aag813 reserved reserved SSP0 SSP1 16-bit counter/timer 1 16-bit counter/timer 0 IOCON system control 19 GPIO interrupts 22 23 GPIO GROUP0 INT 24 GPIO GROUP1 INT flash/EEPROM controller 0xE000 0000 0xE010 0000 private peripheral bus 2 kB SRAM1 (LPC11U35/501 LPC11U37/501) I/O Handler code area for LPC11U37HFBD64/401 0x2000 0800 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 19 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 7.7 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Connect peripherals to the appropriate pins before activating the peripheral and before enabling any related interrupt. Activity of any enabled peripheral function that is not mapped to a related pin is treated as undefined. 7.7.1 Features • Programmable pull-up, pull-down, or repeater mode. • All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their pull-up resistor is enabled. • Programmable pseudo open-drain mode. • Programmable 10 ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to PIO0_16. The glitch filter is turned on by default. • Programmable hysteresis. • Programmable input inverter. 7.8 General-Purpose Input/Output GPIO The GPIO registers control device pin functions that are not connected to a specific peripheral function. Pins can be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC11U3x use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved. • Entire port value can be written in one instruction. Any GPIO pin providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. The GPIO block consists of three parts: 1. The GPIO ports. 2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts. 3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO pins. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 20 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.8.1 Features • GPIO pins can be configured as input or output by software. • All GPIO pins default to inputs with interrupt disabled at reset. • Pin registers allow pins to be sensed and set individually. • Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • Any pin or pins in each port can trigger a port interrupt. 7.9 USB interface The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the devices. The host controller initiates all transactions. The LPC11U3x USB interface consists of a full-speed device controller with on-chip PHY (PHYsical layer) for device functions. Remark: Configure the LPC11U3x in default power mode with the power profiles before using the USB (see Section 7.18.5.1). Do not use the USB with the part in performance, efficiency, or low-power mode. 7.9.1 Full-speed USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. If enabled, an interrupt is generated. 7.9.1.1 Features • Dedicated USB PLL available. • Fully compliant with USB 2.0 specification (full speed). • Supports 10 physical (5 logical) endpoints including one control endpoint. • Single and double buffering supported. • Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. • Supports wake-up from Deep-sleep mode and Power-down mode on USB activity and remote wake-up. • Supports SoftConnect. 7.10 I/O Handler (LPC11U37HFBD64/401 only) The I/O Handler is a software library-supported hardware engine for emulating serial interfaces and off-loading the CPU for processing-intensive functions. The I/O Handler can emulate, among others, DMA and serial interfaces such as UART, I2C, or I2S with no or very low additional CPU load. The software libraries are available with supporting LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 21 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller application notes from NXP (see http://www.LPCware.com.) LPCXpresso, Keil, and IAR IDEs are supported. I/O Handler library code must be executed from the memory area 0x2000 0000 to 0x2000 07FF. This memory is not available for other use. For application examples, see Section 11.8 “I/O Handler software library applications”. Each I/O Handler library uses a specific subset of I/O Handler pins and in some cases other pins and peripherals such as the counter/timers. 7.11 USART The LPC11U3x contains one USART. The USART includes full modem control, support for synchronous mode, and a smart card interface. The RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The USART uses a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.11.1 Features • Maximum USART data bit rate of 3.125 Mbit/s. • 16 byte receive and transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit mode. • Support for modem control. • Support for synchronous mode. • Includes smart card interface. 7.12 SSP serial I/O controller The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. The controller can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.12.1 Features • Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode) • Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 22 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame 7.13 I2C-bus serial I/O controller The LPC11U3x contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, and more than one bus master connected to the interface can be controlled the bus. 7.13.1 Features • The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.14 10-bit ADC The LPC11U3x contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.14.1 Features • 10-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range 0 V to VDD. • 10-bit conversion time  2.44 s (up to 400 kSamples/s). • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 23 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.15 General purpose external event counter/timers The LPC11U3x includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.15.1 Features • A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. • Counter or timer operation. • Up to two capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event can also generate an interrupt. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • The timer and prescaler can be configured to be cleared on a designated capture event. This feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. 7.16 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.17 Windowed WatchDog Timer (WWDT) The purpose of the WWDT is to prevent an unresponsive system state. If software fails to update the watchdog within a programmable time window, the watchdog resets the microcontroller 7.17.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time before watchdog time-out. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 24 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller • Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is required to disable the WWDT. • Incorrect feed sequence causes reset or interrupt, if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated watchdog oscillator (WDO). The clock source selection provides a wide range of potential timing choices of watchdog operation under different power conditions. 7.18 Clocking and power control 7.18.1 Integrated oscillators The LPC11U3x include three independent oscillators: the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11U3x operates from the internal RC oscillator until software switches to a different clock source. The IRC allows the system to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 7 for an overview of the LPC11U3x clock generation. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 25 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.18.1.1 Internal RC oscillator The IRC can be used as the clock source for the WDT, and/or as the clock that drives the system PLL and then the CPU. The nominal IRC frequency is 12 MHz. Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U3x use the IRC as the clock source. Software can later switch to one of the other available clock sources. Fig 7. LPC11U3x clocking generation block diagram system oscillator watchdog oscillator IRC oscillator USB PLL USBPLLCLKSEL (USB clock select) SYSTEM CLOCK DIVIDER SYSAHBCLKCTRLn (AHB clock enable) CPU, system control, PMU memories, peripheral clocks SSP0 PERIPHERAL CLOCK DIVIDER SSP0 SSP1 PERIPHERAL CLOCK DIVIDER SSP1 USART PERIPHERAL CLOCK DIVIDER UART WDT WDCLKSEL (WDT clock select) USB 48 MHz CLOCK DIVIDER USB USBUEN (USB clock update enable) watchdog oscillator IRC oscillator system oscillator CLKOUT PIN CLOCK DIVIDER CLKOUT pin CLKOUTUEN (CLKOUT update enable) 002aaf892 system clock SYSTEM PLL IRC oscillator system oscillator watchdog oscillator MAINCLKSEL (main clock select) SYSPLLCLKSEL (system PLL clock select) main clock IRC oscillator n LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 26 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.18.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC11U3x, use the system oscillator to provide the clock source to USB. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 7.18.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and temperature is 40 % (see also Table 13). 7.18.2 System PLL and USB PLL The LPC11U3x contain a system PLL and a dedicated PLL for generating the 48 MHz USB clock. The system and USB PLLs are identical. The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset. Software can enable the PLL later. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.18.3 Clock output The LPC11U3x feature a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.18.4 Wake-up process The LPC11U3x begin operation by using the 12 MHz IRC oscillator as the clock source at power-up and when awakened from Deep power-down mode . This mechanism allows chip operation to resume quickly. If the application uses the main oscillator or the PLL, software must enable these components and wait for them to stabilize. Only then can the system use the PLL and main oscillator as a clock source. 7.18.5 Power control The LPC11U3x support various power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate can also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This power control mechanism allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals. This register allows fine-tuning of power LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 27 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.18.5.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the LPC11U3x for one of the following power modes: • Default mode corresponding to power configuration after reset. • CPU performance mode corresponding to optimized processing capability. • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. Remark: When using the USB, configure the LPC11U3x in Default mode. 7.18.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and can generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, by memory systems and related controllers, and by internal buses. 7.18.5.3 Deep-sleep mode In Deep-sleep mode, the LPC11U3x is in Sleep-mode and all peripheral clocks and all clock sources are off except for the IRC. The IRC output is disabled unless the IRC is selected as input to the watchdog timer. In addition all analog blocks are shut down and the flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC11U3x can wake up from Deep-sleep mode via reset, selected GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity. Deep-sleep mode saves power and allows for short wake-up times. 7.18.5.4 Power-down mode In Power-down mode, the LPC11U3x is in Sleep-mode and all peripheral clocks and all clock sources are off except for watchdog oscillator if selected. In addition all analog blocks and the flash are shut down. In Power-down mode, the application can keep the BOD circuit running for BOD protection. The LPC11U3x can wake up from Power-down mode via reset, selected GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 28 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 7.18.5.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin. The LPC11U3x can wake up from Deep power-down mode via the WAKEUP pin. The LPC11U3x can be prevented from entering Deep power-down mode by setting a lock bit in the PMU block. Locking out Deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times. When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. 7.18.6 System control 7.18.6.1 Reset Reset has four sources on the LPC11U3x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. In Deep power-down mode, an external pull-up resistor is required on the RESET pin. 7.18.6.2 Brownout detection The LPC11U3x includes up to four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Four threshold levels can be selected to cause a forced reset of the chip. 7.18.6.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details, see the LPC11Uxx user manual. There are three levels of Code Read Protection: LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 29 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details, see the LPC11Uxx user manual. 7.18.6.4 APB interface The APB peripherals are located on one APB bus. 7.18.6.5 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the ROM. 7.18.6.6 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 30 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.19 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC11U3x is in reset. To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 31 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 8. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table 5. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 5) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] See Table 6 for maximum operating voltage. [4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [5] Including voltage on outputs in 3-state mode. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD supply voltage (core and external rail) [2] 0.5 +4.6 V VI input voltage 5 V tolerant digital I/O pins; VDD  1.8 V [5][2] 0.5 +5.5 V VDD = 0 V 0.5 +3.6 V 5 V tolerant open-drain pins PIO0_4 and PIO0_5 [2][4] 0.5 +5.5 VIA analog input voltage pin configured as analog input [2] [3] 0.5 4.6 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); Tj < 125 C - 100 mA Tstg storage temperature non-operating [6] 65 +150 C Tj(max) maximum junction temperature - 150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [7]- +6500 V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 32 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 5. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD supply voltage (core and external rail) [2] 1.8 3.3 3.6 V IDD supply current Active mode; VDD = 3.3 V; Tamb = 25 C; code while(1){} executed from flash; system clock = 12 MHz [3][4][5] [6][7][8] - 2 - mA system clock = 50 MHz [4][5][6] [7][8][9] - 7 - mA Sleep mode; VDD = 3.3 V; Tamb = 25 C; system clock = 12 MHz [3][4][5] [6][7][8] - 1 - mA Deep-sleep mode; VDD = 3.3 V; Tamb = 25 C [4][7]- 300 - A Power-down mode; VDD = 3.3 V; Tamb = 25 C - 2 - A Deep power-down mode; VDD = 3.3 V; Tamb = 25 C [10]- 220 - nA Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function; VDD  1.8 V [11] [12] 0 - 5.0 V VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage 2.0 V  VDD  3.6 V; IOH = 4 mA VDD  0.4- - V 1.8 V  VDD < 2.0 V; IOH = 3 mA VDD  0.4- - V VOL LOW-level output voltage 2.0 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.0 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.0 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.0 V 3 - - mA LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 33 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller IOL LOW-level output current VOL = 0.4 V 2.0 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.0 V 3 - - mA IOHS HIGH-level short-circuit output current VOH = 0 V [13]- - 45 mA IOLS LOW-level short-circuit output current VOL = VDD [13]- - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; 2.0 V  VDD  3.6 V 15 50 85 A 1.8 V  VDD < 2.0 V 10 50 85 A VDD < VI < 5 V 0 0 0 A High-drive output pin (PIO0_7) IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function; VDD  1.8 V [11] [12] 0 - 5.0 V VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 20 mA VDD  0.4- - V 1.8 V  VDD < 2.5 V; IOH = 12 mA VDD  0.4- - V VOL LOW-level output voltage 2.0 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.0 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.5 V 12 - - mA IOL LOW-level output current VOL = 0.4 V 2.0 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.0 V 3 - - mA IOLS LOW-level short-circuit output current VOL = VDD [13]- - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 34 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Ipu pull-up current VI = 0 V 2.0 V  VDD  3.6 V 15 50 85 A 1.8 V  VDD < 2.0 V 10 50 85 A VDD < VI < 5 V 0 0 0 A I2C-bus pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as standard mode pins 2.0 V  VDD  3.6 V 3.5 - - mA 1.8 V  VDD < 2.0 V 3 - - IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as Fast-mode Plus pins 2.0 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.0 V 16 - - ILI input leakage current VI = VDD [14]- 2 4 A VI = 5 V - 10 22 A Oscillator pins Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V USB pins IOZ OFF-state output current 0 V < VI < 3.3 V [2]- - 10 A VBUS bus supply voltage [2]- - 5.25 V VDI differential input sensitivity voltage (D+)  (D) [2] 0.2 - - V VCM differential common mode voltage range includes VDI range [2] 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage [2] 0.8 - 2.0 V VOL LOW-level output voltage for low-/full-speed; RL of 1.5 k to 3.6 V [2]- - 0.18 V VOH HIGH-level output voltage driven; for low-/full-speed; RL of 15 k to GND [2] 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND [2]- - 20 pF ZDRV driver output impedance for driver which is not high-speed capable with 33  series resistor; steady state drive [15][2] 36 - 44.1  Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 35 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V  VDD  3.6 V. Guaranteed by design. [3] IRC enabled; system oscillator disabled; system PLL disabled. [4] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [5] BOD disabled. [6] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the SYSCON block. [7] USB_DP and USB_DM pulled LOW externally. [8] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [9] IRC disabled; system oscillator enabled; system PLL enabled. [10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode. [11] Including voltage on outputs in 3-state mode. [12] 3-state outputs go into 3-state mode in Deep power-down mode. [13] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [14] To VSS. [15] Includes external resistors of 33   1 % on USB_DP and USB_DM. Pin capacitance Cio input/output capacitance pins configured for analog function - - 7.1 pF I2C-bus pins (PIO0_4 and PIO0_5) - - 2.5 pF pins configured as GPIO - - 2.8 pF Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 36 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 8. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 8. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 8. [6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 8. [7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF. [8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia). Table 6. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDD V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2]- - 1 LSB EL(adj) integral non-linearity [3]- - 1.5 LSB EO offset error [4]- - 3.5 LSB EG gain error [5]- - 0.6 % ET absolute error [6]- - 4 LSB Rvsi voltage source interface resistance - - 40 k Ri input resistance [7][8]- - 2.5 M LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 37 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 8. ADC characteristics 002aaf426 1023 1022 1021 1020 1019 (2) (1) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 LSB (ideal) code out VDD − VSS 1024 offset error EO gain error EG offset error EO VIA (LSBideal) 1 LSB = LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 38 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 9.1 BOD static characteristics [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the LPC11Uxx user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see the LPC11Uxx user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. Table 7. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Min Typ Max Unit Vth threshold voltage interrupt level 1 assertion - 2.22 - V de-assertion - 2.35 - V interrupt level 2 assertion - 2.52 - V de-assertion - 2.66 - V interrupt level 3 assertion - 2.80 - V de-assertion - 2.90 - V reset level 0 assertion - 1.46 - V de-assertion - 1.63 - V reset level 1 assertion - 2.06 - V de-assertion - 2.15 - V reset level 2 assertion - 2.35 - V de-assertion - 2.43 - V reset level 3 assertion - 2.63 - V de-assertion - 2.71 - V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 39 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Conditions: Tamb = 25 C; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. Typical supply current versus regulator supply voltage VDD in active mode Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 10. Typical supply current versus temperature in Active mode VDD (V) 1.8 2.4 3.0 3.6 002aag749 3 6 9 IDD (mA) 0 12 MHz(1) 24 MHz(2) 36 MHz(2) 48 MHz(2) temperature (°C) -40 -15 10 35 60 85 002aag750 3 6 9 IDD (mA) 0 12 MHz(1) 24 MHz(2) 36 MHz(2) 48 MHz(2) LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 40 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 11. Typical supply current versus temperature in Sleep mode Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; USB_DP and USB_DM pulled LOW externally. Fig 12. Typical supply current versus temperature in Deep-sleep mode 002aag751 temperature (°C) -40 -15 10 35 60 85 1 3 2 4 IDD (mA) 0 12 MHz(1) 36 MHz(2) 48 MHz(2) 24 MHz(2) 002aag745 temperature (°C) -40 -15 10 35 60 85 355 375 365 385 IDD (μA) 345 VDD = 3.6 V VDD = 3.3 V VDD = 2.0 V VDD = 1.8 V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 41 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz. Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; USB_DP and USB_DM pulled LOW externally. Fig 13. Typical supply current versus temperature in Power-down mode Fig 14. Typical supply current versus temperature in Deep power-down mode 002aag746 temperature (°C) -40 -15 10 35 60 85 5 15 10 20 IDD (μA) 0 VDD = 3.6 V, 3.3 V VDD = 2.0 V VDD = 1.8 V 002aag747 temperature (°C) -40 -15 10 35 60 85 0.2 0.6 0.4 0.8 IDD (μA) 0 VDD = 3.6 V VDD = 3.3 V VDD = 2.0 V VDD = 1.8 V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 42 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Table 8. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.004 - - System oscillator running; PLL off; independent of main clock frequency. BOD 0.051 - - Independent of main clock frequency. Main PLL - 0.21 - - ADC - 0.08 0.29 - CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV register. CT16B0 - 0.02 0.06 - CT16B1 - 0.02 0.06 - CT32B0 - 0.02 0.07 - CT32B1 - 0.02 0.06 - GPIO - 0.23 0.88 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. IOCONFIG - 0.03 0.10 - I2C - 0.04 0.13 - ROM - 0.04 0.15 - SPI0 - 0.12 0.45 - SPI1 - 0.12 0.45 - UART - 0.22 0.82 - WWDT - 0.02 0.06 Main clock selected as clock source for the WDT. USB - - 1.2 - LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 43 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 9.4 Electrical pin characteristics Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 15. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 16. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL IOH (mA) 0 10 20 30 40 50 60 002aae990 2.8 2.4 3.2 3.6 VOH (V) 2 T = 85 °C 25 °C −40 °C VOL (V) 0 0.2 0.4 0.6 002aaf019 20 40 60 IOL (mA) 0 T = 85 °C 25 °C −40 °C LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 44 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL Conditions: VDD = 3.3 V; standard port pins. Fig 18. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH VOL (V) 0 0.2 0.4 0.6 002aae991 5 10 15 IOL (mA) 0 T = 85 °C 25 °C −40 °C IOH (mA) 0 8 16 24 002aae992 2.8 2.4 3.2 3.6 VOH (V) 2 T = 85 °C 25 °C −40 °C LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 45 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Conditions: VDD = 3.3 V; standard port pins. Fig 19. Typical pull-up current Ipu versus input voltage VI Conditions: VDD = 3.3 V; standard port pins. Fig 20. Typical pull-down current Ipd versus input voltage VI VI (V) 0 1 2 3 4 5 002aae988 −30 −50 −10 10 Ipu (μA) −70 T = 85 °C 25 °C −40 °C VI (V) 0 1 2 3 4 5 002aae989 40 20 60 80 Ipd (μA) 0 T = 85 °C 25 °C −40 °C LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 46 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Flash memory [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 100000 - cycles tret retention time powered 10 - - years unpowered 20 - - years ter erase time sector or multiple consecutive sectors 95 100 105 ms tprog programming time [2] 0.95 1 1.05 ms Table 10. EEPROM characteristics Tamb = 40 C to +85C; VDD = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 100000 1000000 - cycles tret retention time powered 100 200 - years unpowered 150 300 - years tprog programming time 64 bytes - 2.9 - ms Table 11. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 47 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 10.3 Internal oscillators [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Table 12. Dynamic characteristics: IRC Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 22. Internal RC oscillator frequency versus temperature Table 13. Dynamic characteristics: Watchdog oscillator Symbol Parameter Conditions Min Typ[1] Max Unit fosc(int) internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; [2][3]- 9.4 - kHz DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] - 2300 - kHz 002aaf403 11.95 12.05 12.15 f (MHz) 11.85 temperature (°C) −40 −15 10 35 60 85 VDD = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 2.0 V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 48 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %. [3] See the LPC11Uxx user manual. 10.4 I/O pins [1] Applies to standard port pins and RESET pin. 10.5 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Table 14. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns Table 15. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz tf fall time [4][5][6][7] of both SDA and SCL signals Standard-mode - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s tHD;DAT data hold time [3][4][8] Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 49 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Fig 23. I2C-bus pins clock timing 002aaf425 tf 70 % SDA 30 % tf 70 % 30 % S 70 % 30 % 70 % 30 % tHD;DAT SCL 1 / fSCL 70 % 30 % 70 % 30 % tVD;DAT tHIGH tLOW tSU;DAT LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 50 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 10.6 SSP interface [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). [2] Tamb = 40 C to 85 C. [3] Tcy(clk) = 12  Tcy(PCLK). [4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V. Table 16. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI master (in SPI mode) Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 ns tDS data set-up time in SPI mode 2.4 V  VDD  3.6 V [2] 15 - - ns 2.0 V  VDD < 2.4 V [2] 20 ns 1.8 V  VDD < 2.0 V [2] 24 - - ns tDH data hold time in SPI mode [2] 0 - - ns tv(Q) data output valid time in SPI mode [2] - - 10 ns th(Q) data output hold time in SPI mode [2] 0 - - ns SPI slave (in SPI mode) Tcy(PCLK) PCLK cycle time 20 - - ns tDS data set-up time in SPI mode [3][4] 0 - - ns tDH data hold time in SPI mode [3][4] 3  Tcy(PCLK) + 4 - - ns tv(Q) data output valid time in SPI mode [3][4] - - 3  Tcy(PCLK) + 11 ns th(Q) data output hold time in SPI mode [3][4] - - 2  Tcy(PCLK) + 5 ns LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 51 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 24. SSP master timing in SPI mode SCK (CPOL = 0) MOSI MISO Tcy(clk) tDS tDH tv(Q) DATA VALID DATA VALID th(Q) SCK (CPOL = 1) DATA VALID DATA VALID MOSI MISO tDS tDH DATA VALID DATA VALID th(Q) DATA VALID DATA VALID tv(Q) CPHA = 1 CPHA = 0 002aae829 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 52 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 25. SSP slave timing in SPI mode SCK (CPOL = 0) MOSI MISO Tcy(clk) tDS tDH tv(Q) DATA VALID DATA VALID th(Q) SCK (CPOL = 1) DATA VALID DATA VALID MOSI MISO tDS tDH tv(Q) DATA VALID DATA VALID th(Q) DATA VALID DATA VALID CPHA = 1 CPHA = 0 002aae830 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 53 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 10.7 USB interface [1] Characterized but not implemented as production test. Guaranteed by design. Table 17. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 26 160 - 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 26 2 - +5 ns tJR1 receiver jitter to next transition 18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns tEOPR EOP width at receiver must accept as EOP; see Figure 26 [1] 82 - - ns Fig 26. Differential data-to-EOP transition skew and EOP width aaa-009330 TPERIOD differential data lines crossover point source EOP width: tFEOPT receiver EOP width: tEOPR crossover point extended differential data to SE0/EOP skew n TPERIOD + tFDEOP LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 54 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 Suggested USB interface solutions The USB device can be connected to the USB as self-powered device (see Figure 27) or bus-powered device (see Figure 28). On the LPC11U3x, the PIO0_3/USB_VBUS pin is 5 V tolerant only when VDD is applied and at operating voltage level. Therefore, if the USB_VBUS function is connected to the USB connector and the device is self-powered, the USB_VBUS pin must be protected for situations when VDD = 0 V. If VDD is always greater than 0 V while VBUS = 5 V, the USB_VBUS pin can be connected directly to the VBUS pin on the USB connector. For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum allowable voltage on the USB_VBUS pin in this case. One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allowable maximum voltage. For the following operating conditions VBUSmax = 5.25 V VDD = 3.6 V, the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V. Fig 27. USB interface on a self-powered device where USB_VBUS = 5 V LPC1xxx USB-B connector USB_DP USB_CONNECT soft-connect switch USB_DM USB_VBUS VSS VDD R1 1.5 kΩ RS = 33 Ω aaa-010178 RS = 33 Ω R2 R3 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 55 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller For a bus-powered device, the VBUS signal does not need to be connected to the USB_VBUS pin (see Figure 28). The USB_CONNECT function can additionally be connected as shown in Figure 27 to prevent the USB from timing out when there is a significant delay between power-up and handling USB traffic. Remark: When a bus-powered circuit as shown in Figure 28 is used, configure the PIO0_3/USB_VBUS pin for GPIO (PIO0_3) in the IOCON block to ensure that the USB_CONNECT signal can still be controlled by software. For details on the soft-connect feature, see the LPC11U3x user manual (Ref. 1). Remark: When a self-powered circuit is used without connecting VBUS, configure the PIO0_3/USB_VBUS pin for GPIO (PIO0_3) and provide software that can detect the host presence through some other mechanism before enabling USB_CONNECT and the soft-connect feature. Enabling the soft-connect without host presence will lead to USB compliance failure. Fig 28. USB interface on a bus-powered device LPC1xxx VDD R1 1.5 kΩ aaa-010179 USB-B connector USB_DP USB_DM VSS RS = 33 Ω RS = 33 Ω REGULATOR VBUS LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 56 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV (RMS) is needed. In slave mode, couple the input clock signal with a capacitor of 100 pF (Figure 29), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This signal corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 30 and in Table 18 and Table 19. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (L, CL and RS represent the fundamental frequency). Capacitance CP in Figure 30 represents the parallel package capacitance and must not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer. Fig 29. Slave mode operation of the on-chip oscillator Fig 30. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation LPC1xxx XTALIN Ci 100 pF Cg 002aae788 002aaf424 LPC1xxx XTALIN XTALOUT CX1 CX2 XTAL = CL CP RS L LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 57 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines Follow these guidelines for PCB layout: • Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip. • Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal use have a common ground plane. • Connect the external components to the ground plain. • To keep parasitics and the noise coupled in via the PCB as small as possible, keep loops as small as possible. • Choose smaller values of Cx1 and Cx2 if parasitics of the PCB layout increase. Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF Table 19. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 58 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.4 Standard I/O pad configuration Figure 31 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input Fig 31. Standard I/O pad configuration PIN VDD VDD ESD VSS ESD strong pull-up strong pull-down VDD weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input 002aaf695 pin configured as digital output driver pin configured as digital input pin configured as analog input 10 ns RC GLITCH FILTER LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 59 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.5 Reset pad configuration 11.6 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See Figure 33. The effective input impedance, Rin, seen by the external voltage source, VEXT, is the parallel impedance of ((1/fs x Cia) + Rmux + Rsw) and (1/fs x Cio), and can be calculated using Equation 1 with fs = sampling frequency Cia = ADC analog input capacitance Rmux = analog mux resistance Rsw = switch resistance Cio = pin capacitance (1) Fig 32. Reset pad configuration VSS reset 002aaf274 VDD VDD VDD Rpu ESD ESD 20 ns RC GLITCH FILTER PIN Fig 33. ADC input channel Cia Rs VSS VEXT 002aah615 ADC COMPARATOR ADC Block Rin Cio Rmux Rsw Source <2 kΩ <1.3 kΩ Rin 1 fs  Cia ----------------- + Rmux + Rsw   1 fs  Cio ----------------- =    LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 60 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Under nominal operating condition VDD = 3.3 V and with the maximum sampling frequency fs = 400 kHz, the parameters assume the following values: Cia = 1 pF (max) Rmux = 2 kΩ (max) Rsw = 1.3 kΩ (max) Cio = 7.1 pF (max) The effective input impedance with these parameters is Rin = 308 kΩ. 11.7 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 6: • The ADC input trace must be short and as close as possible to the LPC11U3x chip. • Shield The ADC input traces from fast switching digital signals and noisy power supply lines. • The ADC and the digital core share the same power supply. Therefore, filter the power supply line adequately. • To improve the ADC performance in a noisy environment, put the device in Sleep mode during the ADC conversion. 11.8 I/O Handler software library applications The following sections provide application examples for the I/O Handler software library. All library examples make use of the I/O Handler hardware to extend the functionality of the part through software library calls. The libraries are available on http://www.LPCware.com. 11.8.1 I/O Handler I2S The I/O Handler software library provides functions to emulate an I2S master transmit interface using the I/O Handler hardware block. The emulated I2S interface loops over a 1 kB buffer, transmitting the datawords according to the I2S protocol. Interrupts are generated every time when the first 512 bytes have been transmitted and when the last 512 bytes have been transmitted. This allows the ARM core to load the free portion of the buffer with new data, thereby enabling streaming audio. Two channels with 16-bit per channel are supported. The code size of the software library is 1 kB and code must be executed from the SRAM1 memory area reserved for the I/O Handler code. 11.8.2 I/O Handler UART The I/O Handler UART library emulates one additional full-duplex UART. The emulated UART can be configured for 7 or 8 data bits, no parity, and 1 or 2 stop bits. The baud rate is configurable up to 115200 baud. The RXD signal is available on three I/O Handler pins (IOH_6, IOH_16, IOH_20), while TXD and CTS are available on all 21 I/O Handler pins. The code size of the software library is about 1.2 kB and code must be executed from the SRAM1 memory area reserved for the I/O Handler code. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 61 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.8.3 I/O Handler I2C The I/O Handler I2C library allows to have an additional I2C-bus master. I2C read, I2C write and combined I2C read/write are supported. Data is automatically read from and written to user-defined buffers. The I/O Handler I2C library combined with the on-chip I2C module allows to have two distinct I2C buses, allowing to separate low-speed from high-speed devices or bridging two I2C buses. 11.8.4 I/O Handler DMA The I/O Handler DMA library offers DMA-like functionality. Four types of transfer are supported: memory to memory, memory to peripheral, peripheral to memory and peripheral to peripheral. Supported peripherals are USART, SSP0/1, ADC and GPIO. DMA transfers can be triggered by the source/target peripheral, software, counter/timer module CT16B1, or I/O Handler pin PIO1_6/IOH_16. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 62 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 12. Package outline Fig 34. Package outline HVQFN33 (5 x 5 x 0.85 mm) Outline References version European projection Issue date IEC JEDEC JEITA MO-220 hvqfn33f_po 11-10-11 11-10-17 Unit(1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 A1 Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm b c 0.30 0.18 A(1) D(1) Dh E(1) Eh e e1 e2 L 3.5 v w 0.1 0.1 y 0.05 0.5 0.3 y1 0.05 0 2.5 5 mm scale 1/2 e v C A B w C terminal 1 index area A A1 c detail X y1 C y e L Eh Dh e e1 b 9 16 32 25 24 8 17 1 X D E C B A e2 terminal 1 index area 1/2 e LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 63 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 35. Package outline HVQFN33 (7 x 7 x 0.85 mm) Outline References version European projection Issue date IEC JEDEC JEITA - - - hvqfn33_po 09-03-17 09-03-23 Unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 A(1) Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm A1 b 0.35 0.28 0.23 c D(1) Dh E(1) Eh 4.85 4.70 4.55 e e1 e2 4.55 L v 0.1 w 0.05 y 0.08 y1 0 2.5 5 mm scale terminal 1 index area D B A E C y1 C y X detail X A1 A c b e2 e1 e e v C A B w C terminal 1 index area Dh Eh L 9 16 32 33 25 17 24 8 1 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 64 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 36. Package outline TFBGA48 (SOT1155-2) Outline References version European projection Issue date IEC JEDEC JEITA SOT1155-2 - - - sot1155-2_po 13-06-17 13-06-19 Unit mm max nom min 1.10 0.95 0.85 0.30 0.25 0.20 0.35 0.30 0.25 4.6 4.5 4.4 4.6 4.5 4.4 0.5 3.5 0.15 0.08 A Dimensions TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm SOT1155-2 A1 A2 0.80 0.70 0.65 b D E e e1 3.5 e2 v w 0.05 y y1 0.1 0 5 mm scale ball A1 index area D B A E A B C D E F H G 1 2 3 4 5 6 7 8 b e2 e1 e e 1/2 e 1/2 e ball A1 index area solder mask open area not for solder ball C y1 C y X detail X A A2 A1 Ø v C A B Ø w C LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 65 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 37. Package outline LQFP48 (SOT313-2) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o 1 0.2 0.12 0.1 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT313-2 136E05 MS-026 00-01-19 03-02-25 D(1) (1) (1) 7.1 6.9 HD 9.15 8.85 Z E 0.95 0.55 D bp e E B 12 HD bp HE v M B D ZD A ZE e v M A 1 48 37 36 25 24 13 θ A1 A Lp detail X L (A 3 ) A2 X y c w M w M 0 2.5 5 mm scale pin 1 index LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 66 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 38. Package outline LQFP64 (SOT314-2) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o 1 0.2 0.12 0.1 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT314-2 136E10 MS-026 00-01-19 03-02-25 D(1) (1) (1) 10.1 9.9 HD 12.15 11.85 Z E 1.45 1.05 D bp e θ E A1 A Lp detail X L (A 3 ) B 16 c HD bp HE A2 v M B D ZD A ZE e v M A X 1 64 49 48 33 32 17 y pin 1 index w M w M 0 2.5 5 mm scale LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 67 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 13. Soldering Fig 39. Reflow soldering for the HVQFN33 (5x5) package Footprint information for reflow soldering of HVQFN33 package occupied area solder paste solder land Dimensions in mm P 0.5 Issue date 002aag766 11-11-15 11-11-20 Ax Ay Bx C D 5.95 5.95 4.25 0.85 By 4.25 0.27 Gx 5.25 Gy 5.25 Hy 6.2 Hx 6.2 SLx SLy nSPx nSPy 3.75 3.75 3 3 0.30 0.60 detail X C SLy D SLx Bx Ay P nSPy nSPx see detail X Gx Hx Hy Gy By Ax LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 68 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 40. Reflow soldering for the HVQFN33 (7x7) package Footprint information for reflow soldering of HVQFN33 package occupied area 001aao134 solder land solder resist solder land plus solder paste solder paste deposit Dimensions in mm Remark: Stencil thickness: 0.125 mm e = 0.65 evia = 4.25 OwDtot = 5.10 OA PID = 7.25 PA+OA OID = 8.20 OA 0.20 SR chamfer (4×) 0.45 DM evia = 1.05 W = 0.30 CU evia = 4.25 evia = 2.40 LbE = 5.80 CU LbD = 5.80 CU PIE = 7.25 PA+OA LaE = 7.95 CU LaD = 7.95 CU OIE = 8.20 OA OwEtot = 5.10 OA EHS = 4.85 CU DHS = 4.85 CU 4.55 SR 4.55 SR B-side (A-side fully covered) number of vias: 20 Solder resist covered via 0.30 PH 0.60 SR cover 0.60 CU SEhtot = 2.70 SP SDhtot = 2.70 SP GapE = 0.70 SP SPE = 1.00 SP SPD = 1.00 SP 0.45 DM GapD = 0.70 SP LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 69 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 41. Reflow soldering for the TFBGA48 package DIMENSIONS in mm P SL SP SR Hx Hy Hx Hy SOT1155-2 solder land plus solder paste occupied area Footprint information for reflow soldering of TFBGA48 package solder land solder paste deposit solder resist P P SL SP SR detail X see detail X 0.50 0.225 0.275 0.325 4.75 4.75 sot1155-2_fr LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 70 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 42. Reflow soldering for the LQFP48 package SOT313-2 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP48 package Ax Bx Gx Hy Gy Hx By Ay P1 D2 (8×) D1 (0.125) Ax Ay Bx By D1 D2 Gx Gy Hx Hy 10.350 P2 0.560 10.350 7.350 7.350 P1 0.500 0.280 C 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land C Generic footprint pattern Refer to the package outline drawing for actual layout P2 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 71 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 43. Reflow soldering for the LQFP64 package SOT314-2 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP64 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) Ax Ay Bx By D1 D2 Gx Gy Hx Hy 13.300 13.300 10.300 10.300 P1 0.500 P2 0.560 0.280 C 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land C Generic footprint pattern Refer to the package outline drawing for actual layout LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 72 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 14. Abbreviations 15. References [1] LPC11U3x User manual UM10462: http://www.nxp.com/documents/user_manual/UM10462.pdf [2] LPC11U3x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11U3X.pdf Table 20. Abbreviations Acronym Description A/D Analog-to-Digital ADC Analog-to-Digital Converter AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input/Output JTAG Joint Test Action Group PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TAP Test Access Port USART Universal Synchronous Asynchronous Receiver/Transmitter LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 73 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 16. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11U3X v.2.2 20140311 Product data sheet - LPC11U3X v.2.1 Modifications: • Use of USB_CONNECT signal explained in Section 11.1 “Suggested USB interface solutions”. • Open-drain I2C-bus and RESET pin descriptions clarified. See Table 3. LPC11U3X v.2.1 20131230 Product data sheet - LPC11U3X v.2 Modifications: Add reserved function to pins PIO0_8/MISO0/CT16B0_MAT0/R/IOH_6 and PIO0_9/MOSI0/CT16B0_MAT1/R/IOH_7. LPC11U3X v.2 20131125 Product data sheet - LPC11U3X v.1.1 Modifications: • Part LPC11U37HFBD64/401 with I/O handler added. • Additional I/O Handler pin functions added in Table 3. • Typical range of watchdog oscillator frequency changed to 9.4 kHz to 2.3 MHz.See Table 13. • Section 11.8 “I/O Handler software library applications” added. • Updated Section 11.1 “Suggested USB interface solutions” for clarity. • Condition VDD = 0 V added to Parameter VI in Table 5 for clarity. LPC11U3X v.1.1 20130924 Product data sheet - LPC11U3X v.1 Modifications: • Removed the footnote “The peak current is limited to 25 times the corresponding maximum current.” in Table 4. • Table 3: Added “5 V tolerant pad” to RESET/PIO0_0 table note. • Table 7: Removed BOD interrupt level 0. • Programmable glitch filter is enabled by default. See Section 7.7.1. • Added Section 11.6 “ADC effective input impedance”. • Table 5 “Static characteristics” added Pin capacitance section. • Updated Section 11.1 “Suggested USB interface solutions”. • Table 4 “Limiting values”: – Updated VDD min and max. – Updated VI conditions. • Table 10 “EEPROM characteristics”: – Removed fclk and ter; the user does not have control over these parameters. – Changed the tprog from 1.1 ms to 2.9 ms; the EEPROM IAP always does an erase and program, thus the total program time is ter + tprog. • Changed title of Figure 29 from “USB interface on a self-powered device” to “USB interface with soft-connect”. • Section 10.7 “USB interface” added. Parameter tEOPR1 and tEOPR2 renamed to tEOPR. LPC11U3X v.1 20120420 Product data sheet - - LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 74 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 17. Legal information 17.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 75 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 76 of 77 continued >> NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 17 7.1 On-chip flash programming memory . . . . . . . 17 7.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19 7.7 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.8 General-Purpose Input/Output GPIO . . . . . . . 19 7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.9 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 20 7.9.1 Full-speed USB device controller . . . . . . . . . . 20 7.9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10 I/O Handler (LPC11U37HFBD64/401 only) . . . . . . . . . . . . 20 7.11 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12 SSP serial I/O controller . . . . . . . . . . . . . . . . . 21 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13 I2C-bus serial I/O controller . . . . . . . . . . . . . . 22 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.14 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.15 General purpose external event counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 23 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.16 System tick timer . . . . . . . . . . . . . . . . . . . . . . 23 7.17 Windowed WatchDog Timer (WWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.18 Clocking and power control . . . . . . . . . . . . . . 24 7.18.1 Integrated oscillators . . . . . . . . . . . . . . . . . . . 24 7.18.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 25 7.18.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 26 7.18.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 26 7.18.2 System PLL and USB PLL. . . . . . . . . . . . . . . 26 7.18.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.18.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 26 7.18.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.18.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 27 7.18.5.5 Deep power-down mode . . . . . . . . . . . . . . . . 28 7.18.6 System control . . . . . . . . . . . . . . . . . . . . . . . . 28 7.18.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.18.6.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 28 7.18.6.3 Code security (Code Read Protection - CRP) . . . . . . . . . . . 28 7.18.6.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.18.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.18.6.6 External interrupt inputs . . . . . . . . . . . . . . . . . 29 7.19 Emulation and debugging . . . . . . . . . . . . . . . 30 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 9 Static characteristics . . . . . . . . . . . . . . . . . . . 32 9.1 BOD static characteristics . . . . . . . . . . . . . . . 38 9.2 Power consumption . . . . . . . . . . . . . . . . . . . 38 9.3 Peripheral power consumption . . . . . . . . . . . 41 9.4 Electrical pin characteristics. . . . . . . . . . . . . . 43 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 46 10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 46 10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47 10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.7 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 53 11 Application information . . . . . . . . . . . . . . . . . 54 11.1 Suggested USB interface solutions . . . . . . . . 54 11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 57 11.4 Standard I/O pad configuration . . . . . . . . . . . 58 11.5 Reset pad configuration . . . . . . . . . . . . . . . . . 59 11.6 ADC effective input impedance . . . . . . . . . . . 59 11.7 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 60 11.8 I/O Handler software library applications . . . . 60 11.8.1 I/O Handler I2S. . . . . . . . . . . . . . . . . . . . . . . . 60 11.8.2 I/O Handler UART . . . . . . . . . . . . . . . . . . . . . 60 11.8.3 I/O Handler I2C. . . . . . . . . . . . . . . . . . . . . . . . 61 11.8.4 I/O Handler DMA . . . . . . . . . . . . . . . . . . . . . . 61 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 March 2014 Document identifier: LPC11U3X Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 62 13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 72 15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 73 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 74 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 74 17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 75 18 Contact information. . . . . . . . . . . . . . . . . . . . . 75 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1. General description The PCA9545A/45B/45C is a quad bidirectional translating switch controlled via the I2C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of the four interrupt inputs. An active LOW reset input allows the PCA9545A/45B/45C to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the channels to be deselected as does the internal power-on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which is passed by the PCA9545A/45B/45C. This allows the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. The PCA9545A, PCA9545B and PCA9545C are identical except for the fixed portion of the slave address. 2. Features and benefits  1-of-4 bidirectional translating switches  I2C-bus interface logic; compatible with SMBus standards  4 active LOW interrupt inputs  Active LOW interrupt output  Active LOW reset input  2 address pins allowing up to 4 devices on the I2C-bus  Alternate address versions A, B and C allow up to a total of 12 devices on the bus for larger systems or to resolve address conflicts  Channel selection via I2C-bus, in any combination  Power-up with all switch channels deselected  Low Ron switches  Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses  No glitch on power-up  Supports hot insertion  Low standby current  Operating power supply voltage range of 2.3 V to 5.5 V PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Rev. 9 — 5 May 2014 Product data sheet PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 2 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset  5 V tolerant Inputs  0 Hz to 400 kHz clock frequency  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Latch-up protection exceeds 100 mA per JESD78  Three packages offered: SO20, TSSOP20, and HVQFN20 3. Ordering information 3.1 Ordering options Table 1. Ordering information Type number Topside marking Package Name Description Version PCA9545ABS 9545A HVQFN20 plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5  5  0.85 mm SOT662-1 PCA9545AD PCA9545AD SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 PCA9545APW PA9545A TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 PCA9545BPW PA9545B PCA9545CPW PA9545C Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature range PCA9545ABS PCA9545ABS,118 HVQFN20 Reel 13” Q1/T1 *standard mark SMD 6000 Tamb = 40 C to +85 C PCA9545AD PCA9545AD,112 SO20 Standard marking * IC’s tube - DSC bulk pack 1520 Tamb = 40 C to +85 C PCA9545AD,118 SO20 Reel 13” Q1/T1 *standard mark SMD 2000 Tamb = 40 C to +85 C PCA9545APW PCA9545APW,112 TSSOP20 Standard marking * IC’s tube - DSC bulk pack 1875 Tamb = 40 C to +85 C PCA9545APW,118 TSSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9545BPW PCA9545BPW,118 TSSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9545CPW PCA9545CPW,118 TSSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 3 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 4. Block diagram Fig 1. Block diagram of PCA9545A/45B/45C SWITCH CONTROL LOGIC PCA9545A/PCA9545B/PCA9545C POWER-ON RESET 002aab168 SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 VSS VDD RESET I2C-BUS CONTROL INPUT FILTER SCL SDA A0 A1 INTERRUPT LOGIC INT0 to INT3 INT PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 4 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 5. Pinning information 5.1 Pinning Fig 2. Pin configuration for SO20 Fig 3. Pin configuration for TSSOP20 Fig 4. Pin configuration for HVQFN20 (transparent top view) PCA9545AD A0 VDD A1 SDA RESET SCL INT0 INT SD0 SC3 SC0 SD3 INT1 INT3 SD1 SC2 SC1 SD2 VSS INT2 002aab165 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 VDD SDA SCL INT SC3 SD3 INT3 SC2 SD2 INT2 A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 VSS PCA9545APW PCA9545BPW PCA9545CPW 002aab166 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 VDD SDA SCL INT SC3 SD3 INT3 SC2 A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 VSS 002aab167 PCA9545ABS Transparent top view 5 11 4 12 3 13 2 14 1 15 6 7 8 9 10 20 19 18 17 16 terminal 1 index area SD2 INT2 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 5 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 5.2 Pin description [1] HVQFN20 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad must be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias must be incorporated in the PCB in the thermal pad region. Table 3. Pin description Symbol Pin Description SO20, TSSOP20 HVQFN20 A0 1 19 address input 0 A1 2 20 address input 1 RESET 3 1 active LOW reset input INT0 4 2 active LOW interrupt input 0 SD0 5 3 serial data 0 SC0 6 4 serial clock 0 INT1 7 5 active LOW interrupt input 1 SD1 8 6 serial data 1 SC1 9 7 serial clock 1 VSS 10 8[1] supply ground INT2 11 9 active LOW interrupt input 2 SD2 12 10 serial data 2 SC2 13 11 serial clock 2 INT3 14 12 active LOW interrupt input 3 SD3 15 13 serial data 3 SC3 16 14 serial clock 3 INT 17 15 active LOW interrupt output SCL 18 16 serial clock line SDA 19 17 serial data line VDD 20 18 supply voltage PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 6 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 6. Functional description Refer to Figure 1 “Block diagram of PCA9545A/45B/45C”. 6.1 Device address Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9545A is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation. The PCA9545BPW and PCA9545CPW are alternate address versions if needed for larger systems or to resolve conflicts. The data sheet references the PCA9545A, but the PCA9545B and PCA9545C function identically except for the slave address. Fig 5. Slave address PCA9545A Fig 6. Slave address PCA9545B Fig 7. Slave address PCA9545C 002aab169 1 1 1 0 0 A1 A0 R/W fixed hardware selectable 002aab835 1 1 0 1 0 A1 A0 R/W fixed hardware selectable 002aab836 1 0 1 1 0 A1 A0 R/W fixed hardware selectable PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 7 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 6.2 Control register Following the successful acknowledgement of the slave address, the bus master sends a byte to the PCA9545A/45B/45C, which is stored in the control register. If multiple bytes are received by the PCA9545A/45B/45C, it saves the last byte received. This register can be written and read via the I2C-bus. 6.2.1 Control register definition One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9545A/45B/45C has been addressed. The 4 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines are in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Remark: Several channels can be enabled at the same time. Example: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and channel 2 are enabled. Care should be taken not to exceed the maximum bus capacity. Fig 8. Control register 002aab170 INT 3 INT 2 INT 1 INT 0 B3 B2 B1 B0 channel selection bits (read/write) 7 6 5 4 3 2 1 0 interrupt bits (read only) channel 0 channel 1 channel 2 channel 3 INT0 INT1 INT2 INT3 Table 4. Control register: write (channel selection); read (channel status) INT3 INT2 INT1 INT0 B3 B2 B1 B0 Command X X X X X X X 0 channel 0 disabled 1 channel 0 enabled X X X X X X 0 X channel 1 disabled 1 channel 1 enabled X X X X X 0 X X channel 2 disabled 1 channel 2 enabled X X X X 0 X X X channel 3 disabled 1 channel 3 enabled 0 0 0 0 0 0 0 0 no channel selected; power-up/reset default state PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 8 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 6.2.2 Interrupt handling The PCA9545A/45B/45C provides 4 interrupt inputs, one for each channel, and one open-drain interrupt output. When an interrupt is generated by any device, it is detected by the PCA9545A/45B/45C and the interrupt output is driven LOW. The channel does not need to be active for detection of the interrupt. A bit is also set in the control register. Bit 4 through bit 7 of the control register corresponds to channel 0 through channel 3 of the PCA9545A/45B/45C, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PCA9545A/45B/45C and read the contents of the control register to determine which channel contains the device generating the interrupt. The master can then reconfigure the PCA9545A/45B/45C to select this channel, and locate the device generating the interrupt and clear it. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. If the interrupt function is not required, the interrupt inputs may be used as general-purpose inputs. If unused, interrupt inputs must be connected to VDD through a pull-up resistor. Remark: Several interrupts can be active at the same time. Example: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and channel 3, and there is interrupt on channel 1 and channel 2. 6.3 RESET input The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9545A/45B/45C resets its registers and I2C-bus state machine and deselects all channels. The RESET input must be connected to VDD through a pull-up resistor. Table 5. Control register: Read — interrupt INT3 INT2 INT1 INT0 B3 B2 B1 B0 Command X X X 0 X X X X no interrupt on channel 0 1 interrupt on channel 0 X X 0 X X X X X no interrupt on channel 1 1 interrupt on channel 1 X 0 X X X X X X no interrupt on channel 2 1 interrupt on channel 2 0 X X X X X X X no interrupt on channel 3 1 interrupt on channel 3 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 9 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 6.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9545A/45B/45C in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9545A/45B/45C registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the device. 6.5 Voltage translation The pass gate transistors of the PCA9545A/45B/45C are constructed such that the VDD voltage can be used to limit the maximum voltage that is passed from one I2C-bus to another. Figure 9 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section 11 “Static characteristics” of this data sheet). In order for the PCA9545A/45B/45C to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to clamp the downstream bus voltages effectively. Looking at Figure 9, we see that Vo(sw)(max) is at 2.7 V when the PCA9545A/45B/45C supply voltage is 3.5 V or lower, so the PCA9545A/45B/45C supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 16). More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches. (1) maximum (2) typical (3) minimum Fig 9. Pass gate voltage versus supply voltage VDD (V) 2.0 3.0 4.0 4.5 5.5 002aaa964 3.0 2.0 4.0 5.0 Vo(sw) (V) 1.0 2.5 3.5 5.0 (1) (2) (3) PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 10 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 10). 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 11). Fig 10. Bit transfer 􀁐􀁅􀁄􀀙􀀓􀀚 􀁇􀁄􀁗􀁄􀀃􀁏􀁌􀁑􀁈􀀃 􀁖􀁗􀁄􀁅􀁏􀁈􀀞􀀃 􀁇􀁄􀁗􀁄􀀃􀁙􀁄􀁏􀁌􀁇 􀁆􀁋􀁄􀁑􀁊􀁈􀀃 􀁒􀁉􀀃􀁇􀁄􀁗􀁄􀀃 􀁄􀁏􀁏􀁒􀁚􀁈􀁇 􀀶􀀧􀀤 􀀶􀀦􀀯 Fig 11. Definition of START and STOP conditions 􀁐􀁅􀁄􀀙􀀓􀀛􀀃 􀀶􀀧􀀤 􀀶􀀦􀀯 􀀳 􀀶􀀷􀀲􀀳􀀃􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 􀀶 􀀶􀀷􀀤􀀵􀀷􀀃􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 11 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 7.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 12). 7.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Fig 12. System configuration 􀀓􀀓􀀕􀁄􀁄􀁄􀀜􀀙􀀙 􀀰􀀤􀀶􀀷􀀨􀀵􀀃 􀀷􀀵􀀤􀀱􀀶􀀰􀀬􀀷􀀷􀀨􀀵􀀒􀀃 􀀵􀀨􀀦􀀨􀀬􀀹􀀨􀀵 􀀶􀀯􀀤􀀹􀀨􀀃 􀀵􀀨􀀦􀀨􀀬􀀹􀀨􀀵 􀀶􀀯􀀤􀀹􀀨􀀃 􀀷􀀵􀀤􀀱􀀶􀀰􀀬􀀷􀀷􀀨􀀵􀀒􀀃 􀀵􀀨􀀦􀀨􀀬􀀹􀀨􀀵 􀀰􀀤􀀶􀀷􀀨􀀵􀀃 􀀷􀀵􀀤􀀱􀀶􀀰􀀬􀀷􀀷􀀨􀀵 􀀰􀀤􀀶􀀷􀀨􀀵􀀃 􀀷􀀵􀀤􀀱􀀶􀀰􀀬􀀷􀀷􀀨􀀵􀀒􀀃 􀀵􀀨􀀦􀀨􀀬􀀹􀀨􀀵 􀀶􀀧􀀤 􀀶􀀦􀀯 􀀬􀀕􀀦􀀐􀀥􀀸􀀶􀀃 􀀰􀀸􀀯􀀷􀀬􀀳􀀯􀀨􀀻􀀨􀀵 􀀶􀀯􀀤􀀹􀀨 Fig 13. Acknowledgement on the I2C-bus 􀀓􀀓􀀕􀁄􀁄􀁄􀀜􀀛􀀚 􀀶 􀀶􀀷􀀤􀀵􀀷􀀃 􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 􀀔 􀀕 􀀛 􀀜 􀁆􀁏􀁒􀁆􀁎􀀃􀁓􀁘􀁏􀁖􀁈􀀃􀁉􀁒􀁕􀀃 􀁄􀁆􀁎􀁑􀁒􀁚􀁏􀁈􀁇􀁊􀁈􀁐􀁈􀁑􀁗 􀁑􀁒􀁗􀀃􀁄􀁆􀁎􀁑􀁒􀁚􀁏􀁈􀁇􀁊􀁈􀀃 􀁄􀁆􀁎􀁑􀁒􀁚􀁏􀁈􀁇􀁊􀁈 􀁇􀁄􀁗􀁄􀀃􀁒􀁘􀁗􀁓􀁘􀁗􀀃 􀁅􀁜􀀃􀁗􀁕􀁄􀁑􀁖􀁐􀁌􀁗􀁗􀁈􀁕 􀁇􀁄􀁗􀁄􀀃􀁒􀁘􀁗􀁓􀁘􀁗􀀃 􀁅􀁜􀀃􀁕􀁈􀁆􀁈􀁌􀁙􀁈􀁕 􀀶􀀦􀀯􀀃􀁉􀁕􀁒􀁐􀀃􀁐􀁄􀁖􀁗􀁈􀁕 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 12 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 7.5 Bus transactions Data is transmitted to the PCA9545A/45B/45C control register using the Write mode as shown in Figure 14. Data is read from PCA9545A/45B/45C using the Read mode as shown in Figure 15. Fig 14. Write control register Fig 15. Read control register 002aab172 S 1 1 1 0 0 A1 A0 0 A X X X X B3 B2 B1 B0 A P slave address START condition R/W acknowledge from slave acknowledge from slave control register SDA STOP condition 002aab173 S 1 1 1 0 0 A1 A0 1 A INT3 INT2 INT1 INT0 B3 B2 B1 B0 NA P slave address START condition R/W acknowledge from slave no acknowledge from master control register SDA STOP condition last byte PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 13 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 8. Application design-in information (1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pull-up resistor is not required. The interrupt inputs should not be left floating. Fig 16. Typical application PCA9545A SD0 SC0 A1 A0 VSS SDA SCL RESET VDD = 2.7 V to 5.5 V VDD = 3.3 V I2C-bus/SMBus master 002aab171 SDA SCL channel 0 V = 2.7 V to 5.5 V INT INT0 see note (1) SD1 SC1 channel 1 V = 2.7 V to 5.5 V INT1 see note (1) SD2 SC2 channel 2 V = 2.7 V to 5.5 V INT2 see note (1) SD3 SC3 channel 3 V = 2.7 V to 5.5 V INT3 see note (1) PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 14 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 9. Limiting values [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C. 10. Thermal characteristics Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V). Symbol Parameter Conditions Min Max Unit VDD supply voltage 0.5 +7.0 V VI input voltage 0.5 +7.0 V II input current - 20 mA IO output current - 25 mA IDD supply current - 100 mA ISS ground supply current - 100 mA Ptot total power dissipation - 400 mW Tj(max) maximum junction temperature [1] - 125 C Tstg storage temperature 60 +150 C Tamb ambient temperature operating 40 +85 C Table 7. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient HVQFN20 package 32 C/W SO20 package 90 C/W TSSOP20 package 146 C/W PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 15 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 11. Static characteristics [1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. Table 8. Static characteristics at VDD = 2.3 V to 3.6 V VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 9 on page 16 for VDD = 4.5 V to 5.5 V[1]. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 2.3 - 3.6 V IDD supply current Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 10 30 A Istb standby current Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS - 0.1 1 A VPOR power-on reset voltage no load; VI = VDD or VSS [2]- 1.6 2.1 V Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current VOL = 0.4 V 3 7 - mA VOL = 0.6 V 6 10 - mA IL leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 10 13 pF Select inputs A0, A1, INT0 to INT3, RESET VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V ILI input leakage current pin at VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 1.6 3 pF Pass gate Ron ON-state resistance VDD = 3.6 V; VO = 0.4 V; IO = 15 mA 5 11 30  VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA 7 16 55  Vo(sw) switch output voltage Vi(sw) = VDD = 3.3 V; Io(sw) = 100 A - 1.9 - V Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = 100 A 1.6 - 2.8 V Vi(sw) = VDD = 2.5 V; Io(sw) = 100 A - 1.5 - V Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = 100 A 1.1 - 2.0 V IL leakage current VI = VDD or VSS 1 - +1 A Cio input/output capacitance VI = VSS - 3 5 pF INT output IOL LOW-level output current VOL = 0.4 V 3 - - mA IOH HIGH-level output current - - +10 A PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 16 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset [1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. Table 9. Static characteristics at VDD = 4.5 V to 5.5 V VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 8 on page 15 for VDD = 2.3 V to 3.6 V[1]. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 4.5 - 5.5 V IDD supply current Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 25 100 A Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS - 0.3 1 A VPOR power-on reset voltage no load; VI = VDD or VSS [2]- 1.7 2.1 V Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current VOL = 0.4 V 3 - - mA VOL = 0.6 V 6 - - mA IL leakage current VI = VSS 1 - +1 A Ci input capacitance VI = VSS - 10 13 pF Select inputs A0, A1, INT0 to INT3, RESET VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V ILI input leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 2 5 pF Pass gate Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA 4 9 24  Vo(sw) switch output voltage Vi(sw) = VDD = 5.0 V; Io(sw) = 100 A - 3.6 - V Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = 100 A 2.6 - 4.5 V IL leakage current VI = VDD or VSS 1 - +1 A Cio input/output capacitance VI = VSS - 3 5 pF INT output IOL LOW-level output current VOL = 0.4 V 3 - - mA IOH HIGH-level output current - - +10 A PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 17 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 12. Dynamic characteristics [1] Pass gate propagation delay is calculated from the 20  typical Ron and the 15 pF load capacitance. [2] After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] Measurements taken with 1 k pull-up resistor and 50 pF load. Table 10. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Unit Min Max Min Max tPD propagation delay from SDA to SDx, or SCL to SCx - 0.3[1] - 0.3[1] ns fSCL SCL clock frequency 0 100 0 400 kHz tBUF bus free time between a STOP and START condition 4.7 - 1.3 - s tHD;STA hold time (repeated) START condition [2] 4.0 - 0.6 - s tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - s tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 s tSU;DAT data set-up time 250 - 100 - ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 ns tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns Cb capacitive load for each bus line - 400 - 400 pF tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time HIGH-to-LOW [5] - 1 - 1 s LOW-to-HIGH [5] - 0.6 - 0.6 s tVD;ACK data valid acknowledge time - 1 - 1 s INT tv(INTnN-INTN) valid time from INTn to INT signal - 4 - 4 s td(INTnN-INTN) delay time from INTn to INT inactive - 2 - 2 s tw(rej)L LOW-level rejection time INTn inputs 1 - 1 - s tw(rej)H HIGH-level rejection time INTn inputs 0.5 - 0.5 - s RESET tw(rst)L LOW-level reset time 4 - 4 - ns trst reset time SDA clear 500 - 500 - ns tREC;STA recovery time to START condition 0 - 0 - ns PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 18 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 17. Definition of timing on the I2C-bus 􀁗􀀥􀀸􀀩 􀁗􀀶􀀳 􀁗􀀫􀀧􀀞􀀶􀀷􀀤 􀀳 􀀶 􀀳 􀁗􀀯􀀲􀀺 􀁗􀁕 􀁗􀀫􀀧􀀞􀀧􀀤􀀷 􀁗􀁉 􀁗􀀫􀀬􀀪􀀫 􀁗􀀶􀀸􀀞􀀧􀀤􀀷 􀁗􀀶􀀸􀀞􀀶􀀷􀀤 􀀶􀁕 􀁗􀀫􀀧􀀞􀀶􀀷􀀤 􀁗􀀶􀀸􀀞􀀶􀀷􀀲 􀀶􀀧􀀤 􀀶􀀦􀀯 􀀓􀀓􀀕􀁄􀁄􀁄􀀜􀀛􀀙 􀀓􀀑􀀚􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀖􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀚􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀖􀀃􀃮􀀃􀀹􀀧􀀧 Fig 18. Definition of RESET timing SDA SCL 002aac549 50 % 30 % 50 % 50 % tREC;STA tw(rst)L RESET START trst ACK or read cycle Rise and fall times refer to VIL and VIH. Fig 19. I2C-bus timing diagram 􀀓􀀓􀀕􀁄􀁄􀁅􀀔􀀚􀀘 􀁓􀁕􀁒􀁗􀁒􀁆􀁒􀁏 􀀶􀀷􀀤􀀵􀀷 􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 􀀋􀀶􀀌 􀁅􀁌􀁗􀀃􀀚 􀀰􀀶􀀥 􀀋􀀤􀀚􀀌 􀁅􀁌􀁗􀀃􀀙 􀀋􀀤􀀙􀀌 􀁅􀁌􀁗􀀃􀀓 􀀋􀀵􀀒􀀺􀀌 􀁄􀁆􀁎􀁑􀁒􀁚􀁏􀁈􀁇􀁊􀁈 􀀋􀀤􀀌 􀀶􀀷􀀲􀀳 􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 􀀋􀀳􀀌 􀀶􀀦􀀯 􀀶􀀧􀀤 􀁗􀀫􀀧􀀞􀀶􀀷􀀤 􀁗􀀶􀀸􀀞􀀧􀀤􀀷 􀁗􀀫􀀧􀀞􀀧􀀤􀀷 􀁗􀀥􀀸􀀩 􀁗􀁉 􀁗􀀶􀀸􀀞􀀶􀀷􀀤 􀁗􀀯􀀲􀀺 􀁗􀀫􀀬􀀪􀀫 􀁗􀀹􀀧􀀞􀀤􀀦􀀮 􀁗􀀶􀀸􀀞􀀶􀀷􀀲 􀀔􀀃􀀒􀀃􀁉􀀶􀀦􀀯 􀁗􀁕 􀁗􀀹􀀧􀀞􀀧􀀤􀀷 􀀓􀀑􀀖􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀚􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀖􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀚􀀃􀃮􀀃􀀹􀀧􀀧 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 19 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 13. Test information Fig 20. Expanded view of read input port register SCL 002aab176 2 1 0 A P 70 % 30 % SDA INPUT 50 % INT tv(INTnN−INTN) td(INTnN−INTN) Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 21. Test circuitry for switching times PULSE GENERATOR VO CL 50 pF RL 500 Ω 002aab177 RT VI VDD VDD D.U.T. PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 20 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 14. Package outline Fig 22. Package outline SOT163-1 (SO20) 􀀸􀀱􀀬􀀷􀀃 􀀤􀀃 􀁐􀁄􀁛􀀑􀀃 􀀤􀀃􀀔􀀃 􀀤􀀃􀀕􀀃 􀀤􀀃􀀖􀀃 􀁅􀀃􀁓􀀃 􀁆􀀃 􀀧􀀃􀀋􀀔􀀌􀀃 􀀨􀀃􀀋􀀔􀀌􀀃 􀁈􀀃 􀀫􀀃􀀨􀀃 􀀯􀀃 􀀯􀀃􀁓􀀃 􀀴􀀃 􀁙􀀃 􀁚􀀃 􀁜􀀃 􀀽􀀃􀀋􀀔􀀌􀀃 􀈙􀀃 􀀲􀀸􀀷􀀯􀀬􀀱􀀨􀀃 􀀃􀀵􀀨􀀩􀀨􀀵􀀨􀀱􀀦􀀨􀀶􀀃 􀀹􀀨􀀵􀀶􀀬􀀲􀀱􀀃 􀀨􀀸􀀵􀀲􀀳􀀨􀀤􀀱􀀃 􀀳􀀵􀀲􀀭􀀨􀀦􀀷􀀬􀀲􀀱􀀃 􀀬􀀶􀀶􀀸􀀨􀀃􀀧􀀤􀀷􀀨􀀃 􀀃􀀬􀀨􀀦􀀃 􀀃􀀭􀀨􀀧􀀨􀀦􀀃 􀀃􀀭􀀨􀀬􀀷􀀤􀀃 􀁐􀁐􀀃 􀁌􀁑􀁆􀁋􀁈􀁖􀀃 􀀕􀀑􀀙􀀘􀀃 􀀓􀀑􀀖􀀃 􀀓􀀑􀀔􀀃 􀀕􀀑􀀗􀀘􀀃 􀀕􀀑􀀕􀀘􀀃 􀀓􀀑􀀗􀀜􀀃 􀀓􀀑􀀖􀀙􀀃 􀀓􀀑􀀖􀀕􀀃 􀀓􀀑􀀕􀀖􀀃 􀀔􀀖􀀑􀀓􀀃 􀀔􀀕􀀑􀀙􀀃 􀀚􀀑􀀙􀀃 􀀚􀀑􀀗􀀃 􀀔􀀑􀀕􀀚􀀃 􀀔􀀓􀀑􀀙􀀘􀀃 􀀔􀀓􀀑􀀓􀀓􀀃 􀀔􀀑􀀔􀀃 􀀔􀀑􀀓􀀃 􀀓􀀑􀀜􀀃 􀀓􀀑􀀗􀀃 􀀛􀀃 􀀓􀀃 􀁒􀀃 􀁒􀀃 􀀓􀀑􀀕􀀘􀀃 􀀓􀀑􀀔􀀃 􀀧􀀬􀀰􀀨􀀱􀀶􀀬􀀲􀀱􀀶􀀃􀀋􀁌􀁑􀁆􀁋􀀃􀁇􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁄􀁕􀁈􀀃􀁇􀁈􀁕􀁌􀁙􀁈􀁇􀀃􀁉􀁕􀁒􀁐􀀃􀁗􀁋􀁈􀀃􀁒􀁕􀁌􀁊􀁌􀁑􀁄􀁏􀀃􀁐􀁐􀀃􀁇􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀌􀀃 􀀱􀁒􀁗􀁈􀀃 􀀔􀀑􀀃􀀳􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁒􀁕􀀃􀁐􀁈􀁗􀁄􀁏􀀃􀁓􀁕􀁒􀁗􀁕􀁘􀁖􀁌􀁒􀁑􀁖􀀃􀁒􀁉􀀃􀀓􀀑􀀔􀀘􀀃􀁐􀁐􀀃􀀋􀀓􀀑􀀓􀀓􀀙􀀃􀁌􀁑􀁆􀁋􀀌􀀃􀁐􀁄􀁛􀁌􀁐􀁘􀁐􀀃􀁓􀁈􀁕􀀃􀁖􀁌􀁇􀁈􀀃􀁄􀁕􀁈􀀃􀁑􀁒􀁗􀀃􀁌􀁑􀁆􀁏􀁘􀁇􀁈􀁇􀀑􀀃􀀃􀀃 􀀔􀀑􀀔􀀃 􀀓􀀑􀀗􀀃 􀀃􀀶􀀲􀀷􀀔􀀙􀀖􀀐􀀔􀀃 􀀔􀀓􀀃 􀀕􀀓􀀃 􀁚􀀃 􀀰􀀃 􀁅􀀃􀁓􀀃 􀁇􀁈􀁗􀁄􀁌􀁏􀀃􀀻􀀃 􀀽􀀃 􀁈􀀃 􀀔􀀔􀀃 􀀔􀀃 􀀧􀀃 􀁜􀀃 􀀓􀀑􀀕􀀘􀀃 􀀃􀀓􀀚􀀘􀀨􀀓􀀗􀀃 􀀃􀀰􀀶􀀐􀀓􀀔􀀖􀀃 􀁓􀁌􀁑􀀃􀀔􀀃􀁌􀁑􀁇􀁈􀁛􀀃 􀀓􀀑􀀔􀀃 􀀓􀀑􀀓􀀔􀀕􀀃 􀀓􀀑􀀓􀀓􀀗􀀃 􀀓􀀑􀀓􀀜􀀙􀀃 􀀓􀀑􀀓􀀛􀀜􀀃 􀀓􀀑􀀓􀀔􀀜􀀃 􀀓􀀑􀀓􀀔􀀗􀀃 􀀓􀀑􀀓􀀔􀀖􀀃 􀀓􀀑􀀓􀀓􀀜􀀃 􀀓􀀑􀀘􀀔􀀃 􀀓􀀑􀀗􀀜􀀃 􀀓􀀑􀀖􀀓􀀃 􀀓􀀑􀀕􀀜􀀃 􀀓􀀑􀀓􀀘􀀃 􀀔􀀑􀀗􀀃 􀀓􀀑􀀗􀀔􀀜􀀃 􀀓􀀑􀀓􀀘􀀘􀀃 􀀓􀀑􀀖􀀜􀀗􀀃 􀀓􀀑􀀓􀀗􀀖􀀃 􀀓􀀑􀀓􀀖􀀜􀀃 􀀓􀀑􀀓􀀖􀀘􀀃 􀀓􀀑􀀓􀀔􀀃 􀀓􀀑􀀓􀀔􀀙􀀃 􀀓􀀑􀀕􀀘􀀃 􀀓􀀑􀀓􀀗􀀖􀀃 􀀓􀀑􀀓􀀔􀀃 􀀓􀀑􀀓􀀓􀀗􀀃 􀀓􀀑􀀓􀀔􀀃 􀀓􀀑􀀓􀀔􀀙􀀃 􀀓􀀃 􀀘􀀃 􀀔􀀓􀀃􀁐􀁐􀀃 􀁖􀁆􀁄􀁏􀁈􀀃 􀀻􀀃 􀈙􀀃 􀀤􀀃 􀀤􀀃􀀔􀀃 􀀤􀀃􀀕􀀃 􀀫􀀃􀀨􀀃 􀀯􀀃􀁓􀀃 􀀴􀀃 􀀨􀀃 􀁆􀀃 􀀯􀀃 􀁙􀀃 􀀰􀀃 􀀤􀀃 􀀋􀀤􀀃􀀖􀀃􀀃􀀌􀀃 􀀤􀀃 􀀶􀀲􀀕􀀓􀀝􀀃􀁓􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁖􀁐􀁄􀁏􀁏􀀃􀁒􀁘􀁗􀁏􀁌􀁑􀁈􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀞􀀃􀀕􀀓􀀃􀁏􀁈􀁄􀁇􀁖􀀞􀀃􀁅􀁒􀁇􀁜􀀃􀁚􀁌􀁇􀁗􀁋􀀃􀀚􀀑􀀘􀀃􀁐􀁐􀀃 􀀶􀀲􀀷􀀔􀀙􀀖􀀐􀀔􀀃 􀀜􀀜􀀐􀀔􀀕􀀐􀀕􀀚􀀃 􀀓􀀖􀀐􀀓􀀕􀀐􀀔􀀜􀀃 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 21 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 23. Package outline SOT360-1 (TSSOP20) 􀀸􀀱􀀬􀀷􀀃 􀀤􀀃􀀔􀀃 􀀤􀀃􀀕􀀃 􀀤􀀃􀀖􀀃 􀁅􀀃􀁓􀀃 􀁆􀀃 􀀧􀀃􀀋􀀔􀀌􀀃 􀀨􀀃􀀋􀀕􀀌􀀃 􀁈􀀃 􀀫􀀃􀀨􀀃 􀀯􀀃 􀀯􀀃􀁓􀀃 􀀴􀀃 􀁙􀀃 􀁚􀀃 􀁜􀀃 􀀽􀀃􀀋􀀔􀀌􀀃 􀈙􀀃 􀀲􀀸􀀷􀀯􀀬􀀱􀀨􀀃 􀀃􀀵􀀨􀀩􀀨􀀵􀀨􀀱􀀦􀀨􀀶􀀃 􀀹􀀨􀀵􀀶􀀬􀀲􀀱􀀃 􀀨􀀸􀀵􀀲􀀳􀀨􀀤􀀱􀀃 􀀳􀀵􀀲􀀭􀀨􀀦􀀷􀀬􀀲􀀱􀀃 􀀬􀀶􀀶􀀸􀀨􀀃􀀧􀀤􀀷􀀨􀀃 􀀃􀀬􀀨􀀦􀀃 􀀃􀀭􀀨􀀧􀀨􀀦􀀃 􀀃􀀭􀀨􀀬􀀷􀀤􀀃 􀁐􀁐􀀃 􀀓􀀑􀀔􀀘􀀃 􀀓􀀑􀀓􀀘􀀃 􀀓􀀑􀀜􀀘􀀃 􀀓􀀑􀀛􀀓􀀃 􀀓􀀑􀀖􀀓􀀃 􀀓􀀑􀀔􀀜􀀃 􀀓􀀑􀀕􀀃 􀀓􀀑􀀔􀀃 􀀙􀀑􀀙􀀃 􀀙􀀑􀀗􀀃 􀀗􀀑􀀘􀀃 􀀗􀀑􀀖􀀃 􀀓􀀑􀀙􀀘􀀃 􀀙􀀑􀀙􀀃 􀀙􀀑􀀕􀀃 􀀓􀀑􀀗􀀃 􀀓􀀑􀀖􀀃 􀀓􀀑􀀘􀀃 􀀓􀀑􀀕􀀃 􀀛􀀃 􀀓􀀃 􀁒􀀃 􀀔􀀃 􀀓􀀑􀀕􀀃 􀀓􀀑􀀔􀀖􀀃 􀀓􀀑􀀔􀀃 􀁒􀀃 􀀧􀀬􀀰􀀨􀀱􀀶􀀬􀀲􀀱􀀶􀀃􀀋􀁐􀁐􀀃􀁄􀁕􀁈􀀃􀁗􀁋􀁈􀀃􀁒􀁕􀁌􀁊􀁌􀁑􀁄􀁏􀀃􀁇􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀌􀀃 􀀱􀁒􀁗􀁈􀁖􀀃 􀀔􀀑􀀃􀀳􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁒􀁕􀀃􀁐􀁈􀁗􀁄􀁏􀀃􀁓􀁕􀁒􀁗􀁕􀁘􀁖􀁌􀁒􀁑􀁖􀀃􀁒􀁉􀀃􀀓􀀑􀀔􀀘􀀃􀁐􀁐􀀃􀁐􀁄􀁛􀁌􀁐􀁘􀁐􀀃􀁓􀁈􀁕􀀃􀁖􀁌􀁇􀁈􀀃􀁄􀁕􀁈􀀃􀁑􀁒􀁗􀀃􀁌􀁑􀁆􀁏􀁘􀁇􀁈􀁇􀀑􀀃 􀀕􀀑􀀃􀀳􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁌􀁑􀁗􀁈􀁕􀁏􀁈􀁄􀁇􀀃􀁓􀁕􀁒􀁗􀁕􀁘􀁖􀁌􀁒􀁑􀁖􀀃􀁒􀁉􀀃􀀓􀀑􀀕􀀘􀀃􀁐􀁐􀀃􀁐􀁄􀁛􀁌􀁐􀁘􀁐􀀃􀁓􀁈􀁕􀀃􀁖􀁌􀁇􀁈􀀃􀁄􀁕􀁈􀀃􀁑􀁒􀁗􀀃􀁌􀁑􀁆􀁏􀁘􀁇􀁈􀁇􀀑􀀃 􀀓􀀑􀀚􀀘􀀃 􀀓􀀑􀀘􀀓􀀃 􀀃􀀶􀀲􀀷􀀖􀀙􀀓􀀐􀀔􀀃 􀀃􀀰􀀲􀀐􀀔􀀘􀀖􀀃 􀀜􀀜􀀐􀀔􀀕􀀐􀀕􀀚􀀃 􀀓􀀖􀀐􀀓􀀕􀀐􀀔􀀜􀀃 􀁚􀀃 􀀰􀀃 􀁅􀀃􀁓􀀃 􀀧􀀃 􀀽􀀃 􀁈􀀃 􀀓􀀑􀀕􀀘􀀃 􀀔􀀃 􀀔􀀓􀀃 􀀕􀀓􀀃 􀀔􀀔􀀃 􀁓􀁌􀁑􀀃􀀔􀀃􀁌􀁑􀁇􀁈􀁛􀀃 􀈙􀀃 􀀤􀀃 􀀤􀀃 􀀔􀀃 􀀤􀀃􀀕􀀃 􀀯􀀃􀁓􀀃 􀀴􀀃 􀁇􀁈􀁗􀁄􀁌􀁏􀀃􀀻􀀃 􀀯􀀃 􀀋􀀤􀀃􀀖􀀃􀀃􀀌􀀃 􀀫􀀃􀀨􀀃 􀀨􀀃 􀁆􀀃 􀁙􀀃 􀀰􀀃 􀀤􀀃 􀀻􀀃 􀀤􀀃 􀁜􀀃 􀀓􀀃 􀀕􀀑􀀘􀀃 􀀘􀀃􀁐􀁐􀀃 􀁖􀁆􀁄􀁏􀁈􀀃 􀀷􀀶􀀶􀀲􀀳􀀕􀀓􀀝􀀃􀁓􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁗􀁋􀁌􀁑􀀃􀁖􀁋􀁕􀁌􀁑􀁎􀀃􀁖􀁐􀁄􀁏􀁏􀀃􀁒􀁘􀁗􀁏􀁌􀁑􀁈􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀞􀀃􀀕􀀓􀀃􀁏􀁈􀁄􀁇􀁖􀀞􀀃􀁅􀁒􀁇􀁜􀀃􀁚􀁌􀁇􀁗􀁋􀀃􀀗􀀑􀀗􀀃􀁐􀁐􀀃 􀀶􀀲􀀷􀀖􀀙􀀓􀀐􀀔􀀃 􀀤􀀃 􀁐􀁄􀁛􀀑􀀃 􀀔􀀑􀀔􀀃 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 22 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 24. Package outline SOT662-1 (HVQFN20) 􀀔􀀃 􀀓􀀑􀀙􀀘􀀃 􀀸􀀱􀀬􀀷􀀃 􀀤􀀔􀀃 􀁅􀀃 􀀨􀁋􀀃 􀁈􀀃 􀁜􀀃 􀀓􀀑􀀕􀀃 􀁆􀀃 􀀲􀀸􀀷􀀯􀀬􀀱􀀨􀀃 􀀃􀀵􀀨􀀩􀀨􀀵􀀨􀀱􀀦􀀨􀀶􀀃 􀀹􀀨􀀵􀀶􀀬􀀲􀀱􀀃 􀀨􀀸􀀵􀀲􀀳􀀨􀀤􀀱􀀃 􀀳􀀵􀀲􀀭􀀨􀀦􀀷􀀬􀀲􀀱􀀃 􀀬􀀶􀀶􀀸􀀨􀀃􀀧􀀤􀀷􀀨􀀃 􀀃􀀬􀀨􀀦􀀃 􀀃􀀭􀀨􀀧􀀨􀀦􀀃 􀀃􀀭􀀨􀀬􀀷􀀤􀀃 􀁐􀁐􀀃 􀀘􀀑􀀔􀀃 􀀗􀀑􀀜􀀃 􀀧􀁋􀀃 􀀖􀀑􀀕􀀘􀀃 􀀕􀀑􀀜􀀘􀀃 􀁜􀀔􀀃 􀀘􀀑􀀔􀀃 􀀗􀀑􀀜􀀃 􀀖􀀑􀀕􀀘􀀃 􀀕􀀑􀀜􀀘􀀃 􀁈􀀔􀀃 􀀕􀀑􀀙􀀃 􀁈􀀕􀀃 􀀓􀀑􀀖􀀛􀀃 􀀕􀀑􀀙􀀃 􀀓􀀑􀀕􀀖􀀃 􀀓􀀑􀀓􀀘􀀃 􀀓􀀑􀀓􀀓􀀃 􀀓􀀑􀀓􀀘􀀃 􀀓􀀑􀀔􀀃 􀀧􀀬􀀰􀀨􀀱􀀶􀀬􀀲􀀱􀀶􀀃􀀋􀁐􀁐􀀃􀁄􀁕􀁈􀀃􀁗􀁋􀁈􀀃􀁒􀁕􀁌􀁊􀁌􀁑􀁄􀁏􀀃􀁇􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀌􀀃 􀀃􀀶􀀲􀀷􀀙􀀙􀀕􀀐􀀔􀀃 􀀐􀀃􀀐􀀃􀀐􀀃 􀀰􀀲􀀐􀀕􀀕􀀓􀀃 􀀐􀀃􀀐􀀃􀀐􀀃 􀀓􀀑􀀚􀀘􀀃 􀀓􀀑􀀘􀀓􀀃 􀀯􀀃 􀀓􀀑􀀔􀀃 􀁙􀀃 􀀓􀀑􀀓􀀘􀀃 􀁚􀀃 􀀓􀀃 􀀕􀀑􀀘􀀃 􀀘􀀃􀁐􀁐􀀃 􀁖􀁆􀁄􀁏􀁈􀀃 􀀶􀀲􀀷􀀙􀀙􀀕􀀐􀀔􀀃 􀀫􀀹􀀴􀀩􀀱􀀕􀀓􀀝􀀃􀁓􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁗􀁋􀁈􀁕􀁐􀁄􀁏􀀃􀁈􀁑􀁋􀁄􀁑􀁆􀁈􀁇􀀃􀁙􀁈􀁕􀁜􀀃􀁗􀁋􀁌􀁑􀀃􀁔􀁘􀁄􀁇􀀃􀁉􀁏􀁄􀁗􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀞􀀃􀁑􀁒􀀃􀁏􀁈􀁄􀁇􀁖􀀞􀀃 􀀕􀀓􀀃􀁗􀁈􀁕􀁐􀁌􀁑􀁄􀁏􀁖􀀞􀀃􀁅􀁒􀁇􀁜􀀃􀀘􀀃􀁛􀀃􀀘􀀃􀁛􀀃􀀓􀀑􀀛􀀘􀀃􀁐􀁐􀀃 􀀤􀀋􀀔􀀌􀀃 􀁐􀁄􀁛􀀑􀀃 􀀤􀀃 􀀤􀀔􀀃 􀁆􀀃 􀁇􀁈􀁗􀁄􀁌􀁏􀀃􀀻􀀃 􀁈􀀃 􀁜􀀔􀀃 􀀦􀀃 􀁜􀀃 􀀯􀀃 􀀨􀁋􀀃 􀀧􀁋􀀃 􀁈􀀃 􀁈􀀔􀀃 􀁅􀀃 􀀙􀀃 􀀔􀀓􀀃 􀀕􀀓􀀃 􀀔􀀙􀀃 􀀔􀀘􀀃 􀀘􀀃 􀀔􀀔􀀃 􀀔􀀃 􀀻􀀃 􀀧􀀃 􀀨􀀃 􀀦􀀃 􀀥􀀃 􀀤􀀃 􀁈􀀕􀀃 􀁗􀁈􀁕􀁐􀁌􀁑􀁄􀁏􀀃􀀔􀀃 􀁌􀁑􀁇􀁈􀁛􀀃􀁄􀁕􀁈􀁄􀀃 􀁗􀁈􀁕􀁐􀁌􀁑􀁄􀁏􀀃􀀔􀀃 􀁌􀁑􀁇􀁈􀁛􀀃􀁄􀁕􀁈􀁄􀀃 􀀓􀀔􀀐􀀓􀀛􀀐􀀓􀀛􀀃 􀀓􀀕􀀐􀀔􀀓􀀐􀀕􀀕􀀃 􀀦􀀃 􀀤􀀃 􀀦􀀃 􀁙􀀃 􀀰􀀃 􀀥􀀃 􀁚􀀃 􀀰􀀃 􀀧􀀋􀀔􀀌􀀃 􀀨􀀋􀀔􀀌􀀃 􀀱􀁒􀁗􀁈􀀃 􀀔􀀑􀀃􀀳􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁒􀁕􀀃􀁐􀁈􀁗􀁄􀁏􀀃􀁓􀁕􀁒􀁗􀁕􀁘􀁖􀁌􀁒􀁑􀁖􀀃􀁒􀁉􀀃􀀓􀀑􀀓􀀚􀀘􀀃􀁐􀁐􀀃􀁐􀁄􀁛􀁌􀁐􀁘􀁐􀀃􀁓􀁈􀁕􀀃􀁖􀁌􀁇􀁈􀀃􀁄􀁕􀁈􀀃􀁑􀁒􀁗􀀃􀁌􀁑􀁆􀁏􀁘􀁇􀁈􀁇􀀑􀀃􀀃 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 23 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 24 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25. Table 11. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 12. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 25 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = MSL limit, damage level peak temperature PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 26 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 16. Soldering: PCB footprints Fig 26. PCB footprint for SOT163-1 (SO20); reflow soldering Fig 27. PCB footprint for SOT163-1 (SO20); wave soldering 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀁖􀁒􀁗􀀔􀀙􀀖􀀐􀀔􀁂􀁉􀁕 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇􀁖 􀁓􀁏􀁄􀁆􀁈􀁐􀁈􀁑􀁗􀀃􀁄􀁆􀁆􀁘􀁕􀁄􀁆􀁜􀀃􀂓􀀃􀀓􀀑􀀕􀀘 􀀧􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁌􀁑􀀃􀁐􀁐 􀀔􀀑􀀘􀀓 􀀓􀀑􀀙􀀓􀀃􀀋􀀕􀀓􀃮􀀌 􀀔􀀑􀀕􀀚􀀃􀀋􀀔􀀛􀃮􀀌 􀀛􀀑􀀓􀀓 􀀔􀀔􀀑􀀓􀀓 􀀔􀀖􀀑􀀗􀀓 􀀔􀀔􀀑􀀗􀀓 􀁖􀁒􀁗􀀔􀀙􀀖􀀐􀀔􀁂􀁉􀁚 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁕􀁈􀁖􀁌􀁖􀁗 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇􀁖 􀀧􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁌􀁑􀀃􀁐􀁐 􀁅􀁒􀁄􀁕􀁇􀀃􀁇􀁌􀁕􀁈􀁆􀁗􀁌􀁒􀁑 􀁓􀁏􀁄􀁆􀁈􀁐􀁈􀁑􀁗􀀃􀁄􀁆􀁆􀁘􀁕􀁕􀁄􀁆􀁜􀀃􀂓􀀃􀀓􀀑􀀕􀀘 􀀛􀀑􀀓􀀓 􀀔􀀖􀀑􀀗􀀓 􀀔􀀑􀀘􀀓 􀀓􀀑􀀖􀀃􀀋􀀕􀃮􀀌 􀀓􀀑􀀙􀀓􀀃􀀋􀀔􀀛􀃮􀀌 􀀔􀀑􀀕􀀓􀀃􀀋􀀕􀃮􀀌 􀀔􀀑􀀕􀀚􀀃􀀋􀀔􀀛􀃮􀀌 􀀔􀀔􀀑􀀓􀀓 􀀔􀀔􀀑􀀗􀀓 􀁈􀁑􀁏􀁄􀁕􀁊􀁈􀁇􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 27 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 28. PCB footprint for SOT360-1 (TSSOP20); reflow soldering 􀀧􀀬􀀰􀀨􀀱􀀶􀀬􀀲􀀱􀀶􀀃􀁌􀁑􀀃􀁐􀁐 􀀳􀀔 􀀤􀁜 􀀥􀁜 􀀦 􀀧􀀔 􀀧􀀕 􀀪􀁛 􀀪􀁜 􀀫􀁜 􀁖􀁒􀁗􀀖􀀙􀀓􀀐􀀔􀁂􀁉􀁕 􀀫􀁛 􀀶􀀲􀀷􀀖􀀙􀀓􀀐􀀔 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀀩􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁌􀁑􀁉􀁒􀁕􀁐􀁄􀁗􀁌􀁒􀁑􀀃􀁉􀁒􀁕􀀃􀁕􀁈􀁉􀁏􀁒􀁚􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀁌􀁑􀁊􀀃􀁒􀁉􀀃􀀷􀀶􀀶􀀲􀀳􀀕􀀓􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈 􀀪􀁜 􀀥􀁜 􀀤􀁜 􀀦 􀀫􀁜 􀀫􀁛 􀀪􀁛 􀀳􀀔 􀀪􀁈􀁑􀁈􀁕􀁌􀁆􀀃􀁉􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁓􀁄􀁗􀁗􀁈􀁕􀁑􀀃 􀀵􀁈􀁉􀁈􀁕􀀃􀁗􀁒􀀃􀁗􀁋􀁈􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀃􀁒􀁘􀁗􀁏􀁌􀁑􀁈􀀃􀁇􀁕􀁄􀁚􀁌􀁑􀁊􀀃􀁉􀁒􀁕􀀃􀁄􀁆􀁗􀁘􀁄􀁏􀀃􀁏􀁄􀁜􀁒􀁘􀁗 􀀳􀀕 􀀋􀀓􀀑􀀔􀀕􀀘􀀌 􀀋􀀓􀀑􀀔􀀕􀀘􀀌 􀀧􀀕􀀃􀀋􀀗􀁛􀀌 􀀧􀀔 􀀳􀀕 􀀓􀀑􀀙􀀘􀀓 􀀓􀀑􀀚􀀘􀀓 􀀚􀀑􀀕􀀓􀀓 􀀗􀀑􀀘􀀓􀀓 􀀔􀀑􀀖􀀘􀀓 􀀓􀀑􀀗􀀓􀀓 􀀓􀀑􀀙􀀓􀀓 􀀙􀀑􀀜􀀓􀀓 􀀘􀀑􀀖􀀓􀀓 􀀚􀀑􀀖􀀓􀀓 􀀚􀀑􀀗􀀘􀀓 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 28 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 29. PCB footprint for SOT662-1 (HVQFN20); reflow soldering 􀀩􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁌􀁑􀁉􀁒􀁕􀁐􀁄􀁗􀁌􀁒􀁑􀀃􀁉􀁒􀁕􀀃􀁕􀁈􀁉􀁏􀁒􀁚􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀁌􀁑􀁊􀀃􀁒􀁉􀀃􀀫􀀹􀀴􀀩􀀱􀀕􀀓􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈 􀀶􀀲􀀷􀀙􀀙􀀕􀀐􀀔 􀀧􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁌􀁑􀀃􀁐􀁐 􀀤􀁛 􀀤􀁜 􀀥􀁛 􀀥􀁜 􀀧 􀀶􀀯􀁛 􀀶􀀯􀁜 􀀶􀀳􀁛􀀃􀁗􀁒􀁗 􀀶􀀳􀁜􀀃􀁗􀁒􀁗 􀀶􀀳􀁛 􀀶􀀳􀁜 􀀪􀁛 􀀪􀁜 􀀫􀁛 􀀫􀁜 􀀙􀀑􀀓􀀓􀀓 􀀙􀀑􀀓􀀓􀀓 􀀖􀀑􀀛􀀓􀀓 􀀖􀀑􀀛􀀓􀀓 􀀳 􀀓􀀑􀀙􀀘􀀓 􀀓􀀑􀀖􀀘􀀓 􀀦 􀀔􀀑􀀔􀀓􀀓 􀀖􀀑􀀓􀀓􀀓 􀀖􀀑􀀓􀀓􀀓 􀀔􀀑􀀛􀀓􀀓 􀀔􀀑􀀛􀀓􀀓 􀀓􀀑􀀙􀀘􀀓 􀀓􀀑􀀙􀀘􀀓 􀀘􀀑􀀖􀀓􀀓 􀀘􀀑􀀖􀀓􀀓 􀀙􀀑􀀕􀀘􀀓 􀀙􀀑􀀕􀀘􀀓 􀁑􀀶􀀳􀁛 􀁑􀀶􀀳􀁜 􀀕 􀀕 􀁖􀁒􀁗􀀙􀀙􀀕􀀐􀀔􀁂􀁉􀁕 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀀤􀁛 􀀥􀁛 􀀶􀀯􀁛 􀀪􀁛 􀀫􀁜 􀀪􀁜 􀀫􀁛 􀀶􀀯􀁜 􀀥􀁜 􀀤􀁜 􀀧 􀀳 􀀓􀀑􀀓􀀕􀀘 􀀓􀀑􀀓􀀕􀀘 􀀋􀀓􀀑􀀔􀀓􀀘􀀌 􀀶􀀳􀁛􀀃􀁗􀁒􀁗 􀀶􀀳􀁜􀀃􀁗􀁒􀁗 􀁑􀀶􀀳􀁛 􀁑􀀶􀀳􀁜 􀀶􀀳􀁛 􀀶􀀳􀁜 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇􀀃􀁓􀁏􀁘􀁖􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁓􀁄􀁖􀁗􀁈 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁓􀁄􀁖􀁗􀁈􀀃􀁇􀁈􀁓􀁒􀁖􀁌􀁗 􀀦 􀀪􀁈􀁑􀁈􀁕􀁌􀁆􀀃􀁉􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁓􀁄􀁗􀁗􀁈􀁕􀁑􀀃 􀀵􀁈􀁉􀁈􀁕􀀃􀁗􀁒􀀃􀁗􀁋􀁈􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀃􀁒􀁘􀁗􀁏􀁌􀁑􀁈􀀃􀁇􀁕􀁄􀁚􀁌􀁑􀁊􀀃􀁉􀁒􀁕􀀃􀁄􀁆􀁗􀁘􀁄􀁏􀀃􀁏􀁄􀁜􀁒􀁘􀁗 􀀬􀁖􀁖􀁘􀁈􀀃􀁇􀁄􀁗􀁈 􀀓􀀚􀀐􀀓􀀘􀀐􀀓􀀚􀀃 􀀓􀀜􀀐􀀓􀀙􀀐􀀔􀀘 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 29 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 17. Abbreviations 18. Revision history Table 13. Abbreviations Acronym Description CDM Charged-Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model IC Integrated Circuit I2C-bus Inter-Integrated Circuit bus LSB Least Significant Bit MSB Most Significant Bit PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9545A_45B_45C v.9 20140505 Product data sheet - PCA9545A_45B_45C v.8 Modifications: • Section 6.4 “Power-on reset”, first paragraph, third sentence corrected from “Thereafter, VDD must be lowered below 0.2 V to reset the device.” to “Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the device.” (this is a correction to documentation only; no change to device) • Table 8 “Static characteristics at VDD = 2.3 V to 3.6 V”: Table note [2] corrected by inserting phrase “for at least 5 s” (this is a correction to documentation only; no change to device) • Table 9 “Static characteristics at VDD = 4.5 V to 5.5 V”: Table note [2] corrected by inserting phrase “for at least 5 s” (this is a correction to documentation only; no change to device) PCA9545A_45B_45C v.8 20130514 Product data sheet - PCA9545A_45B_45C v.7 PCA9545A_45B_45C v.7 20090619 Product data sheet - PCA9545A_45B_45C v.6 PCA9545A_45B_45C v.6 20070319 Product data sheet - PCA9545A_45B_45C v.5 PCA9545A_45B_45C v.5 20061017 Product data sheet - PCA9545A v.4 PCA9545A v.4 20060925 Product data sheet - PCA9545A v.3 PCA9545A v.3 20050303 Product data sheet - PCA9545A v.2 PCA9545A v.2 20040929 Objective data sheet - PCA9545A v.1 PCA9545A v.1 20040728 Objective data sheet - - PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 30 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 19. Legal information 19.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 31 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 May 2014 Document identifier: PCA9545A_45B_45C Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2.1 Control register definition . . . . . . . . . . . . . . . . . 7 6.2.2 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.5 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 9 7 Characteristics of the I2C-bus . . . . . . . . . . . . 10 7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2 START and STOP conditions . . . . . . . . . . . . . 10 7.3 System configuration . . . . . . . . . . . . . . . . . . . 11 7.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 12 8 Application design-in information . . . . . . . . . 13 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 10 Thermal characteristics . . . . . . . . . . . . . . . . . 14 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 15 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 17 13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 19 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 15 Soldering of SMD packages . . . . . . . . . . . . . . 23 15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 23 15.2 Wave and reflow soldering . . . . . . . . . . . . . . . 23 15.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 15.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24 16 Soldering: PCB footprints. . . . . . . . . . . . . . . . 26 17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29 18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 20 Contact information. . . . . . . . . . . . . . . . . . . . . 31 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using a 90 nanometer process to implement an ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go. The LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz. The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The ARM926EJ-S also has a hardware based set of DSP instruction extensions, which includes single cycle MAC operations, and hardware based native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB instruction cache and a 32 kB data cache. For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced technology development to optimize intrinsic power and uses software controlled architectural enhancements to optimize application based power management. The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external bus interface that supports SDR and DDR SDRAM as well as static devices. In addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs, two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single output PWMs, a motor control PWM, six general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC) with a touch screen sense option. 2. Features and benefits  ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz.  Vector Floating Point (VFP) coprocessor.  32 kB instruction cache and 32 kB data cache.  Up to 256 kB of Internal SRAM (IRAM).  Selectable boot-up from various external devices: NAND flash, SPI memory, USB, UART, or static memory.  Multi-layer AHB system that provides a separate bus for each AHB master, including both an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD, and a final one for the Ethernet MAC. There are no arbitration delays in the system unless two masters attempt to access the same slave at the same time. LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 2 — 20 October 2011 Product data sheet LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 2 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers  External memory controller for DDR and SDR SDRAM as well as for static devices.  Two NAND flash controllers: One for single-level NAND flash devices and the other for multi-level NAND flash devices.  Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting 74 interrupt sources.  Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be used with the SD card port, the high-speed UARTs, I2S-bus interfaces, and SPI interfaces, as well as memory-to-memory transfers.  Serial interfaces:  10/100 Ethernet MAC with dedicated DMA Controller.  USB interface supporting either device, host (OHCI compliant), or On-The-Go (OTG) with an integral DMA controller and dedicated PLL to generate the required 48 MHz USB clock.  Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One of the standard UARTs supports IrDA.  Three additional high-speed UARTs intended for on-board communications that support baud rates up to 921 600 when using a 13 MHz main oscillator. All high-speed UARTs provide 64 byte FIFOs.  Two SPI controllers.  Two SSP controllers.  Two I2C-bus interfaces with standard open-drain pins. The I2C-bus interfaces support single master, slave, and multi-master I2C-bus configurations.  Two I2S-bus interfaces, each with separate input and output channels. Each channel can be operated independently on three pins, or both input and output channels can be used with only four pins and a shared clock.  Additional peripherals:  LCD controller supporting both STN and TFT panels, with dedicated DMA controller. Programmable display resolution up to 1024  768.  Secure Digital (SD) memory card interface, which conforms to the SD Memory Card Specification Version 1.01.  General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24 GP output pins, and 51 GP I/O pins.  10-bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from three pins. Optionally, the ADC can operate as a touch screen controller.  Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator. NXP implemented the RTC in an independent on-chip power domain so it can remain active while the rest of the chip is not powered. The RTC also includes a 32-byte scratch pad memory.  32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer includes one external capture input pin and a capture connection to the RTC clock. Interrupts may be generated using three match registers.  Six enhanced timer/counters which are architecturally identical except for the peripheral base address. Two capture inputs and two match outputs are pinned out to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all four match outputs, timer 4 has one match output, and timer 5 has no inputs or outputs.  32-bit millisecond timer driven from the RTC clock. This timer can generate interrupts using two match registers. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 3 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers  WatchDog timer clocked by the peripheral clock.  Two single-output PWM blocks.  Motor control PWM.  Keyboard scanner function allows automatic scanning of an up to 8  8 key matrix.  Up to 18 external interrupts.  Standard ARM test/debug interface for compatibility with existing tools.  Emulation Trace Buffer (ETB) with 2048  24 bit RAM allows trace via JTAG.  Stop mode saves power while allowing many peripheral functions to restart CPU activity.  On-chip crystal oscillator.  An on-chip PLL allows CPU operation up to the maximum CPU rate without the requirement for a high frequency crystal. Another PLL allows operation from the 32 kHz RTC clock rather than the external crystal.  Boundary scan for simplified board testing.  User-accessible unique serial ID number for each chip.  TFBGA296 package with a 15 mm  15 mm  0.7 mm body. 3. Applications  Consumer  Medical  Industrial  Network control LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 4 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 4. Ordering information [1] F = 40 C to +85 C temperature range. Note that Revision “A” parts with and without the /01 suffix are identical. For example, LPC3220FET296 Revision “A” is identical to LPC3220FET296/01 Revision “A”. [2] Available starting with Revision “A”. 4.1 Ordering options Table 1. Ordering information Type number[1] Package Name Description Version LPC3220FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 LPC3230FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 LPC3240FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 LPC3250FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 Table 2. Part options Type number SRAM (kB) 10/100 Ethernet LCD controller Temperature range (C) Package LPC3220FET296/01 128 0 0 40 to +85 TFBGA296 LPC3230FET296/01 256 0 1 40 to +85 TFBGA296 LPC3240FET296/01 256 1 0 40 to +85 TFBGA296 LPC3250FET296/01 256 1 1 40 to +85 TFBGA296 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 5 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 5. Block diagram Fig 1. Block diagram of LPC3220/30/40/50 ARM 9EJS D-CACHE 32 kB I-CACHE 32 kB DATA INSTRUCTION ethernet PHY interface USB transceiver interface LCD panel interface EXTERNAL MEMORY CONTROLLER ROM 16 kB SRAM 256 kB DMA USB SDRAM ETB STANDARD UART × 4 I2C × 2 TIMERS × 6 WATCHDOG TIMER DEBUG SYSTEM CONTROL HS UART × 3 KEY SCANNER 10-BIT ADC/TS UART CONTROL RTC PWM × 2 GPIO M0 M1 AHB TO APB BRIDGE AHB TO APB BRIDGE AHB TO APB BRIDGE master layer 0 1 2 3 4 5 6 slave port 0 1 7 6 5 3 2 = Master/Slave connection supported by the multilayer AHB matrix 32-bit AHB matrix APB slaves FAB slaves AHB slaves APB slaves port 3 port 4 port 0 32-bit wide external memory VFP9 ETB ETM 9 ETHERNET LCD MOTOR CONTROL PWM 002aae397 MMU D-SIDE CONTROLLER I-SIDE CONTROLLER DMA CONTROLLER ETHERNET 10/100 MAC USB OTG CONTROLLER LCD CONTROLLER MLC NAND SLC NAND SD CARD SPI × 2 I2S × 2 SSP × 2 INTERRUPT CONTROL register interfaces LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 6 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 6. Pinning information 6.1 Pinning Fig 2. Pin configuration for SOT1048-1 (TFBGA296) 002aae398 Transparent top view V U T R P N L J M K H G F E D B C A 2 4 6 8 10 12 13 14 15 17 16 18 1 3 5 7 9 11 ball A1 index area Table 3. Pin allocation table (TFBGA296) Pin Symbol Pin Symbol Pin Symbol Row A A3 I2C2_SCL A4 I2S1TX_CLK/MAT3[0] A5 I2C1_SCL A6 MS_BS/MAT2[1] A7 MS_DIO1/MAT0[1] A8 MS_DIO0/MAT0[0] A9 SPI2_DATIO/MOSI1/LCDVD[20][1] A10 SPI2_DATIN/MISO1/ LCDVD[21][1]/GPI_27 A11 GPIO_1 A12 GPIO_0 A13 GPO_21/U4_TX/LCDVD[3][1] A14 GPO_15/MCOA1/LCDFP[1] A15 GPO_7/LCDVD[2][1] A16 GPO_6/LCDVD[18][1] Row B B2 GPO_20 B3 GPO_5 B4 I2S1TX_WS/CAP3[0] B5 P0[0]/I2S1RX_CLK B6 I2C1_SDA B7 MS_SCLK/MAT2[0] B8 MS_DIO2/MAT0[2] B9 SPI1_DATIO/MOSI0/MCI2 B10 SPI2_CLK/SCK1/LCDVD[23][1] B11 GPIO_4/SSEL1/LCDVD[22][1] B12 GPO_12/MCOA2/LCDLE[1] B13 GPO_13/MCOB1/LCDDCLK[1] B14 GPO_2/MAT1[0]/LCDVD[0][1] B15 GPI_19/U4_RX B16 GPI_8/KEY_COL6/ SPI2_BUSY/ENET_RX_DV[2] B17 n.c. Row C C1 FLASH_RD C2 GPO_19 C3 GPO_0/TST_CLK1 C4 USB_ATX_INT C5 USB_SE0_VM/U5_TX C6 TST_CLK2 C7 GPI_6/HSTIM_CAP/ ENET_RXD2[2] C8 MS_DIO3/MAT0[3] C9 SPI1_CLK/SCK0 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 7 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers C10 SPI1_DATIN/MISO0/GPI_25/ MCI1 C11 GPIO_3/KEY_ROW7/ ENET_MDIO[2] C12 GPO_9/LCDVD[9][1] C13 GPO_8/LCDVD[8][1] C14 GPI_2/CAP2[0]/ ENET_RXD3[2] C15 GPI_1/SERVICE C16 GPI_0/I2S1RX_SDA C17 KEY_ROW4/ENET_TXD0[2] C18 KEY_ROW5/ENET_TXD1[2] Row D D1 FLASH_RDY D2 FLASH_ALE D3 GPO_14 D4 GPO_1 D5 USB_DAT_VP/U5_RX D6 USB_OE_TP D7 P0[1]/I2S1RX_WS D8 GPO_4 D9 GPIO_2/KEY_ROW6/ENET_MDC[2] D10 GPO_16/MCOB0/LCDENAB[1]/ LCDM[1] D11 GPO_18/MCOA0/LCDLP[1] D12 GPO_3/LCDVD[1][1] D13 GPI_7/CAP4[0]/MCABORT D14 PWM_OUT1/LCDVD[16][1] D15 PWM_OUT2/INTSTAT/LCDVD[19][1] D16 KEY_ROW3/ENET_TX_EN[2] D17 KEY_COL2/ENET_RX_ER[2] D18 KEY_COL3/ENET_CRS[2] Row E E1 FLASH_IO[3] E2 FLASH_IO[7] E3 FLASH_CE E4 I2C2_SDA E5 USB_I2C_SCL E6 USB_I2C_SDA E7 I2S1TX_SDA/MAT3[1] E8 GPO_11 E9 GPIO_5/SSEL0/MCI0 E10 GPO_22/U7_HRTS/ LCDVD[14][1] E11 GPO_10/MCOB2/LCDPWR[1] E12 GPI_9/KEY_COL7/ENET_COL[2] E13 GPI_4/SPI1_BUSY E14 KEY_ROW1/ENET_TXD2[2] E15 KEY_ROW0/ENET_TX_ER[2] E16 KEY_COL1/ENET_RX_CLK[2]/ ENET_REF_CLK[2] E17 U7_RX/CAP0[0]/ LCDVD[10][1]/GPI_23 E18 U7_TX/MAT1[1]/LCDVD[11][1] Row F F1 FLASH_IO[2] F2 FLASH_WR F3 FLASH_CLE F4 GPI_3 F5 VSS_IOC F6 VSS_IOB F7 VDD_IOC F8 VDD_IOB F9 VDD_IOD F10 VSS_IOD F11 VSS_IOD F12 VSS_IOD F13 VDD_IOD F14 KEY_ROW2/ENET_TXD3[2] F15 KEY_COL0/ENET_TX_CLK[2] F16 KEY_COL5/ENET_RXD1[2] F17 U6_IRRX/GPI_21 F18 U5_RX/GPI_20 Row G G1 EMC_DYCS1 G2 FLASH_IO[5] G3 FLASH_IO[6] G4 RESOUT G5 VSS_IOC G6 VDD_IOC G7 VDD_CORE G8 VSS_CORE G9 VDD_CORE G10 VSS_CORE G11 VDD_CORE G12 VSS_CORE G13 U7_HCTS/CAP0[1]/ LCDCLKIN[1]/GPI_22 G14 DBGEN G15 KEY_COL4/ENET_RXD0[2] G16 U6_IRTX G17 SYSCLKEN/LCDVD[15][1] G18 JTAG_TMS Row H H1 EMC_OE H2 FLASH_IO[0] H3 FLASH_IO[1] H4 FLASH_IO[4] H5 VSS_IOC H6 VDD_IOC H7 VSS_CORE H12 VSS_IOD H13 VDD_IOA H14 JTAG_TCK H15 U5_TX Table 3. Pin allocation table (TFBGA296) Pin Symbol Pin Symbol Pin Symbol LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 8 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers H16 HIGHCORE/LCDVD[17][1] H17 JTAG_NTRST H18 JTAG_RTCK Row J J1 EMC_A[20]/P1[20] J2 EMC_A[21]/P1[21] J3 EMC_A[22]/P1[22] J4 EMC_A[23]/P1[23] J5 VDD_IOC J6 VDD_EMC J7 VDD_CORE J12 VDD_CORE J13 VDD_IOA J14 U3_RX/GPI_18 J15 JTAG_TDO J16 JTAG_TDI J17 U3_TX J18 U2_HCTS/U3_CTS/GPI_16 Row K K1 EMC_A[19]/P1[19] K2 EMC_A[18]/P1[18] K3 EMC_A[16]/P1[16] K4 EMC_A[17]/P1[17] K5 VSS_EMC K6 VDD_EMC K7 VDD_EMC K12 VSS_CORE K13 VSS_IOA K14 VDD_RTC K15 U1_RX/CAP1[0]/GPI_15 K16 U1_TX K17 U2_TX/U3_DTR K18 U2_RX/U3_DSR/GPI_17 Row L L1 EMC_A[15]/P1[15] L2 EMC_CKE1 L3 EMC_A[0]/P1[0] L4 EMC_A[1]/P1[1] L5 VSS_EMC L6 VDD_EMC L7 VSS_CORE L12 VDD_COREFXD L13 VDD_RTCCORE L14 VSS_RTCCORE L15 P0[4]/I2S0RX_WS/LCDVD[6][1] L16 P0[5]/I2S0TX_SDA/LCDVD[7][1] L17 P0[6]/I2S0TX_CLK/ LCDVD[12][1] L18 P0[7]/I2S0TX_WS/LCDVD[13][1] Row M M1 EMC_A[2]/P1[2] M2 EMC_A[3]/P1[3] M3 EMC_A[4]/P1[4] M4 EMC_A[8]/P1[8] M5 VSS_EMC M6 VDD_EMC M7 VDD_CORE M8 VDD_EMC M9 VSS_CORE M10 VSS_CORE M11 VDD_CORE M12 VSS_CORE M13 VDD_COREFXD M14 RESET M15 ONSW M16 GPO_23/U2_HRTS/U3_RTS M17 P0[2]/I2S0RX_SDA/ LCDVD[4][1] M18 P0[3]/I2S0RX_CLK/LCDVD[5][1] Row N N1 EMC_A[5]/P1[5] N2 EMC_A[6]/P1[6] N3 EMC_A[7/P1[7] N4 EMC_A[12]/P1[12] N5 VSS_EMC N6 VSS_EMC N7 VDD_EMC N8 VDD_EMC N9 VDD_EMC N10 VDD_EMC N11 VDD_EMC N12 VDD_AD N13 VDD_AD N14 VDD_FUSE N15 VDD_RTCOSC N16 GPI_5/U3_DCD N17 GPI_28/U3_RI N18 GPO_17 Row P P1 EMC_A[9]/P1[9] P2 EMC_A[10]/P1[10] P3 EMC_A[11]/P1[11] P4 EMC_DQM[1] P5 EMC_DQM[3] P6 VSS_EMC Table 3. Pin allocation table (TFBGA296) Pin Symbol Pin Symbol Pin Symbol LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 9 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] LCD on LPC3230 and LPC3250 only. [2] Ethernet on LPC3240 and LPC3250 only. P7 VSS_EMC P8 VSS_EMC P9 VSS_EMC P10 VSS_EMC P11 VSS_EMC P12 EMC_BLS[3] P13 VSS_AD P14 VSS_OSC P15 VDD_PLLUSB P16 RTCX_IN P17 RTCX_OUT P18 VSS_RTCOSC Row R R1 EMC_A[13]/P1[13] R2 EMC_A[14]/P1[14] R3 EMC_DQM[0] R4 EMC_WR R5 EMC_CAS R6 EMC_DYCS0 R7 EMC_D[1] R8 EMC_D[7] R9 EMC_D[17]/EMC_DQS1 R10 EMC_D[24]/P2[5] R11 EMC_CS1 R12 EMC_BLS[2] R13 TS_XP R14 PLL397_LOOP R15 SYSX_OUT R16 VSS_PLLUSB R17 VDD_PLLHCLK R18 VSS_PLLHCLK Row T T1 EMC_DQM[2] T2 EMC_RAS T3 EMC_CLK T4 EMC_CLKIN T5 EMC_D[2] T6 EMC_D[6] T7 EMC_D[11] T8 EMC_D[14] T9 EMC_D[20]/P2[1] T10 EMC_D[23]/P2[4] T11 EMC_D[27]/P2[8] T12 EMC_CS2 T13 EMC_BLS[1] T14 ADIN1/TS_XM T15 VSS_PLL397 T16 VDD_PLL397 T17 SYSX_IN T18 VDD_OSC Row U U2 n.c. U3 EMC_CKE0 U4 EMC_D[0] U5 EMC_D[3] U6 EMC_D[9] U7 EMC_D[12] U8 EMC_D[15] U9 EMC_D[19]/P2[0] U10 EMC_D[22]/P2[3] U11 EMC_D[26]/P2[7] U12 EMC_D[30]/P2[11] U13 EMC_CS0 U14 EMC_BLS[0] U15 ADIN0/TS_YM U16 TS_YP U17 n.c. Row V V3 EMC_D[4] V4 EMC_D[5] V5 EMC_D[8] V6 EMC_D[10] V7 EMC_D[13] V8 EMC_D[16]/EMC_DQS0 V9 EMC_D[18]/EMC_CLK V10 EMC_D[21]/P2[2] V11 EMC_D[25]/P2[6] V12 EMC_D[28]/P2[9] V13 EMC_D[29]/P2[10] V14 EMC_D[31]/P2[12] V15 EMC_CS3 V16 ADIN2/TS_AUX_IN Table 3. Pin allocation table (TFBGA296) Pin Symbol Pin Symbol Pin Symbol LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 10 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 6.2 Pin description Table 4. Pin description Symbol Pin Power supply domain Type Description ADIN0/TS_YM U15 VDD_AD analog in ADC input 0/touch screen Y minus ADIN1/TS_XM T14 VDD_AD analog in ADC input 0/touch screen X minus ADIN2/TS_AUX_IN V16 VDD_AD analog in ADC input 2/touch screen AUX input DBGEN G14 VDD_IOD I: PD Device test input LOW = JTAG in-circuit debug available; normal operation. HIGH = I/O cell boundary scan test; for board assembly BSDL test. EMC_A[0]/P1[0] L3 VDD_EMC I/O EMC address bit 0 I/O Port 1 GPIO bit 0 EMC_A[1]/P1[1] L4 VDD_EMC I/O EMC address bit 1 I/O Port 1 GPIO bit 1 EMC_A[2]/P1[2] M1 VDD_EMC I/O EMC address bit 2 I/O Port 1 GPIO bit 2 EMC_A[3]/P1[3] M2 VDD_EMC I/O EMC address bit 3 I/O Port 1 GPIO bit 3 EMC_A[4]/P1[4] M3 VDD_EMC I/O EMC address bit 4 I/O Port 1 GPIO bit 4 EMC_A[5]/P1[5] N1 VDD_EMC I/O EMC address bit 5 I/O Port 1 GPIO bit 5 EMC_A[6]/P1[6] N2 VDD_EMC I/O EMC address bit 6 I/O Port 1 GPIO bit 6 EMC_A[7/P1[7] N3 VDD_EMC I/O EMC address bit 7 I/O Port 1 GPIO bit 7 EMC_A[8]/P1[8] M4 VDD_EMC I/O EMC address bit 8 I/O Port 1 GPIO bit 8 EMC_A[9]/P1[9] P1 VDD_EMC I/O EMC address bit 9 I/O Port 1 GPIO bit 9 EMC_A[10]/P1[10] P2 VDD_EMC I/O EMC address bit 10 I/O Port 1 GPIO bit 10 EMC_A[11]/P1[11] P3 VDD_EMC I/O EMC address bit 11 I/O Port 1 GPIO bit 11 EMC_A[12]/P1[12] N4 VDD_EMC I/O EMC address bit 12 I/O Port 1 GPIO bit 12 EMC_A[13]/P1[13] R1 VDD_EMC I/O EMC address bit 13 I/O Port 1 GPIO bit 13 EMC_A[14]/P1[14] R2 VDD_EMC I/O EMC address bit 14 I/O Port 1 GPIO bit 14 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 11 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers EMC_A[15]/P1[15] L1 VDD_EMC I/O EMC address bit 15 I/O Port 1 GPIO bit 15 EMC_A[16]/P1[16] K3 VDD_EMC I/O EMC address bit 16 I/O Port 1 GPIO bit 16 EMC_A[17]/P1[17] K4 VDD_EMC I/O EMC address bit 17 I/O Port 1 GPIO bit 17 EMC_A[18]/P1[18] K2 VDD_EMC I/O EMC address bit 18 I/O Port 1 GPIO bit 18 EMC_A[19]/P1[19] K1 VDD_EMC I/O EMC address bit 19 I/O Port 1 GPIO bit 19 EMC_A[20]/P1[20] J1 VDD_EMC I/O EMC address bit 20 I/O Port 1 GPIO bit 20 EMC_A[21]/P1[21] J2 VDD_EMC I/O EMC address bit 21 I/O Port 1 GPIO bit 21 EMC_A[22]/P1[22] J3 VDD_EMC I/O EMC address bit 22 I/O Port 1 GPIO bit 22 EMC_A[23]/P1[23] J4 VDD_EMC I/O EMC address bit 23 I/O Port 1 GPIO bit 23 EMC_BLS[0] U14 VDD_EMC O Static memory byte lane 0 select EMC_BLS[1] T13 VDD_EMC O Static memory byte lane 1 select EMC_BLS[2] R12 VDD_EMC O Static memory byte lane 2 select EMC_BLS[3] P12 VDD_EMC O Static memory byte lane 3 select EMC_CAS R5 VDD_EMC O SDRAM column address strobe out, active LOW EMC_CKE0 U3 VDD_EMC O Clock enable out for SDRAM bank 0 EMC_CKE1 L2 VDD_EMC O Clock enable out for SDRAM bank 1 EMC_CLK T3 VDD_EMC O SDRAM clock out EMC_CLKIN T4 VDD_EMC I SDRAM clock feedback EMC_CS0 U13 VDD_EMC O EMC static memory chip select 0 EMC_CS1 R11 VDD_EMC O EMC static memory chip select 1 EMC_CS2 T12 VDD_EMC O EMC static memory chip select 2 EMC_CS3 V15 VDD_EMC O EMC static memory chip select 3 EMC_D[0] U4 VDD_EMC I/O: BK EMC data bit 0 EMC_D[1] R7 VDD_EMC I/O: BK EMC data bit 1 EMC_D[2] T5 VDD_EMC I/O: BK EMC data bit 2 EMC_D[3] U5 VDD_EMC I/O: BK EMC data bit 3 EMC_D[4] V3 VDD_EMC I/O: BK EMC data bit 4 EMC_D[5] V4 VDD_EMC I/O: BK EMC data bit 5 EMC_D[6] T6 VDD_EMC I/O: BK EMC data bit 6 EMC_D[7] R8 VDD_EMC I/O: BK EMC data bit 7 EMC_D[8] V5 VDD_EMC I/O: BK EMC data bit 8 Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 12 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers EMC_D[9] U6 VDD_EMC I/O: BK EMC data bit 9 EMC_D[10] V6 VDD_EMC I/O: BK EMC data bit 10 EMC_D[11] T7 VDD_EMC I/O: BK EMC data bit 11 EMC_D[12] U7 VDD_EMC I/O: BK EMC data bit 12 EMC_D[13] V7 VDD_EMC I/O: BK EMC data bit 13 EMC_D[14] T8 VDD_EMC I/O: BK EMC data bit 14 EMC_D[15] U8 VDD_EMC I/O: BK EMC data bit 15 EMC_D[16]/ EMC_DQS0 V8 VDD_EMC I/O: BK EMC data bit 16 I/O: BK DDR data strobe 0 EMC_D[17]/ EMC_DQS1 R9 VDD_EMC I/O: BK EMC data bit 17 I/O: BK DDR data strobe 1 EMC_D[18]/ EMC_CLK V9 VDD_EMC I/O: P EMC data bit 18 I/O: P DDR inverted clock output EMC_D[19]/P2[0] U9 VDD_EMC I/O: P EMC data bit 19 I/O: P Port 2 GPIO bit 0 EMC_D[20]/P2[1] T9 VDD_EMC I/O: P EMC data bit 20 I/O: P Port 2 GPIO bit 1 EMC_D[21]/P2[2] V10 VDD_EMC I/O: P EMC data bit 21 I/O: P Port 2 GPIO bit 2 EMC_D[22]/P2[3] U10 VDD_EMC I/O: P EMC data bit 22 I/O: P Port 2 GPIO bit 3 EMC_D[23]/P2[4] T10 VDD_EMC I/O: P EMC data bit 23 I/O: P Port 2 GPIO bit 4 EMC_D[24]/P2[5] R10 VDD_EMC I/O: P EMC data bit 24 I/O: P Port 2 GPIO bit 5 EMC_D[25]/P2[6] V11 VDD_EMC I/O: P EMC data bit 25 I/O: P Port 2 GPIO bit 6 EMC_D[26]/P2[7] U11 VDD_EMC I/O: P EMC data bit 26 I/O: P Port 2 GPIO bit 7 EMC_D[27]/P2[8] T11 VDD_EMC I/O: P EMC data bit 27 I/O: P Port 2 GPIO bit 8 EMC_D[28]/P2[9] V12 VDD_EMC I/O: P EMC data bit 28 I/O: P Port 2 GPIO bit 9 EMC_D[29]/P2[10] V13 VDD_EMC I/O: P EMC data bit 29 I/O: P Port 2 GPIO bit 10 EMC_D[30]/P2[11] U12 VDD_EMC I/O: P EMC data bit 30 I/O: P Port 2 GPIO bit 11 EMC_D[31]/P2[12] V14 VDD_EMC I/O: P EMC data bit 31 I/O: P Port 2 GPIO bit 12 EMC_DQM[0] R3 VDD_EMC O SDRAM data mask 0 out Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 13 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers EMC_DQM[1] P4 VDD_EMC O SDRAM data mask 1 out EMC_DQM[2] T1 VDD_EMC O SDRAM data mask 2 out EMC_DQM[3] P5 VDD_EMC O SDRAM data mask 3 out EMC_DYCS0 R6 VDD_EMC O SDRAM active LOW chip select 0 EMC_DYCS1 G1 VDD_EMC O SDRAM active LOW chip select 1 EMC_OE H1 VDD_EMC O EMC static memory output enable EMC_RAS T2 VDD_EMC O SDRAM row address strobe, active LOW EMC_WR R4 VDD_EMC O EMC write strobe, active LOW FLASH_ALE D2 VDD_IOC O Flash address latch enable FLASH_CE E3 VDD_IOC O Flash chip enable FLASH_CLE F3 VDD_IOC O Flash command latch enable FLASH_IO[0] H2 VDD_IOC I/O: BK Flash data bus, bit 0 FLASH_IO[1] H3 VDD_IOC I/O: BK Flash data bus, bit 1 FLASH_IO[2] F1 VDD_IOC I/O: BK Flash data bus, bit 2 FLASH_IO[3] E1 VDD_IOC I/O: BK Flash data bus, bit 3 FLASH_IO[4] H4 VDD_IOC I/O: BK Flash data bus, bit 4 FLASH_IO[5] G2 VDD_IOC I/O: BK Flash data bus, bit 5 FLASH_IO[6] G3 VDD_IOC I/O: BK Flash data bus, bit 6 FLASH_IO[7] E2 VDD_IOC I/O: BK Flash data bus, bit 7 FLASH_RD C1 VDD_IOC O Flash read enable FLASH_RDY D1 VDD_IOC I Flash ready (from flash device) FLASH_WR F2 VDD_IOC O Flash write enable GPI_0/I2S1RX_SDA C16 VDD_IOD I General purpose input 0 I I2S1 Receive data GPI_1/SERVICE C15 VDD_IOD I General purpose input 1 I Boot select input GPI_2/CAP2[0]/ ENET_RXD3 C14 VDD_IOD I General purpose input 2 I Timer 2 capture input 0 I Ethernet receive data 3 (LPC3240 and LPC3250 only) GPI_3 F4 VDD_IOC I General purpose input 3 GPI_4/SPI1_BUSY E13 VDD_IOD I General purpose input 4 I SPI1 busy input GPI_5/U3_DCD N16 VDD_IOA I General purpose input 5 I UART 3 data carrier detect input GPI_6/ HSTIM_CAP/ ENET_RXD2 C7 VDD_IOB I: BK General purpose input 6 I: BK High-speed timer capture input I : BK Ethernet receive data 2 (LPC3240 and LPC3250 only) Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 14 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers GPI_7/CAP4[0]/ MCABORT D13 VDD_IOD I General purpose input 7 I Timer 4 capture input 0 I Motor control PWM LOW-active fast abort input GPI_8/KEY_COL6/ SPI2_BUSY/ ENET_RX_DV B16 VDD_IOD I General purpose input 8 I Keyscan column 6 input I SPI2 busy input I Ethernet receive data valid input (LPC3240 and LPC3250 only) GPI_9/KEY_COL7/ ENET_COL E12 VDD_IOD I General purpose input 9 I Keyscan column 7 input I Ethernet collision input (LPC3240 and LPC3250 only) GPI_19/U4_RX B15 VDD_IOD I General purpose input 19 I UART 4 receive GPI_28/U3_RI N17 VDD_IOA I General purpose input 28 I UART 3 ring indicator input GPIO_0 A12 VDD_IOD I/O General purpose input/output 0 GPIO_1 A11 VDD_IOD I/O General purpose input/output 1 GPIO_2/ KEY_ROW6/ ENET_MDC D9 VDD_IOD I/O General purpose input/output 2 O Keyscan row 6 output O Ethernet PHY interface clock (LPC3240 and LPC3250 only) GPIO_3/ KEY_ROW7/ ENET_MDIO C11 VDD_IOD I/O General purpose input/output 3 I/O Keyscan row 7 output I/O Ethernet PHY interface data (LPC3240 and LPC3250 only) GPIO_4/ SSEL1/ LCDVD[22] B11 VDD_IOD I/O General purpose input/output 4 I/O SSP1 Slave Select I/O LCD data bit 22 (LPC3230 and LPC3250 only) GPIO_5/ SSEL0/ MCI0 E9 VDD_IOD I/O General purpose input/output 5 I/O SSP0 Slave Select I/O Motor control channel 0 input GPO_0/ TST_CLK1 C3 VDD_IOC O General purpose output 0 O Test clock 1 out GPO_1 D4 VDD_IOC O General purpose output 1 GPO_2/ MAT1[0]/ LCDVD[0] B14 VDD_IOD O General purpose output 2 O Timer 1 match output 0 O LCD data bit 0 (LPC3230 and LPC3250 only) GPO_3/ LCDVD[1] D12 VDD_IOD O General purpose output 3 O LCD data bit 1 (LPC3230 and LPC3250 only) GPO_4 D8 VDD_IOB O General purpose output 4 Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 15 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers GPO_5 B3 VDD_IOC O General purpose output 5 GPO_6/ LCDVD[18] A16 VDD_IOD O General purpose output 6 O LCD data bit 18 (LPC3230 and LPC3250 only) GPO_7/ LCDVD[2] A15 VDD_IOD O General purpose output 7 O LCD data bit 2 (LPC3230 and LPC3250 only) GPO_8/ LCDVD[8] C13 VDD_IOD O General purpose output 8 O LCD data bit 8 (LPC3230 and LPC3250 only) GPO_9/ LCDVD[9] C12 VDD_IOD O General purpose output 9 O LCD data bit 9 (LPC3230 and LPC3250 only) GPO_10/ MCOB2/ LCDPWR E11 VDD_IOD O General purpose output 10 O Motor control PWM channel 2, output B O LCD panel power enable (LPC3230 and LPC3250 only) GPO_11 E8 VDD_IOB O General purpose output 11 GPO_12/ MCOA2/ LCDLE B12 VDD_IOD O General purpose output 12 O Motor control PWM channel 2, output A O LCD line end signal (LPC3230 and LPC3250 only) GPO_13/ MCOB1/ LCDDCLK B13 VDD_IOD O General purpose output 13 O Motor control PWM channel 1, output B O LCD clock output (LPC3230 and LPC3250 only) GPO_14 D3 VDD_IOC O General purpose output 14 GPO_15/ MCOA1/ LCDFP A14 VDD_IOD O General purpose output 15 O Motor control PWM channel 1, output A O LCD frame/sync pulse (LPC3230 and LPC3250 only) GPO_16/ MCOB0/ LCDENAB/LCDM D10 VDD_IOD O General purpose output 16 O Motor control PWM channel 0, output B O LCD STN AC bias/TFT data enable (LPC3230 and LPC3250 only) GPO_17 N18 VDD_IOA O General purpose output 17 GPO_18/ MCOA0/ LCDLP D11 VDD_IOD O General purpose output 18 O Motor control PWM channel 0, output A O LCD line sync/horizontal sync (LPC3230 and LPC3250 only) GPO_19 C2 VDD_IOC O General purpose output 19 GPO_20 B2 VDD_IOC O General purpose output 20 GPO_21/ U4_TX/ LCDVD[3] A13 VDD_IOD O General purpose output 21 O UART 4 transmit O LCD data bit 3 (LPC3230 and LPC3250 only) Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 16 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers GPO_22/ U7_HRTS/ LCDVD[14] E10 VDD_IOD O General purpose output 22 O HS UART 7 RTS out O LCD data bit 14 (LPC3230 and LPC3250 only) GPO_23/ U2_HRTS/ U3_RTS M16 VDD_IOA O General purpose output 23 O HS U ART 2 RTS out O UART 3 RTS out HIGHCORE/ LCDVD[17] H16 VDD_IOD O Core voltage control out O LCD data bit 17 (LPC3230 and LPC3250 only) I2C1_SCL A5 VDD_IOB I/O T I2C1 serial clock input/output I2C1_SDA B6 VDD_IOB I/O T I2C1 serial data input/output I2C2_SCL A3 VDD_IOC I/O T I2C2 serial clock input/output I2C2_SDA E4 VDD_IOC I/O T I2C2 serial data input/output I2S1TX_CLK/ MAT3[0] A4 VDD_IOB I/O I2S1 transmit clock O Timer 3 match output 0 I2S1TX_SDA/ MAT3[1] E7 VDD_IOB I/O I2S1 transmit data O Timer 3 match output 1 I2S1TX_WS/ CAP3[0] B4 VDD_IOB I/O I2S1 transmit word select I/O Timer 3 capture input 0 JTAG_NTRST H17 VDD_IOD I: PU JTAG1 reset input. Must be LOW during power-on reset. JTAG_RTCK H18 VDD_IOD O JTAG1 return clock out JTAG_TCK H14 VDD_IOD I JTAG1 clock input JTAG_TDI J16 VDD_IOD I: PU JTAG1 data input JTAG_TDO J15 VDD_IOD O JTAG1 data out JTAG_TMS G18 VDD_IOD I: PU TAG1 test mode select input KEY_COL0/ ENET_TX_CLK F15 VDD_IOD I Keyscan column 0 input I Ethernet transmit clock (LPC3240 and LPC3250 only) KEY_COL1/ ENET_RX_CLK/ ENET_REF_CLK E16 VDD_IOD I Keyscan column 1 input I Ethernet receive clock (MII mode, LPC3240 and LPC3250 only) I Ethernet reference clock (RMII mode, LPC3240 and LPC3250 only) KEY_COL2/ ENET_RX_ER D17 VDD_IOD I Keyscan column 2 input I Ethernet receive error input (LPC3240 and LPC3250 only) KEY_COL3/ ENET_CRS D18 VDD_IOD I Keyscan column 3 input I Ethernet carrier sense input (LPC3240 and LPC3250 only) KEY_COL4/ ENET_RXD0 G15 VDD_IOD I Keyscan column 4 input I Ethernet receive data 0 (LPC3240 and LPC3250 only) Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 17 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers KEY_COL5/ ENET_RXD1 F16 VDD_IOD I Keyscan column 5 input I Ethernet receive data 1 (LPC3240 and LPC3250 only) KEY_ROW0/ ENET_TX_ER E15 VDD_IOD I/O T Keyscan row 0 out I/O T Ethernet transmit error (LPC3240 and LPC3250 only) KEY_ROW1/ ENET_TXD2 E14 VDD_IOD I/O T Keyscan row 1 out I/O T Ethernet transmit data 2 (LPC3240 and LPC3250 only) KEY_ROW2/ ENET_TXD3 F14 VDD_IOD I/O T Keyscan row 2 out I/O T Ethernet transmit data 3 (LPC3240 and LPC3250 only) KEY_ROW3/ ENET_TX_EN D16 VDD_IOD I/O T Keyscan row 3 out I/O T Ethernet transmit enable (LPC3240 and LPC3250 only) KEY_ROW4/ ENET_TXD0 C17 VDD_IOD I/O T Keyscan row 4 out I/O T Ethernet transmit data 0 (LPC3240 and LPC3250 only) KEY_ROW5/ ENET_TXD1 C18 VDD_IOD I/O T Keyscan row 5 out I/O T Ethernet transmit data 1 (LPC3240 and LPC3250 only) MS_BS/MAT2[1] A6 VDD_IOD I/O: P MS/SD card command out O Timer 2 match output 1 MS_DIO0/MAT0[0] A8 VDD_IOD I/O: P MS/SD card data 0 O Timer 0 match output 0 MS_DIO1/ MAT0[1] A7 VDD_IOD I/O: P MS/SD card data 1 O Timer 0 match output 1 MS_DIO2/ MAT0[2] B8 VDD_IOD I/O: P MS/SD card data 2 O Timer 0 match output 2 MS_DIO3/ MAT0[3] C8 VDD_IOD I/O: P MS/SD card data 3 O Timer 0 match output 3 MS_SCLK/ MAT2[0] B7 VDD_IOD I/O MS/SD card clock output O Timer 2 match output 0 n.c. B17, U17, U2 - - not connected ONSW M15 VDD_RTC O RTC match output for external power control P0[0]/ I2S1RX_CLK B5 VDD_IOB I/O Port 0 GPIO bit 0 I/O I2S1 receive clock P0[1]/ I2S1RX_WS D7 VDD_IOB I/O Port 0 GPIO bit 1 I/O I2S1 receive word select Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 18 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers P0[2]/ I2S0RX_SDA/ LCDVD[4] M17 VDD_IOA I/O Port 0 GPIO bit 2 I/O I2S0 receive data I/O LCD data bit 4 (LPC3230 and LPC3250 only) P0[3]/ I2S0RX_CLK/ LCDVD[5] M18 VDD_IOA I/O Port 0 GPIO bit 3 I/O I2S0 receive clock I/O LCD data bit 5 (LPC3230 and LPC3250 only) P0[4]/ I2S0RX_WS/ LCDVD[6] L15 VDD_IOA I/O Port 0 GPIO bit 4 I/O I2S0 receive word select I/O LCD data bit 6 (LPC3230 and LPC3250 only) P0[5]/ I2S0TX_SDA/ LCDVD[7] L16 VDD_IOA I/O Port 0 GPIO bit 5 I/O I2S0 transmit data I/O LCD data bit 7 (LPC3230 and LPC3250 only) P0[6]/ I2S0TX_CLK/ LCDVD[12] L17 VDD_IOA I/O Port 0 GPIO bit 6 I/O I2S0 transmit clock I/O LCD data bit 12 (LPC3230 and LPC3250 only) P0[7]/ I2S0TX_WS/ LCDVD[13] L18 VDD_IOA I/O Port 0 GPIO bit 7 I/O I2S0 transmit word select I/O LCD data bit 13 (LPC3230 and LPC3250 only) PLL397_LOOP R14 VDD_PLL397 analog filter PLL397 loop filter (for external components) PWM_OUT1/ LCDVD[16] D14 VDD_IOD O PWM1 out O LCD data bit 16 (LPC3230 and LPC3250 only) PWM_OUT2/INTSTAT/ LCDVD[19] D15 VDD_IOD O PWM2 output/internal interrupt status[1] O LCD data bit 19 (LPC3230 and LPC3250 only) RESET M14 VDD_RTC I Reset input, active LOW RESOUT G4 VDD_IOC O Reset out. Reflects external and WDT reset RTCX_IN P16 VDD_RTC analog in RTC oscillator input RTCX_OUT P17 VDD_RTC analog out RTC oscillator output SPI1_CLK/ SCK0 C9 VDD_IOD O SPI1 clock out O SSP0 clock out SPI1_DATIN/ MISO0/ GPI_25/ MCI1 C10 VDD_IOD I/O SPI1 data in I/O SSP0 MISO I/O General purpose input bit 25 I Motor control channel 1 input SPI1_DATIO/ MOSI0/ MCI2 B9 VDD_IOD I/O SPI1 data out (and optional input) I/O SSP0 MOSI I Motor control channel 2 input SPI2_CLK/ SCK1/ LCDVD[23] B10 VDD_IOD I/O SPI2 clock out I/O SSP1 clock out I/O LCD data bit 23 (LPC3230 and LPC3250 only) Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 19 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers SPI2_DATIO/ MOSI1/ LCDVD[20] A9 VDD_IOD I/O SPI2 data out (and optional input) I/O SSP1 MOSI I/O LCD data bit 20 (LPC3230 and LPC3250 only) SPI2_DATIN/ MISO1/ LCDVD[21]/ GPI_27 A10 VDD_IOD I/O SPI2 data in I/O SSP1 MISO I/O LCD data 21 (LPC3230 and LPC3250 only) I/O General purpose input bit 27 SYSCLKEN/ LCDVD[15] G17 VDD_IOD I/O T Clock request out for external clock source I/O T LCD data bit 15 (LPC3230 and LPC3250 only) SYSX_IN T17 VDD_OSC analog in System clock oscillator input SYSX_OUT R15 VDD_OSC analog out System clock oscillator output TS_XP R13 VDD_AD I/O Touchscreen X output TS_YP U16 VDD_AD I/O Touchscreen Y output TST_CLK2 C6 VDD_IOB O Test clock 2 out U1_RX/CAP1[0]/ GPI_15 K15 VDD_IOA I/O HS UART 1 receive I/O Timer 1 capture input 0 I/O General purpose input bit 15 U1_TX K16 VDD_IOA O HS UART 1 transmit U2_HCTS/ U3_CTS/GPI_16 J18 VDD_IOA I/O HS UART 2 Clear to Send input I UART 3 Clear to Send I/O General purpose input bit 16 U2_RX/ U3_DSR/GPI_17 K18 VDD_IOA I/O HS UART 2 receive I/O UART 3 data set ready I/O General purpose input bit 17 U2_TX/U3_DTR K17 VDD_IOA O HS UART 2 transmit O UART 3 data terminal ready out U3_RX/ GPI_18 J14 VDD_IOD I/O UART 3 receive I/O General purpose input bit 18 U3_TX J17 VDD_IOD O UART 3 transmit U5_RX/ GPI_20 F18 VDD_IOD I/O UART 5 receive I General purpose input bit 20 U5_TX H15 VDD_IOD O UART 5 transmit U6_IRRX/ GPI_21 F17 VDD_IOD I/O UART 6 receive (with IrDA) I General purpose input bit 21 U6_IRTX G16 VDD_IOD O UART 6 transmit (with IrDA) U7_HCTS/ CAP0[1]/ LCDCLKIN/ GPI_22 G13 VDD_IOD I HS UART 7 CTS in I Timer 0 capture input 1 I LCD panel clock in (LPC3230 and LPC3250 only) I General purpose input bit 22 Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 20 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers U7_RX/ CAP0[0]/ LCDVD[10]/ GPI_23 E17 VDD_IOD I/O HS UART 7 receive I/O Timer 0 capture input 0 I/O LCD data bit 10 (LPC3230 and LPC3250 only) I/O General purpose input bit 23 U7_TX/ MAT1[1]/ LCDVD[11] E18 VDD_IOD O HS UART 7 transmit O Timer 1 match output 1 O LCD data bit 11 (LPC3230 and LPC3250 only) USB_ATX_INT C4 VDD_IOC I Interrupt from USB ATX USB_DAT_VP/ U5_RX D5 VDD_IOC I/O: P USB transmit data, D+ receive I/O: P UART 5 receive USB_I2C_SCL E5 VDD_IOC I/O T I2C clock for USB ATX interface USB_I2C_SDA E6 VDD_IOC I/O T I2C data for USB ATX interface USB_OE_TP D6 VDD_IOC I/O USB transmit enable for DAT/SE0 USB_SE0_VM/ U5_TX C5 VDD_IOC I/O: P USB single ended zero transmit, D Receive I/O: P UART 5 transmit VDD_AD N12, N13 VDD_AD power 3.3 V supply for ADC/touch screen VDD_CORE G7, G9, G11, J7, J12, M7, M11 VDD_CORE power 1.2 V or 0.9 V supply for core VDD_COREFXD L12, M13 VDD_COREFXD power Fixed 1.2 V supply for digital portion of the analog block VDD_EMC J6, K6, K7, L6, M6, M8, N7, N8, N9, N10, N11 VDD_EMC power 1.8 V or 2.5 V or 3.3 V supply for External Memory Controller (EMC) VDD_IOA H13, J13 VDD_IOA power 1.8 V or 3.3 V supply for IOA domain VDD_IOB F8 VDD_IOB power 1.8 V or 3.3 V supply for IOB domain VDD_IOC F7, G6, H6, J5 VDD_IOC power 1.8 V or 3.3 V supply for IOC domain VDD_IOD F13, F9 VDD_IOD power 1.8 V to 3.3 V supply for IOD domain VDD_OSC T18 VDD_OSC power 1.2 V supply for main oscillator Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 21 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] The PWM2_CTRL register controls this pin function (see LPC32x0 User manual). VDD_PLL397 T16 VDD_PLL397 power 1.2 V supply for 397x PLL VDD_PLLHCLK R17 VDD_PLLHCLK power 1.2 V supply for HCLK PLL VDD_PLLUSB P15 VDD_PLLUSB power 1.2 V supply for USB PLL VDD_FUSE N14 VDD_FUSE power 1.2 V supply VDD_RTC K14 VDD_RTC power 1.2 V supply for RTC I/O VDD_RTCCORE L13 VDD_RTCCORE power 1.2 V supply for RTC VDD_RTCOSC N15 VDD_RTCOSC power 1.2 V supply for RTC oscillator VSS_AD P13 - power Ground for ADC/touch screen VSS_CORE G8, G10, G12, H7, K12, L7, M9, M10, M12 - power Ground for core VSS_EMC K5, L5, M5, N5, N6, P6, P7, P8, P9, P10, P11 - power Ground for EMC VSS_IOA K13 - power Ground VDD_IOA domain VSS_IOB F6 - power Ground VDD_IOB domain VSS_IOC F5, G5, H5 - power Ground VDD_IOC domain VSS_IOD F10, F11, F12, H12 - power Ground VDD_IOD domain VSS_OSC P14 - power Ground for main oscillator VSS_PLL397 T15 - power Ground for 397x PLL VSS_PLLHCLK R18 - power Ground for HCLK PLL VSS_PLLUSB R16 - power Ground for USB PLL VSS_RTCCORE L14 - power Ground for RTC VSS_RTCOSC P18 - power Ground for RTC oscillator Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 22 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] See LPC32x0 User manual for details. Table 5. Digital I/O pad types[1] Parameter Abbreviation I/O type I = input. O = output. I/O = bidirectional. I/O T = bidirectional or high impedance. Pin detail BK: pin has a bus keeper function that weakly retains the last logic level driven on an I/O pin. Bus keeper current for different I/O pin voltages: 0 V= 1 A (max) VDD_x = 1 A (max) 2/3  VDD_x = 55 A (max) 1/3  VDD_x = 60 A (max) PU: pin has a nominal 50 A internal pull-up connected. PD: pin has a nominal 50 A internal pull-down connected. P: pin has programmable input characteristics. Table 6. Supply domains Supply domain Voltage range Related supply pins Description VDD_CORE 0.9 V to 1.39 V VDD_CORE Core power domain. VDD_COREFXD 1.2 V VDD_COREFXD Fixed 1.2 V supply for digital portion of the analog block. other core domains 1.2 V VDD_PLL397, VDD_PLLHCLK, VDD_PLLUSB, VDD_FUSE, VDD_OSC 1.2 V supplies, tied to VDD_COREFXD. VDD_RTC 0.9 V to 1.39 V VDD_RTC, VDD_RTCCORE, VDD_RTCOSC RTC supply domain. Can be connected to a battery backed-up power source. VDD_AD 2.7 V to 3.6 V VDD_AD 3.3 V supply for ADC and touch screen. VDD_EMC 1.7 V to 1.95 V 2.3 V to 2.7 V 2.7 V to 3.6 V VDD_EMC External memory interface IO pins in 1.8 V range, 2.5 V range, or 3.3 V range. VDD_IOA[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOA Peripheral supply. VDD_IOB[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOB Peripheral supply. VDD_IOC[1] 1.7 V to 1.95 V or 2.3 V to 3.6 V VDD_IOC Peripheral supply. VDD_IOD[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOD Peripheral supply. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 23 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] The VDD_IOA, VDD_IOB, VDD_IOC, and VDD_IOD supply domains can be operated at a voltage independent of the other domains as long as all pins connected to the same peripheral are at the same voltage level. There are two special cases for determining supply domain voltages (for details see application note AN10777): a) Ethernet configured in MII mode: VDD_IOD must be the same as VDD_IOB. b) UART 3 when used with hardware flow control or when sharing an RS-232 transceiver with another UART: VDD_IOA must be the same as VDD_IOD. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 24 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7. Functional description 7.1 CPU and subsystems 7.1.1 CPU NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented a 32 kB instruction cache, a 32 kB data cache and a Vector Floating Point coprocessor. The ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the virtual memory capabilities required to support the multi-programming demands of modern operating systems. The basic ARM926EJ-S core V5TE instruction set includes DSP instruction extensions for native Jazelle Java Byte-code execution in hardware. The LPC3220/30/40/50 operates at CPU frequencies up to 266 MHz. 7.1.2 Vector Floating Point (VFP) coprocessor The LPC3220/30/40/50 includes a VFP co-processor providing full support for single-precision and double-precision add, subtract, multiply, divide, and multiply-accumulate operations at CPU clock speeds. It is compliant with the IEEE 754 standard for binary Floating-Point Arithmetic. This hardware floating point capability makes the microcontroller suitable for advanced motor control and DSP applications. The VFP has 3 separate pipelines for floating-point MAC operations, divide or square root operations, and Load/Store operations. These pipelines operate in parallel and can complete execution out of order. All single-precision instructions execute in one cycle, except the divide and square root instructions. All double-precision multiply and multiply-accumulate instructions take two cycles. The VFP also provides format conversions between floating-point and integer word formats. 7.1.3 Emulation and debugging The LPC3220/30/40/50 supports emulation and debugging via a dedicated JTAG serial port. An Embedded Trace Buffer allows tracing program execution. The dedicated JTAG port allows debugging of all chip features without impact to any pins that may be used in the application. 7.1.3.1 Embedded ICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an Embedded ICE protocol converter. The Embedded ICE protocol converter converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel (DCC) function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or entering the debug state. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 25 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.1.3.2 Embedded trace buffer The Embedded Trace Module (ETM) is connected directly to the ARM core. It compresses the trace information and exports it through a narrow trace port. An internal Embedded Trace Buffer (ETB) of 2048  24 bits captures the trace information under software debugger control. Data from the ETB is recovered by the debug software through the JTAG port. The trace contains information about when the ARM core switches between states. Instruction shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. For data accesses either data or address or both can be traced. 7.2 AHB matrix The LPC3220/30/40/50 has a multi-layer AHB matrix for inter-block communication. AHB is an ARM defined high-speed bus, which is part of the ARM bus architecture. AHB is a high-bandwidth low-latency bus that supports multi-master arbitration and a bus grant/request mechanism. For systems that have only one (CPU), or two (CPU and DMA) bus masters a simple AHB works well. However, if a system requires multiple bus masters and the CPU needs access to external memory, a single AHB bus can cause a bottleneck. To increase performance, the LPC3220/30/40/50 uses an expanded AHB architecture known as Multi-layer AHB. A Multi-layer AHB replaces the request/grant and arbitration mechanism used in a simple AHB with an interconnect matrix that moves arbitration out toward the slave devices. Thus, if a CPU and a DMA controller want access to the same memory, the interconnect matrix arbitrates between the two when granting access to the memory. This advanced architecture allows simultaneous access by bus masters to different resources with an increase in arbitration complexity. In this architectural implementation, removing guaranteed central arbitration and allowing more than one bus master to be active at the same time provides better overall microcontroller performance. In the LPC3220/30/40/50, the multi-Layer AHB system has a separate bus for each of seven AHB Masters: • CPU data bus • CPU instruction bus • General purpose DMA Master 0 • General purpose DMA Master 1 • Ethernet controller • USB controller • LCD controller There are no arbitration delays unless two masters attempt to access the same slave at the same time. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 26 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.2.1 APB Many peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APB performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 FAB Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions. A write access to FAB peripherals takes a single AHB clock and a read access to FAB peripherals takes two AHB clocks. 7.3 Physical memory map The physical memory map incorporates several distinct regions, as shown in Figure 3. When an application is running, the CPU interrupt vectors are re-mapped to allow them to reside in on-chip SRAM (IRAM). LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 27 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 3. LPC3220/30/40/50 memory map on-chip memory 0x4000 0000 0x0000 0000 0.0 GB 768 MB 1.0 GB 4.0 GB peripherals on AHB matrix slave port 5 0x0FFF FFFF 0x2000 0000 0x3000 0000 0x2FFF FFFF 0x1FFF FFFF 0x8000 0000 0xFFFF FFFF 0x1000 0000 0x3FFF FFFF 0x4FFF FFFF 0x5000 0000 0x7FFF FFFF peripherals on AHB matrix slave port 6 peripherals on AHB matrix slave port 7 off-chip memory IROM or IRAM 0x0000 0000 to 0x03FF FFFF dummy space for DMA 0x0400 0000 to 0x07FF FFFF IRAM 0x0800 0000 to 0x0BFF FFFF IROM 0x0C00 0000 to 0x0FFF FFFF AHB peripherals 0x2000 0000 to 0x2007 FFFF AHB peripherals 0x200A 0000 to 0x200B FFFF APB peripherals 0x2008 0000 to 0x2009 FFFF RESERVED AHB peripherals 0x3000 0000 to 0x31FF FFFF RESERVED FAB peripherals 0x4000 0000 to 0x4007 FFFF APB peripherals 0x4008 0000 to 0x400F FFFF RESERVED RESERVED RESERVED RESERVED RESERVED 0x9FFF FFFF 0xA000 0000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 0xE000 0000 0xE0FF FFFF 0xE100 0000 0xE1FF FFFF 0xE200 0000 0xE2FF FFFF 0xE300 0000 0xE3FF FFFF 0xE400 0000 2.0 GB EMC_DYCS0 EMC_DYCS1 EMC_CS0 EMC_CS1 EMC_CS2 EMC_CS3 002aae468 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 28 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.4 Internal memory 7.4.1 On-chip ROM The built-in 16 kB ROM contains a program which runs a boot procedure to load code from one of four external sources, UART 5, SSP0 (SPI mode), EMC Static CS0 memory, or NAND FLASH. After reset, execution always begins from the internal ROM. The bootstrap software first reads the SERVICE input (GPI_1). If SERVICE is LOW, the bootstrap starts a service boot and can download a program over serial link UART 5 to IRAM and transfer execution to the downloaded code. If the SERVICE pin is HIGH, the bootstrap routine jumps to normal boot. The normal boot process first tests SPI memory for boot information if present it uploads the boot code and transfers execution to the uploaded software. If the SPI is not present or no software is loaded, the bootloader will test the EMC Static CS0 memory for the presence of boot code and if present boots from static memory, If this test fails the boot loader will test external NAND flash for boot code and boot if code is present. The boot loader consumes no user memory space because it is in ROM. 7.4.2 On-chip SRAM On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8, 16, or 32 bit memory. The LPC3220/30/40/50 provides 256 kB of internal SRAM. 7.5 External memory interfaces The LPC3220/30/40/50 includes three external memory interfaces, NAND Flash controllers, Secure Digital Memory Controller, and an external memory controller for SDRAM, DDR SDRAM, and Static Memory devices. 7.5.1 NAND flash controllers The LPC3220/30/40/50 includes two NAND flash controllers, one for multi-level cell NAND flash devices and one for single-level cell NAND flash devices. The two NAND flash controllers use the same pins to interface to external NAND flash devices, so only one interface is active at a time. 7.5.1.1 Multi-Level Cell (MLC) NAND flash controller The MLC NAND flash controller interfaces to either multi-level or single-level NAND flash devices. An external NAND flash device is used to allow the bootloader to automatically load a portion of the application code into internal SRAM for execution following reset. The MLC NAND flash controller supports small (528 byte) and large (2114 byte) pages. Programmable NAND timing parameters allow support for a variety of NAND flash devices. A built-in Reed-Solomon encoder/decoder provides error detection and correction capability. A 528 byte data buffer reduces the need for CPU supervision during loading. The MLC NAND flash controller also provides DMA support. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 29 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.5.1.2 Single-Level Cell (SLC) NAND flash controller The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page transfers are supported, including a 20-byte DMA read and write FIFO. Hardware support for ECC (Error Checking and Correction) is included for the main data area. Software can correct a single bit error. 7.5.2 SD card controller The SD interface allows access to external SD memory cards. The SD card interface conforms to the SD Memory Card Specification Version 1.01. 7.5.2.1 Features • 1-bit and 4-bit data line interface support. • DMA is supported through the system DMA controller. • Provides all functions specific to the SD memory card. These include the clock generation unit, power management control, command and data transfer. 7.5.3 External memory controller The LPC3220/30/40/50 includes a memory controller that supports data bus SDRAM, DDR SDRAM, and static memory devices. The memory controller provides an interface between the system bus and external (off-chip) memory devices. The controller supports 16-bit and 32-bit wide SDR SDRAM devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes, as well as 16-bit wide data bus DDR SDRAM devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes. Two dynamic memory chip selects are supplied, supporting two groups of SDRAM: • DYCS0 in the address range 0x8000 0000 to 0x9FFF FFFF • DYCS1 in the address range 0xA000 0000 to 0xBFFF FFFF The memory controller also supports 8-bit, 16-bit, and 32-bit wide asynchronous static memory devices, including RAM, ROM, and flash, with or without asynchronous page mode. Four static memory chip selects are supplied for SRAM devices: • CS0 in the address range 0xE000 0000 to 0xE0FF FFFF • CS1 in the address range 0xE100 0000 to 0xE1FF FFFF • CS2 in the address range 0xE200 0000 to 0xE2FF FFFF • CS3 in the address range 0xE300 0000 to 0xE3FF FFFF The SDRAM controller uses three data ports to allow simultaneous requests from multiple on-chip AHB bus masters and has the following features. • Dynamic memory interface supports SDRAM, DDR-SDRAM, and low-power variants. • Read and write buffers to reduce latency and improve performance. • Static memory features include – asynchronous page mode read – programmable wait states – bus turnaround cycles – output enable and write enable delays LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 30 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers – extended wait • Power-saving modes dynamically control EMC_CKE[1:0] and EMC_CLK. • Dynamic memory self-refresh mode supported by software. • Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is, typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16, or 32 data bits per device. • Two reset domains enable dynamic memory contents to be preserved over a soft reset. • This controller does not support synchronous static memory devices (burst mode devices). 7.6 AHB master peripherals The LPC3220/30/40/50 implements four AHB master peripherals, which include a General Purpose Direct Memory Access (GPDMA) controller, a 10/100 Ethernet Media Access Controller (MAC), a Universal Serial Bus (USB) controller, and an LCD controller. Each of these four peripherals contain an integral DMA controller optimized to support the performance demands of the peripheral. 7.6.1 General Purpose DMA (GPDMA) controller The GPDMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the same AHB master, or one area by each master. The DMA controller supports the following peripheral device transfers. • Secure Digital (SD) Memory interface • High-speed UARTs • I2S0 and I2S1 ports • SPI1 and SPI2 interfaces • SSP0 and SSP1 interfaces • Memory The DMA controls eight DMA channels with hardware prioritization. The DMA controller interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width. DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either big-endian or little-endian. Incrementing or non-incrementing addressing for source and destination are supported, as well as programmable DMA burst size. Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. 7.6.2 Ethernet MAC The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 31 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.6.2.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. Wake-on-LAN power management support allows system wake-up using the receive filters or a magic frame detection filter. • Physical interface – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.6.3 USB interface The LPC3220/30/40/50 supports USB in either device, host, or OTG configuration. 7.6.3.1 USB device controller The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 32 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers condition is indicated via status registers. An interrupt is also generated if enabled. The DMA controller when enabled transfers data between the endpoint buffer and the USB RAM. Features • Fully compliant with USB 2.0 full-speed specification. • Supports 32 physical (16 logical) endpoints. • Supports control, bulk, interrupt and isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. • RAM message buffer size based on endpoint realization and maximum packet size. • Supports bus-powered capability with low suspend current. • Supports DMA transfer on all non-control endpoints. • One duplex DMA channel serves all endpoints. • Allows dynamic switching between CPU controlled and DMA modes. • Double buffer implementation for bulk and isochronous endpoints. 7.6.3.2 USB host controller The host controller enables data exchange with various USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies to the OHCI specification. Features • OHCI compliant. • OHCI specifies the operation and interface of the USB host controller and software driver. • The host controller has four USB states visible to the software driver: – USBOperational: Process lists and generate SOF tokens. – USBReset: Forces reset signaling on the bus, SOF disabled. – USBSuspend: Monitor USB for wake-up activity. – USBResume: Forces resume signaling on the bus. • HCCA register points to interrupt and isochronous descriptors list. • ControlHeadED and BulkHeadED registers point to control and bulk descriptors list. 7.6.3.3 USB OTG controller USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. Features • Fully compliant with On-The-Go supplement to the USB Specification 2.0 Revision 1.0. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 33 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers • Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices under software control. HNP is partially implemented in hardware. • Provides programmable timers required for HNP and SRP. • Supports slave mode operation through AHB slave interface. • Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG specification compliant ATX. 7.6.4 LCD controller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.6.4.1 Features • AHB bus master interface to access frame buffer. • Setup and control via a separate AHB slave interface. • Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. • Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320  200, 320  240, 640  200, 640  240, 640  480, 800  600, and 1024  768. • Hardware cursor support for single-panel displays. • 15 gray-level monochrome, 3375 color STN, and 32 k color palettized TFT support. • 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. • 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. • 16 bpp true-color non-palettized, for color STN and TFT. • 24 bpp true-color non-palettized, for color TFT. • Programmable timing for different display panels. • 256 entry, 16-bit palette RAM, arranged as a 128  32 bit RAM. • Frame, line, and pixel clock signals. • AC bias signal for STN, data enable signal for TFT panels. • Supports little and big-endian, and Windows CE data formats. • LCD panel clock may be generated from the peripheral clock or from a clock input pin. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 34 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.7 System functions To enhance the performance of the LPC3220/30/40/50 incorporates the following system functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and several power control features. These functions are described in the following sections 7.7.1 Interrupt controller The interrupt controller is comprised of three basic interrupt controller blocks, supporting a total of 73 interrupt sources. Each interrupt source can be individually enabled/disabled and configured for high or low level triggering, or rising or falling edge triggering. Each interrupt may also be steered to either the FIQ or IRQ input of the ARM9. Raw interrupt status and masked interrupt status registers allow versatile condition evaluation. In addition to peripheral functions, each of the six general purpose input/output pins and 12 of the 22 general purpose input pins are connected directly to the interrupt controller. 7.7.2 Watchdog timer The watchdog timer block is clocked by the main peripheral clock, which clocks a 32-bit counter. A match register is compared to the Timer. When configured for watchdog functionality, a match drives the match output low. The match output is gated with an enable signal that gives the opportunity to generate two type of reset signal: one that only resets chip internally, and another that goes through a programmable pulse generator before it goes to the external pin RESOUT and to the internal chip reset. 7.7.2.1 Features • Programmable 32-bit timer. • Internally resets the device if not periodically reloaded. • Flag to indicate that a watchdog reset has occurred. • Programmable watchdog pulse output on RESOUT pin. • Can be used as a standard timer if watchdog is not used. • Pause control to stop counting when core is in debug state. 7.7.3 Millisecond timer The millisecond timer is clocked by 32 kHz RTC clock, so a prescaler is not needed to obtain a lower count rate. The millisecond timer includes three match registers that are compared to the Timer/Counter value. A match can generate an interrupt and the cause the Timer/Counter either continue to run, stop, or be reset. 7.7.3.1 Features • 32-bit Timer/Counter, running from the 32 kHz RTC clock. • Counter or Timer operation. • Three 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Pause control to stop counting when core is in debug state. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 35 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.7.4 Clocking and power control features 7.7.4.1 Clocking Clocking in the LPC3220/30/40/50 is designed to be versatile, so that system and peripheral requirements may be met, while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed and some peripherals do this automatically. The LPC3220/30/40/50 supports three operational modes, two of which are specifically designed to reduce power consumption. The modes are: Run mode, Direct run mode, and Stop mode.These three operational modes give control over processing speed and power consumption. In addition, clock rates to different functional blocks may be changed by switching clock sources, changing PLL values, or altering clock divider configurations. This allows a trade-off of power versus processing speed based on application requirements. 7.7.4.2 Crystal oscillator The main oscillator is the basis for the clocks most chip functions use by default. Optionally, many functions can be clocked instead by the output of a PLL (with a fixed 397x rate multiplication) which runs from the RTC oscillator. In this mode, the main oscillator may be turned off unless the USB interface is enabled. If a SYSCLK frequency other than 13 MHz is required in the application, or if the USB block is not used, the main oscillator may be used with a frequency of between 1 MHz and 20 MHz. 7.7.4.3 PLLs The LPC3220/30/40/50 includes three PLLs: The 397x PLL allows boosting the RTC frequency to 13.008896 MHz for use as the primary system clock. The USB PLL provides the 48 MHz clock required by the USB block, and the HCLK PLL provides the basis for the CPU clock, the AHB bus clock, and the main peripheral clock. The 397x PLL multiplies the 32768 Hz RTC clock by 397 to obtain a 13.008896 MHz clock. The 397x PLL is designed for low power operation and low jitter. This PLL requires an external RC loop filter for proper operation. The HCLK PLL accepts an input clock from either the main oscillator or the output of the 397x PLL. The USB PLL only accepts an input clock from the main oscillator.The USB input clock runs through a divide-by-N pre-divider before entering the USB PLL. The input to the HCLK and USB PLLs may initially be divided down by a pre-divider value ‘N’, which may have the values 1, 2, 3, or 4. This pre-divider can allow a greater number of possibilities for the output frequency. Following the PLL input divider is the PLL multiplier. This can multiply the pre-divider output by a value ‘M’, in the range of 1 through 256. The resulting frequency must be in the range of 156 MHz to 320 MHz. The multiplier works by dividing the output of a Current Controlled Oscillator (CCO) by the value of M, then using a phase detector to compare the divided CCO output to the pre-divider output. The error value is used to adjust the CCO frequency. At the PLL output, there is a post-divider that can be used to bring the CCO frequency down to the desired PLL output frequency. The post-divider value can divide the CCO output by 1, 2, 4, 8, or 16. The post-divider can also be bypassed, allowing the PLL CCO LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 36 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers output to be used directly. The maximum PLL output frequency supported by the CPU is 266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock has strict requirements for nominal frequency (500 ppm) and jitter (500 ps). 7.7.4.4 Power control modes The LPC3220/30/40/50 supports three operational modes, two of which are specifically designed to reduce power consumption. The modes are: Run mode, Direct Run mode, and Stop mode. Run mode is the normal operating mode for applications that require the CPU, AHB bus, or any peripheral function other than the USB block to run faster than the main oscillator frequency. In Run mode, the CPU can run at up to 266 MHz and the AHB bus can run at up to 133 MHz. Direct Run mode allows reducing the CPU and AHB bus rates in order to save power. Direct Run mode can also be the normal operating mode for applications that do not require the CPU, AHB bus, or any peripheral function other than the USB block to run faster than the main oscillator frequency. Direct Run mode is the default mode following chip reset. Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals other than the USB block. 7.7.4.5 Reset Reset is accomplished by an active LOW signal on the RESET input pin. A reset pulse with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the oscillator to start up and stabilize after VDD reaches operational voltage. An internal reset with a minimum duration of 10 clock pulses will also be applied if the watchdog timer generates an internal device reset. The RESET pin is located in the RTC power domain. This means that the RTC power must be present for an external reset to have any effect. The RTC power domain nominally runs from 1.2 V, but the RESET pin can be driven as high as 1.95 V. 7.8 Communication peripheral interfaces In addition to the Ethernet MAC and USB interfaces there are many more serial communication peripheral interfaces available on the LPC3220/30/40/50. Here is a list of the serial communication interfaces: • Seven UARTs; four standard UARTs and three high-speed UARTs • Two SPI serial I/O controllers • Two SSP serial I/O controllers • Two I2C serial I/O controllers • Two I2S audio controllers A short functional description of each of these peripherals is provided in the following sections. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 37 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.8.1 UARTs The LPC3220/30/40/50 contains seven UARTs. Four are standard UARTs, and three are high-speed UARTs. 7.8.1.1 Standard UARTs The four standard UARTs are compatible with the INS16Cx50. These UARTs support rates up to 460800 bit/s from a 13 MHz peripheral clock. Features • Each standard UART has 64 byte Receive and Transmit FIFOs. • Receiver FIFO trigger points at 16, 32, 48, and 60 Bytes. • Transmitter FIFO trigger points at 0, 4, 8, and 16 Bytes. • Register locations conform to the “550” industry standard. • Each standard UART has a fractional rate pre-divider and an internal baud rate generator. • The standard UARTs support three clocking modes: on, off, and auto-clock. The auto-clock mode shuts off the clock to the UART when it is idle. • UART 6 includes an IrDA mode to support infrared communication. • The standard UARTs are designed to support data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800) bit/s. • Each UART includes an internal loopback mode. 7.8.1.2 High-speed UARTs The three high-speed UARTs are designed to support rates up to 921600 bit/s from a 13 MHz peripheral clock for on-board communication in low noise conditions. This is accomplished by changing the over sampling from 16 to 14 and altering the rate generation logic. Features • Each high-speed UART has 64-byte Receive and Transmit FIFOs. • Receiver FIFO trigger points at 1, 4, 8, 16, 32, and 48 B. • Transmitter FIFO trigger points at 0, 4, and 8 B. • Each high-speed UART has an internal baud rate generator. • The high-speed UARTs are designed to support data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s. • The three high speed UARTs only support (8N1) 8-bit data word length, 1-stop bit, no parity, and no flow control as a the communications protocol. • Each UART includes an internal loopback mode. 7.8.2 SPI serial I/O controller The LPC3220/30/40/50 has two Serial Peripheral Interfaces (SPI). The SPI is a 3-wire serial interface that is able to interface with a large range of serial peripheral or memory devices (SPI mode 0 to 3 compatible slave devices). LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 38 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. The SPI implementation on the LPC3220/30/40/50 does not support operation as a slave. 7.8.2.1 Features • Supports slaves compatible with SPI modes 0 to 3. • Half duplex synchronous transfers. • DMA support for data transmit and receive. • 1-bit to 16-bit word length. • Choice of LSB or MSB first data transmission. • 64  16-bit input or output FIFO. • Bit rates up to 52 Mbit/s. • Busy input function. • DMA time out interrupt to allow detection of end of reception when using DMA. • Timed interrupt to facilitate emptying the FIFO at the end of a transmission. • SPI clock and data pins may be used as general purpose pins if the SPI is not used. • Slave selects can be supported using GPO or GPIO pins 7.8.3 SSP serial I/O controller The LPC3220/30/40/50 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.8.3.1 Features • Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • Maximum SPI bus data bit rate of 1⁄2 (Master mode) and 1⁄2 (Slave mode) of the input clock rate • DMA transfers supported by GPDMA 7.8.4 I2C-bus serial I/O controller There are two I2C-bus interfaces in the LPC32x0 family of controllers. These I2C blocks can be configured as a master, multi-master or slave supporting up to 400 kHz. The I2C blocks also support 7 or 10 bit addressing. Each has a four word FIFO for both transmit and receive. An interrupt signal is available from each block. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 39 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are only available when the controller is configured as a Master/Slave device and is operating in a multi-master environment. Separate TX FIFOs are needed in a multi-master because a controller might have a message queued for transmission when an external master addresses it to be come a slave-transmitter, a second source of data is needed. Note that the I2C clock must be enabled in the I2CCLK_CTRL register before using the I2C. The I2C clock can be disabled between communications, if used as a single master I2C-bus interface, software has full control of when I2C communication is taking place on the bus. 7.8.4.1 Features • The two I2C-bus blocks are standard I2C-bus compliant interfaces that may be used in Single-master, Multi-master or Slave modes. • Programmable clock to allow adjustment of I2C-bus transfer rates. • Bidirectional data transfer. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. 7.8.5 I2S-bus audio controller The I2S-bus provides a standard communication interface for digital audio applications The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. Each I2S connection can act as a master or a slave. The master connection determines the frequency of the clock line and all other slaves are driven by this clock source. The two I2S-bus interfaces on the LPC3220/30/40/50 provides a separate transmit and receive channel, providing a total of two transmit channels and two receive channels. Each I2S channel supports monaural or stereo formatted data. 7.8.5.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • Supports standard sampling frequencies (8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz). • Word select period can be configured in master mode (separately for I2S input and output). • Two eight-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop, and mute options separately for I2S input and I2S output. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 40 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.9 Other peripherals In addition to the communication peripherals there are many general purpose peripherals available in the LPC3220/30/40/50. Here is a list of the general purpose peripherals. • GPI/O • Keyboard scanner • Touch screen controller and 10-bit Analog-to-Digital-Converter • Real-time clock • High-speed timer • Four general purpose 32-bit timer/external event counters • Two simple PWMs • One motor control PWM A short functional description of each of these peripherals is provided in the following sections. 7.9.1 General purpose parallel I/O Some device pins that are not dedicated to a specific peripheral function have been designed to be general purpose inputs, outputs, or input/outputs. Also, some pins may be configured either as a specific peripheral function or a general purpose input, output, or input/output. A total of 51 pins can potentially be used as general purpose input/outputs, 24 as general purpose outputs, and 22 as general purpose inputs. GPIO pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of GPIO and GPO outputs controlled by that register simultaneously. The value of the output register for standard GPIOs and GPO pins may be read back, as well as the current actual state of the port pins. In addition to GPIO pins on port 0, port 1, and port 2, there are 22 GPI, 24 GPO, and six GPIO pins. When the SDRAM bus is configured for 16 data bits, 13 of the remaining SDRAM data pins may be used as GPIOs. 7.9.1.1 Features • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • A single register selects direction for pins that support both input and output modes. • Direction control of individual bits. • For input/output pins, both the programmed output state and the actual pin state can be read. • There are a total of 12 general purpose inputs, 24 general purpose outputs, and six general purpose input/outputs. • Additionally, 13 SDRAM data lines may be used as GPIOs if a 16-bit SDRAM interface is used (rather than a 32-bit interface). LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 41 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.9.2 Keyboard scanner The keyboard scanner function can automatically scan a keyboard of up to 64 keys in an 8  8 matrix. In operation, the keyboard scanner’s internal state machine will normally be in an idle state, with all KEY_ROWn pins set high, waiting for a change in the column inputs to indicate that one or more keys have been pressed. When a keypress is detected, the matrix is scanned by setting one output pin high at a time and reading the column inputs. After de-bouncing, the keypad state is stored and an interrupt is generated. The keypad is then continuously scanned waiting for ‘extra key pressed’ or ‘key released’. Any new keypad state is scanned and stored into the matrix registers followed by a new interrupt request to the interrupt controller. It is possible to detect and separate up to 64 multiple keys pressed. 7.9.2.1 Features • Supports up to 64 keys in 8  8 matrix. • Programmable de-bounce period. • A key press can wake up the CPU from Stop mode. 7.9.3 Touch screen controller and 10-bit ADC The LPC3220/30/40/50 microcontrollers includes Touch Screen Controller (TSC) hardware, which automatically measures and determines the X and Y coordinates where a touch screen is pressed. In addition, the TSC can measure an analog input signal on the AUX_IN pin. Optionally, the TSC can operate as an Analog-to-Digital Converter (ADC). The ADC supports three channels and uses 10-bit successive approximation to produce results with a resolution of 10 bits in 11 clock cycles. The analog portion of the ADC has its own power supply to enhance the low noise characteristics of the converter. This voltage is only supplied internally when the core has voltage. However, the ADC block is not affected by any difference in ramp-up time for VDD_AD and VDD_CORE voltage supplies. 7.9.3.1 Features • Measurement range of 0 V to VDD_AD (nominally 3.3 V). • Low-noise ADC. • 10-bit resolution. • Three input channels. • Uses 32 kHz RTC clock or peripheral clock. 7.9.4 Real-Time Clock (RTC) and battery RAM The RTC runs at 32768 Hz using a very low power oscillator. The RTC counts seconds and can generate alarm interrupts that can wake up the device from Stop mode. The RTC clock can also clock the 397x PLL, the Millisecond Timer, the ADC, the Keyboard Scanner and the PWMs. The RTC up-counter value represents a number of seconds elapsed since second 0, which is an application determined time. The RTC counter will reach maximum value after about 136 years. The RTC down-counter is initiated with all ones. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 42 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Two 32-bit match registers are readable and writable by the processor. A match will result in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be triggered by a match event and cause an external power supply to turn on all of the operating voltages, as a way to startup after power has been removed. The RTC block is implemented in a separate voltage domain. The block is supplied via a separate supply pin from a battery or other power source. The RTC block also contains 32 words (128 bytes) of very low voltage SRAM. This SRAM is able to hold its contents down to the minimum RTC operating voltage. 7.9.4.1 Features • Measures the passage of time in seconds. • 32-bit up and down seconds counters. • Ultra-low power design to support battery powered systems. • Dedicated 32 kHz oscillator. • An output pin is included to assist in waking up when the chip has had power removed to all functions except the RTC. • Two 32-bit match registers with interrupt option. • 32 words (128 bytes) of very low voltage SRAM. • The RTC and battery RAM power have an independent power domain and dedicated supply pins, which can be powered from a battery or power supply. Remark: The LPC3220/30/40/50 will run at voltages down to 0.9 V at frequencies below 14 MHz. However, the ARM core cannot access the RTC registers and battery RAM when the core supply voltage is at 0.9 V and the RTC supply is at 1.2 V. 7.9.5 Enhanced 32-bit timers/external event counters The LPC3220/30/40/50 includes six 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.9.5.1 Features • A 32-bit Timer/Counter with a programmable 32-bit pre-scaler. • Counter or Timer operation. • Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – continuous operation with optional interrupt generation on match – stop timer on match with optional interrupt generation – reset timer on match with optional interrupt generation • Up to four external outputs corresponding to match registers, with the following capabilities: LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 43 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers – set LOW on match – set HIGH on match – toggle on match – do nothing on match 7.9.6 High-speed timer The high-speed timer block is clocked by the main peripheral clock. The clock is first divided down in a 16-bit programmable pre-scale counter which clocks a 32-bit timer/counter. The high-speed timer includes three match registers that are compared to the timer/counter value. A match can generate an interrupt and cause the timer/counter to either continue to run, stop, or be reset. The high-speed timer also includes two capture registers that can take a snapshot of the timer/counter value when an input signal transitions. A capture event may also generate an interrupt. 7.9.6.1 Features • 32-bit timer/counter with programmable 16-bit pre-scaler. • Counter or timer operation. • Two 32-bit capture registers. • Three 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Pause control to stop counting when core is in debug state. 7.9.7 Pulse Width Modulators (PWMs) The LPC3220/30/40/50 provides two simple PWMs. They are clocked separately by either the main peripheral clock or the 32 kHz RTC clock. Both PWMs have a duty cycle programmable in 255 steps. 7.9.7.1 Features • Clocked by the main peripheral clock or the 32 kHz RTC clock. • Programmable 4-bit pre-scaler. • Duty cycle programmable in 255 steps. • Output frequency up to 50 kHz when using a 13 MHz peripheral clock. 7.9.8 Motor control pulse width modulator The Motor Control PWM (MCPWM) provides a set of features for three-phase AC and DC motor control applications in a single peripheral. The MCPWM can also be configured for use in other generalized timing, counting, capture, and compare applications. 7.9.8.1 Features • 32-bit timer • 32-bit period register LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 44 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers • 32-bit pulse-width (match) register • 10-bit dead-time register and an associated 10-bit dead-time counter • 32-bit capture register • Two PWM (match) outputs (pins MCOA0/1/2 and MCOB0/1/2) with opposite polarities • Period interrupt, pulse-width interrupt, and capture interrupt 8. Basic architecture The LPC3220/30/40/50 is a general purpose ARM926EJ-S 32-bit microprocessor with a 32 kB instruction cache and a 32 kB data cache. The microcontroller offers high performance and very low power consumption. The ARM architecture is based on RISC principles, which results in the instruction set and related decode mechanism being much simpler than equivalent micro programmed CISCs. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. The ARM926EJ-S core employs a 5-stage pipeline so processing and memory system accesses can occur continuously. At any one point in time, several operations are in progress: subsequent instruction fetch, next instruction decode, instruction execution, memory access, and write-back. The combination of architectural enhancements gives the ARM9 about 30 % better performance than an ARM7 running at the same clock rate: • Approximately 1.3 clocks per instruction for the ARM926EJ-S compared to 1.9 clocks per instruction for ARM7TDMI. • Approximately 1.1 Dhrystone MIPS/MHz for the ARM926EJ-S compared to 0.9 Dhrystone MIPS/MHz for ARM7TDMI. The ARM926EJ-S processor also employs an operational state known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb state is the use of a super-reduced instruction set. Essentially, the ARM926EJ-S processor core has two instruction sets: 1. The standard 32-bit ARM set 2. The 16-bit Thumb set The Thumb set’s smaller 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining many of ARM’s 32-bit performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates using the same 32-bit register set as ARM code. Thumb code size is up to 65 % smaller than ARM code size, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. Additionally, the ARM926EJ-S core includes enhanced DSP instructions and multiplier, as well as an enhanced 32-bit MAC block. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 45 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 9. Limiting values [1] The following applies to Table 7: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Core, PLL, oscillator, and RTC supplies; applies to pins VDD_CORE, VDD_COREFXD, VDD_OSC, VDD_PLL397, VDD_PLLHCLK, VDD_PLLUSB, VDD_RTC, VDD_RTCCORE, and VDD_RTCOSC. [3] I/O pad supply; applies to domains VDD_EMC. [4] Applies to VDD_AD pins. [5] Applies to pins in the following domains VDD_IOA, VDD_IOB, VDD_IOC, and VDD_IOD. [6] Including voltage on outputs in 3-state mode. [7] Based on package heat transfer, not device power consumption. Calculated package thermal resistance (ThetaJA): 35.766 C/W (with JEDEC Test Board and 0 m/s airflow, 15 % accuracy). [8] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. [9] Charge device model per AEC-Q100-011. Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Notes Min Max Unit VDD(1V2) supply voltage (1.2 V) [2] 0.5 +1.4 V VDD(EMC) external memory controller supply voltage [3] 0.5 +4.6 V VDDA(3V3) analog supply voltage (3.3 V) [4] 0.5 +4.6 V VDD(IO) input/output supply voltage [5] 0.5 +4.6 V VIA analog input voltage 0.5 +4.6 V VI input voltage 1.8 V pins [6] 0.5 +2.4 V 3.3 V pins [6] 0.5 +4.6 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Tstg storage temperature 65 +150 C Ptot(pack) total power dissipation (per package) max. junction temp 125 C max. ambient temp 85 C [7]- 1.12 W VESD electrostatic discharge voltage HBM [8] - 2500 V CDM [9] - 1000 V LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 46 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD(1V2) supply voltage (1.2 V) core supply voltage for full performance; 266 MHz (see Figure 4); VDD_CORE supply domain [2] 1.31 1.35 1.39 V core supply voltage for normal performance; 208 MHz (see Figure 4); VDD_CORE supply domain [2] 1.1 1.2 1.39 V core supply voltage for reduced power; up to 14 MHz CPU; VDD_CORE supply domain [2] 0.9 - 1.39 V RTC supply voltage; VDD_RTC supply domain [3] 0.9 - 1.39 V PLL and oscillator supply voltage [4] 1.1 1.2 1.39 V VDD(EMC) external memory controller supply voltage in 1.8 V range [5] 1.7 1.8 1.95 V in 2.5 V range [6] 2.3 2.5 2.7 V in 3.3 V range [7] 2.7 3.3 3.6 V VDD(IO) input/output supply voltage VDD_IOA, VDD_IOB, and VDD_IOD supply domain in 1.8 V range 1.7 1.8 1.95 V in 3.3 V range 2.7 3.3 3.6 V VDD_IOC supply domain in 1.8 V range 1.7 1.8 1.95 V in 3.3 V range 2.3 3.3 3.6 V VDDA(3V3) analog supply voltage (3.3 V) applies to pins in VDD_AD power domain 2.7 3.3 3.6 V LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 47 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Power consumption in Run, direct Run, and Stop modes IDD(run) Run mode supply current Tamb = 25 C; code while(1){} executed from IRAM; all peripherals enabled I-cache/D-cache, MMU enabled; CPU clock = 208 MHz; VDD_CORE = 1.2 V - 150 - mA I-cache/D-cache, MMU enabled; CPU clock = 266 MHz; VDD_CORE = 1.35 V - 218 - mA I-cache/D-cache, MMU disabled; CPU clock = 208 MHz; VDD_CORE = 1.2 V - 78 - mA I-cache/D-cache, MMU disabled; CPU clock = 266 MHz; VDD_CORE = 1.35 V - 111 - mA IDD(drun) direct Run mode supply current Tamb = 25 C; CPU clock = 13 MHz; code while(1){} executed from IRAM; all peripherals disabled I-cache/D-cache, MMU enabled; VDD_CORE = 1.2 V - 7.8 - mA I-cache/D-cache, MMU enabled; VDD_CORE = 0.9 V - 5.6 - mA I-cache/D-cache, MMU disabled; VDD_CORE = 1.2 V - 5 - mA I-cache/D-cache, MMU disabled; VDD_CORE = 0.9 V - 3.5 - mA IDD(stop) Stop mode supply current Tamb = 25 C; CPU clock stopped internally; all peripherals disabled VDD_CORE = 1.2 V - 400 - A VDD_CORE = 0.9 V - 400 - A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 48 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers IDD(RTC) RTC supply current normal operation; VDD_RTC = VDD_RTCCORE = VDD_RTCOSC = 1.2 V; Tamb = 25 C [8]- 13 - A RTC back up operation; Rev “-” silicon [9]- 30 - A Rev “A” silicon [9]- 4 - IDD supply current for HCLK; PLL output frequency = 266 MHz; VDD_PLLHCLK = 1.2 V - 2 - mA for USB; VDD_PLLUSB = 1.2 V - 2 - mA for ADC; interrupt driven loop converting ADIN[2:0]; VDD_AD = 3.3 V -  1 - mA Input pins and I/O pins configured as input VI input voltage [10][12]0 - VDD(IO) V VIH HIGH-level input voltage 1.8 V inputs 0.7  VDD(IO) - - V 3.3 V inputs 0.7  VDD(IO) - - V VIL LOW-level input voltage 1.8 V inputs - - 0.3  VDD(IO) V 3.3 V inputs - - 0.3  VDD(IO) V Vhys hysteresis voltage 1.8 V inputs 0.1  VDD(IO) - - V 3.3 V inputs 0.1  VDD(IO) - - V IIL LOW-level input current VI = 0 V; no pull-up - - 1 A IIH HIGH-level input current VI = VDD(IO); no pull-down [10]- - 1 A Ilatch I/O latch-up current (1.5VDD(IO)) < VI < (1.5VDD(IO)) [10]- - 100 mA Ipu pull-up current 1.8 V inputs with pull-up; VI = 0 V 6 12 22 A 3.3 V inputs with pull-up; VI = 0 V 25 50 80 A Ipd pull-down current 1.8 V inputs with pull-down; VI = VDD(IO) 5 12 22 A 3.3 V inputs with pull-down; VI = VDD(IO) 25 50 85 A II input current bus keeper inputs; VI = VDD - - 1 A VI = 0.67  VDD - - 55 A VI = 0.33  VDD - - 60 A VI = 0 V - - 1 A Ci input capacitance Excluding bonding pad capacitance - - 3.3 pF Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 49 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Output pins and I/O pins configured as output VO output voltage [10][11] [12][13] 0 - VDD(IO) V VOH HIGH-level output voltage 1.8 V outputs; IOH = 1 mA [14] VDD(IO)  0.4 - - V 3.3 V outputs; IOH = 4 mA [14] VDD(IO)  0.4 - - V VOL LOW-level output voltage 1.8 V outputs; IOL = 4 mA [14]- - 0.4 V 3.3 V outputs; IOL = 4 mA [14]- - 0.4 V IOH HIGH-level output current VDD(IO) = 1.8 V; VOH = VDD(IO)  0.4 V [10][14] 3.3 - - mA VDD(IO) = 3.3 V; VOH = VDD(IO)  0.4 V 6.5 - - mA IOL LOW-level output current VDD(IO) = 1.8 V; VOL = 0.4 V [10][14] 1.5 - - mA VDD(IO) = 3.3 V; VOL = 0.4 V 3 - - mA IOZ OFF-state output current VO = 0 V; VO = VDD(IO); no pull-up/down [10]- - 1 A IOHS HIGH-level short-circuit output current VDD(IO) = 1.8 V; VOH = 0 V [15]- - 66 mA VDD(IO) = 3.3 V; VOH = 0 V - - 183 mA IOLS LOW-level short-circuit output current VDD(IO) = 1.8 V; VOL = VDD(IO) [10][15]- - 34 mA VDD(IO) = 3.3 V; VOL = VDD(IO) - - 105 mA Zo output impedance VDD(IO) = 1.8 V 40 - 60  VDD(IO) = 3.3 V 40 - 60  EMC pins VI input voltage [12]0 - VDD(EMC) V VIH HIGH-level input voltage 1.8 V inputs 0.7  VDD(EMC) - - V 3.3 V inputs 0.7  VDD(EMC) - - V VIL LOW-level input voltage 1.8 V inputs - - 0.3  VDD(EMC) V 3.3 V inputs - - 0.3  VDD(EMC) V Vhys hysteresis voltage 1.8 V inputs 0.4 - 0.6 V 3.3 V inputs 0.55 - 0.85 V IIL LOW-level input current VI = 0 V; no pull-up - - 0.3 A IIH HIGH-level input current VI = VDD(EMC); no pull-down - - 0.3 A Ilatch I/O latch-up current (1.5VDD(EMC)) < VI < (1.5VDD(EMC)) - - 100 mA Ipu pull-up current 1.8 V inputs with pull-up; VI = 0 34 62 107 A 3.3 V inputs with pull-up; VI = 0 97 169 271 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 50 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Ipd pull-down current 1.8 V inputs with pull-down; VI = VDD(EMC) 23 51 93 A 3.3 V inputs with pull-down; VI = VDD(EMC) 73 155 266 A Ci input capacitance Excluding bonding pad capacitance - - 2.1 pF VO output voltage [11] [12][13] 0 - VDD(EMC) V VOH HIGH-level output voltage 1.8 V outputs; IOH = 1 mA [14] VDD(EMC)  0.3 - - V 3.3 V outputs; IOH = 4 mA [14] VDD(EMC)  0.3 - - V VOL LOW-level output voltage 1.8 V outputs; IOL = 4 mA [14]- - 0.3 V 3.3 V outputs; IOL = 4 mA [14]- - 0.3 V IOH HIGH-level output current VDD(EMC) = 1.8 V; VOH = VDD(EMC)  0.4 V [14] 6 - - mA VDD(EMC) = 3.3 V; VOH = VDD(EMC)  0.4 V 6 - - mA IOL LOW-level output current VDD(EMC) = 1.8 V; VOL = 0.4 V [14]6 - - mA VDD(EMC) = 3.3 V; VOL = 0.4 V 6 - - mA IOZ OFF-state output current VO = 0 V; VO = VDD(EMC); no pull-up/down - - 0.3 A IOHS HIGH-level short-circuit output current VDD(EMC) = 1.8 V; VOH = 0 V [15]- - 49 mA VDD(EMC) = 3.3 V; VOH = 0 V - - 81 mA IOLS LOW-level short-circuit output current VDD(EMC) = 1.8 V; VOL = VDD(EMC) [14]- - 49 mA VDD(EMC) = 3.3 V; VOL = VDD(EMC) - - 86 mA Zo output impedance VDD(EMC) = 1.8 V 35 40 58  VDD(EMC) = 3.3 V 32 35 45  I2C pins VI input voltage [10] [12] 0 - 5.5 V VIH HIGH-level input voltage 1.8 V inputs 0.7  VDD(IO) - - V 3.3 V inputs 0.7  VDD(IO) - - V VIL LOW-level input voltage 1.8 V inputs - - 0.3  VDD(IO) V 3.3 V inputs - - 0.3  VDD(IO) V IIL LOW-level input current VI = 0 V; no pull-up - - 10 A IIH HIGH-level input current VI = VDD(IO); no pull-down [10]- - 10 A Ilatch I/O latch-up current (1.5VDD(IO)) < VI < (1.5VDD(IO)) [10]- - 100 mA Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 51 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Ci input capacitance Excluding bonding pad capacitance - - 1.6 pF VOL LOW-level output voltage 1.8 V outputs; IOL = 4 mA [14]- - 0.4 V 3.3 V outputs; IOL = 4 mA [14]- - 0.4 V IOL LOW-level output current VDD(IO) = 1.8 V; VOL = 0.4 V [10][14]3 - - mA VDD(IO) = 3.3 V; VOL = 0.4 V 3 - - mA IOZ OFF-state output current VO = 0 V; VO = VDD(IO); no pull-up/down [10]- - 10 A IOLS LOW-level short-circuit output current VDD(IO) = 1.8 V; VOL = VDD(IO) [10][15]- - 40 mA VDD(IO) = 3.3 V; VOL = VDD(IO) - - 40 mA ONSW pin VO output voltage [10][11] [12][13] 0 - VDD(1V2) V VOH HIGH-level output voltage 1.2 V outputs; IOH = 1 mA [14] VDD(1V2)  0.4 - - V VOL LOW-level output voltage 1.2 V outputs; IOL = 4 mA [14]- - 0.4 V IOH HIGH-level output current VOH = VDD(1V2)  0.4 V [10][14] 4 - - mA IOL LOW-level output current VOL = 0.4 V [10][14]3 - - mA IOZ OFF-state output current VO = 0 V; VO = VDD(1V2); no pull-up/down [10]- - 1.5 A IOHS HIGH-level short-circuit output current VDD(1V2) = 1.8 V; VOH = 0 V [15]- - 135 mA IOLS LOW-level short-circuit output current VOL = VDD(1V2) [10][15]- - 135 mA Zo output impedance VDD(1V2) = 1.2 V 40 - 60  Oscillator input/output pins Vi(xtal) crystal input voltage on pins RTCX_IN and SYSX_IN 0.5 - +1.3 V Vo(xtal) crystal output voltage on pins RTCX_OUT and SYSX_OUT 0.5 - +1.3 V RESET pin VI input voltage [10] [12] 0 - 1.95 V VIH HIGH-level input voltage 1.2 V inputs 0.7  VDD(1V2) - - V VIL LOW-level input voltage 1.2 V inputs - - 0.3  VDD(1V2) V IIL LOW-level input current VI = 0 V; no pull-up - - 1 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 52 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Applies to VDD_CORE pins. [3] Applies to pins VDD_RTC, VDD_RTCCORE, and VDD_RTCOSC. [4] Applies to pins VDD_COREFXD, VDD_OSC, VDD_PLL397, VDD_PLLHCLK, and VDD_PLLUSB. [5] Applies when using 1.8 V Mobile DDR or Mobile SDR SDRAM. [6] Applies when using 2.5 V DDR memory. [7] Applies when using 3.3 V SDR SDRAM and SRAM. [8] Specifies current on combined VDD_RTCx during normal chip operation: VDD_RTC, VDD_CORE, VDD_OSC = 1.2 V and VDD_CORE, VDD_IOx at typical voltage. [9] Specifies current on combined VDD_RTCx during backup operation: VDD_RTC, VDD_CORE, VDD_OSC = 1.2 V and all other VDD_x at 0 V. [10] Referenced to the applicable VDD for the pin. [11] Including voltage on outputs in 3-state mode. [12] The applicable VDD voltage for the pin must be present. [13] 3-state outputs go into 3-state mode when the applicable VDD voltage for the pin is grounded. [14] Accounts for 100 mV voltage drop in all supply lines. [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. IIH HIGH-level input current VI = VDD; no pull-down [10]- - 1 A IOZ OFF-state output current VO = 0 V; VO = VDD; no pull-up/down [10]- - 1 A Ilatch I/O latch-up current (1.5VDD) < VI < (1.5VDD) [10]- - 100 mA Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 53 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10.1 Minimum core voltage requirements Figure 4 shows the minimum core supply voltage that should be applied for a given core frequency on pin VDD_CORE to ensure stable operation of the LPC3220/30/40/50. 10.2 Power supply sequencing The LPC32x0 has no power sequencing requirements, that is, VDD(1V2), VDD(EMC), VDD(IO), and VDDA(3V3) can be switched on or off independent of each other. An internal circuit ensures that the system correctly powers up in the absence of core power. During IO power-up this circuit takes care that the system is powered in a defined mode. The same is valid for core power-down. 10.3 Power consumption per peripheral [1] All three Ethernet clocks are in enabled in the MAC_CLK_CTRL register (see LPC32x0 User manual). Fig 4. Minimum required core supply voltage for different core frequencies core frequency (MHz) 160 200 240 280 002aae872 1.0 1.2 1.4 0.8 VDD_CORE (V) Table 9. Power consumption per peripheral Tamb = 25 C; CPU clock = 208 MHz; I-cache/D-cache, MMU disabled; VDD_CORE = 1.2 V; VDD(IO) = 1.8 V; USB AHB, IRAM, and IROM clocks always on; all peripherals are at their default state at reset. Peripheral clocks are disabled except for peripheral measured. Peripheral IDD(run) / mA High-speed UART (set to 115 200 Bd (8N1)) 0.3 I2C-bus 0.3 SSP 0.6 I2S 0.5 DMA 6.3 EMC 7.3 Multi-level NAND controller 1.4 Single-level NAND controller 0.3 LCD 5.6 Ethernet MAC[1] 2.9 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 54 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10.4 Power consumption in Run mode Power consumption is shown in Figure 5 for WinCE applications running under typical conditions from SDRAM. MMU and I-cache/D-cache are enabled. The VFP is turned on but not used. I2S-interface (channel 1), LCD, SLC NAND controller, I2C1-bus, SD card, touchscreen ADC, and UART 3 are turned on. All other peripherals are turned off. The AHB clock HCLK is identical to the core clock for frequencies up to 133 MHz, which is the maximum allowed HCLK frequency. For higher core frequencies, the HCLK PLL output must be divided by 2 to obtain an HCLK frequency lower than or equal to 133 MHz resulting in correspondingly lower power consumption by the AHB peripherals. Conditions: Tamb = 25 C; VDD_CORE = 1.2 V for core frequencies  208 MHz; VDD_CORE = 1.35 V for core frequencies > 208 MHz; VDD(IO) = 1.8 V. (1) WinCE running from SDRAM; playing wmv file at 20 frames/s, 32 kHz mono. (2) WinCE running from SDRAM; playing mp3 file at 128 kbit/s, stereo. (3) WinCE running from SDRAM; no application running. Fig 5. Core current versus core frequency for WinCE applications core frequency (MHz) 40 120 200 280 002aae762 80 40 120 160 IDD(run) (mA) 0 (1) (2) (3) HCLK = 133 MHz HCLK = 72 MHz VDD_CORE = 1.2 V VDD_CORE = 1.35 V LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 55 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10.5 ADC static characteristics [1] Conditions: VSSA = 0 V (on pin VSS_AD); VDDA(3V3) = 3.3 V (on pin VDD_AD). [2] The ADC is monotonic; there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 6. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 6. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 6. [6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 6. [7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 6. Table 10. ADC static characteristics VDDA(3V3) = 3.3 V; Tamb = 25C unless otherwise specified; ADC clock frequency 4.5 MHz. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA(3V3) V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2][3] - 0.5 1 LSB EL(adj) integral non-linearity [1][4] - 0.6 1 LSB EO offset error [1][5] - 1 3 LSB EG gain error [1][6] - 0.3 0.6 % ET absolute error [1][7] - 4 LSB Rvsi voltage source interface resistance - - 40 k LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 56 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 6. ADC characteristics 002aae434 1023 1022 1021 1020 1019 (2) (1) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 LSB (ideal) code out VDDA(3V3) − VSSA 1024 offset error EO gain error EG offset error EO VIA (LSBideal) 1 LSB = LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 57 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11. Dynamic characteristics 11.1 Clocking and I/O port pins [1] Parameters are valid over operating temperature range unless otherwise specified. [2] After supply voltages are stable [3] Supplied by an external crystal. 11.2 Static memory controller Table 11. Dynamic characteristics Tamb = 40 C to +85 C, unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit Reset tw(RESET)ext external RESET pulse width [2] 10 - - ms External clock fext external clock frequency [3]1 13 20 MHz Port pins tr rise time - 5 - ns tf fall time - 5 - ns Table 12. Dynamic characteristics: static external memory interface CL = 25 pF, Tamb = 20C, VDD(EMC) = 1.8 V, 2.5 V, or 3.3 V. Symbol Parameter Notes Min Typ Max Unit Common to read and write cycles TCLCL clock cycle time [1] 7.5 9.6 - ns tCSLAV CS LOW to address valid time - 0 - ns Read cycle parameters tOELAV OE LOW to address valid time [2]- 0 WAITOEN  TCLCL - ns tBLSLAV BLS LOW to address valid time [2]- 0 WAITOEN  TCLCL - ns tCSLOEL CS LOW to OE LOW time - 0 + WAITOEN  TCLCL - ns tCSLBLSL CS LOW to BLS LOW time [2] - 0 + WAITOEN  TCLCL - ns tOELOEH OE LOW to OE HIGH time [2][3]- (WAITRD WAITOEN + 1)  TCLCL - ns tBLSLBLSH BLS LOW to BLS HIGH time [2][3]- (WAITRD WAITOEN + 1)  TCLCL - ns tsu(DQ) data input/output set-up time [6]- 8.4 - ns th(DQ) data input/output hold time [6]- 0 - ns tCSHOEH CS HIGH to OE HIGH time - 0 - ns tCSHBLSH CS HIGH to BLS HIGH time - 0 - ns tOEHANV OE HIGH to address invalid time - 1  TCLCL - ns tBLSHANV BLS HIGH to address invalid time - 1  TCLCL - ns Write cycle parameters tCSLDV CS LOW to data valid time - 0 - ns tCSLWEL CS LOW to WE LOW time [4]- (WAITWEN+1) TCLCL - ns tCSLBLSL CS LOW to BLS LOW time [4]- (WAITWEN+ 1)  TCLCL - ns tWELDV WE LOW to data valid time [4]- 0 (WAITWEN + 1)  TCLCL - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 58 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] TCLCL = 1/HCLK [2] Refer to the LPC32x0 User manual EMCStaticWaitOen0-3 register for the programming of WAITOEN value. [3] Refer to the LPC32x0 User manual EMCStaticWaitRd0-3 register for the programming of WAITRD value. [4] Refer to the LPC32x0 User manual EMCStaticWaitWen0-3 register for the programming of WAITWEN value. [5] Refer to the LPC32x0 User manual EMCStaticWaitWr0-3 register for the programming of WAITWR value. [6] Earliest of CS HIGH, OE HIGH, address change to data invalid. tWELWEH WE LOW to WE HIGH time [4][5]- (WAITWR WAITWEN + 1)  TCLCL - ns tBLSLBLSH BLS LOW to BLS HIGH time [4][5]- (WAITWR WAITWEN + 1)  TCLCL - ns tWEHANV WE HIGH to address invalid time - 1  TCLCL - ns tWEHDNV WE HIGH to data invalid time - 1  TCLCL - ns tBLSHANV BLS HIGH to address invalid time - 1  TCLCL - ns tBLSHDNV BLS HIGH to data invalid time - 1  TCLCL - ns Table 12. Dynamic characteristics: static external memory interface …continued CL = 25 pF, Tamb = 20C, VDD(EMC) = 1.8 V, 2.5 V, or 3.3 V. Symbol Parameter Notes Min Typ Max Unit Fig 7. External memory read access EMC_CS[3:0] EMC_A[23:0] EMC_D[31:0] EMC_OE EMC_BLS[3:0] tCSLAV tOELAV tOELOEH tCSLOEL tsu(DQ) th(DQ) tCSHOEH tOEHANV 002aae402 tBLSLAV tCSHBLSH tBLSLBLSH tCSLBLSL tBLSHANV LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 59 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 8. External memory write access EMC_A[23:0] EMC_D[31:0] tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tWEHANV tBLSHANV tWEHDNV tBLSHDNV 002aae469 tCSLAV EMC_CS[3:0] tBLSLBLSH EMC_BLS[3:0] EMC_WR LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 60 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.3 SDR SDRAM Controller [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC = 3.3 V, VDD_CORE = 1.2 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual). [3] All min or max values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC = 3.3 V, VDD_CORE = 1.2 V. [4] foper = 1/tCK. [5] Applies to signals: EMC_DQM[3:0], EMC_DYCS[1:0], EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0]. [6] CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External Memory Controller (EMC) chapter in LPC32x0 User manual. Table 13. EMC SDR SDRAM memory interface dynamic characteristics CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified.[1][3] Symbol Parameter Min Typical[2] Max Unit foper operating frequency [4] 104 133 MHz tCK clock cycle time 7.5 9.6 - ns tCL CK LOW-level width - 4.8 - ns tCH CK HIGH-level width - 4.8 - ns td(V)ctrl control valid delay time [5][6] - (CMD_DLY  0.25) + 2.7 ns th(ctrl) control hold time [5][6] (CMD_DLY  0.25) + 1.2 - ns td(AV) address valid delay time [6] - (CMD_DLY  0.25) + 3.2 ns th(A) address hold time [6] (CMD_DLY  0.25) + 1.2 - ns td(QV) data output valid delay time [6] - (CMD_DLY  0.25) + 3.5 ns th(Q) data output hold time [6] (CMD_DLY  0.25) + 1.2 - ns tsu(D) data input set-up time - 0.6 - ns th(D) data input hold time - 0.9 - ns tQZ data output high-impedance time - -  tCK ns Fig 9. SDR SDRAM signal timing 002aae420 EMC_CLK output signal (O) input signal (I) td(V)ctrl, td(AV), td(QV) th(ctrl), th(Q), th(A) tsu(D) th(D) tCK tCH tCL tQZ LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 61 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.4 DDR SDRAM controller [1] All values valid for EMC pads set to fast slew rate at 1.8 V unless otherwise specified (see SDRAMCLK_CTRL register in the LPC32x0 User manual). [2] CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External Memory Controller (EMC) chapter in LPC32x0 User manual. [3] Applies to signals EMC_DQM[3:0], EMC_DYCS[1:0], EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0]. [4] DQS_DELAY, see LPC32x0 User manual, External Memory Controller Chapter, Section 8 DDR DQS delay calibration for details on configuring this value. [5] Test conditions for measurements: Tamb = 40 C to +85 C; operating frequency range foper = 52 MHz to 133 MHz; EMC_DQM[3:0] and EMC_D[31:0] driving 2 inches of 50  characteristic impedance trace with 10 pF capacitive load; no external source series termination resistors used. EMC pads set to fast slew rate at 1.8 V or 2.5 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual). Table 14. EMC DDR SDRAM memory interface dynamic characteristics[1] CL = 25 pF, Tamb = 25C, unless otherwise specified. Symbol Parameter Conditions Min Typical Max Unit foper operating frequency - 104 133 MHz tCK clock cycle time 7.5 9.6 - ns tCL CK LOW-level width - 0.5  tCK - ns tCH CK HIGH-level width - 0.5  tCK - ns td(V)ctrl control valid delay time [2][3] - (CMD_DLY  0.25) + 1.5 - ns th(ctrl) control hold time [2][3] - (CMD_DLY  0.25)  1.5 - ns td(AV) address valid delay time [2] - (CMD_DLY  0.25) + 1.5 - ns th(A) address hold time [2] - (CMD_DLY  0.25)  1.5 - ns tsu(Q) data output set-up time EMC_D[31:0] and EMC_DQM[3:0] to EMC_DQS[1:0] out [5] 0.08  tCK 0.15  tCK 0.25  tCK ns th(Q) data output hold time EMC_D[31:0] and EMC_DQM[3:0] to EMC_DQS[1:0] out [5] 0.25  tCK 0.35  tCK 0.42  tCK ns tDQSH DQS HIGH time for WRITE command - 0.5  tCK - ns tDQSL DQS LOW time for WRITE command - 0.5  tCK - ns tDQSS WRITE command to first DQS latching transition time for DQS out - tCK + 0.7 - ns tDSS DQS falling edge to CK set-up time for DQS in - 0.5  tCK - ns tDSH DQS falling edge hold time from CK for DQS in - 0.5  tCK - ns td(DQS) DQS delay time for DQS in [4] - DQS_DELAY - ns tsu(D) data input set-up time - 0.3 - ns th(D) data input hold time - 0.5 - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 62 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 10. DDR control timing parameters EMC_CLK EMC control and address signals 002aae436 tCK tCH tCL td(AV); td(V)ctrl th(A); th(ctl) valid Fig 11. DDR write timing parameters command EMC_D[31:0], EMC_DQM[3:0] tDQSS tDQSL tDQSH th(Q) EMC_DQS[1:0] EMC_CLK 002aae437 WRITE tsu(Q) tDSS tDSH (1) The delay of the EMC_DQS[1:0] signal is determined by the DQS_DELAY settings. See LPC32x0 User manual, External Memory Controller Chapter, section DDR DQS delay calibration for details on configuring this value. Fig 12. DDR read timing parameters EMC_CLK command EMC_D[31:0] tsu(D) EMC_DQS[1:0] 002aae438 th(D) READ delayed EMC_DQS[1:0](1) td(DQS) LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 63 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.5 USB controller [1] Parameters are valid over operating temperature range unless otherwise specified. 11.6 Secure Digital (SD) card interface [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Table 15. Dynamic characteristics USB digital I/O pins VDD(IO) = 3.3 V; Tamb = 40 C to +85 C, unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit tTIO bus turnaround time (I/O) OE_N/INT_N to DAT/VP and SE0/VM - 7 - ns tTOI bus turnaround time (O/I) OE_N/INT_N to DAT/VP and SE0/VM - 0 - ns Fig 13. USB bus turnaround time 002aae440 USB_DAT_VP tTIO tTOI USB_OE_TP USB_SE0_VM input output input Table 16. Dynamic characteristics: SD card pin interface Tamb = 40 C to +85 C for industrial applications; VDD(IO) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit Tcy(clk) clock cycle time on pin MS_SCLK; Data transfer mode - - 25 MHz on pin MS_SCLK; Identification mode - - 400 kHz tsu(D) data input set-up time on pins MS_BS, MS_DIO[3:0] as inputs - 2.7 - ns th(D) data input hold time on pins MS_BS, MS_DIO[3:0] as inputs - 0 - ns td(QV) data output valid delay time on pins MS_BS, MS_DIO[3:0] as outputs - 9.7 - ns th(Q) data output hold time on pins MS_BS, MS_DIO[3:0] as outputs - 7.7 - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 64 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.7 MLC NAND flash memory controller [1] THCLK = 1/HCLK [2] CEAD = bitfield TCEA_DELAY[1:0] in register MLC_TIME_REG[25:24] [3] WL = bitfield WR_LOW[3:0] in register MLC_TIME_REG[3:0] [4] WH = bitfield WR_HIGH[3:0] in register MLC_TIME_REG[7:4] [5] RL = bitfield RD_LOW[3:0] in register MLC_TIME_REG[11:8] [6] RH = bitfield RD_HIGH [3:0] in register MLC_TIME_REG[15:12] [7] RHZ = bitfield NAND_TA[2:0] in register MLC_TIME_REG[18:16] [8] BD = bitfield BUSY_DELAY[4:0] in register MLC_TIME_REG[23:19] Fig 14. SD card pin interface timing 002aae441 MS_SCLK MS_DIO[3:0](O) MS_DIO[3:0] (I) td(QV) tsu(D) th(D) Tcy(clk) th(Q) MS_BS (O) MS_BS (I) Table 17. Dynamic characteristics of the MLC NAND flash memory controller Tamb = 40 C to +85 C. Symbol Parameter Min Typ Max Unit tCELREL CE LOW to RE LOW time [1][2] - THCLK  CEAD - ns tRC RE cycle time [1][5][6] - THCLK  (RL + 1) + THCLK  (RH  RL) - ns tREH RE HIGH hold time [1][5][6] - THCLK  (RH  RL) - ns tRHZ RE HIGH to output high-impedance time [1][5][7] - THCLK  (RH  RL) + THCLK  RHZ - ns tRP RE pulse width [1][5] - THCLK  (RL + 1) - ns tREHRBL RE HIGH to R/B LOW time [1][8] - THCLK  BD - ns tWB WE HIGH to R/B LOW time [1][8] - THCLK  BD - ns tWC WE cycle time [1][3][4] - THCLK  (WL + 1) + THCLK  (WH  WL) - ns tWH WE HIGH hold time [1][3][4] - THCLK  (WH  WL) - ns tWP WE pulse width [1][3] - THCLK  (WL + 1) - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 65 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.8 SLC NAND flash memory controller Fig 15. MLC NAND flash controller write timing (writing to NAND flash) Fig 16. MLC NAND flash controller read timing (reading from NAND flash) tWB FLASH_IO[7:0] FLASH_WR tWP tWC FLASH_RDY (R/B) FLASH_CE D0 D1 Dn 10h tWH 002aae442 FLASH_IO[7:0] tRP tREH tRC FLASH_RD FLASH_CE tCELREL D0 D1 D2 D3 tRHZ 002aae443 Table 18. Dynamic characteristics of SLC NAND flash memory controller Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit tALS ALE set-up time read [1][2][4][6] - THCLK  (Rsu + Rw) - ns write - THCLK  (Wsu + Ww) - ns tALH ALE hold time read [1][7] - THCLK  Rh - ns write - THCLK  Wh - ns tAR ALE to RE delay time read [1][2][6] - THCLK  Rsu - ns write - THCLK  Wsu - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 66 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers tCEA CE access time read [1][2][4][6][8] - THCLK  (Rsu + Rw) - ns write - THCLK  (Wsu + Ww) - ns tCS CE set-up time read [1][2][4][6][8] - THCLK  (Rsu + Rw) - ns write - THCLK  (Wsu + Ww) - ns tCH CE hold time read [1][3] - THCLK  Rh - ns write - THCLK  Wh - ns tCLS CLE set-up time read [1][2][4][6][8] - THCLK  (Rsu + Rw) - ns write - THCLK  (Wsu + Ww) - ns tCLH CLE hold time read [1][3] - THCLK  Rh - ns write - THCLK  Wh - ns tCLR CLE to RE delay time read [1][2][6] - THCLK  Rsu - ns write - THCLK  Wsu - ns tDH data hold time output from NAND controller; read [1][3][7] - THCLK  Rh - ns output from NAND controller; write - THCLK  Wh - ns tDS data set-up time output from NAND controller; read [1][2][4][6][8] - THCLK  (Rsu + Rw) - ns output from NAND controller; write - THCLK  (Wsu + Ww) - tIR output high-impedance to RE LOW time read [1][2][6] - THCLK  Rsu - ns write - THCLK  Wsu - ns tRC RE cycle time read [1][2] - THCLK  (Rsu + Rw + Rh) - ns tREA RE access time read [1][4] - THCLK  Rw - ns tREH RE high hold time read [1][2][3] - THCLK  (Rsu + Rh) - ns tRHOH RE HIGH to output hold time input hold for flash controller; read - 0 - - input hold for flash controller; write - 0 - - tRHZ RE HIGH to output high-impedance time read [1] - THCLK  Rh - ns tRP RE pulse width read [1][4] - THCLK  Rw - ns tRR ready to RE LOW time read [1][2][3] - THCLK  Rsu - ns tWB WE HIGH to R/B LOW time write [1][7][9] - (THCLK  Wh) + (2  THCLK  Wb) - ns tWC WE cycle time write [1][6][7][8] - THCLK  (Wsu + Ww + Wh) - ns Table 18. Dynamic characteristics of SLC NAND flash memory controller …continued Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 67 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] THCLK = 1/HCLK [2] Rsu = bitfield R_SETUP[3:0] in register SLC_TAC[3:0] for reads [3] Rh = bitfield R_HOLD[3:0] in register SLC_TAC[7:4] for reads [4] Rw = bitfield R_WIDTH[3:0] in register SLC_TAC[11:8] for reads [5] Rb = bitfield R_RDY[3:0] in register SLC_TAC[15:12] for reads [6] Wsu = bitfield W_SETUP[3:0] in register SLC_TAC[19:16] for writes [7] Wh = bitfield W_HOLD[3:0] in register SLC_TAC[23:20] for writes [8] Ww = bitfield W_WIDTH[3:0] in register SLC_TAC[27:24] for writes [9] Wb = bitfield W_RDY[3:0] in register SLC_TAC[31:28] for writes tWH WE HIGH hold time write [1][6][7] - THCLK  (Wsu + Wh) - ns tWHR WE HIGH to RE LOW time write [1][7][9] - (THCLK  Wh) + (2  THCLK  Wb) - ns tWP WE pulse width write [1][8] - THCLK  Ww - ns tREHRBL RE HIGH to R/B LOW time write [1][3][5] - (THCLK  Rh) + (2  THCLK  Rb) - ns Table 18. Dynamic characteristics of SLC NAND flash memory controller …continued Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit Fig 17. MLC NAND flash memory write timing (writing to NAND flash) command tDS tDH tWB FLASH_IO[7:0] address tDS tDH tALS tALH tDS tDH tWP tWH tWC tCS tCH tCH tCLS tCLH command address data D0 D1 Dn tALS tCLH tALS tALH tWP tWP tWH tCLS tCS 002aae444 FLASH_CE FLASH_CLE FLASH_WR FLASH_ALE FLASH_RDY LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 68 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 18. MLC NAND Flash memory read timing (reading from NAND flash) command tDS tDH tWB FLASH_IO[7:0] address tDS tDH tALS tALH tDS tDH tRP tREH tRC tRR tAR tCS tCH tCEA tCLR tCLS tCLH command address data tCOH tREA D0 D1 D2 D3 tRHZ tRHOH tALS tALH tCLS tCS tWP tWP tWH 002aae445 FLASH_ALE FLASH_CLE FLASH_RDY FLASH_WR FLASH_RD FLASH_CE LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 69 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.9 SPI and SSP Controller 11.9.1 SPI [1] THCLK = period time of SPI IP block input clock (HCLK) Fig 19. MLC NAND flash memory status timing tCS tCH tCEA 70 h tDS tDH status tRHOH tCLS tCLH command data tCLR tCOH tREA tIR FLASH_IO[7:0] tWHR tWP tRHZ FLASH_CLE FLASH_WR FLASH_CE FLASH_RD 002aae446 Table 19. Dynamic characteristics of SPI pins on SPI master controller Tamb = 40 C to +85 C. Symbol Parameter Min Typ Max Unit Common to SPI1 and SPI2 TSPICYC SPI cycle time [1] 2  THCLK - 256  THCLK ns SPI1 tSPIDSU SPI data set-up time - 6 - ns tSPIDH SPI data hold time - 0 - ns tSPIDV SPI enable to output data valid time - 2 - ns tSPIOH SPI output data hold time - 0 - ns SPI2 tSPIDSU SPI data set-up time - 10 - ns tSPIDH SPI data hold time - 0 - ns tSPIDV SPI enable to output data valid time - 2 - ns tSPIOH SPI output data hold time - 0 - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 70 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.9.2 Timing diagrams for SPI and SSP (in SPI mode) Fig 20. SPI master timing (CPHA = 0) Fig 21. SPI master timing (CPHA = 1) 002aae457 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH DATA VALID DATA VALID tSPIOH DATA VALID DATA VALID tSPIQV SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or MOSI0/1 SPI1/2_DATAIN or MISO0/1 002aae454 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH DATA VALID DATA VALID SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or MOSI0/1 SPI1/2_DATAIN or MISO0/1 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 71 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 22. SPI slave timing (CPHA = 0) Fig 23. SPI slave timing (CPHA = 1) 002aae458 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH DATA VALID DATA VALID SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or MOSI0/1 SPI1/2_DATAIN or MISO0/1 002aae459 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH DATA VALID DATA VALID SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or MOSI0/1 SPI1/2_DATAIN or MISO0/1 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 72 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 12. Package outline Fig 24. Package outline SOT1048-1 (TFBGA296) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT1048-1 MO-216 SOT1048-1 07-10-19 07-11-02 UNIT A max mm 1.2 0.4 0.3 0.80 0.65 15.1 14.9 15.1 14.9 0.8 13.6 0.15 0.08 0.1 A1 DIMENSIONS (mm are the original dimensions) TFBGA296: plastic thin fine-pitch ball grid array package; 296 balls 0 5 10 mm scale A2 b 0.5 0.4 D E e e1 e2 13.6 v w y 0.12 y1 C y1 C y X A B C D E F H K G L J M N P R T U 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 18 17 b e2 e1 e e 1/2 e 1/2 e ∅ v M C A B ∅ w M C ball A1 index area V B A ball A1 index area D E detail X A A2 A1 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 73 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 13. Abbreviations Table 20. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BSDL Boundary Scan Description Language CISC Complex Instruction Set Computer DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory DMA Direct Memory Access DSP Digital Signal Processing ETM Embedded Trace Macrocell FAB Fast Access Bus FIFO First In, First Out FIQ Fast Interrupt Request GPIO General Purpose Input/Output I/O Input/Output IRQ Interrupt Request HS High-Speed IrDA Infrared Data Association JTAG Joint Test Action Group LCD Liquid Crystal Display MAC Media Access Control MIIM Media Independent Interface Management OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLL Phase-Locked Loop PWM Pulse Width Modulator RAM Random Access Memory RMII Reduced Media Independent Interface SE0 Single Ended Zero SDR SDRAM Single Data Rate Synchronous Dynamic Random Access Memory SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TFT Thin Film Transistor TTL Transistor-Transistor Logic STN Super Twisted Nematic LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 74 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus VFP Vector Floating Point processor Table 20. Abbreviations …continued Acronym Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 75 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 14. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC3220_30_40_50 v.2 20111020 Product data sheet - LPC3220_30_40_50 v.1 Modifications: • Corrected pin functions for pin T14 (ADIN1/TS_XM) and pin U15 (ADIN0/TS_YM) in Table 3 and Table 4. • Power domain for pin PLL397_LOOP corrected in Table 4. • Power supply domain for pins SYSX_IN and SYSX_OUT pins corrected in Table 4. • Power supply domain for pin VDD_OSC corrected in Table 4. • Description of DEBUG pin updated in Table 4. • Added Table 6 “Supply domains”. • Changed VESD to 2500 V (HBM) and 1000 V (CDM) in Table 7. • Power consumption for HCLK, USB, and ADC added in Table 8. • Parameter IDD(RTC) updated in Table 8. • Parameter VDD(EMC) table notes updated in Table 8. • Input current for bus keeper inputs added in Table 8. • Added power consumption data (Table 8, Table 9, and Figure 5). • Static memory controller: added tsu(DQ) value in Table 12. • DDR SDRAM controller: updated tDQSS value in Table 14. • Minimum and maximum characterization data added for parameters tsu(Q) and th(Q) over temperature range 40 C to +85 C (see Table 14). • DDR SDRAM characteristics extended to maximum operating frequency foper = 133 MHz (see Table 14). • Parameters tWB, tWHR, and tREHRBL updated in Table 18. • Changed data sheet status to Product data sheet. • Parts LPC3220FET296/01, LPC3230FET296/01, LPC3240FET296/01, LPC3250FET296/01 added. LPC3220_30_40_50 v.1 20090206 Preliminary data sheet - - LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 76 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 15. Legal information 15.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 77 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 78 of 79 continued >> NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 24 7.1 CPU and subsystems . . . . . . . . . . . . . . . . . . . 24 7.1.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.2 Vector Floating Point (VFP) coprocessor . . . . 24 7.1.3 Emulation and debugging. . . . . . . . . . . . . . . . 24 7.1.3.1 Embedded ICE . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.3.2 Embedded trace buffer . . . . . . . . . . . . . . . . . . 25 7.2 AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.1 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.2 FAB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 Physical memory map . . . . . . . . . . . . . . . . . . 26 7.4 Internal memory . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.1 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.2 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5 External memory interfaces . . . . . . . . . . . . . . 28 7.5.1 NAND flash controllers . . . . . . . . . . . . . . . . . . 28 7.5.1.1 Multi-Level Cell (MLC) NAND flash controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5.1.2 Single-Level Cell (SLC) NAND flash controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5.2 SD card controller. . . . . . . . . . . . . . . . . . . . . . 29 7.5.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5.3 External memory controller. . . . . . . . . . . . . . . 29 7.6 AHB master peripherals . . . . . . . . . . . . . . . . . 30 7.6.1 General Purpose DMA (GPDMA) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6.2 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.3 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.3.1 USB device controller . . . . . . . . . . . . . . . . . . . 31 7.6.3.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 32 7.6.3.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 32 7.6.4 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 33 7.6.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.7 System functions . . . . . . . . . . . . . . . . . . . . . . 34 7.7.1 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 34 7.7.2 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.3 Millisecond timer . . . . . . . . . . . . . . . . . . . . . . 34 7.7.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.4 Clocking and power control features . . . . . . . 35 7.7.4.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.2 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.3 PLLs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.4 Power control modes . . . . . . . . . . . . . . . . . . . 36 7.7.4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.8 Communication peripheral interfaces . . . . . . 36 7.8.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.8.1.1 Standard UARTs. . . . . . . . . . . . . . . . . . . . . . . 37 7.8.1.2 High-speed UARTs . . . . . . . . . . . . . . . . . . . . 37 7.8.2 SPI serial I/O controller . . . . . . . . . . . . . . . . . 37 7.8.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8.3 SSP serial I/O controller. . . . . . . . . . . . . . . . . 38 7.8.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8.4 I2C-bus serial I/O controller . . . . . . . . . . . . . . 38 7.8.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.8.5 I2S-bus audio controller . . . . . . . . . . . . . . . . . 39 7.8.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.9 Other peripherals . . . . . . . . . . . . . . . . . . . . . . 40 7.9.1 General purpose parallel I/O . . . . . . . . . . . . . 40 7.9.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.9.2 Keyboard scanner . . . . . . . . . . . . . . . . . . . . . 41 7.9.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9.3 Touch screen controller and 10-bit ADC . . . . 41 7.9.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9.4 Real-Time Clock (RTC) and battery RAM . . . . . . . . . . . . . . . . . . . . . . 41 7.9.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.5 Enhanced 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.6 High-speed timer . . . . . . . . . . . . . . . . . . . . . . 43 7.9.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9.7 Pulse Width Modulators (PWMs) . . . . . . . . . . 43 7.9.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9.8 Motor control pulse width modulator . . . . . . . 43 7.9.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 Basic architecture . . . . . . . . . . . . . . . . . . . . . . 44 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Static characteristics . . . . . . . . . . . . . . . . . . . 46 10.1 Minimum core voltage requirements . . . . . . . 53 10.2 Power supply sequencing . . . . . . . . . . . . . . . 53 10.3 Power consumption per peripheral . . . . . . . . 53 10.4 Power consumption in Run mode . . . . . . . . . 54 10.5 ADC static characteristics . . . . . . . . . . . . . . . 55 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 October 2011 Document identifier: LPC3220_30_40_50 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 57 11.1 Clocking and I/O port pins . . . . . . . . . . . . . . . 57 11.2 Static memory controller . . . . . . . . . . . . . . . . . 57 11.3 SDR SDRAM Controller . . . . . . . . . . . . . . . . . 60 11.4 DDR SDRAM controller . . . . . . . . . . . . . . . . . 61 11.5 USB controller . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6 Secure Digital (SD) card interface . . . . . . . . . 63 11.7 MLC NAND flash memory controller. . . . . . . . 64 11.8 SLC NAND flash memory controller . . . . . . . . 65 11.9 SPI and SSP Controller . . . . . . . . . . . . . . . . . 69 11.9.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.9.2 Timing diagrams for SPI and SSP (in SPI mode) . . . . . . . . . . . . . . . . . . . . . . . . . 70 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 72 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 73 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 75 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 76 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 76 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 77 16 Contact information. . . . . . . . . . . . . . . . . . . . . 77 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1. General description The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory and 4 kB of SRAM. The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins. 2. Features and benefits  System:  ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port.  ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  System tick timer.  Serial Wire Debug (SWD) and JTAG boundary scan modes supported.  Micro Trace Buffer (MTB) supported.  Memory:  Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.  Up to 4 kB SRAM.  ROM API support:  Boot loader.  USART drivers.  I2C drivers.  Power profiles.  Flash In-Application Programming (IAP) and In-System Programming (ISP).  Digital peripherals:  High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and glitch filter.  High-current source output driver (20 mA) on four pins.  High-current sink driver (20 mA) on two true open-drain pins.  GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs.  Switch matrix for flexible configuration of each I/O pin function. LPC81xM 32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and 4 kB SRAM Rev. 4.3 — 22 April 2014 Product data sheet LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 2 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller  State Configurable Timer/PWM (SCTimer/PWM) with input and output functions (including capture and match) assigned to pins through the switch matrix.  Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.  Self Wake-up Timer (WKT) clocked from either the IRC or a low-power, low-frequency internal oscillator.  CRC engine.  Windowed Watchdog timer (WWDT).  Analog peripherals:  Comparator with internal and external voltage references with pin functions assigned or enabled through the switch matrix.  Serial interfaces:  Three USART interfaces with pin functions assigned through the switch matrix.  Two SPI controllers with pin functions assigned through the switch matrix.  One I2C-bus interface with pin functions assigned through the switch matrix.  Clock generation:  12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be used as a system clock.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  10 kHz low-power oscillator for the WKT.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input CLKIN, or the internal RC oscillator.  Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator.  Power control:  Integrated PMU (Power Management Unit) to minimize power consumption.  Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode.  Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI, and I2C peripherals.  Timer-controlled self wake-up from Deep power-down mode.  Power-On Reset (POR).  Brownout detect.  Unique device serial number for identification.  Single power supply.  Operating temperature range 40 °C to 105 °C except for the DIP8 package, which is available for a temperature range of 40 °C to 85 °C.  Available as DIP8, TSSOP16, SO20, TSSOP20, and XSON16 package. 3. Applications  8/16-bit applications  Lighting  Consumer  Motor control  Climate control  Fire and security applications LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 3 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 4. Ordering information 4.1 Ordering options Table 1. Ordering information Type number Package Name Description Version LPC810M021FN8 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT097-2 LPC811M001JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101JD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC812M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 LPC812M101JTB16 XSON16 plastic extremely thin small outline package; no leads; 16 terminals; body 2.5  3.2  0.5 mm SOT1341-1 Table 2. Ordering options Type number Flash/kB SRAM/kB USART I2C-bus SPI Comparator GPIO Package LPC810M021FN8 4 1 2 1 1 1 6 DIP8 LPC811M001JDH16 8 2 2 1 1 1 14 TSSOP16 LPC812M101JDH16 16 4 3 1 2 1 14 TSSOP16 LPC812M101JD20 16 4 2 1 1 1 18 SO20 LPC812M101JDH20 16 4 3 1 2 1 18 TSSOP20 LPC812M101JTB16 16 4 3 1 2 1 14 XSON16 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 4 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 5. Marking The LPC81xM devices typically have the following top-side marking: LPC81x xxxxx xxxxxxxx xxYWWxR[x] The last two letters in the last line (field ‘xR’) identify the boot code version and device revision. Field ‘Y’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Remark: On the TSSOP16 package, the last line includes only the date code xxYWW. Table 3. Device revision table Revision identifier (xR) Revision description ‘1A’ Initial device revision with boot code version 13.1 ‘2A’ Device revision with boot code version 13.2 ’4C’ Device revision with boot code version 13.4 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 5 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 6. Block diagram Fig 1. LPC81xM block diagram 􀀶􀀵􀀤􀀰 􀀔􀀒􀀕􀀒􀀗􀀃􀁎􀀥 􀀤􀀵􀀰 􀀦􀀲􀀵􀀷􀀨􀀻􀀐􀀰􀀓􀀎 􀀷􀀨􀀶􀀷􀀒􀀧􀀨􀀥􀀸􀀪 􀀬􀀱􀀷􀀨􀀵􀀩􀀤􀀦􀀨 􀀩􀀯􀀤􀀶􀀫 􀀗􀀒􀀛􀀒􀀔􀀙􀀃􀁎􀀥 􀀫􀀬􀀪􀀫􀀐􀀶􀀳􀀨􀀨􀀧 􀀪􀀳􀀬􀀲 􀀤􀀫􀀥􀀃􀀷􀀲􀀃􀀤􀀳􀀥 􀀥􀀵􀀬􀀧􀀪􀀨􀀃 􀀦􀀯􀀲􀀦􀀮 􀀪􀀨􀀱􀀨􀀵􀀤􀀷􀀬􀀲􀀱􀀏 􀀳􀀲􀀺􀀨􀀵􀀃􀀦􀀲􀀱􀀷􀀵􀀲􀀯􀀏 􀀶􀀼􀀶􀀷􀀨􀀰􀀃 􀀩􀀸􀀱􀀦􀀷􀀬􀀲􀀱􀀶 􀀵􀀨􀀶􀀨􀀷􀀏􀀃􀀦􀀯􀀮􀀬􀀱 􀁆􀁏􀁒􀁆􀁎􀁖􀀃􀁄􀁑􀁇􀀃 􀁆􀁒􀁑􀁗􀁕􀁒􀁏􀁖 􀀯􀀳􀀦􀀛􀀔􀁛􀀰 􀁄􀁄􀁄􀀐􀀓􀀓􀀘􀀚􀀗􀀙 􀁖􀁏􀁄􀁙􀁈 􀁖􀁏􀁄􀁙􀁈 􀁖􀁏􀁄􀁙􀁈 􀀵􀀲􀀰 􀁖􀁏􀁄􀁙􀁈 􀀦􀀵􀀦 􀁖􀁏􀁄􀁙􀁈 􀀳􀀬􀀱􀀃􀀬􀀱􀀷􀀨􀀵􀀵􀀸􀀳􀀷􀀶􀀒 􀀳􀀤􀀷􀀷􀀨􀀵􀀱􀀃􀀰􀀤􀀷􀀦􀀫 􀀤􀀫􀀥􀀐􀀯􀀬􀀷􀀨􀀃􀀃􀀥􀀸􀀶 􀀬􀀵􀀦 􀀺􀀧􀀲􀁖􀁆 􀀥􀀲􀀧 􀀳􀀲􀀵 􀀶􀀳􀀬􀀓 􀀸􀀶􀀤􀀵􀀷􀀓 􀀶􀀧􀀤 􀀶􀀦􀀯 􀀦􀀷􀀬􀀱􀁂􀀾􀀖􀀝􀀓􀁀 􀀦􀀷􀀲􀀸􀀷􀁂􀀾􀀖􀀝􀀓􀁀 􀀔􀀛􀀃􀁛􀀃 􀀳􀀬􀀲􀀓 􀀔􀀛􀀃􀁛􀀃 􀀺􀀺􀀧􀀷 􀀬􀀲􀀦􀀲􀀱 􀀳􀀰􀀸 􀀶􀀨􀀯􀀩 􀀺􀀤􀀮􀀨􀀐􀀸􀀳􀀃􀀷􀀬􀀰􀀨􀀵 􀀰􀀸􀀯􀀷􀀬􀀐􀀵􀀤􀀷􀀨􀀃􀀷􀀬􀀰􀀨􀀵 􀀶􀀳􀀬􀀔 􀀬􀀕􀀦􀀐􀀥􀀸􀀶 􀀶􀀦􀀷􀀬􀀰􀀨􀀵􀀒 􀀳􀀺􀀰 􀀶􀀺􀀬􀀷􀀦􀀫 􀀰􀀤􀀷􀀵􀀬􀀻 􀀦􀀲􀀰􀀳􀀤􀀵􀀤􀀷􀀲􀀵 􀀻􀀷􀀤􀀯􀀬􀀱 􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀤􀀦􀀰􀀳􀁂􀀲 􀀶􀀼􀀶􀀦􀀲􀀱 􀀵􀀻􀀧􀀏􀀃􀀦􀀷􀀶 􀀷􀀻􀀧􀀏􀀃􀀵􀀷􀀶 􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀕 􀀹􀀧􀀧􀀦􀀰􀀳 􀀶􀀦􀀮􀀏􀀃􀀶􀀶􀀨􀀯 􀀰􀀬􀀶􀀲􀀏􀀃􀀰􀀲􀀶􀀬 􀀶􀀦􀀮􀀏􀀃􀀶􀀶􀀨􀀯 􀀰􀀬􀀶􀀲􀀏􀀃􀀰􀀲􀀶􀀬 􀀤􀀯􀀺􀀤􀀼􀀶􀀐􀀲􀀱􀀃􀀳􀀲􀀺􀀨􀀵􀀃􀀧􀀲􀀰􀀤􀀬􀀱 􀀻􀀷􀀤􀀯 􀀶􀀦􀀯􀀮 􀀸􀀶􀀤􀀵􀀷􀀔 􀀵􀀻􀀧􀀏􀀃􀀦􀀷􀀶 􀀷􀀻􀀧􀀏􀀃􀀵􀀷􀀶 􀀶􀀦􀀯􀀮 􀀸􀀶􀀤􀀵􀀷􀀕 􀀵􀀻􀀧􀀏􀀃􀀦􀀷􀀶 􀀷􀀻􀀧􀀏􀀃􀀵􀀷􀀶 􀀶􀀦􀀯􀀮 􀀦􀀯􀀮􀀲􀀸􀀷 􀀶􀀺􀀦􀀯􀀮􀀏􀀃􀀶􀀺􀀧 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 6 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 7. Pinning information 7.1 Pinning Fig 2. Pin configuration DIP8 package (LPC810M021JN8) 􀀵􀀨􀀶􀀨􀀷􀀒􀀳􀀬􀀲􀀓􀁂􀀘 􀀳􀀬􀀲􀀓􀁂􀀓􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀷􀀧􀀲 􀀳􀀬􀀲􀀓􀁂􀀗􀀒􀀺􀀤􀀮􀀨􀀸􀀳􀀒􀀷􀀵􀀶􀀷 􀀹􀀶􀀶 􀀶􀀺􀀦􀀯􀀮􀀒􀀳􀀬􀀲􀀓􀁂􀀖􀀒􀀷􀀦􀀮 􀀹􀀧􀀧 􀀶􀀺􀀧􀀬􀀲􀀒􀀳􀀬􀀲􀀓􀁂􀀕􀀒􀀷􀀰􀀶 􀀳􀀬􀀲􀀓􀁂􀀔􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀕􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀷􀀧􀀬 􀁄􀁄􀁄􀀐􀀓􀀓􀀘􀀚􀀗􀀚 􀀔 􀀕 􀀖 􀀗 􀀙 􀀘 􀀛 􀀚 􀀧􀀬􀀳􀀛 Fig 3. Pin configuration TSSOP16 package (LPC811M001JDH16 and LPC812M101JDH16) 􀀷􀀶􀀶􀀲􀀳􀀔􀀙 􀀳􀀬􀀲􀀓􀁂􀀔􀀖 􀀳􀀬􀀲􀀓􀁂􀀓􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀷􀀧􀀲 􀀳􀀬􀀲􀀓􀁂􀀔􀀕 􀀳􀀬􀀲􀀓􀁂􀀙􀀒􀀹􀀧􀀧􀀦􀀰􀀳 􀀵􀀨􀀶􀀨􀀷􀀒􀀳􀀬􀀲􀀓􀁂􀀘 􀀳􀀬􀀲􀀓􀁂􀀚 􀀳􀀬􀀲􀀓􀁂􀀗􀀒􀀺􀀤􀀮􀀨􀀸􀀳􀀒􀀷􀀵􀀶􀀷 􀀹􀀶􀀶 􀀶􀀺􀀦􀀯􀀮􀀒􀀳􀀬􀀲􀀓􀁂􀀖􀀒􀀷􀀦􀀮 􀀹􀀧􀀧 􀀶􀀺􀀧􀀬􀀲􀀒􀀳􀀬􀀲􀀓􀁂􀀕􀀒􀀷􀀰􀀶 􀀳􀀬􀀲􀀓􀁂􀀛􀀒􀀻􀀷􀀤􀀯􀀬􀀱 􀀳􀀬􀀲􀀓􀁂􀀔􀀔 􀀳􀀬􀀲􀀓􀁂􀀜􀀒􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀳􀀬􀀲􀀓􀁂􀀔􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀕􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀷􀀧􀀬 􀁄􀁄􀁄􀀐􀀓􀀓􀀖􀀚􀀓􀀚 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀔􀀓 􀀜 􀀔􀀕 􀀔􀀔 􀀔􀀗 􀀔􀀖 􀀔􀀙 􀀔􀀘 Fig 4. Pin configuration SO20 package (LPC812M101JD20) 􀀶􀀲􀀕􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀚 􀀳􀀬􀀲􀀓􀁂􀀔􀀗 􀀳􀀬􀀲􀀓􀁂􀀔􀀖 􀀳􀀬􀀲􀀓􀁂􀀓􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀷􀀧􀀲 􀀳􀀬􀀲􀀓􀁂􀀔􀀕 􀀳􀀬􀀲􀀓􀁂􀀙􀀒􀀹􀀧􀀧􀀦􀀰􀀳 􀀵􀀨􀀶􀀨􀀷􀀒􀀳􀀬􀀲􀀓􀁂􀀘 􀀳􀀬􀀲􀀓􀁂􀀚 􀀳􀀬􀀲􀀓􀁂􀀗􀀒􀀺􀀤􀀮􀀨􀀸􀀳􀀒􀀷􀀵􀀶􀀷 􀀹􀀶􀀶 􀀶􀀺􀀦􀀯􀀮􀀒􀀳􀀬􀀲􀀓􀁂􀀖􀀒􀀷􀀦􀀮 􀀹􀀧􀀧 􀀶􀀺􀀧􀀬􀀲􀀒􀀳􀀬􀀲􀀓􀁂􀀕􀀒􀀷􀀰􀀶 􀀳􀀬􀀲􀀓􀁂􀀛􀀒􀀻􀀷􀀤􀀯􀀬􀀱 􀀳􀀬􀀲􀀓􀁂􀀔􀀔 􀀳􀀬􀀲􀀓􀁂􀀜􀀒􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀳􀀬􀀲􀀓􀁂􀀔􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀒􀀤􀀦􀀰􀀳􀁂􀀕􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀷􀀧􀀬 􀀳􀀬􀀲􀀓􀁂􀀔􀀙 􀀳􀀬􀀲􀀓􀁂􀀔􀀘 􀁄􀁄􀁄􀀐􀀓􀀓􀀖􀀚􀀘􀀙 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀜 􀀔􀀓 􀀔􀀕 􀀔􀀔 􀀔􀀗 􀀔􀀖 􀀔􀀙 􀀔􀀘 􀀔􀀛 􀀔􀀚 􀀕􀀓 􀀔􀀜 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 7 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 5. Pin configuration TSSOP20 package (LPC812M101JDH20) 􀀷􀀶􀀶􀀲􀀳􀀕􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀚 􀀳􀀬􀀲􀀓􀁂􀀔􀀗 􀀳􀀬􀀲􀀓􀁂􀀔􀀖 􀀳􀀬􀀲􀀓􀁂􀀓􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀷􀀧􀀲 􀀳􀀬􀀲􀀓􀁂􀀔􀀕 􀀳􀀬􀀲􀀓􀁂􀀙􀀒􀀹􀀧􀀧􀀦􀀰􀀳 􀀵􀀨􀀶􀀨􀀷􀀒􀀳􀀬􀀲􀀓􀁂􀀘 􀀳􀀬􀀲􀀓􀁂􀀚 􀀳􀀬􀀲􀀓􀁂􀀗􀀒􀀺􀀤􀀮􀀨􀀸􀀳􀀒􀀷􀀵􀀶􀀷 􀀹􀀶􀀶 􀀶􀀺􀀦􀀯􀀮􀀒􀀳􀀬􀀲􀀓􀁂􀀖􀀒􀀷􀀦􀀮 􀀹􀀧􀀧 􀀶􀀺􀀧􀀬􀀲􀀒􀀳􀀬􀀲􀀓􀁂􀀕􀀒􀀷􀀰􀀶 􀀳􀀬􀀲􀀓􀁂􀀛􀀒􀀻􀀷􀀤􀀯􀀬􀀱 􀀳􀀬􀀲􀀓􀁂􀀔􀀔 􀀳􀀬􀀲􀀓􀁂􀀜􀀒􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀳􀀬􀀲􀀓􀁂􀀔􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀕􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀷􀀧􀀬 􀀳􀀬􀀲􀀓􀁂􀀔􀀙 􀀳􀀬􀀲􀀓􀁂􀀔􀀘 􀁄􀁄􀁄􀀐􀀓􀀓􀀖􀀚􀀚􀀘 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀜 􀀔􀀓 􀀔􀀕 􀀔􀀔 􀀔􀀗 􀀔􀀖 􀀔􀀙 􀀔􀀘 􀀔􀀛 􀀔􀀚 􀀕􀀓 􀀔􀀜 Fig 6. Pin configuration XSON16 package (LPC812M101JTB16) terminal 1 index area XSON16 16 aaa-009570 Transparent top view 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 PIO0_13 PIO0_12 RESET/PIO0_5 PIO0_4/WAKEUP/TRST SWCLK/PIO0_3/TCK SWDIO/PIO0_2/TMS PIO0_11 PIO0_10 PIO0_0/ACMP_I1/TDO PIO0_6/VDDCMP PIO0_7 VSS VDD PIO0_8/XTALIN PIO0_9/XTALOUT PIO0_1/ACMP_I2/CLKIN/TDI LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 8 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 7.2 Pin description The pin description consists of two parts showing pin functions that are fixed to a certain package pin (see Table 4) and showing pin functions that can be assigned to any pin on the package through the switch matrix (see Table 5). The pin description table in Table 4 shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable between GPIO and the comparator inputs, SWD, RESET, and the XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only. Table 5 shows the the I2C, USART, SPI, and SCT pin functions, which can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions. The following exceptions apply: For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_11 and PIO0_10. Do not assign more than one output to any pin. However, more than one input can be assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is disabled. Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode. Table 4. Pin description table (fixed pins) Symbol SO20/ TSSOP20 TSSOP16 XSON16 DIP8 Type Reset state [1] Description PIO0_0/ACMP_I1/ TDO 19 16 16 8 [5] I/O I; PU PIO0_0 — General purpose digital input/output port 0 pin 0. In ISP mode, this is the USART0 receive pin U0_RXD. In boundary scan mode: TDO (Test Data Out). AI - ACMP_I1 — Analog comparator input 1. PIO0_1/ACMP_I2/ CLKIN/TDI 12 9 9 5 [5] I/O I; PU PIO0_1 — General purpose digital input/output pin. In boundary scan mode: TDI (Test Data In). ISP entry pin on chip versions 1A and 2A and on the DIP8 package (see Table 6). For these chip versions and packages, a LOW level on this pin during reset starts the ISP command handler. See PIO0_12 for all other packages. AI - ACMP_I2 — Analog comparator input 2. I - CLKIN — External clock input. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 9 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller SWDIO/PIO0_2/TMS 7 6 6 4 [2] I/O I; PU SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select). I/O - PIO0_2 — General purpose digital input/output pin. SWCLK/PIO0_3/ TCK 6 5 5 3 [2] I/O I; PU SWCLK — Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock). I/O - PIO0_3 — General purpose digital input/output pin. PIO0_4/WAKEUP/ TRST 5 4 4 2 [6] I/O I; PU PIO0_4 — General purpose digital input/output pin. In ISP mode, this is the USART0 transmit pin U0_TXD. In boundary scan mode: TRST (Test Reset). This pin triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. This pin should be pulled HIGH externally before entering Deep power-down mode. A LOW-going pulse as short as 50 ns causes the chip to exit Deep power-down mode and wakes up the part. RESET/PIO0_5 4 3 3 1 [4] I/O I; PU RESET — External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO or for any movable function if an external RESET function is not needed and the Deep power-down mode is not used. I - PIO0_5 — General purpose digital input/output pin. PIO0_6/VDDCMP 18 15 15 - [9] I/O I; PU PIO0_6 — General purpose digital input/output pin. AI - VDDCMP — Alternate reference voltage for the analog comparator. PIO0_7 17 14 14 - [2] I/O I; PU PIO0_7 — General purpose digital input/output pin. PIO0_8/XTALIN 14 11 11 - [8] I/O I; PU PIO0_8 — General purpose digital input/output pin. I - XTALIN — Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.95 V. PIO0_9/XTALOUT 13 10 10 - [8] I/O I; PU PIO0_9 — General purpose digital input/output pin. O - XTALOUT — Output from the oscillator circuit. PIO0_10 9 8 8 - [3]I IA PIO0_10 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification. PIO0_11 8 7 7 - [3]I IA PIO0_11 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification. Table 4. Pin description table (fixed pins) Symbol SO20/ TSSOP20 TSSOP16 XSON16 DIP8 Type Reset state [1] Description LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 10 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. [3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. Remark: If this pin is not available on the package, prevent it from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0 register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally. [4] See Figure 11 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [5] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep power-down mode, pulling this pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other purposes, if the WKT low power oscillator is enabled for waking up the part from Deep power-down mode. [7] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [9] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is disabled. PIO0_12 3 2 2 - [2] I/O I; PU PIO0_12 — General purpose digital input/output pin. ISP entry pin on the SO20/TSSOP20/TSSOP16/XSON16 packages starting with chip version 4C (see Table 6). A LOW level on this pin during reset starts the ISP command handler. See pin PIO0_1 for the DIP8 package and chip versions 1A and 2A. PIO0_13 2 1 1 - [2] I/O I; PU PIO0_13 — General purpose digital input/output pin. PIO0_14 20 - - - [7] I/O I; PU PIO0_14 — General purpose digital input/output pin. PIO0_15 11 - - - [7] I/O I; PU PIO0_15 — General purpose digital input/output pin. PIO0_16 10 - - - [7] I/O I; PU PIO0_16 — General purpose digital input/output pin. PIO0_17 1 - - - [7] I/O I; PU PIO0_17 — General purpose digital input/output pin. VDD 15 12 12 6 - - 3.3 V supply voltage. VSS 16 13 13 7 - - Ground. Table 4. Pin description table (fixed pins) Symbol SO20/ TSSOP20 TSSOP16 XSON16 DIP8 Type Reset state [1] Description Table 5. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) Function name Type Description U0_TXD O Transmitter output for USART0. U0_RXD I Receiver input for USART0. U0_RTS O Request To Send output for USART0. U0_CTS I Clear To Send input for USART0. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 11 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode. U1_TXD O Transmitter output for USART1. U1_RXD I Receiver input for USART1. U1_RTS O Request To Send output for USART1. U1_CTS I Clear To Send input for USART1. U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode. U2_TXD O Transmitter output for USART2. U2_RXD I Receiver input for USART2. U2_RTS O Request To Send output for USART2. U2_CTS I Clear To Send input for USART2. U2_SCLK I/O Serial clock input/output for USART2 in synchronous mode. SPI0_SCK I/O Serial clock for SPI0. SPI0_MOSI I/O Master Out Slave In for SPI0. SPI0_MISO I/O Master In Slave Out for SPI0. SPI0_SSEL I/O Slave select for SPI0. SPI1_SCK I/O Serial clock for SPI1. SPI1_MOSI I/O Master Out Slave In for SPI1. SPI1_MISO I/O Master In Slave Out for SPI1. SPI1_SSEL I/O Slave select for SPI1. CTIN_0 I SCT input 0. CTIN_1 I SCT input 1. CTIN_2 I SCT input 2. CTIN_3 I SCT input 3. CTOUT_0 O SCT output 0. CTOUT_1 O SCT output 1. CTOUT_2 O SCT output 2. CTOUT_3 O SCT output 3. I2C0_SCL I/O I2C-bus clock input/output (open-drain if assigned to pin PIO0_10). High-current sink only if assigned to PIO0_10 and if I2C Fast-mode Plus is selected in the I/O configuration register. I2C0_SDA I/O I2C-bus data input/output (open-drain if assigned to pin PIO0_11). High-current sink only if assigned to pin PIO0_11 and if I2C Fast-mode Plus is selected in the I/O configuration register. ACMP_O O Analog comparator digital output. CLKOUT O Clock output. GPIO_INT_BMAT O Output of the pattern match engine. Table 5. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) Function name Type Description LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 12 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Table 6. Pin location in ISP mode ISP entry pin USART RXD USART TXD Marking Boot loader version Package PIO0_1 PIO0_0 PIO0_4 1A v 13.1 TSSOP20; SO20; TSSOP16; DIP8; XSON16 PIO0_1 PIO0_0 PIO0_4 2A v 13.2 TSSOP20; SO20; TSSOP16; DIP8; XSON16 PIO0_1 PIO0_0 PIO0_4 4C and later v 13.4 and later DIP8 PIO0_12 PIO0_0 PIO0_4 4C and later v 13.4 and later TSSOP20; SO20; TSSOP16; XSON16 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 13 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8. Functional description 8.1 ARM Cortex-M0+ core The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 8.2 On-chip flash program memory The LPC81xM contain up to 16 kB of on-chip flash program memory. The flash memory supports a 64 Byte page size with page write and erase. 8.3 On-chip SRAM The LPC81xM contain a total of up to 4 kB on-chip static RAM data memory. 8.4 On-chip ROM The 8 kB on-chip ROM contains the boot loader and the following Application Programming Interfaces (API): • In-System Programming (ISP) and In-Application Programming (IAP) support for flash programming • Power profiles for configuring power consumption and PLL settings • USART driver API routines • I2C-bus driver API routines 8.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.5.1 Features • Controls system exceptions and peripheral interrupts. • On the LPC81xM, the NVIC supports 32 vectored interrupts including up to 8 external interrupt inputs selectable from all GPIO pins. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation using the ARM exceptions SVCall and PendSV. • Relocatable interrupt vector table using vector table offset register. 8.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 14 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Up to eight pins, regardless of the selected function, can be programmed to generate an interrupt on a level, a rising or falling edge, or both. The interrupt generating pins can be selected from all digital or mixed digital/analog pins. The pin interrupt/pattern match block controls the edge or level detection mechanism. 8.6 System tick timer The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to generate a dedicated SysTick exception at a fixed time interval (typically 10 ms). 8.7 Memory map The LPC81xM incorporates several distinct memory regions. Figure 7 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The ARM private peripheral bus includes the ARM core registers for controlling the NVIC, the system tick timer (SysTick), and the reduced power modes. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 15 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.8 I/O configuration The IOCON block controls the configuration of the I/O pins. Each digital or mixed digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10 and PIO0_11) in Table 4 can be configured as follows: • Enable or disable the weak internal pull-up and pull-down resistors. • Select a pseudo open-drain mode. The input cannot be pulled up above VDD. This pin is not 5 V tolerant when VDD = 0. Fig 7. LPC81xM Memory map 􀀤􀀳􀀥􀀃􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀁖 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀔􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀔􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀕􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀕􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀖􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀖􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀗􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀗􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀗􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀗􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀘􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀘􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀘􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀙􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀙􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀛􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀕􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀔􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀔􀀃􀀗􀀓􀀓􀀓 􀀺􀀺􀀧􀀷 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀰􀀵􀀷 􀀃􀁖􀁈􀁏􀁉􀀃􀁚􀁄􀁎􀁈􀀐􀁘􀁓􀀃􀁗􀁌􀁐􀁈􀁕 􀀳􀀰􀀸 􀀖􀀔􀀃􀀐􀀃􀀕􀀛􀀃􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁄􀁑􀁄􀁏􀁒􀁊􀀃􀁆􀁒􀁐􀁓􀁄􀁕􀁄􀁗􀁒􀁕 􀀓􀁛􀀗􀀓􀀓􀀕􀀃􀀦􀀓􀀓􀀓 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀀓􀁛􀀗􀀓􀀓􀀖􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀖􀀃􀀗􀀓􀀓􀀓 􀀓 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀜 􀀔􀀙 􀀔􀀘 􀀔􀀗 􀀔􀀚 􀀔􀀛 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀀓􀀃􀀪􀀥 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀀑􀀘􀀃􀀪􀀥 􀀗􀀃􀀪􀀥 􀀔􀀃􀀪􀀥 􀀓􀁛􀀔􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀔􀀩􀀩􀀩􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀔􀀩􀀩􀀩􀀃􀀕􀀓􀀓􀀓 􀀓􀁛􀀕􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀘􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀘􀀓􀀓􀀓􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀩􀀩􀀩􀀩􀀃􀀩􀀩􀀩􀀩 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀛􀀃􀀓􀀓􀀓􀀓 􀀤􀀳􀀥􀀃􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀁖 􀀓􀁛􀀘􀀓􀀓􀀓􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀤􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀤􀀓􀀓􀀓􀀃􀀗􀀓􀀓􀀓 􀀦􀀵􀀦 􀀶􀀦􀀷􀁌􀁐􀁈􀁕􀀒􀀳􀀺􀀰 􀀪􀀳􀀬􀀲 􀀓􀁛􀀤􀀓􀀓􀀓􀀃􀀛􀀓􀀓􀀓 􀁓􀁌􀁑􀀃􀁌􀁑􀁗􀁈􀁕􀁕􀁘􀁓􀁗􀁖􀀒􀁓􀁄􀁗􀁗􀁈􀁕􀁑􀀃􀁐􀁄􀁗􀁆􀁋 􀀓􀁛􀀔􀀓􀀓􀀓􀀃􀀓􀀛􀀓􀀓 􀀕􀀃􀁎􀀥􀀃􀀃􀀶􀀵􀀤􀀰􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀔􀀌 􀀓􀁛􀀔􀀓􀀓􀀓􀀃􀀓􀀗􀀓􀀓 􀀔􀀃􀁎􀀥􀀃􀀃􀀶􀀵􀀤􀀰􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀓􀀌 􀀓􀁛􀀔􀀓􀀓􀀓􀀃􀀔􀀓􀀓􀀓 􀀗􀀃􀁎􀀥􀀃􀀃􀀶􀀵􀀤􀀰􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀕􀀌 􀀓􀁛􀀔􀀗􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀔􀀗􀀓􀀓􀀃􀀓􀀗􀀓􀀓 􀀔􀀃􀁎􀀥􀀃􀀰􀀷􀀥􀀃􀁕􀁈􀁊􀁌􀁖􀁗􀁈􀁕􀁖 􀀯􀀳􀀦􀀛􀀔􀁛􀀰 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀗􀀓􀀓􀀓 􀀔􀀙􀀃􀁎􀀥􀀃􀁒􀁑􀀐􀁆􀁋􀁌􀁓􀀃􀁉􀁏􀁄􀁖􀁋􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀕􀀌 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀕􀀓􀀓􀀓 􀀛􀀃􀁎􀀥􀀃􀁒􀁑􀀐􀁆􀁋􀁌􀁓􀀃􀁉􀁏􀁄􀁖􀁋􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀔􀀌 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀔􀀓􀀓􀀓 􀀗􀀃􀁎􀀥􀀃􀁒􀁑􀀐􀁆􀁋􀁌􀁓􀀃􀁉􀁏􀁄􀁖􀁋􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀓􀀌 􀀛􀀃􀁎􀀥􀀃􀁅􀁒􀁒􀁗􀀃􀀵􀀲􀀰 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀓􀀓􀀦􀀓 􀁄􀁆􀁗􀁌􀁙􀁈􀀃􀁌􀁑􀁗􀁈􀁕􀁕􀁘􀁓􀁗􀀃􀁙􀁈􀁆􀁗􀁒􀁕􀁖 􀁄􀁄􀁄􀀐􀀓􀀓􀀘􀀚􀀗􀀛 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁉􀁏􀁄􀁖􀁋􀀃􀁆􀁒􀁑􀁗􀁕􀁒􀁏􀁏􀁈􀁕 􀀶􀀳􀀬􀀓 􀁖􀁚􀁌􀁗􀁆􀁋􀀃􀁐􀁄􀁗􀁕􀁌􀁛 􀀬􀀲􀀦􀀲􀀱 􀀶􀀼􀀶􀀦􀀲􀀱 􀀓􀁛􀀗􀀓􀀓􀀘􀀃􀀗􀀓􀀓􀀓 􀀔􀀜 􀀕􀀕 􀀕􀀖 􀀶􀀳􀀬􀀔 􀀸􀀶􀀤􀀵􀀷􀀓 􀀸􀀶􀀤􀀵􀀷􀀔 􀀓􀁛􀀗􀀓􀀓􀀙􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀙􀀃􀀦􀀓􀀓􀀓 􀀸􀀶􀀤􀀵􀀷􀀕 􀀓􀁛􀀗􀀓􀀓􀀚􀀃􀀓􀀓􀀓􀀓 􀀕􀀗 􀀓􀁛􀀨􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀨􀀓􀀔􀀓􀀃􀀓􀀓􀀓􀀓 􀁓􀁕􀁌􀁙􀁄􀁗􀁈􀀃􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀀃􀁅􀁘􀁖 􀀕􀀓 􀀬􀀕􀀦 􀀕􀀔 􀀕􀀘 􀀕􀀙 􀀕􀀚 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀀔􀀓 􀀔􀀔 􀀔􀀕 􀀔􀀖 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 16 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • Program the input glitch filter with different filter constants using one of the IOCON divided clock signals (IOCONCLKCDIV, see Figure 10 “LPC81xM clock generation”). You can also bypass the glitch filter. • Invert the input signal. • Hysteresis can be enabled or disabled. • For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard digital operation, for I2C standard and fast modes, or for I2C Fast mode+. • On mixed digital/analog pins, enable the analog input mode. Enabling the analog mode disconnects the digital functionality. Remark: The functionality of each I/O pin is flexible and is determined entirely through the switch matrix. See Section 8.9 for details. 8.8.1 Standard I/O pad configuration Figure 8 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver with configurable open-drain output • Digital input: Weak pull-up resistor (PMOS device) enabled/disabled • Digital input: Weak pull-down resistor (NMOS device) enabled/disabled • Digital input: Repeater mode enabled/disabled • Digital input: Input glitch filter selectable on all pins • Analog input LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 17 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.9 Switch Matrix (SWM) The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in Table 5. Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. The fixed-pin functions are listed in Table 4. If a fixed-pin function is disabled, any other movable function can be assigned to this pin. 8.10 Fast General-Purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC81xM use accelerated GPIO functions: • GPIO registers are located on the ARM Cortex M0+ IO bus for fastest possible single-cycle I/O timing, allowing GPIO toggling with rates of up to 15 MHz. Fig 8. Standard I/O pad configuration 􀀳􀀬􀀱 􀀹􀀧􀀧 􀀹􀀧􀀧 􀀨􀀶􀀧 􀀹􀀶􀀶 􀀨􀀶􀀧 􀁖􀁗􀁕􀁒􀁑􀁊 􀁓􀁘􀁏􀁏􀀐􀁘􀁓 􀁖􀁗􀁕􀁒􀁑􀁊 􀁓􀁘􀁏􀁏􀀐􀁇􀁒􀁚􀁑 􀀹􀀧􀀧 􀁚􀁈􀁄􀁎 􀁓􀁘􀁏􀁏􀀐􀁘􀁓 􀁚􀁈􀁄􀁎 􀁓􀁘􀁏􀁏􀀐􀁇􀁒􀁚􀁑 􀁒􀁓􀁈􀁑􀀐􀁇􀁕􀁄􀁌􀁑􀀃􀁈􀁑􀁄􀁅􀁏􀁈 􀁒􀁘􀁗􀁓􀁘􀁗􀀃􀁈􀁑􀁄􀁅􀁏􀁈 􀁕􀁈􀁓􀁈􀁄􀁗􀁈􀁕􀀃􀁐􀁒􀁇􀁈 􀁈􀁑􀁄􀁅􀁏􀁈 􀁓􀁘􀁏􀁏􀀐􀁘􀁓􀀃􀁈􀁑􀁄􀁅􀁏􀁈 􀁓􀁘􀁏􀁏􀀐􀁇􀁒􀁚􀁑􀀃􀁈􀁑􀁄􀁅􀁏􀁈 􀁖􀁈􀁏􀁈􀁆􀁗􀀃􀁇􀁄􀁗􀁄 􀁌􀁑􀁙􀁈􀁕􀁗􀁈􀁕 􀁇􀁄􀁗􀁄􀀃􀁒􀁘􀁗􀁓􀁘􀁗 􀁇􀁄􀁗􀁄􀀃􀁌􀁑􀁓􀁘􀁗 􀁖􀁈􀁏􀁈􀁆􀁗􀀃􀁊􀁏􀁌􀁗􀁆􀁋 􀁉􀁌􀁏􀁗􀁈􀁕 􀁄􀁑􀁄􀁏􀁒􀁊􀀃􀁌􀁑􀁓􀁘􀁗 􀁖􀁈􀁏􀁈􀁆􀁗􀀃􀁄􀁑􀁄􀁏􀁒􀁊􀀃􀁌􀁑􀁓􀁘􀁗 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀖􀀚􀀚 􀁓􀁌􀁑􀀃􀁆􀁒􀁑􀁉􀁌􀁊􀁘􀁕􀁈􀁇 􀁄􀁖􀀃􀁇􀁌􀁊􀁌􀁗􀁄􀁏􀀃􀁒􀁘􀁗􀁓􀁘􀁗 􀁇􀁕􀁌􀁙􀁈􀁕 􀁓􀁌􀁑􀀃􀁆􀁒􀁑􀁉􀁌􀁊􀁘􀁕􀁈􀁇 􀁄􀁖􀀃􀁇􀁌􀁊􀁌􀁗􀁄􀁏􀀃􀁌􀁑􀁓􀁘􀁗 􀁓􀁌􀁑􀀃􀁆􀁒􀁑􀁉􀁌􀁊􀁘􀁕􀁈􀁇 􀁄􀁖􀀃􀁄􀁑􀁄􀁏􀁒􀁊􀀃􀁌􀁑􀁓􀁘􀁗 􀀳􀀵􀀲􀀪􀀵􀀤􀀰􀀰􀀤􀀥􀀯􀀨 􀀪􀀯􀀬􀀷􀀦􀀫􀀃􀀩􀀬􀀯􀀷􀀨􀀵 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 18 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • An entire port value can be written in one instruction. • Mask, set, and clear operations are supported for the entire port. All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default. 8.10.1 Features • Bit level port registers allow a single instruction to set and clear any number of bits in one write operation. • Direction control of individual bits. • All I/O default to inputs with internal pull-up resistors enabled after reset - except for the I2C-bus true open-drain pins PIO0_2 and PIO0_3. • Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the IOCON block for each GPIO pin (see Figure 8). • 8.11 Pin interrupt/pattern match engine The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. The pattern match engine can be used, in conjunction with software, to create complex state machines based on pin inputs. Any digital pin, independently of the function selected through the switch matrix, can be configured through the SYSCON block as input to the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match engine are located on the IO+ bus for fast single-cycle access. 8.11.1 Features • Pin interrupts – Up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. – Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. – Level-sensitive interrupt pins can be HIGH- or LOW-active. – Pin interrupts can wake up the LPC81xM from sleep mode, deep-sleep mode, and power-down mode. • Pin interrupt pattern match engine – Up to eight pins can be selected from all digital pins to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins. – Each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. – Any occurrence of a pattern match can be programmed to also generate an RXEV notification to the ARM CPU. The RXEV signal can be connected to a pin. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 19 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller – The pattern match engine does not facilitate wake-up. 8.12 USART0/1/2 Remark: USART0 and USART1 are available on all LPC800 parts. USART2 is available on parts LPC812M101JDH16 and LPC812M101JDH20 only. All USART functions are movable functions and are assigned to pins through the switch matrix. 8.12.1 Features • Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins except PIO0_10 and PIO0_11. • 7, 8, or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. • Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.) • Parity generation and checking: odd, even, or none. • One transmit and one receive data buffer. • RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. • Received data and status can optionally be read from a single register • Break generation and detection. • Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. • Built-in Baud Rate Generator. • A fractional rate divider is shared among all UARTs. • Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected. • Separate data and flow control loopback modes for testing. • Supported by on-chip ROM API. 8.13 SPI0/1 Remark: SPI0 is available on all LPC800 parts. SPI1 is available on parts LPC812M101JDH16 and LPC812M101JDH20 only. All SPI functions are movable functions and are assigned to pins through the switch matrix. 8.13.1 Features • Maximum data rates of 30 Mbit/s in master mode and 25 Mbit/s in slave mode for SPI functions connected to all digital pins except PIO0_10 and PIO0_11. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 20 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • Data frames of 1 to 16 bits supported directly. Larger frames supported by software. • Master and slave operation. • Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI memory. • Control information can optionally be written along with data. This allows very versatile operation, including “any length” frames. • One Slave Select input/output with selectable polarity and flexible usage. Remark: Texas Instruments SSI and National Microwire modes are not supported. 8.14 I2C-bus interface The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. The I2C-bus functions are movable functions and can be assigned through the switch matrix to any pin. However, only the true open-drain PIO0_10 and PIO0_11 provide the electrical characteristics to support the full I2C-bus specification (see Ref. 1). 8.14.1 Features • Supports standard and fast mode with data rates of up to 400 kbit/s. • Independent Master, Slave, and Monitor functions. • Supports both Multi-master and Multi-master with Slave functions. • Multiple I2C slave addresses supported in hardware. • One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses. • 10-bit addressing supported with software assist. • Supports SMBus. • Supported by on-chip ROM API. • If the I2C functions are connected to the true open-drain pins (PIO0_10 and PIO0_11), the I2C supports the full I2C-bus specification: – Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA and SCL pins connected to the I2C-bus are floating and do not disturb the bus. – Supports Fast-mode Plus with bit rates up to 1 Mbit/s. 8.15 State-Configurable Timer/PWM (SCTimer/PWM) The state configurable timer (SCTimer/PWM or SCT) can perform basic 16-bit and 32-bit timer/counter functions with match outputs and external and internal capture inputs. In addition, the SCTimer/PWM can employ up to two different programmable states, which can change under the control of events, to provide complex timing patterns. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 21 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller All inputs and outputs of the SCTimer/PWM are movable functions and are assigned to pins through the switch matrix. 8.15.1 Features • Two 16-bit counters or one 32-bit counter. • Counters clocked by bus clock or selected input. • Up counters or up-down counters. • State variable allows sequencing across multiple counter cycles. • The following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state, and the count direction. • Events control outputs, interrupts, and the SCT states. – Match register 0 can be used as an automatic limit. – In bi-directional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs. • Selected events can limit, halt, start, or stop a counter. • Supports: – 4 inputs – 4 outputs – 5 match/capture registers – 6 events – 2 states 8.16 Multi-Rate Timer (MRT) The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. 8.16.1 Features • 31-bit interrupt timer • Four channels independently counting down from individually set values • Bus stall, repeat and one-shot interrupt modes 8.17 Windowed WatchDog Timer (WWDT) The watchdog timer resets the controller if software fails to periodically service it within a programmable time window. 8.17.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 22 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect feed sequence causes reset or interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK)is generated by a the dedicated watchdog oscillator (WDOSC). 8.18 Self Wake-up Timer (WKT) The self wake-up timer is a 32-bit, loadable down-counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. When the counter is used as a wake-up timer, this write can occur just prior to entering a reduced power mode. 8.18.1 Features • 32-bit loadable down-counter. Counter starts automatically when a count value is loaded. Time-out generates an interrupt/wake up request. • The WKT resides in a separate, always-on power domain. • The WKT supports two clock sources: the low-power oscillator and the IRC. The low-power oscillator is located in the always-on power domain, so it can be used as the clock source in Deep power-down mode. • The WKT can be used for waking up the part from any reduced power mode, including Deep power-down mode, or for general-purpose timing. 8.19 Analog comparator (ACMP) The analog comparator with selectable hysteresis can compare voltage levels on external pins and internal voltages. After power-up and after switching the input channels of the comparator, the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. Settling times are given in Table 22. The analog comparator output is a movable function and is assigned to a pin through the switch matrix. The comparator inputs and the voltage reference are enabled or disabled on pins PIO0_0 and PIO0_1 through the switch matrix. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 23 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.19.1 Features • Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input hysteresis. • Two selectable external voltages (VDD or VDDCMP on pin PIO0_6); fully configurable on either positive or negative input channel. • Internal voltage reference from band gap selectable on either positive or negative input channel. • 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. • Voltage ladder source voltage is selectable from an external pin or the main 3.3 V supply voltage rail. • Voltage ladder can be separately powered down for applications only requiring the comparator function. • Interrupt output is connected to NVIC. • Comparator level output is connected to output pin ACMP_O. • The comparator output can be routed internally to the SCT input through the switch matrix. Fig 9. Comparator block diagram 􀀕 􀀖􀀕 􀀕 􀀤􀀦􀀰􀀳􀁂􀀬􀀾􀀕􀀝􀀔􀁀 􀀹􀀧􀀧 􀀹􀀧􀀧􀀦􀀰􀀳 􀁌􀁑􀁗􀁈􀁕􀁑􀁄􀁏 􀁙􀁒􀁏􀁗􀁄􀁊􀁈 􀁕􀁈􀁉􀁈􀁕􀁈􀁑􀁆􀁈 􀁈􀁇􀁊􀁈􀀃􀁇􀁈􀁗􀁈􀁆􀁗 􀁖􀁜􀁑􀁆 􀁆􀁒􀁐􀁓􀁄􀁕􀁄􀁗􀁒􀁕 􀁏􀁈􀁙􀁈􀁏􀀃􀀤􀀦􀀰􀀳􀁂􀀲 􀁆􀁒􀁐􀁓􀁄􀁕􀁄􀁗􀁒􀁕 􀁈􀁇􀁊􀁈􀀃􀀱􀀹􀀬􀀦 􀀦􀀲􀀰􀀳􀀤􀀵􀀤􀀷􀀲􀀵􀀃􀀤􀀱􀀤􀀯􀀲􀀪􀀃􀀥􀀯􀀲􀀦􀀮 􀀦􀀲􀀰􀀳􀀤􀀵􀀤􀀷􀀲􀀵􀀃􀀧􀀬􀀪􀀬􀀷􀀤􀀯􀀃􀀥􀀯􀀲􀀦􀀮 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀘􀀓􀀛 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 24 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.20 Clocking and power control 8.20.1 Crystal and internal oscillators The LPC81xM include four independent oscillators: 1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz. 2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz, trimmed to 1% accuracy. 3. The internal low-power, low-frequency Oscillator with a nominal frequency of 10 kHz with 40% accuracy for use with the self wake-up timer. 4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal frequency between 9.4 kHz and 2.3 MHz with 40% accuracy. Fig 10. LPC81xM clock generation 􀀶􀀼􀀶􀀷􀀨􀀰􀀃􀀃􀀳􀀯􀀯 􀁚􀁄􀁗􀁆􀁋􀁇􀁒􀁊􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀬􀀵􀀦􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀬􀀵􀀦􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀁚􀁄􀁗􀁆􀁋􀁇􀁒􀁊􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀶􀀼􀀶􀀷􀀨􀀰 􀀲􀀶􀀦􀀬􀀯􀀯􀀤􀀷􀀲􀀵 􀀰􀀤􀀬􀀱􀀦􀀯􀀮􀀶􀀨􀀯 􀀋􀁐􀁄􀁌􀁑􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁖􀁈􀁏􀁈􀁆􀁗􀀌 􀀶􀀼􀀶􀀳􀀯􀀯􀀦􀀯􀀮􀀶􀀨􀀯 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀀳􀀯􀀯􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁖􀁈􀁏􀁈􀁆􀁗 􀀦􀀯􀀲􀀦􀀮􀀃􀀧􀀬􀀹􀀬􀀧􀀨􀀵 􀀶􀀼􀀶􀀤􀀫􀀥􀀦􀀯􀀮􀀧􀀬􀀹 􀀤􀀫􀀥􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀀓 􀀋􀁆􀁒􀁕􀁈􀀏􀀃􀁖􀁜􀁖􀁗􀁈􀁐􀀞􀀃 􀁄􀁏􀁚􀁄􀁜􀁖􀀐􀁒􀁑􀀌 􀀦􀀯􀀲􀀦􀀮􀀃􀀧􀀬􀀹􀀬􀀧􀀨􀀵 􀀸􀀤􀀵􀀷􀀦􀀯􀀮􀀧􀀬􀀹 􀀸􀀶􀀤􀀵􀀷􀀓 􀀸􀀶􀀤􀀵􀀷􀀔 􀀸􀀶􀀤􀀵􀀷􀀕 􀀺􀀺􀀧􀀷 􀀬􀀵􀀦􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀺􀀮􀀷 􀁏􀁒􀁚􀀐􀁓􀁒􀁚􀁈􀁕􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀺􀀮􀀷 􀁚􀁄􀁗􀁆􀁋􀁇􀁒􀁊􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀬􀀵􀀦􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀦􀀯􀀲􀀦􀀮􀀃􀀧􀀬􀀹􀀬􀀧􀀨􀀵 􀀦􀀯􀀮􀀲􀀸􀀷􀀧􀀬􀀹 􀀦􀀯􀀮􀀲􀀸􀀷􀀃􀁓􀁌􀁑 􀀦􀀯􀀮􀀲􀀸􀀷􀀶􀀨􀀯 􀀋􀀦􀀯􀀮􀀲􀀸􀀷􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁖􀁈􀁏􀁈􀁆􀁗􀀌 􀁐􀁄􀁌􀁑􀀃􀁆􀁏􀁒􀁆􀁎 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁆􀁏􀁒􀁆􀁎 􀀶􀀼􀀶􀀤􀀫􀀥􀀦􀀯􀀮􀀦􀀷􀀵􀀯􀀾􀀔􀀝􀀔􀀜􀁀 􀀋􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁈􀁑􀁄􀁅􀁏􀁈􀀌 􀁐􀁈􀁐􀁒􀁕􀁌􀁈􀁖 􀁄􀁑􀁇􀀃􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀁖􀀏 􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀀃􀁆􀁏􀁒􀁆􀁎􀁖 􀀔􀀜 􀁄􀁄􀁄􀀐􀀓􀀓􀀘􀀚􀀗􀀜 􀀬􀀲􀀦􀀲􀀱􀀦􀀯􀀮􀀧􀀬􀀹 􀀦􀀯􀀲􀀦􀀮􀀃􀀧􀀬􀀹􀀬􀀧􀀨􀀵 􀀬􀀲􀀦􀀲􀀱􀀃 􀁊􀁏􀁌􀁗􀁆􀁋􀀃􀁉􀁌􀁏􀁗􀁈􀁕 􀀚 􀀻􀀷􀀤􀀯􀀬􀀱 􀀦􀀯􀀮􀀬􀀱 􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀶􀀼􀀶􀀦􀀲􀀱 􀀳􀀰􀀸 􀀩􀀵􀀤􀀦􀀷􀀬􀀲􀀱􀀤􀀯􀀃􀀵􀀤􀀷􀀨 􀀪􀀨􀀱􀀨􀀵􀀤􀀷􀀲􀀵 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 25 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Each oscillator, except the low-frequency oscillator, can be used for more than one purpose as required in a particular application. Following reset, the LPC81xM will operate from the IRC until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 10 for an overview of the LPC81xM clock generation. 8.20.1.1 Internal RC Oscillator (IRC) The IRC may be used as the clock source for the WWDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1.5 % accuracy over the entire voltage and temperature range. The IRC can be used as a clock source for the CPU with or without using the PLL. The IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. Upon power-up or any chip reset, the LPC81xM use the IRC as the clock source. Software may later switch to one of the other available clock sources. 8.20.1.2 Crystal Oscillator (SysOsc) The crystal oscillator can be used as the clock source for the CPU, with or without using the PLL. The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 8.20.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc) The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process variations is  40%. The WDOsc is a dedicated oscillator for the windowed WWDT. The internal low-power 10 kHz (  40% accuracy) oscillator serves a the clock input to the WKT. This oscillator can be configured to run in all low power modes. 8.20.2 Clock input An external clock source can be supplied on the selected CLKIN pin. When selecting a clock signal for the CLKIN pin, follow the specifications for digital I/O pins in Table 9 “Static characteristics” and Table 15 “Dynamic characteristics: I/O pins[1]”. An 1.8 V external clock source can be supplied on the XTALIN pins to the system oscillator limiting the voltage of this signal ((see Section 14.2). The maximum frequency for both clock signals is 25 MHz. 8.20.3 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 26 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is nominally 100 s. 8.20.4 Clock output The LPC81xM features a clock output function that routes the IRC, the SysOsc, the watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can be connected to any digital pin through the switch matrix. 8.20.5 Wake-up process The LPC81xM begin operation at power-up by using the IRC as the clock source. This allows chip operation to resume quickly. If the SysOsc, the external clock source, or the PLL is needed by the application, software must enable these features and wait for them to stabilize before they are used as a clock source. 8.20.6 Power control The LPC81xM supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 8.20.6.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile API. The API is accessible through the on-chip ROM. The power configuration routine configures the LPC81xM for one of the following power modes: • Default mode corresponding to power configuration after reset. • CPU performance mode corresponding to optimized processing capability. • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. 8.20.6.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 27 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.20.6.3 Deep-sleep mode In Deep-sleep mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all clock sources are off except for the IRC and watchdog oscillator or low-power oscillator if selected. The IRC output is disabled. In addition all analog blocks are shut down and the flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC81xM can wake up from Deep-sleep mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C blocks (in slave mode). Any interrupt used for waking up from Deep-sleep mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Deep-sleep mode saves power and allows for short wake-up times. 8.20.6.4 Power-down mode In Power-down mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all clock sources are off except for watchdog oscillator or low-power oscillator if selected. In addition all analog blocks and the flash are shut down. In Power-down mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC81xM can wake up from Power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C blocks (in slave mode). Any interrupt used for waking up from Power-down mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 8.20.6.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin and the self wake-up timer if enabled. Four general-purpose registers are available to store information during Deep power-down mode. The LPC81xM can wake up from Deep power-down mode via the WAKEUP pin, or without an external signal by using the time-out of the self wake-up timer (see Section 8.18). The LPC81xM can be prevented from entering Deep power-down mode by setting a lock bit in the PMU block. Locking out Deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 28 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. 8.21 System control 8.21.1 Reset Reset has four sources on the LPC81xM: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. In Deep power-down mode, an external pull-up resistor is required on the RESET pin. 8.21.2 Brownout detection The LPC81xM includes up to four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Four threshold levels can be selected to cause a forced reset of the chip. Fig 11. Reset pad configuration 􀀹􀀶􀀶 􀁕􀁈􀁖􀁈􀁗 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀔􀀖 􀀹􀀧􀀧 􀀹􀀧􀀧 􀀹􀀧􀀧 􀀵􀁓􀁘 􀀨􀀶􀀧 􀀨􀀶􀀧 􀀕􀀓􀀃􀁑􀁖􀀃􀀵􀀦 􀀪􀀯􀀬􀀷􀀦􀀫􀀃􀀩􀀬􀀯􀀷􀀨􀀵 􀀳􀀬􀀱 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 29 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.21.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For details, see the LPC800 user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using the ISP entry pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can be disabled. For details, see the LPC800 user manual. 8.21.4 APB interface The APB peripherals are located on one APB bus. 8.21.5 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the main static RAM, the CRC, and the ROM. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 30 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.22 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watch points. The Micro Trace Buffer is implemented on the LPC81xM. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC81xM is in reset. The JTAG boundary scan pins are selected by hardware when the part is in boundary scan mode on pins PIO0_0 to PIO0_3 (see Table 4). To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. Fig 12. Connecting the SWD pins to a standard SWD connector 􀀵􀀨􀀶􀀨􀀷 􀀶􀀺􀀧􀀬􀀲 􀀶􀀺􀀦􀀯􀀮 􀀹􀀧􀀧 􀀯􀀳􀀦􀀛􀀓􀀓 􀀬􀀶􀀳􀀃􀁈􀁑􀁗􀁕􀁜 􀀳􀀬􀀲􀀓􀁂􀀔􀀕􀀃 􀀃􀀃 􀀹􀀷􀀵􀀨􀀩 􀀶􀀺􀀧􀀬􀀲 􀀶􀀺􀀦􀀯􀀮 􀁑􀀵􀀨􀀶􀀨􀀷 􀀪􀀱􀀧 􀁄􀁄􀁄􀀐􀀓􀀓􀀙􀀓􀀛􀀙 􀁉􀁕􀁒􀁐􀀃􀀶􀀺􀀧 􀁆􀁒􀁑􀁑􀁈􀁆􀁗􀁒􀁕 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 31 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 9. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended and proper operation is not guaranteed. The conditions for functional operation are specified in Table 9. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 9) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Including voltage on outputs in tri-state mode. Does not apply to pin PIO0_6. [4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [5] VDD present or not present. [6] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below VDD without affecting the hysteresis range of the comparator function. [7] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [8] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [9] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD supply voltage (core and external rail) [2] 0.5 +4.6 V VI input voltage 5 V tolerant I/O pins; VDD  1.8 V [3] 0.5 +5.5 V 5 V tolerant open-drain pins PIO0_10 and PIO0_11 [4] 0.5 +5.5 V 3 V tolerant I/O pin PIO0_6 [5] 0.5 +3.6 V VIA analog input voltage [6] [7] 0.5 4.6 V Vi(xtal) crystal input voltage [2] 0.5 +2.5 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); Tj < 125 C - 100 mA Tstg storage temperature non-operating [8] 65 +150 C Tj(max) maximum junction temperature - 150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [9] - 5500 V charged device model; TSSOP20 and SOP20 packages - 1200 V charged device model; TSSOP16 package - 1000 V charged device model; XSON16 package - 800 V LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 32 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 8. Thermal resistance Symbol Parameter Conditions Max/Min Unit DIP8 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 60 ± 15 % C/W Single-layer (4.5 in  3 in); still air 81 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 38 ± 15 % C/W TSSOP16 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 133 ± 15 % C/W Single-layer (4.5 in  3 in); still air 182 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 33 ± 15 % C/W TSSOP20 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 110 ± 15 % C/W Single-layer (4.5 in  3 in); still air 153 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 23 ± 15 % C/W SO20 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 87 ± 15 % C/W Single-layer (4.5 in  3 in); still air 112 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 50 ± 15 % C/W XSON16 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 92 ± 15 % C/W Single-layer (4.5 in  3 in); still air 180 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 27 ± 15 % C/W Tj = Tamb + PD  Rthj – a LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 33 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11. Static characteristics Table 9. Static characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD supply voltage (core and external rail) 1.8 3.3 3.6 V IDD supply current Active mode; code while(1){} executed from flash; system clock = 12 MHz; default mode; VDD = 3.3 V [2][3][4][5]- 1.4 - mA system clock = 12 MHz; low-current mode; VDD = 3.3 V [2][3][4][5] [6] - 1.0 - mA system clock = 24 MHz; low-current mode; VDD = 3.3 V [2][4][5][6] [7] - 2.2 - mA system clock = 30 MHz; default mode; VDD = 3.3 V [2][4][5][8]- 3.3 - mA system clock = 30 MHz; low-current mode; VDD = 3.3 V [2][4][5][6] [8] - 3 - mA Sleep mode system clock = 12 MHz; default mode; VDD = 3.3 V [2][3][4][5]- 0.8 - mA system clock = 12 MHz; low-current mode; VDD = 3.3 V [2][3][4][5] [6] - 0.7 - mA system clock = 24 MHz; low-current mode; VDD = 3.3 V [2][4][5][6] [7] - 1.3 - mA system clock = 30 MHz; default mode; VDD = 3.3 V [2][4][5][8]- 1.8 - mA system clock = 30 MHz; low-current mode; VDD = 3.3 V [2][4][5][6] [8] - 1.7 - mA Deep-sleep mode VDD = 3.3 V, Tamb = 25 °C [2][9] - 150 300 A VDD = 3.3 V, Tamb = 105 °C [2][9] - - 400 A Power-down mode VDD = 3.3 V, Tamb = 25 °C [2][9]- 0.9 5 A VDD = 3.3 V, Tamb = 105 °C [2][9]- - 40 A Deep power-down mode; Low-power oscillator and self wakeup timer (WKT) disabled VDD = 3.3 V, Tamb = 25 °C [10] - 170 1000 nA VDD = 3.3 V, Tamb = 105 °C [10] - - 4 A Deep power-down mode; Low-power oscillator and self wakeup timer (WKT) enabled - 1 - A LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 34 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Standard port pins configured as digital pins, RESET; see Figure 13 IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage VDD  1.8 V; 5 V tolerant pins except PIO0_6 [11] [12] 0 - 5.0 V VDD  1.8 V; on 3 V tolerant pin PIO0_6 0 - 3.6 VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 4 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 3 mA VDD  0.4 - - V VOL LOW-level output voltage 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.5 V 3 - - mA IOL LOW-level output current VOL = 0.4 V 2.5 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.5 V 3 - - mA IOHS HIGH-level short-circuit output current VOH = 0 V [13] - - 45 mA IOLS LOW-level short-circuit output current VOL = VDD [13] - - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; 2.0 V  VDD  3.6 V 15 50 85 A 1.8 V  VDD < 2.0 V 10 50 85 A VDD < VI < 5 V 0 0 0 A High-drive output pins configured as digital pins (PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13); see Figure 13 IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 35 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller VI input voltage VDD  1.8 V [11] [12] 0 - 5.0 V VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 20 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 12 mA VDD  0.4 - - V VOL LOW-level output voltage 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.5 V 12 - - mA IOL LOW-level output current VOL = 0.4 V 2.5 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.5 V 3 - - mA IOLS LOW-level short-circuit output current VOL = VDD [13] - - 50 mA Ipd pull-down current VI = 5 V [14] 10 50 150 A Ipu pull-up current VI = 0 V 2.0 V  VDD  3.6 V [14] 15 50 85 A 1.8 V  VDD < 2.0 V 10 50 85 A VDD < VI < 5 V 0 0 0 A I2C-bus pins (PIO0_10 and PIO0_11); see Figure 13 VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as standard mode pins 2.5 V  VDD  3.6 V 3.5 - - mA 1.8 V  VDD < 2.5 V 3 - - IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as Fast-mode Plus pins 2.5 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.5 V 16 - - ILI input leakage current VI = VDD [15]- 2 4 A VI = 5 V - 10 22 A Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 36 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [2] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [3] IRC enabled; system oscillator disabled; system PLL disabled. [4] BOD disabled. [5] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system configuration block. [6] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [7] IRC enabled; system oscillator disabled; system PLL enabled. [8] IRC disabled; system oscillator enabled; system PLL enabled. [9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [10] WAKEUP pin pulled HIGH externally. [11] Including voltage on outputs in tri-state mode. [12] 3-state outputs go into tri-state mode in Deep power-down mode. [13] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [14] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 8. [15] To VSS. Oscillator input pins (PIO0_8 and PIO0_9) Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Fig 13. Pin input/output current measurement 􀀯􀀳􀀦􀀛􀀓􀀓 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀓 􀀎 􀀐 􀁓􀁌􀁑􀀃􀀳􀀬􀀲􀀓􀁂􀁑 􀀬􀀲􀀫 􀀬􀁓􀁘 􀀐 􀀎 􀁓􀁌􀁑􀀃􀀳􀀬􀀲􀀓􀁂􀁑 􀀬􀀲􀀯 􀀬􀁓􀁇 􀀹􀀧􀀧 􀀤 􀀤 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 37 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.1 Power consumption Power measurements in Active, Sleep, Deep-sleep,and Power-down modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW. Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: IRC disabled; SYSOSC enabled; PLL enabled. Fig 14. Active mode: Typical supply current IDD versus supply voltage VDD 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀗 􀀔􀀑􀀛 􀀕􀀑􀀔􀀙 􀀕􀀑􀀘􀀕 􀀕􀀑􀀛􀀛 􀀖􀀑􀀕􀀗 􀀖􀀑􀀙 􀀓 􀀓􀀑􀀙 􀀔􀀑􀀕 􀀔􀀑􀀛 􀀕􀀑􀀗 􀀖 􀀹􀀧􀀧􀀃􀀋􀀹􀀌 􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀓􀀓􀀓􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀙􀀙􀀙􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀖􀀖􀀖􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 38 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: IRC disabled; SYSOSC enabled; PLL enabled. Fig 15. Active mode: Typical supply current IDD versus temperature 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀖 􀀐􀀗􀀓 􀀐􀀔􀀔 􀀔􀀛 􀀗􀀚 􀀚􀀙 􀀔􀀓􀀘 􀀓 􀀓􀀑􀀙 􀀔􀀑􀀕 􀀔􀀑􀀛 􀀕􀀑􀀗 􀀖 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀦􀀌 􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀓􀀓􀀓􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀙􀀙􀀙􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀖􀀖􀀖􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 39 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: IRC disabled; SYSOSC enabled; PLL enabled. Fig 16. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 17. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀘 􀀐􀀗􀀓 􀀐􀀔􀀔 􀀔􀀛 􀀗􀀚 􀀚􀀙 􀀔􀀓􀀘 􀀓 􀀓􀀑􀀗 􀀓􀀑􀀛 􀀔􀀑􀀕 􀀔􀀑􀀙 􀀕 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀦􀀌 􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀓􀀓􀀓􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀙􀀙􀀙􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀖􀀖􀀖􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀙􀀗 􀀐􀀗􀀓 􀀐􀀔􀀘 􀀔􀀓 􀀖􀀘 􀀙􀀓 􀀛􀀘 􀀔􀀔􀀓 􀀔􀀓􀀓 􀀔􀀕􀀓 􀀔􀀗􀀓 􀀔􀀙􀀓 􀀔􀀛􀀓 􀀕􀀓􀀓 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀃􀀦􀀌 􀀬􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀈝􀈝􀈝􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀑􀀑􀀑􀀙􀀙􀀙􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀓􀀓􀀓􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 40 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 18. Power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD WKT not running. Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀙􀀖 􀀐􀀗􀀓 􀀐􀀔􀀘 􀀔􀀓 􀀖􀀘 􀀙􀀓 􀀛􀀘 􀀔􀀔􀀓 􀀓 􀀚 􀀔􀀗 􀀕􀀔 􀀕􀀛 􀀖􀀘 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀃􀀦􀀌 􀀬􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀈝􀈝􀈝􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀑􀀑􀀑􀀙􀀙􀀙􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀙􀀕 􀀐􀀗􀀓 􀀐􀀔􀀘 􀀔􀀓 􀀖􀀘 􀀙􀀓 􀀛􀀘 􀀔􀀔􀀓 􀀓 􀀓􀀑􀀘 􀀔 􀀔􀀑􀀘 􀀕 􀀕􀀑􀀘 􀀖 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀃􀀦􀀌 􀀬􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀈝􀈝􀈝􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀑􀀑􀀑􀀙􀀙􀀙􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀓􀀓􀀓􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 41 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.2 CoreMark data Conditions: VDD = 3.3 V; Tamb = 25 C; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL register; system clock derived from the IRC; system oscillator disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7. Fig 20. Active mode: CoreMark power consumption IDD Conditions: VDD = 3.3 V; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL register; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7. Fig 21. CoreMark score 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀙 􀀓 􀀗 􀀛 􀀔􀀕 􀀔􀀙 􀀕􀀓 􀀕􀀗 􀀓 􀀔 􀀕 􀀖 􀀗 􀀘 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁉􀁕􀁈􀁔􀁘􀁈􀁑􀁆􀁜􀀃􀀋􀀰􀀫􀁝􀀌 􀀬􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀧􀀧􀀧􀁈􀁈􀁈􀁉􀁉􀁉􀁄􀁄􀁄􀁘􀁘􀁘􀁏􀁏􀁏􀁗􀁗􀁗 􀀦􀀦􀀦􀀳􀀳􀀳􀀸􀀸􀀸􀀒􀀒􀀒􀁈􀁈􀁈􀁉􀁉􀁉􀁉􀁉􀁉􀁌􀁌􀁌􀁆􀁆􀁆􀁌􀁌􀁌􀁈􀁈􀁈􀁑􀁑􀁑􀁆􀁆􀁆􀁜􀁜􀁜 􀀯􀀯􀀯􀁒􀁒􀁒􀁚􀁚􀁚􀀐􀀐􀀐􀁆􀁆􀁆􀁘􀁘􀁘􀁕􀁕􀁕􀁕􀁕􀁕􀁈􀁈􀁈􀁑􀁑􀁑􀁗􀁗􀁗 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀚 􀀓 􀀗 􀀛 􀀔􀀕 􀀔􀀙 􀀕􀀓 􀀕􀀗 􀀓 􀀓􀀑􀀘 􀀔 􀀔􀀑􀀘 􀀕 􀀕􀀑􀀘 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁉􀁕􀁈􀁔􀁘􀁈􀁑􀁆􀁜􀀃􀀋􀀰􀀫􀁝􀀌 􀀋􀀋􀁐􀁐􀀤􀀤􀀌􀀌 􀀧􀀧􀀧􀁈􀁈􀁈􀁉􀁉􀁉􀁄􀁄􀁄􀁘􀁘􀁘􀁏􀁏􀁏􀁗􀁗􀁗 􀀦􀀦􀀦􀀳􀀳􀀳􀀸􀀸􀀸􀀒􀀒􀀒􀁈􀁈􀁈􀁉􀁉􀁉􀁉􀁉􀁉􀁌􀁌􀁌􀁆􀁆􀁆􀁌􀁌􀁌􀁈􀁈􀁈􀁑􀁑􀁑􀁆􀁆􀁆􀁜􀁜􀁜 􀀯􀀯􀀯􀁒􀁒􀁒􀁚􀁚􀁚􀀐􀀐􀀐􀁆􀁆􀁆􀁘􀁘􀁘􀁕􀁕􀁕􀁕􀁕􀁕􀁈􀁈􀁈􀁑􀁑􀁑􀁗􀁗􀁗 􀀦􀀰 􀀋􀀋􀁌􀁗􀁈􀁕􀁄􀁗􀁌􀁒􀁑􀁖􀀒􀁖􀀌􀀒􀀰􀀫􀁝􀀌􀀌 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 42 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 30 MHz. Table 10. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 30 MHz IRC 0.21 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.28 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.002 - - System oscillator running; PLL off; independent of main clock frequency. BOD 0.05 - - Independent of main clock frequency. Main PLL - 0.31 - - CLKOUT - 0.06 0.09 Main clock divided by 4 in the CLKOUTDIV register. ROM - 0.08 0.19 - I2C - 0.06 0.15 - GPIO + pin interrupt/pattern match - 0.09 0.23 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. SWM - 0.03 0.07 - SCT - 0.17 0.42 - WKT - 0.01 0.03 - MRT - 0.09 0.21 - SPI0 - 0.05 0.13 - SPI1 - 0.06 0.14 - CRC - 0.03 0.07 - USART0 - 0.04 0.10 - USART1 - 0.04 0.11 - USART2 - 0.04 0.10 - WWDT - 0.04 0.10 Main clock selected as clock source for the WDT. IOCON - 0.03 0.08 - Comparator - 0.04 0.09 - LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 43 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.4 Electrical pin characteristics Conditions: VDD = 3.3 V and VDD = 1.8 V; on pins PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13. Fig 22. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH Conditions: VDD = 3.3 V and VDD = 1.8 V; on pins PIO0_10 and PIO0_11. Fig 23. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀙􀀓 􀀓 􀀔􀀓 􀀕􀀓 􀀖􀀓 􀀗􀀓 􀀘􀀓 􀀙􀀓 􀀚􀀓 􀀛􀀓 􀀔􀀑􀀕 􀀔􀀑􀀙 􀀕 􀀕􀀑􀀗 􀀕􀀑􀀛 􀀖􀀑􀀕 􀀖􀀑􀀙 􀀬􀀲􀀫􀀃􀀋􀁐􀀤􀀌 􀀹􀀹􀀹􀀲􀀲􀀲􀀫􀀫􀀫 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀁙􀁙 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀁙􀁙 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀘􀀜 􀀓 􀀓􀀑􀀔 􀀓􀀑􀀕 􀀓􀀑􀀖 􀀓􀀑􀀗 􀀓􀀑􀀘 􀀓􀀑􀀙 􀀓 􀀔􀀘 􀀖􀀓 􀀗􀀘 􀀙􀀓 􀀹􀀲􀀯􀀃􀀋􀀹􀀌 􀀬􀀬􀀬􀀲􀀲􀀲􀀯􀀯􀀯 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 44 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins and high-drive pins PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13. Fig 24. Typical LOW-level output current IOL versus LOW-level output voltage VOL Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins. Fig 25. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀘􀀛 􀀓 􀀓􀀑􀀔 􀀓􀀑􀀕 􀀓􀀑􀀖 􀀓􀀑􀀗 􀀓􀀑􀀘 􀀓􀀑􀀙 􀀓 􀀖 􀀙 􀀜 􀀔􀀕 􀀔􀀘 􀀹􀀲􀀯􀀃􀀋􀀹􀀌 􀀬􀀬􀀬􀀲􀀲􀀲􀀯􀀯􀀯 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀚􀀜􀀖 􀀓 􀀖 􀀙 􀀜 􀀔􀀕 􀀔􀀘 􀀔􀀛 􀀕􀀔 􀀔􀀑􀀕 􀀔􀀑􀀙 􀀕 􀀕􀀑􀀗 􀀕􀀑􀀛 􀀖􀀑􀀕 􀀖􀀑􀀙 􀀬􀀲􀀫􀀃􀀋􀁐􀀤􀀌 􀀹􀀹􀀹􀀲􀀲􀀲􀀫􀀫􀀫 􀀋􀀋􀀋􀀹􀀹􀀹􀀌􀀌􀀌 􀀹􀀧􀀧􀀃􀀠􀀃􀀖􀀑􀀖􀀃􀀹􀀞 􀀷􀀃􀀠􀀃􀀃􀀐􀀗􀀓􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀕􀀘􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀛􀀘􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀔􀀓􀀘􀀃􀂃􀀦 􀀹􀀧􀀧􀀃􀀠􀀃􀀔􀀑􀀛􀀃􀀹􀀞 􀀷􀀃􀀠􀀃􀀃􀀐􀀗􀀓􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀕􀀘􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀛􀀘􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀔􀀓􀀘􀀃􀂃􀀦 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 45 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins. Fig 26. Typical pull-up current Ipu versus input voltage VI Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins. Fig 27. Typical pull-down current Ipd versus input voltage VI 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀛􀀙 􀀓 􀀔 􀀕 􀀖 􀀗 􀀘 􀀐􀀓􀀑􀀓􀀚 􀀐􀀓􀀑􀀓􀀙 􀀐􀀓􀀑􀀓􀀗 􀀐􀀓􀀑􀀓􀀖 􀀐􀀓􀀑􀀓􀀕 􀀓 􀀓􀀑􀀓􀀔 􀀹􀀬􀀃􀀋􀀹􀀌 􀀬􀀬􀀬􀁓􀁓􀁓􀁘􀁘􀁘 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀜􀀜􀀜􀀓􀀓􀀓􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀜􀀜􀀜􀀓􀀓􀀓􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀹􀀧􀀧􀀃􀀠􀀃􀀔􀀑􀀛􀀃􀀹 􀀹􀀧􀀧􀀃􀀠􀀃􀀖􀀑􀀖􀀃􀀹 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀙􀀔 􀀓 􀀔 􀀕 􀀖 􀀗 􀀘 􀀓 􀀓􀀑􀀓􀀕 􀀓􀀑􀀓􀀗 􀀓􀀑􀀓􀀙 􀀓􀀑􀀓􀀛 􀀹􀀬􀀃􀀋􀀹􀀌 􀀬􀀬􀀬􀀳􀀳􀀳􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 46 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12. Dynamic characteristics 12.1 Flash memory [1] Number of program/erase cycles. [2] Programming times are given for writing 64 bytes to the flash. Tamb  +85 C. Flash programming with IAP calls (see LPC800 user manual). 12.2 External clock for the oscillator in slave mode Remark: The input voltage on the XTAL1/2 pins must be  1.95 V (see Table 9). For connecting the oscillator to the XTAL pins, also see Section 14.2. [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. Table 11. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 100000 - cycles tret retention time powered 10 20 - years unpowered 20 40 - years ter erase time page or multiple consecutive pages, sector or multiple consecutive sectors 95 100 105 ms tprog programming time [2] 0.95 1 1.05 ms Table 12. Dynamic characteristic: external clock (XTALIN inputs) Tamb = 40 C to +105 C; VDD over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Fig 28. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 􀁗􀀦􀀫􀀦􀀯 􀁗􀀦􀀯􀀦􀀻 􀁗􀀦􀀫􀀦􀀻 􀀷􀁆􀁜􀀋􀁆􀁏􀁎􀀌 􀁗􀀦􀀯􀀦􀀫 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀛 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 47 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12.3 Internal oscillators [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %. [3] See the LPC81xM user manual. Table 13. Dynamic characteristics: IRC Tamb = 40 C to +105 C; 2.7 V  VDD  3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency Tamb = 40 C to +105 C 11.82 12 12.18 MHz Conditions: Frequency values are typical values. 12 MHz  1.5 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb = 40 C to +105 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1.5 % accuracy specification for voltages below 2.7 V. Fig 29. Typical Internal RC oscillator frequency versus temperature Table 14. Dynamic characteristics: Watchdog oscillator Symbol Parameter Conditions Min Typ[1] Max Unit fosc(int) internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; [2][3]- 9.4 - kHz DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] - 2300 - kHz 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀚􀀘 􀀐􀀗􀀓 􀀐􀀔􀀓 􀀕􀀓 􀀘􀀓 􀀛􀀓 􀀔􀀔􀀓 􀀔􀀔􀀑􀀛􀀛 􀀔􀀔􀀑􀀜􀀕 􀀔􀀔􀀑􀀜􀀙 􀀔􀀕 􀀔􀀕􀀑􀀓􀀗 􀀔􀀕􀀑􀀓􀀛 􀀔􀀕􀀑􀀔􀀕 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀦􀀌 􀁉 􀀋􀀋􀀋􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝􀀌􀀌􀀌 􀀖􀀖􀀖􀀑􀀑􀀑􀀙􀀙􀀙􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀓􀀓􀀓􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀑􀀑􀀑􀀚􀀚􀀚􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀑􀀑􀀑􀀗􀀗􀀗􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀑􀀑􀀑􀀔􀀔􀀔􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 48 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12.4 I/O pins [1] Applies to standard port pins and RESET pin. 12.5 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. Table 15. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +105 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns Table 16. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus; on pins PIO0_10 and PIO0_11 0 1 MHz tf fall time [4][5][6][7] of both SDA and SCL signals Standard-mode - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus; on pins PIO0_10 and PIO0_11 - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0.5 - s tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0.26 - s tHD;DAT data hold time [3][4][8] Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0 - s tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus; on pins PIO0_10 and PIO0_11 50 - ns LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 49 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Fig 30. I2C-bus pins clock timing 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀖 􀁗􀁉 􀀚􀀓􀀃􀀈 􀀶􀀧􀀤 􀀖􀀓􀀃􀀈 􀁗􀁉 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀀶 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀁗􀀫􀀧􀀞􀀧􀀤􀀷 􀀶􀀦􀀯 􀀔􀀃􀀒􀀃􀁉􀀶􀀦􀀯 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀁗􀀹􀀧􀀞􀀧􀀤􀀷 􀁗􀀫􀀬􀀪􀀫 􀁗􀀯􀀲􀀺 􀁗􀀶􀀸􀀞􀀧􀀤􀀷 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 50 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12.6 SPI interfaces The maximum data bit rate is 30 Mbit/s in master mode and 25 Mbit/s in slave mode. Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_10 and PIO0_11. [1] Capacitance on pin SPIn_SCK CSCK < 5 pF. [2] Tcy(clk) = DIVVAL/CCLK with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC800 User manual UM10601. Table 17. SPI dynamic characteristics Tamb = 40 C to 105 C; 1.8 V  VDD  3.6 V. Simulated parameters sampled at the 50 % level of the rising or falling edge; values guaranteed by design. Symbol Parameter Conditions Min Max Unit SPI master[1] Tcy(clk) clock cycle time [2] 33 - ns tDS data set-up time 0 - ns tDH data hold time 16 - ns tv(Q) data output valid time CL = 10 pF - 0.5 ns th(Q) data output hold time CL = 10 pF 0.5 - ns SPI slave Tcy(clk) 40 ns tDS data set-up time 0 - ns tDH data hold time 16 - ns tv(Q) data output valid time CL = 10 pF - 10 ns th(Q) data output hold time CL = 10 pF 10 - ns LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 51 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 31. SPI master timing 􀀶􀀦􀀮􀀃􀀋􀀦􀀳􀀲􀀯􀀃􀀠􀀃􀀓􀀌 􀀰􀀲􀀶􀀬 􀀰􀀬􀀶􀀲 􀀷􀁆􀁜􀀋􀁆􀁏􀁎􀀌 􀁗􀀧􀀶 􀁗􀀧􀀫 􀁗􀁙􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁋􀀋􀀴􀀌 􀀶􀀦􀀮􀀃􀀋􀀦􀀳􀀲􀀯􀀃􀀠􀀃􀀔􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀰􀀲􀀶􀀬 􀀰􀀬􀀶􀀲 􀁗􀀧􀀶 􀁗􀀧􀀫 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁋􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁙􀀋􀀴􀀌 􀀦􀀳􀀫􀀤􀀃􀀠􀀃􀀔 􀀦􀀳􀀫􀀤􀀃􀀠􀀃􀀓 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀗 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 52 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 32. SPI slave timing 􀀶􀀦􀀮􀀃􀀋􀀦􀀳􀀲􀀯􀀃􀀠􀀃􀀓􀀌 􀀰􀀲􀀶􀀬 􀀰􀀬􀀶􀀲 􀀷􀁆􀁜􀀋􀁆􀁏􀁎􀀌 􀁗􀀧􀀶 􀁗􀀧􀀫 􀁗􀁙􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁋􀀋􀀴􀀌 􀀶􀀦􀀮􀀃􀀋􀀦􀀳􀀲􀀯􀀃􀀠􀀃􀀔􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀰􀀲􀀶􀀬 􀀰􀀬􀀶􀀲 􀁗􀀧􀀶 􀁗􀀧􀀫 􀁗􀁙􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁋􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀦􀀳􀀫􀀤􀀃􀀠􀀃􀀔 􀀦􀀳􀀫􀀤􀀃􀀠􀀃􀀓 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀘 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 53 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12.7 USART interface The maximum USART bit rate is 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode slave and master mode. Remark: USART functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_10 and PIO0_11. [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), VDD = 3.3 V, typical samples. [2] Tcy(clk) = U_PCLK/BRGVAL. See the LPC800 User manual UM10601. [3] Capacitance on pin Un_SCLK CSCLK < 5 pF. Table 18. USART dynamic characteristics Tamb = 40 C to 105 C; 1.8 V  VDD  3.6 V. Simulated parameters sampled at the 50 % level of the falling or rising edge; values guaranteed by design. Symbol Parameter Conditions Min Max Unit Tcy(clk) clock cycle time [2] 100 - ns USART master (in synchronous mode)[3] tsu(D) data input set-up time 44 - ns th(D) data input hold time 0 - ns tv(Q) data output valid time - -8 ns th(Q) data output hold time -8 - ns USART slave (in synchronous mode) tsu(D) data input set-up time 5 - ns th(D) data input hold time 0 - ns tv(Q) data output valid time CL = 10 pF - 40 ns th(Q) data output hold time CL = 10 pF 40 - ns Fig 33. USART timing 􀀸􀁑􀁂􀀶􀀦􀀯􀀮􀀃􀀋􀀦􀀯􀀮􀀳􀀲􀀯􀀃􀀠􀀃􀀓􀀌 􀀷􀀻􀀧 􀀵􀀻􀀧 􀀷􀁆􀁜􀀋􀁆􀁏􀁎􀀌 􀁗􀁖􀁘􀀋􀀧􀀌 􀁗􀁋􀀋􀀧􀀌 􀁗􀁙􀀋􀀴􀀌 􀀶􀀷􀀤􀀵􀀷 􀀥􀀬􀀷􀀓 􀁗􀁋􀀋􀀴􀀌 􀀸􀁑􀁂􀀶􀀦􀀯􀀮􀀃􀀋􀀦􀀯􀀮􀀳􀀲􀀯􀀃􀀠􀀃􀀔􀀌 􀀶􀀷􀀤􀀵􀀷 􀀥􀀬􀀷􀀓 􀀥􀀬􀀷􀀔 􀀥􀀬􀀷􀀔 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀓􀀓􀀔 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 54 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 13. Analog characteristics 13.1 BOD [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL. [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), VDD = 3.3 V, typical samples. 13.2 Internal voltage reference [1] Characterized through simulation. [2] Characterized on a typical silicon sample. Table 19. BOD static characteristics[1] Tamb = 40 C to +105 C. Symbol Parameter Conditions Typ[2] Unit Vth threshold voltage interrupt level 1 assertion 2.3 V de-assertion 2.4 V interrupt level 2 assertion 2.6 V de-assertion 2.7 V interrupt level 3 assertion 2.8 V de-assertion 2.9 V reset level 1 assertion 2.1 V de-assertion 2.2 V reset level 2 assertion 2.4 V de-assertion 2.5 V reset level 3 assertion 2.6 V de-assertion 2.8 V Table 20. Internal voltage reference static and dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit VO output voltage Tamb = 40 C to +105 C [1] 0.855 0.900 0.945 V Tamb = 70 C to 105 C [2] - 0.906 - V Tamb = 50 C [2] - 0.905 - V Tamb = 25 C [4] 0.893 0.903 0.913 V Tamb = 0 C [2] - 0.902 - V Tamb = 20 C [2] - 0.899 - V Tamb = 40 C [2] - 0.896 - V ts(pu) power-up settling time to 99% of VO [3] - 155 195 s LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 55 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [3] Typical values are derived from nominal simulation (VDD = 3.3 V; Tamb = 27 C; nominal process models). Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 105 C; slow process models). [4] Maximum and minimum values are measured on samples from the corners of the process matrix lot. 13.3 Comparator VDD = 3.3 V Fig 34. Typical internal voltage reference output voltage 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀔􀀖 􀀐􀀗􀀓 􀀐􀀔􀀘 􀀔􀀓 􀀖􀀘 􀀙􀀓 􀀛􀀘 􀀔􀀔􀀓 􀀛􀀜􀀓 􀀛􀀜􀀘 􀀜􀀓􀀓 􀀜􀀓􀀘 􀀜􀀔􀀓 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀦􀀌 􀀹􀀹􀀹􀀲􀀲􀀲 􀀋􀀋􀀋􀁐􀁐􀁐􀀹􀀹􀀹􀀌􀀌􀀌 Table 21. Comparator characteristics VDD = 3.0 V and Tamb = 27 C unless noted otherwise. Symbol Parameter Conditions Min Typ Max Unit Static characteristics Vref(cmp) comparator reference voltage pin PIO0_6/VDDCMP configured for function VDDCMP 1.5 - 3.6 V IDD supply current - 55 - A VIC common-mode input voltage 0 - VDD V DVO output voltage variation 0 - VDD V Voffset offset voltage VIC = 0.1 V - 1.9 - mV VIC = 1.5 V - 2.1 - mV VIC = 2.8 V - 2.0 mV Dynamic characteristics tstartup start-up time nominal process - 4 - s LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 56 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = 40 C to +105 C. Typical data are for Tamb = 27 C. [2] Input hysteresis is relative to the reference input channel and is software programmable to three levels. [1] Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 105 C; slow process models). [2] Settling time applies to switching between comparator channels. tPD propagation delay HIGH to LOW; VDD = 3.0 V; VIC = 0.1 V; 50 mV overdrive input [1] - 109 121 ns VIC = 0.1 V; rail-to-rail input [1] - 155 164 ns VIC = 1.5 V; 50 mV overdrive input [1] - 95 105 ns VIC = 1.5 V; rail-to-rail input [1] - 101 108 ns VIC = 2.9 V; 50 mV overdrive input [1] - 122 129 ns VIC = 2.9 V; rail-to-rail input [1] - 74 82 ns tPD propagation delay LOW to HIGH; VDD = 3.0 V; VIC = 0.1 V; 50 mV overdrive input [1] - 246 260 ns VIC = 0.1 V; rail-to-rail input [1] - 57 59 ns VIC = 1.5 V; 50 mV overdrive input [1] - 218 ns VIC = 1.5 V; rail-to-rail input [1] - 146 155 ns VIC = 2.9 V; 50 mV overdrive input [1] - 184 206 ns VIC = 2.9 V; rail-to-rail input [1] - 250 286 ns Vhys hysteresis voltage positive hysteresis; VDD = 3.0 V; VIC = 1.5 V [2] - 6, 11, 21 - mV Vhys hysteresis voltage negative hysteresis; VDD = 3.0 V; VIC = 1.5 V [2][2] - 4, 9, 19 - mV Rlad ladder resistance - - 1.034 - M Table 21. Comparator characteristics …continued VDD = 3.0 V and Tamb = 27 C unless noted otherwise. Symbol Parameter Conditions Min Typ Max Unit Table 22. Comparator voltage ladder dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit ts(pu) power-up settling time to 99% of voltage ladder output value [1]- - 30 s ts(sw) switching settling time to 99% of voltage ladder output value [1] [2] - - 15 s LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 57 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V. [2] All peripherals except comparator and IRC turned off. Table 23. Comparator voltage ladder reference static characteristics VDD = 3.3 V; Tamb = 40 C to + 105C. Symbol Parameter Conditions Min Typ Max[1] Unit EV(O) output voltage error Internal VDD supply decimal code = 00 [2]- 0 0 % decimal code = 08 - 0 0.4 % decimal code = 16 - 0.2 0.2 % decimal code = 24 - 0.2 0.2 % decimal code = 30 - 0.1 0.1 % decimal code = 31 - 0.1 0.1 % EV(O) output voltage error External VDDCMP supply decimal code = 00 - 0 0 % decimal code = 08 - 0.1 0.5 % decimal code = 16 - 0.2 0.4 % decimal code = 24 - 0.2 0.3 % decimal code = 30 - 0.2 0.2 % decimal code = 31 - 0.1 0.1 % LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 58 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 14. Application information 14.1 Typical wake-up times [1] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR) wake-up handler. [2] IRC enabled, all peripherals off. [3] Watchdog oscillator disabled, Brown-Out Detect (BOD) disabled. [4] Self wakeup-timer disabled. Wake-up from deep power-down causes the LPC800 to go through entire reset process. The wake-up time measured is the time between when a wake-up pin is triggered to wake the device up from the low power modes and from when a GPIO output pin is set in the reset handler. 14.2 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 35), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 36 and in Table 25 and Table 26. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and Table 24. Typical wake-up times (3.3 V, Temp = 25 °C) Power modes VDD current Wake-up time Sleep mode (12 MHz)[1][2] 0.7 mA 2.6 s Deep-sleep mode[1][3] 150 A 4 s Power-down mode[1][3] 0.9 A 50 s Deep Power-down mode[4] 170 nA 215 s Fig 35. Slave mode operation of the on-chip oscillator 􀀯􀀳􀀦􀀛􀀓􀀓 􀀻􀀷􀀤􀀯􀀬􀀱 􀀦􀁌 􀀔􀀓􀀓􀀃􀁓􀀩 􀀦􀁊 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀙 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 59 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller RS). Capacitance CP in Figure 36 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer (see Table 25). Fig 36. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 25. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF Table 26. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀚 􀀯􀀳􀀦􀀛􀀓􀀓 􀀻􀀷􀀤􀀯􀀬􀀱 􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀦􀀻􀀔 􀀦􀀻􀀕 􀀻􀀷􀀤􀀯 􀀠 􀀦􀀯 􀀦􀀳 􀀵􀀶 􀀯 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 60 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 14.3 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 61 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 15. Package outline Fig 37. Package outline SOT097-2 (DIP8) Outline References version European projection Issue date IEC JEDEC JEITA SOT97-2 MO-001 sot097-2_po 10-10-15 10-10-18 Unit(1) mm max nom min 4.2 0.51 0.53 0.38 1.07 0.89 0.38 0.20 6.48 6.20 9.8 9.2 2.54 7.62 A Dimensions (inch dimensions are derived from the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-2 A1 b 1.73 1.14 b1 b2 c D(1) E(1) e e1 L ME MH w 0.254 Z(1) 1.15 inches max nom min 0.17 0.02 3.43 A2 0.14 0.021 0.015 0.042 0.035 0.015 0.008 9.40 7.88 0.37 0.31 7.88 7.62 0.31 0.30 0.26 0.24 0.39 0.36 3.60 3.05 0.14 0.12 0.1 0.3 0.068 0.045 0.01 0.045 0 2.5 5 mm scale Z e w b1 D seating plane A2 A1 A L pin 1 index b b2 E 1 4 8 5 (e1) MH ME c - - - - - - LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 62 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 38. Package outline SOT403-1 (TSSOP16) UNIT A1 A2 A3 bp c D(1) E (2) e HE L Lp Q v w y Z (1) θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o 1 0.2 0.13 0.1 o DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 1 8 16 9 θ A A1 A2 Lp Q detail X L (A 3 ) HE E c v M A X A y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 63 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 39. Package outline SOT163-1 (SO20) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z (1) θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT163-1 10 20 w M bp detail X Z e 11 1 D y 0.25 075E04 MS-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale X θ A A1 A2 HE Lp Q E c L v M A (A 3 ) A SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 99-12-27 03-02-19 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 64 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 40. Package outline SOT360-1 (TSSOP20) UNIT A1 A2 A3 bp c D(1) E (2) e HE L Lp Q v w y Z (1) θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o 1 0.2 0.13 0.1 o DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT360-1 MO-153 99-12-27 03-02-19 w M bp D Z e 0.25 1 10 20 11 pin 1 index θ A A1 A2 Lp Q detail X L (A 3 ) HE E c v M A X A y 0 2.5 5 mm scale TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 A max. 1.1 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 65 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 41. Package outline SOT1341-1 (XSON16) Outline References version European projection Issue date IEC JEDEC JEITA SOT1341-1 MO-252 sot1341-1_po 12-09-05 13-02-13 Unit(1) mm max nom min 0.5 0.05 0.00 A Dimensions (mm are the original dimensions) XSON16: plastic extremely thin small outline package; no leads; 16 terminals; body 2.5 x 3.2 x 0.5 mm S OT1341-1 A1 0.25 0.20 0.15 2.6 2.5 2.4 0.9 0.8 0.7 3.3 3.2 3.1 0.4 2.8 0.2 b c 0.152 0.050 D E e e1 k L 1.0 0.9 0.8 L1 v 0.1 0.05 w y 0.05 y1 0.05 0 1 2 3 mm scale Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. e1 e terminal 1 index area terminal 1 index area D B A E detail X c A A1 L1 k L - - - - - - X C b y1 C y v C A B w C 1 8 16 9 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 66 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 16. Soldering Fig 42. Reflow soldering of the TSSOP16 package DIMENSIONS in mm P1 Ay By C D1 D2 Gx Gy Hy sot403-1_fr Hx SOT403-1 solder land occupied area Footprint information for reflow soldering of TSSOP16 package Gy By Ay C Hy Hx Gx P1 Generic footprint pattern Refer to the package outline drawing for actual layout P2 (0.125) (0.125) D2 (4x) D1 P2 0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 67 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 43. Reflow soldering of the SO20 package occupied area sot163-1_fr solder lands placement accuracy ± 0.25 Dimensions in mm 1.50 0.60 (20×) 1.27 (18×) 8.00 11.00 13.40 11.40 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 68 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 44. Reflow soldering of the TSSOP20 package DIMENSIONS in mm P1 Ay By C D1 D2 Gx Gy Hy sot360-1_fr Hx SOT360-1 solder land occupied area Footprint information for reflow soldering of TSSOP20 package Gy By Ay C Hy Hx Gx P1 Generic footprint pattern Refer to the package outline drawing for actual layout P2 (0.125) (0.125) D2 (4x) D1 P2 0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 69 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 45. Reflow soldering of the XSON16 package 􀀩􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁌􀁑􀁉􀁒􀁕􀁐􀁄􀁗􀁌􀁒􀁑􀀃􀁉􀁒􀁕􀀃􀁕􀁈􀁉􀁏􀁒􀁚􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀁌􀁑􀁊􀀃􀁒􀁉􀀃􀀻􀀶􀀲􀀱􀀔􀀙􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀃 􀀶􀀲􀀷􀀔􀀖􀀗􀀔􀀐􀀔 􀁖􀁒􀁗􀀔􀀖􀀗􀀔􀀐􀀔􀁂􀁉􀁕 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁓􀁄􀁖􀁗􀁈 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁕􀁈􀁖􀁌􀁖􀁗 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇􀁖 􀀬􀁖􀁖􀁘􀁈􀀃􀁇􀁄􀁗􀁈 􀀧􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁌􀁑􀀃􀁐􀁐 􀀔􀀗􀀐􀀓􀀕􀀐􀀕􀀛 􀀔􀀗􀀐􀀓􀀖􀀐􀀓􀀚 􀀓􀀑􀀚 􀀔􀀑􀀔􀀚 􀀔􀀑􀀓􀀚 􀀖􀀑􀀔􀀗 􀀓􀀑􀀗 􀀓􀀑􀀕􀀕 􀀓􀀑􀀔􀀛 􀀖􀀑􀀓􀀕 􀀖􀀑􀀔􀀕 􀀖􀀑􀀘 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 70 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 17. Abbreviations 18. References [1] I2C-bus specification UM10204. Table 27. Abbreviations Acronym Description AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General-Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 71 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 19. Revision history Table 28. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC81XM v.4.3 20140422 Product data sheet - LPC81XM v.4.2 Modifications: • Section 8.20.2 “Clock input” updated for clarity. • CLKIN signal removed from Table 12 “Dynamic characteristic: external clock (XTALIN inputs)”. • Name “SCT” changed to “SCTimer/PWM” for clarity. • Remove slew rate control from GPIO features for clarity. • MRT bus stall mode added. • WWDT clock source corrected in Section 8.17.1. • Pin description table updated for clarification (I2C-bus pins, WAKEUP, RESET). • Added reflow solder diagram and thermal resistance numbers for XSON16 (SOT1341-1). • Table 21: Added Vref(cmp) spec for PIO0_6/VDDCMP. LPC81XM v.4.2 20131210 Product data sheet - LPC81XM v.4.1 Modifications: Corrected vertical axis marker in Figure 21 “CoreMark score”. LPC81XM v.4.1 20131112 Product data sheet - LPC81XM v.4 Modifications: • Corrected XSON16 pin information in Figure 6 and Table 4. LPC81XM v.4 20131025 Product data sheet - LPC81XM v.3.1 Modifications: • Added Section 14.1 “Typical wake-up times”. • Added LPC812M101JTB16 and XSON16 package. LPC81XM v.3.1 20130916 Product data sheet - LPC81XM v.3 Modifications: • Correct the pin interrupt features: Pin interrupts can wake up the part from Sleep mode, Deep-sleep mode, and Power-down mode. See Section 8.11.1. • Table 9 “Static characteristics”: Updated power numbers for Deep-sleep, Power-down, and Deep power-down. • Added 30 MHz data to Figure 13 “Active mode: Typical supply current IDD versus supply voltage VDD”, Figure 14 “Active mode: Typical supply current IDD versus temperature”, and Figure 15 “Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies”. LPC81XM v.3 20130729 Product data sheet - LPC81XM v.2.1 • Operating temperature range changed to 40 °C to 105 °C. • Type numbers updated to reflect the new operating temperature range. See Table 1 “Ordering information” and Table 2 “Ordering options”. • ISP entry pin moved from PIO0_1 to PIO0_12 for TSSOP, and SSOP packages. See Table 4 and Table 6. • Propagation delay values updated in Table 21 “Comparator characteristics”. • SPI characteristics updated. See Section 12.6. • IRC characteristics updated. See Section 12.3. • CoreMark data updated. See Figure 19 and Figure 20. • IRC frequency changed to 12 MHz +/- 1.5 %. See Table 13. • Data sheet status updated to Product data sheet. LPC81XM v.2.1 20130325 Preliminary data sheet - LPC81XM v.2 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 72 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • Editorial updates (temperature sensor removed). • CoreMark data added. See Figure 19 “Active mode: CoreMark power consumption IDD” and Figure 20 “CoreMark score”. • IDD in Deep power-down mode added for condition Low-power oscillator on/WKT wake-up enabled. See Table 10. • Table note 3 updated for Table 4 “Pin description table (fixed pins)”. • Conditions for ter and tprog updated in Table 12 “Flash characteristics”. • Section 13.3 “Internal voltage reference” added. • Typical timing data added for SPI. See Section 12.6. • Typical timing data added for USART in synchronous mode. See Section 12.7. • BOD characterization added. See Section 13.1. • IRC characterization added. See Section 12.3. • Internal voltage reference characteristics added. See Section 13.3. • Data sheet status changed to Preliminary data sheet. LPC81XM v.2 20130128 Objective data sheet - LPC81XM v.1 Modifications: • MTB memory space changed to 1 kB in Figure 6. • Electrical pin characteristics added in Table 10. • Figure 11 “Connecting the SWD pins to a standard SWD connector” added. • Peripheral power consumption added in Table 11. • Table 7 updated. • MRT implementation changed to 31-bit timer. • Power consumption data in active and sleep mode with IRC added. See Figure 13 to Figure 15. • Power consumption (parameter IDD) in active and sleep mode for low-power mode at 12 MHz corrected in Table 10. • Power consumption (parameter IDD) in active and sleep mode at 24 MHz added in Table 10. • Maximum USART speed in synchronous mode changed to 10 Mbit/s. • Section 5 “Marking” added. LPC81XM v.1 20121112 Objective data sheet - - Table 28. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 73 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 20. Legal information 20.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 74 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 75 of 76 continued >> NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 Functional description . . . . . . . . . . . . . . . . . . 13 8.1 ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . 13 8.2 On-chip flash program memory . . . . . . . . . . . 13 8.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5 Nested Vectored Interrupt Controller (NVIC) . 13 8.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13 8.6 System tick timer . . . . . . . . . . . . . . . . . . . . . . 14 8.7 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.8 I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 15 8.8.1 Standard I/O pad configuration . . . . . . . . . . . . 16 8.9 Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . . 17 8.10 Fast General-Purpose parallel I/O (GPIO) . . . 17 8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.11 Pin interrupt/pattern match engine . . . . . . . . . 18 8.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.12 USART0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.13 SPI0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.14 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 20 8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.15 State-Configurable Timer/PWM (SCTimer/PWM) . . . . . . . . . . . . . . . . . . . . . . . 20 8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.16 Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 21 8.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.17 Windowed WatchDog Timer (WWDT) . . . . . . 21 8.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.18 Self Wake-up Timer (WKT). . . . . . . . . . . . . . . 22 8.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.19 Analog comparator (ACMP) . . . . . . . . . . . . . . 22 8.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.20 Clocking and power control . . . . . . . . . . . . . . 24 8.20.1 Crystal and internal oscillators . . . . . . . . . . . . 24 8.20.1.1 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . 25 8.20.1.2 Crystal Oscillator (SysOsc) . . . . . . . . . . . . . . 25 8.20.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc) . . . . . . . . . . . . . . . . . . . . 25 8.20.2 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.20.3 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.20.4 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20.5 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 26 8.20.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20.6.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20.6.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20.6.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27 8.20.6.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 27 8.20.6.5 Deep power-down mode . . . . . . . . . . . . . . . . 27 8.21 System control . . . . . . . . . . . . . . . . . . . . . . . . 28 8.21.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.21.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 28 8.21.3 Code security (Code Read Protection - CRP) 29 8.21.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.21.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.22 Emulation and debugging . . . . . . . . . . . . . . . 30 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Thermal characteristics . . . . . . . . . . . . . . . . . 32 11 Static characteristics . . . . . . . . . . . . . . . . . . . 33 11.1 Power consumption . . . . . . . . . . . . . . . . . . . . 37 11.2 CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 41 11.3 Peripheral power consumption . . . . . . . . . . . 42 11.4 Electrical pin characteristics. . . . . . . . . . . . . . 43 12 Dynamic characteristics. . . . . . . . . . . . . . . . . 46 12.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2 External clock for the oscillator in slave mode 46 12.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47 12.4 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.6 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 50 12.7 USART interface . . . . . . . . . . . . . . . . . . . . . . 53 13 Analog characteristics . . . . . . . . . . . . . . . . . . 54 13.1 BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.2 Internal voltage reference . . . . . . . . . . . . . . . 54 13.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14 Application information . . . . . . . . . . . . . . . . . 58 14.1 Typical wake-up times . . . . . . . . . . . . . . . . . . 58 14.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14.3 XTAL Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 61 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 April 2014 Document identifier: LPC81XM Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 70 18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 71 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 73 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 73 20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 74 21 Contact information. . . . . . . . . . . . . . . . . . . . . 74 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins. The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series. 2. Features and benefits  ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit (MPU) supporting eight regions is included.  ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).  Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.  On-chip SRAM includes:  32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 9.4 — 4 April 2014 Product data sheet LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 2 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller  Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage.  Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.  Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays.  Split APB bus allows high throughput with few stalls between the CPU and DMA.  Serial interfaces:  Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on all parts, see Table 2.)  USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see Table 2.)  Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.  CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.)  SPI controller with synchronous, serial, full duplex communication and programmable data length.  Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.  Three enhanced I2C bus interfaces, one with an open-drain output supporting full I2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.  I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. (Not available on all parts, see Table 2.)  Other peripherals:  70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.  12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.  10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. (Not available on all parts, see Table 2)  Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.  One motor control PWM with support for three-phase motor control. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 3 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller  Quadrature encoder interface that can monitor one external quadrature encoder.  One standard PWM/timer block with external count input.  RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.  WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.  ARM Cortex-M3 system tick timer, including an external clock input option.  Repetitive interrupt timer provides programmable and repeating timed interrupts.  Each peripheral has its own clock divider for further power savings.  Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.  Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.  Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Single 3.3 V power supply (2.4 V to 3.6 V).  Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.  Non-maskable Interrupt (NMI) input.  Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock.  The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes.  Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI).  Brownout detect with separate threshold for interrupt and forced reset.  Power-On Reset (POR).  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.  USB PLL for added flexibility.  Code Read Protection (CRP) with different security levels.  Unique device serial number for identification purposes.  Available as LQFP100 (14 mm  14 mm  1.4 mm), TFBGA1001 (9 mm  9 mm  0.7 mm), and WLCSP100 (5.074  5.074  0.6 mm) package. 1. LPC1768/65 only. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 4 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 3. Applications 4. Ordering information 4.1 Ordering options  eMetering  Alarm systems  Lighting  White goods  Industrial networking  Motor control Table 1. Ordering information Type number Package Name Description Version LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1768UK WLCSP100 wafer level chip-scale package; 100 balls; 5.074  5.074  0.6 mm - LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1766FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1765FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1765FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 Table 2. Ordering options Type number Flash SRAM in kB Ethernet USB CAN I2S DAC Maximum CPU operating frequency CPU AHB SRAM0 AHB SRAM1 Total LPC1769FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 120 MHz LPC1768FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768FET100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768UK 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1767FBD100 512 kB 32 16 16 64 yes no no yes yes 100 MHz LPC1766FBD100 256 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1765FBD100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1765FET100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1764FBD100 128 kB 16 16 - 32 yes Device only 2 no no 100 MHz LPC1763FBD100 256 kB 32 16 16 64 no no no yes yes 100 MHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 5 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 5. Marking The LPC176x devices typically have the following top-side marking: LPC176xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This data sheet covers the following revisions of the LPC176x: Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Table 3. Device revision table Revision identifier (R) Revision description ‘-’ Initial device revision ‘A’ Second device revision ‘B’ Third device revision LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 6 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 6. Block diagram (1) Not available on all parts. See Table 2. Fig 1. Block diagram SRAM 32/64 kB ARM CORTEX-M3 TEST/DEBUG INTERFACE EMULATION TRACE MODULE FLASH ACCELERATOR FLASH 512/256/128 kB DMA CONTROLLER ETHERNET CONTROLLER WITH DMA(1) USB HOST/ DEVICE/OTG CONTROLLER WITH DMA(1) I-code bus D-code bus system bus AHB TO APB BRIDGE 0 HIGH-SPEED GPIO AHB TO APB BRIDGE 1 CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS XTAL1 XTAL2 RESET clocks and controls JTAG interface debug port USB PHY SSP0 UART2/3 I2S(1) I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM QUADRATURE ENCODER SSP1 UART0/1 CAN1/2(1) I2C0/1 SPI0 TIMER 0/1 WDT PWM1 12-bit ADC PIN CONNECT GPIO INTERRUPT CONTROL RTC BACKUP REGISTERS 32 kHz OSCILLATOR APB slave group 0 APB slave group 1 DAC(1) RTC POWER DOMAIN LPC1769/68/67/ 66/65/64/63 master master master 002aad944 slave slave slave slave slave ROM slave MULTILAYER AHB MATRIX P0 to P4 SDA2 SCL2 SCK0 SSEL0 MISO0 MOSI0 SCK1 SSEL1 MISO1 MOSI1 RXD2/3 TXD2/3 PHA, PHB INDEX EINT[3:0] AOUT MCOA[2:0] MCOB[2:0] MCI[2:0] MCABORT 4 × MAT2 2 × MAT3 2 × CAP2 2 × CAP3 3 × I2SRX 3 × I2STX TX_MCLK RX_MCLK RTCX1 RTCX2 VBAT PWM1[7:0] 2 × MAT0/1 2 × CAP0/1 RD1/2 TD1/2 SDA0/1 SCL0/1 AD0[7:0] SCK/SSEL MOSI/MISO 8 × UART1 RXD0/TXD0 P0, P2 PCAP1[1:0] RMII pins USB pins CLKOUT MPU = connected to DMA LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 7 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 7.1 Pinning Fig 2. Pin configuration LQFP100 package Fig 3. Pin configuration TFBGA100 package LPC176xFBD100 50 1 25 75 51 26 76 100 002aad945 002aaf723 LPC1768/65FET100 Transparent top view J G K H F E D C B A 1 2 3 4 5 6 7 8 9 10 ball A1 index area LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 8 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 4. Pin configuration WLCSP100 package Transparent top view 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 LPC1768UK bump A1 index area aaa-009522 Table 4. Pin allocation table TFBGA100 Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 3 VDD(3V3) 4 P1[4]/ENET_TX_EN 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(REG)(3V3) 8 P0[4]/I2SRX_CLK/ RD2/CAP2[0] 9 P0[7]/I2STX_CLK/ SCK1/MAT2[1] 10 P0[9]/I2STX_SDA/ MOSI1/MAT2[3] 11 - 12 - Row B 1 TMS/SWDIO 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 7 VSS 8 P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 - Row C 1 TCK/SWDCLK 2 TRST 3 TDI 4 P0[2]/TXD0/AD0[7] 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK 7 P4[28]/RX_MCLK/ MAT2[0]/TXD3 8 P0[8]/I2STX_WS/ MISO1/MAT2[2] 9 VSS 10 VDD(3V3) 11 - 12 - Row D 1 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] 2 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 3 P0[26]/AD0[3]/ AOUT/RXD3 4 n.c. 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/ TD2/CAP2[1] 8 P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] 9 P2[4]/PWM1[5]/ DSR1/TRACEDATA[1] 10 P2[5]/PWM1[6]/ DTR1/TRACEDATA[0] 11 - 12 - Row E 1 VSSA 2 VDDA 3 VREFP 4 n.c. 5 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] 6 P4[29]/TX_MCLK/ MAT2[1]/RXD3 7 P2[3]/PWM1[4]/ DCD1/TRACEDATA[2] 8 P2[6]/PCAP1[0]/ RI1/TRACECLK LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 9 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 - Row F 1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/ AD0[5] 5 P1[21]/MCABORT/ PWM1[3]/SSEL0 6 P0[18]/DCD1/ MOSI0/MOSI 7 P2[9]/USB_CONNECT/ RXD2 8 P0[16]/RXD1/ SSEL0/SSEL 9 P0[17]/CTS1/ MISO0/MISO 10 P0[15]/TXD1/ SCK0/SCK 11 - 12 - Row G 1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D 5 P1[25]/MCOA1/ MAT1[1] 6 P1[29]/MCOB2/ PCAP1[1]/MAT0[1] 7 VSS 8 P0[21]/RI1/RD1 9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 - Row H 1 P1[30]/VBUS/ AD0[4] 2 XTAL1 3 P3[25]/MAT0[0]/ PWM1[2] 4 P1[18]/USB_UP_LED/ PWM1[1]/CAP1[0] 5 P1[24]/MCI2/ PWM1[5]/MOSI0 6 VDD(REG)(3V3) 7 P0[10]/TXD2/ SDA2/MAT3[0] 8 P2[11]/EINT1/ I2STX_CLK 9 VDD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 10 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7.2 Pin description Row J 1 P0[28]/SCL0/ USB_SCL 2 P0[27]/SDA0/ USB_SDA 3 P0[29]/USB_D+ 4 P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 5 P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 6 VSS 7 P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 8 P0[1]/TD1/RXD3/SCL1 9 P2[13]/EINT3/ I2STX_SDA 10 P2[10]/EINT0/NMI 11 - 12 - Row K 1 P3[26]/STCLK/ MAT0[1]/PWM1[3] 2 VDD(3V3) 3 VSS 4 P1[20]/MCI0/ PWM1[2]/SCK0 5 P1[23]/MCI1/ PWM1[4]/MISO0 6 P1[26]/MCOB1/ PWM1[6]/CAP0[0] 7 P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 8 P0[0]/RD1/TXD3/SDA1 9 P0[11]/RXD2/ SCL2/MAT3[1] 10 P2[12]/EINT2/ I2STX_WS 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Table 5. Pin description Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0]/RD1/TXD3/ SDA1 46 K8 H10 [1] I/O P0[0] — General purpose digital input/output pin. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output. (This is not an I2C-bus compliant open-drain pin). P0[1]/TD1/RXD3/ SCL1 47 J8 H9 [1] I/O P0[1] — General purpose digital input/output pin. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output. (This is not an I2C-bus compliant open-drain pin). P0[2]/TXD0/AD0[7] 98 C4 B1 [2] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. I AD0[7] — A/D converter 0, input 7. P0[3]/RXD0/AD0[6] 99 A2 C3 [2] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. I AD0[6] — A/D converter 0, input 6. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 11 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[4]/ I2SRX_CLK/ RD2/CAP2[0] 81 A8 G2 [1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). I CAP2[0] — Capture input for Timer 2, channel 0. P0[5]/ I2SRX_WS/ TD2/CAP2[1] 80 D7 H1 [1] I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). I CAP2[1] — Capture input for Timer 2, channel 1. P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] 79 B8 G3 [1] I/O P0[6] — General purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. P0[7]/ I2STX_CLK/ SCK1/MAT2[1] 78 A9 J1 [1] I/O P0[7] — General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/ I2STX_WS/ MISO1/MAT2[2] 77 C8 H2 [1] I/O P0[8] — General purpose digital input/output pin. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 76 A10 H3 [1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ SDA2/MAT3[0] 48 H7 H8 [1] I/O P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 12 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[11]/RXD2/ SCL2/MAT3[1] 49 K9 J10 [1] I/O P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15]/TXD1/ SCK0/SCK 62 F10 H6 [1] I/O P0[15] — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ SSEL0/SSEL 63 F8 J5 [1] I/O P0[16] — General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ MISO0/MISO 61 F9 K6 [1] I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ MOSI0/MOSI 60 F6 J6 [1] I/O P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ SDA1 59 G10 K7 [1] I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. I/O SDA1 — I2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[20]/DTR1/SCL1 58 G9 J7 [1] I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. I/O SCL1 — I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21]/RI1/RD1 57 G8 H7 [1] I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). P0[22]/RTS1/TD1 56 H10 K8 [1] I/O P0[22] — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 13 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] 9 E5 D5 [2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[0] — Capture input for Timer 3, channel 0. P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] 8 D1 B4 [2] I/O P0[24] — General purpose digital input/output pin. I AD0[1] — A/D converter 0, input 1. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[1] — Capture input for Timer 3, channel 1. P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 7 D2 A3 [2] I/O P0[25] — General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ AOUT/RXD3 6 D3 C5 [3] I/O P0[26] — General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — DAC output (LPC1769/68/67/66/65/63 only). I RXD3 — Receiver input for UART3. P0[27]/SDA0/ USB_SDA 25 J2 C8 [4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). I/O USB_SDA — USB port I2C serial data (OTG transceiver, LPC1769/68/66/65 only). P0[28]/SCL0/ USB_SCL 24 J1 B9 [4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). I/O USB_SCL — USB port I2C serial clock (OTG transceiver, LPC1769/68/66/65 only). P0[29]/USB_D+ 29 J3 B10 [5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. (LPC1769/68/66/65/64 only). P0[30]/USB_D 30 G4 C9 [5] I/O P0[30] — General purpose digital input/output pin. I/O USB_D — USB bidirectional D line. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 14 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0]/ ENET_TXD0 95 D5 C1 [1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64 only). P1[1]/ ENET_TXD1 94 B4 C2 [1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64 only). P1[4]/ ENET_TX_EN 93 A4 D2 [1] I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. (LPC1769/68/67/66/64 only). P1[8]/ ENET_CRS 92 C5 D1 [1] I/O P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. (LPC1769/68/67/66/64 only). P1[9]/ ENET_RXD0 91 B5 D3 [1] I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[10]/ ENET_RXD1 90 A5 E3 [1] I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[14]/ ENET_RX_ER 89 D6 E2 [1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. (LPC1769/68/67/66/64 only). P1[15]/ ENET_REF_CLK 88 C6 E1 [1] I/O P1[15] — General purpose digital input/output pin. I ENET_REF_CLK — Ethernet reference clock. (LPC1769/68/67/66/64 only). P1[16]/ ENET_MDC 87 A6 F3 [1] I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock (LPC1769/68/67/66/64 only). P1[17]/ ENET_MDIO 86 B6 F2 [1] I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MIIM data input and output. (LPC1769/68/67/66/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 15 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0] 32 H4 D9 [1] I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. (LPC1769/68/66/65/64 only). O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 33 J4 C10 [1] I/O P1[19] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB_PPWR — Port Power enable signal for USB port. (LPC1769/68/66/65 only). I CAP1[1] — Capture input for Timer 1, channel 1. P1[20]/MCI0/ PWM1[2]/SCK0 34 K4 E8 [1] I/O P1[20] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/MCABORT/ PWM1[3]/ SSEL0 35 F5 E9 [1] I/O P1[21] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 36 J5 D10 [1] I/O P1[22] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch, LPC1769/68/66/65 only). O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/MCI1/ PWM1[4]/MISO0 37 K5 E7 [1] I/O P1[23] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/MCI2/ PWM1[5]/MOSI0 38 H5 F8 [1] I/O P1[24] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 16 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[25]/MCOA1/ MAT1[1] 39 G5 F9 [1] I/O P1[25] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. O MAT1[1] — Match output for Timer 1, channel 1. P1[26]/MCOB1/ PWM1[6]/CAP0[0] 40 K6 E10 [1] I/O P1[26] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 43 K7 G9 [1] I/O P1[27] — General purpose digital input/output pin. O CLKOUT — Clock output pin. I USB_OVRCR — USB port Over-Current status. (LPC1769/68/66/65 only). I CAP0[1] — Capture input for Timer 0, channel 1. P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 44 J7 G10 [1] I/O P1[28] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/MCOB2/ PCAP1[1]/ MAT0[1] 45 G6 G8 [1] I/O P1[29] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 1. P1[30]/VBUS/ AD0[4] 21 H1 B8 [2] I/O P1[30] — General purpose digital input/output pin. I VBUS — Monitors the presence of USB bus power. (LPC1769/68/66/65/64 only). Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/SCK1/ AD0[5] 20 F4 C7 [2] I/O P1[31] — General purpose digital input/output pin. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0]/PWM1[1]/ TXD1 75 B9 K1 [1] I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. P2[1]/PWM1[2]/ RXD1 74 B10 J2 [1] I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 17 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[2]/PWM1[3]/ CTS1/ TRACEDATA[3] 73 D8 K2 [1] I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O TRACEDATA[3] — Trace data, bit 3. P2[3]/PWM1[4]/ DCD1/ TRACEDATA[2] 70 E7 K3 [1] I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O TRACEDATA[2] — Trace data, bit 2. P2[4]/PWM1[5]/ DSR1/ TRACEDATA[1] 69 D9 J3 [1] I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACEDATA[1] — Trace data, bit 1. P2[5]/PWM1[6]/ DTR1/ TRACEDATA[0] 68 D10 H4 [1] I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. P2[6]/PCAP1[0]/ RI1/TRACECLK 67 E8 K4 [1] I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. P2[7]/RD2/ RTS1 66 E9 J4 [1] I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8]/TD2/ TXD2 65 E10 H5 [1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). O TXD2 — Transmitter output for UART2. P2[9]/ USB_CONNECT/ RXD2 64 F7 K5 [1] I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. (LPC1769/68/66/65/64 only). I RXD2 — Receiver input for UART2. P2[10]/EINT0/NMI 53 J10 K9 [6] I/O P2[10] — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 18 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[11]/EINT1/ I2STX_CLK 52 H8 J8 [6] I/O P2[11] — General purpose digital input/output pin. I EINT1 — External interrupt 1 input. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[12]/EINT2/ I2STX_WS 51 K10 K10 [6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[13]/EINT3/ I2STX_SDA 50 J9 J9 [6] I/O P2[13] — General purpose digital input/output pin. I EINT3 — External interrupt 3 input. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25]/MAT0[0]/ PWM1[2] 27 H3 D8 [1] I/O P3[25] — General purpose digital input/output pin. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. P3[26]/STCLK/ MAT0[1]/PWM1[3] 26 K1 A10 [1] I/O P3[26] — General purpose digital input/output pin. I STCLK — System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28]/RX_MCLK/ MAT2[0]/TXD3 82 C7 G1 [1] I/O P4[28] — General purpose digital input/output pin. O RX_MCLK — I2S receive master clock. (LPC1769/68/67/66/65 only). O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. P4[29]/TX_MCLK/ MAT2[1]/RXD3 85 E6 F1 [1] I/O P4[29] — General purpose digital input/output pin. O TX_MCLK — I2S transmit master clock. (LPC1769/68/67/66/65 only). O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 19 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller TDO/SWO 1 A1 A1 [1][7] O TDO — Test Data out for JTAG interface. O SWO — Serial wire trace output. TDI 2 C3 C4 [1][8] I TDI — Test Data in for JTAG interface. TMS/SWDIO 3 B1 B3 [1][8] I TMS — Test Mode Select for JTAG interface. I/O SWDIO — Serial wire debug data input/output. TRST 4 C2 A2 [1][8] I TRST — Test Reset for JTAG interface. TCK/SWDCLK 5 C1 D4 [1][7] I TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock. RTCK 100 B2 B2 [1][7] O RTCK — JTAG interface control signal. RSTOUT 14 - - - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the microcontroller being in Reset state. RESET 17 F3 C6 [9] I External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 22 H2 D7 [10][11] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 23 G3 A9 [10][11] O Output from the oscillator amplifier. RTCX1 16 F2 A7 [10][11] I Input to the RTC oscillator circuit. RTCX2 18 G1 B7 [10] O Output from the RTC oscillator circuit. VSS 31, 41, 55, 72, 83, 97 B3, B7, C9, G7, J6, K3 E5, F5, F6, G5, G6, G7 [10] I ground: 0 V reference. VSSA 11 E1 B5 [10] I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD(3V3) 28, 54, 71, 96 K2, H9, C10 , A3 E4, E6, F7, G4 [10] I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. VDD(REG)(3V3) 42, 84 H6, A7 F4, F0 [10] I 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. VDDA 10 E2 A4 [10] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. VREFP 12 E3 A5 [10] I ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 20 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [7] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled. [8] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor. [9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. [11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. VREFN 15 F1 A6 I ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. VBAT 19 G2 A8 [10][12] I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. n.c. 13 D4, E4 B6, D6 - not connected. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 21 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8. Functional description 8.1 Architectural overview Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64/63. The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 8.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website. 8.3 On-chip flash program memory The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. 8.4 On-chip SRAM The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. 8.5 Memory Protection Unit (MPU) The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 22 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to 8 regions each of which can be divided into 8 subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 8.6 Memory map The LPC17xx incorporates several distinct memory regions, shown in the following figures. Figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 23 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (1) Not available on all parts. See Table 2. Fig 5. LPC17xx memory map 0x5000 0000 0x5000 4000 0x5000 8000 0x5000 C000 0x5020 0000 0x5001 0000 AHB peripherals Ethernet controller(1) USB controller(1) reserved 127- 4 reserved GPDMA controller 0 1 2 3 APB0 peripherals 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 C000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4005 C000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 WDT 0x4000 0000 timer 0 timer 1 UART0 UART1 reserved reserved SPI RTC + backup registers GPIO interrupts pin connect SSP1 ADC CAN AF RAM(1) CAN AF registers(1) CAN common(1) CAN1(1) CAN2(1) 22 - 19 reserved I2C1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 reserved reserved 32 kB local SRAM (LPC1769/8/7/6/5/3) 16 kB local SRAM (LPC1764) reserved reserved private peripheral bus 0 GB 0x0000 0000 0.5 GB 4 GB 1 GB 0x0004 0000 0x0002 0000 0x0008 0000 0x1000 4000 0x1000 0000 0x1000 8000 0x1FFF 0000 0x1FFF 2000 0x2008 0000 0x2007 C000 0x2008 4000 0x2200 0000 0x200A 0000 0x2009 C000 0x2400 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x5000 0000 0x5020 0000 0xE000 0000 0xE010 0000 0xFFFF FFFF reserved reserved GPIO reserved reserved reserved reserved APB0 peripherals AHB peripherals APB1 peripherals AHB SRAM bit-band alias addressing peripheral bit-band alias addressing 16 kB AHB SRAM1 (LPC1769/8/7/6/5) 16 kB AHB SRAM0 256 kB on-chip flash (LPC1766/65/63) 128 kB on-chip flash (LPC1764) 512 kB on-chip flash (LPC1769/8/7) PWM1 8 kB boot ROM 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words I-code/D-code memory space 002aad946 APB1 peripherals 0x4008 0000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 0x400F C000 0x4010 0000 SSP0 DAC(1) timer 2 timer 3 UART2 UART3 reserved I2S(1) I2C2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 reserved repetitive interrupt timer 11 12 reserved motor control PWM 30 - 16 reserved 13 14 15 31 system control QEI LPC1769/68/67/66/65/64/63 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 24 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.1 Features • Controls system exceptions and peripheral interrupts • In the LPC17xx, the NVIC supports 33 vectored interrupts • 32 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table • Non-Maskable Interrupt (NMI) • Software interrupt generation 8.7.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 8.8 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 8.9 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. The GPDMA controller allows data transfers between the USB and Ethernet controllers and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC. Two match signals for each timer can be used to trigger DMA transfers. Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The USB controller is available on parts LPC1769/68/66/65/64. The I2S-bus interface is available on parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 25 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 8.10 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC17xx use accelerated GPIO functions: • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. • Support for Cortex-M3 bit banding. • Support for use with the GPDMA controller. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 26 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 8.10.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 8.11 Ethernet Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120 MHz (LPC1769). See Table 2. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 8.11.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x full duplex flow control and half duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 27 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. 8.12 USB interface Remark: The USB controller is available as device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in Section 15.1. 8.12.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. 8.12.1.1 Features • Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 28 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the part can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 8.12.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of a register interface, a serial interface engine, and a DMA controller. The register interface complies with the OHCI specification. 8.12.2.1 Features • OHCI compliant. • One downstream port. • Supports port power switching. 8.12.3 USB OTG controller USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus interface controls an external OTG transceiver. 8.12.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 8.13 CAN controller and acceptance filters Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See Table 2. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 29 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.13.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 8.14 12-bit ADC The LPC17xx contain a single 12-bit successive approximation ADC with eight channels and DMA support. 8.14.1 Features • 12-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range VREFN to VREFP. • 12-bit conversion rate: 200 kHz. • Individual channels can be selected for conversion. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. 8.15 10-bit DAC The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2. 8.15.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive • Dedicated conversion timer • DMA support LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 30 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 8.16.1 Features • Maximum UART data bit rate of 6.25 Mbit/s. • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • Support for RS-485/9-bit/EIA-485 mode (UART1). • UART3 includes an IrDA mode to support infrared communication. • All UARTs have DMA support. 8.17 SPI serial I/O controller The LPC17xx contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 8.17.1 Features • Maximum SPI data bit rate of 12.5 Mbit/s • Compliant with SPI specification • Synchronous, serial, full duplex communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer 8.18 SSP serial I/O controller The LPC17xx contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 31 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 8.18.1 Features • Maximum SSP speed of 50 Mbit/s (master) or 8 Mbit/s (slave) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • DMA transfers supported by GPDMA 8.19 I2C-bus serial I/O controllers The LPC17xx each contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 8.19.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. • I2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 32 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.20 I2S-bus serial I/O controllers Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 8.20.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48, 96) kHz. • Support for an audio master clock. • Configurable word select period in master mode (separately for I2S-bus input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. 8.21 General purpose 32-bit timers/external event counters The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 8.21.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 33 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 8.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 8.22.1 Features • One PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 34 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 8.23 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 8.24 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 8.24.1 Features • Tracks encoder position. • Increments/decrements depending on direction. • Programmable for 2 or 4 position counting. • Velocity capture using built-in timer. • Velocity compare function with “less than” interrupt. • Uses 32-bit registers for position and velocity. • Three position compare registers with interrupts. • Index counter for revolution counting. • Index compare register with interrupts. • Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 35 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 8.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.25.1 Features • 32-bit counter running from PCLK. Counter can be free-running or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 8.26 ARM Cortex-M3 system tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be clocked from the internal AHB clock or from a device pin. 8.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 8.27.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  232  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC) oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 36 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. • Includes lock/safe feature. 8.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC17xx is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V Lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. A clock output function (see Section 8.29.4) makes measuring the oscillator rate easy and accurate. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC17xx is powered off. The RTC includes an alarm function that can wake up the LPC17xx from all reduced power modes with a time resolution of 1 s. 8.28.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. 8.29 Clocking and power control 8.29.1 Crystal oscillators The LPC17xx include three independent oscillators. These are the main oscillator, the IRC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU. Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 37 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller See Figure 6 for an overview of the LPC17xx clock generation. 8.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC17xx use the IRC as the clock source. Software may later switch to one of the other available clock sources. 8.29.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the dedicated USB PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 8.29.2 for additional information. 8.29.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC block, the main PLL, and/or the CPU. Fig 6. LPC17xx clocking generation block diagram MAIN OSCILLATOR INTERNAL RC OSCILLATOR RTC OSCILLATOR MAIN PLL WATCHDOG TIMER REAL-TIME CLOCK CPU CLOCK DIVIDER PERIPHERAL CLOCK GENERATOR USB BLOCK ARM CORTEX-M3 ETHERNET BLOCK DMA GPIO NVIC USB CLOCK DIVIDER system clock select (CLKSRCSEL) USB clock config (USBCLKCFG) CPU clock config (CCLKCFG) pllclk CCLK/8 CCLK/6 CCLK/4 CCLK/2 CCLK pclkWDT rtclk = 1Hz usbclk (48 MHz) cclk USB PLL USB PLL enable main PLL enable 32 kHz APB peripherals LPC17xx 002aad947 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 38 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 is enabled by software only. The program must configure and activate the PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source. 8.29.3 USB PLL (PLL1) The LPC17xx contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main PLL0. The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle. 8.29.4 RTC clock output The LPC17xx feature a clock output function intended for synchronizing with external devices and for use during system development to allow checking the internal clocks CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC clock output allows tuning the RTC frequency without probing the pin, which would distort the results. 8.29.5 Wake-up timer The LPC17xx begin operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 39 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 8.29.6 Power control The LPC17xx support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. The LPC17xx also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 8.29.6.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.29.6.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 40 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 8.29.6.3 Power-down mode Power-down mode does everything that Deep-sleep mode does, but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 8.29.6.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC17xx can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 8.29.6.5 Wake-up interrupt controller The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 8.29.7 Peripheral power control A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 41 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC17xx application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore, there is no power drain from the RTC battery when VDD(REG)(3V3) is available. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 42 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30 System control 8.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see description in Section 8.29.5). The wake-up timer ensures that reset remains asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. Once reset is de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD threshold, the RSTOUT pin goes HIGH. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Fig 7. Power distribution REAL-TIME CLOCK BACKUP REGISTERS REGULATOR 32 kHz OSCILLATOR RTC POWER DOMAIN MAIN POWER DOMAIN 002aad978 RTCX1 VBAT VDD(REG)(3V3) RTCX2 VDD(3V3) VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC ADC POWER DOMAIN VDDA VREFP VREFN VSSA LPC17xx ULTRA LOW-POWER REGULATOR POWER SELECTOR LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 43 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.2 Brownout detection The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 8.30.3 Code security (Code Read Protection - CRP) This feature of the LPC17xx allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. 8.30.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 44 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.5 AHB multilayer matrix The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM blocks. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 8.30.6 External interrupt inputs The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 8.30.7 Memory mapping control The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC17xx is configured for 128 total interrupts. 8.31 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 45 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table 8. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 8) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] See Table 19 for maximum operating voltage. [4] Including voltage on outputs in 3-state mode. [5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail [2] 0.5 +4.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V VDDA analog 3.3 V pad supply voltage [2] 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC [2] 0.5 +4.6 V Vi(VREFP) input voltage on pin VREFP [2] 0.5 +4.6 V VIA analog input voltage on ADC related pins [2][3] 0.5 +5.1 V VI input voltage 5 V tolerant digital I/O pins; VDD  2.4 V [2][4] 0.5 +5.5 VI VDD = 0 V 0.5 +3.6 5 V tolerant open-drain pins PIO0_27 and PIO0_28 [2][5] 0.5 +5.5 IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C - 100 mA Tstg storage temperature [6] 65 +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [7] 4000 +4000 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 46 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C) • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal resistance (15 %) Symbol Parameter Conditions Max/Min Unit LQFP100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 38.01 C/W Single-layer (4.5 in  3 in); still air 55.09 C/W Rth(j-c) thermal resistance from junction to case 9.065 C/W TFBGA100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 55.2 C/W Single-layer (4.5 in  3 in); still air 45.6 C/W Rth(j-c) thermal resistance from junction to case 9.5 C/W Tj = Tamb + PD  Rthj – a LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 47 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supply pins VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.3 3.6 V VDDA analog 3.3 V pad supply voltage [3][4] 2.5 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT [5] 2.1 3.3 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.5 3.3 VDDA V IDD(REG)(3V3) regulator supply current (3.3 V) active mode; code while(1){} executed from flash; all peripherals disabled; PCLK = CCLK⁄8 CCLK = 12 MHz; PLL disabled [6][7]- 7 - mA CCLK = 100 MHz; PLL enabled [6][7]- 42 - mA CCLK = 100 MHz; PLL enabled (LPC1769) [6][8]- 50 - mA CCLK = 120 MHz; PLL enabled (LPC1769) [6][8]- 67 - mA sleep mode [6][9]- 2 - mA deep sleep mode [6][10]- 240 - A power-down mode [6][10]- 31 - A deep power-down mode; RTC running [11]- 630 - nA IBAT battery supply current deep power-down mode; RTC running VDD(REG)(3V3) present [12]- 530 - nA VDD(REG)(3V3) not present [13] - 1.1 - A IDD(IO) I/O supply current deep sleep mode [14][15]- 40 - nA power-down mode [14][15]- 40 - nA deep power-down mode [14]- 10 - nA LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 48 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller IDD(ADC) ADC supply current active mode; ADC powered [16][17]- 1.95 - mA ADC in Power-down mode [16][18]- <0.2 - A deep sleep mode [16]- 38 - nA power-down mode [16]- 38 - nA deep power-down mode [16]- 24 - nA II(ADC) ADC input current on pin VREFP deep sleep mode [19]- 100 - nA power-down mode [19]- 100 - nA deep power-down mode [19]- 100 - nA Standard port pins, RESET, RTCK IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function [20][21] [22] 0 - 5.0 V VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input voltage 0.7VDD(3V3)- - V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA VDD(3V3)  0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(3V3)  0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOHS HIGH-level short-circuit output current VOH = 0 V [23]- - 45 mA IOLS LOW-level short-circuit output current VOL = VDD(3V3) [23]- - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V 15 50 85 A VDD(3V3) < VI < 5 V 0 0 0 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 49 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V  VDD((3V3)  3.6 V. Guaranteed by design. [3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [4] VDDA for DAC specs are from 2.7 V to 3.6 V. I2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3)- - V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05  VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA - - 0.4 V ILI input leakage current VI = VDD(3V3) [24]- 2 4 A VI = 5 V - 10 22 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 - 3.6 V Vo(RTCX2) output voltage on pin RTCX2 0.5 - 3.6 V USB pins (LPC1769/68/66/65/64 only) IOZ OFF-state output current 0 V < VI < 3.3 V [2]- - 10 A VBUS bus supply voltage [2]- - 5.25 V VDI differential input sensitivity voltage (D+)  (D) [2] 0.2 - - V VCM differential common mode voltage range includes VDI range [2] 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage [2] 0.8 - 2.0 V VOL LOW-level output voltage for low-/full-speed RL of 1.5 k to 3.6 V [2]- - 0.18 V VOH HIGH-level output voltage (driven) for low-/full-speed RL of 15 k to GND [2] 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND [2]- - 20 pF ZDRV driver output impedance for driver which is not high-speed capable with 33  series resistor; steady state drive [2][25] 36 - 44.1  Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 50 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [5] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [6] VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. [7] Applies to LPC1768/67/66/65/64/63. [8] Applies to LPC1769 only. [9] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = CCLK⁄8. [10] BOD disabled. [11] On pin VDD(REG)(3V3). IBAT = 530 nA. VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C. [12] On pin VBAT; IDD(REG)(3V3) = 630 nA; VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C. [13] On pin VBAT; VBAT = 3.0 V; Tamb = 25 C. [14] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C. [15] TCK/SWDCLK pin needs to be externally pulled LOW. [16] On pin VDDA; VDDA = 3.3 V; Tamb = 25 C. The ADC is powered if the PDN bit in the AD0CR register is set to 1 and in Power-down mode of the PDN bit is set to 0. [17] The ADC is powered if the PDN bit in the AD0CR register is set to 1. See LPC17xx user manual UM10360_1. [18] The ADC is in Power-down mode if the PDN bit in the AD0CR register is set to 0. See LPC17xx user manual UM10360_1. [19] Vi(VREFP) = 3.3 V; Tamb = 25 C. [20] Including voltage on outputs in 3-state mode. [21] VDD(3V3) supply voltages must be present. [22] 3-state outputs go into 3-state mode in Deep power-down mode. [23] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [24] To VSS. [25] Includes external resistors of 33   1 % on D+ and D. 11.1 Power consumption Conditions: BOD disabled. Fig 8. Deep-sleep mode: typical regulator supply current IDD(Reg)(3V3) versus temperature 002aaf568 temperature (°C) −40 −15 10 35 60 85 250 350 300 400 IDD(Reg)(3V3) (μA) 200 3.6 V 3.3 V 2.4 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 51 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: BOD disabled. Fig 9. Power-down mode: Typical regulator supply current IDD(Reg)(3V3) versus temperature Conditions: VDD(REG)(3V3) floating; RTC running. Fig 10. Deep power-down mode: Typical battery supply current IBAT versus temperature 002aaf569 40 80 120 0 temperature (°C) −40 −15 10 35 60 85 IDD(Reg)(3V3) (μA) 3.6 V 3.3 V 2.4 V 002aag119 1.0 1.4 1.8 0.6 temperature (°C) -40 -15 10 35 60 85 IBAT) (μA) Vi(VBAT) = 3.6 V 3.3 V 3.0 V 2.4 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 52 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: VBAT = 3.0 V; VDD(REG)(3V3) = 3.0 V; RTC running. Fig 11. Deep power-down mode: Typical regulator supply current IDD(REG)(3V3) and battery supply current IBAT versus temperature 002aag120 temperature (°C) -40 -15 10 35 60 85 0.8 1.6 0.4 1.2 2.0 0 IDD(REG)(3V3) IBAT IDD(REG)(3V3)/IBAT (μA) LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 53 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock PCLK = CCLK/4. [1] The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately. Table 9. Power consumption for individual analog and digital blocks Peripheral Conditions Typical supply current in mA; CCLK = Notes 12 MHz 48 MHz 100 MHz Timer 0.03 0.11 0.23 Average current per timer UART 0.07 0.26 0.53 Average current per UART PWM 0.05 0.20 0.41 Motor control PWM 0.05 0.21 0.42 I2C 0.02 0.08 0.16 Average current per I2C SPI 0.02 0.06 0.13 SSP1 0.04 0.16 0.32 ADC PCLK = 12 MHz for CCLK = 12 MHz and 48 MHz; PCLK = 12.5 MHz for CCLK = 100 MHz 2.12 2.09 2.07 CAN PCLK = CCLK/6 0.13 0.49 1.00 Average current per CAN CAN0, CAN1, acceptance filter PCLK = CCLK/6 0.22 0.85 1.73 Both CAN blocks and acceptance filter[1] DMA PCLK = CCLK 1.33 5.10 10.36 QEI 0.05 0.20 0.41 GPIO 0.33 1.27 2.58 I2S 0.09 0.34 0.70 USB and PLL1 0.94 1.32 1.94 Ethernet Ethernet block enabled in the PCONP register; Ethernet not connected. 0.49 1.87 3.79 Ethernet connected Ethernet initialized, connected to network, and running web server example. - - 5.19 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 54 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11.3 Electrical pin characteristics Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL IOH (mA) 0 8 16 24 002aaf112 2.8 2.4 3.2 3.6 VOH (V) 2.0 T = 85 °C 25 °C −40 °C VOL (V) 0 0.2 0.4 0.6 002aaf111 5 10 15 IOL (mA) 0 T = 85 °C 25 °C −40 °C LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 55 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 14. Typical pull-up current Ipu versus input voltage VI Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15. Typical pull-down current Ipd versus input voltage VI 0 1 2 3 4 5 002aaf108 −30 −50 −10 10 Ipu (μA) −70 T = 85 °C 25 °C −40 °C VI (V) 002aaf109 VI (V) 0 1 2 3 4 5 10 70 50 30 90 Ipd (μA) −10 T = 85 °C 25 °C −40 °C LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 56 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12. Dynamic characteristics 12.1 Flash memory [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 12.2 External clock [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Table 10. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 100000 - cycles tret retention time powered 10 - - years unpowered 20 - - years ter erase time sector or multiple consecutive sectors 95 100 105 ms tprog programming time [2] 0.95 1 1.05 ms Table 11. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Fig 16. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 57 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.3 Internal oscillators [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 12.4 I/O pins [1] Applies to standard I/O pins. Table 12. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz fi(RTC) RTC input frequency - - 32.768 - kHz Conditions: Frequency values are typical values. 4 MHz  1 % accuracy is guaranteed for 2.7 V  VDD(REG)(3V3)  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 4 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 17. Internal RC oscillator frequency versus temperature 002aaf107 temperature (°C) -40 -15 10 35 60 85 4.024 4.032 4.020 4.028 4.036 fosc(RC) (MHz) 4.016 VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V Table 13. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 58 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.5 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [7] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see the I2C-bus specification UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Table 14. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz tf fall time [3][4][5][6] of both SDA and SCL signals Standard-mode - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s tHD;DAT data hold time [3][7][8] Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 59 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.6 I2S-bus interface Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. [1] CCLK = 20 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK⁄4; I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK signal in the I2S-bus specification. Fig 18. I2C-bus pins clock timing 002aaf425 tf 70 % SDA 30 % tf 70 % 30 % S 70 % 30 % 70 % 30 % tHD;DAT SCL 1 / fSCL 70 % 30 % 70 % 30 % tVD;DAT tHIGH tLOW tSU;DAT Table 15. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time [1] - - 35 ns tf fall time [1] - - 35 ns tWH pulse width HIGH on pins I2STX_CLK and I2SRX_CLK [1] 0.495  Tcy(clk) - - - tWL pulse width LOW on pins I2STX_CLK and I2SRX_CLK [1] - - 0.505  Tcy(clk) ns output tv(Q) data output valid time on pin I2STX_SDA [1] - - 30 ns on pin I2STX_WS [1] - - 30 ns input tsu(D) data input set-up time on pin I2SRX_SDA [1] 3.5 - - ns th(D) data input hold time on pin I2SRX_SDA [1] 4.0 - - ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 60 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 19. I2S-bus timing (output) Fig 20. I2S-bus timing (input) 002aad992 I2STX_CLK I2STX_SDA I2STX_WS Tcy(clk) tf tr tWH tWL tv(Q) tv(Q) 002aae159 Tcy(clk) tf tr tWH tsu(D) th(D) tsu(D) tsu(D) tWL I2SRX_CLK I2SRX_SDA I2SRX_WS LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 61 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.7 SSP interface [1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz. Table 16. Dynamic characteristic: SSP interface Tamb = 25C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit SSP interface tsu(SPI_MISO) SPI_MISO set-up time measured in SPI Master mode; see Figure 21 [1] 30 - ns Fig 21. MISO line set-up time in SSP Master mode tsu(SPI_MISO) SCK shifting edges MOSI MISO 002aad326 sampling edges LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 62 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.8 USB interface Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. [1] Characterized but not implemented as production test. Guaranteed by design. Table 17. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3); 3.0 V  VDD(3V3)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 22 160 - 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 22 2 - +5 ns tJR1 receiver jitter to next transition 18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns tEOPR1 EOP width at receiver must reject as EOP; see Figure 22 [1] 40 - - ns tEOPR2 EOP width at receiver must accept as EOP; see Figure 22 [1] 82 - - ns Fig 22. Differential data-to-EOP transition skew and EOP width 002aab561 TPERIOD differential data lines crossover point source EOP width: tFEOPT receiver EOP width: tEOPR1, tEOPR2 crossover point extended differential data to SE0/EOP skew n × TPERIOD + tFDEOP LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 63 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.9 SPI [1] TSPICYC = (Tcy(PCLK)  n)  0.5 %, n is the SPI clock divider value (n  8); PCLK is derived from the processor clock CCLK. [2] Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %) edge of the data signal (MOSI or MISO). Table 18. Dynamic characteristics of SPI pins Tamb = 40 C to +85 C. Symbol Parameter Min Typ Max Unit Tcy(PCLK) PCLK cycle time 10 - - ns TSPICYC SPI cycle time [1] 79.6 - - ns tSPICLKH SPICLK HIGH time 0.485  TSPICYC - - ns tSPICLKL SPICLK LOW time - 0.515  TSPICYC ns SPI master tSPIDSU SPI data set-up time [2] 0 - - ns tSPIDH SPI data hold time [2] 2  Tcy(PCLK)  5 - - ns tSPIQV SPI data output valid time [2] 2  Tcy(PCLK) + 30 - - ns tSPIOH SPI output data hold time [2] 2  Tcy(PCLK) + 5 - - ns SPI slave tSPIDSU SPI data set-up time [2] 0 - - ns tSPIDH SPI data hold time [2] 2  Tcy(PCLK) + 5 - - ns tSPIQV SPI data output valid time [2] 2  Tcy(PCLK) + 35 - - ns tSPIOH SPI output data hold time [2] 2  Tcy(PCLK) + 15 - - ns Fig 23. SPI master timing (CPHA = 1) SCK (CPOL = 0) MOSI MISO 002aad986 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 64 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 24. SPI master timing (CPHA = 0) Fig 25. SPI slave timing (CPHA = 1) SCK (CPOL = 0) MOSI MISO 002aad987 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID tSPIQV SCK (CPOL = 0) MOSI MISO 002aad988 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 65 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 13. ADC electrical characteristics [1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 27. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 27. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 27. [6] ADCOFFS value (bits 7:4) = 2 in the ADTRM register. See LPC17xx user manual UM10360. [7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 27. [8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 27. [9] See Figure 28. [10] The conversion frequency corresponds to the number of samples per second. Fig 26. SPI slave timing (CPHA = 0) SCK (CPOL = 0) MOSI MISO 002aad989 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID Table 19. ADC characteristics (full resolution) VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution.[1] Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA V Cia analog input capacitance - - 15 pF ED differential linearity error [2][3]- - 1 LSB EL(adj) integral non-linearity [4]- - 3 LSB EO offset error [5][6]- - 2 LSB EG gain error [7]- - 0.5 % ET absolute error [8]- - 4 LSB Rvsi voltage source interface resistance [9]- - 7.5 k fclk(ADC) ADC clock frequency - - 13 MHz fc(ADC) ADC conversion frequency [10]- - 200 kHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 66 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 27. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 27. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 27. [6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 27. [7] The conversion frequency corresponds to the number of samples per second. Table 20. ADC characteristics (lower resolution) Tamb = 40 C to +85 C unless otherwise specified; 12-bit ADC used as 10-bit resolution ADC.[1] Symbol Parameter Conditions Min Typ Max Unit ED differential linearity error [2][3] - 1 - LSB EL(adj) integral non-linearity [4] - 1.5 - LSB EO offset error [5] - 2 - LSB EG gain error [6] - 2 - LSB fclk(ADC) ADC clock frequency 3.0 V  VDDA  3.6 V - - 33 MHz 2.7 V  VDDA < 3.0 V - - 25 MHz fc(ADC) ADC conversion frequency 3 V  VDDA  3.6 V [7]- - 500 kHz 2.7 V  VDDA < 3.0 V [7]- - 400 kHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 67 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 27. 12-bit ADC characteristics 002aad948 4095 4094 4093 4092 4091 (2) (1) 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 LSB (ideal) code out VREFP − VREFN 4096 offset error EO gain error EG offset error EO VIA (LSBideal) 1 LSB = LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 68 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 14. DAC electrical characteristics Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2. The values of resistor components Ri1 and Ri2 vary with temperature and input voltage and are process-dependent (see Table 21). Parasitic resistance and capacitance from the pad are not included in this figure. Fig 28. ADC interface to pins AD0[n] Table 21. ADC interface components Component Range Description Ri1 2 k to 5.2 k Switch-on resistance for channel selection switch. Varies with temperature, input voltage, and process. Ri2 100  to 600  Switch-on resistance for the comparator input switch. Varies with temperature, input voltage, and process. C1 750 fF Parasitic capacitance from the ADC block level. C2 65 fF Parasitic capacitance from the ADC block level. C3 2.2 pF Sampling capacitor. LPC17xx AD0[n] 750 fF 65 fF Cia 2.2 pF Rvsi Ri2 100 Ω - 600 Ω Ri1 2 kΩ - 5.2 kΩ VSS VEXT 002aaf197 ADC COMPARATOR BLOCK C1 C3 C2 Table 22. DAC electrical characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit ED differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.6 - % CL load capacitance - 200 - pF RL load resistance 1 - - k LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 69 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15. Application information 15.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. If the LPC1769/68/67/66/65/64/63 VDD is always greater than 0 V while VBUS = 5 V, the VBUS pin can be connected directly to the VBUS pin on the USB connector. This applies to bus powered devices where the USB cable supplies the system power. For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken to reduce the voltage to below 3.6 V. The maximum allowable voltage on the VBUS pin is 3.6 V. One method is to use a voltage divider to connect the VBUS pin to the VBUS on the USB connector. The voltage divider ratio should be such that the VBUS pin will be greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allowable maximum voltage. Use the following operating conditions: VBUSmax = 5.25 V VDD = 3.6 V The voltage divider would need to provide a reduction of 3.6 V/5.25 V or ~0.686 V. Fig 29. USB interface on a bus-powered device LPC17xx VDD(3V3) R1 1.5 kΩ R2 USB_UP_LED 002aad940 USB-B connector USB_D+ USB_D− VBUS VSS RS = 33 Ω RS = 33 Ω LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 70 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 30. USB interface on a bus-powered device where VBUS = 5 V, VDD not present LPC17xx VDD R1 1.5 kΩ R2 R3 USB-B connector USB_D+ USB_DUSB_ VBUS VSS RS = 33 Ω RS = 33 Ω aaa-008962 R2 USB_UP_LED Fig 31. USB interface with soft-connect LPC17xx USB-B connector USB_D+ USB_CONNECT SoftConnect switch USB_D− VBUS VSS VDD(3V3) R1 1.5 kΩ RS = 33 Ω 002aad939 RS = 33 Ω USB_UP_LED LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 71 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 32. USB OTG port configuration USB_D+ USB_D− USB_SDA USB_SCL RSTOUT LPC17xx Mini-AB connector 33 Ω 33 Ω VDD VDD 002aad941 EINTn RESET_N ADR/PSW SPEED SUSPEND OE_N/INT_N SCL SDA INT_N VBUS ID DP DM ISP1302 VSS USB_UP_LED VDD Fig 33. USB host port configuration USB_UP_LED USB_D+ USB_D− USB_PWRD LPC17xx 15 kΩ 15 kΩ USB-A connector 33 Ω 33 Ω 002aad942 VDD USB_OVRCR USB_PPWR LM3526-L ENA IN 5 V FLAGA OUTA VDD D+ D− VBUS VSS LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 72 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 35), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 36 and in Table 23 and Table 24. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 36 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer. Fig 34. USB device port configuration LPC17xx USB-B connector 33 Ω 33 Ω 002aad943 USB_UP_LED USB_CONNECT VDD VDD D+ D− USB_D+ USB_D− VBUS VBUS VSS Fig 35. Slave mode operation of the on-chip oscillator LPC1xxx XTAL1 Ci 100 pF Cg 002aae835 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 73 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in Fig 36. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 23. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1/CX2 1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF Table 24. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF 002aaf424 LPC1xxx XTALIN XTALOUT CX1 CX2 XTAL = CL CP RS L LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 74 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 15.4 Standard I/O pin configuration Figure 37 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver: Open-drain mode enabled/disabled • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. Fig 37. Standard I/O pin configuration with analog input PIN VDD VDD ESD VSS ESD strong pull-up strong pull-down VDD weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aaf272 pin configured as digital output driver pin configured as digital input pin configured as analog input LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 75 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.5 Reset pin configuration Fig 38. Reset pin configuration VSS reset 002aaf274 VDD VDD VDD Rpu ESD ESD 20 ns RC GLITCH FILTER PIN LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 76 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for part LPC1768. [1] IEC levels refer to Appendix D in the IEC61967-2 Specification. Table 25. ElectroMagnetic Compatibility (EMC) for part LPC1768 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C. Parameter Frequency band System clock = Unit 12 MHz 24 MHz 48 MHz 72 MHz 100 MHz Input clock: IRC (4 MHz) maximum peak level 150 kHz to 30 MHz 7 6 4 7 7 dBV 30 MHz to 150 MHz +1 +5 +11 +16 +9 dBV 150 MHz to 1 GHz 2 +4 +11 +12 +19 dBV IEC level[1] - O O N M L - Input clock: crystal oscillator (12 MHz) maximum peak level 150 kHz to 30 MHz 5 4 4 7 8 dBV 30 MHz to 150 MHz 1 +5 +10 +15 +7 dBV 150 MHz to 1 GHz 1 +6 +11 +10 +16 dBV IEC level[1] - O O N M M - LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 77 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 16. Package outline Fig 39. Package outline SOT407-1 (LQFP100) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o 1 0.2 0.08 0.08 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT407-1 136E20 MS-026 00-02-01 03-02-20 D(1) (1) (1) 14.1 13.9 HD 16.25 15.75 Z E 1.15 0.85 D bp e θ E A1 A Lp detail X L (A 3 ) B 25 c HD bp HE A2 v M B D ZD A ZE e v M A X 1 100 76 75 51 50 26 y pin 1 index w M w M 0 5 10 mm scale LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 78 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 40. Package outline SOT926-1 (TFBGA100) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT926-1 - - - - - - - - - SOT926-1 05-12-09 05-12-22 UNIT A max mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 A1 DIMENSIONS (mm are the original dimensions) TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm A2 b D E e2 7.2 e 0.8 e1 7.2 v 0.15 w 0.05 y 0.08 y1 0.1 0 2.5 5 mm scale b e2 e1 e e 1/2 e 1/2 e ∅ v M C A B ∅ w M C ball A1 index area A B C D E F H K G J 1 2 3 4 5 6 7 8 9 10 ball A1 index area B A E D C y1 C y X detail X A A1 A2 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 79 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 41. Package outline LPC1768UK (WLCSP100) Outline References version European projection Issue date IEC JEDEC JEITA wlcsp100_lpc1768uk_po Unit mm max nom min 0.65 0.60 0.55 0.27 0.24 0.21 0.35 0.32 0.29 5.104 5.074 5.044 5.104 5.074 5.044 4.5 4.5 0.15 A Dimensions (mm are the original dimensions) A1 A2 0.385 0.360 0.335 b D E 0.05 e y 0.5 e1 e2 v 0.05 w ball A1 index area X detail X C y A A2 A1 ball A1 index area LPC1768UK 11-10-19 13-11-04 WLCSP100: wafer level chip-scale package; 100 balls; 5.074 x 5.074 x 0.6 mm LPC1768UK 0 scale 3 mm D B E A 1 K J H G F E D C B A 2 3 4 5 6 7 8 9 10 e1 e b Ø v C A B Ø w C 1/2 e e2 e 1/2 e LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 80 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 17. Soldering Fig 42. Reflow soldering for the LQFP100 package SOT407-1 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP100 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy sot407-1 solder land C Generic footprint pattern Refer to the package outline drawing for actual layout 0.500 0.560 17.300 17.300 14.300 14.300 1.500 0.280 0.400 14.500 14.500 17.550 17.550 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 81 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 43. Reflow soldering of the TFBGA100 package DIMENSIONS in mm P SL SP SR Hx Hy Hx Hy SOT926-1 solder land plus solder paste occupied area Footprint information for reflow soldering of TFBGA100 package solder land solder paste deposit solder resist P P SL SP SR Generic footprint pattern Refer to the package outline drawing for actual layout detail X see detail X sot926-1_fr 0.80 0.330 0.400 0.480 9.400 9.400 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 82 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 18. Abbreviations Table 26. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter DMA Direct Memory Access EOP End Of Packet GPIO General Purpose Input/Output IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group MAC Media Access Control MIIM Media Independent Interface Management OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLL Phase-Locked Loop PWM Pulse Width Modulator RIT Repetitive Interrupt Timer RMII Reduced Media Independent Interface SE0 Single Ended Zero SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TCM Tightly Coupled Memory TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 83 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 19. Revision history Table 27. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1769_68_67_66_65_64_63 v.9.4 20140404 Product data sheet - LPC1769_68_67_66_65_64 v.9.3 Modifications: • Added LPC1768UK. • Table 5 “Pin description”: Changed RX_MCLK and TX_MCLK type from INPUT to OUTPUT. LPC1769_68_67_66_65_64_63 v.9.3 20140108 Product data sheet - LPC1769_68_67_66_65_64 v.9.2 Modifications: • Table 7 “Thermal resistance (±15 %)”: – Added TFBGA100. – Added 15 % to table title. LPC1769_68_67_66_65_64_63 v.9.2 20131021 Product data sheet - LPC1769_68_67_66_65_64 v.9.1 Modifications: • Table 8 “Static characteristics”: – Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” – Added Table note 4 “VDDA for DAC specs are from 2.7 V to 3.6 V.” – VDDA/VREFP spec changed from 2.7 V to 2.5 V. • Table 19 “ADC characteristics (full resolution)”: – Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” – VDDA changed from 2.7 V to 2.5 V. • Table 20 “ADC characteristics (lower resolution)”: Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” LPC1769_68_67_66_65_64_63 v.9.1 20130916 Product data sheet - LPC1769_68_67_66_65_64 v.9 Modifications: • Added Table 7 “Thermal resistance”. • Table 6 “Limiting values”: – Updated min/max values for VDD(3V3) and VDD(REG)(3V3). – Updated conditions for VI. – Updated table notes. • Table 8 “Static characteristics”: Added Table note 15 “TCK/SWDCLK pin needs to be externally pulled LOW.” • Updated Section 15.1 “Suggested USB interface solutions”. • Added Section 5 “Marking”. • Changed title of Figure 31 from “USB interface on a self-powered device” to “USB interface with soft-connect”. LPC1769_68_67_66_65_64_63 v.9 20120810 Product data sheet - LPC1769_68_67_66_65_64 v.8 Modifications: • Remove table note “The peak current is limited to 25 times the corresponding maximum current.” from Table 5 “Limiting values”. • Change VDD(3V3) to VDD(REG)(3V3) in Section 11.3 “Internal oscillators”. • Glitch filter constant changed to 10 ns in Table note 6 in Table 4. • Description of RESET function updated in Table 4. • Pull-up value added for GPIO pins in Table 4. • Pin configuration diagram for LQFP100 package corrected (Figure 2). LPC1769_68_67_66_65_64_63 v.8 20111114 Product data sheet - LPC1769_68_67_66_65_64 v.7 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 84 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Modifications: • Pin description of USB_UP_LED pin updated in Table 4. • Ri1 and Ri2 labels in Figure 27 updated. • Part LPC1765FET100 added. • Table note 10 updated in Table 4. • Table note 1 updated in Table 12. • Pin description of STCLK pin updated in Table 4. • Electromagnetic compatibility data added in Section 14.6. • Section 16 added. LPC1769_68_67_66_65_64_63 v.7 20110405 Product data sheet - LPC1769_68_67_66_65_64 v.6 Modifications: • Pin description of pins P0[29] and P0[30] updated in Table note 5 of Table 4. Pins are not 5 V tolerant. • Typical value for Parameter Nendu added in Table 9. • Parameter Vhys for I2C bus pins: typical value corrected Vhys = 0.05VDD(3V3) in Table 7. • Condition 3.0 V  VDD(3V3)  3.6 V added in Table 16. • Typical values for parameters IDD(REG)(3V3) and IBAT with condition Deep power-down mode corrected in Table 7 and Table note 9, Table note 10, and Table note 11 updated. • For Deep power-down mode, Figure 9 updated and Figure 10 added. LPC1769_68_67_66_65_64_63 v.6 20100825 Product data sheet - LPC1769_68_67_66_65_64 v.5 Modifications: • Part LPC1768TFBGA added. • Section 7.30.2; BOD level corrected. • Added Section 10.2. LPC1769_68_67_66_65_64_63 v.5 20100716 Product data sheet - LPC1769_68_67_66_65_64 v.4 LPC1769_68_67_66_65_64 v.4 20100201 Product data sheet - LPC1768_67_66_65_64 v.3 LPC1768_67_66_65_64 v.3 20091119 Product data sheet - LPC1768_66_65_64 v.2 LPC1768_66_65_64 v.2 20090211 Objective data sheet - LPC1768_66_65_64 v.1 LPC1768_66_65_64 v.1 20090115 Objective data sheet - - Table 27. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 85 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 20. Legal information 20.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 86 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 87 of 88 continued >> NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 21 8.1 Architectural overview . . . . . . . . . . . . . . . . . . 21 8.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 21 8.3 On-chip flash program memory . . . . . . . . . . . 21 8.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 Memory Protection Unit (MPU). . . . . . . . . . . . 21 8.6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.7 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 24 8.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 24 8.9 General purpose DMA controller . . . . . . . . . . 24 8.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.10 Fast general purpose parallel I/O . . . . . . . . . . 25 8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 27 8.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.2 USB host controller . . . . . . . . . . . . . . . . . . . . 28 8.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 28 8.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.13 CAN controller and acceptance filters . . . . . . 28 8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 30 8.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 30 8.18.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19 I2C-bus serial I/O controllers . . . . . . . . . . . . . 31 8.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 32 8.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 33 8.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 34 8.24 Quadrature Encoder Interface (QEI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.25 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 35 8.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.26 ARM Cortex-M3 system tick timer . . . . . . . . . 35 8.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 35 8.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.28 RTC and backup registers . . . . . . . . . . . . . . . 36 8.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.29 Clocking and power control . . . . . . . . . . . . . . 36 8.29.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 36 8.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 37 8.29.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37 8.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37 8.29.2 Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 38 8.29.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 38 8.29.4 RTC clock output . . . . . . . . . . . . . . . . . . . . . . 38 8.29.5 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 38 8.29.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 40 8.29.6.4 Deep power-down mode . . . . . . . . . . . . . . . . 40 8.29.6.5 Wake-up interrupt controller . . . . . . . . . . . . . 40 8.29.7 Peripheral power control . . . . . . . . . . . . . . . . 40 8.29.8 Power domains . . . . . . . . . . . . . . . . . . . . . . . 41 8.30 System control . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 43 8.30.3 Code security (Code Read Protection - CRP) . . . . . . . . . . . 43 8.30.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.30.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 44 8.30.6 External interrupt inputs . . . . . . . . . . . . . . . . . 44 8.30.7 Memory mapping control . . . . . . . . . . . . . . . . 44 8.31 Emulation and debugging . . . . . . . . . . . . . . . 44 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 April 2014 Document identifier: LPC1769_68_67_66_65_64_63 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Thermal characteristics . . . . . . . . . . . . . . . . . 46 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 47 11.1 Power consumption . . . . . . . . . . . . . . . . . . . . 50 11.2 Peripheral power consumption . . . . . . . . . . . . 53 11.3 Electrical pin characteristics . . . . . . . . . . . . . . 54 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 56 12.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.3 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 57 12.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.6 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 59 12.7 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.8 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 62 12.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 ADC electrical characteristics . . . . . . . . . . . . 65 14 DAC electrical characteristics . . . . . . . . . . . . 68 15 Application information. . . . . . . . . . . . . . . . . . 69 15.1 Suggested USB interface solutions . . . . . . . . 69 15.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 73 15.4 Standard I/O pin configuration . . . . . . . . . . . . 74 15.5 Reset pin configuration. . . . . . . . . . . . . . . . . . 75 15.6 ElectroMagnetic Compatibility (EMC) . . . . . . . 76 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 77 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 82 19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 83 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 85 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 85 20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 21 Contact information. . . . . . . . . . . . . . . . . . . . . 86 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1. General description The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire bidirectional I2C-bus (serial clock (SCL), serial data (SDA)). The devices consist of eight quasi-bidirectional ports, 100 kHz I2C-bus interface, three hardware address inputs and interrupt output operating between 2.5 V and 6 V. The quasi-bidirectional port can be independently assigned as an input to monitor interrupt status or keypads, or as an output to activate indicator devices such as LEDs. System master can read from the input port or write to the output port through a single register. The low current consumption of 2.5 A (typical, static) is great for mobile applications and the latched output ports directly drive LEDs. The PCF8574 and PCF8574A are identical, except for the different fixed portion of the slave address. The three hardware address pins allow eight of each device to be on the same I2C-bus, so there can be up to 16 of these I/O expanders PCF8574/74A together on the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs). The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic of the microcontroller and is activated when any input state differs from its corresponding input port register state. It is used to indicate to the microcontroller that an input state has changed and the device needs to be interrogated without the microcontroller continuously polling the input register via the I2C-bus. The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal pull-up 100 A current source. 2. Features and benefits  I2C-bus to parallel port expander  100 kHz I2C-bus interface (Standard-mode I2C-bus)  Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD with 100 A current source  8-bit remote I/O pins that default to inputs at power-up  Latched outputs directly drive LEDs  Total package sink capability of 80 mA  Active LOW open-drain interrupt output  Eight programmable slave addresses using three address pins  Low standby current (2.5 A typical)  40 C to +85 C operation  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt Rev. 5 — 27 May 2013 Product data sheet PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 2 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt  Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA  Packages offered: DIP16, SO16, SSOP20 3. Applications  LED signs and displays  Servers  Key pads  Industrial control  Medical equipment  PLC  Cellular telephones  Mobile devices  Gaming machines  Instrumentation and test measurement 4. Ordering information 4.1 Ordering options Table 1. Ordering information Type number Topside mark Package Name Description Version PCF8574P PCF8574P DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 PCF8574AP PCF8574AP PCF8574T/3 PCF8574T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 PCF8574AT/3 PCF8574AT PCF8574TS/3 8574TS SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 PCF8574ATS/3 8574A Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature range PCF8574P PCF8574P,112 DIP16 Standard marking * IC’s tube - DSC bulk pack 1000 Tamb = 40 C to +85 C PCF8574AP PCF8574AP,112 DIP16 Standard marking * IC’s tube - DSC bulk pack 1000 Tamb = 40 C to +85 C PCF8574T/3 PCF8574T/3,512 SO16 Standard marking * tube dry pack 1920 Tamb = 40 C to +85 C PCF8574T/3,518 SO16 Reel 13” Q1/T1 *standard mark SMD dry pack 1000 Tamb = 40 C to +85 C PCF8574AT/3 PCF8574AT/3,512 SO16 Standard marking * tube dry pack 1920 Tamb = 40 C to +85 C PCF8574AT/3,518 SO16 Reel 13” Q1/T1 *standard mark SMD dry pack 1000 Tamb = 40 C to +85 C PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 3 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 5. Block diagram PCF8574TS/3 PCF8574TS/3,112 SSOP20 Standard marking * IC’s tube - DSC bulk pack 1350 Tamb = 40 C to +85 C PCF8574TS/3,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCF8574ATS/3 PCF8574ATS/3,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C Table 2. Ordering options …continued Type number Orderable part number Package Packing method Minimum order quantity Temperature range Fig 1. Block diagram Fig 2. Simplified schematic diagram of P0 to P7 002aad624 INT I2C-BUS CONTROL LP FILTER PCF8574 PCF8574A INTERRUPT LOGIC A0 A1 A2 INPUT FILTER SHIFT REGISTER SDA SCL 8 bits write pulse read pulse POWER-ON VDD RESET VSS I/O PORT P0 P1 P2 P3 P4 P5 P6 P7 002aac109 write pulse read pulse D CI S FF Q power-on reset data from Shift Register Itrt(pu) 100 μA IOH IOL VDD P0 to P7 VSS D CI S FF Q data to Shift Register to interrupt logic PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 4 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 3. Pin configuration for DIP16 Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for SSOP20 PCF8574P PCF8574AP A0 VDD A1 SDA A2 SCL P0 INT P1 P7 P2 P6 P3 P5 VSS P4 002aad625 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 A0 VDD A1 SDA A2 SCL P0 INT P1 P7 P2 P6 P3 P5 VSS P4 PCF8574T/3 PCF8574AT/3 002aad626 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 PCF8574TS/3 PCF8574ATS/3 P7 SCL P6 n.c. n.c. SDA P5 P4 A0 A1 P3 n.c. n.c. A2 P2 P0 P1 002aad627 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 VDD INT VSS