Lattice Sub-LVDS Signaling Using Lattice Devices April 2013 Technical Note TN1210
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DIODE-ZENER-1.5W-15V..> 14-Dec-2012 08:42 3.1K
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DIODE-ZENER-500MW-11..> 14-Dec-2012 08:39 3.2K
DIODE-ZENER-500MW-12..> 14-Dec-2012 08:39 3.2K
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DIODE-ZENER-500MW-22..> 14-Dec-2012 08:39 3.1K
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DIODE-ZENER-500MW-43..> 14-Dec-2012 08:39 3.2K
DIP-SWITCH-2V-108246..> 14-Dec-2012 08:43 3.2K
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DRIVER-DE-MOSFET-3PH..> 14-Dec-2012 08:46 3.2K
DRIVER-DE-MOSFET-3PH..> 14-Dec-2012 08:46 3.2K
DRIVER-DE-MOSFET-3PH..> 14-Dec-2012 08:48 3.2K
DRIVER-DE-MOSFET-CMS..> 14-Dec-2012 08:46 3.2K
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DRIVER-DE-MOSFET-SIM..> 14-Dec-2012 08:43 3.2K
DRIVER-DE-MOSFET-SIM..> 14-Dec-2012 08:43 3.2K
DRIVER-DE-PWM-109742..> 14-Dec-2012 08:38 3.2K
DRIVER-DEMI-PONT-CMS..> 14-Dec-2012 08:50 3.2K
DRIVER-DEMI-PONT-CMS..> 14-Dec-2012 08:55 3.2K
DRIVER-DEMI-PONT-CMS..> 14-Dec-2012 08:55 3.2K
DRIVER-DEMI-PONT-CMS..> 14-Dec-2012 08:55 3.2K
DRIVER-DEMI-PONT-CMS..> 13-Dec-2012 19:02 3.2K
DRIVER-DEMI-PONT-CMS..> 14-Dec-2012 08:49 3.2K
DRIVER-DEMI-PONT-SIM..> 14-Dec-2012 08:42 3.2K
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DVI-I-R-A-RCPT-FORKL..> 14-Dec-2012 08:53 3.2K
DVI-I-R-A-RCPT-FORKL..> 13-Dec-2012 19:02 3.2K
ECHELLE-DIN72-0-1MA-..> 14-Dec-2012 08:50 3.1K
ECHELLE-DIN72-1A-101..> 14-Dec-2012 08:50 3.2K
ECHELLE-DIN72-5A-101..> 14-Dec-2012 08:45 3.2K
ECHELLE-DIN72-60MV-1..> 14-Dec-2012 08:50 3.1K
ECHELLE-DIN96-0-1MA-..> 14-Dec-2012 08:48 3.1K
ECHELLE-DIN96-4-20MA..> 14-Dec-2012 08:48 3.0K
ECHELLE-DIN96-60MV-1..> 14-Dec-2012 08:48 3.0K
ECLAIRAGE-MURAL-BLAN..> 14-Dec-2012 08:41 3.0K
ECLAIRAGE-TRIPLE-SPO..> 14-Dec-2012 08:41 3.1K
ECROU-BNC-TNC-102096..> 14-Dec-2012 08:44 2.8K
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EMBASE-1-RANGEE-8-VO..> 14-Dec-2012 08:49 3.2K
EMBASE-1-RANGEE-8-VO..> 14-Dec-2012 08:49 3.2K
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EMBASE-1-RANGEE-36-V..> 14-Dec-2012 08:46 3.2K
EMBASE-1-RANGEE-36-V..> 14-Dec-2012 08:49 3.2K
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EMBASE-2-RANGEES-3-V..> 14-Dec-2012 08:49 3.2K
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EMBASE-2-RANGEES-4-V..> 14-Dec-2012 08:47 3.2K
EMBASE-2-RANGEES-5-V..> 14-Dec-2012 08:46 3.2K
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www.latticesemi.com 1 tn1210_01.1
April 2013 Technical Note TN1210
© 20103 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
Sub-LVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. Being similar to LVDS, Lattice FPGA
devices can support the sub-LVDS signaling with other differential I/O standards already supported as part of the
standard I/O types. This technical note summarizes the main differences between sub-LVDS and LVDS, in order to
show how Lattice devices can support the sub-LVDS I/O standard. Knowing the differences, you can then refer
back to the Lattice data sheets to both confirm compatibility and choose compatible I/O types to implement subLVDS solutions with Lattice devices.
Differences Between LVDS and Sub-LVDS Signals
Devices such as the LatticeECP3™, LatticeXP2™ and MachXO2™ include the LVDS I/O types. Sub-LVDS is different from LVDS in that the differential and common mode signal levels are reduced yet still within the LVDS input
range. As such, a sub-LVDS output can directly drive an LVDS input, as shown in Figure 1.
Figure 1. Sub-LVDS Output Driving a Lattice Device Input
Table 1 shows sub-LVDS output signal voltages, and the Lattice device LVDS input specifications. When comparing
the values in the table, it is clear that the Lattice device’s LVDS inputs are compatible to receive sub-LVDS output
signals.
Table 1. Sub-LVDS Output Signal Voltages and LVDS Input Specifications
Characteristic Sub-LVDS
Output
LatticeECP3
LVDS Input
LatticeXP2
LVDS Input
MachXO2
LVDS Input
MachXO2
HSTL18D_I
Input
Units
Common Mode Voltage Min (Vcm) 0.75 0.05 0.05 0.05 0.05 V
Common Mode Voltage Max (Vcm) 1.05 2.35 2.35 2.0 1.1 V
Differential Voltage Min (Vod) 100 100 100 100 100 mV
Differential Voltage Max (Vod) 200 2400 2400 2050 1105 mV
LatticeXP2
LatticeECP3
MachXO2 PCB Traces, Connectors or Cables
+
-
Off-chip On-chip
Set I/O type to:
LVDS or HSTL18D
Sub-LVDS
Output
+
-
* The LatticeECP3 and MachXO2 can be configured to do the 100 ohm termination on-chip.
100 ohm differential
Z0 = 50
RT = 100 ohms
+/- 1%*
Z0 = 50
Sub-LVDS Signaling Using
Lattice Devices2
Sub-LVDS Signaling Using
Lattice Devices
In some instances, a sub-LVDS receiver is expected to detect signals below the sub-LVDS minimum differential
output level of 100 mV. Based on simulation and characterization tests, the LatticeXP2 and LatticeECP3 LVDS
inputs can detect differential signal levels down to 70 mV. Figure 2 shows a typical simulation waveform of a
LatticeECP3 and LatticeXP2 differential input buffer that is able to properly detect the input differential at 70 mV.
Figures 3 and 4 show a similar hardware test condition to the simulation that shows the input and output signals
associated with the differential input voltage at 70 mV.
Figure 2. LatticeECP3 and LatticeXP2 Typical Differential Input Simulation Waveform3
Sub-LVDS Signaling Using
Lattice Devices
Figure 3. Differential Input Waveform for Hardware Test
Figure 4. Typical Differential Output Waveform from Hardware Test4
Sub-LVDS Signaling Using
Lattice Devices
The LatticeECP3 and LatticeXP2 devices, when configured as an HSTL18D input, have the same input differential
and common mode performance as the LVDS input type. You can also set the Lattice design software to use the
HSTL18D input type to represent a sub-LVDS input. On the MachXO2, the HSTL18D inputs have different specification compared to the LVDS inputs. See table 1 for values.
Sub-LVDS, like LVDS, requires 100 ohm termination at the receiver but does not specify that the termination is
internal or external to the receiver. The LatticeECP3 device has built-in differential termination with selectable values of 80, 100, 120, or off. The internal differential 100 ohm terminations are only available for inputs on the left and
right sides of the device. See the LatticeECP3 Family Data Sheet for additional information about on-die termination. The MachXO2 device supports on-chip 100 ohm (nominal) input differential termination on the bottom edge of
MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices. The
LatticeXP2 device has no internal input termination so it does require external 100 ohm differential input terminations. When an external termination is used, the resistor should be either 0402 body size or surface mount resistor
packs and placed as close as possible to the input BGA balls on the device.
If you would like to generate sub-LVDS output signals using a LatticeECP3 and LatticeXP2 devices, it is recommended to set the I/O type to SSTL18D_II, and add the resistor network shown in Figure 5 to emulate a sub-LVDS
output type:
Figure 5. Lattice Device Generating a Sub-LVDS Signal Level - LatticeXP2 and LatticeECP3
VCCIO = +1.8V
0
LatticeXP2
LatticeECP3
+
-
Sub-LVDS Input
+
-
100 ohm differential
PCB Traces, Connectors or Cables
Rs = 267 ohms
+/- 1%
Set I/O type to:
SSTL18D_II
On-chip Off-chip
Z0 = 50
Rs = 267 ohms
+/- 1%
Rp = 121 ohms
+/- 1%
Z0 = 50
RT = 100 ohms
+/- 1%5
Sub-LVDS Signaling Using
Lattice Devices
Figure 6. Lattice Device Generating a Sub-LVDS Signal Level - MachXO2
The resistor network shown in Figure 5 and Figure 6 will produce Vod = 156 mV at the RT termination. Table 2
shows various resistor values that can be used to produce other output voltage levels smaller or larger than 156
mV, while maintaining a 100 ohm differential source termination.
Table 2. Sub-LVDS Output Voltages for Rs and Rp 1% Resistor Values
The Vcm value for the network shown in Figure 5 and Figure 6 is by default half the VCCIO voltage. The Rp and Rs
resistors should be placed as close as possible to the Lattice device output pins and should be either 0402 body
size or surface mount resistor packs with minimal stub length traces to the resistors.
If you need the lowest common mode output noise, you will get the best performance with the output resistor network shown in Figure 7 and Figure 8 where the original Rp resistor has been split into two resistors of value onehalf Rp each with their center connection to a floating, or a 0.9V VTT, plane island that is itself bypassed to the
GND plane. The GND plane should cover the entire extent of the PCB with no major line or area breaks in the
plane.
Vod (mV) Rs (Ohms) Rp (Ohms)
104 412 113
136 309 118
156 267 121
174 237 124
207 196 130
VCCIO = +1.8V
0
MachXO2
+
-
Sub-LVDS Input
+
-
100 ohm differential
PCB Traces, Connectors or Cables
Rs = 267 ohms
+/- 1%
Set I/O Type to
SSTL18D_I or
HSTL18D_I
(Fast slew, 8mA drive)
On-chip Off-chip
Z0 = 50
Rs = 267 ohms
+/- 1%
Rp = 121 ohms
+/- 1%
Z0 = 50
RT = 100 ohms
+/- 1%6
Sub-LVDS Signaling Using
Lattice Devices
Figure 7. Lattice Device Generating a Low Noise Sub-LVDS Signal - LatticeXP2 and LatticeECP3
Figure 8. Lattice Device Generating a Low Noise Sub-LVDS Signal - MachXO2
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
July 2010 01.0 Initial release.
April 2013 01.1 Added sub-LVDS implementation for XO2.
VCCIO = +1.8V
0
VTT = +0.9V
VTT = +0.9V
VTT = +0.9V
LatticeXP2
LatticeECP3
+
-
Sub-LVDS Input
+
-
100 ohm differential
PCB Traces, Connectors or Cables
Set I/O type to:
SSTL18D_II
On-chip Off-chip
Rp = 60.4 ohms
+/- 1%
Z0 = 50
Rs = 267 ohms
+/- 1%
Rp = 60.4 ohms
+/- 1%
Rs = 267 ohms
+/- 1%
RT = 100 ohms
+/- 1%
C2
1n
Z0 = 50
VCCIO = +1.8V
0
VTT = +0.9V
VTT = +0.9V
VTT = +0.9V
MachXO2
+
-
Sub-LVDS Input
+
-
100 ohm differential
PCB Traces, Connectors or Cables
Set I/O Type to
SSTL18D_I or
HSTL18D_I
(Fast slew, 8mA drive)
On-chip Off-chip
Rp = 60.4 ohms
+/- 1%
Z0 = 50
Rs = 267 ohms
+/- 1%
Rp = 60.4 ohms
+/- 1%
Rs = 267 ohms
+/- 1%
RT = 100 ohms
+/- 1%
C2
1n
Z0 = 50
www.latticesemi.com 1 tn1112_01.1
September 2006 Technical Note TN1112
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
In order to optimize speed in Lattice devices such as the ispMACH™ 4000 and MachXO™, device inputs are con-
figurable with internal pull-up, pull-down, bus-hold latch or no bus maintenance. Typically, inputs can tolerate rise
and fall times in the 50ns to 100ns range. When interfacing to slow input signals with input rise and fall time in hundreds of nanoseconds, external board design techniques are necessary to make the slow input signals immune to
input noise that may be injected. This technical note suggests a few such techniques.
Input Circuit Techniques
Simple external circuitry along with the internal bus maintenance circuit can significantly improve slow rising and
falling input noise immunity. Three common methods are described below.
Figure 1. Method 1: Input Series Resistor
Figure 2. Method 2: Input and Feedback Resistor
Figure 3. Method 3: Input Resistor and Feedback Capacitor
The following experimental data was collected to demonstrate the improvement that can be achieved with the different methods as compared to inputs without any external circuitry. The tables below highlight the maximum input
rise (tRISE) and fall (tFALL) time of the results.
Test Device: MachXO
I/O Standard: LVCMOS 3.3V with input bus-hold latch turned on
Temperature: Room temperature
External Input Circuit Input Series Resistor tRISE t
FALL
None — <54ns <56ns
Method 1
100Ω 65ns 63ns
470Ω 500ns 470ns
680Ω >15ms >15ms
Cin 20 59 Cout
Cin 20
HCout 21
59 Cout
Cin 20
HCout 21
59 Cout
Input Hysteresis in Lattice CPLD and
FPGA Devices2
Input Hysteresis in
Lattice Semiconductor Lattice CPLD and FPGA Devices
Test Device: ispMACH 4128V
I/O Standard: LVCMOS 3.3V with input bus-hold latch turned on
Temperature: Room temperature
The plots below are measured with MachXO. A 680Ω resistor is used in Method 1. The I/Os are configured as “bushold”.
Figure 4. Test Setup
In the following figures, top trace represents outputs and bottom trace represents inputs. Persistence was set to 5
seconds for all waveforms.
External Input
Circuit
Input Series
Resistor
Feedback Resistor or
Capacitor tRISE t
FALL
None — — <100ns <100ns
Method 1
100Ω — 220ns 155ns
1KΩ — 2µs 1.5µs
4.7KΩ — 6µs 7µs
Method 2
100Ω
1KΩ 800ns 300ns
560Ω 700ns 350ns
1KΩ 10KΩ 5µs 1.9µs
Method 3
100Ω
33pF 700ns 350ns
100pF 2µs 600ns
1KΩ 33pF 5µs 1.5µs
MachXO
with Bus-Hold Input
In Out
680
A B3
Input Hysteresis in
Lattice Semiconductor Lattice CPLD and FPGA Devices
Figure 5. Input Measured at Point A
Figure 6. Zoomed View of Rising Edge of Figure 54
Input Hysteresis in
Lattice Semiconductor Lattice CPLD and FPGA Devices
Input Hysteresis
Figure 7 demonstrates the input signal with slow ramp rate virtually follow the ramp rate of MachXO output.
Figure 7. Input measured at Point B
Note “jump” at transition point.
Figure 8. Zoomed View of Rising Edge of Figure 7
Most digital circuitry is effectively linear in nature. The output normally swings from one extreme (VOL) to the other
(VOH). At threshold level a smallest amount of noise will cause the output to swing widely from one extreme to the
other. 5
Input Hysteresis in
Lattice Semiconductor Lattice CPLD and FPGA Devices
With a fast slew rate input, the signal will stay around the threshold region for a short time. With a slower signal,
which stays in the threshold region for a long time, the noise will have more time to reverse the signal direction.
Hysteresis is one common solution to this problem. Hysteresis means that the state of the output is not only dependent on the state of the input but, also, on the immediate past history of the input. A Schmitt trigger adds hysteresis
to the input by creating different trip points for low-to-high and high-to-low transition. For the CPLDs and FPGAs
that do not have the Schmitt trigger input, the bus-hold latch with an external resistor works in a similar manner.
The bus-hold input circuitry works by sinking a small amount of current when it's below the threshold and sourcing
when it's above the threshold. This means that the input voltage tends to stay low when it's low and high when it's
high. If all of the I/Os on a bus go high impedance, the bus will tend to stay in the same state until an output turns
on.
If a resistor is inserted in series with the input, the change in current will result in change in the voltage seen at the
pin. This is what causes that jump. The optimum resistor value will cause enough ΔV to put the input well past the
threshold region so that noise will not be able to cause unwanted switching, but will not be so large as to exacerbate the noise or slow the signal.
Refer to Figure 9 for discussion of the 'jump'.
The voltage jump is 128mV at the output (Ch3) transition point.
When the input is below the threshold, the voltage across the resistor is 96mV and -32mV after the transition. In
other words, the input signal source must source 144µA (96mV/680Ω). When input A passes the threshold, the signal source sinks 47µA (-32mV/680Ω). At this point, any noise spike is unlikely to go back beyond the threshold.
Figure 9. Input Series Resistor and Hysteresis
Summary
As the data indicate, even with the very simple input series resistor used in Method 1 and the CPLD internal input
bus-hold latch, maximum input rise and fall times will extend to hundreds of nanoseconds to microseconds. 6
Input Hysteresis in
Lattice Semiconductor Lattice CPLD and FPGA Devices
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
April 2006 01.0 Initial release.
September 2006 01.1 Waveforms updated. Detailed explanation added.
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LatticeMico8 Open, Free 8-bit Soft Microcontroller
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The LatticeMico8 is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 32 General Purpose registers, the LatticeMico8 is a flexible reference design written in Verilog and VHDL suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.
The LatticeMico8 is licensed under a new open intellectual property (IP) core license, the first such license offered by any FPGA supplier. The main benefits of using open source IP are greater flexibility, improved portability, and no cost. This new agreement provides all the benefits of standard open source and allows users to mix proprietary designs with the open source core. Additionally, it allows for the distribution of designs in bitstream or FPGA format without accompanying it with a copy of the license.
Contribute to the LatticeMico8! Do you have designs you would like to share with us? Have you come across a bug? Is there a new feature you would like to see? Let us know! Send an email to Technical Support at techsupport@latticesemi.com.
Features
8-bit Data Path
18-bit Wide Instructions
Configurable 16 or 32 General Purpose Registers
Input/Output is Performed Using "Ports" (256 Ports/page, up to 65536 pages)
Optional upto 4 giga bytes of External Scratch Pad RAM
Two Cycles Per Instruction
Three cycles per Input/Output cycle (extendable using READY strobe)
UART, SPI, I2C and many other peripherals available as free Lattice Reference Designs
Evaluation Configurations
The following table shows a few of the many possible configurations. The v3.0 or higher of the LatticeMico8 core can be targeted to any Lattice FPGA.
Config. Number Description* Device LUTs Registers SLICEs f MAX (MHz)
1
16 - Regs, 32 byte Ext SP, 512 PROM, 8-bit Ext Address
LCMXO2-1200HC-5 259 62 131 53.4 (LCMXO2-1200HC-5)
LFXP3C-4,
LFEC3E-4 250 61 144 65.7 (LFXP3C-4)
78.8 (LFEC3E-4)
LFXP2-6 281 61 168 87.3 (LFXP2-6)
LCMX01200C-4 239 61 120 74.0 (LCMXO1200C-4)
LFE2-50E-5 265 61 155 103.5 (LFE2-50E-5)
2
32 - Regs, 32 byte Ext SP, 512 PROM, 8-bit Ext Address
LCMXO2-1200HC-5 305 62 154 50.8 (LCMXO2-1200HC-5)
LFXP3C-4,
LFEC3E-4 299 61 169 63.9 (LFXP3C-4)
71.7 (LFEC3E-4)
LFXP2-6 326 61 186 88.3 (LFXP2-6)
LCMXO1200C-4 290 61 145 77.0 (LCMXO1200C-4)
LFE2-50E-5 308 61 177 98.8 (LFE2-50E-5)
3
16 - Regs, 32 byte Ext SP,
512 PROM, 16-bit Ext Address LCMXO2-1200HC-5 262 70 132 52.3 (LCMXO2-1200HC-5)
LFXP3C-4,
LFEC3E-4 255 69 145 66.7 (LFXP3C-4)
76.8 (LFEC3E-4)
LFXP2-6 283 61 168 93.6 (LFXP2-6)
LCMXO1200C-4 242 69 121 81.3 (LCMXO1200C-4)
LFE2-50E-5 274 70 157 102.6 (LFE2-50E-5)
4
32 - Regs, 32 byte Ext SP, 512 PROM, 16-bit Ext Address
LCMXO2-1200HC-5 313 70 158 51.7 (LCMXO2-1200HC-5)
LFXP3C-4,
LFEC3E-4 303 69 168 62.2 (LFXP3C-4)
66.5 (LFEC3E-4)
LFXP2-6 322 61 185 88.6 (LFXP2-6)
LCMXO1200C-4 296 69 148 72.5 (LCMXO1200C-4)
LFE2-50E-5 323 69 181 99.2 (LFE2-50E-5)
* SP = Scratch Pad
LatticeMico8 Documentation
LatticeMico8 User Guide
Core Code
Version 3.15 of the LatticeMico8 increases addressable code space, has configurable address range and improved stack operations for support of high-level compilers, while keeping a very small footprint. The code will run on ispLever 5.1 and later. The predefined ispLever project (i.e. .syn) files are valid for 8.0 and later.
LatticeMico8 Core Source Code Revision 3.15 Verilog Only- NEW
Development Kit Demonstrations
Mini System-on-Chip Demo for MachXO Mini Development Kit, EB41 MachXO Mini Development Kit User's Guide
Control System-on-Chip Demo for MachXO Control Development Kit, EB46 MachXO Control Development Kit User's Guide
Brevia System-on-Chip Demo for LatticeXP2 Brevia Development Kit, EB53 LatticeXP2 Brevia Development Kit User's Guide
Technote 1095 - Using the LatticeMico8 Microcontroller with the LatticeXP Evaluation Board
LatticeMico8 Development Tools
The LatticeMico8 development tools consist of a LatticeMico8 port of version 4.4.3 of the GNU Compiler Collection (GCC) and version 2.18 of GNU Binary Utilities (binutils - assembler, linker and more). These tools are a collection of command line executables hosted on a Linux/Unix or Cygwin (Linux/Unix terminal emulation for Windows) environment.
The toolchain outputs an executable in the ELF format. A deployment tool converts the ELF format executable into a memory output file (.MEM file) which can be used for simulation or as input into Lattice Diamond or ispLever development tools.
LatticeMico8 Development Tools Documentation
LatticeMico8 Development Tools Usage Guide
Writing Efficient C Code for the LatticeMico8 Microcontroller
Tool Code
NEW - LatticeMico8 Development Tools Installer for Windows - LatticeMico8 Core Revision 3.15
NEW - LatticeMico8 Development Tools Installer for Linux - LatticeMico8 Core Revision 3.15
NEW - LatticeMico8 Development Tools Source Code - LatticeMico8 Core Revision 3.15
Demo
LatticeMico8 Demo
Useful External Links
AS Assembler maintained by Alfred Arnold
Another assembler that supports the LatticeMico8
Archived Code
LatticeMico8 Core Source Code Revision 3.1 Verilog
The above source code is the Verilog source code for ispLEVER version 8.0 and above
LatticeMico8 Core Source Code Revision 3.1 VHDL - NEW
The above source code is the VHDL source code for ispLEVER version 8.0 and above
LatticeMico8 Core Source Code Revision 3.0 Verilog
The above source code is the Verilog source code for ispLEVER version 7.0 and above.
LatticeMico8 Core Source Code Revision 3.0 VHDL
The above source code is the VHDL source code for ispLEVER version 7.0 and above.
LatticeMico8 Core Source Code Revision 2.4 Verilog
The above source code is the Verilog source code for ispLEVER version 6.0 and above.
LatticeMico8 Core Source Code Revision 2.4 VHDL
The above source code is the VHDL source code for ispLEVER version 6.0 and above.
LatticeMico8 Core Source Code Revision 2.3 Verilog
The above Verilog source code supports the LatticeECP2, the LatticeECP/EC, LatticeXP, and MachXO devices. Additionally, this version handles a larger number of instructions (1024 for LatticeECP2) and supports a bigger jump/branch (2048). For new designs, it is recommended to use Revision 2.4.
LatticeMico8 Core Source Code Revision 2.3 VHDL
The above VHDL source code supports the LatticeECP2, the LatticeECP/EC, LatticeXP, and MachXO devices. Additionally, this version handles a larger number of instructions (1024 for LatticeECP2) and supports a bigger jump/branch (2048). For new designs, it is recommended to use Revision 2.4.
LatticeMico8 Core Source Code Revision 2.2 Verilog Only
The above source code has a couple of bug fixes and has been fully tested for the MachXO family of Crossover Programmable Logic devices.
LatticeMico8 Core Source Code Revision 1.0 Verilog Only
LatticeMico8 Tools Code for Core Revision 3.1 and above
The above tools package contains both the source code and the executable files for the LatticeMico8
LatticeMico8 Tools Code for Core Revision 3.0
The above tools package contains both the source code and the executable files for the LatticeMico8
LatticeMico8 Tools Code for Core Revision 2.3
LatticeMico8 Tools Code Revision 1.0
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www.latticesemi.com 12-1 tn1180_02.3
April 2013 Technical Note TN1180
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
LatticeECP3™ devices support high-speed I/O interfaces, including Double Data Rate (DDR) and Single Data
Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one
edge of a clock while DDR interfaces capture data on both the rising and falling edges of the clock, thus doubling
the performance. LatticeECP3 I/Os also have dedicated circuitry that is used along with the DDR I/O to support
DDR, DDR2 and DDR3 SDRAM memory interfaces. Refer to the LatticeECP3 Family Data Sheet for a detailed
description of the I/O logic architecture.
This document discusses how to utilize the capabilities of the LatticeECP3 “E” and “EA” devices to implement both
the high-speed generic DDR interface and the DDR and DDR2 memory interfaces. Refer to the Implementing
DDR/DDR2/DDR3 Memory Interfaces section of this document for more information.
There are some differences in high-speed interface architecture between the LatticeECP3 “EA” and “E” devices.
The implementation differences between the two devices are indicated in the appropriate sections of this document.
This document assumes that version 8.0 of the ispLEVER®
software is used for all interfaces. Please see exceptions under each section if you are using the ispLEVER 7.2 SP2.
Steps to Design a High-Speed DDR Interface:
The following steps must be followed to successfully design a high-speed DDR interface using this document.
• Step 1: Determine the type of interface to implement.
Based on the external interface determine the type of high-speed interface to be built. See the Types of HighSpeed DDR Interfaces section for details.
• Step 2: Use the ispLEVER IPexpress™ tool to build the interface.
Once you have determined the type of interface to be built, use IPexpress to build the interface. See the section
Using IPexpress to Build High-Speed DDR Interfaces.
• Step 3: Understand design rules, clocking requirements for each interface.
Understand the architecture, interface rules and clocking requirements for each of the interfaces. See the HighSpeed DDR Interface Details section for a detailed description of each interface. If multiple interfaces are used in
one device, it is critical to follow these design rules to avoid resource conflicts between interfaces.
• Step 4: Review pinout requirements for clock and data pins for each interface before making pin assignments. It is critical that the interface clock and data pins follow the placement recommendations listed in the section Placement Guidelines for High-Speed DDR Interfaces. If using interfaces requiring DQ-DQS grouping, follow
the rules described in the section DQ-DQS Grouping Rules.
• Step 5: Assign timing preferences and clock preferences.
Follow the guidelines in the section Timing Analysis for High-Speed DDR Interfaces to assign timing preferences
for the interfaces.
• Step 6: Run software Place and Route without DRC and Trace.
It is important that the software Place and Route tool pass without any DRC errors. If it runs into DRC errors
review the sections described above to make sure you are not violating any of the design/pinout rules for the
interface. Run Trace to look at the static timing analysis results for all the timing preferences added to the design.
Make design changes as necessary to assure that you are meeting your timing requirements.
LatticeECP3 High-Speed
I/O Interface12-2
LatticeECP3 High-Speed
I/O Interface
Steps to Generate a Valid Pinout for a High-Speed DDR Interface:
Due to the various design rules and pinout requirements for each interface, it is critical that the interfaces be created as described above and run through the software before designing the PCB. If it is necessary to determine
pinouts for a PCB design before the complete design is in place, the user must follow the steps listed below to create the pinouts.
• Step 1: Determine the type of interface to implement.
Based on the external interface, determine the type of high-speed interface to be built. See the section Types of
High-Speed DDR Interfaces for details.
• Step 2: Use the ispLEVER IPexpress Tool to build the interface.
Once you have determined the type of interface to be built, IPexpress should be used to build the interface. See
the section Using IPexpress to Build High-Speed DDR Interfaces.
• Step 3: Build the complete I/O ring and clocking structure.
Some dummy logic may be required to assure that the data out of the DDR elements are not optimized out by the
software. For example, if you are building an input and a corresponding output interface you may connect them
using dummy register between the two interfaces. If you are building receive-only interfaces, the signals out of
the receive interface will need to be used in dummy logic or assigned to outputs. Similarly, if building a transmitonly interface you must provide input signals that are used in the transmit interface.
• Step 3: Understand the design rules and clocking requirements for each interface.
Understand the architecture, interface rules and clocking requirements for each of the interfaces. See the HighSpeed DDR Interface Details section for a detailed description of each interface. If multiple interfaces are used in
one device, it is critical to follow these design rules to avoid resource conflicts between interfaces.
• Step 4: Make pin assignments for clock and data pins for each interface following the design and pinout
rules. Assign the input and output pins to specific sites, banks or DQS groups. Review the pinout requirements
for the clock and data pins for each interface before making pin assignments. It is critical that the interface clock
and data pins follow the placement recommendations listed in the section Placement Guidelines for High-Speed
DDR Interfaces. If using interfaces requiring a DQ-DQS grouping, you must follow the rules described in the section DQ-DQS Grouping Rules.
• Step 5: Run the design through ispLEVER Place and Route and pass without any DRC errors.
If you run into errors, change pin assignments as required to pass all the DRC checks. When the design passes
Place and Route, the pin assignments listed in the PAD report can be used on the board.
External Interface Description
This technical note uses two types of external interface definitions, centered and aligned. In a centered external
interface, at the device pins, the clock is centered in the data opening. In an aligned external interface, at the device
pins, the clock and data transition are aligned. This is also sometimes called “edge-on-edge”. Figure 12-1 shows
the external interface waveform for SDR and DDR.12-3
LatticeECP3 High-Speed
I/O Interface
Figure 12-1. External Interface Definition
The interfaces described are referenced as centered or aligned interfaces. An aligned interface is needed to adjust
the clock location to satisfy the capture flip-flop setup and hold times. A centered interface is needed to balance the
clock and data delay to the first flip-flop to maintain the setup and hold already provided.
High-Speed I/O Interface Building Blocks
The LatticeECP3 device contains dedicated functions for building high-speed interfaces. This section describes
when and how to use these functions. A complete description of the library elements including descriptions and
attributes is provided at the end of this document.
Figure 12-2 shows a high-level diagram of the clocking resources available in the “E” and “EA” devices for building
high-speed I/O interfaces.
DDR Aligned DDR Centered
SDR Aligned SDR Centered
Data at Pin
Clock at Pin
Clock at Pin
Data at Pin12-4
LatticeECP3 High-Speed
I/O Interface
Figure 12-2. LatticeECP3 Clocking Diagram (LatticeECP3-35 Shown)
A complete description and of the LatticeECP3 clocking resources and clocking routing restrictions is available in
TN1178, LatticeECP3 sysCLOCK™ PLL/DLL Design and Usage Guide.
Below is a brief description for each of the major elements used for building various high-speed interfaces. The
DDR Software Primitives and Attributes section describes the library elements for these components.
ECLK
Edge clocks are high-speed, low-skew I/O dedicated clocks. They are arranged in groups of two on the left, right,
and top sides of the device.
SCLK
SCLK refers to the system clock of the design. SCLK can use either primary or secondary clocks.
DQS Lane
A DQS Lane borrows its name from memory interfaces, but can be used for general-purpose high-speed interfaces. Each DQS Lane provides a clock (DQS) and up to 10 data bits on that clock. The number of DQS Lanes on
the device is different for each device size. LatticeECP3 devices support DQS signals on the top, left and right
sides of the device.
Bank 0 Bank 1
Bank 7
Bank 2
DQ Lane DQ Lane DQ Lane DQ Lane DQ Lane
DQ Lane DQ Lane DQ Lane DQ Lane
DQ Lane DQ Lane DQ Lane DQ Lane
ECLK1
ECLK1
ECLK2
DQSDLL
ECLK2
DLL
CLKDIV
DLLDEL
SERDES Quad
PLL
PLL
CLKDIV ECLK1
ECLK2
DQSDLL
DLLDEL DLL
PLL
PLL
Primary
Clocks
QUADRANT_TL QUADRANT_TR
QUADRANT_BL QUADRANT_BR
Bank 6
Bank 3
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region
Secondary
Region12-5
LatticeECP3 High-Speed
I/O Interface
PLL
The PLL provides frequency synthesis as well as static and dynamic phase adjustment. Three output ports are provided: CLKOP, CLKOS and CLKOK. CLKOK provides a dedicated divide-by-2 function for use with the I/O logic
gearing. The number of PLLs available on the device varies by device size from 2 to 10 PLLs per device.
DLL
The general-purpose DLL provides clock injection delay removal as well as 90° delay compensation when used
with the DLLDEL element. There are two DLLs, one on each side of all LatticeECP3 devices.
DQSDLL
The DQSDLL is a dedicated DLL for creating a 90° clock delay. There are two DQSDLLs provided on all
LatticeECP3 devices. There is one DQSDLL on each side of the device.
Input DDR (IDDR)
The input DDR function can be used in either x1 or x2 gearing modes. The x1 mode is supported by the IDDRXD
element. This library element inputs a single DDR data input and clock (DQS, ECLK or SCLK) and provides a 2-bit
wide data synchronized to the SCLK (system clock) to the FPGA fabric.
In the x2 mode, the IDDRX2D element is used. This element is useful for interfaces with greater than a 200MHz
clock. It supports a 4-bit wide interface to the FPGA fabric. The clock input to the IDDRX2D is the high-speed
ECLK. The SCLK clock is divided down to half of the ECLK input clock.
Output DDR (ODDR)
The output DDR function can also be supported in either x1 or x2 gearing modes. The output x1 DDR function is
supported by the ODDRXD element. This library element provides a single DDR output and clock (SCLK) and
accepts 2-bit wide data from the FPGA fabric.
The ODDR2XD element is used in the x2 mode and supports a 4-bit wide interface to the FPGA fabric. This element is useful for interfaces with greater than a 200MHz clock. The SCLK clock is divided down to half of the ECLK.
CLKDIV
The CLKDIV element is used to divide the high-speed ECLK by 2 to generate the SCLK when using x2 input or output gearing modes.
DELAY
There are three types of input data available. DELAYC provides a fixed value of delay to compensate for clock
injection delay. DELAYC is used by default when configuring the interface in the software. Software will configure
the DELAYC with delay values based on the interface used. DELAYB provides dynamic or user-defined delay.
DELAYC is also used for SDR interfaces where it provides clock injection delay.
ECLK/SCLK vs. DQS Lanes
ECLK and SCLK span the entire side of the device and is useful for creating wide input bus interfaces. The DQS
Lanes cover only 10 bits of data width and work well for narrow input bus interfaces. Each DQS Lane is serviced by
a DQSBUF to control clock access and delay. The DQS Lane is supported by the DQSDLL for 90° clock delay.
There is only one DQSDLL per side of the device, but this DQSDLL can be used for all of the DQS Lanes on the
side. If several narrow input bus interfaces are required it is best to use the DQS Lanes instead of the ECLK or
SCLK.
Due to architectural difference between “E” and “EA” devices, wider buses are supported using ECLK in “E”
devices and SCLK in “EA” devices in x1 mode.12-6
LatticeECP3 High-Speed
I/O Interface
Building Generic High-Speed Interfaces
This section explains in detail how to build high-speed interfaces using the building blocks described above. The
ispLEVER IPexpress tool builds these interfaces based on external interface requirements.
Types of High-Speed DDR Interfaces
This section describes the different types of high-speed DDR interfaces available in the LatticeECP3 device.
Table 12-1 lists these interfaces. A description of each interface in the table is provided below the table.
Table 12-1. Generic High-Speed I/O DDR Interfaces
Mode Interface Name Description
LatticeECP3
Device Support
RX SDR GIREG_RX.SCLK SDR Input register using SCLK E, EA
RX DDRX1 Aligned GDDRX1_RX.SCLK.Aligned/
GDDRX1_RX.SCLK.PLL.Aligned
DDR x1 Input using SCLK. Data is edge-to-edge
with incoming clock.
EA
RX DDRX1 Aligned GDDRX1_RX.DQS.Aligned DDR x1 Input using DQS. Data is edge-to-edge
with incoming clock.
E, EA
RX DDRX1 Aligned GDDRX1_RX.ECLK.Aligned DDR x1 Input using ECLK. Data is edge-to-edge
with incoming clock.
E
RX DDRX2 Aligned GDDRX2_RX.ECLK.Aligned/
GDDRX2_RX.ECLK.Aligned
(no CLKDIV)
DDR x2 Input using ECLK. Data is edge-to-edge
with incoming clock.
E, EA
RX DDRX2 Aligned GDDRX2_RX.DQS.Aligned DDR x2 Input using DQS. Data is edge-to-edge
with incoming clock.
E, EA
RX DDRX1 Centered GDDRX1_RX.DQS.Centered DDR x1 Input using DQS. Clock is already
centered in data window.
E, EA
RX DDRX1 Centered GDDRX1_RX.ECLK.Centered DDR x1 Input using ECLK. Clock is already
centered in data window.
E
RX DDRX2 Centered GDDRX2_RX.ECLK.Centered DDR x2 Input using ECLK. Clock is already
centered in data window.
E, EA
RX DDRX2 Centered GDDRX2_RX.DQS.Centered DDR x2 Input using DQS. Clock is already
centered in data window.
E, EA
RX DDRX2 Dynamic GDDRX2_RX.ECLK.Dynamic DDR x2 Input with Dynamic Alignment using
ECLK.
EA
RX DDRX2 Dynamic GDDRX2_RX.DQS.Dynamic DDR x2 Input with Dynamic Alignment using
DQS.
EA
RX DDRX2 Dynamic GDDRX2_RX.PLL.Dynamic DDR x2 Input with Dynamic Alignment using
ECLK.
EA
TX SDR GOREG_TX.SCLK SDR Output using SCLK. Clock is forwarded
through ODDR.
E, EA
TX DDRX1 Centered GDDRX1_TX.SCLK.Centered DDR x1 Output using SCLK. Clock is centered
using PLL with different SCLK.
E, EA
TX DDRX1 Centered GDDRX1_TX.DQS.Centered DDR x1 Output using DQS. Clock is centered
using DQSDLL and ODDRDQS.
E, EA
TX DDRX1 Aligned GDDRX1_TX.SCLK.Aligned DDR x1 Output using SCLK. Data is edge-onedge using same clock through ODDR.
E, EA
TX DDRX2 Aligned GDDRX2_TX.Aligned DDR x2 Output that is edge-on-edge. EA
TX DDRX2 Centered GDDRX2_TX.DQSDLL.Centered DDR x2 Output that is pre-centered using DQSDLL
EA
TX DDRX2 Centered GDDRX2_TX.PLL.Centered DDR x2 Output that is pre-centered using PLL EA12-7
LatticeECP3 High-Speed
I/O Interface
The following describes the naming conventions used for each of the interfaces listed in Table 12-1.
• G – Generic
• IREG – SDR input I/O register
• OREG – SDR output I/O register
• DDRX1 – DDR x1 I/O register
• DDRX2 – DDR x2 I/O register
• _RX – Receive interface
• _TX – Transmit interface
• .ECLK – Uses ECLK (edge clock) clocking resource
• .SCLK – Uses SCLK (primary clock) clocking resource
• .DQS – Uses DQS clocking resource
• .Centered – Clock is centered to the data when coming into the device
• .Aligned– Clock is aligned edge-on-edge to the data when coming into the device
Receive Interfaces
This section lists the receive interfaces can be implemented.
1. Single Date Rate Interface (GIREG_RX.SCLK)
This interface is used when a simple input register is required for the design. The clock input to the input
register can be optionally inverted if required. These interfaces always use SCLK.
2. Input DDR 1x Interfaces
Input DDR 1x interfaces are used for DDR interfaces running at or below 200MHz. The 1x interfaces can
be further split into aligned and centered interfaces depending on the incoming clock-to-data relationship.
In addition, for each of these interfaces the incoming data is delayed using the DELAYC element to compensate for the clock injection time.
a. Aligned Interfaces
These interfaces are used when the data and clock are aligned edge-on-edge when input to the
device. The clock on the aligned interfaces is phase-shifted 90° using the on-chip DLL or DQSLL on
each side of the device. These interfaces are further split into the following interfaces.
i. Input DDR 1x Aligned Interface using SCLK (GDDRX1_RX.SCLK.Aligned/
GDDRX1_RX.SCLK.PLL.Aligned)
This interface is used on “EA” devices when the clock and data are aligned edge-on-edge.
The clock is shifted 90° using a DLL or PLL before it is used in the IDDRX1 element. The
SCLK is used in this case to clock the IDDRX1 element on the “EA” device.
ii. Input DDR 1x Aligned Interface using ECLK (GDDRX1_RX.ECLK.Aligned)
This interface is used on “E” devices when the clock and data are aligned edge-on-edge
when coming into the device. ECLK is used to clock the IDDRX1 element on the “E” device.
This clock is shifted 90° using DLL before it is routed to the ECLK.
iii. Input DDR 1x Aligned Interface using DQS (GDDRX1_RX.DQS.Aligned)
This interface is used when the interface bus is narrow (<10 bits) and the clock and data
are aligned edge-on-edge. In this case, the DQS Lanes are used for each interface and the
DQS pin is used for the clock input. The 90° shift for the clock is generated using the DQSDLL and the clock is delayed in the DQSBUF element. This delayed clock is used to clock
the IDDRX1 element. This interface then uses SCLK to clock the data from the interface to
the FPGA logic.12-8
LatticeECP3 High-Speed
I/O Interface
b. Centered Interfaces
These interfaces are used when the data and clock are centered when input to the device. Since
the clock is centered to the data, it is not required to be phase-shifted for these interfaces. These
interfaces are further split into the following interfaces.
i. Input DDR 1x Centered Interface Using ECLK (GDDRX1_RX.ECLK.Centered)
This interface is used on “E” devices when the clock and data are centered coming into the
device. The ECLK is used to clock the input DDR element on the “E” device.
ii. Input DDR 1x Centered Interface Using SCLK (GDDRX1_RX.SCLK.Centered)
This interface is used on “EA” devices when the clock and data are centered coming into
the device. The SCLK is used to clock the input DDR element on the “EA” device.
iii. Input DDR 1x Centered Interface using DQS (GDDRX1_RX.DQS.Centered)
This interface is used when the interface bus is narrow (<10 bits) and the clock and data
are centered. In this case, the DQS Lanes are used for each interface and the DQS pin is
used for the clock input. DQSDLL is held in reset for this case as no clock shift is required.
This interface then uses SCLK to clock the data from the interface to the FPGA logic.
3. Input DDR 2x Interfaces
Input DDR 2x interfaces are used for DDR interfaces running higher than 200MHz. The 2x interfaces can
be further split into aligned and centered interfaces depending on the incoming clock-to-data relationship.
In addition, for each of these interfaces the incoming data is delayed using DELAYC element to compensate for the clock injection time.
a. Aligned Interfaces
These interfaces are used when the data and clock are aligned edge-on-edge when input to the
device. The clock on the aligned interfaces is phase shifted 90° using the on-chip DLL or DQSLL on
each side of the device. These interfaces are further split into the following interfaces.
i. Input DDR 2x Aligned Interface using ECLK (GDDRX2_RX.ECLK.Aligned/
GDDRX2_RX.ECLK.Aligned (No CLKDIV))
This interface is used when the clock and data are aligned edge-on-edge. The incoming
clock is shifted 90° using the DLL. The output of the DLL is routed to the ECLK which is
used to clock the IDDRX2 element.The SCLK required for this interface is generated by
dividing the ECLK by two in the CLKDIV module or in the DLL module.
ii. Input DDR 2x Aligned Interface using DQS (GDDRX2_RX.DQS.Aligned)
This interface is used when the interface bus is narrow (<10 bits) and the clock and data
are aligned edge-on-edge. In this case, the DQS Lanes are used for each interface and
DQS pin is used for the clock input. The 90° shift for clock is generated using the DQSDLL
and the clock is delayed in the DQSBUF element. This delayed clock is used to clock the
IDDRX2 element. The SCLK required for this interface is generated by dividing the ECLK
by two in the CLKDIV module.
b. Centered Interfaces
These interfaces are used when the data and clock are centered when input to the device. Since
the clock is centered to the data, it does not required to be phase-shifted for these interfaces. These
interfaces are further split into the following interfaces.
i. Input DDR 2x Centered Interface using ECLK (GDDRX2_RX.ECLK.Centered)
This interface is used when clock and data are centered coming into the device. The clock
is connected directly to the ECLK which is used to clock the IDDRX2 element. The SCLK
required for this interface is generated by dividing the ECLK by two in the CLKDIV module.12-9
LatticeECP3 High-Speed
I/O Interface
ii. Input DDR 1x Centered Interface using DQS (GDDRX2_RX.DQS.Centered)
This interface is used when the interface bus is narrow (<10 bits) and the clock and data
are centered. In this case, the DQS Lanes are used for each interface and the DQS pin is
used for the clock input going to the DQSBUF module. DQSDLL is held in reset for this
case as no clock shift is required. The clock output of the DQSBUF is used to clock the
IDDRX2 element. A PLL is used to generate the SCLK for this interface.
c. Dynamic Interfaces (“EA” Devices Only)
The data delay input on the data input of the input DDR 2x centered interfaces can optionally be
controlled dynamically by the user logic using the DELAYB element. For dynamic control of the
clock or data delay, one of following dynamic interfaces can be used. The dynamic interfaces are
only available on “EA” devices.
i. Input DDR 2x Centered Interface Using ECLK and Dynamic Delay
(GDDRX2_RX.ECLK.Dynamic)
This interface is similar to the GDDRX2_RX.ECLK.Centered interface described above but
the input data delay is controlled by the user with the DELAYB element.
ii. Input DDR 2x Centered Interface Using DQS and Dynamic Delay
(GDDRX2_RX.DQS.Dynamic)
This interface is similar to the GDDRX2_RX.DQS.Centered interface described above but
the input data delay is controlled by the user with the DELAYB element.
iii. Input DDR 2x Centered Interface Using PLL and Dynamic Delay
(GDDRX2_RX.PLL.Dynamic)
In this interface the PLL is used to dynamically shift the clock to adjust to the correct position to the data. This interface will generate a bus-based delay for the interface.
d. 7:1 LVDS Interface
This interface should be used when implementing a 7:1 LVDS interface. The 7:1 LVDS interface
requires that the input clock is multiplied 3.5x before input to the IDDRX2 element to demux the
data. Refer to RD1030, 7:1 LVDS Video Interface Reference Design for further information.
Transmit Interfaces
This section lists the transmit interfaces can be implemented.
1. Single Date Rate Interface (GOREG_TX.SCLK)
This interface is used for a SDR data output implementation with tight specifications on clock out to data
out skew. This interface uses a simple output flip-flop for the data but forwards the clock using an ODDRX
register. The same clock is used for both data and clock generation.
2. Output DDR 1x Interfaces
Output DDR 1x interfaces are used for DDR interfaces running at or below 200MHz. The 1x interfaces can
further be spilt into aligned and centered interfaces depending on the relationship between the forwarded
clock and data. The following are the different 1x interfaces.
a. Aligned Interfaces
These interfaces are used to provide data and clocks that are aligned edge-on-edge when leaving
the device. These interfaces are further split into the following.
i. Output DDR 1x Aligned Interface Using SCLK (GDDRX1_TX.SCLK.Aligned)
This interface uses SCLK to generate clock and data that are aligned edge on edge
b. Centered Interfaces
These interfaces are used to provide data and clocks that are centered when leaving the device.
The clock output is phase-shifted 90° using the on-chip PLL so that it can be centered to the data.
These interfaces are further split as follows.12-10
LatticeECP3 High-Speed
I/O Interface
i. Output DDR 1x Centered Interface Using SCLK (GDDRX1_TX.SCLK.Centered)
In this case, the SCLK is used to generate the data and clock output. SCLK used to generate the clock is shifted 90° using a PLL so that it can be pre-centered to the data output.
ii. Output DDR 1x Centered Interface Using DQS (GDDRX1_TX.DQS.Centered)
This interface is used when implementing interfaces that are <10 bits wide. The DQS
Lanes are for data and clock assignments. The clock is pre-centered to the data using the
DQSLL and the ODDRDQSA blocks.
3. Output DDR 2x Interfaces
Output DDR 2x interfaces are used for DDR interfaces running higher than 200MHz. The 2x interfaces can
further be spilt into aligned and centered interfaces depending on the relationship between the forwarded
clock and data. Output DDR 2x interfaces are supported only on “EA” devices. The following are the different 2x interfaces.
a. Aligned Interfaces
These interfaces are used to provide data and clocks that are aligned edge-on-edge when leaving
the device. These interfaces are further split into the following.
i. Output DDR 2x Aligned Interface (GDDRX2_TX.Aligned)
ODDRX2 is used generate the clock and data that are aligned in phase.
b. Centered Interfaces
These interfaces are used to provide data and clocks that are centered when leaving the device.
The clock output is phase shifted 90° so that it can be centered to the data. These interfaces are
further split into the following.
i. Output DDR 2x Centered Interface using DQSDLL (GDDRX2_TX.DQSDLL.Centered)
This interface is primarily used for interfaces that are <10 bits wide. In this case, a DQSDLL
is used to generate the 90° shift required to pre-center the clock to the data output.
ii Output DDR 2x Centered Interface using PLL (GDDRX2_TX.PLL.Centered)
This interface is primarily used for wider interfaces. Here, a PLL is used to generate the 90°
shift required to pre-center the clock to the data output.
c. 7:1 LVDS Interface
This interface is used when implementing a 7:1 LVDS interface. The 7:1 LVDS interface requires
that the clock output be multiplied 3.5x before going to the ODDRX2 module. Refer to RD1030, 7:1
LVDS Video Interface Reference Design for further information.
Using IPexpress to Build High-Speed DDR Interfaces
The IPexpress tool is used to configure and generate all the high-speed interfaces described above. IPexpress
generates a complete HDL module including clocking requirements for each of the interfaces.
This section assumes that ispLEVER 8.0 is used for generation of the interfaces. If you are using ispLEVER 7.2
SP2, see Appendix A. Building DDR Interfaces Using IPexpress in ispLEVER 7.2 SP2. If you are using Lattice Diamond®
design software, see Appendix B. Building SDR/DDR Interfaces Using IPexpress in Diamond.
For a detailed block diagram of each interface generated by IPexpress, see the High-Speed DDR Interface Details
section.
IPexpress can be opened from the Tools menu in Project Navigator. All DDR modules are located under Architecture Modules -> IO. This section will cover SDR and DDR_GENERIC. DDR_MEM is discussed in the Implementing DDR/DDR2/DDR3 Memory Interfaces section.12-11
LatticeECP3 High-Speed
I/O Interface
Figure 12-3. IPexpress Main Window
Select the type of interface you would like to build and enter the name of the module. Figure 12-3 shows the type of
interface selected as “SDR” and module name entered. Each module can then be configured by clicking the Customize button.
Building SDR Modules
Choose interface type SDR, enter module name and click Customize to open the configuration tab.
Figure 12-4 shows the Configuration Tab for the SDR module in IPexpress. Table 12-2 lists the various configurations options available for SDR modules.12-12
LatticeECP3 High-Speed
I/O Interface
Figure 12-4. SDR Configuration Tab
Table 12-2. SDR Configuration Parameters
GUI Option Description Values Default
Interface Type Type of interface (transmit or receive) Transmit, Receive Receive
I/O Standard for this Interface I/O standard to be used for the interface.
Transmit and Receive:
LVCMOS25, LVCMOS18, LVCMOS15,
LVCMOS12, LVCMOS33,
LVCMOS33D,
LVDS25, BLVDS25, MLVDS,
LVPECL33,
HSTL18_I, HSTL18_II, HSTL18D_I,
HSTL18D_II, HSTL15_I, HSTL15D_I,
SSTL33_I, SSTL33_II, SSTL33D_I,
SSTL33D_II, SSTL25_I, SSTL25_II,
SSTL25D_I, SSTL25D_II, SSTL18_I,
SSTL18_II, SSTL18D_I, SSTL18D_II,
SSTL15, SSTL15D, PCI33, LVTTL33
Transmit only:
RSDS, MINILVDS, PPLVDS,
LVDS25E, RSDSE
LVCMOS25
Bus Width for this Interface Bus size for the interface. 1 - 256 16
Clock Frequency for this Interface
Speed at which the interface will run. 1 - 200 200
Bandwidth (Calculated) Calculated from the clock frequency
entered.
(Calculated) (Calculated)
Interface Interface selected based on previous
entries.
Transmit: GOREG_TX.SCLK
Receive: GIREG_RX.SCLK (default)
GIREG_RX.S
CLK
Clock Inversion Option to invert the clock input to the
I/O register.
DISABLED, ENABLED DISABLED
Data Path Delay Data input can be optionally delayed
using the DELAY block.
Bypass, Dynamic1
, User Defined Bypass12-13
LatticeECP3 High-Speed
I/O Interface
Building DDR Generic Modules
Choose interface type DDR_GENERIC, enter module name and click Customize to open the configuration tab.
Figure 12-5. “DDR_Generic” Selected in Main IPexpress Window
When clicking Customize, DDR modules have a Pre-Configuration Tab and a Configuration” Tab. The Pre-Configuration Tab allows users to enter information about the type of interface to be built. Based on the entries in the Preconfiguration Tab, the Configuration Tab will be populated with the best interface selection. The user can also, if
necessary, override the selection made for the interface in the Configuration Tab and customize the interface based
on design requirements.
Figure 12-6 shows the Pre-Configuration Tab for DDR generic interfaces. Table 12-3 lists the various parameters in
the tab.
FDEL for User Defined If Delay type selected above is user
defined, delay values can be entered
with this parameter.
0 to 152
0
1. When Delay type Dynamic is selected, the 16-step delay values must be controlled from the user’s design.
2. A FDEL is a fine-delay value that is additive. The delay value for a FDEL can be found in the LatticeECP3 Family Data Sheet.
Table 12-2. SDR Configuration Parameters (Continued)
GUI Option Description Values Default12-14
LatticeECP3 High-Speed
I/O Interface
Figure 12-6. DDR Generic Pre-Configuration Tab
.
Table 12-3. Pre-Configuration Tab Settings
GUI Option Description Values
Interface Type (Transmit or Receive) Type of interface (Receive or Transmit) Transmit, Receive
I/O Standard for this Interface I/O Standard used for the interface Transmit and Receive:
LVCMOS25,LVCMOS18, LVCMOS15,
LVCMOS12, LVCMOS33, LVCMOS33D,
LVDS25, BLVDS25, MLVDS, LVPECL33,
HSTL18_I, HSTL18_II, HSTL18D_I,
HSTL18D_II, HSTL15_I, HSTL15D_I,
SSTL33_I, SSTL33_II, SSTL33D_I,
SSTL33D_II, SSTL25_I, SSTL25_II,
SSTL25D_I, SSTL25D_II, SSTL18_I,
SSTL18_II, SSTL18D_I, SSTL18D_II,
SSTL15, SSTL15D, PCI33, LVTTL33
Transmit only:
RSDS, MINILVDS, PPLVDS,
LVDS25E, RSDSE
Number of interfaces on a side of a
device
Number of interfaces to be implemented
per side. This is used primarily for narrow bus width interfaces (<10). Otherwise it is recommended to leave this at
1.
1 to 8
Bus Width for this Interface Bus width for each interface. If the number of interfaces per side is >1 then the
bus width per interface is limited to 10.
If number of interfaces per side is >1
and if using differential I/O standards
then bus width is limited to 5.
1-256
Clock Frequency for this Interface Interface speed 2 - 500 MHz12-15
LatticeECP3 High-Speed
I/O Interface
Based on the selections made in the Pre-Configuration Tab, the Configuration Tab is populated with the selections.
Figure 12-7 shows the Configuration Tab for the selections made in the Pre-Configuration Tab.
Figure 12-7. DDR Generic Configuration Tab
The checkbox at the top of this tab indicates that the interface is selected based on entries in the Pre-Configuration
Tab. The user can choose to change these values by disabling this entry. Note that IPexpress chooses the most
suitable interface based on selections made in the Pre-Configuration Tab.
Table 12-4 lists the various parameters in the Configuration Tab.
Interface Bandwidth (Calculated) Bandwidth is calculated from the clock
frequency.
Calculated
Clock to Data Relationship at the Pins Relationship between clock and data. Edge-to-Edge, Centered, Dynamic Data
Phase Alignment Required1
,Dynamic Clock
Phase Alignment Required
1. Dynamic Phase Alignment is only available for x2 interfaces (i.e, when the clock frequency is higher than 200 MHz).
Table 12-3. Pre-Configuration Tab Settings (Continued)
GUI Option Description Values12-16
LatticeECP3 High-Speed
I/O Interface
Table 12-4. Configuration Tab Settings
GUI Option Description Values Default Value
Interface Selection Based on
Pre-configuration
Indicates interface is selected based on selection made in the Pre-configuration tab. Disabling
this checkbox allows users to make changes if
needed.
ENABLED, DISABLED ENABLED
Interface Type Type of interface (receive or transmit) Transmit, Receive Receive
I/O Standard I/O standard used for the interface All the ones listed in the
Pre-configuration tab LVCMOS25
Clock Frequency Speed of the interface 2 to 500 MHz 200 MHz
Gearing Ratio DDR register gearing ratio (1x or 2x) 1x, 2x 1x
Alignment Clock to data alignment
Edge-to-Edge,
Centered,
Dynamic Data Phase
Alignment Required,
Dynamic Clock Phase
Alignment Required
Edge-to-Edge
Number of Interfaces
Number of interfaces to be implemented per
side. This is primarily used for narrow bus width
interfaces (<10), otherwise it is recommended
to leave this at 1.
1 to 8 1
Bus Width
Bus width for each interface. If the number of
interfaces per side is >1 then the bus width per
interface is limited to 10. If the number of interfaces per side is >1 and if using differential I/O
standards then the bus width is limited to 5.
1 to 256 10
Phase Adjust Module used for phase shifting input clock. TRDLLB/DLLDELB,
PLL1
TRDLLB/DLLDELB
Clock Divider Module used for generation of SCLK from
ECLK. CLKDIVB, TRDLLB2
CLKDIVB
Interface Shows list of all valid high-speed interfaces for a
given configuration.
See Table 12-5 for
interfaces available for
a given configuration.
GDDRX1_RX.SCLK.
Aligned (EA devices);
GDDRX1_RX.ECLK.
Aligned (E devices)
Data Path Delay
Data input can be optionally delayed using the
DELAY block. Value is selected based on Interface Type.
Bypass, Fixed,
Dynamic3
Fixed
Number of DQS Groups Enabled when a DQS interface is selected in
the Interface selection. 1 to 8
Number of DQ:
DQS Group1 to DQS Group8
This option can be used to change the number
of DQ assigned to each DQS lane. Each DQS
lane can support up to 10 DQ.
1 to 10
1. Only available when using GDDRX2_RX.ECLK.Aligned interface.
2. Only available when using GDDRX2_RX.SCLK Aligned interface.
3. When Dynamic Delay is selected, the 16-step delay values must be controlled from the user’s design.12-17
LatticeECP3 High-Speed
I/O Interface
Table 12-5 shows how the interfaces are selected by IPexpress based on the selections made in the Pre-Configuration Tab.
The implementation for several of the interfaces described above differs between the “E” and “EA” devices. Refer to
the High-Speed DDR Interface Details section to see implementation details for “E” and “EA” devices.
The Data Delay setting for each interface is predetermined and cannot be changed by the user. User can only control Data Delay values when using a dynamic interface.
Note: Some modules generated by IPexpress have a SCLK and ECLK output port. If present, this port must be
used to drive logic outside the interface driven by the same signal. In these modules, the input buffer for the clock is
inside the IPexpress module and therefore cannot be used to drive other logic in the top level.
High-Speed DDR Interface Details
This section describes each of the generic high-speed interfaces in detail including the clocking to be used for each
interface. For detailed information about the LatticeECP3 clocking structure, refer to TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide. The various interface rules and preferences listed under each interface
should be followed to build these interfaces successfully. Each of the interfaces for the “EA” devices has an ID label
associated with the interface. The interface ID will be set when generating the interface using IPexpress. This ID is
entered using an attribute called IDDRAPPS or ODDRAPPS. The software uses this ID to set appropriate the data
delay for the DELAYC element used in each of the interfaces. It is required that every interface on the “EA” devices
use this attribute to achieve the correct timing results in the software Trace report. Refer to the Timing Analysis for
High-Speed DDR Interfaces section for more information about the timing analysis on these interfaces. It is also
necessary to follow the interface rules and preferences listed for each of the interface descriptions below for the
interfaces to work as described.
Table 12-5. IPexpress Interface Selection
Device
Selected Interface Type
Gearing
Ratio1
Alignment
Number of
Interfaces Interface
EA Receive 1x Edge-to-Edge 1 GDDRX1_RX.SCLK.Aligned
EA Receive 1x Centered 1 GDDRX1_RX.SCLK.Centered
E Receive 1x Edge-to-Edge 1 GDDRX1_RX.ECLK.Aligned
E Receive 1x Centered 1 GDDRX1_RX.ECLK.Centered
E, EA Receive 1x Edge-to-Edge >1 GDDRX1_RX.DQS.Aligned
E, EA Receive 1x Centered >1 GDDRX1_RX.DQS.Centered
E, EA Receive 2x Edge-to-Edge 1 GDDRX2_RX.ECLK.Aligned
E, EA Receive 2x Centered 1 GDDRX2_RX.ECLK.Centered
E, EA Receive 2x Edge-to-Edge >1 GDDRX2_RX.DQS.Aligned
E, EA Receive 2x Centered >1 GDDRX2_RX.DQS.Centered
EA
Receive 2x Dynamic 1
GDDRX2_RX.ECLK.Dynamic (Default)
EA GDDRX2_RX.DQS.Dynamic2
EA GDDRX2_RX.PLL.Dynamic2
E, EA Transmit 1x Centered 1 GDDRX1_TX.SCLK.Centered
E, EA Transmit 1x Edge-to-Edge 1 GDDRX1_TX.SCLK.Aligned
E, EA Transmit 1x Centered >1 GDDRX1_TX.DQS.Centered
EA Transmit 2x Edge-to-Edge 1 GDDRX2_TX.Aligned
EA Transmit 2x Centered >1 GDDRX2_TX.DQSDLL.Centered
EA Transmit 2x Centered 1 GDDRX2_TX.PLL.Centered
1. Gearing Ratio of 1x is selected for clock frequencies less than 200MHz. Gearing ratio of 2x is selected for frequencies above 200 MHz.
2. These interfaces can only be selected in the Configuration Tab.12-18
LatticeECP3 High-Speed
I/O Interface
In order to achieve higher speeds, the guidelines described in the Placement Guidelines for High-Speed DDR
Interfaces section should be strictly followed.
All the interfaces described below are supported using ispLEVER 8.0 software. Some of these interfaces will not
work in versions of ispLEVER prior to version 8.0. Refer to the Generic DDR Design Guidelines section to see all
other design guidelines.
GIREG_RX.SCLK
Generic SDR Receive Interface using SCLK.
Device Support: “E” and “EA” devices
Description
This is a generic interface for single data rate (SDR) data. An optional inverter can be used to center the clock for
aligned inputs. A PLL or DLL can be used to remove the clock injection delay or adjust the setup and hold times.
There are a limited number of DLLs in the architecture and these should be saved for high-speed interfaces when
necessary. This interface can either be built using IPexpress or inferred during synthesis.
Figure 12-8. GIREG_RX Interface (“E” and “EA” Devices)
This interface also supports data delay on the data input. This delay value is set using a DELAYB or a DELAYC element. A DELAYC element provides a fixed delay to match the SCLK injection time.
DELAYB is used when user chooses to update the delay dynamically or use user-defined static values. Figure 12-
9 shows the DELAYB element connected to this interface.
Figure 12-9. GIREG_RX.SCLK with Delay Interface (“E” and “EA” Devices)
Interface Rules
• The input clock must use a dedicated clock (PCLK) input pin.
Clk
IREG
Sclk
Din
IREG
Sclk
Din
Clk
Clk
IREG
Sclk
Din
Clk
Din
IREG
Sclk
DELAYB DELAYB12-19
LatticeECP3 High-Speed
I/O Interface
GDDRX1_RX.ECLK.Aligned
Generic DDR Receive Interface using ECLK with Aligned External Interface
Device Support: “E” devices only
Description
This DDR interface uses the ECLK and the TRDLLB to provide a 90° clock shift to center the clock at the IDDRXD.
DLLDELB is used to delay the incoming clock by 90°. CLKDIV is used to generate a divide-by-1 clock that is connected to the SCLK. Since this interface uses the ECLK it can be extended to support large data bus sizes for the
entire side of the device.
Figure 12-10. GDDRX1_RX.ECLK.Aligned Interface (“E” Devices Only)
Interface Rules
• The input clock must use a GPLLT_IN or GDLLT_IN pin. All data for the interface must all be on the same ECLK
(same side).
• Since there is only one DLLDELB and one CLKDIVB per left and right sides of the device, users can implement
only one such interface per side, or two total on the device.
• The clock net connected to SCLK should be on a primary clock net. The user must assign the “USE PRIMARY
NET” preference to assign the SCLK clock net to a primary clock.
• The pin assignments for data and clocks will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
GDDRX1_RX.ECLK.Centered
Generic DDR Receive Interface using ECLK with Centered External Interface.
Device Support: “E” devices only
Description
This DDR interface uses the ECLK and DELAYC to match clock and data delay at the IDDRXD. Since this interface
uses the ECLK it can be extended to support large data bus sizes for the entire side of the device.
DLLDELB
ECLK
clk
TRDLLB
IDDRXD
DQSBUFG DDRCLKPOL ECLKDQSR SCLK
D
datain DELAYC
CDIV1
CLKDIVB
2
q12-20
LatticeECP3 High-Speed
I/O Interface
Figure 12-11. GDDRX1_RX.ECLK.Centered Interface (“E” Devices Only)
Interface Rules
• The input clock port must use a dedicated clock (PCLK) input pin. All data for the interface must be on the same
ECLK (same side).
• The clock net connected to SCLK must be routed on a primary clock net. It is the user’s responsibility to assign
the SCLK clock net to a primary clock tree using the “USE PRIMARY NET” preference.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
GDDRX1_RX.SCLK.Aligned
Generic DDR Receive Interface using SCLK with Aligned External Interface
Device Support: “EA” devices only
Description
This DDR interface uses the SCLK and the TRDLLB to provide a 90° clock shift to center the clock at the
IDDRXD1. This interface is useful for large data buses (>10 bits). A DELAYC is used to adjust data delay for the
SCLK clock injection time. CLKDIV in divide-by-1 setting is used to generate the SCLK.
Figure 12-12. GDDRX1_RX.SCLK.Aligned Interface (“EA” Devices Only)
ECLK
clk
IDDRXD
DQSBUFG DDRCLKPOL ECLKDQSR SCLK
D
datain
DELAYC
2
q
clk
TRDLLB
IDDRXD1
IDDRAPPS=SCLK_ALIGNED
SCLK
D
datain
DELAYC
CDIV1
CLKDIVB
DLLDELB
2
q12-21
LatticeECP3 High-Speed
I/O Interface
Interface Rules
• The clock input must use a dedicated GPLLT_IN or GDLLT_IN clock input pin (two pins per side). A dedicated
PCLK pin on the top side can connect directly to the TRDLLB as well.
• There is only one DLLDELB per side of the device (left and right sides) which limits this interface to one clock
rate per side or two per device.
• CLKDIV is required to generate SCLK.
• The clock net connected to SCLK should be on a primary clock net. The user must assign the “USE PRIMARY
NET” preference to assign the SCLK clock net to a primary clock.
GDDRX1_RX.SCLK.PLL.Aligned
Generic DDR Receive Interface using SCLK with Aligned External Interface
Device Support: “EA” devices only
Description
This DDR interface uses the SCLK and a PLL to provide a 90° clock shift to center the clock at the IDDRXD1. This
interface is useful for large data buses (>10 bits). A DELAYC is used to adjust data delay for the SCLK clock injection time. CLKDIV in divide by 1 setting is used to generate the SCLK.
Figure 12-13. GDDRX1_RX.SCLK.PLL.Aligned Interface (“EA” Devices Only)
Interface Rules
The clock input must use a dedicated GPLLT_IN clock input pin (two pins per side).
CLKDIV is required to generate SCLK.
The clock net connected to SCLK should be on a primary clock net. The user must assign the “USE PRIMARY
NET” preference to assign the SCLK clock net to a primary clock.
clk
IDDRXD1
IDDRAPPS=SCLK_PLLALIGNED
SCLK
D
datain DELAYC
PLL CLKOS
2
q12-22
LatticeECP3 High-Speed
I/O Interface
GDDRX1_RX.SCLK.Centered
Generic DDR Receive Interface using SCLK with Centered External Interface
Device Support: “EA” devices only
Description
This DDR interface uses the SCLK and DELAYC to match clock and data delay at the IDDRXD. This interface is
useful for large data buses (>10 bits).
Figure 12-14. GDDRX1_RX.SCLK.Centered Interface (“EA” Devices Only)
Interface Rules
• The clock input must use a dedicated clock (PCLK) input pin. The output of a PLL clock in bypass mode can be
connected to the SCLK as well.
• The clock connected to SCLK should be on a primary clock net. The user must assign the “USE PRIMARY
NET” preference to assign the SCLK clock net to a primary clock.
GDDRX1_RX.DQS.Aligned
Generic DDR Receive Interface using DQS Lane with Aligned External Interface
Device Support: “E” and “EA” devices
Description
This DDR interface uses the DQS and the DQSDLL to provide a 90° clock shift to center the clock at the IDDRXD.
This interface is uses a DQS lane and is useful for small data buses (< 11 bits). DQSDLL provide the 90° delay to
the DQSBUFF which is used to delay the incoming clock.
A reference clock input “dqsdll_clk” running at the same frequency as DQS clock is required to be input to the
DQSDLL to generate the delay.
clk
IDDRXD1
SCLK
D
datain DELAYC
IDDRAPPS = SCLK_CENTERED
2
q12-23
LatticeECP3 High-Speed
I/O Interface
Figure 12-15. GDDRX1_RX.DQS.Aligned Interface (“E” and “EA” Devices)
Any frequency-locked clock or the local clock from the input pin can be used for SCLK. The timing transfer between
the ECLKDQSR and SCLK is handled in the hardware through the DDRCLKPOL.
Interface Rules
• The input clock must use a DQS input pin and all data inputs must be in the same DQS lane.
• The VREF1 for the selected DQS lane must be powered on the board.
• There is only one DQSDLL per side of the device which limits sharing of this interface on a side unless all are
running at the same rate.
• The following sequence must be followed when resetting the interface:
– Assert DQSDLL_RESET to DQSDLL and RESET to the modules
– Deassert DQSDLL_RESET to DQSDLL first
– Wait for DQSDLL lock to go high
– Assert DQSDLL_UDDCNTLN input of DQSDLL for at least four SCLK cycles. See the section “DQSDLLB”
on page 89 for the detailed requirements for the DQSDLL_UDDCNTLN input of DQSDLLB
– Deassert DQSDLL_UDDCNTLN
– Wait for four SCLK cycles, then deassert RESET to the other modules
• “dqsdll_clk” and clock net connected to SCLK must use the primary clock tree. It is the user’s responsibility to
assign the “USE PRIMARY NET” preference on these nets to assign it to the primary clock.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
GDDRX1_RX.DQS.Centered
Generic DDR Receive Interface using DQS Lane with Centered External Interface
Device Support: “E” and “EA” devices
Description
This DDR interface uses the DQS and DELAYC to match clock and data delay at the IDDRXD. This interface is
useful for small data buses (<11 bits). Since a 90° shift is not required, the DQSDLL is held in reset for this interface.
DQSBUFF
ECLKDQSR
clk_0
DQSDLL
IDDRXD
IDDRAPPS=DQS_ALIGNED*
DDRCLKPOL ECLKDOSR SCLK
datain_0 D
DQSI
SCLK
RESET
READ
reset_0
dqsdll_clk
dqsdll_reset
dqsdll_uddcntln
* IDDRAPPS required for “EA” devices only.
2
q_012-24
LatticeECP3 High-Speed
I/O Interface
The user can use any frequency-locked clock for SCLK or the local clock from the input pin. The timing transfer
between the ECLKDQSR and SCLK is handled in the hardware through the DDRCLKPOL
Figure 12-16. GDDRX1_RX.DQS.Centered Interface (“E” and “EA” Devices)
Notes:
1. The DELAYC is only applicable for “EA” devices. For “E” devices, change the DELAYC to DELAYB with a delay value of 7.
2. When retargeting from “E” to “EA” devices, manually update DELYAB to DELAYC, otherwise the software will error out.
Interface Rules
• The input clock must use a DQS input pin and all data inputs must be in the same DQS lane.
• The VREF1 for the selected DQS lane must be powered on the board.
• There is only one DQSDLL per side of the device which limits sharing of this interface on a side unless all are
running at the same rate.
• The clock net connected to SCLK must use the primary clock tree. It is the user’s responsibility to assign “USE
PRIMARY NET” preference on this SCLK clock net to assign it to the primary clock.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
GDDRX2_RX.ECLK.Aligned
Generic DDR Receive Interface with x2 Gearing using ECLK with Aligned External Interface
Device Support: “E” and “EA” devices
Description
This DDR x2 interface uses the ECLK and the TRDLLB to provide a 90° clock shift to center the clock at the
IDDRX2D. DELAYC is used to delay data to match the ECLK injection delay. Since this interface uses the ECLK it
can be extended to support large data bus sizes for the entire side of the device.
This interface uses x2 gearing with the IDDRX2D element. This requires the use of a CLKDIVB to provide the
SCLK which is half the frequency of the ECLK and ECLKDQSR.
DQSBUFF
ECLKDQSR
clk_0
dqsdll_clk DQSDLL
IDDRXD
IDDRAPPS=DQS_CENTERED*
DDRCLKPOL ECLKDOSR SCLK
datain_0 D
DQSI
SCLK
reset_0 READ
RST
‘1’
DELAYC
*IDDRAPPS required for “EA” devices only.
2
q12-25
LatticeECP3 High-Speed
I/O Interface
Note the difference in interface implementation between the “E” and “EA” devices. “E” devices require the use of a
DQSBUFE which is not required on the “EA” devices.
Figure 12-17. GDDRX2_RX.ECLK.Aligned Interface (“EA” Devices)
Figure 12-18. GDDRX2_RX.ECLK.Aligned Interface (“E” Devices)
DLLDELB
ECLK
clk
TRDLLB
IDDRX2D1
ECLK SCLK
datain DELAYC D
CDIV2
CLKDIVB
IDDRAPPS = ECLK_ALIGNED
4
q
DLLDELB
ECLK
clk
TRDLLB
IDDRX2D
ECLK SCLK
datain DELAYC D
CDIV2
CLKDIVB
4
q
DQSBUFE
DDRLAT
DDRCLKPOL ECLKDQSR12-26
LatticeECP3 High-Speed
I/O Interface
Interface Rules
• It is recommended that a dedicated GDLL T_IN is used for the clock input. In “EA” devices, a GPLLT_IN or PCLK
from the top side can also be used for the clock input.
• The clock net output of the CLKDIVB module is connected to SCLK and it must be routed on a primary clock.
The “USE PRIMARY NET” preference must be used on this clock net as well.
• There is only one DLLDELB and one CLKDIV per side of the device (left and right sides) which limits this interface to one clock rate per side or two per device.
• The data/clock pin assignments for “E” devices require following the DQ-DQS group pinout guidelines. See the
Generic DDR Design Guidelines section for details. This is not required for “EA” devices.
GDDRX2_RX.ECLK.Aligned (No CLKDIV)
Generic DDR Receive Interface with x2 Gearing using ECLK with Aligned External Interface Device Support: “EA”
devices
Description
This DDR x2 interface uses the ECLK and the TRDLLB to provide a 90° clock shift to center the clock at the
IDDRX2D. DELAYC is used to delay data to match the ECLK injection delay. Since this interface uses the ECLK it
can be extended to support large data bus sizes for the entire side of the device.
This interface uses x2 gearing with the IDDRX2D element. The CLKOS output of the TRDLLB can be set up to
divide ECLK by 2 to generate the SCLK.
Figure 12-19. GDDRX2_RX.ECLK.Aligned (No CLKDIV) Interface (“EA” Devices)
Interface Rules
It is recommended that a dedicated TGDLL_IN pin be used for the clock input. In an “EA” device a GPLLT_IN or
PCLK from the top side can also be used for the clock input.
The clock CLKOS output of the TRDLLB module is connected to SCLK of IDDRX2D1 and it must be routed on a
primary clock. The “USE PRIMARY NET” preference must be used on this clock net as well.
There is only one DLLDELB per side of the device (left and right sides) which limits this interface to one clock rate
per side or two per device.
DLLDELB
ECLK
clk
IDDRX2D1
IDDRAPPS =
ECLK_ALIGNEDNOCLKDIV
ECLK SCLK
data DELAYC
TRDLLB
CLKOS
(divby2/
90deg)
4
q12-27
LatticeECP3 High-Speed
I/O Interface
GDDRX2_RX.ECLK.Centered
Generic DDR Receive Interface with x2 Gearing using ECLK with Centered External Interface
Device Support: “E” and “EA” devices
Description
This DDR x2 interface uses the ECLK and DELAYC to match clock and data delay at the IDDRX2D. Since this
interface uses the ECLK it can be extended to support large data bus sizes for the entire side of the device.
This interface uses x2 gearing with the IDDRX2D element. This requires the use of a CLKDIVB to provide the
SCLK which is half the frequency of the ECLK and ECLKDQSR.
Note the difference in interface implementation between the “E” and “EA” devices. “E” devices require the use of a
DQSBUFE which is not required on the “EA” devices.
Figure 12-20. GDDRX2_RX.ECLK.Centered Interface (“EA” Devices)
Figure 12-21. GDDRX2_RX.ECLK.Centered Interface (“E” Devices)
Interface Rules
• Input clock port must use a dedicated clock (PCLK) input pin. All the data for the interface must be on the same
ECLK tree (same side of the device). In “EA” devices, PLL output in Bypass mode can be connected to the ECLK
ECLK
clk
IDDRX2D1
ECLK SCLK
D
datain
CDIV2
CLKDIVB
DELAYC
IDDRAPPS=ECLK_CENTERED q
4
ECLK
clk
IDDRX2D
ECLK SCLK
datain D
CDIV2
CLKDIVB
DELAYC
q
4
DQSBUFE ECLKDQSR
DDRLAT
DDRCLKPOL12-28
LatticeECP3 High-Speed
I/O Interface
as well.
• The clock net connected to SCLK must be routed on a primary routing resource using the “USE PRIMARY
NET” preference.
• There is only one CLKDIVB per side of the device, so the interface is limited to one per side.
• The data/clock pin assignments for “E” devices require following the DQ-DQS group pinout guidelines. See the
Generic DDR Design Guidelines section for details. This is not required for “EA” devices.
GDDRX2_RX.DQS.Aligned
Generic DDR Receive Interface with x2 Gearing using a DQS lane with Aligned External Interface
Device Support: “E” and “EA” devices
Description
This DDR x2 interface uses the DQS and the DQSDLL to provide a 90° clock shift to center the clock at the
IDDRXD. This interface uses a DQS lane and is useful for small data buses (<11 bits). There is only one DQSDLL
per side of the device which limits sharing of this interface on a side unless all are running at the same rate.
This interface uses x2 gearing with the IDDRX2D element. This requires the use of a CLKDIVB to provide the
SCLK which is half the frequency of the ECLK and ECLKDQSR.
This interface requires the use of a secondary input pll_clk for the PLL input. The PLL output must run at the same
rate as the DQSI clk input, but can be arbitrary phase.
Figure 12-22. GDDRX2_RX.DQS.Aligned Interface (“E” and “EA” Devices)
Interface Rules
• The input clock must use a DQS input pin and all data inputs must be in the same DQS lane.
DQSBUFD
ECLKDQSR
dqsdll_uddcntln
dqsdll_reset
DQSDLL
IDDRX2D
IDDRAPPS=DQS_ALIGNED*
DDRCLKPOL ECLKDQSR SCLK
datain_0 D
ECLK
pll_clk
DDRLAT
DQSI ECLKDQSR
ECLK
SCLK
DDRLAT
RESET DDRCLKPOL
READ
reset_0
PLL
CLKOS
CLKOK
*IDDRAPPS is only required for “EA” devices.
4
q_012-29
LatticeECP3 High-Speed
I/O Interface
• The input pll_clk must use a GPLLT_IN or GDLLT_IN input pin or from a primary clock tree.
• The clock net connected to SCLK must also be routed on a primary routing resource using the “USE PRIMARY
NET” preference.
• There is only one DQSDLL per side of the device which limits sharing of this interface on a side unless all are
running at the same rate.
• The following sequence must be followed when resetting the interface:
– Assert DQSDLL_RESET to DQSDLL and RESET to the modules
– Deassert DQSDLL_RESET to DQSDLL first
– Wait for DQSDLL lock to go high
– Assert DQSDLL_UDDCNTLN input of DQSDLL for at least four SCLK cycles. See the section “DQSDLLB”
on page 89 for the detailed requirements for the DQSDLL_UDDCNTLN input of DQSDLLB
– Deassert DQSDLL_UDDCNTLN
– Wait for four SCLK cycles, then deassert RESET to the other modules
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
• The VREF1 for the selected DQS lane must be powered on the board.
GDDRX2_RX.DQS.Centered
Generic DDR Receive Interface with x2 Gearing using a DQS lane with Centered External Interface
Device Support: “E” and “EA” devices
Description
This DDR x2 interface uses the DQS and DELAYC to match clock and data delay at the IDDRX2D. This interface is
useful for small data buses (<11 bits). Since a 90° shift is not required, the DQSDLL is held in reset for this interface. An additional refclk input running at the same as the clk input to DQSI is provided to the DQSDLL, ECLK input
of the IDDRX2D. It is also used in the CLKDIV module to generate the SCLK which is half the frequency as the
input clock.12-30
LatticeECP3 High-Speed
I/O Interface
Figure 12-23. GDDRX2_RX.DQS.Centered Interface (“E” and “EA” Devices)
Notes:
1. The DELAYC is only applicable for “EA” devices. For “E” devices, change DELAYC to DELAYB and set the value to 7.
2. When retargeting from “E” to “EA”, manually update DELYAB to DELAYC, otherwise the software will error out.
Interface Rules
• The input clock must use a DQS input pin and all data inputs must be in the same DQS lane.
• The ECLK clock input must use a dedicated GPLLT_IN input or PCLK input pin or from a primary clock tree. This
second synchronous clock input is used for the DQSDLL, ECLK, and CLKDIV.
• There is only one DLLDELB and one CLKDIV per side of the device (left and right sides) which limits this interface to one clock rate per side or two per device.
• The clock net connected to SCLK must be routed on a primary routing resource using the “USE PRIMARY
NET” preference.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
• The VREF1 for the selected DQS lane must be powered on the board.
GDDRX2_RX.ECLK.Dynamic
Generic DDR Receive Interface with x2 Gearing using ECLK with Centered External Interface and Dynamic Data
Delay Control
Device Support: “EA” devices
Description
This interface uses a DELAYB and ECLK for bit-level control of the alignment. User logic will control the inputs of
the DELAYB delay module. The CLKDIV module is used to generate the SCLK which is half the frequency of
DQSBUFD
ECLKDQSR
clk_0
DQSDLL
IDDRX2D
IDDRAPPS =DQS_CENTERED *
DDRCLKPOL ECLKDQSR SCLK
datain_0 D
CLKDIVB
ECLK
eclk
DDRLAT
DQSI ECLKDQSR
ECLK
SCLK
DDRLAT
DDRCLKPOL
1
RST
DELAYC
reset_0 READ
*IDDRAPPS is only required for “EA” devices.
4
q_012-31
LatticeECP3 High-Speed
I/O Interface
ECLK. This interface should only be used when the input clock is centered to the data as this interface does not
have phase-shift capability on the clock. This interface is similar to the GDDRX2_RX.ECLK.Centered, but in this
version the data delay is controlled dynamically by the user.
Figure 12-24. GDDRX2_RX.ECLK.Dynamic (“EA” Devices)
Interface Rules
• Input clock port must use a dedicated clock (PCLK) input pin. All the data for the interface must be on the same
ECLK tree (same side of the device).
• The clock net connected to SCLK must be routed on a primary routing resource using the “USE PRIMARY
NET” preference.
• There is only one CLKDIVB per side of the device, so the interface is limited to one per side.
GDDRX2_RX.DQS.Dynamic
Generic DDR Receive Interface with x2 Gearing using a DQS lane with Centered External Interface and Dynamic
Data Delay Control
Device Support: “EA” devices
Description
This interface uses a DELAYB and DQS lane for bit-level control of the alignment. User logic will control the inputs
of the DELAYB delay module. CLKDIV module is used to generate the SCLK which is half the frequency of ECLK.
This interface should only be used when the input clock is centered to the data as this interface does not have
phase-shift capability on the clock. This interface is similar to the GDDRX2_RX.DQS.Centered, but in this version
the data delay is controlled dynamically by the user.
clk
IDDRX2D1
ECLK SCLK
datain DELAYB D
CDIV2
CLKDIVB
IDDRAPPS = ECLK_DYNAMIC
4
q
412-32
LatticeECP3 High-Speed
I/O Interface
Figure 12-25. GDDRX2_RX.DQS.Dynamic (“EA” Devices)
Interface Rules
• The input clock must use a DQS input pin and all data inputs must be in the same DQS lane.
• The eclk clock input must use a dedicated GPLLT_IN input or PCLK input pin. This second synchronous “eclk”
input is used for the DQSDLL, ECLK, and CLKDIV.
• The clock net connected to SCLK must be routed on a primary routing resource using the “USE PRIMARY
NET” preference.
• There is only one DLLDELB and one CLKDIV per side of the device (left and right sides) which limits this interface to one clock rate per side or two per device.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
GDDRX2_RX.PLL.Dynamic
Generic DDR Receive Interface with x2 Gearing using ECLK with Dynamic control on ECLK phase using PLL
Device Support: EA devices
Description
This interface uses a PLL to delay the ECLK for bus-level control of the alignment. The benefit of the PLL is that an
entire period of delay is provided. User logic will control the DPHASE input to the PLL.
DQSBUFD
ECLKDQSR
clk_0
DQSDLL
IDDRX2D
IDDRAPPS=DQS_DYNAMIC
DDRCLKPOL ECLKDQSR SCLK
datain_0 D
CLKDIVB
ECLK
eclk
DDRLAT
DQSI ECLKDQSR
ECLK
SCLK
DDRLAT
DDRCLKPOL
1
RST
DELAYB
reset_0 READ
q_0
4
412-33
LatticeECP3 High-Speed
I/O Interface
Figure 12-26. GDDRX2_RX.PLL.Dynamic (“EA” Devices)
Interface Rules
• The input clock must use a dedicated GPLLT_IN clock input pin. The clock net connected to SCLK must be
routed on a primary routing resource using the “USE PRIMARY NET” preference.
GOREG_TX.SCLK
Generic SDR Transmit Interface using SCLK
Device Support: “E” and “EA” devices
Description
This is a generic interface for SDR data and a forwarded clock. The ODDR used for the clock balances the clock
path to match the data path. A PLL can also be used to clock the ODDRXD to phase shift the clock to provide a
precise clock-to-data output.
On “E” devices, the sides (left and right) need to pass through a DQSBUFG before going to the ODDRXD element.
The top does not require the DQSBUFG and can take SCLK directly.
The “EA” device does not require a DQSBUFG block.
Figure 12-27. GOREG_TX.SCLK Interface (“EA” Devices)
clkin
IDDRX2D1
ECLK SCLK
datain D
DPHASE[3:0]
CLKOS
CLKOK
PLL
IDDRAPPS = PLL_DYNAMIC 4
q
OREG
clk
dout
Clkout
ODDRXD1
0
1
SCLK
ODDRAPPS =
SCLK_ALIGNED
d12-34
LatticeECP3 High-Speed
I/O Interface
Figure 12-28. GOREG_TX.SCLK Interface (“E” Devices, Top)
Figure 12-29. GOREG_TX.SCLK Interface (“E” Devices, Left/Right)
Interface Rules
• SCLK must be routed on either primary or secondary clock resources using the USE PRIMARY NET or
USE SECONDARY preferences.
GDDRX1_TX.SCLK.Centered
Generic DDR Transmit Interface using SCLK with Centered External Interface
Device Support: “E” and “EA” devices
OREG
clk
dout
clkout
ODDRXD
0
1
DQCLK1
SCLK
d
OREG
clk
dout
DQSBUFG
clkout
ODDRXD
0
1
DQCLK1
SCLK
d12-35
LatticeECP3 High-Speed
I/O Interface
Description
This output DDR interface provides clock and data that are pre-centered using a PLL and two SCLKs.
On “E” devices, the left and right sides need to pass through a DQSBUFG before going to the ODDRXD element.
The top side of the “E” device does not require the DQSBUFG and can take SCLK directly. When using the DQSBUFG the clock output will need to be in a different DQS lane than the data since there is only one DQSBUFG per
lane.
The “EA” device does not require the DQSBUFG.
Figure 12-30. GDDRX1_TX.SCLK.Centered Interface (“EA” Devices)
Figure 12-31. GDDRX1_TX.SCLK.Centered Interface (“E” Devices, Top)
PLL 90°
da[0]
clk clkout
ODDRXD1
1
0
q
ODDRXD1
SCLK
DA
SCLK
ODDRAPPS =
SCLK_CENTERED
ODDRAPPS =
SCLK_ALIGNED
db[0] DB
DA
DB
PLL 90°
da[0]
clk clkout
ODDRXD
1
0
DQCLK1
q
ODDRXD
DQCLK1
SCLK
SCLK
DA
DB
DA
DB db[0]12-36
LatticeECP3 High-Speed
I/O Interface
Figure 12-32. GDDRX1_TX.SCLK.Centered Interface (“E” Devices, Left/Right)
Interface Rules
• On “E” devices, the clock and data outputs need to be in different DQS lanes on the left and right sides since
there is only one DQSBUFG per lane. Clock and data outputs can use the same DQS lane on top. Clock and
data outputs cannot use the DQS site. They must use the DQ site.
• SCLK and 90° shifted SCLK should be assigned to a primary clock pin using the “USE PRIMARY NET”
preference.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments for the “E” device.
Refer to the Generic DDR Design Guidelines section for details. “EA” devices do not have this requirement. The
clock pin to the PLL path must be routed on a dedicated clock route. A dedicated GPLLT_IN pin must be used for
input of this clock.
GDDRX1_TX.SCLK.Aligned
Generic DDR Transmit Interface using SCLK with Aligned External Interface
Device Support: “E” and “EA” devices
Description
This output DDR interface provides clock and data that are aligned using a single SCLK.
PLL 90°
da[0]
clk DQSBUFG
DQSBUFG
clkout
ODDRXD
1
0
DQCLK1
SCLK
q
ODDRXD
DQCLK1
SCLK
DA
DA
DB
db[0] DB12-37
LatticeECP3 High-Speed
I/O Interface
Figure 12-33. GDDRX1_TX.SCLK.Aligned Interface (“EA” Devices)
“E” devices require the use of DQSBUFG on the left and right sides of the device. If the clock and data bus can fit
in the same DQS lane then a single DQSBUFG is all that is needed (<10 bits). For a wider data bus (>0 bits) it is
required to use a DQSBUFG for clock and data and assign the clock to a different DQS lane.
Figure 12-34. GDDRX1_TX.SCLK.Aligned Interface (“E” Devices, Top Side)
clk clkout
ODDRXD1
1
0
q
ODDRXD1
SCLK
DA
SCLK
DA
DB
db[0] DB
da[0]
ODDRAPPS =
SCLK_CENTERED
ODDRAPPS =
SCLK_ALIGNED
clk clkout
ODDRXD
1
0
DQCLK1
q
ODDRXD
DQCLK1
SCLK
SCLK
DA
DA
DB
db[0] DB
da[0]12-38
LatticeECP3 High-Speed
I/O Interface
Figure 12-35. GDDRX1_TX.SCLK.Aligned Interface (“E” Devices, Left/Right Sides) < 10 Bits
Figure 12-36. GDDRX1_TX.SCLK.Aligned Interface (“E” Devices, Left/Right Sides) > 10 Bits
Interface Rules
• On “E” devices, the clock and data outputs need to be in different DQS lanes on the left and right sides since
there is only one DQSBUFG per lane. Clock and data outputs can use the same DQS lane on top. Clock and
data outputs cannot use the DQS site. They must use the DQ site.
• The clock to SCLK must be routed on a primary routing resource using the “USE PRIMARY NET” preference.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments for “E” devices.
Refer to the Generic DDR Design Guidelines section for details. “EA” devices do not have this requirement.
clk ODDRXD clkout
1
0
DQCLK1
q
ODDRXD
DQCLK1
SCLK
SCLK
DQSBUFG
DA
DA
DB
db[0] DB
da[0]
da[0]
clk clkout
ODDRXD
1
0
DQCLK1
q
ODDRXD
DQCLK1
SCLK
SCLK
DQSBUFG
DQSBUFG
DA
DA
DB
db[0] DB12-39
LatticeECP3 High-Speed
I/O Interface
GDDRX1_TX.DQS.Centered
Generic DDR Transmit Interface using DQS Lane with Centered External Interface
Device Support: “E” and “EA” devices
Description
This output DDR x1 interface provides clock and data that is pre-centered using a DQSDLL and ODDRXDQSA.
This is the same as the GDDRX1_TX.SCLK.Centered, but does not require a PLL. This interface can also be used
multiple times using the same DQSDLL. This interface should be used for narrow data buses (<11 bits wide)
Figure 12-37. GDDRX1_TX.DQS.Centered Interface (“E” and “EA” Devices)
Interface Rules
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
• There is only one DQSDLL per side of the device. One of these interfaces can be placed in each DQS group, but
they all need to run at the same rate for that side.
• The following sequence must be followed when resetting the interface:
– Assert DQSDLL_RESET to DQSDLL and RESET to the modules
– Deassert DQSDLL_RESET to DQSDLL first
– Wait for DQSDLL lock to go high
– Assert DQSDLL_UDDCNTLN input of DQSDLL for at least four SCLK cycles. See the section “DQSDLLB”
on page 89 for the detailed requirements for the DQSDLL_UDDCNTLN input of DQSDLLB
DQSBUFF
DQCLK1
clk_0
reset
dqsdll_uddcntln
dqsdll_reset
DQSDLL
ODDRXDQSA
DQCLK1 SCLK
da_0[0] D
ODDRXD
q_0
clkout_0
DQCLK1 SCLK
DQSW
SCLK
READ
ODDRAPPS = DQS_CENTERED*
ODDRAPPS = DQS_ALIGNED*
DA
db_0[0] DB
1
DA
*ODDRAPPS required only for “EA” devices.12-40
LatticeECP3 High-Speed
I/O Interface
– Deassert DQSDLL_UDDCNTLN
– Wait for four SCLK cycles, then deassert RESET to the other modules
• “clk_0” must use the primary clock tree. It is the user’s responsibility to assign “USE PRIMARY NET” preference on this net to assign it to the primary clock.
• This interface cannot use the LVDS25 IO_TYPE for the clkout from the DQSI.
GDDRX2_TX.Aligned
Generic DDR x2 Transmit Interface with Aligned External Interface
Device Support: “EA” devices only
Description
This output DDR x2 interface provides clock and data that are aligned. A PLL is used to generate ECLK. A CLKDIV
is use to generate the SCLK which is half the frequency of the ECLK. The PLL CLKOK can also be used to generate the SCLK. Additional soft logic is required for this interface to work as expected. This logic is used to control the
ECLKSYNCA to create the proper relationship between ECLK and SCLK.
Figure 12-38. GDDRX2_TX.Aligned Interface (“EA” Devices)
Interface Rules
• Clock input must use a dedicated GPLLT_IN input pin or from a primary clock tree.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
• The additional soft logic required for this interface is included in the module generated using IPexpress.
• Clock to the reset flops should be at least half the speed or slower than the ECLK.
• The clock to SCLK must be routed on a primary routing resource using the “USE PRIMARY NET” preference.
GDDRX2_TX.DQSDLL.Centered
Generic DDR x2 Transmit Interface with Centered External Interface using DQSDLL
da[0]
Reset
clk
ODDRX2D
SCLK DQCLK1 DQCLK0
DQSBUFE1
RESET
ECLKW
Eclk
ECLKSYNCA
ODDRX2D
SCLK DQCLK1 DQCLK0
clkout
q
PLL
CLKDIV
Set Set
ODDRAPPS=ECLK_ALIGNED
ODDRAPPS=ECLK_ALIGNED
DA0
DB0
DA1
DB1
DA0
DB0
DA1
DB1
db[0]
da[0]
db[0]
0
1
0
1
CLKOK
CLKOP12-41
LatticeECP3 High-Speed
I/O Interface
Device Support: “EA” devices
Description
This output DDR x2 interface provides a clock and data that are centered. This interface uses a DQSDLL along
with the DQSBUFD to generate the 90° delayed clock used to generate the clock output. ODDRDQSA module is
used for clock generation. A CLKDIV is use to generate SCLK which is half the frequency of the ECLK. Additional
logic is needed to control the ECLKSYNCA to create the proper relationship between ECLK and SCLK.
Figure 12-39. GDDRX2_TX.DQSDLL.Centered Interface (“EA” Devices)
Interface Rules
• Clock inputs must come in from a primary clock tree.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
• The additional logic required for this interface is included in the module generated using IPexpress.
• Clock to the reset flops should be at least half the speed or slower than the ECLK.
• There is only one DQSDLL per side of the device. One of these interfaces can be placed in each DQS group, but
they all need to run at the same rate for that side.
• The following sequence must be followed when resetting the interface:
– Assert DQSDLL_RESET to DQSDLL and RESET to the modules
– Deassert DQSDLL_RESET to DQSDLL first
– Wait for DQSDLL lock to go high
– Assert DQSDLL_UDDCNTLN input of DQSDLL for at least four SCLK cycles. See the section “DQSDLLB”
on page 89 for the detailed requirements for the DQSDLL_UDDCNTLN input of DQSDLLB
– Deassert DQSDLL_UDDCNTLN
– Wait for four SCLK cycles, then deassert RESET to the other modules
ODDRX2D
SCLK DQCLK1 DQCLK0
DQSBUFD
SCLK
RESET
ECLK/ECLKW
dqsdll_uddcntln
dqsdll_reset
reset
ODDRX2DQSA
SCLK DQCLK1 DQSW DQCLK0
clkout_0
q_0
DQSDLL
ECLKSYNCA
CLKDIV
Set Set
clk
clk_s
ODDRAPPS = DQS_CENTERED
ODDRAPPS = DQS_ALIGNED
da_0[0]
DB0
DB1
DA0
DB0
DA1
DB1
db_0[0]
da_1[0]
db_1[0]
1
112-42
LatticeECP3 High-Speed
I/O Interface
• The clock to SCLK must be routed on a primary routing resource using the “USE PRIMARY NET” preference.
• CLKOUT must be assigned to a DQS pin. The DQS pins do not support True LVDS outputs, hence CLKOUT
cannot use LVDS IO_TYPE.
GDDRX2_TX.PLL.Centered
Generic DDR x2 Transmit Interface with Centered External Interface using PLL
Device Support: “EA” devices only
Description
This output DDR x2 interface provides a clock and data that are centered. This interface uses a PLL to generate
the 90° phase shift required for the clock. A CLKDIV is used to generate SCLK which is half the frequency of the
ECLK. Additional logic is required to control the ECLKSYNCA to create the proper relationship between ECLK and
SCLK.
Figure 12-40. GDDRX2_TX.PLL.Centered (“EA” Devices)
Interface Rules
• Clock input must use a dedicated GPLLT_IN input pin or from a primary clock tree.
• The pin assignments for data and clock will require following the DQ-DQS lane assignments. Refer to the
Generic DDR Design Guidelines section for details.
reset
clk
ODDRX2D
SCLK DQCLK1 DQCLK0
DQSBUFE1
RESET
ECLKW
Eclk
ECLKSYNCA
q
PLL
CLKDIV
Set Set
ODDRX2D
SCLK DQCLK1 DQCLK0
clkout
DQSBUFE1
RESET
ECLKW
Eclk 90°
ODDRAPPS=ECLK_CENTERED
ODDRAPPS=ECLK_ALIGNED
DA0
DB0
DA1
DB1
0
1
0
1
da[0] DA0
DB0
DA1
DB1
db[0]
da[0]
db[0]
CLKOK
CLKOP
CLKOS12-43
LatticeECP3 High-Speed
I/O Interface
• The clock to SCLK must be routed on a primary routing resource using the “USE PRIMARY NET“preference.
• The additional soft logic required for this interface is included in the module generated using IPexpress.
• Clock to the reset flops should be at least half the speed or slower than the ECLK.
7:1 LVDS Implementation
It is recommended that the 7:1 LVDS Video Interface Reference Design provided on the lattice web site be used to
implement all 7:1 LVDS designs.
Generic DDR Design Guidelines
This section describes the various design guidelines used for building generic high-speed DDR interfaces in
LatticeECP3 FPGAs. In additional to these guidelines, it is also necessary to follow the interface rules for each
interface type as described above.
Placement Guidelines for High-Speed DDR Interfaces
The following clock and data placement guidelines should be followed for high-speed design requirements. The
software will place the clock and data as specified by the user, but in order to achieve higher speeds the user must
follow the placement rules listed in Table 12-6 for each interface type.
It is required that all clocks used to clock the DDR Interfaces use a dedicated clock path. No general routing should
be used to route the clock pin. General routing used for a clock path will cause duty cycle distortion as well as limit
the operational frequency of the interface. It is the responsibility of the user to assign clock inputs to dedicated
clock pins and use preferences such as “USE PRIMARY NET” to route clock nets on dedicated clock paths.
Table 12-6 lists the various high-speed interfaces and the placement required for the clock and data.
Table 12-6. Pin Placement Guidelines for High-Speed Interfaces
DDR Interface
LatticeECP3 “EA” Devices LatticeECP3 “E” Devices
DATA CLK CLK PIN DATA CLK CLK PIN
GDDRX1_RX.SCLK.Aligned
L/R/T L/R GDLLT_IN N/A N/A N/A
L/R/T L/R GPLLT_IN N/A N/A N/A
L/R/T T PCLK N/A N/A N/A
GDDRX1_RX.SCLK.Centered
L/R/T L/R/T PCLK N/A N/A N/A
L/R/T L/R/T GPLLT_IN N/A N/A N/A
GDDRX1_RX.ECLK.Aligned N/A N/A N/A L/R L/R GDLLT_IN
GDDRX1_RX.ECLK.Centered N/A N/A N/A L/R L/R PCLK
GDDRX1_RX.DQS.Aligned L/R/T L/R/T DQS L/R L/R DQS
GDDRX1_RX.DQS.Centered L/R/T L/R/T DQS L/R L/R DQS
GDDRX2_RX.ECLK.Aligned
L/R/T L/R GDLLT_IN L/R L/R GDLLT_IN
L/R/T L/R GPLLT_IN N/A N/A N/A
L/R/T T PCLK N/A N/A N/A
GDDRX2_RX.ECLK.Centered
L/R L/R PCLK L/R L/R PCLK
L/R/T L/R GPLLT_IN N/A N/A N/A
GDDRX2_RX.DQS.Aligned L/R L/R DQS L/R L/R DQS
GDDRX2_RX.DQS.Centered L/R L/R DQS L/R L/R DQS
GDDRX2_RX.ECLK.Dynamic L/R L/R PCLK N/A N/A N/A
GDDRX2_RX.DQS.Dynamic L/R L/R DQS N/A N/A N/A12-44
LatticeECP3 High-Speed
I/O Interface
High-Speed Clock Bridge (“EA” Devices)
The high-speed clock bridge is available only on “EA” devices on the GDDRX2.RX.PLL_Dynamic interface. The
bridge enables a clock to route to a single edge clock or multiple edge clocks on the device using a three-way
(left/right/top) bridge. It can only be used on clocks coming in from the left side dedicated GPLLT pin or PLL output.
The software preference EDGE2EDGE is used to enable this route.
For example, USE EDGE2EDGE ; where “pllin_c” is the clock net coming from the dedicated GPLLT pin.
When this preference is placed on the clock coming in on the left side GPLLT pin, this clock will be connected to the
one of the ECLK on the left, right and top sides using a dedicated route. This ECLK on all three sides cannot be
used for any other ECLK function. User will have to make the following changes to the GDDRX2.RX.PLL_Dynamic
module generated by IPExpress to incorporate the ECLKBRIDGE.
• A CLKDIV should be used to generate SCLK instead of using PLL CLKOK. The CLKOS output of the PLL should
be connected to the input of the CLKDIV module. Output of CLKDIV is used as SCLK.
• User will have to instantiate 2 ECLKSYNC modules to be used on either side of the device. Both of them should
be connected to the CLKOS of the PLL used as ECLK.
• An EDGE2EDGE preference should be assigned to the CLKOS output of the PLL to be used as ECLKBRIDGE.
DQ-DQS Grouping Rules
Due to differences in architecture between the LatticeECP3 “E” and “EA” devices, the DQ-DQS grouping that is
required for some interfaces in “E” devices is not required for “EA” devices. It is necessary to use the DQS grouping
structure to group pins when either of the DQSBUFE/DQSBUFF/DQSBUFG modules is used in an interface. Refer
to the section High-Speed DDR Interface Details to see the requirements for each device.
Below are some of the rules to be followed when locking DQS groups. ispLEVER will check for these rules during
MAP and Place and Route.
• Each DQS pin has a DQSBUF block which spans across 12 pins including the DQS and DQS# pins. Each DQSBUF sends out control logic to these pins.
• The DQS# I/O logic registers cannot be used to implement DDR registers. DQS pins can be used for IDDR
implementation only. ODDR cannot be assigned to a DQS pin.
GDDRX2_RX.PLL.Dynamic
L/R L/R GPLLT_IN N/A N/A N/A
L/R/T L High Speed
Bridge2,3 N/A N/A N/A
GDDRX2_RX.ECLK.DR L/R L/R GPLLT_IN N/A N/A N/A
GDDRX1_TX.SCLK.Centered L/R/T L/R/T ANY L/R L/R ANY
GDDRX1_TX.SCLK.Aligned L/R/T L/R/T ANY L/R L/R ANY
GDDRX1_TX.DQS.Centered L/R/T L/R/T DQS L/R L/R DQS
GDDRX2_TX.ECLK.Aligned L/R L/R ANY L/R L/R ANY
GDDRX2_TX.Centered (DQS) L/R L/R DQS L/R L/R DQS
GDDRX2_TX.Centered (PLL) L/R L/R ANY L/R L/R ANY
1. L, R and T refer to “Left”, “Right” and “Top” sides of the device.
2. The high-speed clock bridge can be accessed by using the “USE EDGE2EDGE < clk> “software preference. For preference details please
see “ispLEVER Help” in the software.
3. High-speed bridge is only available on “EA” devices.
4. Top-side DDR is not supported on “E” devices.
Table 12-6. Pin Placement Guidelines for High-Speed Interfaces (Continued)
DDR Interface
LatticeECP3 “EA” Devices LatticeECP3 “E” Devices
DATA CLK CLK PIN DATA CLK CLK PIN 12-45
LatticeECP3 High-Speed
I/O Interface
• The DQS and DQS# I/O logic registers can be used to implement SDR input and output registers. If the DQSBUF of that DQS group is used then it cannot be used for SDR functions unless the same clock going to the
DQSBUF is used to clock the SDR register at the DQS/DQS# site.
• An IDDRX element used for a generic DDR interface cannot be mixed in a DQS group with an ODDRX element
used for implementing a DDR memory interface.
• Similarly, an ODDRX element used for a generic DDR interface cannot be mixed in a DQS group with an IDDRX
element used for a DDR memory interface.
• The ODDRXD and ODDRX2D elements in a given DQS group cannot share the same DQSBUF and therefore
cannot be placed together within the same DQS group.
• The upper left corner of the LatticeECP3 device has a DQS group without a DQS pin. This group of I/Os does not
have a DQS function. It is recommended to use this group for pins in non-DQS interfaces.
• See Table 12-13 to see the availability on each side.
I/O Logic (IOL) Site Types/Names
Based on the functions they support, I/O logic blocks are divided into the following site types.
• IOLOGIC – This site supports IREG, OREG, IDDRX, IDDRX2, ODDRX and ODDRX2 functions. These are the
IOLs on the left and right sides of the device.
• SIOLOGIC – This site supports IREG, OREG, IDDRX, IDDRX2 and ODDRX functions. There is no ODDRX2
support in this site. These are mainly the IOLs on the top side of the device.
• XSIOLOGIC – This site supports IREG and OREG only. These are primarily the bottom side IOLs and DQS#
IOLs.
• DQSIOL – These are the DQS IOLs. They support IREG, OREG, IDDRXD, IDDRX2, ODDRXDQSA and
ODDRX2DQSA (left and right sides only) functions
• SDQSIOL – These are DQS IOLs with support for IREG, OREG and DQS ODDRXDQSA functions. Compared
to DQSIOL, there is no ODDRX2DQSA support in this site. These are mostly the DQS IOLs on the top side of
the device.
The software will issue an error message using these site names when an unsupported function is placed on one
of these sites.12-46
LatticeECP3 High-Speed
I/O Interface
Figure 12-41. IOLOGIC Site Types
DQS Lane DQS Lane DQS Lane DQS Lane DQS Lane
DQS Lane DQS Lane DQS Lane DQS Lane
DQS Lane DQS Lane DQS Lane DQS Lane DQS Lane
PCS PCS
DQS Lane
SIOLOGIC
S OI LOG CI
S OI LOGIC
SIOLOGIC
..
..
SDQSIOL DQSBUF
IOLOGIC
IOLOGIC
IOLOGIC
IOLOGIC
.. ..
DQSIOL DQSBUF
XSIOLOGIC
IOLOGIC
IOLOGIC
IOLOGIC
IOLOGIC
.. ..
DQSIOL DQSBUF12-47
LatticeECP3 High-Speed
I/O Interface
Design Rules for Fitting Multiple Interfaces into One Device
Rx Interfaces Running at High Speeds (>250 MHz)
Receive interfaces running at speeds higher than 250 MHz must use the x2 mode gearing DDR elements.
• To achieve high speeds these interfaces must be placed on the left and right sides of the device.
• If implementing a centered interface then the clock input must be locked to a primary clock (PCLK) input pin
• If implementing an aligned interface then the clock input must be locked to a dedicated GPLLT if interface is
using a PLL GDLLT input pin if interface is using a DLL.
• Interfaces using the x2 gearing will need to use the edge clock resource. A single edge clock covers only one
side of the device, hence all the data bits in the data bus should be assigned to one side of the device.
• There are two edge clocks per side. Two interfaces can be implemented per side of the device as long as they
both do not require the DLL or CLKDIV module. See below:
– There is only one CLKDIV and one DLL module available per side, hence two interfaces that use the CLKDIV and/or the DLL module cannot be on the same side.
– When implementing an aligned interface using the DLL module (GDDRX2_RX.ECLK.Aligned) only one
interface can be implemented per side as there is only one DLL and one CLKDIV per side of the device.
– When implementing an aligned interface using a PLL (GDDRX2_RX.PLL.Dynamic), up to two of these interfaces can be implemented per side. It is recommended to allow the software to choose the best clock pins
after locking the data inputs to the desired banks.
– You can mix an aligned interface using a PLL (GDDRX2_RX.PLL.Dynamic) and a centered interface
(GDDRX2_RX.ECLK.Centered) on the same side of the device. It is recommended to allow the software to
choose the best clock pins after locking the data inputs to the desired banks.
– You can mix an aligned interface using a DLL (GDDRX2_RX.ECLK.Aligned) and a centered interface
(GDDRX2_RX.ECLK.Centered) on the same side of the device. It is recommended to allow the software to
choose the best clock pins after locking the data inputs to the desired banks.
– A GDDRX2_RX.ECLK.Aligned and GDDRX2_RX.PLL.Dynamic can be implemented on the same side of
the device. In this case, the clock going to the PLL must be locked to a dedicated PLL clock input pin in the
center of the device close to the DLL pin. For example, if the DLL pin is placed on the LUM0_GDLLT_IN_A
pin then the clock input to the PLL must be placed on the LUM0_GPLLT_IN_A pin. It is recommended to
allow the software to pick the best clock pins after locking the data inputs to the desired banks
– For all interfaces using PLLs, refer to TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide
to see which two dedicated PLL clock outputs can feed the ECLK tree
• When multiple receive interfaces with multiple input clocks are required, and if the data widths for each of these
interfaces is <10 bits wide, then the DQS clock can be used to implement these interfaces
(GDDRX2_RX.DQS.Aligned and GDDRX2_RX.DQS.Centered)
– For these interfaces it is required to connect the input clock to the DQS input pin
– Data bits of the bus must be locked to the corresponding data pins
– See the section “DQ-DQS Grouping Rules” for pin assignment rules.
Rx Interfaces Running at Low Speeds (<250 MHz)
• Receive interfaces running at speeds lower than 250 MHz can use the x1 mode gearing DDR elements.
• If implementing a centered interface then the clock input must be locked to a primary clock (PCLK) input pin
• If implementing an aligned interface then the clock input must be locked to a dedicated “GPLLT” if interface is
using a PLL “GDLLT” input pin if interface is using a DLL.
• Interfaces using the x1 gearing will use the primary clock resource. You can use as many interfaces as the number of primary clocks supported in the device.
– If all interfaces are aligned and using a GDDRX1_RX.SCLK.Aligned interface that uses a DLL, then the
number of interfaces is limited to two as there are two DLLs supported per device.
– If using a GDDRX1_RX.SCLK.PLL.Aligned interface then the number of interfaces per device is limited by
the number of PLLs available in that device.12-48
LatticeECP3 High-Speed
I/O Interface
Tx Interface Running at High Speeds (> 250 MHz)
• Transmit Interfaces running at speeds higher than 250 MHz must use the x2 mode gearing DDR elements.
• To achieve high speeds these interfaces must be placed on the left and right sides of the device.
• Both edge clock and DQS clocks are used to implement the transmit side interfaces
• Data pins must be grouped into the DQS groups on these interfaces
• For interfaces requiring True LVDS outputs, the number of available True LVDS pins per DQS group must be calculated from the data sheet pinout tables since only a limited number of pins support True LVDS outputs. It may
be required to modify the HDL generated from IPexpress to reduce the number of pins assigned to each DQS
group
• All transmit interfaces using the x2 gearing mode use the CLKDIV module, hence only one TX interface can be
implemented per side of the device.
• Inputs to the PLL used in the interface should be on primary clock routing or come in from a dedicated GPLLT
input pin
Tx Interface Running at High Speeds (<250 MHz)
• Transmit interfaces running at speeds lower than 250 MHz can use the x1 mode gearing DDR elements
• Interfaces using the x1 gearing will use the primary clock resource. You can as many interfaces as the number of
primary clocks supported in the device.
• If all interfaces are centered, then the number of interfaces will depend on the number of available PLLs on the
device.
Clocking Guidelines for Generic DDR Interfaces
• Edge clock and primary clock resources are used when implementing a x2 receive or transmit interface
• Only the primary clock (PCLK) resources are used when implementing x1 receive or transmit interfaces
• Each edge clock can only span one side of the device, hence all the data bits of the in the x2 interface must be
locked to one side of the device
• When implementing x1 interfaces, the bus can span any two sides as primary clocks can access DDR registers
on all sides
• There are two edge clocks on each left, right of top side of the device. The bottom side does not support DDR
registers and does not have any edge clocks. There are up to eight primary clocks available on a LatticeECP3
device.
• For high-speed interfaces it is recommended to use the edge clocks on the left and right sides of the device
instead of the top side
• See Design Rules for Fitting Multiple Interfaces into One Device for details on implementing multiple interfaces
on one side of a device
• The ECLK to DDR registers can be accessed through dedicated PCLK pins, GPLL outputs, DLL outputs, and
GPLL input pins. See “LatticeECP3 sysCLOCK PLL/DLL Design & Usage Guide” for details
• Primary clock to DDR registers can be accessed through dedicated PCLK pins, GPLL outputs, DLL outputs &
CLKDIV outputs. See “LatticeECP3 sysCLOCK PLL/DLL Design & Usage Guide” for details
• None of the clocks going to the DDR registers can come from internal general routing.
• DQS clocking is mainly used for DDR memory interface implementation.
• The DQS clock spans every 12 I/O’s include the DQS pins, but only 10 of these can be used for generic DDR
implementation12-49
LatticeECP3 High-Speed
I/O Interface
• DQS clocking can also be used for Generic DDR Receive interfaces when the bus size is 10 or less
• DQS clocking is also used when implementing all Generic DDR x2 Transmit interfaces
• Refer to the “DQ-DQS Grouping Rule” section for pinout assignment rules when using DQS clocking
Common Software Errors and Solutions
• Placement error when implementing Transmit high speed True LVDS interface:
“ERROR - par: DDR assignment finished unsuccessfully.”
DQS grouping is used when implementing 2x gearing on the transmit side. This error occurs then there aren’t
enough true LVDS buffers in one DQS group. IPexpress generates DQS groups correctly for emulated buffers.
Since the number of true LVDS pins vary per device and package, users need to update the module generated
by IPexpress to correct the number of pins per DQS group.
• PAR Routing error when not using dedicated clock routing:
“ERROR - par: netsanitycheck: the clock buf_clk on comp Inst4_DLLDELB port CLKI is driven by general routing
through comp clk”
This error usually occurs when general routing is used on any of clocks routed to any of the DDR modules.
Check the following:
– If using a DLL or PLL, the clock input to the DLL or PLL should be on a dedicated GDLLT or GPLLT pin. A
PCLK pin can be used but a USE PRIMARY preference must be assigned on this clock route from the PCLK
pin to a DLL or PLL.
– If an interface requires the clock to be routed directly to the ECLK or PCLK tree, the PCLK pin should be
used to input the clock. GPLLT or GDLLT pins do not have access to the PCLK or ECLK tree and cannot be
used here.
– If the clocks going to any of the DDR registers are not used in any logic inside the FPGA (like a mux function) this will cause it to get on general route.
– Refer to High-Speed DDR Interface Details to see the clock placement requirements for each type of interface.
• PAR error when assigning a DDR function to a non-DDR I/O pin:
ERROR - par: Cannot place PIO comp "datain_2" on the proposed PIO site "PB11A / AE4" because the types of
their IOLOGICs are incompatible: the associated IOLOGIC comp "datain_2_MGIOL" has been set to
"IDDR_OREG" mode (of type IDDRIOL), while the IOLOGIC site is of type XSIOLOGIC and supports FF only.
In this case an IDDRX2D1 function is placed on the bottom side pin which does not support this function, hence
the error.
See section I/O Logic (IOL) Site Types/Names to see the functions supported on each site type.
• Map Error on IDDRAPPS/ODDRAPPS function:
ERROR - map: The 'IDDRAPPS' property is missing on IDDR instance 'Inst_IDDRX2D1_1_2'. Each IDDR component targeted for this device needs the 'IDDRAPPS' property identifying the interface being implemented.
Refer to DDR usage documentation for details.
All LatticeECP3 “EA” designs require an IDDRAPPS attribute assigned to the input DDR module and an ODDRAPPS attribute assigned to the output DDR module. If these attributes are not assigned then MAP will error out
with the error message above. To fix the error, regenerate the module in IPexpress. IPexpress will generate the
module with all the required input and output DDR attributes. 12-50
LatticeECP3 High-Speed
I/O Interface
Timing Analysis for High-Speed DDR Interfaces
It is recommended that the user run Static Timing Analysis in the software for each of the high-speed interfaces.
This section describes the timing preferences to use for each type of interface and the expected Trace results. The
preferences can either be entered directly in the .lpf file or through the Design Planner graphical user interface.
The External Switching Characteristics section of the LatticeECP3 Family Data Sheet should be used along with
this section. The data sheet specifies the actual values for these constraints for each of the interfaces.
Frequency Constraints
Users must explicitly specify FREQUENCY (or PERIOD) PORT preferences to all input clocks in the design. This
preference may not be required if the clock is generated out of a PLL or DLL or is input to a PLL or DLL.
DDR Input Setup and Hold Time Constraints
All of the receive (RX) interfaces, both x1 and x2, can be constrained with setup and hold preferences.
1. Receive Centered Interface
Figure 12-42 shows the data and clock relationship for a Receive Centered Interface. The clock is centered
to the data, so it comes into the devices with a setup and hold time.
Figure 12-42. RX Centered Interface Timing
Note: tSUGDDR = Setup Time, tHOGDDR = Hold Time
In this case the user must specify in the software preference the amount of setup and hold time available.
These parameters are listed in the figure as tSUGDDR and tHGDDR. These can be directly provided using the
INPUT_SETUP and HOLD preference as:
INPUT_SETUP PORT “Data” ns HOLD ns CLKPORT “Clock”;
where:
Data = Input Data Port
Clock = Input Clock Port
The External Switching Characteristics section of the LatticeECP3 Family Data Sheet specifies the minimum setup and hold times required for each of the high-speed interfaces running at maximum speed.
These values can be picked up from the data sheet if the interface is running at maximum speed.
Example:
For a GDDRX2_RX.ECLK.Centered interface on the left or right sides using a PCLK pin on the
LatticeECP3-150EA-8 device when running at the maximum speed of 405MHz, the preference would be:
INPUT_SETUP PORT "Data" 0.321 ns HOLD 0.321 ns CLKPORT "Clock”;
Note: Please check the LatticeECP3 Family Data Sheet for the latest tSUDDR and tHOGDDR numbers.
t
t
t
HOGDDR t
HOGDDR
SUGDDR SUGDDR
Clock
Data12-51
LatticeECP3 High-Speed
I/O Interface
2. Receive Aligned Interface
Figure 12-43 shows the data and clock relationship for a Receive Aligned Interface. The clock is aligned
edge-to-edge with the data.
Figure 12-43. RX Aligned Interface Timing
Note: tDVACLKGDDR = Data Valid after CLK, tDVECLKGDDR = Data Hold After CLK
In this case, worst case data may occur after the clock edge resulting in a negative setup time when entering the device. The worst case setup is specified by the tDVACLKGDDR after the clock edge and the worst
case hold time is specified as tDVECLKGDDR. The setup and hold time can be specified as:
INPUT_SETUP PORT “Data” <-tDVACLKGDDR > ns HOLD < tDVECLKGDDR> ns CLKPORT
“Clock”;
where:
Data = Input Data Port
Clock = Input Clock Port
Note: A negative number is used for SETUP time as the data occurs after the clock edge in this case.
The External Switching Characteristics section of the LatticeECP3 Family Data Sheet specifies the minimum tDVACLKGDDR and tDVECLKGDDR values required for each of the high-speed interfaces running at maximum speed. These values can be picked up from the data sheet if the interface is running at maximum
speed. The data sheet numbers for this preference are listed in UI (Unit Interface). 1UI is equal to one-half
the clock period. Therefore, these numbers will need to be calculated from the clock period used.
Preference Example:
For a GDDRX2_RX.ECLK.Aligned (no CLKDIV) interface on the left or right side using DLLCLKPIN for
clock input on a LatticeECP3-150EA-8 device running at the maximum speed of 460MHz (UI = 1.09ns),
the preference would be:
t
DVACLKGDDR = 0.225UI = 0.25ns, tDVECLKGDDR = 0.775UI = 0.84ns
The preference for this case is:
INPUT_SETUP PORT "Data" -0.250000 ns HOLD 0.840000 ns CLKPORT "Clock”;
Note: Please check the LatticeECP3 Family Data Sheet for the latest tDVACLKGDDR and tDVECLKGDDR numbers.
3. Receive Dynamic Interfaces
Static Timing Analysis will not show timing for all the dynamic interface cases as the either the clock or
data delay will be dynamically updated at run time.
t
t t
t
Clock
Data
DVACLKGDDR DVACLKGDDR
DVECLKGDDR DVECLKGDDR12-52
LatticeECP3 High-Speed
I/O Interface
DDR Clock to Out Constraints for Transmit Interfaces
All of the transmit (TX) interfaces, both x1 and x2, can be constrained with clock-to-out constraints to detect the
relationship between the clock and data when leaving the device.
Figure 12-44 shows how the clock-to-out is constrained in the software. Minimum tCO is the minimum time after the
clock edge transition that the data will not transition. So any data transition must occur between the tCO minimum
and maximum values.
Figure 12-44. tCO Minimum and Maximum Timing Analysis
1. Transmit Centered Interfaces
In this case, the transmit clock is expected to be centered with the data when leaving the device. Figure 12-
45 shows the timing for a centered transmit interface.
Figure 12-45. Transmit Centered Interface Timing
Figure 12-45 shows that the maximum value after which the data cannot transition is -tDVBCKGDDR. The
minimum value before which the data cannot transition is -(tU + tVBCKGDDR). A negative sign is used
because in this particular case where clock is forwarded centered-aligned to the data, these two conditions
occur before the clock edge.
The LatticeECP3 Family Data Sheet specifies the tDVBCKGDDR and tDVACKGDDR values at maximum speed.
But we do not know the tU value, so the minimum tCO can be calculated using the following equation.
t
CO Min. = -(tDVBGDDR + tU)
½T = tDVAGDDR + tDVBGDDR + tU
t
CO Min. = Data cannot transition BEFORE Min.
t
CO Max. = Data cannot transition AFTER Max.
t
COMin.
t
CO Max.
Clock
Data
t
U
t
DVBGDDR t
DVAGDDR t
DVAGDDR t
DVBGDDR
½ T
Target Edge
Clock
Data
t
DVBGDDR = Data valid before clock
t
DVAGDDR = Data valid after clock
t
U = Data transition12-53
LatticeECP3 High-Speed
I/O Interface
-(tDVBGDDR + tU) = tDVAGDDR - ½T
t
CO Min. = tDVAGDDR - ½T
The clock-to-out time in the software can be specified as:
CLOCK_TO_OUT PORT “Data” MAX <-tDVBGDDR> MIN
CLKPORT “clk” CLKOUT PORT “Clock”;
where:
Data = Data Output Port
Clock = Forwarded Clock Output Port
clk = Input Clock Port
The values for tDVBCKGDDR and tDVACKGDDR can be found in the External Switching Characteristics section
of the LatticeECP3 Family Data Sheet for the maximum speed.
Preference Example:
For a GDDRX1_TX.SCLK.Centered interface running on the LatticeECP3-150EA-8 device at 250MHz,
t
DVBGDDR = tDVAGDDR = 0.670ns, the preference would be:
CLOCK_TO_OUT PORT "Data" MAX -0.670000 ns MIN -1.330000 ns CLKPORT "clk"
CLKOUT PORT "Clock”;
Note: Please check the LatticeECP3 Family Data Sheet for the latest tDVAGDDR and tDVBGDDR numbers.
2. Transmit Aligned Interfaces
In this case, the clock and data are aligned when leaving the device. Figure 12-46 shows the timing diagram for this interface.
Figure 12-46. Transmit Aligned Interface Timing
Figure 12-46 shows that maximum value after which the data cannot transition is tDIAGDDR. The minimum
value before which the data cannot transition is -tDIBGDDR. A negative sign is used for the minimum value
because the minimum condition occurs before the clock edge.
The clock to out time in the software can be specified as:
t
t
t
t
Clock
Data
DIBGDDR
DIBGDDR
DIAGDDR
DIAGDDR
t
DIAGDDR = Data valid after clock.
t
DIBGDDR = Data valid before clock.12-54
LatticeECP3 High-Speed
I/O Interface
CLOCK_TO_OUT PORT “Data” MAX MIN <-tDIBGDDR> CLKPORT “clk” CLKOUT PORT “Clock”;
where:
Data = Data Output Port
Clock = Forwarded Clock Output Port
clk = Input Clock Port
The tDIAGDDR and tDIBGDDR values are available in the External Switching Characteristics section of the
LatticeECP3 Family Data Sheet for maximum speed.
Preference Example:
For a GDDRX2_TX.Aligned interface on the LatticeECP3-150EA-8 device running on the left or right sides
at 500MHz, tDIAGDDR = tDIBGDDR = 0.200ns. The preference would be:
CLOCK_TO_OUT PORT "Data" MAX 0.200000 ns MIN -0.200000 ns CLKPORT "clk" CLKOUT
PORT "Clock”;
Note: Please check the LatticeECP3 Family Data Sheet for the latest tDIAGDDR and tDIBGDDR numbers.
Timing Rule Check for Clock Domain Transfers
Clock Domain Transfers within the IDDR and ODDR modules are checked by Trace automatically when these elements are used in a design. Most clock domain transfers occur in the IDDRX2 and ODDRX2 modules where there
are fast-speed and slow-speed clock inputs. For IDDRX2, there is a transfer from the fast-speed ECLK to the slowspeed SCLK. On the ODDRX2, the transfer happens from the slow-speed SCLK to the fast-speed ECLK.
For ispLEVER 8.0, no special preferences are needed to run this check. The clock domain transfer checks are
automatically done by the software and reported in the Trace report under section called “Timing Rule Check”. The
report lists the timing for the both the input and output DDR blocks where a clock domain transfer is done.
Figure 12-47 shows the transfer of data between the ECLK and SCLK for the IDDRX2 block. A cause of concern is
the phase relationship between the ECLK and SCLK. As in the waveforms below, these two clocks have to maintain a certain amount of skew to transfer data successfully between the two clocks.12-55
LatticeECP3 High-Speed
I/O Interface
Figure 12-47. IDDRX2 ECLK to SCLK Transfer
The skew between the two clocks is specified in terms of “min.” skew and “max.” skew. Figure 12-48 shows how the
“min.” and “max.” skew is measured for the IDDRX2 block. It is required that the “min.” and “max.” skew be within
the specified “min.” and “max.” specs.
Figure 12-48. IDDRX2 ECLK to SCLK Skew Calculation
The following equations are used to check for valid skew between the ECLK and SCLK for an IDDRX2 block.
Max. Skew < - (0 + Internal ECLK to SCLK Setup Time)
Min. Skew > - (ECLK cycle + Internal ECLK to SCLK Hold Time)
D Q
D Q
D Q
D Q
D Q
D Q
L
L
SCLK
D Q
D Q
A
B
J
I
ECLK
L
K
C
D
Max. Skew
Min.
Skew
ECLK
SCLK12-56
LatticeECP3 High-Speed
I/O Interface
The Trace report below shows an example IDDRX2 ECLK to SCLK Timing rule check.
Internal Preference: Timing Rule Check
32 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
This section of the Trace report will identify any inherent timing rule violations
in the design. These rules may be independent of preferences.
Passed: din_i_13_MGIOL meets ECLK to CLK skew range from -2.489ns to 0.006ns
Max skew of -1.367ns meets timing requirement of 0.006ns by 1.373ns
Max ECLK:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.369 M4.PAD to M4.PADDI clk_i
ROUTE 33 0.509 M4.PADDI to IOL_L43EA.ECLK iddr_inst/buf_clk (to sclk_o_c)
--------
0.878 (42.0% logic, 58.0% route), 1 logic levels.
Min CLK:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.369 M4.PAD to M4.PADDI clk_i
ROUTE 33 0.476 M4.PADDI to *V_R61C15.CLKI iddr_inst/buf_clk
CLKOUT_DEL --- 0.353 *V_R61C15.CLKI to *_R61C15.CDIV2 iddr_inst/Inst3_CLKDIVB
ROUTE 33 1.047 *_R61C15.CDIV2 to IOL_L43EA.CLK sclk_o_c
--------
2.245 (32.2% logic, 67.8% route), 2 logic levels.
Min skew of -1.537ns meets timing requirement of -2.489ns by 0.952ns
Min ECLK:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.423 M4.PAD to M4.PADDI clk_i
ROUTE 33 0.476 M4.PADDI to IOL_L43EA.ECLK iddr_inst/buf_clk (to sclk_o_c)
--------
0.899 (47.1% logic, 52.9% route), 1 logic levels.
Max CLK:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.423 M4.PAD to M4.PADDI clk_i
ROUTE 33 0.509 M4.PADDI to *V_R61C15.CLKI iddr_inst/buf_clk
CLKOUT_DEL --- 0.353 *V_R61C15.CLKI to *_R61C15.CDIV2 iddr_inst/Inst3_CLKDIVB
ROUTE 33 1.151 *_R61C15.CDIV2 to IOL_L43EA.CLK sclk_o_c
--------
2.436 (31.9% logic, 68.1% route), 2 logic levels
Note: For paths that are common between the ECLK and CLK, the same delay will be used. For example, since
PADI_DEL is the shared path between the Max. ECLK and Min. CLK for “Max skew calculation” and between Min.
ECLK and Max. CLK for “Min skew calculation” the value is the same in both cases.
The “ECLK to CLK skew range from -2.510 ns to -0.019 ns” for this case is an allowable skew range between the
two clocks.The skew between the two clocks must fall within this range or the Trace will fail on this preference. The
allowable skew range is determined by the frequency at which the fast ECLK clock is running.12-57
LatticeECP3 High-Speed
I/O Interface
Similarly for the ODDRX2D, there is an internal transfer from SCLK to DQCLK0/1 which will be listed in the Timing
Rule Check section as well.
This internal rule check is required for normal data pins but is not required for the forwarded clock output itself
where data inputs to the ODDRX2D are constants. There is no internal data transfer in this case. Users can ignore
Trace reported errors on this Internal Rule Check only for forwarded clocks. These errors may be blocked by a preference like:
BLOCK NET "sclk_c" COMP "clkout_MGIOL";
Where sclk_c is the net on the CLK pin of the IOLOGIC component clkout_MGIOL, where clkout is the forwarded
clock. Trace violations of this rule check on corresponding data outputs need to be understood and resolved.
Preferences for Specific Elements
1. DLLDELB – This element is used in to generate a 90° delay in all receive aligned interfaces. The 90° delay
is calculated based on the input clock to the TRDLLB element. A frequency preference must be provided
on the CLKI of the TRDLLB to allow trace to produce the 90° delay.
2. DQSBUFx – The DQSBUF element used in all the DQS interfaces will delay the DQSI input by 90°. The
90° delay is calculated from the input clock to the DQSDLL element connected via the DQSDEL signal. A
frequency preference must be provided on the CLK input of the DQSDLL to allow trace to produce the 90°
delay.
The DDR Software Primitives and Attributes section provides a detailed description of the DQSBUF elements.
Note: Some device I/O pin names end with an “E_A”, “E_B”, “E_C” or “E_D” (for example, PR43E_B). These pins
are “Input Only” pins. These pins can be used only to implement receive interfaces. The clock delay to these pins is
~50ps longer than the other pins, so you will see some difference in timing between these and other I/O pins.
Valid Window Calculation
Users can calculate the available valid window using the transmitter device specifications to determine if it will be
possible to meet the receiver timing requirements at the LatticeECP3 device.
The data sheet numbers can be used to estimate the required valid window at the LatticeECP3 DDR inputs
depending on the interface type.
For an Rx centered interface the total data valid window required = tSUGDDR + tHGDDR
For an Rx aligned interface the total data valid window required = tDVECLKGDDR - tDVACLKGDDR
For example, in the following case the data at the receiver looks like Figure 12-49.
Figure 12-49. Data at Receiver (Tx Data)
In this case, the data at the LatticeECP3 input is an aligned interface, with the following timing:12-58
LatticeECP3 High-Speed
I/O Interface
Data Rate = 594 Mbps
f
MAX = 297 MHz
Uncertainty around clock edges = 0.350ns
UI = 1.684ns
Since this is an aligned interface, we can calculate tDVECLKGDDR and tDVACLKGDDR to determine the available Data
Valid Window.
t
DVECLKGDDR = 0.350 ns
t
DVACLKGDDR = 1.684 ns – 0.350 ns = 1.334 ns
Data Valid Window = tDVECLKGDDR - tDVACLKGDDR = 0.984 ns
On the LatticeECP3 receive side, we must use the GDDRX2_RX.ECLK.Aligned interface given the frequency and
data to clock alignment of this interface.
For the GDDRX2_RX.ECLK.Aligned for the -6 speed grade, here are the requirements from the data sheet at 297
MHz.
t
DVECLKGDDR = 0.225 UI = 0.379ns
t
DVACLKGDDR = 0.775 UI = 1.305ns
Data Valid Window = tDVECLKGDDR - tDVACLKGDDR = 0.926ns
Note: Please refer to the LatticeECP3 Family Data Sheet for the latest timing numbers.
The required data valid window for this example at the LatticeECP3 DDR input is 0.926 ns and the data valid window available on the interface is 0.984ns. This interface will just meet the timing requirements at the LatticeECP3
device.
To calculate the worst corner case, the software I/O Timing Analysis should be run to see if the worst case required
timing will be met. I/O Timing Analysis will run the timing through all the speed grades of the device family and
show the worst case results. The Trace Report will provide the worst case timing on the same speed grade.
DDR/DDR2/DDR3 SDRAM Interfaces Overview
The DDR SDRAM interface transfers data at both the rising and falling edges of the clock. The DDR2 is the second
generation of the DDR SRDRAM memory, whereas DDR3 is the third generation.
The DDR, DDR2 and DDR3 SDRAM interfaces rely on the use of a data strobe signal, called DQS, for high-speed
operation. The DDR SDRAM interface uses a single-ended DQS strobe signal and the DDR2 and DDR3 interfaces
use a differential DQS strobe. The figures below show typical DDR and DDR2/DDR3 SDRAM interface signals.
SDRAM interfaces are typically implemented with eight DQ data bits per DQS. So, a x16 interface will use two DQS
signals, and each DQS is associated with eight DQ bits. Both the DQ and DQS are bi-directional ports and are
used to read and write to the memory.
When reading data from the external memory device, data coming into the device is edge-aligned with respect to
the DQS signal. This DQS strobe signal needs to be phase shifted 90° before the FPGA logic can sample the read
data. When writing to a DDR/DDR2/DDR3 SDRAM, the memory controller (FPGA) must shift the DQS by 90° to
center-align with the data signals (DQ). A clock signal is also provided to the memory. This clock is provided as a
differential clock (CLKP and CLKN) to minimize duty cycle variations. The memory also uses these clock signals to
generate the DQS signal during a read via a DLL inside the memory. The figures below show DQ and DQS timing
relationships for read and write cycles.12-59
LatticeECP3 High-Speed
I/O Interface
During read, the DQS signal is low for some duration after it comes out of tristate. This state is called Preamble.
The state when the DQS is low before it goes into tristate is the Postamble state. This is the state after the last valid
data transition.
DDR SDRAM also requires a Data Mask (DM) signal to mask data bits during write cycles. Note that the ratio of
DQS to data bits is independent of the overall width of the memory. An 8-bit interface will have one strobe signal.
DDR SDRAM interfaces use the SSTL25 Class I/II I/O standards, DDR2 SDRAM interface uses the SSTL18 Class
I/II and DDR3 SDRAM interface uses the SSTL15 I/O standards. Both the DDR2 and DDR3 SDRAM interfaces
require differential DQS (DQS and DQS#). DDR2 has an option to use either single-ended or differential DQS.
In addition, the DDR3 memory module uses fly-by architecture for the data and strobe signals. This requires the
memory controller to support read and write leveling to adjust for leveled delay on read and write data transfers.
Table 12-7. DDR DDR2 and DDR3 Summary
Figure 12-50. Typical DDR SDRAM Interface
DDR DDR2 DDR3
Data Rate 200 to 400Mbps 250Mbps to 532Mbps 600 to 800Mbps
DQS Single-Ended Single-Ended /Differential Differential
Interface SSTL25 SSTL18 SSTL15
Leveling No No Yes
DDR Memory FPGA
(DDR Memory Controller)
DQ<7:0> 8
DM
DQ<7:0>
DQS
ADDRESS
CONTROL
COMMAND
CLK/CLKN
ADDRESS
CONTROL
COMMAND
CLKP/CLKN
X ADDRESS
CONTROL
COMMAND
DQ<7:0>
DQS
CLK/CLKN
Y
Z
DQS
DM DM12-60
LatticeECP3 High-Speed
I/O Interface
Figure 12-51. Typical DDR2 and DDR3 SDRAM Interface
Figures 12-52 and 12-53 show the DQ and DQS relationship for memory read and write interfaces.
Figure 12-52. DQ-DQS During Read
Figure 12-53. DQ-DQS During Write
Implementing DDR/DDR2/DDR3 Memory Interfaces
As described in the DDR/DDR2/DDR3 SDRAM Interfaces Overview section, all the DDR SDRAM interfaces rely on
the use of a data strobe signal, called DQS, for high-speed operation. When reading data from the external memory device, data coming into the LatticeECP3 device is edge-aligned with respect to the DQS signal. Therefore, the
LatticeECP3 device needs to shift the DQS (90° phase shift) before using it to sample the read data. When writing
FPGA DDR Memory
(DDR Memory Controller)
DQ<7:0> 8
DM
DQ<7:0>
DQS, DQS#
ADDRESS
CONTROL
COMMAND
CLK/CLKN
ADDRESS
CONTROL
COMMAND
CLKP/CLKN
X
ADDRESS
CONTROL
COMMAND
DQ<7:0>
DQS, DQS#
CLK/CLKN
Y
Z
DQS, DQS#
DM DM
DQS
(at PIN) Preamble Postamble
DQS PIN to
REG and 90
Degree
Phase Shift
DQ
(at PIN)
DQS
(at REG)
DQ
(at REG)
DQS
(at PIN)
DQ
(at PIN)12-61
LatticeECP3 High-Speed
I/O Interface
to a DDR SDRAM from the memory controller, the LatticeECP3 device must generate a DQS signal that is centeraligned with the DQ, the data signals. This is accomplished by ensuring a DQS strobe is 90° shifted relative to the
DQ data.
For DDR3 memory, the memory controller also needs to handle the read and write leveling required by the interface due to the newer fly-by topology.
LatticeECP3 devices have dedicated DQS support circuitry for generating appropriate phase-shifting for DQS. The
DQS phase shift circuit uses a frequency reference DLL to generate delay control signals associated with each of
the dedicated DQS pins, and is designed to compensate for process, voltage and temperature (PVT) variations.
The frequency reference is provided through one of the global clock pins. The dedicated DDR support circuit is also
designed to provide comfortable and consistent margins for the data sampling window.
This section describes how to implement the read and write sections of a DDR memory interface. It also provides
details of the DQ and DQS grouping rules associated with the LatticeECP3 devices.
Both the LatticeECP3 “E” and “EA” devices can be used to implement DDR and DDR2 memory interfaces. DDR3
memory interface can only be implemented on the “EA” devices. There are some differences in the DDR memory
implementation between the “EA” and “E” devices. These differences between the devices are indicated in the
appropriate sections below.
See the LatticeECP3 DDR3 Memory Controller IP to see how the DDR3 memory interface can be implemented on
LatticeECP3 “EA” devices. DDR and DDR2 memory interface implementations are described in the sections below.
DQS Grouping
Each DQS group generally consists of at least 10 I/Os (one DQS, eight DQ and one DM) for an 8-bit DDR/DDR2
memory interface or 11 I/Os (two DQS, eight DQ, one DM) to implement a complete 8-bit DDR3 memory interface.
LatticeECP3 devices support DQS signals on the top, left and right sides of the device.
Each DQS signal spans across 12 I/Os. Any 10 (for DDR/DDR2) or 11 (for DDR2/DDR3) of these 12 I/Os spanned
by the DQS can be used to implement an 8-bit DDR memory interface. In addition to the DQS grouping, the user
must also assign one reference voltage VREF1 for a given I/O bank.
Figure 12-54. DQ-DQS Grouping
Figure 12-54 shows a typical DQ-DQS group for LatticeECP3 devices. The seventh I/O of this group of 12 I/Os is
the dedicated DQS pin. All six pads before of the DQS and five pads after the DQS are covered by this DQS bus
span. If using DDR2 or DDR3 memory then the DQS is differential and the eighth pad is used by the DQS# signal.
The user can assign any eight of the other I/O pads to be DQ data pins. Therefore, to implement a 32-bit wide
memory interface you would need to use four such DQ-DQS groups.
When not interfacing with the memory, the dedicated DQS pin can be used as a general-purpose I/O. Note that the
DQS/DQS# pads cannot be used for other DDR functions like DQ, DM or generic DDR. Each of the dedicated DQS
pins is internally connected to the DQS phase shift circuitry. The pinout information contained in the LatticeECP3
Family Data Sheet shows pin locations for the DQS pads and the corresponding DQ pads.
DQS PAD
n* I/O PADS
(7th I/O Pad)
DQ, DM or VREF1 DQ, DM or VREF1
*n=1212-62
LatticeECP3 High-Speed
I/O Interface
Some I/Os on the left, right and top sides will not support DQS grouping. See the DDR Memory DQ/DQS Design
Rules and Guidelines section of this document for further information.
Memory Read Implementation
The LatticeECP3 devices contain a variety of features to simplify implementation of the read portion of a DDR interface:
• DLL-compensated DQS delay elements
• DDR input registers
• Automatic DQS to system/edge clock domain transfer circuitry
• Data Valid Module
DLL-Compensated DQS Delay Elements
The DQS from the memory is connected to the DQS Delay element. The DQS delay block receives a 7-bit delay
control from the on-chip DQSDLL. LatticeECP3 devices support two DQSDLL, one on the left and the other on the
right side of the device. The DQSDEL generated by the DQSDLL on the left side of the device is routed to all the
DQS blocks on the left and top halves of the device. The delay generated by the DQSDLL on the right side of the
device is distributed to all the DQS delay blocks on the right side and the top half of the device. There are no DQS
pins on the bottom banks of the device. These digital delay control signals are used to delay the DQS from the
memory by 90°.
The DQS received from the memory is delayed in each of the DQS delay blocks and this delay DQS is used to
clock the first set stage DDR input registers.
Automatic DQS to System/Edge Clock Domain Transfer Circuitry
In a typical DDR memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system clock (during the read cycle) is unknown. Prior to the read operation in DDR memories DQS is in
tristate. Coming out of tristate, the DDR memory device drives DQS low in the preamble state. The DQS Transition
Detect block detects this transition and generates a signal indicating the required polarity for the FPGA system
clock (DDRCLKPOL). This signal is used to control the polarity of the clock to the synchronizing registers. For the
DDR3 memory interface, this block generates two signals, DDRCLKPOL and DDRLAT. DDRCLKPOL is used to
transfer data from the DDR registers to the synchronization registers clocked by ECLK and the DDRLAT signal is
used to transfer data from the synchronization registers to the clock transfer registers.
Data Valid Module
The data valid module generates a DATAVALID signal. This signal indicates to the FPGA that valid data is transmitted out the input DDR registers to the FPGA core. Note that the DATAVALID signal indicates only the start of valid
read data. It is the memory controller’s responsibility to make the proper width of the read data valid signal.
DDR I/O Register Implementation
The first set of DDR registers is used to de-mux the DDR data at the positive and negative edges of the phaseshifted DQS signal. The latch that captures the positive-edge data is followed by a negative-edge triggered register.
This register transfers the positive edge data from the first register to the negative edge of DQS so that both the
positive and negative portions of the data are now aligned to the negative edge of DQS.
For DDR and DDR2 memory interfaces, the second stage synchronization registers are clocked by the FPGA
clock. The polarity of this clock is selected by the DDR Clock Polarity (DDRCLKPOL) signal generated by the DQS
Transition Detect Block. The FPGA clock clocks an additional set of clock transfer registers at the end before the
data enters the FPGA core.
The DDR3 memory interface uses the gearing feature of the input registers. The synchronization registers are
clocked by the fast edge clock (ECLK) input and are then transferred to the clock transfer registers clocked by the
slower FPGA clock. The polarity of the ECLK is set by the DDRCLKPOL signal and the FPGA clock (SCLK) polarity is set by the DDRLAT signal.12-63
LatticeECP3 High-Speed
I/O Interface
The LatticeECP3 Family Data Sheet describes each of these circuit elements in more depth.
DDR/DDR2 Memory Read Implementation
The following sections explain the DDR/DDR2 read-ide implementation. LatticeECP3 devices support the
DDR/DDR2 memory interface function using the DDR memory mode module generated through the IPexpress
tool. Using IPexpress, a designer can generate the different modules required to read the data coming from the
DDR/DDR2 memory. See the section DDR Memory Interface Generation Using IPexpress for details on the IPexpress interface. This section explains the read side module generated by IPexpress.
The DDR/DDR2 read side is implemented using the following three software elements. The DQSDLL represents
the DLL used for calibration. The IDDRXD implements the input DDR registers. The DQSBUFF represents the
DQS delay block, the clock polarity control logic and the Data Valid module. Figure 12-55 shows the read side
implementation for both the “E” and “EA” devices. IPexpress should be used to generate this interface. See the section DDR Memory Interface Generation Using IPexpress for details.12-64
LatticeECP3 High-Speed
I/O Interface
Figure 12-55. DDR/DDR2 Read Side Implementation for “E” and “EA” Devices
DDR3 Memory Read Implementation
The following sections explain the DDR3 read side implementation. LatticeECP3 devices support the DDR3 memory interface function using the DDR memory mode module generated through the IPexpress tool. Using IPexpress, a designer can generate the different modules required to read the data coming from the DDR3 memory.
See the section DDR Memory Interface Generation Using IPexpress for details on the IPexpress interface. This
section explains the read side module generated by IPexpress.
The DDR3 memory interface generated in IPexpress also includes a Clock Synchronization Module (CSM) that
provides the clock synchronization and alignment among the required clocks for successful DDR3 functionality.
The DDR3 read side is implemented using three software elements. The DQSDLL represents the DLL used for calibration. The IDDRX2D implements the input DDR registers in x2 gearing mode required for DDR3 memory. The
DQSBUFD represents the DQS delay block, the clock polarity control logic and the Data Valid module.
DQSI
DQSW
DQSBUFF
SCLK
READ
DDRCLKPOL
PRMBDET
DQSDEL
DATAVALID
ECLKDQSR
DQCLK1
CLK
RST
UDDCNTLN
LOCK
DQSDEL
DQSDLLB
dq
uddcntln
lock
prmbdet
dqclk1
datavalid
datain_p(0)
datain_n(0)
dqsw
IDDRXD
ECLKDQSR
D
QA
SCLK
DDRCLKPOL QB
dqs
clk
read
clk
DDRCLKPO L
E CLKDQ SR
DQSDEL
rst
dq
IDDRXD
ECLKDQSR
D
SCLK
DDRCLKPOL
.
.
.
clk
clk
datain_p(7)
datain_n(7)
QA
QB12-65
LatticeECP3 High-Speed
I/O Interface
The ECLK, SCLK2X and SCLK are generated in a clock synchronization module (CSM) that provides the clock
synchronization and alignment among the required clocks for successful DDR3 functionality. See the DDR3 Clock
Synchronization Module section for details on the Clock Synchronization Module and internal clock generation
Figure 12-56 shows the read side implementation. IPexpress should be used to generate this interface.
Figure 12-56. DDR3 Read Side Implementation for “EA” Devices
Memory Write Implementation
To implement the write portion of a DDR memory interface, two streams of single data rate data must be multiplexed together with data transitioning on both edges of the clock. In addition, during a write cycle, DQS must arrive
at the memory pins center-aligned with data, DQ. Along with the DQS strobe and DQ, CLKP, CLKN, Address/Command and Data Mask (DM) signals also need to be generated. IPexpress should be used to generate this interface.
See the section DDR Memory Interface Generation Using IPexpress for details.
CLK
RST
UDDCNTLN
LOCK
DQSDEL
DQSDLLB
dq(0)
uddcntln
lock
datain_p0(0)
datain_p1(1)
IDDRX2D
ECLKDQSR
D
QA0
SCLK
QA1 DDRLAT
ECLK
QB0
QB1 DDRCLKPOL datain_n1(1)
datain_n0(0)
DDRLAT
DDRCLKPO L
E CLKDQS R
DQSDEL
rst
datain_p0(7)
datain_p1(7)
IDDRX2D
ECLKDQSR
D
QA0
SCLK
QA1 DDRLAT
ECLK
QB0
QB1 DDRCLKPOL datain_n1(7)
datain_n0(7)
.
.
.
DQSI
DQSW
DQSBUFD
SCLK
READ
DDRCLKPOL
PRMBDET
DQSDEL
ECLK
DATAVALID
DYNDELPOL
DDRLAT
ECLKDQSR
DQCLK0
DQCLK1
prmbdet
dqclk0
dqclk1
datavalid
dqsw
ECLKW
RST
DYNDELAY[6:0]
dqs
read
dyndelay[7:0]
rst
dyndelpol
dq(7)
ECLK
SCLK
S CLK2X
Generated in the
“Clock Synchronization
Module”12-66
LatticeECP3 High-Speed
I/O Interface
Challenges encountered during memory write:
• Differential CLK signals (CLKP and CLKN) need to be generated.
• Generate ADDR/CMD signal edge-aligned to CLKP falling edge.
• DQS needs to be edge-aligned to CLKP. In DDR3 interfaces where fly-by routing is used, write leveling should be
used to compensate for skews between CLKP and DQS.
• DQ/DM needs to be center-aligned to DQS and therefore center-aligned to CLKP as well.
• The controller must meet the DDR interface specification for the tDSS and tDSH parameters, defined as DQS falling edge setup and hold time to/from CLKP rising edge, respectively. The skews, if caused by the fly-by topology,
are compensated by write-leveling.
• The DDR output data must be muxed from two SDR streams into a single outgoing DDR data stream. For the
DDR3 memory interface, this DDR output data is generated from four SDR streams.
The DDR/DDR2 memory write interface is implemented using the following modules:
• IDDRXD, ODDRXD, OFD1S3AX – Used for DDR2 DQ input, output and tri-state control. DDR2 DM uses ODDRXD and OFD1S3AX only.
• ODDRXDQSA, ODDRTDQSA – Used for DDR2 DQS output and tri-state control.
• DQSBUFF – Dedicated for DDR2 memory interface application.
• DQSBUFG – Generic ODDRXD support for clocks on “E” devices.
• ODDRXD – Generic DDR mode for clocks on “E” devices.
• ODDRXD1 – Generic DDR mode for clocks on “EA” devices.
DDR/DDR2 Internal Clock Generation
LatticeECP3 devices require two clocks to implement a DDR/DDR2 memory interface. SCLK (k_clk) is used to
generate the data and data strobe signals while a 270° shifted clock, SCLK1 (k1_clk), is needed to generate the
memory clock and address/command signals. Figure 12-57 shows the generation of these clocks using a PLL.
SCLK is also used for the read side implementation as described in Figure 12-55.
Figure 12-57. DDR/DDR2 Internal Clock Generation
DDR/DDR2 Memory Write Implementation
The following sections explain the DDR/DDR2 write side implementation. LatticeECP3 devices support the
DDR/DDR2 memory interface function using the DDR memory mode module generated through the IPexpress
tool.Using IPexpress, a designer may generate the Data (DQ), Strobe (DQS), Data Mask, Clock (CLKP/CLKN),
Address/Command (ADDR/CMD) signals required when writing to the DDR memory. See the section DDR Memory Interface Generation Using IPexpress for details on the IPexpress Interface. This section explains the different
Write Side modules generated by IPexpress.
DDR/DDR2 Write Side Data (DQ) and Strobe (DQS) Generation
Figure 12-58 shows the DDR2 write side for data and strobe generation. The DQCLK1 and DQSW are signals generated in the DQSBUFF module. DQCLK0 is not used for the DDR2 memory interface. For details on each element, refer to the DDR Software Primitives and Attributes section. The DDR2 memory interface does not require
CLKOP
CLK PLL
CLKOS
SCLK
SCLK1 (270° Shift)12-67
LatticeECP3 High-Speed
I/O Interface
write leveling, therefore the DYNDELAY [6:0] and DYNDELPOL are not used here. The DDR write side will use the
same implementation except that the DQS signal in this case is single-ended.
Figure 12-58. DDR/DDR2 Memory Write DQ and DQS Generation (“E” and “EA” Devices)
DDR/DDR2 Write Side Clock (CLKP/CLKN) Generation
The figures below show the DDR clock output (CLKP/CLKN) generation. The 270° shifted SCLK1 is used to generate the DDR clock outputs. See the section DDR/DDR2 Internal Clock Generation for details. On the LatticeECP3
dqsoa
dqstri_p
ODDRTDQSA
TA
SCLK Q
DB
DQSTCLK
DQSW
SCLK
Q
DA
DQCLK1
ODDRXDQSA
DQSW DQSTCLK
dqs
dqs
dataout_p(0)
dq
OFD1S3AX
SCLK
Q
dataout_n(0)
ta
DQCLK1
DQSW
SCLK
dqstri_n
SCLK
Q
DA
DB
ODDRXD
DQCLK1
D
CK
dataout_p(n)
dq
OFD1S3AX
Q
dataout_n(n)
ta
SCLK
Q
DA
DB
ODDRXD
DQCLK1
D
CK
.
.
.
.
DQSI
DQSW
DQSBUFF
SCLK
READ
DDRCLKPOL
PRMBDET
DQSDEL
DATAVALID
ECLKDQSR
DQCLK1
CLK
RST
UDDCNTLN
LOCK
DQSDEL
DQSDLLB
uddcntln
lock
clk
rst12-68
LatticeECP3 High-Speed
I/O Interface
“E” devices the ODDRXD primitive is used to generate the clocks. The left and right sides of the “E” devices also
require the DQSBUFG which is used to generate the DQCLK1 required in the ODDRXD module. The top side of
the “E” device does not require the use of DQSBUFG and the DQCLK1 input of the ODDRXD can be tied to SCLK.
The “EA” device uses the ODDRXD1 element instead. “EA” devices do not require the use of the DQSBUFG element.
The inputs to the ODDRXD/ODDRXD1 are tied to constant values to generate a clock out of the ODDRXD/ODDRXD1. When interfacing to the DDR SDRAM memory, CLKP should be connected to the SSTL25D I/O
Standard and when interfacing to DDR2 memory it should be connected to SSTL18D I/O Standard to generate the
differential clock outputs. Generating the CLKN in this manner will prevent skew between the two signals.
Figure 12-59. DDR/DDR2 Write Clock Generation (“E” Devices, Left/Right/Top Sides)
Note: (SCLK1=SCLK+270, DA0=0, DB0=1)
ODDRXD
DQSBUFG ODDRXD
SCLK
SCLK1
DA da0
db0
CLK0
CLK0N
da0
db0
CLK1
CLK1N
da0
db0
CLK3
CLK3N
DB
Q
DA
DB
Q
DA
DB
Q
ODDRXD
.
.
DCLK1
DQCLK1
SCLK
DQCLK1
SCLK
DQCLK1
SCLK
DQCLK112-69
LatticeECP3 High-Speed
I/O Interface
Figure 12-60. DDR/DDR2 Write Clock Generation (“E” Devices, Top Side)
Note: (SCLK1=SCLK+270, DA0=0, DB0=1)
ODDRXD
ODDRXD
SCLK
SCLK1
DA da0
db0
CLK0
CLK0N
da0
db0
CLK1
CLK1N
da0
db0
CLK3
CLK3N
DB
Q
DA
DB
Q
DA
DB
Q
ODDRXD
.
.
DQCLK1
SCLK
DQCLK1
SCLK
DQCLK112-70
LatticeECP3 High-Speed
I/O Interface
Figure 12-61. DDR/DDR2 Write Clock Generation (“EA” Devices)
DDR/DDR2 Address/Command Generation
Figure 12-62 shows the address and command generation for the LatticeECP3 “E” and “EA” devices. The 270°
shifted SCLK is used for address and command generation. See the section DDR/DDR2 Internal Clock Generation
for details. SDR registers are used to generate the address and command signals.
Figure 12-62. DDR/DDR2 Address / Command Implementation (“E” and “EA” Devices)
Note: (SCLK1=SCLK+270, DA0=0, DB0=1)
ODDRXD1
ODDRXD1
SCLK
SCLK1
SCLK
SCLK
DA da0
db0
CLK0
CLK0N
da0
db0
CLK1
CLK1N
da0
db0
CLK3
CLK3N
DB
Q
DA
DB
Q
DA
DB
Q
ODDRXD1
.
.
Note: A: Address; BA: Bank Address; RASN: RAS; CASN: CAS; WEN: Write Enable;
CSN: Chip Select; CKE: Clock Enable; ODT: On-Die Termination.
OREG
D
D
Address Din
Command Din
Control Din
SCLK1 (K1_CLK)
A, BA
RASN, CASN, WEN
D Q CSN, CKE, ODT
Q
Q
OREG
OREG12-71
LatticeECP3 High-Speed
I/O Interface
DDR3 Memory Write Implementation
The following sections explain the DDR3 write side implementation. LatticeECP3 devices support the DDR3 memory interface function using the DDR memory mode module generated through the IPexpress tool. Using IPexpress, a designer may generate the Data (DQ), Strobe (DQS), Data Mask, Clock (CLKP/CLKN) and
Address/Command (ADDR/CMD) signals required when writing to the DDR3 memory. See the section DDR Memory Interface Generation Using IPexpress for details on the IPexpress Interface. This section explains the different
write side modules generated by IPexpress.
The DDR3 memory interface generated in IPexpress also includes a Clock Synchronization Module (CSM) that
provides the clock synchronization and alignment among the required clocks for successful DDR3 functionality.
DDR3 Data (DQ) and Strobe (DQS) Generation
Figure 12-63 shows the DDR3 write side implementation for data (DQ) and strobe (DQS) generation. The
DQCLK0, DQCLK1 and DQSW are signals generated in the DQSBUFD module. ODDRX2D implements the output
DDR registers in x2 gearing mode required for DDR3 DQ generation. The ODDRX2DQSA module is used to generate the DQS strobe output. For details on each element, refer to the DDR Software Primitives and Attributes section.
The DDR3 memory interface requires write leveling which is supported with the DYNDELAY [6:0] and DYNDELPOL inputs of DQSBUFD. Users can provide the delays for each DQS group using these ports. They are available
to the user as ports in the top-level module generated by IPexpress.
The ECLK, SCLK2X and SCLK are generated in a clock synchronization module (CSM) that provides the clock
synchronization and alignment among the required clocks for successful DDR3 functionality. See the DDR3 Clock
Synchronization Module section for details on the Clock Synchronization Module.
IPexpress is used to generate these signals. Figure 12-63 shows the module generated by IPexpress data (DQ)
and strobe (DQS) generation.12-72
LatticeECP3 High-Speed
I/O Interface
Figure 12-63. DDR3 Write Side Implementation for DQ and DQS Generation
DDR3 Write Side Clock (CLKP/CLKN) Generation
The SCLK2X out of the Clock Synchronization Module is used to generate the DDR clock outputs. See the section
DDR3 Clock Synchronization Module for details.
The ODDRXD1 element is used to generate the clock. The inputs to the ODDRXD1 are tied to constant values to
generate a clock out of the ODDRXD1. When interfacing to the DDR3 SDRAM memory, CLKP (ddrclkP) should be
connected to the SSTL15D I/O standard to generate the differential clock outputs. Generating the CLKN (ddrclkN)
in this manner will prevent skew between the two signals
dqsob
dqstri_p
ODDRTDQSA
TA
SCLK Q
DB
DQSTCLK
DQSW
SCLK
Q
DB0
DB1
DQCLK0
ODDRX2DQSA
DQSW
DQSTCLK
DQCLK1
dqsoa
dqs
dqs
ODDRX2D
SCLK
DA0
DB0
Q
DQCLK1
dataout_p0(n)
dq
DQCLK0
DA1
DB1
ODDRTDQA
TA
SCLK
Q
DQCLK1
DQCLK0
dataout_p1(n)
dataout_n0(n)
dataout_n1(n)
datatri(1)
DQ CLK0
DQ CLK1
DQSW
SCLK
dqstri_n
ODDRX2D
SCLK
DA0
DB0
Q
DQCLK1
dataout_p0(0)
dq
DQCLK0
DA1
DB1
ODDRTDQA
TA
SCLK
Q
DQCLK1
DQCLK0
dataout_p1(0)
dataout_n0(0)
dataout_n1(0)
datatri(0)
.
.
.
.
DQSW
DQSBUFD
SCLK
DQSDEL
ECLK
DYNDELPOL
DQCLK0
DQCLK1
ECLKW
RST
CLK
RST
UDDCNTLN
LOCK
DQSDEL
DQSDLLB
uddcntln
lock
reset
ECLK
Generated in the
“Clock
Synchronization
Module”
reset_datapath_out
SCLK2X
DYNDELAY[6:0]12-73
LatticeECP3 High-Speed
I/O Interface
IPexpress is used to generate these signals. Figure 12-64 shows the module generated by IPexpress for DDR
clock outputs (CLKP/CLKN).
Figure 12-64. DDR3 Write Side Clock Generation
DDR3 Write Side Address/Command (ADDR/CMD) Generation
The SCLK output of the Clock Synchronization Module, along with the ODDRXD1 element, is used for address and
command generation. See the section DDR3 Clock Synchronization Module for details on how the SCLK is generated.
IPexpress is used to generate these signals. Figure 12-65 shows the module generated by IPexpress for address
and command signals.
ODDRXD1
SCLK
DA
DB
Q
.
.
.
.
SCLK2X
ddrclk(0)P
ODDRXD1
SCLK
DA
DB
Q
ODDRXD1
SCLK
DA
DB
Q
ddrclk(0)N
ddrclk(1)P
ddrclk(1)N
ddrclk(n)P
ddrclk(n)N
“0”
“1”
“0”
“1”
“1”
“0”12-74
LatticeECP3 High-Speed
I/O Interface
Figure 12-65. DDR3 Write Side Address/Command Generation
DDR3 Clock Synchronization Module
The DDR3 memory interface generated in IPexpress includes a clock synchronization module (CSM) that provides
the clock synchronization and alignment among the required clocks for successful DDR3 functionality. A DDR3
memory interface that is implemented in LatticeECP3 must use the CSM block for correct read data transfer from
the ECLK to SCLK domain. It is also used to provide the proper clock relationship between SCLK and DQCLK0/1
used for write data generation.
The CSM block generates the ECLK, SCLK2X and SCLK clocks to be used in the read and write side implementations. It generates a clocking_good output to indicate that all the clocks for DDR3 operation have been synchronized and the device is ready to serve the DDR3 operation. The DDR3 memory interface and controller should wait
until the clocking_good signal is detected as high.
The DDR3 mode supports the write leveling feature by providing the dynamic delay control ports inputs (DYNDELAY) of DQSBUFD to users. In order for the CSM block to support write leveling, the reset_datapath input port
should be asserted high for at least one PLL input clock cycle (pll_clk) to reset the DQSBUFD blocks through the
reset_datapath_out signal after a write leveling operation is finished. The reset_datapath_out signal is directly connected to the reset (RST) port of all DQSBUFD.
Figure 12-66 shows the block diagram of the CSM block.
ODDRXD1
SCLK
DA
DB
Q
.
.
.
.
SCLK
ADDR, BA
ODDRXD1
SCLK
DA
DB
Q
ODDRXD1
SCLK
DA
DB
Q
RASN, CASN, WEN
CSN, CKE, ODT
addr_p_din, ba_p_din
addr_n_din, ba_n_din
rasn_p_din, casn_p_din, wen_p_din
rasn_n_din, casn_n_din, wen_n_din
csn_p_din, cke_p_din, odt_p_din
csn_n_din, cke_n_din, odt_n_din12-75
LatticeECP3 High-Speed
I/O Interface
Figure 12-66. DDR3 Clock Synchronization Module
PLL Settings for Clock Synchronization Module: LatticeECP3 devices allow two dedicated PLL blocks per side
to support the DDR3 memory interface applications. One of the four available PLLs (two PLLs in the left side and
two PLLs in the right side) must be used to implement the CSM block. Since the PLL input clock is also used to
control the synchronization logic, the use of a PLL input clock that is too fast may cause failures in PAR timing
results. Therefore, it is recommended to use the 1:2:4 clock multiplication ratios for high-speed DDR3 memory
interface applications as shown in the example of a 400MHz/800Mbps DDR3 memory interface below. A dedicated
PLL input clock pad or a PCLK pad can be used to drive the selected PLL.
Table 12-8. PLL Settings for 400 MHz DDR3 Operation
Timing Preferences for Clock Synchronization Module: Since the CSM block includes a few timing-sensitive
nets that affect the performance of DDR3 I/O functions, the route delays on these nets should be tightly controlled.
To consistently guarantee successful routing results, these nets should be constrained by the MAXDDELAY preferences. The nets shown in Table 12-9 include the net delay preferences to force the software Place and Route
(PAR) tool to meet the required net delays.
Table 12-9. MAXDELAY NET Preferences for Clock Synchronization Module
The preferences for the constrained PAR targets are located in the HDL module generated by IPexpress. It is automatically transferred to the project preference file (.prf) to achieve the optimum timing results.
The example shown below includes the target preferences with the following conditions:
PLL Pin Name Clock Output Speed (400MHz) Speed (300MHz)
Input Clock CLKI pll_clk 100 MHz 75 MHz
Output Clocks
CLKOP sclk2x 400 MHz 300 MHz
CLKOS eclk 400 MHz 300 MHz
CLKOK sclk 200 MHz 150 MHz
PLL Divider Setting CLKOK_DIV=2, CLKOP_DIV=2, CLKFB_DIV=4, CLKI_DIV=1
Preference Net Name -8 Device -7 Device -6 Device
MAXDELAY NET eclk 1.2 ns 1.3 ns 1.45 ns
MAXDELAY NET stop 0.8 ns 0.85 ns 0.9 ns
MAXDELAY NET clkos (PLL 1) 1.1 ns 1.2 ns 1.35 ns
MAXDELAY NET clkos (PLL 2) 0.65 ns 0.75 ns 0.8 ns
MAXDELAY NET dqclk1bar_ff 0.65 ns 0.7 ns 0.75 ns
Clock
Synchronization
and Alignment
PLL
CLKOS
CLKOP
CLKOK
pll_clk CLKI
eclk
(400 MHz)
sclk2x
(400 MHz)
sclk
(200 MHz)
reset_datapath
reset_datapath_out
clocking_good12-76
LatticeECP3 High-Speed
I/O Interface
• DDR3 module's instance name is "u_ddr3"
• Speed grade -8 device is targeted
• PLL location 1 is selected
MAXDELAY NET "[path]/eclk" 1.200000 nS;
MAXDELAY NET "[path]/u_ddr3/stop" 0.800000 nS;
MAXDELAY NET "[path]/u_ddr3/clkos" 1.100000 nS;
MAXDELAY NET "[path]/u_ddr3/Inst8_clk_phase/dqclk1bar_ff" 0.650000 nS;
Locate Preferences for Clock Synchronization Module: The CSM block also requires several manual locations
for the clock resources in the module like PLL, ECLKSYNC etc. These modules are all generated by IPexpress and
include an UGROUP attribute added to the modules. The corresponding PGROUP (physical grouping) should be
locked to the specific sites as shown in Table 12-10.
Table 12-10. DDR3 Clock and PGROUP Locations for CSM Support
LatticeECP3-150EA 1156 LatticeECP3-150EA 672
Left 1 Left 2 Right 1 Right 2 Left 1 Left 2 Right 1 Right 2
PLL input clock pad U6 Y9 V34 Y28 M3 U4 T21 V20
PLL R61C5 R79C5 R61C178 R79C178 R61C5 R79C5 R61C178 R79C178
ECLKSYNC L2 L1 R2 R1 L2 L1 R2 R1
PGROUP clk_phase0 R50C5D R78C5D R50C178D R78C178D R50C5D R78C5D R50C178D R78C178D
PGROUP clk_phase1a R60C2D R60C2D R60C181D R60C181D R60C2D R60C2D R60C181D R60C181D
PGROUP clk_phase1b R60C2D R60C2D R60C181D R60C181D R60C2D R60C2D R60C181D R60C181D
PGROUP clk_stop R60C2D R60C2D R60C180D R60C180D R60C2D R60C2D R60C180D R60C180D
LatticeECP3-95/70EA 1156 LatticeECP3-95/70EA 672
Left 1 Left 2 Right 1 Right 2 Left 1 Left 2 Right 1 Right 2
PLL input clock pad U6 Y9 V34 Y28 M3 U4 T21 V20
PLL R43C5 R61C5 R43C142 R61C142 R43C5 R61C5 R43C142 R61C142
ECLKSYNC L2 L1 R2 R1 L2 L1 R2 R1
PGROUP clk_phase0 R32C5D R60C5D R32C142D R60C142D R32C5D R60C5D R32C142D R60C142D
PGROUP clk_phase1a R42C2D R42C2D R42C145D R42C145D R42C2D R42C2D R42C145D R42C145D
PGROUP clk_phase1b R42C2D R42C2D R42C145D R42C145D R42C2D R42C2D R42C145D R42C145D
PGROUP clk_stop R42C2D R42C2D R42C144D R42C144D R42C2D R42C2D R42C144D R42C144D
LatticeECP3-95/70EA 484 LatticeECP3-35EA 672
Left 1 Left 2 Right 1 Right 2 Left 1 Left 2 Right 1 Right 2
PLL input clock pad L5 T3 M18 R17 M3 U4 T21 V20
PLL R43C5 R61C5 R43C142 R61C142 R35C5 R53C5 R35C70 R53C70
ECLKSYNC L2 L1 R2 R1 L2 L1 R2 R1
PGROUP clk_phase0 R32C5D R60C5D R32C142D R60C142D R24C5D R52C5D R24C70D R52C70D
PGROUP clk_phase1a R42C2D R42C2D R42C145D R42C145D R34C2D R34C2D R34C73D R34C73D
PGROUP clk_phase1b R42C2D R42C2D R42C145D R42C145D R34C2D R34C2D R34C73D R34C73D
PGROUP clk_stop R42C2D R42C2D R42C144D R42C144D R34C2D R34C2D R34C72D R34C72D
LatticeECP3-35EA 484 LatticeECP3-35EA 256
Left 1 Left 2 Right 1 Right 2 Left 1 Left 2 Right 1 Right 2
PLL input clock pad L5 T3 M18 R17 K3 P2 K14 T15
PLL R35C5 R53C5 R35C70 R53C70 R35C5 R53C5 R35C70 R53C70
ECLKSYNC L2 L1 R2 R1 L2 L1 R2 R1
PGROUP clk_phase0 R24C5D R52C5D R24C70D R52C70D R24C5D R52C5D R24C70D R52C70D12-77
LatticeECP3 High-Speed
I/O Interface
The PLL input pad, the corresponding PLL site and the legal ECLKSYNC site for the selected PLL are constrained
in the user preference file (.lpf) as shown in the example below:
LOCATE COMP "clk_in” SITE "U6";
LOCATE COMP "[path]/u_ddr3/Inst1_EHXPLLF" SITE "PLL_R61C5";
LOCATE COMP "[path]/u_ddr3/Inst6_ECLKSYNCA" SITE "LECLKSYNC2";
Locating the defined PGROUPs is crucial for successful DDR3 operation. The PGROUPs should be manually
located according to the table as shown below:
LOCATE PGROUP "clk_phase0" SITE "R59C3D";
LOCATE PGROUP "clk_phase1" SITE "R59C2D";
LOCATE PGROUP "clk_stop" SITE "R60C2D";
LOCATE PGROUP "rst_dp_out" SITE "R60C4D";
The following block paths should also be included to help avoid unnecessary domain crossing nets being reported
in the trace report as false alarms.
[False paths for PAR and TRACE]
BLOCK PATH FROM CLKNET "pll_clk" TO CLKNET "sclk" ;
BLOCK PATH FROM CLKNET "pll_clk" TO CLKNET "*/clkos" ;
BLOCK PATH FROM CLKNET "sclk" TO CLKNET "pll_clk" ;
BLOCK PATH FROM CLKNET "*sclk2x" TO CLKNET "pll_clk" ;
BLOCK PATH FROM CLKNET "pll_clk" TO CLKNET "*eclk" ;
BLOCK PATH FROM CLKNET "*/clkos" TO CLKNET "*eclk" ;
BLOCK PATH FROM CLKNET "*/clkos" TO CLKNET "sclk" ;
BLOCK PATH FROM CLKNET "*sclk2x" TO CLKNET "*/clkos" ;
Note: The clock net names and hierarchy path names may be changed after synthesis. If this happens, updates on
the preferences to follow the changed names are required.
DDR Memory Interface Generation Using IPexpress
The IPexpress tool is used to configure and generate the DDR, DDR2 and DDR3 memory interfaces. This section
assumes that ispLEVER 8.0 SP1 is used for generation of the interfaces. If you are using ispLEVER 7.2 SP2, see
Appendix A. Building DDR Interfaces Using IPexpress in ispLEVER 7.2 SP2. If you are using Lattice Diamond
design software, see Appendix B. Building SDR/DDR Interfaces Using IPexpress in Diamond.
To see the detailed block diagram for each interface generated by IPexpress see the Memory Read Implementation
and Memory Write Implementation sections.
PGROUP clk_phase1a R34C2D R34C2D R34C73D R34C73D R34C2D R34C2D R34C73D R34C73D
PGROUP clk_phase1b R34C2D R34C2D R34C73D R34C73D R34C2D R34C2D R34C73D R34C73D
PGROUP clk_stop R34C2D R34C2D R34C72D R34C72D R34C2D R34C2D R34C72D R34C72D
LatticeECP3-17EA 484 LatticeECP3-17EA 256
Left 1 Left 2 Right 1 Right 2 Left 1 Left 2 Right 1 Right 2
PLL input clock pad L5 NA M18 NA K3 NA K14 NA
PLL R26C5 NA R26C52 NA R26C5 NA R26C52 NA
ECLKSYNC L2 NA R2 NA L2 NA R2 NA
PGROUP clk_phase0 R15C5D NA R15C52D NA R15C5D NA R15C52D NA
PGROUP clk_phase1a R25C2D NA R25C55D NA R25C2D NA R25C55D NA
PGROUP clk_phase1b R25C2D NA R25C55D NA R25C2D NA R25C55D NA
PGROUP clk_stop R25C2D NA R25C54D NA R25C2D NA R25C54D NA
Table 12-10. DDR3 Clock and PGROUP Locations for CSM Support (Continued)12-78
LatticeECP3 High-Speed
I/O Interface
IPexpress can be opened from the Tools menu in Project Navigator. All the DDR modules are located under Architecture Modules > IO. DDR_MEM is used to generate DDR memory interfaces.
Figure 12-67. IPexpress Main Window
Figure 12-67 shows the IPexpress Main Window. To generate a DDR memory interface, select DDR_MEM, assign
a module name and click on Customize to see the Configuration Tab.
Figure 12-68 shows the Configuration Tab for the DDR_MEM interface. You can choose to implement the
DDR1_MEM, DDR2_MEM or DDR3_MEM interface.12-79
LatticeECP3 High-Speed
I/O Interface
Figure 12-68. Configuration Tab for DDR_MEM
Table 12-11 describes the various settings shown in the Configuration Tab above.
Table 12-11. Configuration Tab Settings for DDR_MEM
GUI Option Description Range Default Value
Interface DDR memory interface type DDR, DDR2, DDR3 DDR2
I/O Buffer Configuration I/O type configuration for DDR pins
SSTL25_I, SSTL25_II
SSTL18_I, SSTL18_II,
SSTL15
DDR – SSTL25_I
DDR2 – SSTL18_I
DDR3 – SSTL15
Number of DQS Interface width (1 DQS per 8 bits of data) 1 to 9 4
DQS Group1 to DQS Group8 Number of DQ per DQS pin 1 to 8 8
DQS Buffer Configuration DQS buffer type
DDR: Single-ended
DDR2: Single-ended,
Differential
DDR3: Differential
DDR – Single-ended
DDR2 – Single-ended
DDR3 – Differential
Clock/Address/Command Clock/address/command interface will be
generated when this option is checked ENABLED, DISABLED DISABLED
Data Mask Data mask signal will be generated when
this option is checked ENABLED, DISABLED DISABLED
Lock/Jitter Sensitivity Lock Sensitivity attribute for DQSDLL1
HIGH, LOW HIGH12-80
LatticeECP3 High-Speed
I/O Interface
If the user selects to generate the Clock/Address/Command signals using IPexpress, then the settings in the
Clock/Address/Command Tab are active and can be set up as required. Figure 12-69 shows the
Clock/Address/Command Tab in the IPexpress for DDR2 Memory.
Figure 12-69. Clock/Address/Command Tab in the IPexpress for DDR_MEM
Table 12-12 lists the values that can be used for the Clock/Address/Command settings.
DDR Memory Frequency DDR Memory Interface Frequency
DDR – 87.5 MHz,
100 MHz, 133.33 MHz,
166.67 MHz, 200 MHz
DDR2 – 125 MHz,
200 MHz, 266.67 MHz
DDR3 – 300 MHz,
400 MHz
DDR – 200 MHz
DDR2 – 200 MHz
DDR3 – 400 MHz
ISI Calibration
ISI calibration is available for the DDR3
interface to adjust for inter-symbol inference adjustment per DQS group
BYPASS, DEL1, DEL2,
DEL3, DEL4, DEL5,
DEL6, DEL7
BYPASS
1. It is recommended to set Lock Sensitivity to HIGH for DDR Memory Frequency higher than 133 MHz.
Table 12-11. Configuration Tab Settings for DDR_MEM (Continued)
GUI Option Description Range Default Value12-81
LatticeECP3 High-Speed
I/O Interface
Table 12-12. Clock/Address/Command Settings for DDR_MEM
DDR Memory DQ/DQS Design Rules and Guidelines
Listed below are some rules and guidelines to keep in mind when implementing DDR memory interfaces in
LatticeECP3 devices.
• LatticeECP3 devices have dedicated DQ-DQS banks. Please refer to the Logical Signal Connections tables in
the LatticeECP3 Family Data Sheet before locking these pins.
• There are two DQSDLLs on the device, one for the left half and one for the right half of the device. Only one
DQSDLL primitive should be instantiated for each half of the device. Since there is only one DQSDLL on each
half, all the DDR memory interfaces on that half should run at the same frequency.
• Each DQSDLL will generate 90° digital delay bits for all the DQS delay blocks on that half of the device based on
the reference clock input to the DLL.
• The clock to the PLL used in the write implementation to generate the clocks for the outputs must be locked to
the correct dedicated PLL pin input.
• When implementing a DDR SDRAM interface, all interface signals should be connected to the SSTL25 I/O standard.
• For the DDR2 SDRAM interface, the interface signal should be connected to the SSTL18 I/O standard.
• For the DDR3 SDRAM interface, these signals should be connected to the SSTL15 standard.
• The DDR, DDR2 and DDR3 require a differential clock signal. For these standards, the differential clock signals
should be connected to SSTL25D (DDR), SSTL18D (DDR2) or SSTL15D (DDR3).
• DDR3 also requires differential DQS signal. The use of differential DQS is optional for DDR2. If differential DQS
is used it should be connected to SSTL18D for DDR2 and SSTL15D for DDR3.
• When implementing the DDR interface, the VREF1 of the bank is used to provide the reference voltage for the
interface pins. VREF1 should not be connected with VREF2 of the bank when implementing DDR memory interfaces.
• There is no DQS strobe support on the bottom of the device, so memory interfaces cannot be implemented on
this side.
• Within a DQS-12 group, the IOLOGIC in the group’s DQS/DQS# pads cannot be used for DDR registers.
• If the register is implemented inside the FPGA fabric instead of the IOLOGIC, there is no restriction on using the
DQS pad.
GUI Option Range Default Value
Number of Clocks 1, 2, 4 1
Number of Clock Enables 1, 2, 4 1
Address Width
DDR: 12-14
DDR2: 13-16
DDR3: 13-16
DDR: 13
DDR2: 13
DDR3: 14
Bank Address Width
DDR: 2
DDR2: 2, 3
DDR3: 3
DDR: 2
DDR2: 2
DDR3: 3
Number of ODT
DDR: N/A
DDR2: 1, 2, 4
DDR3: 1, 2, 4
DDR: N/A
DDR2: 1
DDR3: 1
Number of Chip Selects
DDR: 1, 2, 4, 8
DDR2: 1, 2, 4
DDR3: 1, 2, 4
DDR: 1
DDR2: 1
DDR3: 112-82
LatticeECP3 High-Speed
I/O Interface
• The upper left corner of the LatticeECP3 device has a non-DQS DDR group. This group of I/Os does not have a
DQS function. This group of I/Os can only be used for generic DDR implementations.
• IDDRX memory cannot be mixed in the same DQS group as an ODDRX generic implementation. Similarly,
ODDRX memory cannot be mixed in the same DQS group with an IDDRX generic implementation.
• Generic DDR interfaces are not available on the top side of the LatticeECP3 “E” device only. The generic DDR
required for DDR clock and control generation needs to be implemented on the left and right sides of the device.
Generic DDR interfaces can be implemented on the top side of the “EA” devices, therefore this issue does not
exist for “EA” devices.
• Table 12-13 summarizes what is available on each side of the LatticeECP3-70E, LatticeECP3-95E and
LatticeECP3-150EA devices. Note that DDR registers are not available on the bottom of the device.
Table 12-13. DDR Pin Limitations
DDR/DDR2 Pinout Guidelines
• The DQS-DQ association rule must be followed.
– All associated DQs (8 or 4) to a DQS must be in the same DQS-12 group.
• The data mask (DM) must be part of the corresponding DQS-12 group.
– Example: DM[0] must be in the DQS-12 group that has DQ[7:0], DQS[0].
• DQS pad must be allocated to a dedicated DQS pad.
– DQS# pad is used when differential DQS is selected.
• Do not assign any signal to the DQS# pad if SSTL18D is applied to the DQS pad.
– The software automatically places DQS# when SSTL18D is applied.
• DQS/DQS# pads cannot be used for other DDR functions.
– The DQS IOLOGIC structure is not compatible with non-DQS DDR IOLOGIC.
• The clock to the PLL used to generate the outputs must be assigned to use dedicated clock routing.
• Data group signals (DQ, DQS, DM) can use either the left, right or top edge of LatticeECP3.
• Locating memory clock signals:
– For the LatticeECP3 “E” device, it is highly recommended to have all clock pads within a memory controller
be in one DQS-12 group to minimize pinout restrictions.
• The bottom-side pads in Bank 6 and Bank 3 are also good candidates for address/command/control signals.
Save pins on the left and right sides for DDR.
• VREF1 of the bank where DQs are located must not be taken by any signal.
Left Right Top
DQS12 group available DQS12 available DQS 12 with some restrictions
Input x1 DDR Generic
Output x1DDR Generic
Input x2 DDR Generic
Output x2 DDR Generic
DDR Memory
DDR2 Memory
DDR3 Memory (“EA” only)
Input x1 DDR Generic
Output x1DDR Generic
Input x2 DDR Generic
Output x2 DDR Generic
DDR Memory
DDR2 Memory
DDR3 Memory (“EA” only)
Input x1 DDR Generic (“EA” only)
Output x1DDR Generic (“EA” only)
Input x2 DDR Generic (“EA” only)
DDR Memory (“E” and “EA”)
DDR2 Memory (“E” and “EA”)
Upper left side has DDR function without
DQS.
Upper right side I/Os shared with sysCONFIG pins in bank 8. No DDR functions are available on these pins
Right part of top side has eight I/Os
shared with the sysCONFIG pins. No
DDR functions are available.
Note: See the LatticeECP3 Family Data Sheet Pinout tables to find DQS group assignments.12-83
LatticeECP3 High-Speed
I/O Interface
– VREF2 is OK to use.
– Do not connect VREF1 and VREF2 together.
• External termination to VTT is required for DDR and DDR2 interfaces. All DQ and DQS pins must be terminated
to VTT using an external termination resistor. VTT = ½ VCCIO (0.9V for DDR2 and 1.25V for DDR). It is recommended that SI Simulation be run to determine the best termination value. If signal integrity simulation is not
available, parallel termination of 75ohms to VTT should be used.
• It is required to provide a PCB connect resistor to the XRES pins. These pins cannot be used for other functions.
See TN1189, LatticeECP3 Hardware Checklist, for detailed requirements on the XRES pin.
DDR3 Termination Guidelines
Proper termination of a DDR3 interface is an important part of implementation that ensures reliable data transactions at high speed. Below is the general termination guideline for the LatticeECP3 DDR3 interface.
Termination for DQ, DQS and DM
• Do not locate any termination on the memory side. The memory side termination on DQ, DQS and DM is dynamically controlled by the DDR3 SDRAM's ODT function.
• External termination to VTT is required for DDR3 interfaces at the FPGA side. Each DQ and DQS pin should be
terminated to VTT using an external termination resistor. The termination resistor location is important. See the
Layout Considerations for DDR3 section for the requirements.
• It is recommended that signal integrity (SI) simulation be run to determine the best termination value. If SI simulation is not available, parallel termination of 100 ohms to 120 ohms to VTT is recommended.
• Use of series termination resistors at the FPGA side is not recommended.
Termination for CK
DDR3 memory clocks require differential termination because they use a differential signaling, SSTL15D, in DDR3
SDRAM applications. You can locate an effective 100-ohm termination resistance on the memory side to achieve
the differential termination using the following guideline:
• Locate a 100-ohm resistor between the positive and negative clock signal, or
• Connect one end of an Rtt resistor to the positive pin and one end of another Rtt to the negative pin of a CK pair,
then connect the other ends of two Rtt resistors together and return to VDD through a Ctt capacitance. This is a
JEDEC CK termination scheme defined in the DIMM specifications. JEDEC uses 36-ohm for Rtt with 0.1uF Ctt
for DIMM. 50-ohm Rtt can also be used for non-DIMM applications.
• Use of series termination resistors at the FPGA side is not recommended.
• When fly-by wiring is used, the CK termination resistor should be located after the last DDR3 SDRAM device.
Termination for Address, Commands and Controls
Parallel termination to VTT on address, command and control lines is typically required.
• Locate a 50-ohm parallel-to-VTT resistor (or a best known resistance obtained from your SI simulation) to each
address, command and control line on the memory side.
• When fly-by wiring is used, the address, command and control termination resistors should be located after the
last DDR3 SDRAM device.
• Series termination resistors can be optionally used on the address, command and control signals to suppress
overshoot/undershoot and to help decrease overall SSO noise level. 22-ohm or 15-ohm series termination is recommended when used. 12-84
LatticeECP3 High-Speed
I/O Interface
Termination for DDR3 DIMM
The DDR3 SDRAM DIMMs incorporate internal termination following the requirements defined by the JEDEC
DIMM specification. For this reason, the user termination requirement for the DDR3 DIMM is slightly different from
that of DDR3 SDRAM devices.
• Do not locate any termination on the memory side. The memory side termination on DQ, DQS and DM is dynamically controlled by the DDR3 SDRAM’s ODT function.
• Do not locate differential termination on CK at the memory side.
• Do not locate parallel termination to VTT on address, command and control signals at the memory side.
• Follow the termination for DQ, DQS and DM guideline above for the FPGA side termination.
DDR3 Interface without Termination
When a wide DDR3 data bus is implemented and requires most of the pin resources in the assigned banks to be
used as data lines, SSO impact usually becomes a designer’s concern. While proper use of termination resistors
provides optimized signal integrity results, removing them may also provide improved noise margin in some cases
due to increased eye height.
DQ, DQS and DM without Parallel VTT Termination
Although the external parallel VTT termination is typically required for read operations at the FPGA side, it can be
removed if the following conditions are met:
a. Point-to-point connection between FPGA and DDR3 SDRAM device
b. PCB trace length is maintained shorter than 3.0"
c. SI simulation confirms that there is no significant reflection or ringing noise due to unmatched line impedance
Either or both of the following considerations are suggested when you implement a DDR3 interface without external
VTT termination:
• You can still keep the external VTT termination in your PCB layout without population if the board space allows. It
will give you an opportunity to return to the external termination scheme without board re-spin work.
• You can connect the VTT input pads in the banks where the DDR3 interface’s data bus is implemented to the
external VTT source. This will allow you to use the LatticeECP3's internal on-chip termination on selective signals in case only a few have bad signal integrity results. This approach also allows you to use internal VTT termination only on DQS signals, which can be a useful termination option in some cases.
Address, Command and Control Signals without Parallel VTT Termination
As described, parallel termination to VTT on address, command and control lines is typically required. However,
the parallel VTT termination on them can also be optionally removed to increase the noise margin or to avoid layout
difficulties at the memory side. When they are removed, use of series termination resistors at the driver side
(FPGA) is recommended to suppress overshoot and undershoot noise. The same condition as specified above for
DQ, DQS and DM is applied to remove the parallel termination.
Layout Considerations for DDR3
• Placement of external discrete resistors or resistor packs (RPACKS) for parallel VTT termination is critical and
must be placed within 0.6 inches (600-mil) of the FPGA ball.
– 120 ohm BGA RPACKS (CTS RT2432B7 type) are recommended for the 64- and 32-bit interfaces due to
better routing and density issues. Each RPACK contains 18 resistors in a very small BGA footprint. Note that
only 120, 75 and 50 ohm values are available in this package type.
– 4x1 RPACKS (CTS 741X083101JP type) can also be used in cases where a 100 ohm value is needed with-12-85
LatticeECP3 High-Speed
I/O Interface
out routing/density issues.
• The termination resistor stubs should be kept minimal.
• All traces should be matched to 50 ohms.
• For SODIMM and UDIMM designs, write leveling should be used and all traces from the FPGA to the DIMM
should be matched in length on the PC board similar to DDR2.
• If using a discrete DDR3 device, fly-by routing can be used for traces. If fly-by routing is used, the Write Leveling
option must be enabled. If not using fly-by routing, the Write Leveling option must be disabled.
• Refer to TN1189, LatticeECP3 Hardware Checklist, DDR3 Interface Requirements section for complete DDR3
layout guidelines.
DDR3 Pinout Guidelines
The LatticeECP3 device contains dedicated I/O functions for supporting DDR3 memory interfaces. The following
pinout rules must be followed to properly use the dedicated I/O functions.
• The DQS-DQ association rule must be followed.
– All associated DQs (8 or 4) to a DQS must be in the same DQS-12 group.
• A data mask (DM) must be part of the corresponding DQS-12 group.
– Example: DM[0] must be in the DQS-12 group that has DQ[7:0], DQS[0].
• A DQS pad must be allocated to a dedicated DQS True (+) pad.
– A DQS# pad is auto-placed when a differential SSTL type (SSTL15D) is selected.
• Do not assign any signal to a DQS# pad if SSTL15D is applied to the DQS pad.
– The software automatically places DQS# when SSTL15D is applied.
• DQS/DQS# pads cannot be used for other DDR functions.
– The DQS IOLOGIC structure is not compatible with non-DQS DDR IOLOGIC.
– Do not use DQS pads for any DDR3 signals except DQS and RST#. They can be used for other user logic
signals if a DDR function is not required.
• Data group signals (DQ, DQS, DM) must use the left and right sides of the LatticeECP3 device.
– Top-side pads do not have 2x gearing.
• Address, command, control and CK signals must be located on generic DDR-capable pads (ODDRXD).
– Place the CK/CK# outputs on the same side where the DQ and DQS pads are located. The top side is not
recommended for the high-speed DDR CK function.
– Place the address, command and control signals either on the same side as where the DQ and DQS pads
are located or on the top side. The bottom side cannot be used.
• RST# can be located anywhere an output is available as long as LVCMOS15 is applicable.
– All DDR3 signals except RST# use DDR functions.
• The DDR3 input reference clock to the PLL must be assigned to use dedicated clock routing.
– The dedicated PLL input pads are recommended while PCLK inputs can also be used.
– Two PLLs that have a direct connection to ECLK in each side can be used for a DDR3 function. (Note that
LatticeECP3-17EA devices have one PLL that supports DDR3 in each side.)
• Do not use the bottom-side pads in Bank 6 and Bank 3 for address, command and control signals.
– No generic DDR support on the bottom side of the device.
• VREF1 of the bank where the DQ, DQS and DM pads are located must not be taken by any signal.
– Do not PROHIBIT VREF1 in the preference file.
– VREF2 can be used for a general purpose I/O signal.
– Do not connect VREF1 and VREF2 together.
• Leave VTT pins unconnected when external VTT termination is implemented.12-86
LatticeECP3 High-Speed
I/O Interface
– VTT pins can be optionally connected to the external VTT source when a DDR3 interface is implemented
without external VTT termination. See the DDR3 Interface without Termination section for details.
– VTT pins can be connected in series with a capacitor (around .01uf) to ground when the bank has LVDS
internal termination to suppress externally generated common mode noise. Internal VTT termination cannot
be used in this case.
• It is required to provide a PCB connect resistor to the XRES pins. These pins cannot be used for other functions.
See TN1189, LatticeECP3 Hardware Checklist, for detailed requirements on the XRES pin.
Pin Placement Considerations for Improved Noise Immunity
In addition to the general pinout guidelines, there are additional pinout considerations for minimizing simultaneous
switching noise (SSN) impact. The following considerations are necessary to control SSN within the required level:
1. Properly terminated interface
2. SSN optimized PCB layout
3. SSN considered I/O pad assignment
4. Use of pseudo power pads
The guidelines listed below address the I/O pad assignment and pseudo power pad usage. Unlike the pinout guidelines, they are not absolute requirements. However, it is recommended that the pin placement follow the guidelines
as much as possible to increase the SSO/SSI noise immunity.
• Place the DQS groups for data implementation starting from the middle of the (right or left) edge of the
LatticeECP3. Allow a corner DQS group to be used as a data group only when necessary to implement the
required width.
• Locate a spacer DQS group between the data DQS groups if possible. A DQS group becomes a spacer DQS
group if the I/O pads inside the group are not used as data pads (DQ, DQS or DM).
– The pads in a spacer group can be used for address, command, control or CK pads as well as for user logic
or the pseudo power pads.
– No more than two consecutive-data DQS group placements is recommended in the middle of the edge.
When a corner-side DQS group is used for data, locate a spacer DQS group right next to it.
– If there is an incomplete DQS group (not the size of DQS-12) or enough space for more than 10 pads
between two DQS groups, the following DQS group can be located next to the previous complete DQS
group, both as data groups. The incomplete DQS groups, or the space between them, can be used as a
spacer.
• It is recommended that you locate a few pseudo VCCIO/ground (GND) pads inside a spacer DQS group. An I/O
pad becomes a pseudo power pad when it is configured to OUTPUT with its maximum driving strength (i.e.,
SSTL15, 10mA for DDR3) and connected to the external VCCIO or ground power source on the PCB.
– Your design needs to drive the pseudo power I/O pads according to the external connection. (i.e., you assign
them as OUTPUT and let your design drive ‘1’ for pseudo VCCIO pads and ‘0’ for pseudo GND pads in your
RTL coding.)
– Locating four pseudo power pads in a spacer DQS group should be sufficient to efficiently suppress the SSN
impact. At least two pseudo pads should be implemented in a spacer DQS group if more pins are needed for
a user design.
– Good candidate pads are two pads in both ends (the first and the last ones in the group) and/or two DQS
(positive and negative) pads in the middle.
• You may have one (DDR2/DDR3) or two (DDR/DDR2) remaining pads in a data DQS group which are not
assigned as a data pad in a DDR memory interface. Assign them to pseudo VCCIO or pseudo GND. The preferred location is in the middle of the group (right next to a DQS pad pair). Note that you may not have this extra
pad in DDR2/DDR3 if the DQS group includes a VREF pad for the bank.
• Avoid fast switching signals located close to the XRES pad of a LatticeECP3 device. XRES requires an external
resistor which is used to create the bias currents for the I/O. Since this resistor is used for a calibration reference 12-87
LatticeECP3 High-Speed
I/O Interface
for sensitive on-chip circuitry, careful pin assignment around the XRES pad is also necessary to produce less jittery PLL outputs for DDR memory interface operations.
The guidelines below are not as effective as the ones listed above. However, following them is still recommended to
improve the SSN immunity further:
• Assign the DM (data mask) pad in a data DQS group close to the other side of DQS pads where a pseudo power
pad is located. If the data DQS group includes VREF, locate DM to the other side of VREF with respect to DQS.
It can be used as an isolator due to its almost static nature in most applications.
• Other DQS groups (neither data nor spacer group) can be used for accommodating DDR3 address, command,
control and clock pads. It is recommended that you still assign all or most DQS pads (both positive and negative)
in these groups to pseudo power. Since LatticeECP3 DQS pads have a dedicated DDR function that cannot be
shared with other DDR3 signals, they are good pseudo power pad candidates.
• You can assign more unused I/O pads to pseudo power if you want to increase the SSN immunity. Note that the
SSN immunity does not get increased at the same rate as the increased number of pseudo power pads. The first
few pseudo power pad placements described above are more crucial. Keep the total pseudo power pad ratio
(VCCIO vs. GND) between 2:1 to 3:1.
• Although not necessary, it is slightly more effective to locate a pseudo VCCIO to a positive pad (A) and GND to a
negative pad (B) of a PIO pair if possible.
• If a bank includes unused input-only pads such as dedicated PLL input pads, you can also connect them to
VCCIO on your PCB. They are not as efficient as the pseudo power pads but can still be used as isolators, and
the connections on the board would provide good shielding. No extra consideration is necessary for these pins in
your design.
• It is a good idea to shield the VREF1 pad by locating pseudo power pads around it if the VREF1 pad is not
located in a data DQS group.
Table 12-14 shows the recommended examples of DQS group allocations following the guidelines. If you have
enough pin resources, following the best examples would provide you with maximized SSN immunity results. It is
more practical in most applications to follow the examples in the “Allowed” columns. It is expected that the SSN and
ground bounce impacts are considerably less than those cases where you do not include any consideration.
Table 12-14. Recommended Examples of DQS Group Allocation
LatticeECP3-150EA
DQS 150-1156 Left 150-1156 Right 150-672 Left 150-672 Right
Best Allowed Best Allowed Best Allowed Best Allowed
1 D D D D*
2 D D D* D D D
3D D
4D DDDDDD
5 D D D* D*
6DDD DD
7 D D* D*
8DDDD
9 D
10 D D D
11 D
12 D D
13
Bus Size 48 64 40 56 32 40 24 32
LatticeECP3-95/70EA
DQS 95/70-1156 Left 95/70-1156 Right 95/70-672 Left 95/70-672 Right 95/70-484 Left 95/70-484 Right
Best Allowed Best Allowed Best Allowed Best Allowed Best Allowed Best Allowed
1 D D D D* D
2D D D DDDDD12-88
LatticeECP3 High-Speed
I/O Interface
DDR Software Primitives and Attributes
This section describes the software primitives that can be used to implement all the DDR interfaces. These primitives are divided into ones that are used to implement the DDR data and ones for DDR Strobe signal or the Source
Synchronous clock. The DQSBUF primitives are used to generate the signals required to correctly capture the data
from the DDR memory.
3DDD DD
4DDDDDDDDD DD
5 D* D* D
6 D D D D D D D*
7 D D* D* D* D*
8 D D*
9
DDR3
Bus 32 48 32 40 32 40 24 32 16 32 16 24
LatticeECP3-35EA
DQS 35-672 Left 35-672 Right 35-484 Left 35-484 Right 35-256 Left 35-256 Right
Best Allowed Best Allowed Best Allowed Best Allowed Best Allowed Best Allowed
1 D D D D* D* D* D*
2 D D D D D D*
3 DDDD
4 DDDDD DD
5 D
6 D D D D*
7
DDR3
Bus 24 32 16 32 16 32 16 24 8 16 8 8
LatticeECP3-17EA
DQS 17-484 Left 17-484 Right 17-256 Left 17-256 Right
Best Allowed Best Allowed Best Allowed Best Allowed
1 D D* D* D*
2 D D D D* D*
3 D D
4 D D
5
DDR3
Bus 16 24 8 16 8 16 8 8
Notes: DQS groups with a ‘D’ indicate the data DQS groups while the blank ones indicate the spacer DQS groups.
Data DQS groups with an asterisk indicate that they have an incomplete DQS group or enough isolation in front.
Shaded cells are not-applicable to the selected device.
Table 12-15. DDR Software Primitives List
Type Primitive Usage
Data Input
IDDRXD E and EA Generic DDRX1
E and EA DDR/DDR2 Memory
IDDRX1D EA Generic DDRX1
IDDRX2D E Data Input Generic DDRX2
E and EA DDR3 Memory
IDDRX2D1 EA Generic DDRX2
Data Output
ODDRXD E and EA Generic DDRX1
E and EA DDR/DDR2/DDR3 Memory
ODDRXD1 EA Generic DDRX1
ODDRX2D E and EA Generic DDRX2
E and EA DDR3 Memory
Table 12-14. Recommended Examples of DQS Group Allocation (Continued)12-89
LatticeECP3 High-Speed
I/O Interface
DQSDLLB
The DQSDLLB will generate the 90° phase shift required for the DQS signal. This primitive will implement the onchip DQSDLL. Only one DQSDLL should be instantiated for all the DDR implementations on one-half of the device.
The clock input to this DLL should be at the same frequency as the DDR interface. The DLL will generate the delay
based on this clock frequency and the update control input to this block. The DLL will update the dynamic delay
control to the DQS delay block when this update control (UDDCNTLN) input is asserted. Figure 12-70 shows the
primitive symbol. The active low signal on UDDCNTLN updates the DQS phase alignment.
Figure 12-70. DQSDLL Symbol
Table 12-16 provides a description of the ports.
Table 12-16. DQSDLLB Ports
Data Tristate
ODDRTDQA E and EA Generic DDRX2
E and EA DDR3 Memory
OFD1S3AX E and EA Generic DDRX1
E and EA DDR/DDR2 Memory
DQS Output
ODDRXDQSA E and EA DDR/DDR2 Memory
ODDRX2DQSA E and EA DDR3 Memory
DQS Tristate ODDRTDQSA E and EA DDR/DDR2 Memory
E and EA DDR3 Memory
DQSBUF Logic
DQSBUFD E and EA DDR3 Memory, E and EA Generic DDRX2 (for bus widths <10
bits)
DQSBUFF E and EA DDR/DDR2 Memory, E and EA Generic DDRX1 (for bus widths
<10 bits)
DQSBUFE E Generic DDRX2
DQSBUFE1 EA Generic DDRX2
DQSBUFG E Generic DDRX1
DQSDLL DQSDLL DLL for Generic DDRX1/DDRX2 (for bus width <10 bits and multiple interfaces per side of the device) and DDR/DDR2/DD3 Memory
Input Delay
DELAYB Delay block for Generic DDRX2 with Dynamic Control
DELAYC Delay block for Generic DDRX1/X2 with clock injection removal. The
amount of Fixed Delay will vary by interface.
ECLK Stop ECLKSYNCA EA Generic DDRX2 Output
EA ECLK Synchronization for DDR3 Memory
Port Name I/O Definition
CLK I CLK should be at the frequency of the DDR interface.
RST I Resets the DQSDLLB.
UDDCNTLN I Provides update signal to the DLL that will update the dynamic delay.
LOCK O Indicates when the DLL is in phase.
DQSDEL O The digital delay generated by the DLL, should be connected to the DQSBUF primitive.
Table 12-15. DDR Software Primitives List (Continued)
Type Primitive Usage
CLK
RST
UDDCNTLN
LOCK
DQSDEL
DQSDLLB12-90
LatticeECP3 High-Speed
I/O Interface
DQSDLL Update Control
The DQS delay can be updated for PVT variation using the UDDCNTLN input. The DQSDEL is updated when the
UDDCNTLN is held low. The DDR memory controller or user logic can update DQSDEL when variations are
expected. It can be updated anytime except during a memory READ or WRITE operation.
It is important to understand that the UDDCNTLN signal is a synchronous input to the DQSDLL CLK domain.
When using DDR in 2x gearing, it is required to use clock domain transfer logic first to transfer UDDCNTLN from
slow clock domain to fast clock domain before it is input to DQSDLL. You can use two- or three-stage pipeline registers to safely transfer the DQSDEL update control input to the DQSDLL block. The first stage register uses the
local domain clock while the second and third registers use the DQSDLL CLK domain clock. The second to third
stage pipelining is desirable because it can eliminate the placement and routing issue due to the increased clock
rate (2x) for the net and also avoids any meta-stability issues.
DQSDLL Configuration
By default this DLL will generate a 90° phase shift for the DQS strobe based on the frequency of the input reference
clock to the DLL.
DQSBUF Logic Primitives for Generic DDR
The DQSBUF primitives (DQSBUFE and DQSBUFG for “E” devices) are used to generate the strobe logic and
delay used in the input DDR modules to correctly demux the DDR data. The DQSBUFE is used for x2 interfaces
and the DQSBUFG is used for x1 interfaces. The DQSBUFE1 is used only for output x2 interfaces in LatticeECP3
devices.
Figure 12-71 shows DQSBUF Generic DDR functions for the “E” and “EA” devices.
Figure 12-71. DQSBUFE Function for Generic Input/Output DDR x2 Interfaces (“E” Devices)
DQS TRANSITION
DETECT LOGIC
DDR WRITE CLOCK
ECLK
SCLK
ECLKW
RST
DYNDELPOL
DYNDELAY[6:0]
DQCLK0
DQCLK1
DDRCLKPOL
DDRLAT12-91
LatticeECP3 High-Speed
I/O Interface
Figure 12-72. DQSBUFG Function for Generic Input/Output DDR x 1 Interface (“E” Devices)
Figure 12-73. DQSBUFE1 Function for Generic Output DDR x2 Interfaces (“EA” Devices)
DQS Transition Detect
The DQS Transition Detect block inputs the fast ECLK and the slower SCLK (=1/2 ECLK) inputs and generates the
DDRCLKPOL and the DDRLAT signals. These signals are generated based on the phase of the FPGA SCLK at
the first ECLK transition. The DDRLAT signal is used in generic DDRX2 mode to transfer data from the ECLK to
SCLK domain. These are only required to implement generic DDR on the LatticeECP3 “E” devices. LatticeECP3
“EA” devices do not require these signals.
DDR Write Clock
This block inputs the fast edge clock used for the write side and generates two control signals, DQCLK0 and
DQCLK1. For Generic DDRX2 gearing, both DQCLK0 and DQCLK1 are generated. These control clocks run at a
rate of one-half the fast edge clock, and DQCLK1 is offset delayed by 90° relative to DQCLK0. DQCLK1 output
matches the phase of the SCLK input to the block. These two clocks toggle between different legs of a 4:1 mux in
the output logic, which allows 4:1 gearing of data at twice the edge clock rate. When using generic DDRX1, instead
of DDRX2 gearing, only the DQCLK1 is output, which toggles at the rate of FPGA clock provided by SCLK and
matches the phase of the SCLK input.
The DDR write clock block also inputs DYNDELPOL and DYNDELAY [6:0] delay inputs. These inputs support the
DDR3 memory interface to adjust delay among the various DQS groups. They can also be used for the generic
DDR for the same purpose. The DYNDELAY [6:0] can input 128 possible delay step settings with each step generating approximately 25ps nominal delay. In addition, the DYNDELPOL can be used to invert the clock for a 180°
DQS TRANSITION
DETECT LOGIC
DDR WRITE CLOCK
SCLK
DQCLK1
DDRCLKPOL
DDR WRITE CLOCK
ECLKW
RST
DYNDELPOL
DYNDELAY[6:0]
DQCLK0
DQCLK112-92
LatticeECP3 High-Speed
I/O Interface
shift of the incoming clock. Each of the source synchronous clock outputs can be adjusted to account for the data
skew using this delay. The DYNDELAY [6:0] and DYNDELPOL inputs should be generated using the FPGA core.
DQSBUFE
This primitive provides the control logic for Generic DDRX2 interface in the LatticeECP3 “E” devices. Figure 12-74
shows the primitive symbol.
Figure 12-74. DQSBUFE Symbol
Table 12-17 provides a description of all the I/O ports associated with the DQSBUFE primitive.
Table 12-17. DQSBUFE Primitive Ports
DQSBUFG
This primitive implements the strobe logic for Generic DDRX1 interface for LatticeECP3 “E” devices. Figure 12-75
shows the primitive symbol.
Figure 12-75. DQSBUFG Symbol
Table 12-18 provides a description of all the I/O ports associated with the DQSBUFG primitive.
Port Name I/O Definition
ECLK I Edge CLK
SCLK I System CLK
ECLKW I Edge CLK used the DDR write side
RST I Reset input
DYNDELPOL I Input from user logic used to invert the clock polarity
DYNDELAY [6:0] I Input from user logic used to delay the ECLK
DQCLK0 O Clock output at frequency of SCLK used for output side gearing
DQCLK1 O Clock output at frequency of SCLK and matches the phase of SCLK using for
output side gearing. DQCLK1 is 90° shifted from DQCLK0.
DDRCLKPOL O DDR clock polarity signal
DDRLAT O DDR latch control signal
ECLK DQCLK0
DQSBUFE
SCLK
DYNDELPOL
DQCLK1
ECLKW DDRCLKPOL
DDRLAT
DYNDELAY[6:0]
RST
DQSBUFG
SCLK
DQCLK1
DDRCLKPOL12-93
LatticeECP3 High-Speed
I/O Interface
Table 12-18. DQSBUFG primitive Ports
DQSBUFE1
This primitive implements the strobe logic for Generic DDRX2 Output interfaces on the LatticeECP3 “EA” devices.
Figure 12-76 shows the primitive symbol.
Figure 12-76. DQSBUFE1 Symbol
Table 12-19 provides a description of all the I/O ports associated with the DQSBUFE1 primitive.
Table 12-19. DQSBUFE1 Primitive Ports
DQSBUF Logic Primitives for DDR Memory Interfaces
The DQSBUF primitives (DQSBUFD and DQSBUFF) are used to generate the DQS strobe logic and delay used in
the input DDR modules to correctly demux the DDR data. The DQSBUF module used for the DDR memory interface is composed of DQS Delay, DQS Transition Detect, Data Valid Generation and the DDR Write Clock block, as
shown in Figure 12-77.
Port Name I/O Definition
SCLK I System CLK
DQCLK1 O Clock output at frequency of SCLK, matches the phase of SCLK
used for output gearing
DDRCLKPOL O DDR clock polarity signal
Port Name I/O Definition
ECLKW I Edge CLK used the DDR write side
RST I Reset input
DYNDELPOL I Input from user logic used to invert the clock polarity
DYNDELAY [6:0] I Input from user logic used to delay the ECLK
DQCLK0 O Clock output at frequency of SCLK used for output side gearing
DQCLK1 O Clock output at frequency of SCLK, matches the phase of SCLK using for output side gearing. DQCLK1 is 90° shifted from DQCLK0.
DQSBUFE1
DYNDELPOL
DYNDELAY[6:0]
ECLKW
RST
DQCLK0
DQCLK112-94
LatticeECP3 High-Speed
I/O Interface
Figure 12-77. DQSBUF Block for DDR Memory Interfaces
DQS Delay Block
The DQS Delay block receives the digital control delay line (DQSDEL) coming from one of the two DQSDLL blocks.
These control signals are used to delay the DQSI by 90°. ECLKDQSR is the delayed DQS and is connected to the
clock input of the first set of input DDR registers.
DQS Transition Detect
The DQS Transition Detect block generates the DDR Clock Polarity (DDRCLKPOL) and DDR Latch Control (DDRLAT) signal based on the phase of the FPGA clock (SCLK) and edge clock signal (ECLK) at the first DQS transition. The DDR READ control signal and FPGA CLK inputs to this block come from the FPGA core. The DDRLAT
signal is used when implementing DDRX2 output gearing to transfer data from the ECLK to SCLK domain.
Data Valid Module
The data valid module generates a DATAVALID signal. This signal indicates to the FPGA that valid data is transmitted out of the input DDR registers to the FPGA core.
DDR Write Clock
This block inputs the fast edge clock used for the write side and generates two control signals, DQCLK0 and
DQCLK1, and the clock used to generate the DQS clock (DQSW). DQSW is generated by applying the DQSDEL
from the DQSDLL to delay the ECLK (DDR3) or SCLK (DDR and DDR2) inputs. For the DDR3 memory interface
both DQCLK0 and DQCLK1 are generated. These control clocks run at a rate of one-half the edge clock, and
DQS DELAY
PRMBDET
DQSI
ECLKDQSR
+
-
+
Vref- DV* -
*DV ~ 170mV for DDR1 (SSTL25 signaling)
*DV ~ 120mV for DDR2 (SSTL18 signaling)
*DV ~ 100mV for DDR3 (SSTL15 signaling)
DQSDEL
Vref
DDRCLKPOL
PRMBDET
DATA VALID MODULE
DATAVALID
DDR WRITE CLOCK
DQS TRANSITION
DETECT LOGIC
DDRLAT
ECLKW
RST
DYNDELPOL
DYNDELAY[6:0]
ECLK
READ
SCLK
DQCLK0
DQCLK1
DQSW12-95
LatticeECP3 High-Speed
I/O Interface
DQCLK1 is offset delayed by 90° relative to DQCLK0. These two clocks toggle between different legs of a 4:1 mux
allowing 4:1 gearing of data at twice the edge clock rate. When using output DDRX1 instead of DDRX2 gearing,
only the DQCLK1 is output, which is the same as the FPGA clock.
The DDR write clock block also inputs DYNDELPOL and DYNDELAY [6:0] delay inputs. These are used to support
the write leveling required for DDR3 memory interface. This delay can be used to adjust the delays among the DQS
groups to account for any skew that may be introduced due to the DDR3 fly-by topology.
The DYNDELAY [6:0] can input 128 possible delay step settings with each step generating approximately 26ps
nominal delay. In addition, the DYNDELPOL can be used to invert the clock for a 180° shift of the incoming clock.
The DYNDELAY [6:0] and DYNDELPOL inputs should be generated in the memory controller.
DQSBUFD
This primitive implements the strobe logic for DDR3 memory interface. Figure 12-78 shows the primitive symbol.
Figure 12-78. DQSBUFD Symbol
Figure 12-20 provides a description of all the I/O ports associated with the DQSBUFD primitive.
Table 12-20. DQSBUFD Primitive Ports
Port Name I/O Definition
DQSI I DQS strobe input from the memory
Read I Read signal generated from the FPGA core
ECLK I Edge CLK
SCLK I System CLK
DQSDEL I DQS delay signal from the DQSDLL module
ECLKW I Edge CLK used the DDR write side
RST I Reset input
DYNDELPOL I Input from user logic used to invert the clock polarity
DYNDELAY [6:0] I Input from user logic used to delay the ECLK
ECLKDQSR O Delay DQS used to capture the data
PRMBDET O Preamble detect signal, going to the FPGA core logic
DATAVALID O Signal indicating transmission of Valid data to the FPGA core
DDRCLKPOL O DDR Clock polarity signal
DDRLAT O DDR latch control signal
DQSW O Clock used to generate DQS on the write side
DQCLK0 O Clock Output at frequency SCLK used for output gearing
DQCLK1 O Clock output at frequency and phase of SCLK used for output gearing
DQSI
DQSW
DQSBUFD
SCLK
READ
DDRCLKPOL
PRMBDET
DQSDEL
ECLK
DATAVALID
DYNDELPOL
DDRLAT
ECLKDQSR
DQCLK0
DQCLK1
ECLKW
RST
DYNDELAY[6:0]12-96
LatticeECP3 High-Speed
I/O Interface
DQSBUFF
This primitive implements the strobe logic for DDR and DDR2 memory interface. Figure 12-79 shows the primitive
symbol.
Figure 12-79. DQSBUFF Symbol
Table 12-21 provides a description of all the I/O ports associated with the DQSBUFF primitive.
Table 12-21. DQSBUFF Primitive Ports
READ Pulse Generation
The READ signal to the DQSBUFF block is internally generated in the FPGA core. The READ signal will go high
after the READ command to control the DDR-SDRAM is initially asserted. This should normally precede the DQS
preamble by one cycle yet may overlap the trailing bits of a prior read cycle. The DQS Detect circuitry requires the
falling edge of the READ signal to be placed within the preamble stage.
Figure 12-80 shows a READ pulse timing example with respect to the PRMBDET signal.
Port Name I/O Definition
DQSI I DQS strobe input from the memory
READ I Read signal generated from the FPGA core
SCLK I System CLK
DQSDEL I DQS delay signal from the DQSDLL module
ECLKDQSR O Delay DQS used to capture the data
PRMBDET O Preamble detect signal, going to the FPGA core logic
DATAVALID O Signal indicating transmission of valid data to the FPGA core
DDRCLKPOL O DDR Clock polarity signal
DQSW O Clock used to generate DQS on the write side
DQCLK1 O Clock output at frequency and phase of SCLK used for output gearing
DQSI
DQSW
DQSBUFF
SCLK
READ
DDRCLKPOL
PRMBDET
DQSDEL
DATAVALID
ECLKDQSR
DQCLK112-97
LatticeECP3 High-Speed
I/O Interface
Figure 12-80. READ Pulse Generation
DQSBUF Attributes
Table 12-22 shows the attributes can be used with the DQSBUF primitives described above.
Table 12-22. DQSBUF Attributes
Input DDR Primitives
The input DDR primitives represent the input DDR module used to capture both the generic DDR data and the
DDR data coming from a memory interface. There are two available modes for the DDR input registers, one is used
to implement DDRX1 gearing and the other is for DDRX2 gearing. The signals connected to the inputs of the IDDR
are different for the DDR memory interface.
IDDRXD
This primitive implements the input register block in x1 gearing mode. This mode is used to implement DDR/DDR2
memory interfaces in the LatticeECP3 “E” and “EA” devices. It is also used to capture the generic DDRX1 data on
the LatticeECP3 “E” device.
DDR registers are designed to use edge clock routing on the I/O side and the primary clock on the FPGA side. The
ECLK input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFF) when implementAttribute Description Values
Software
Default Used in DQSBUF
DYNDEL_TYPE
Type of Static Delay input to the write control block
Normal: 0° phase shifted
Shifted: 180° phase shifted using clock inversion
NORMAL,
SHIFTED NORMAL DQSBUFD,
DQSBUFE
DYNDEL_VAL Value of Static Delay to the write control block 0-127 0 DQSBUFD,
DQSBUFE
DYNDEL_CNTL Attribute to enable Static or Dynamic DYNDEL STATIC,
DYNAMIC DYNAMIC DQSBUFD,
DQSBUFE
NRZMODE1
Attribute used to select NRZMODE for DDR3 Memory DISABLED
ENABLED DISABLED DQSBUFD
1. NRZMODE is only used with the DDR3 memory interface. This attribute affects the read data valid signal. When enabled, the read data
valid signal will toggle to indicate valid data.
READ
DQS
PRMBDET
FIRST DQS
TRANSITION
PREAMBLE
PRIOR READ CYCLE
POSTAMBLE
POSTAMBLE
OK
FAIL READ
FAIL READ
VTH
OK READ12-98
LatticeECP3 High-Speed
I/O Interface
ing a DDR or DDR2 memory interface. For generic source synchronous DDR applications, this signal should connect to the edge clock input. The SCLK input should be connected to the system (FPGA) clock. DDRCLKPOL is an
input from the DQS clock polarity tree. This signal is generated by the DQS Transition detect circuit in the corresponding DQSBUF block. The DDRCLKPOL signal is used to choose the polarity of the SCLK to the synchronization registers.
Figure 12-81 shows the primitive symbol and all the I/O ports.
Figure 12-81. IDDRXD Symbol
Table 12-23 provides a description of all I/O ports associated with the IDDRXD primitive.
Table 12-23. IDDRXD Ports
Figure 12-82 shows the Input Register Block configured in the IDDRXD mode.
Port Name I/O Definition
D I DDR data
ECLKDQSR I Phase-shifted DQS for DDR memory interfaces. ECLK for generic
DDR interfaces.
SCLK I System clock
DDRCLKPOL I DDR clock polarity signal
QA O Data at positive edge of the clock
QB O Data at the negative edge of the clock
Note: The DDRCLKPOL input to IDDRXD should be connected to the DDRCLKPOL output of the DQSBUFF or
DQFBUFG modules.
IDDRXD
SCLK
QA
QB
D
ECLKDQSR
DDRCLKPOL12-99
LatticeECP3 High-Speed
I/O Interface
Figure 12-82. Input Register Block in IDDRXD Mode
D D Q
D Q
D Q
D Q
DDRCLKPOL D Q
L
SCLK
D Q
L
D Q
L
D Q
L
D Q
D Q
DDR Registers
A
B
D F
E
H
C
G
ECLK CLKP
Synch Registers
DQS
ECLKDQSR
Clock Transfer
Registers
1 0
DDR mem
Note: Simplified diagram does not show CE, SET and RST details. All latches are transparent when low.
1
0
IDDRXD Mode
QB
QA12-100
LatticeECP3 High-Speed
I/O Interface
Figure 12-83. IDDRXD Waveform DDRCLKPOL=0
DQS at I/O
DDR DATA at I/O
ECLKDQSR
DDR DATA at IDDRXD A
E
CLKP
DDRCLKPOL
F
C
XX P0 P1
XX N0 N1
G
H
QA
QB
XX N0 N1
XX P0 P1
XX N0 N1
XX P0 P1
P0 P1 N1
D XX N0 N1
B
N0
P0 N0 P1 N1
P0 N0 P1 N1
XX P0 P1
SCLK
DDR2 Read Waveforms using IDDRXD,
DDRCLKPOL = 012-101
LatticeECP3 High-Speed
I/O Interface
Figure 12-84. IDDRXD Waveform DDRCLKPOL=1
IDDRXD1
This primitive is a simplified version of IDDRXD without the DDRCLKPOL and ECLKDQSR signal for the “EA”
devices. This will also implement the input register block in x1 gearing mode for generic DDRX1 interfaces.
On “EA” devices, the DDR registers use the primary clock (SCLK) only. The SCLK input should be connected to
the system (FPGA) clock. “EA” devices do not require the control signals from the DQSBUF module in the
IDDRXD1 element, making it more flexible for placement than the “E” device.
Figure 12-85 shows the primitive symbol and all the I/O ports.
Figure 12-85. IDDRXD1 Symbol (“EA” Devices)
Table 12-24 provides a description of all I/O ports associated with the IDDRXD1 primitive.
DQS at I/O
DDR DATA at I/O
ECLKDQSR
DDR DATA at IDDRXD A
E
CLKP
DDRCLKPOL
F
C
XX P0 P1
XX N0 N1
G
H
QA
QB
XX N0 N1
XX P0 P1
XX N0 N1
XX P0 P1
P0 P1 N1
D XX N0 N1
B
N0
P0 N0 P1 N1
P0 N0 P1 N1
XX P0 P1
SCLK
DDR2 Read Waveforms using IDDRXD,
DDRCLKPOL = 1
IDDRXD1
D
SCLK
QA
QB12-102
LatticeECP3 High-Speed
I/O Interface
Table 12-24. IDDRXD1 Ports
Figure 12-86 shows the Input Register Block configured in the IDDRXD1 mode.
Figure 12-86. Input Register Block in IDDRXD1 Mode (“EA” Devices)
Figure 12-87. IDDRXD1 Waveform
Port Name I/O Definition
D I DDR data
SCLK I System clock
QA O Data at the positive edge of the clock
QB O Data at the negative edge of the clock
Note: Simplified version does not show CE/SET/RST details. All latches are transparent when LOW.
D D Q
D Q
D Q
D Q
SCLK
D Q
L
D Q
L
D Q
L
D Q
D Q
DDR Registers Synch Registers Clock Transfer
Registers
A
B
D F
E
H
C
G
QB
QA
Data
SCLK
E
F
C
XX P0 P1
XX N0 N1
G
H
QA
QB
XX N0 N1
XX P0 P1
XX N0 N1
XX P0 P1
D XX N0 N1
B
P0 N0 P1 N1
P0 N0 P1 N1
XX P0 P1
P2 N2 P3 N3
P1 P2
P2
N1 P3
P3
N3
N2 N3
P2
N2
P2
N212-103
LatticeECP3 High-Speed
I/O Interface
IDDRX2D
This primitive will implement the input register block in x2 gearing mode. This mode is used to implement DDR3
memory interface on the LatticeECP3 “E” and “EA” devices. It is also used on “E” devices to capture the generic
DDRX2 Input data.
Figure 12-88 shows the IDDRX2D primitive symbol and all the I/O ports.
Figure 12-88. IDDRX2D Symbol
Table 12-25 provides a description of all I/O ports associated with the IDDRX2D primitive.
Table 12-25. IDDRX2D Ports
Figure 12-89 shows the LatticeECP3 Input Register Block configured to function in the IDDRX2D mode.
The ECLKDQSR input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFD) when
implementing a DDR3 memory interface. For generic source synchronous DDR applications, this signal should be
connected to the high-speed source synchronous edge clock input. The ECLK input is connected to the edge
clock. The SCLK input should be connected to the system (FPGA) clock. The SCLK should run at half the frequency of ECLK.
The DDRCLKPOL and DDRLAT inputs are generated by the DQS transition detect circuit in the corresponding
DQSBUF block. The DDRCLKPOL signal is used to choose the polarity of the ECLK to the synchronization registers.DDRLAT is used to transfer data from the ECLK to the SCLK in the Clock Transfer Register block.
Port Name I/O Definition
D I DDR Data
ECLKDQSR I Phase-shifted DQS for DDR memory interfaces. Edge clock for generic DDR interfaces.
ECLK I Edge Clock. Should be connected to DQS strobe for DDR3 memory interfaces.
SCLK I System clock running at one-half the ECLK or DQS signal.
DDRCLKPOL I DDR clock polarity signal
DDRLAT I DDR latch control signal
QA0, QA1 O Data at the positive edge of the clock.
QB0, QB1 O Data at the negative edge of the clock.
Notes:
1. The DDRCLKPOL input to IDDRX2D should be connected to the DDRCLKPOL output of the DQSBUFD for DDR3 memory interfaces or
the DDRCLKPOL output of the DQSBUFE for generic DDRX2 interfaces.
2. The DDRLAT input to the IDDRX2D should be connected to the DDRLAT output of the DQSBUFD for DDR3 memory interfaces or the
DDRLAT output of the DQSBUFE for generic DDRX2 interfaces.
SCLK
QA0
QA1
D
ECLKDQSR
QB0
QB1
ECLK
DDRCLKPOL
DDRLAT
IDDRX2D12-104
LatticeECP3 High-Speed
I/O Interface
Figure 12-89. Input Register Block in IDDRX2D Mode
D D Q
D Q
DDRCLKPOL D Q
L
SCLK
QB0
QB1
QA1
QA0
L
D Q D Q
D Q
D Q
L
D Q
L
D Q
L
D Q
D Q
D Q
D Q
L
D Q D Q
L
DDRLAT
X0
01
11
D Q
CE
R
DDR Registers
A
B
D F
E
H
C
G
L
K
J
I
CLKP
01
11
ECLK
Synch Registers
ECLKDQSR
Clock Transfer and
Gearing Registers
Notes:
1. Simplified version does not show CE/SET/RST details. All latches are transparent when LOW.
2. ECLKDQSR is connected to the DQS signal when in DDR memory mode. In DDR generic mode ECLKDQSR
should be connected to the ECLK signal.
1 012-105
LatticeECP3 High-Speed
I/O Interface
Figure 12-90. IDDRX2D Waveform DDRLAT=0
DQS at I/O
DDR DATA at I/O
ECLKDQSR
DDR DATA at IDDRXDA
E
CLKP
DDRCLKPOL
F
C
XX P0 P1
XX N0 N1
G
H
QA1
QB1
XX N0 N1
XX P0 P1
P0 P1 N1
D XX N0 N1
B
N0
P0 N0 P1 N1
P0 N0 P1 N1
XX P0 P1
ECLK
I
J
K
L
XX N0
XX P0
XX N1
XX P1
QA0
QB0
XX P0 P1
XX N0 N1
XX P0
XX N0
SCLK
SCLK12-106
LatticeECP3 High-Speed
I/O Interface
Figure 12-91. IDDRX2D Waveform DDRLAT=1
IDDRX2D1
This primitive is a simplified version of IDDRX2D without the DDRLAT, DDCLKPOL and the ECLKDQSR signals for
the LatticeECP3 “EA” devices. It is used for input generic DDRX2 input data in “EA” devices.
In this case, the first stage of registers is clocked by the ECLK signal and the second stage is clocked by the SCLK
signal. The “EA” device does not require the control signals from the DQSBUF module in the IDDRX2D1 element.
This makes the “EA” device more flexible for placement than the “E” device.
Figure 12-92 shows the IDDRX2D1 primitive symbol and all the I/O ports.
Figure 12-92. IDDRX2D1 Symbol (“EA” Devices)
Table 12-26 provides a description of all I/O ports associated with the IDDRX2D1 primitive.
G
H
QA1
QB1
XX N0 N1
XX P0 P1
ECLK
I
J
K
L
XX N0
XX P0
XX N1
XX P1
QA0
QB0
XX P0 P1
XX N0 N1
XX P0
XX N0
SCLK
SCLK
IDDRX2D1
D
SCLK
ECLK
QA0
QA1
QB0
QB112-107
LatticeECP3 High-Speed
I/O Interface
Table 12-26. IDDRX2D1 Ports
Figure 12-93 shows the LatticeECP3 Input Register Block configured to function in IDDRX2D1 mode. The ECLK
input is connected to the edge clock. The SCLK input should be connected to the system (FPGA) clock. The SCLK
should run at half the frequency of ECLK.
Figure 12-93. Input Register Block in IDDRX2D1 Mode (“EA” Devices)
Port Name I/O Definition
D I DDR data
ECLK I Edge clock. Should be connected to DQS strobe for DDR3 memory
interfaces.
SCLK I System clock running at one-half ECLK
QA0, QA1 O Data at the positive edge of the clock.
QB0, QB1 O Data at the negative edge of the clock.
D D Q D Q
D Q
SCLK
D Q
D Q
D Q
L
D Q
L
QB0
QB1
QA1
QA0
D Q D Q D Q
L
D Q
L
D Q
L
D Q
CE
R
DDR Registers
A
B
D F
C E
L
K
J
I
ECLK
Synch Registers Clock Transfer and
Gearing Registers
Note: Simplified version does not show CE/SET/RST details. All latches are transparent when LOW.12-108
LatticeECP3 High-Speed
I/O Interface
Figure 12-94. IDDRX2D1 Waveform
ECLKSYNCA
ECLKSYNCA is used in x2 gearing Tx interfaces to synchronize the signals generated from the ECLK after
RESET. These signals include the SCLK, DQCLK0/DQCLK1 and DQSW for DDR memory interfaces.
This module will STOP the ECLK to the CLKDIV and DQSBUF modules until the RESET is released.
Asserting the STOP input of the ECLKSYNC will stop the ECLK output. When the STOP signal is released, every
clock toggling from the second rising edge of the ECLK input will be output from this block. This block resides after
the muxes for edge clock sources and before driving onto the actual edge clock.
Figure 12-95 shows the ECLKSYNCA primitive symbol.
Figure 12-95. ECLKSYNCA Symbol
Table 12-27 lists the port descriptions of the ECLKSYNCA primitive.
Data
ECLK
E
F
C
QA1
QB1
D
B
P0 N0 P1 N1
I
J
L
XX N0
XX P0
XX N1
XX P1
QA0
QB0
XX P0 P1
XX N0 N1
P0 N0 N1 P1
XX P0 P1
XX N0 N1
XX P0 P1
XX N0 N1
K
XX P0
XX N0
SCLK
P2 N2 P3 N3
ECLKSYNCA
STOP
ECLKO
ECLK
eclk12-109
LatticeECP3 High-Speed
I/O Interface
Table 12-27. ECLKSYNCA Port Descriptions
Figure 12-96 is a waveform that shows this operation.
Figure 12-96. ECLKSYNC Operation
This will stop the ECLK to the CLKDIV and DQSBUF until after these blocks are out if reset. By doing this, the user
can synchronize the ECLK, SCLK and the DQCLKs used in the ODDR module.
It is required that there is at least two clock cycles between the release of RESET and the release of the STOP
input to ECLKSYNC. In the IPexpress-generated module, a soft IP consisting of two flip-flops is used to generate
this delayed STOP signal to ECLKSYNC. The reset input to the CLKDIV and DQSBUF is used as an input to these
two flip-flops. The clock input to these flip-flops must be slower than the ECLK.
Refer to the GDDRX2_TX.Aligned, GDDRX2_TX.DQSDLL.Centered and GDDRX2_TX.PLL.Centered interface
descriptions in the High-Speed DDR Interface Details section.
DELAYC
Data going to the DDR registers can be optionally delayed using the delay block. The DELAYC block is used to
compensate for clock injection delay times. The amount of the delay is determined by the software based on the
type of interface implemented using the Interface ID attribute IDDRAPPS. Refer to Interface ID Attribute section for
details. If an incorrect Interface ID is used for a given interface, then the DELAYC setting will be incorrect. It is
important that the correct Interface ID attribute be assigned for each interface to allow the software to set the correct value for DELAYC.
Figure 12-97. DELAYC Symbol
Table 12-28. DELAYC Port Names
DELAYB
Data going to the DDR registers can also be delayed the DELAYB block. Unlike the DELAYC block where the software will control the amount of data delay, DELAYB block will allow user to control the amount of data delay. This
block receives 4-bit delay control. The 4-bit delay can be set by using static delay values or can be dynamically
Port Name I/O Definition
ECLK I Edge clock input
STOP I Signal used to stop the edge clock
ECLKO O Edge clock output
Port Name I/O Description
A I DDR input from sysIO™ buffer
Z O Delayed output
A Z
DELAYC12-110
LatticeECP3 High-Speed
I/O Interface
controlled by the user logic. DELAYB can only be used when the interface type is dynamic. See the Building
Generic High-Speed Interfaces section for details.
The delay can be adjusted in 35ps steps. The user can choose from two types of delay values:
1. Dynamic – The delay value is controlled by the user logic using the inputs DEL[3:0] of the DELAYB block.
2. User-Defined – In this mode, the user chooses a static delay value from one of the 16 delay values. This
will tie the inputs DEL[3:0] of the DELAYB block to a fixed value depending on the value chosen.
Figure 12-98 shows the primitive symbol for the DELAYB mode.
Figure 12-98. DELAYB Symbol
Table 12-29 lists the port names and descriptions for the DELAYB primitive.
Table 12-29. DELAYB Port Names
Output DDR Primitives
The output DDR primitives represent the output DDR module used to generate both the generic DDR output data
and the DDR memory interface data. There are two available modes for DDR output registers. One is used to
implement DDRX1 gearing and the other for DDRX2 gearing.
ODDRXD
This primitive will implement the output register block in x1 gearing mode. This mode is used to implement
DDR/DDR2 memory interfaces on the “E” and “EA” devices. It is also used to generate the generic DDRX1 data on
“E” devices.
Figure 12-99 shows the ODDRXD primitive symbol and its I/O ports.
Figure 12-99. ODDRXD Symbol
Table 12-30 provides a description of all I/O ports associated with the ODDRXD primitive.
Port Name I/O Definition
A I DDR input from the sysIO buffer
DEL (0:3) I Delay inputs
Z O Delay DDR data
A
DEL[3:0]
Z
DELAYB
Q
SCLK
Q
DA
DB
DQCLK1
ODDRXD12-111
LatticeECP3 High-Speed
I/O Interface
Table 12-30. ODDRXD Ports
Figure 12-100 shows the LatticeECP3 Output Register Block configured in the ODDRXD mode.
Figure 12-100. Output Register Block in ODDRXD Mode
Note: Tristate control for ODDRXD can only be implemented using the OFD1S3AX module. If this module is not
implemented in the user’s design then software will infer this module. The clock used in the OFD1SAX should be
the same as the one used in the ODDRXD module. This module will not support tristate inversion.
Figure 12-101 shows the ODDRXD timing waveform.
Port Name I/O Definition
SCLK I System CLK or ECLK
DA I Data at the positive edge of the clock
DB I Data at the negative edge of the clock
DQCLK1 I Clock output at frequency of SCLK used for output gearing
Q O DDR data output
D Q
CE
R
Q
DB D Q
DA
D Q
L
1
0
SCLK
DQCLK1
Note: All latches are transparent when LOW.
D Q
CE
R
D
A
D
Q
(tristate)
Clock Transfer
Registers
DDR Gearing and
ISI Correction
ODDRXD
OFD1S3AX
Data
Output12-112
LatticeECP3 High-Speed
I/O Interface
Figure 12-101. ODDRXD Waveform
ODDRXD1
This element is used to generate the generic DDRX1 data on “EA” devices. The ODDRXD1 in the “EA” device does
not require the DQCLK1 control signal from the DQSBUF block. This makes the “EA” device more flexible for placement than “E” devices.
Figure 12-102 shows the ODDRXD1 primitive symbol and its I/O ports.
Figure 12-102. ODDRXD1 Symbol (“EA” Devices)
Table 12-31 provides a description of all I/O ports associated with the ODDRXD1 primitive.
Table 12-31. ODDRXD1 Ports
Figure 12-103 shows the LatticeECP3 Output Register Block configured in the ODDRXD1 mode.
Port Name I/O Definition
SCLK I System CLK or ECLK
DA I Data at the positive edge of the clock
DB I Data at the negative edge of the clock
Q O DDR data output
SCLK
P0
P0 N0
P1 P2
P2 N2 P3 N3
P3 P4
N0
N0 N1 N2 N3 N4
N1 N2 N3 N4
P0 P1 P2 P3 P4
Q
(tristate)
DA
DB
Q
(data)
DQCLK1
A
D
ODDRXD1
SCLK
DA
DB
Q12-113
LatticeECP3 High-Speed
I/O Interface
Figure 12-103. Output Register Block in ODDRXD1 Mode (“EA” Devices)
Note: Tristate control for ODDRXD1 can only be implemented using the OFD1S3AX module. If this module is not
implemented in the user’s design then software will infer this module. The clock used in the OFD1SAX should be
the same as the one used in the ODDRXD1 module. This module will not support tristate inversion.
Figure 12-104. ODDRXD1 Waveform
ODDRX2D
The ODDRX2D primitive implements the output register for DDR3 memory and generic DDRX2 write functions.
Figure 12-105 shows the ODDRX2D primitive symbol and its I/O ports.
D Q
CE
R
Q
DB D Q
DA
D Q
1
0
SCLK
D Q
CE
R
D
A
D
Q
(tristate)
Clock Transfer
Registers
DDR Gearing
and ISI Correction
ODDRXD1
OFD1S3AX
Data Output
Note: All latches are transparent when LOW.
SCLK
Q (tristate)
DA
DB
D (tristate)
Q (data)12-114
LatticeECP3 High-Speed
I/O Interface
Figure 12-105. ODDRX2D Symbol
Table 12-32 provides a description of all I/O ports associated with the ODDRX2D primitive.
Table 12-32. ODDRX2D Ports
ODDRTDQA
The ODDRTDQA primitive implements the tristate register block for DDR3 memory and generic x2 DDR write functions.
Figure 12-106 shows the ODDRTDQA primitive symbol and its I/O ports.
Figure 12-106. ODDRTDQA Symbol
Figure 12-33 provides a description of all I/O ports associated with the ODDRTDQA primitive.
Port Name I/O Definition
SCLK I System CLK or ECLK
DA0 I First data at the positive edge of the clock
DB0 I First data at the negative edge of the clock
DA1 I Second data at the positive edge of the clock
DB1 I Second data at the negative edge of the clock
DQCLK0 I Clock Output at frequency of SCLK used for output gearing
DQCLK1 I Clock output at frequency of SCLK used for output gearing (90°
shifted from DQCLK0)
Q O DDR data output
Q
SCLK
Q
DQCLK0
DA1
DA0
DB0
DB1
DQCLK1
ODDRX2D
ODDRTDQA
TA
SCLK
Q
DQCLK1
DQCLK012-115
LatticeECP3 High-Speed
I/O Interface
Table 12-33. ODDRTDQA Ports
Figure 12-107. Output Register Block in ODDRX2D/ODDRTDQA Mode
Figure 12-107 shows the LatticeECP3 Output Register Block configured in the ODDRX2D and ODDRTDQA
tristate modes.
Note: Tristate control for ODDRX2D can only be implemented using the ODDRTDQA module. The clock used in
the ODDRTDQA should be the same as the one used in the ODDRX2D module. This module will not support
tristate inversion.
Port Name I/O Definition
SCLK I System CLK or ECLK
TA I Tristate input
DQCLK0 I Clock output at frequency of SCLK used for output gearing
DQCLK1 I Clock output at frequency of SCLK used for output gearing (90° shifted from DQCLK0)
Q O DDR tristate output
D Q
D Q
Q
Q
D Q
DB1 D Q
DA0
DA1
DB0
D Q
L
L
SCLK
DQCLK1
DQCLK0
Note: All latches are transparent when LOW.
ISI
D Q
CE
R
TA D Q
A
B
C
D
C1
D1
(tristate)
Clock Transfer
Registers
DDR Gearing and
ISI Correction
ODDRX2D
ODDRTDQA
Data
Output
SCLK
DQCLK1
DQCLK0
11
10
00
01
D Q
CE
R12-116
LatticeECP3 High-Speed
I/O Interface
On the ODDRX2, it is required that the SCLK be in correct phase with DQCLK1 for the data to be captured correctly inside the ODDRX2. The figure below explains the correct relationship between the SCLK and DQCLK1.
SCLK edge must be delayed to occur after the DQCLK1 edge for the data to be captured without any glitches.
Figure 12-108. Correct DQCLK1 Polarity
Figure 12-109. Incorrect DQCLK1 Polarity
The soft IP, ECLKSYNCA, CLKDIVB, DQSBUFE1 and the SCLK routing delay will ensure the correct phase relationship between SCLK and DQCLK inside the ODDRX2 module. The user must generate the interface using IPexpress to guarantee this delay is achieved.
ODDRXDQSA
The ODDRXDQSA primitive implements the output register for generating the DQS strobe signal for DDR and
DDR2 memory
Figure 12-110 shows the ODDRXDQSA primitive symbol and its I/O ports.
ECLK
A/B
C/D
DQCLK1
DQCLK0
SCLK
DQCLK1
DQCLK0
P0/N0 P2/N2
P1/N1 P3/N3
N0 P0 N1 P1 N2 P2 N3 P3
A/B
C/D
DQCLK1
DQCLK0
SCLK
DQCLK1
DQCLK0
P0/N0 P2/N2
P1/N1 P3/N3
N0 P0 N1 P1 N2 P2 N3 P312-117
LatticeECP3 High-Speed
I/O Interface
Figure 12-110. ODDRXDQSA Symbol
Table 12-34 provides a description of all I/O ports associated with the ODDRXDQSA primitive.
Table 12-34. ODDRXDQSA Ports
ODDRTDQSA
The ODDRTDQSA primitive implements the tristate register block for DDR/DDR2 and DDR3 memory DQS output
clock generation.
Figure 12-111 shows the ODDRTDQSA primitive symbol and its I/O ports.
Figure 12-111. ODDRTDQSA Symbol
Table 12-35 provides a description of all I/O ports associated with the ODDRTDQSA primitive.
Table 12-35. ODDRTDQSA Ports
Figure 12-112 shows the LatticeECP3 Output Register Block configured in the ODDRXDQSA and ODDRTDQSA
tristate modes.
Port Name I/O Definition
SCLK I System CLK or ECLK
DA I Data input
DQSW I DQS write clock
DQCLK1 I Clock output at frequency of SCLK used for output gearing
DQSTCLK O DQS tristate clock
Q O DQS data output
Port Name I/O Definition
SCLK I System CLK or ECLK
DB I Data input
DQSW I DQS write clock
DQSTCLK I DQS tristate Clock
TA I Tristate input
Q O DQS tristate output
ODDRXDQSA
SCLK
Q
DA
DQCLK1
DQSW
DQSTCLK
ODDRTDQSA
TA
SCLK
Q
DB
DQSTCLK
DQSW12-118
LatticeECP3 High-Speed
I/O Interface
Figure 12-112. Output Register Block in ODDRXDQSA/ODDRTDQSA Mode
Note: Tristate control for ODDRXDQSA can only be implemented using the ODDRTDQSA module. The clock used
in the ODDRTDQSA should be the same as the one used in the ODDRXDQSA module. This module will not support tristate inversion.
Figure 12-113 shows the ODDRXDQSA and ODDRTDQSA timing waveform.
Figure 12-113. ODDRXDQSA/ODDRTDQSA Waveform
D Q
CE
R
Q
DB0
1
0
SCLK
DQCLK1
D Q
CE
R
TA D Q
A
D
Q
(tristate)
Clock Transfer
Registers
DDR Gearing
& ISI Correction
ODDRXDQSA
ODDRTDQSA
D Q
L
1
0
D Q
2E
D Q
2E
DQSW
0
DB
DQSTCLK
DQS
Output
DQSW
DQSTCLK
DQCLK1
DQSW
Q
E
A
D
SCLK
DQS TRI
DB0
0
TA
DB
P0
P0
P1
P1
P2
P2
P3
P3
P4
P4
P0 P2 P312-119
LatticeECP3 High-Speed
I/O Interface
ODDRX2DQSA
The ODDRX2DQSA primitive implements the output register for generating the DQS strobe signal for DDR3 memory interfaces.
Figure 12-114 shows the ODDRX2DQSA primitive symbol and its I/O ports.
Figure 12-114. ODDRX2DQSA Symbol
Table 12-36 provides a description of all I/O ports associated with the ODDRX2DQSA primitive.
Table 12-36. Table 33 ODDRX2DQSA Ports
Table 12-115 shows the LatticeECP3 Output Register Block configured in the ODDRX2DQSA and ODDRTDQSA
tristate mode.
Port Name I/O Definition
SCLK I System CLK or ECLK
DB0 I Data input
DB1 I Data input
DQSW I DQS write clock
DQCLK0 I Clock output at frequency of SCLK used for output gearing
DQCLK1 I Clock output at frequency of SCLK and shifted 90°, used for output gearing
DQSTCLK O DQS tristate clock
Q O DDR data output
SCLK
Q
DB0
DB1
DQCLK1
ODDRX2DQSA
DQSW
DQSTCLK
DQCLK012-120
LatticeECP3 High-Speed
I/O Interface
Figure 12-115. Output Register Block in ODDRX2DQSA/ODDRTDQSA Mode
Note: Tristate control for ODDRX2DQSA can only be implemented using the ODDRTDQSA module. The clock
used in the ODDRTDQSA should be the same as the one used in the ODDRX2DQSA module. This module will not
support tristate inversion.
Figure 12-116 shows the ODDRX2DQSA timing waveform.
D Q
D Q
CE
R
Q
D Q
L
11
10
00
01
ISI
D Q
CE
R
D Q
A
B
C
D
C1
Q
(tristate)
Clock Transfer Registers
DDR Gearing &
ISI Correction
Ouput Register Block for DQS
Tristate Register Block for DQS
DQS
Output
D Q
L
1
0
D Q
2E
D Q
2E
0
0
DQSTCLK
SCLK
DQCLK1
DQCLK0
Note: All latches are transparent when LOW.
TA
DQSW
DB
DQSW
DQSTCLK
DB0
DB112-121
LatticeECP3 High-Speed
I/O Interface
Figure 12-116. ODDRX2DQSA/ODDRTDQSA Waveform
Interface ID Attribute
This attribute provides an ID setting for each of the high-speed interfaces in the LatticeECP3 “EA” device.
IDDRAPPS attribute is used for input interfaces and ODDRAPPS attribute is used for output interfaces. The value
for these is pre-determined for each high-speed DDR interfaces. These attributes will be set to the correct values
when the interfaces are generated by IPexpress. If an IDDRAPPS or ODDRAPPS attribute is not set for a given
interface, the software will error out. If an attribute value is not set correctly for a given interface, then the wrong
data delay is used in the DELAYC element for that interface.
The IDDRAPPS and ODDRAPPS attributes are strings. They are only generated for “EA” devices.
Table 12-37. Interface ID (IDDRAPPS/ODDRAPPS) Attribute Values
Interfaces Name Interface ID (Primitive: ATTRIBUTE = Value)1, 2
Generic Interfaces
GIREG_RX.SCLK N/A
GDDRX1_RX.SCLK.Aligned IDDRXD1: IDDRAPPS = SCLK_ALIGNED
GDDRX1_RX.SCLK.Centered IDDRXD1: IDDRAPPS = SCLK_CENTERED
GDDRX1_RX.DQS.Aligned IDDRXD: IDDRAPPS = DQS_ALIGNED
GDDRX1_RX.DQS.Centered IDDRXD: IDDRAPPS = DQS_CENTERED
GDDRX2_RX.ECLK.Aligned IDDRX2D1: IDDRAPPS = ECLK_ALIGNED
GDDRX2_RX.ECLK.Centered IDDRX2D1: IDDRAPPS = ECLK_CENTERED
GDDRX2_RX.DQS.Aligned IDDRX2D: IDDRAPPS = DQS_ALIGNED
GDDRX2_RX.DQS.Centered IDDRX2D: IDDRAPPS = DQS_CENTERED
GDDRX2_RX.ECLK.Dynamic IDDRX2D1: IDDRAPPS = ECLK_DYNAMIC
GDDRX2_RX.DQS.Dynamic IDDRX2D: IDDRAPPS = DQS_DYNAMIC
GDDRX2_RX.PLL.Dynamic IDDRX2D1: IDDRAPPS = PLL_DYNAMIC
DQCLK1
DQCLK0
DQSW
Q (DQS)
E
SCLK
DQS TRI
DB –> TSB
TA –> TSA
0 –> D
DB1 –> C
0 –> B
DB0 –> A P0
N0
P1 P2 P3 P4
N1 N2 N3 N4
P0 N0 P2
P0 N0 N1
P1 N1 P3
P2 N2 P3 N312-122
LatticeECP3 High-Speed
I/O Interface
ISI Calibration
ISI correction is only available in the ODDRX2D or ODDRX2DQSA modes on the left and right sides of the device.
ISI calibration settings exist once per output, so each I/O in a DQS-12 group may have a different ISI calibration
setting.
The ISI Calibration is set using the ISI_CAL attribute. Table 12-38 shows the values that can be set for this attribute.
Table 12-38. ISI Calibration Attribute
The ISI block extends output signals at certain times, as a function of recent signal history, so it can be read at the
output signal’s destination. If the output pattern consists of long strings of 0s to long strings of 1s, there are no
delays on output signals. However, if there are quick, successive transitions from 010, the block will stretch out the
binary 1. This is because the long trail of 0s will cause these symbols to interfere with the logic 1. Likewise, if there
are quick, successive transitions from 101, the block will stretch out the binary 0.
This block is controlled by a 3-bit delay “stretching” control, set in the DQS logic section. There are eight settings in
the range from “BYPASS” to “DEL7”.
GOREG_TX.SCLK ODDRXD1: ODDRAPPS = SCLK_ALIGNED
GDDRX1_TX.SCLK.Centered ODDRXD1: ODDRAPPS = SCLK_CENTERED (CLOCK)
ODDRXD1: ODDRAPPS = SCLK_ALIGNED (DATA)
GDDRX1_TX.SCLK.Aligned ODDRXD1: ODDRAPPS = SCLK_ALIGNED (CLOCK)
ODDRXD1: ODDRAPPS = SCLK_ALIGNED (DATA)
GDDRX1_TX.DQS.Centered ODDRXDQSA: ODDRAPPS = DQS_CENTERED (CLOCK)
ODDRXD: ODDRAPPS = DQS_ALIGNED (DATA)
GDDRX2_TX.Aligned ODDRX2D: ODDRAPPS = ECLK_ALIGNED (CLOCK)
ODDRX2D: ODDRAPPS = ECLK_ALIGNED (DATA)
GDDRX2_TX.DQSDLL.Centered ODDRX2DQSA: ODDRAPPS = DQS_CENTERED (CLOCK)
ODDRX2D: ODDRAPPS = DQS_ALIGNED (DATA)
GDDRX2_TX.PLL.Centered ODDRX2D: ODDRAPPS = ECLK_CENTERED (CLOCK)
ODDRX2D: ODDRAPPS = ECLK_ALIGNED (DATA)
GDDRX1_RX.ECLK.Aligned N/A: not a LatticeECP3 “EA” configuration.
GDDRX1_RX.ECLK.Centered N/A: not a LatticeECP3 “EA” configuration.
DDR Memory Interfaces
DDR MEM
ODDRXDQSA: ODDRAPPS = DDR_MEM_DQS
IDDRXD: IDDRAPPS = DDR_MEM_DQ
ODDRXD: ODDRAPPS = DDR_MEM_DQ
DDR2 MEM
ODDRXDQSA: ODDRAPPS = DDR2_MEM_DQS
IDDRXD: IDDRAPPS = DDR2_MEM_DQ
ODDRXD: ODDRAPPS = DDR2_MEM_DQ
1. Attribute should be assigned on the corresponding IDDRX/ODDRX primitives.
2. Interface IDs are only valid for LatticeECP3 “EA” devices.
Attribute Description Values Software Default
ISI_CAL Used to set the ISI Correction values
BYPASS, DEL1,
DEL2, DEL3,
DEL4, DEL5,
DEL6, DEL7
BYPASS
Table 12-37. Interface ID (IDDRAPPS/ODDRAPPS) Attribute Values (Continued)
Interfaces Name Interface ID (Primitive: ATTRIBUTE = Value)1, 212-123
LatticeECP3 High-Speed
I/O Interface
Migrating Designs from LatticeECP3 “E” to “EA”
This section lists the changes in design required when moving from LatticECP3 “E” device to an “EA” device. The
LatticeECP3-150EA device was designed as an “E” device in ispLEVER 7.2 SP2. So these changes will also be
required if moving a LatticeECP3-150EA design from ispLEVER 7.2 SP2 to ispLEVER 8.0 or later versions. It is
required that all LatticeECP3-150EA designs be implemented in ispLEVER 8.0 or newer software. Refer to the section Migrating Designs from ispLEVER 7.2 SP2 to ispLEVER 8.0 to see other changes required when you are moving designs from ispLEVER 7.2 SP2 to ispLEVER 8.0 or later versions of the software. The same changes will
apply if moving from ispLEVER 7.2 to the Lattice Diamond design software as well.
A summary of the differences between the “E” and “EA” devices are listed below:
• DDR x1 interfaces on “E” devices use ECLK (edge clock) as the clock input limiting the number of interfaces to 1
per side. DDR x1 interfaces on “EA” devices use the SCLK clock input, so you can have more than one interface
per side of the device.
• “E” device requires that DQSBUF be used to implement both x1 and x2 input and output DDR functions. “EA”
devices do not require the DQSBUF to implement the input and x1 output DDR functions. X2 output DDR functions will require the use of DQSBUF.
• The “E” devices require the data pins to be grouped into DQS groups so that every 10 data bits are locked to a
DQS group. This grouping is not required on the “EA” devices for inputs and 1x output interfaces. 2x output interfaces on “EA” would require DQS grouping.
• The primitives used for Generic DDR input and output functions are different between “E” and “EA”.
• All “EA” designs require that the IDDRAPPS/ODDRAPPS be assigned to each interface which is not required on
the “E” device. Refer to the section Interface ID Attribute for a description of this attribute. IPexpress-generated
modules will contain this attribute.
• In DDR and DDR2 memory, the implementation will mostly be same between “E” and “EA” devices. But since
DDR and DDR2 use generic DDR to generate the output CLKP/CLKN signal, these must use new primitives on
the “EA” device. In addition, all the primitives require the IDDRAPPS/ODDRAPPS attributes to be added for the
“EA” device.
Refer to the section DDR Software Primitives and Attributes for a detailed description of the primitives. Table 12-39
lists the clocking differences between “E” and “EA” devices for each interface. Table 12-40 lists the differences in
library elements used for each interfaces. Refer to the High-Speed DDR Interface Details section for block diagrams of each of the interfaces in the tables below.
Table 12-39. “E” to “EA” Clocking Differences
“E” Interface
Clocking
Resource
DQS Grouping
for Pins Equivalent “EA” Interface
Clocking
Resource
DQS Grouping
for Pins
GIREG_RX.SCLK SCLK No GIREG_RX.SCLK SCLK No
GDDRX1_RX.ECLK.Aligned ECLK Yes GDDRX1_RX.SCLK.Aligned SCLK No
GDDRX1_RX.ECLK.Centered ECLK Yes GDDRX1_RX.SCLK.Centered SCLK No
GDDRX1_RX.DQS.Aligned DQS Tree Yes GDDRX1_RX.DQS.Aligned DQS Tree Yes
GDDRX1_RX.DQS.Centered DQS Tree Yes GDDRX1_RX.DQS.Centered DQS Tree Yes
GDDRX2_RX.ECLK.Aligned ECLK Yes GDDRX2_RX.ECLK.Aligned ECLK No12-124
LatticeECP3 High-Speed
I/O Interface
Table 12-40. “E” to “EA” Primitive Changes
Due to the differences described above, some of the “E” interfaces must be regenerated in the software as an “EA”
device. Table 12-41 can be used as a guide to determine which interfaces need to be regenerated. When necessary, interfaces should be regenerated using the IPexpress software tool.
“E” Interface Primitives Required Equivalent “EA” Interface Primitives Used
GIREG_RX.SCLK IFS1P3DX GIREG_RX.SCLK IFS1P3DX
GDDRX1_RX.ECLK.Aligned
IDDRXD
DQSBUFG
TRDLLB
DLLDELB
CLKDIVB
GDDRX1_RX.SCLK.Aligned
IDDRX1D
TRDLLB
DLLDELB
CLKDIVB
GDDRX1_RX.ECLK.Centered IDDRXD
DQSBUFG GDDRX1_RX.SCLK.Centered IDDRX1D
GDDRX1_RX.DQS.Aligned
IDDRXD
DQSBUFF
DQSDLL
GDDRX1_RX.DQS.Aligned
IDDRXD
DQSBUFF
DQSDLL
GDDRX1_RX.DQS.Centered
IDDRXD
DQSBUFF
DQSDLL
GDDRX1_RX.DQS.Centered
IDDRXD
DQSBUFF
DQSDLL
GDDRX2_RX.ECLK.Aligned
IDDRX2D
DQSBUFE
TRDLLB
DLLDELB
CLKDIV
GDDRX2_RX.ECLK.Aligned
IDDRX2D1
TRDLLB
DLLDELB
CLKDIVB
GDDRX2_RX.ECLK.Centered
IDDRX2D
DQSBUFE
CLKDIVB
GDDRX2_RX.ECLK.Centered IDDRX2D1
CLKDIVB
GDDRX2_RX.DQS.Aligned
IDDRX2D
DQSBUFD
DQSDLL
PLL
GDDRX2_RX.DQS.Aligned
IDDRX2D
DQSBUFD
DQSDLL
PLL
GDDRX2_RX.DQS.Centered
IDDRX2D
DQSBUFD
DQSDLL
CLKDIVB
GDDRX2_RX.DQS.Centered
IDDRX2D
DQSBUFD
DQSDLL
CLKDIVB
GOREG_TX.SCLK
OFS1P3DX (data)
ODDRXD (clock)
DQSBUFG (left/right sides only)
GOREG_TX.SCLK OFS1P3DX (data)
ODDRXD1
GDDRX1_TX.SCLK.Centered
ODDRXD
DQSBUFG (left/right sides only)
PLL
GDDRX1_TX.SCLK.Centered ODDRXD1
PLL
GDDRX1_TX.SCLK.Aligned ODDRXD
DQSBUFG GDDRX1_TX.SCLK.Aligned ODDRX1D
GDDRX1_TX.DQS.Centered
ODDRXD (data)
ODDRDQSA (clock)
DQSBUFF
DQSDLL
GDDRX1_TX.DQS.Centered
ODDRXD (data)
ODDRDQSA (clock)
DQSBUFF
DQSDLL12-125
LatticeECP3 High-Speed
I/O Interface
Table 12-41. “E” to “EA” Design Conversion Table
Migrating Designs from ispLEVER 7.2 SP2 to ispLEVER 8.0
This section lists changes that need to be made to existing designs when migrating from ispLEVER 7.2 SP2 to ispLEVER 8.0 and later versions of the software. The same changes will apply if moving from ispLEVER 7.2 to the
Lattice Diamond design software as well.
LatticeECP3-70E and LatticeECP3-90E designs:
• No HDL changes are required to move the LatticeECP3 “E” generic designs from ispLEVER 7.2 SP2 to ispLEVER 8.0
• It is required to re-run the designs through the software Map, Place and Route. ispLEVER 8.0 has an added
Design Rule Check that will flag any general non-dedicated routed used on clock paths to DDR interfaces.
• If any of these errors occur, they must be fixed by either changing the clock pin assignment to a dedicated pin or
by adding preferences to route the clock on dedicated clock routes.
• All the interface rules and placement guidelines specified for the interface must be followed.
LatticeECP3-150EA designs:
• All “EA” designs were implemented as “E” designs in ispLEVER 7.2 SP2. All “EA” generic DDR designs will have
to be regenerated when moving over to ispLEVER 8.0 except for the designs using DQS interfaces.
• The requirements listed in the section Migrating Designs from LatticeECP3 “E” to “EA” should be followed when
moving “EA” designs from ispLEVER 7.2 SP2 to ispLEVER 8.0.
• All modules should be regenerated using IPexpress.
• “EA” designs require that an Interface ID attribute, IDDRAPPS or ODDRAPPS, be added to all the IDDR and
ODDR elements to indicate the interface topology being used. The software will error out if it does not see this
attribute on the DDR elements. These attributes are added automatically when IPexpress is used to generate the
interface.
Other important migration rules:
• All DDR designs must only use one of the pre-defined topologies listed in this technical note.
• All DDR interfaces must be generated using the IPexpress software tool.
“E” Interface Equivalent “EA” Interface Regeneration Required1
GIREG_RX.SCLK GIREG_RX.SCLK No
GDDRX1_RX.ECLK.Aligned GDDRX1_RX.SCLK.Aligned Yes
GDDRX1_RX.ECLK.Centered GDDRX1_RX.SCLK.Centered Yes
GDDRX1_RX.DQS.Aligned GDDRX1_RX.DQS.Aligned No
GDDRX1_RX.DQS.Centered GDDRX1_RX.DQS.Centered No
GDDRX2_RX.ECLK.Aligned GDDRX2_RX.ECLK.Aligned Yes
GDDRX2_RX.ECLK.Centered GDDRX2_RX.ECLK.Centered Yes
GDDRX2_RX.DQS.Aligned GDDRX2_RX.DQS.Aligned No
GDDRX2_RX.DQS.Centered GDDRX2_RX.DQS.Centered No
GOREG_TX.SCLK GOREG_TX.SCLK Yes
GDDRX1_TX.SCLK.Centered GDDRX1_TX.SCLK.Centered Yes
GDDRX1_TX.SCLK.Aligned GDDRX1_TX.SCLK.Aligned Yes
GDDRX1_TX.DQS.Centered GDDRX1_TX.DQS.Centered No
1. All designs should be regenerated using IPexpress.12-126
LatticeECP3 High-Speed
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• This technical note must be strictly followed to understand the interface rules, placement guidelines and timing
analysis for all interfaces.
• ispLEVER 7.2 SP2 allows the use of either the DELAYB or DELAYC element to delay the incoming data. In ispLEVER 8.0, all non-dynamic interfaces must only use the DELAYC element to delay the data input. DELAYB can
only be used only for dynamic interfaces.
• A new Interface ID attribute IDDRAPPS and ODDRAPPS is required for “EA” devices. The software uses this
attribute to determine the delay settings to be programmed into the DELAYC element. Refer to the DDR Software
Primitives and Attributes section for the values to be used for this attribute. In ispLEVER 8.0 the software will
error out if this attribute is not assigned for “EA” devices. “E” devices do not require this attribute.
• It is required that clocks connected to the DDR registers only use dedicated clock resources. No general routing
should be used on these clocks. A new DRC check was added to ispLEVER 8.0 Place and Route that will generate an error message if the clocks to any of the DDR elements are not using a dedicated clock route. This check
will also generate an error message if the clock going to the PLL/DLL that is generating the DDR clocks is not
using a dedicated route. As a result, you may see designs passing all DRC checks in ispLEVER 7.2 SP2 fail in
ispLEVER 8.0. It is recommended that this problem be fixed by changing either clock location or adding preferences to reroute the clock using a dedicated clock route.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com12-127
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I/O Interface
Revision History
Date Version Change Summary
February 2009 01.0 Initial release.
June 2009 01.1 Updated for ispLEVER 7.2 SP2. Some of the implementation listed here
may not be valid if using ispLEVER 7.2 SP1.
November 2009 01.2 Updated for the LatticeECP3 “EA” device and for ispLEVER 8.0 software support. Includes new methodology to implement DDR interfaces
in LatticeECP3 devices.
November 2009 01.3 Updated DDR3 termination and pin assignments.
March 2010 01.4 Updated the termination scheme for DDR3 to external VTT termination.
April 2010 01.5 Updated to reflect all the Generic DDR and DDR memory enhancements made in ispLEVER 8.0 Service Pack 1.
June 2010 01.6 Added Appendix B. Building SDR/DDR Interfaces Using IPexpress in
Diamond.
April 2011 01.7 Updated to include additional clarification in the Generic Timing Analysis, DDR Primitive and Attribute and DDR3 Clock Synchronization modules.
September 2011 01.8 Updated the DDR3 Pinout Guidelines.
Added the DDR3 Termination Guidelines and Layout Considerations.
Updated the DQSDLL Update Control section.
December 2011 01.9 Updated Generic DDR Design Guidelines with new sections on Design
guidelines, Clocking guidelines, Common software errors and valid window calculation.
Updated DDR3 Clock Synchronization Module with new table for DDR3
clock and PGROUP locations.
Updated DDR3 Pinout Guidelines with a new sections on DDR3 pin
placements for Improved Noise Immunity and table for DQS Group Allocation.
Updated ECLKSYNCA & ODDRX2D in the DDR Software Primitives
and Attributes section.
Updated GDDRX2_TX.DQSDLL.Centered Interface with the requirement that CLKOUT must be assigned to DQS pin and this pin cannot
support LVDS IO Standard.
Updated DQSDLLB with domain transfer consideration on the
UDDCNTLN input.
February 2012 02.0 Updated document with new corporate logo.
November 2012 02.2 Updated GDDRX1_RX.DQS.Centered Interface (“E” and “EA” Devices)
diagram.
Updated DQSDLL Configuration text section and removed DQSDLL
Attributes table.
Updated IDDRXD1 Waveform diagram.
Updated ODDRXD Waveform diagram.
April 2013 02.3 Updated GDDRX2_RX.DQS.Aligned Interface (“E” and “EA” Devices)
figure.
Updated Interface Rules for GDDRX1_RX.DQS.Centered,
GDDRX1_RX.DQS.Aligned, GDDRX2_RX.DQS.Aligned,
GDDRX2_RX.DQS.Centered, GDDRX2_TX.DQSDLL.Centered, and
GDDRX2_TX.PLL.Centered.
Update the Pin Placement Guidelines for High-Speed Interfaces table.
Added information to the High-Speed Clock Bridge (“EA” Devices) section.12-128
LatticeECP3 High-Speed
I/O Interface
Appendix A. Building DDR Interfaces Using IPexpress in ispLEVER 7.2 SP2
This appendix describes the interface generation for DDR Generic and DDR Memory using IPexpress in ispLEVER
7.2 SP2. It is highly recommended to update your software to the latest version. This appendix is only for reference.
IPexpress can be used to configure and generate the DDR Memory Interface and Generic DDR Module. The tool
will generate an HDL module that will contain the DDR primitives. This module can be used in the top-level design.
To implement the correct clocking structures to be used for high-speed source synchronous interfaces, see the
High-Speed DDR Interface Details section.
Figure 12-117 shows the main window of IPexpress. The DDR_Generic and DDR_MEM options are under Architecture.
Figure 12-117. IPexpress Main Window12-129
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I/O Interface
DDR Generic
Figure 12-117 shows the main window when DDR_GENERIC is selected. The only entry required in this window is
the module name. Other entries are set to the project settings. The user may change these entries if desired. After
entering the module name, click on Customize to open the Configuration Tab window as shown in Figure 12-118.
Figure 12-118. IPexpress Main Window for DDR_Generic12-130
LatticeECP3 High-Speed
I/O Interface
Configuration Tab
The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate
to generate source and constraint files. The user may choose to use the .lpc file to load parameters.
Figure 12-119. Configuration Tab for DDR_Generic
The user can change the Mode parameter to choose either Input or Output Tristate DDR module.
The other configuration parameters will change according to the mode selected. The delay and parameter are only
available for Input modes.
Table 12-42 describes all user parameters in the IPexpress GUI and their usage.
Table 12-42. User Parameters in the IPexpress GUI
User Parameter Description Values/Range Default
Mode Mode selection for the DDR block Input, Output, Tristate Input
Data Width Width of the data bus 1-64 8
Gearing Ratio Gearing ratio selection 1x, 2x 1x
Delay Input delay configuration Dynamic, User Defined, Fixed User Defined
FDEL User-defined delay values. Available only when Delay is
configured to User Defined. 0-15 012-131
LatticeECP3 High-Speed
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DDR_MEM
Figure 12-120 shows the main window when DDR_MEM is selected. Similar to the DDR_Generic, the only entry
required here is the module name. Other entries are set to the project settings. The user may change these entries
if desired. After entering the module name, click on Customize to open the Configuration Tab window as shown in
Figure 12-120. Although the user can generate the DDR3_MEM using IPexpress in ispLEVER 7.2 SP2, it is recommended that the LatticeECP3 DDR3 Memory Controller IP Core be referred to prior to building any DDR3 memory
controllers with LatticeECP3 devices.
Figure 12-120. IPexpress Main Window for DDR_MEM12-132
LatticeECP3 High-Speed
I/O Interface
Configuration Tab
The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate
to generate source and constraint files. The user may choose to use the .lpc file to load parameters.
Figure 12-121. Configuration Tab for DDR_MEM
The user can change the Mode parameter to the DDR, DDR2 or DDR3 interface. The other configuration parameters will change according to the mode selected. The Number of DQS parameter determines the number of DDR
Interfaces. The software will assume there are eight data bits for every DQS. The user can also choose the frequency of operation; the DDRDLL will be configured to this frequency.
It is recommended that the Lock/Jitter be enabled if the DDR interface is running at 133 MHz or higher. ISI Calibration is only allowed for DDR3 configuration. The parameters available depend on the mode selected. Tables 35, 36
and 37 describe all user parameters in the IPexpress GUI and their usage for modes DDR, DDR2 and DDR3.12-133
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I/O Interface
Table 12-43. User Parameters in the IPexpress GUI when in DDR Mode
Table 12-44. User Parameters in the IPexpress GUI when in DDR2 Mode
Table 12-45. User Parameters in the IPexpress GUI when in DDR3 Mode
User Parameter Description Values/Range Default
I/O Buffer Configuration I/O standard used for the interface. This also depends on
the mode selected. SSTL25_I, SSTL25_II SSTL25_I
Data Width Width of the data bus. 8-64 8
Number of DQS Number of DQS will determine the number of DQS groups 1, 2, 4, 8 1
Frequency of DQS DDR Interface Frequency. This is also input to the DDR
DLL. The values will depend on the mode selected.
100 MHz, 133MHz,
166MHz, 200MHz 200 MHz
Lock/Jitter Sensitivity DLL sensitivity to jitter. High, Low High
User Parameter Description Values/Range Default
I/O Buffer Configuration I/O standard used for the interface. This also depends on
the mode selected. SSTL18_I, SSTL18_II SSTL18_I
Data Width Width of the data bus. 8-64 8
Number of DQS Number of DQS will determine the number of DQS groups 1, 2, 4, 8 1
Frequency of DQS DDR Interface Frequency. This is also input to the DDR
DLL. The values will depend on the mode selected.
166 MHz, 200 MHz,
266 MHz 200 MHz
Lock/Jitter Sensitivity DLL sensitivity to jitter. High, Low High
DQS Buffer
Configuration for DDR2
DQS buffer can be optionally configured as Differential for
DDR2. On/Off Off
User Parameter Description Values/Range Default
I/O Buffer Configuration I/O standard used for the interface. This also depends on
the mode selected. SSTL15_I, SSTL15_II SSTL15_I
Data Width Width of the data bus. 8-64 8
Number of DQS Number of DQS will determine the number of DQS groups 1, 2, 4, 8 1
Frequency of DQS DDR Interface Frequency. This is also input to the DDR
DLL. The values will depend on the mode selected. 400 MHz 400 MHz
Lock/Jitter Sensitivity DLL sensitivity to jitter. High, Low High
ISI Calibration ISI calibration setting for DDR3 output.
BYPASS, DEL1, DEL2,
DEL3, DEL4, DEL5,
DEL6, DEL7
BYPASS12-134
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Appendix B. Building SDR/DDR Interfaces Using IPexpress in Diamond
This appendix describes the interface generation for DDR Generic and DDR Memory using IPexpress in Lattice
Diamond design software. The IPexpress tool is used to configure and generate all the high-speed interfaces
described in this document. IPexpress generates a complete HDL module including clocking requirements for each
of the interfaces.
For a detailed block diagram of each interface generated by IPexpress, see the section High-Speed DDR Interface
Details. IPexpress can be opened from the Tools menu in Project Navigator. All DDR modules are located under
Architecture Modules > IO. This section will cover SDR and DDR_GENERIC. DDR_MEM as discussed in the
Implementing DDR/DDR2/DDR3 Memory Interfaces section.
Figure 12-122. IPexpress Main Window
Select the type of interface you would like to build and enter the name of the module. Figure 12-122 shows the type
of interface selected as “SDR” and the module name entered. Each module can then be configured by clicking the
Customize button.
Building SDR Modules
Choose the interface type SDR, enter the module name and click the Customize to open the configuration tab.
Figure 12-123 shows the Configuration Tab for the SDR module in IPexpress. Table 12-46 lists the various configurations options available for SDR modules.12-135
LatticeECP3 High-Speed
I/O Interface
Figure 12-123. SDR Configuration Tab
Table 12-46. SDR Configuration Parameters
GUI Option Description Values Default
Interface Type Type of interface (transmit or receive) Transmit, Receive Receive
I/O Standard for this Interface I/O standard to be used for the interface.
Transmit and Receive:
LVCMOS25, LVCMOS18, LVCMOS15,
LVCMOS12, LVCMOS33,
LVCMOS33D,
LVDS25, BLVDS25, MLVDS,
LVPECL33,
HSTL18_I, HSTL18_II, HSTL18D_I,
HSTL18D_II, HSTL15_I, HSTL15D_I,
SSTL33_I, SSTL33_II, SSTL33D_I,
SSTL33D_II, SSTL25_I, SSTL25_II,
SSTL25D_I, SSTL25D_II, SSTL18_I,
SSTL18_II, SSTL18D_I, SSTL18D_II,
SSTL15, SSTL15D, PCI33, LVTTL33
Transmit only:
RSDS, MINILVDS, PPLVDS,
LVDS25E, RSDSE
LVCMOS25
Bus Width for this Interface Bus size for the interface. 1 - 256 16
Clock Frequency for this Interface
Speed at which the interface will run. 1 - 200 200
Bandwidth (Calculated) Calculated from the clock frequency
entered.
(Calculated) (Calculated)
Interface Interface selected based on previous
entries.
Transmit: GOREG_TX.SCLK
Receive: GIREG_RX.SCLK (default)
GIREG_RX.S
CLK
Clock Inversion Option to invert the clock input to the
I/O register.
DISABLED, ENABLED DISABLED12-136
LatticeECP3 High-Speed
I/O Interface
Building DDR Generic Modules
Choose interface type DDR_GENERIC, enter the module name and click Customize to open the configuration tab.
Figure 12-124. “DDR_Generic” Selected in Main IPexpress Window
When you click Customize, DDR modules have a Pre-Configuration tab and a Configuration tab. The Pre-Configuration tab allows users to enter information about the type of interface to be built. Based on the entries in the Preconfiguration tab, the Configuration tab will be populated with the best interface selection. The user can also, if necessary, override the selection made for the interface in the Configuration tab and customize the interface based on
design requirements.
Figure 12-22 shows the Pre-Configuration tab for DDR generic interfaces. Table 12-47 lists the various parameters
in the tab.
Data Path Delay Data input can be optionally delayed
using the DELAY block.
Bypass, Dynamic1
, User Defined Bypass
FDEL for User Defined If Delay type selected above is user
defined, delay values can be entered
with this parameter.
0 to 152
0
1. When Delay type Dynamic is selected, the 16-step delay values must be controlled from the user’s design.
2. A FDEL is a fine-delay value that is additive. The delay value for a FDEL can be found in the LatticeECP3 Family Data Sheet.
Table 12-46. SDR Configuration Parameters (Continued)
GUI Option Description Values Default12-137
LatticeECP3 High-Speed
I/O Interface
Figure 12-125. DDR Generic Pre-Configuration Tab
Table 12-47. Pre-Configuration Tab Settings
GUI Option Description Values
Interface Type (Transmit or Receive) Type of interface (Receive or Transmit) Transmit, Receive
I/O Standard for this Interface I/O Standard used for the interface Transmit and Receive:
LVCMOS25,LVCMOS18, LVCMOS15,
LVCMOS12, LVCMOS33, LVCMOS33D,
LVDS25, BLVDS25, MLVDS, LVPECL33,
HSTL18_I, HSTL18_II, HSTL18D_I,
HSTL18D_II, HSTL15_I, HSTL15D_I,
SSTL33_I, SSTL33_II, SSTL33D_I,
SSTL33D_II, SSTL25_I, SSTL25_II,
SSTL25D_I, SSTL25D_II, SSTL18_I,
SSTL18_II, SSTL18D_I, SSTL18D_II,
SSTL15, SSTL15D, PCI33, LVTTL33
Transmit only:
RSDS, MINILVDS, PPLVDS,
LVDS25E, RSDSE
Number of interfaces on a side of a
device
Number of interfaces to be implemented
per side. This is used primarily for narrow bus width interfaces (<10). Otherwise it is recommended to leave this at
1.
1 to 8
Bus Width for this Interface Bus width for each interface. If the number of interfaces per side is >1 then the
bus width per interface is limited to 10.
If number of interfaces per side is >1
and if using differential I/O standards
then bus width is limited to 5.
1-256
Clock Frequency for this Interface Interface speed 2 - 500 MHz
Interface Bandwidth (Calculated) Bandwidth is calculated from the clock
frequency.
Calculated12-138
LatticeECP3 High-Speed
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Based on the selections made in the Pre-Configuration Tab, the Configuration Tab is populated with the selections.
Figure 12-126 shows the Configuration Tab for the selections made in the Pre-Configuration Tab.
Figure 12-126. DDR Generic Configuration Tab
The checkbox at the top of this tab indicates that the interface is selected based on entries in the Pre-Configuration
tab. The user can choose to change these values by disabling this entry. Note that IPexpress chooses the most
suitable interface based on selections made in the Pre-Configuration tab.
Table 12-48 lists the various parameters in the Configuration tab.
Clock to Data Relationship at the Pins Relationship between clock and data. Edge-to-Edge, Centered, Dynamic Data
Phase Alignment Required1
,Dynamic Clock
Phase Alignment Required
1. Dynamic Phase Alignment is only available for x2 interfaces (i.e, when the clock frequency is higher than 200 MHz).
Table 12-47. Pre-Configuration Tab Settings (Continued)
GUI Option Description Values12-139
LatticeECP3 High-Speed
I/O Interface
Table 12-48. Configuration Tab Settings
GUI Option Description Values Default Value
Interface Selection Based on
Pre-configuration
Indicates interface is selected based on selection made in the Pre-configuration tab. Disabling
this checkbox allows users to make changes if
needed.
ENABLED, DISABLED ENABLED
Interface Type Type of interface (receive or transmit) Transmit, Receive Receive
I/O Standard I/O standard used for the interface All the ones listed in the
Pre-configuration tab LVCMOS25
Clock Frequency Speed of the interface 2 to 500 MHz 200 MHz
Gearing Ratio DDR register gearing ratio (1x or 2x) 1x, 2x 1x
Alignment Clock to data alignment
Edge-to-Edge,
Centered,
Dynamic Data Phase
Alignment Required,
Dynamic Clock Phase
Alignment Required
Edge-to-Edge
Number of Interfaces
Number of interfaces to be implemented per
side. This is primarily used for narrow bus width
interfaces (<10), otherwise it is recommended
to leave this at 1.
1 to 8 1
Bus Width
Bus width for each interface. If the number of
interfaces per side is >1 then the bus width per
interface is limited to 10. If the number of interfaces per side is >1 and if using differential I/O
standards then the bus width is limited to 5.
1 to 256 10
Phase Adjust Module used for phase shifting input clock. TRDLLB/DLLDELB,
PLL1
TRDLLB/DLLDELB
Clock Divider Module used for generation of SCLK from
ECLK. CLKDIVB, TRDLLB2
CLKDIVB
Interface Shows list of all valid high-speed interfaces for a
given configuration.
See Table 12-5 for
interfaces available for
a given configuration.
GDDRX1_RX.SCLK.
Aligned (EA devices);
GDDRX1_RX.ECLK.
Aligned (E devices)
Data Path Delay
Data input can be optionally delayed using the
DELAY block. Value is selected based on Interface Type.
Bypass, Fixed,
Dynamic3
Fixed
Number of DQS Groups Enabled when a DQS interface is selected in
the Interface selection. 1 to 8
Number of DQ:
DQS Group1 to DQS Group8
This option can be used to change the number
of DQ assigned to each DQS lane. Each DQS
lane can support up to 10 DQ.
1 to 10
1. Only available when using GDDRX2_RX.ECLK.Aligned interface.
2. Only available when using GDDRX2_RX.SCLK Aligned interface.
3. When Dynamic Delay is selected, the 16-step delay values must be controlled from the user’s design.12-140
LatticeECP3 High-Speed
I/O Interface
Table 12-49 shows how the interfaces are selected by IPexpress based on the selections made in the Pre-Configuration tab.
Table 12-49. IPexpress Interface Selection
The implementation for several of the interfaces described above differs between the “E” and “EA” devices. Refer to
the High-Speed DDR Interface Details section to see implementation details for “E” and “EA” devices.
The Data Delay setting for each interface is predetermined and cannot be changed by the user. User can only control Data Delay values when using a dynamic interface.
Note: Some modules generated by IPexpress have a SCLK and ECLK output port. If present, this port must be
used to drive logic outside the interface driven by the same signal. In these modules, the input buffer for the clock is
inside the IPexpress module and therefore cannot be used to drive other logic in the top level.
Building DDR Memory Interfaces
The IPexpress tool is used to configure and generate the DDR, DDR2 and DDR3 memory interfaces.
To see the detailed block diagram for each interface generated by IPexpress see the Memory Read Implementation
and Memory Write Implementation sections. IPexpress can be opened from the Tools menu in Project Navigator.
All the DDR modules are located under Architecture Modules > IO. DDR_MEM is used to generate DDR memory
interfaces.
Device
Selected Interface Type
Gearing
Ratio1
Alignment
Number of
Interfaces Interface
EA Receive 1x Edge-to-Edge 1 GDDRX1_RX.SCLK.Aligned
EA Receive 1x Centered 1 GDDRX1_RX.SCLK.Centered
E Receive 1x Edge-to-Edge 1 GDDRX1_RX.ECLK.Aligned
E Receive 1x Centered 1 GDDRX1_RX.ECLK.Centered
E, EA Receive 1x Edge-to-Edge >1 GDDRX1_RX.DQS.Aligned
E, EA Receive 1x Centered >1 GDDRX1_RX.DQS.Centered
E, EA Receive 2x Edge-to-Edge 1 GDDRX2_RX.ECLK.Aligned
E, EA Receive 2x Centered 1 GDDRX2_RX.ECLK.Centered
E, EA Receive 2x Edge-to-Edge >1 GDDRX2_RX.DQS.Aligned
E, EA Receive 2x Centered >1 GDDRX2_RX.DQS.Centered
EA
Receive 2x Dynamic 1
GDDRX2_RX.ECLK.Dynamic (Default)
EA GDDRX2_RX.DQS.Dynamic2
EA GDDRX2_RX.PLL.Dynamic2
E, EA Transmit 1x Centered 1 GDDRX1_TX.SCLK.Centered
E, EA Transmit 1x Edge-to-Edge 1 GDDRX1_TX.SCLK.Aligned
E, EA Transmit 1x Centered >1 GDDRX1_TX.DQS.Centered
EA Transmit 2x Edge-to-Edge 1 GDDRX2_TX.Aligned
EA Transmit 2x Centered >1 GDDRX2_TX.DQSDLL.Centered
EA Transmit 2x Centered <1 GDDRX2_TX.PLL.Centered
1. Gearing Ratio of 1x is selected for clock frequencies less than 200MHz. Gearing ratio of 2x is selected for frequencies above 200 MHz.
2. These interfaces can only be selected in the Configuration Tab.12-141
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I/O Interface
Figure 12-127. “DDR_MEM” Selected in Main IPexpress Window
Figure 12-127 shows the IPexpress Main Window. To generate a DDR memory interface, select DDR_MEM,
assign a module name and click on Customize to see the Configuration tab. Figure 12-128 shows the Configuration tab for the DDR_MEM interface. You can choose to implement the DDR1_MEM, DDR2_MEM or DDR3_MEM
interface.12-142
LatticeECP3 High-Speed
I/O Interface
Figure 12-128. Configuration Tab for DDR_MEM
Table 12-50 describes the various settings shown in the Configuration tab above.
Table 12-50. Configuration Tab Settings for DDR_MEM
GUI Option Description Range Default Value
Interface DDR memory interface type DDR, DDR2, DDR3 DDR2
I/O Buffer Configuration I/O type configuration for DDR pins
SSTL25_I, SSTL25_II
SSTL18_I, SSTL18_II,
SSTL15
DDR – SSTL25_I
DDR2 – SSTL18_I
DDR3 – SSTL15
Number of DQS Interface width (1 DQS per 8 bits of data) 1 to 9 4
DQS Group1 to DQS Group8 Number of DQ per DQS pin 1 to 8 8
DQS Buffer Configuration for
DDR2 DQS buffer type Single-ended,
Differential
DDR – Single-ended
DDR2 – Single-ended
DDR3 – Differential
Clock/Address/Command Clock/address/command interface will be
generated when this option is checked ENABLED, DISABLED DISABLED
Data Mask Data mask signal will be generated when
this option is checked ENABLED, DISABLED DISABLED
Lock/Jitter Sensitivity Lock Sensitivity attribute for DQSDLL1
HIGH, LOW HIGH12-143
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I/O Interface
If the user chooses to generate the Clock/Address/Command signals using IPexpress, then the settings in the
Clock/Address/Command Tab are active and can be set up as required. Figure 12-129 shows the
Clock/Address/Command Tab in the IPexpress for DDR2 Memory.
Figure 12-129. Clock/Address/Command Tab in the IPexpress for DDR_MEM
Table 12-51 lists the values that can be used for the Clock/Address/Command settings.
DDR Memory Frequency DDR Memory Interface Frequency
DDR – 87.5 MHz,
100 MHz, 133.33 MHz,
166.67 MHz, 200 MHz
DDR2 – 125 MHz,
200 MHz, 266.67 MHz
DDR3 – 150 MHz,
200 Mhz, 300 MHz,
400 MHz
DDR – 200 MHz
DDR2 – 200 MHz
DDR3 – 400 MHz
ISI Calibration
ISI calibration is available for the DDR3
interface to adjust for inter-symbol inference adjustment per DQS group
BYPASS, DEL1, DEL2,
DEL3, DEL4, DEL5,
DEL6, DEL7
BYPASS
1. It is recommended to set Lock Sensitivity to HIGH for DDR Memory Frequency higher than 133 MHz.
GUI Option Description Range Default Value12-144
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Table 12-51. Clock/Address/Command Settings for DDR_MEM
GUI Option Range Default Value
Number of Clocks 1, 2, 4 1
Number of Clock Enables 1, 2, 4 1
Address Width
DDR: 12-14
DDR2: 13-16
DDR3: 13-16
DDR: 13
DDR2: 13
DDR3: 14
Bank Address Width
DDR: 2
DDR2: 2, 3
DDR3: 3
DDR: 2
DDR2: 2
DDR3: 3
Number of ODT
DDR: N/A
DDR2: 1, 2, 4
DDR3: 1, 2, 4
DDR: N/A
DDR2: 1
DDR3: 1
Number of Chip Selects
DDR: 1, 2, 4, 8
DDR2: 1, 2, 4
DDR3: 1, 2, 4
DDR: 1
DDR2: 1
DDR3: 1
www.latticesemi.com 15-1 tn1169_02.4
May 2013 Technical Note TN1169
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
Configuration is the process of loading or programming a design into volatile memory of an SRAM-based FPGA.
This is accomplished via a bitstream file, representing the logical states, that is loaded into the FPGA internal configuration SRAM memory. The functional operation of the device after programming is determined by these internal
configuration RAM settings. The SRAM cells must be loaded with configuration data each time the device powers
up.
The configuration memory in LatticeECP3™ FPGAs is built using volatile SRAM; therefore, an external non-volatile
configuration memory is required to maintain the configuration data when the power is removed. This non-volatile
memory supplies the configuration data to the LatticeECP3 when it powers up or anytime the device needs to be
updated.
To support multiple configuration options the LatticeECP3 supports the Lattice sysCONFIG™ interface as well as
the dedicated JTAG port. The available configuration options, or modes, are listed in Table 15-1.
Table 15-1. Supported Configuration Modes
This technical note covers all of the configuration options available for LatticeECP3.
The LatticeECP3 configuration RAM can be loaded in a number of different modes. In these configuration modes,
the FPGA can act as a master, a peripheral to a CPU, or a slave of other system devices. It also supports in-system
configuration via the JTAG port.
The decision about which configuration mode to use is a system design concern. There are many methods for configuring the FPGA utilizing four basic schemes.
• Master: As a master, the FPGA is the source of the clock, and accesses an external PROM or EPROM storage
device through a serial connection, with no additional timing or control signals used. This scheme includes Serial
Programming Interface (SPI) that supports a seamless connection for programming using industry-standard
external Flash-based memory devices.
• Slave: In slave mode the FPGA receives bit-serial or byte-wide data and a clock from an external data and timing
source, either from a microprocessor, or from the lead device in an FPGA-daisy chain. As a slave device, the
clock used to configure the FPGA is generated externally and provided to the CCLK input.
Interface Port Description
sysCONFIG
SPI Serial Peripheral Interface to single or multiple FPGA devices.
SPIm Serial Peripheral Interface to single Flash memory devices with partitioned memory.
SSPI Configure and readback by standard SPI Master driver or devices.
SCM Slave Serial Mode for daisy chain configuration.
SPCM Slave 8-bit parallel CPU-like programming interface.
JTAG JTAG (IEEE 1149.1 and
IEEE 1532 compliant) Standard 4-pin JTAG interface.
LatticeECP3 sysCONFIG
Usage Guide15-2
LatticeECP3 sysCONFIG Usage Guide
• JTAG: The device can be configured through the JTAG port. The JTAG port is always on and available regardless of the configuration mode selected.
The system designer should determine the requirements for configuration very early in the design. Many factors
must be considered when deciding which configuration mode is best suited for the design. The flexible features
for configuration can provide a seamless design to the system.
General Configuration Flow
The LatticeECP3 enters Configuration mode when one of three things happens: power is applied to the device, the
PROGRAMN pin is driven low, or a JTAG or SSPI Refresh instruction is issued. Upon entering Configuration mode
the INITN pin and the DONE pin are driven low to indicate that the device is initializing (i.e. getting ready to receive
configuration data).
Once initialization is complete, the INITN pin will be driven high. The low-to-high transition of the INITN pin causes
the CFG pins to be sampled, telling the LatticeECP3 which port it will configure from. The LatticeECP3 then begins
reading data from the selected port and starts looking for the preamble header (BDB3 hex for unencrypted bitstreams, and BAB3 for encrypted bitstreams). All data after the preamble is valid configuration data.
When the LatticeECP3 has finished reading all of the configuration data, and assuming there have been no errors,
the DONE pin goes high and the LatticeECP3 enters user mode. In other words, the device begins to function
according to your design.
Note that the LatticeECP3 may also be programmed via JTAG. When programming via JTAG, the INITN and DONE
signals have no meaning, because JTAG, per the IEEE standard, takes complete control of all device I/Os. It is recommended that the PROGRAMN input be held high when using the JTAG port to configure the FPGA. This prevents the FPGA SRAM memory from being cleared when the JTAG programming cycle is complete.
The following sections define each configuration pin, each configuration mode, and all of the configuration options
for the LatticeECP3.
Configuration Pins
The LatticeECP3 supports two types of configuration pins, dedicated and dual-purpose. The dedicated pins are
used exclusively for configuration; the dual-purpose pins, when configuration is complete, are available as extra I/O
pins. If a dual-purpose pin is to be used both for configuration and as a general purpose I/O (GPIO) the following
conditions must be met:
• The I/O type must remain the same. For example, if the pin is a 3.3V CMOS pin (LVCMOS33) during configuration, it must remain a 3.3V CMOS pin as a GPIO.
• You must select the correct CONFIG_MODE setting and set the PERSISTENT attribute to OFF. Doing so permits the dual-purpose sysCONFIG pins to be used as GPIO when configuration completes. These settings can
be found in the ispLEVER®
Design Planner or Spreadsheet View in Lattice Diamond™ design software. See
Table 15-3 for more information.
• You are responsible for insuring that no internal or external logic will interfere with the control signals required by
configuration mode you have selected.
The dual-purpose configuration pins are controlled using HDL source file attributes, or with the ispLEVER or Diamond Preference Editor. You can read about how to apply HDL preferences in TN1177, LatticeECP3 sysIO Usage
Guide.
The LatticeECP3 also supports JTAG for configuration, transparent read back, and JTAG testing. The following
sections describe the function of the various sysCONFIG and JTAG pins. Table 15-2 is provided for reference.15-3
LatticeECP3 sysCONFIG Usage Guide
Table 15-2. LatticeECP3 Configuration Pins
Pin Name I/O Type Pin Type
Configuration Mode
SPI SPIm SSPI1
SCM1
SPCM1
JTAG
CFG[2:0] Input, weak pull-up Dedicated =000 =010 =001 =101 =111
PROGRAMN Input, weak pull-up Dedicated ALL
INITN Bi-directional open drain5
Dedicated ALL
DONE Bi-directional open drain5
Dedicated ALL
CCLK Input Dedicated Slave mode, determined by the CFG0 setting =1
MCLK Bi-directional, weak pull-up Dual-Purpose Master mode, determined by the CFG0 setting =0
D0/SPIFASTN2
Bi-directional2
Dual-Purpose SPIFASTN SPIFASTN D0
D12, 3 Bi-directional2
Dual-Purpose D1
D22, 3 Bi-Directional2
Dual-Purpose D2
D3/SI2, 3 Bi-directional2
Dual-Purpose SI D3
D4/SO2, 3 Bi-directional2
Dual-Purpose SO D4
D52
Bi-directional2
Dual-Purpose D5
D62, 3 Bi-directional2
Dual-Purpose D6
D7/SPID02, 3 Bi-directional2
Dual-Purpose SPID0 SPID0 Note 4 D7
CSN/SN Bi-directional, weak pull-up Dual-Purpose SN CSN
CS1N/HOLDN Bi-directional, weak pull-up Dual-Purpose HOLDN3
CS1N
WRITEN Active low control input pin Dual-Purpose WRITEN
BUSY/SISPI Bi-directional, weak pull-up Dual-Purpose SISPI SSIPI Note 4 BUSY
DI/CSSPI0N Bi-directional, weak pull-up6
Dual-Purpose CSSPI0N CSSPI0N Note 4 DI
DOUT/CSON Bi-directional, weak pull-up Dual-Purpose DOUT DOUT DOUT DOUT/
CSON
1. SSPI = Slave SPI, SCM = Serial Configuration Mode, SPCM = Slave Parallel Configuration Mode.
2. D[0:7] pins have no pull-up during power-up and configuration in all programming modes. This allows you to use large pull-up or pulldown resistors to pre-set those pins to a certain state while powering up your systems.
3. Weak pull-ups consist of a current source of 30µA to 150µA. The pull-ups for sysCONFIG dedicated and dual-purpose pins track
VCCIO8. The pull-ups for TDI, TDO, and TMS track VCCJ.
4. This pin is used for programming the SPI Flash boot PROM.
5. Optional weak pull-up resistor available.
6. Requires external pull-up to VCCIO8.15-4
LatticeECP3 sysCONFIG Usage Guide
Configuration Process and Flow
Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration
and wake-up.
Figure 15-1. Configuration Flow
Power-up Sequence
In order for the LatticeECP3 to operate, power must be applied to the device. During a short period of time, as the
voltages applied to the system rise, the FPGA will have an indeterminate state. Other devices in the system will
also be in an indeterminate state.
As power continues to ramp, a Power On Reset (POR) circuit inside the FPGA becomes active. The POR circuit,
once active, makes sure the external I/O pins are in a high-impedance state. It also monitors the VCCcore, VCCaux,
and the VCCIO8 input rails. The POR circuit waits for the following conditions:
• VCCcore > 0.8V
• VCCaux > 2.7V
• VCCIO8 > 0.8V (Supply used for configuration I/O)
Power not stable PROGRAMN must not be asserted low
until after all power rails have reached
stable operation.
PROGRAMN must not make a falling edge
transition during the time the FPGA is in the
Initialization state. PROGRAMN must be asserted
for a minimum low period of tPRGMRJ in order for
it to be recognized by the FPGA. Failure to meet this
requirement can cause the device to become
non-operational, requiring power to be cycled.
PROGRAMN or
INITN=Low
INITN=Low
User Mode
Configuration
Write Progamming Data
ERROR
Power Up
VCCore > 0.8V
VCCaux > 2.7V
VCCIO8 > 0.8V (Supply used for
configuration I/O)
INITN and DONE
Driven Low
Initialization
Wake Up
GSR, GWDIS, GOE, DONE
DONE Released
INITN Released
CFG[2:0] Sampled
Device refresh
Device refresh
Device refresh
Device refresh:
• PROGRAMN falling edge
• IEEE 1532 refresh command
• Power cycle
PROGRAMN de-asserted and tICFG expired
All configuration data received15-5
LatticeECP3 sysCONFIG Usage Guide
When these conditions are met the POR circuit releases an internal reset strobe, allowing the device to begin its
initialization process. The FPGA samples the CFG[2:0] input pins to determine if a master or a slave mode configuration is selected. The FPGA uses this information to determine the tICFG initialization period. The next step is to
assert INITN active low, and to drive DONE low. When INITN and DONE are asserted low the device moves to the
initialization state, as shown in Figure 15-1.
The PROGRAMN input must not be asserted low as power is applied to the FPGA. Nor should it be allowed to transition from high to low at any time that INITN is in the initialization state.
Figure 15-2. Configuration from Power-On-Reset Timing
Initialization
The LatticeECP3 enters the memory initialization phase immediately after the Power On Reset circuit drives the
INITN and DONE status pins low. The purpose of the initialization state is to clear all of the SRAM memory inside
the FPGA.
The FPGA remains in the initialization state until all of the following conditions are met:
• The tICFG time period has elapsed
• The PROGRAMN pin is deasserted
• The INITN pin is no longer asserted low by an external master
The dedicated INITN pin provides two functions during the initialization phase. The first is to indicate the FPGA is
currently clearing its configuration SRAM. The second is to act as an input preventing the transition from the initialization state to the configuration state.
During the tICFG time period the FPGA is clearing the configuration SRAM. When the LatticeECP3 is part of a chain
of devices each device will have different tICFG initialization times. The FPGA with the slowest tICFG parameter can
prevent other devices in the chain from starting to configure. Premature release of the INITN in a multi-device chain
may cause configuration of one or more chained devices to fail to configure intermittently.
The active-low, open-drain initialization signal INITN must be pulled high by an external resistor when initialization
is complete. To synchronize the configuration of multiple FPGAs, one or more INITN pins should be wire-ANDed. If
one or more FPGAs or an external device holds INITN low, the FPGA remains in the initialization state.
Loading the Configuration Memory
The rising edge of the INITN pin causes the FPGA to enter the configuration state. The FPGA is able to accept the
configuration bitstream created by the ispLEVER and Diamond development tools.
If the FPGA CFG[2:0] input pins have placed it in a master configuration mode it will begin fetching data from an
external non-volatile memory.
If the FPGA CFG[2:0] input pins have placed it in a slave configuration mode, the FPGA waits for configuration data
to be presented to it on each CCLK rising edge.
DONE
INITN
V
CC/VCCAUX/
V
CCIO0
t
ICFG
Valid15-6
LatticeECP3 sysCONFIG Usage Guide
During the time the FPGA receives its configuration data the INITN control pin takes on its final function. INITN is
used to indicate an error exists in the configuration data. When INITN is active high configuration is proceeding
without issue. If INITN is asserted low, an error has occurred and the FPGA will not operate.
Wake-up
Wake-up is the transition from configuration mode to functional mode. Wake-up starts when the device has correctly received all of its configuration data. When all configuration data is received, the FPGA asserts an internal
DONE strobe. The assertion of the internal DONE causes a Wake Up state machine to run that sequences four
controls. The four control strobes are:
• External DONE
• Global Write Disable (GWDISn)
• Global Output Enable (GOE)
• Global Set/Reset (GSR)
External DONE is a bi-directional, open-drain I/O. The FPGA releases the open-drain DONE pin at the programmed wake-up phase. If an external agent is holding the external DONE pin low, the wake-up process of the
LatticeECP3 does not proceed. Only after the external DONE is active high do the final wake-up phases complete.
Once the final wake-up phases are complete, the FPGA enters user mode.
The Global Output Enable, when it is asserted, permits the FPGA’s I/O to exit a high-impedance state and take on
their programmed output function. The FPGA inputs are always active. However, they are typically prevented from
performing any action on the FPGA logic by the assertion of the Global Set/Reset (GSR).
The Global Set/Reset is an internal strobe that, when asserted, causes all I/O/LUT flip-flops, distributed RAM output flip-flops, and Embedded Block RAM output flip-flops that have the GSR enabled attribute to be set/cleared per
their HDL definition.
The Global Write Disable is a control that overrides the write enable strobe for all RAM logic inside the FPGA. The
inputs on the FPGA are always active, as mentioned in the Global Output Enable section. Keeping GWDIS
asserted prevents accidental corruption of the instantiated RAM resources inside the FPGA.
Clearing the Configuration Memory and Re-initialization
Several methods are available to clear the internal configuration memory of the LatticeECP3 device. The first is
mentioned earlier when the device powers up (see the “Power-up Sequence” section of this document). A second
method is to toggle the PROGRAMN pin. Also, JTAG can reinitialize the memory through an ISC Refresh command. SSPI can also initiate a reconfiguration with the Refresh command.
The other methods available are:
• Assertion of the PROGRAMn dedicated input
• Sending the ISC Refresh command using a configuration port (JTAG, or Slave SPI)
Invoking one of these methods causes the LatticeECP3 to drive INITN and DONE low. The FPGA enters the initialization state described above.
FPGA Configuration Control Pin Definitions
The LatticeECP3 FPGA provides a set of I/O pins that can be used to load a configuration bitstream into the
device. Some of these I/O are single purpose and are always available to perform configuration operations. Those
configuration pins that are not dedicated can be configured for your use after the FPGA has entered user mode.
This section describes what each I/O is, how it functions, and how to reclaim some for your own use.15-7
LatticeECP3 sysCONFIG Usage Guide
Configuration Pin Management
The dual-purpose sysCONFIG pins described in the Table 15-2 are dedicated configuration pins during the device
configuration process. The PERSISTENT attribute is used to determine whether the dual-purpose sysCONFIG
pins remain sysCONFIG pins during normal operation. The LatticeECP3 provides three settings for the PERSISTENT feature. The available options are shown in Table 15-3.
Table 15-3. PERSISTENT Setting and Affected Pins
You can use the SLAVE_PARALLEL or the Slave SPI configuration port to access some of the resources connected to the FPGA. Accessing the FPGA resources requires special command sequences, which are described in
other documents.
Dedicated Control Pins
The LatticeECP3 makes a set of dedicated control pins available to allow you to select the way you want to configure the FPGA. The following sub-sections describe the LatticeECP3 dedicated sysCONFIG pins. These pins are
powered by VCCIO8.
While the device is under IEEE 1149.1 or 1532 JTAG control the dedicated programming pins have no meaning.
This is because a boundary scan cell will control each pin, per JTAG 1149.1, rather than normal internal logic.
JTAG Pins
The JTAG pins are standard IEEE 1149.1 TAP (Test Access Port) pins. The JTAG pins are dedicated pins and are
always accessible when the LatticeECP3 device is powered up. While the device is under 1149.1 or 1532 JTAG
control the dedicated programming pins INITN, DONE, and CCLK have no meaning. This is because a boundary
scan cell will control each pin, per the IEEE standard, rather than normal internal logic. If the device is being
accessed by JTAG then PROGRAMN will still be an active input even in JTAG mode.
These pins are powered by VCCJ.
TDO
The Test Data Output pin is used to shift out serial test instructions and data. When TDO is not being driven by the
internal circuitry, the pin will be in a high impedance state. This pin should be wired to TDO of the JTAG connector,
or to TDI of a downstream device in a JTAG chain. An internal pull-up resistor on the TDO pin is provided. The
internal resistor is pulled up to VCCJ.
TDI
The Test Data Input pin is used to shift in serial test instructions and data. This pin should be wired to TDI of the
JTAG connector, or to TDO of an upstream device in a JTAG chain. An internal pull-up resistor on the TDI pin is
provided. The internal resistor is pulled up to VCCJ.
TMS
The Test Mode Select pin controls test operations on the TAP controller. On the falling edge of TCK, depending on
the state of TMS, a transition will be made in the TAP controller state machine. An internal pull-up resistor on the
TMS pin is provided. The internal resistor is pulled up to VCCJ.
Persistent Setting Pins
OFF All dual-purpose configuration pins are available as GPIO
SLAVE_PARALLEL D [0:7], CSN, CS1N, WRITEN, BUSY, CSON, MCLK1
SSPI SI, SO, SN, HOLDN, SISPI, SPID0, SPID1, CSSPIN and CSSPI1N
1. These pins are not used by the Slave Parallel logic, but they are reserved by the Slave Parallel logic. They are not
available for use as GPIO.15-8
LatticeECP3 sysCONFIG Usage Guide
TCK
The test clock pin, TCK, provides the clock to run the TAP controller state machine, which loads and unloads the
JTAG data and instruction registers. TCK can be stopped in either the high or low state and can be clocked at frequencies up to that indicated in the LatticeECP3 Family Data Sheet. The TCK pin supports hysterisis; the typical
hysterisis is approximately 100mV when VCCJ = 3.3V. The TCK pin does not have a pull-up. A pull-down resistor
between TCK and ground on the PCB of 4.7 K is recommended to avoid inadvertent clocking of the TAP controller
as VCC ramps up.
Optional TRST
Test Reset, TRST, is not supported on the LatticeECP3.
V
CCJ
Having a separate JTAG VCC (VCCJ) pin lets you apply a voltage level to the JTAG port that is independent from the
rest of the device. Valid voltage levels are 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V, but the voltage used must match the
other voltages in the JTAG chain. VCCJ must be connected even if JTAG is not used.
Please see In-System Programming Design Guidelines for ispJTAG Devices for further JTAG chain information.
Configuration and JTAG Pin Physical Description
All of the sysCONFIG dedicated and dual-purpose pins are part of Bank 8. Bank 8 VCCIO determines the output
voltage level of these pins, input thresholds are determined by the I/O Type selected in the ispLEVER Design Planner (default is 3.3V LVCMOS) and Diamond Spreadsheet View.
JTAG voltage levels and thresholds are determined by the VCCJ pin, allowing the LatticeECP3 to accommodate
JTAG chain voltages from 1.2V to 3.3V.
CFG[2:0]
The Configuration Mode pins, CFG[2:0], are used to inform the FPGA how you want to configure the device. The
actions performed by the remaining configuration pins depend on the state of the CFG[2:0] inputs. The CFG[2:0]
input pins have weak internal pull-up resistors, that guarantee a valid configuration mode is selected should they be
left unconnected. Lattice recommends the CFG pins be connected with independent pull-up/pull-down resistors. It
is also recommended that these pins not be directly connected to the power or ground planes.
The CFG[2:0] pins are sampled at two different points in the configuration process. The first sample point is when
the Power-On Reset state machine starts up. The POR sample point determines if the FPGA to be configured in
master or slave mode. The tICFG time period changes based on this information.
The second time the CFG pins are sampled is at the rising edge of the INITN pin. This sample is used to make the
final configuration selection. Table 15-4 describes the configuration mode that is active based on the CFG input
pins. The state on the CFG pins at any other time is not important. The state pins can be changed freely, which
may be useful for selecting a new configuration mode.
Table 15-4. LatticeECP3 Configuration Pins1
Configuration Mode Clock CFG [2] CFG [1] CFG [0]
SPI Master (Single) MCLK 0 0 0
SPI Master (Multiple) 0 1 0
Slave SPI CCLK
001
XXX
SCM CCLK 1 0 1
SPCM CCLK 1 1 1
1. JTAG is always available for IEEE 1149.1 and 1532 support.15-9
LatticeECP3 sysCONFIG Usage Guide
PROGRAMN
The PROGRAMn is a dedicated input that is used to configure the FPGA. The PROGRAMn pin is a falling edge
sensitive, and has an internal weak pull-up. When a falling edge occurs, the FPGA exits user mode and starts a
device configuration sequence at the Initialization phase, as described earlier.
Proper operation of the LatticeECP3 FPGA depends on the PROGRAMn pin. The following conditions must be
met:
• The PROGRAMn pin must not be asserted until after all of the supply rails are stable. This can be achieved by
either placing an external pullup resistor and tying it to the VCCIO8 voltage, or permitting the FPGA's internal
pull-up resistor to pull the input high.
• The PROGRAMn pin must make a high to low transition in order to cause the FPGA to enter configuration mode.
This is not necessary when first powering the FPGA, as the FPGA will enter configuration mode after the internal
Power On Reset circuit releases the internal reset.
• The PROGRAMn pin must not be allowed to transition from high to low at any time INITn is active (i.e. low) as a
result of being in the Initialization state.
• PROGRAMn must meet the minimum active pulse width tPRGMRJ.
• PROGRAMn remains an active input even when the JTAG bus is being used to program the FPGA. The PROGRAMn pin should not be asserted during JTAG programming sequences.
Failing to follow these guidelines may prevent the FPGA from operating.
PROGRAMn must be de-asseted in order for the FPGA to exit the Initialization state.
Figure 15-3. Configuration from PROGRAMN Timing
INITN
The INITn pin is a bidirectional open-drain control pin. It has the following functions:
• After power is applied, or after a PROGRAMn assertion it goes low to indicate the FPGA configuration cells are
being erased. The low time assertion is specified with the tICFG parameter.
• After the tICFG time period has elapsed the INITn pin is deasserted (i.e. is active high) to indicate the FPGA is
ready for its configuration bits. In master mode the FPGA starts loading bits from an attached non-volatile memory. In slave mode the FPGA waits for the bits to arrive over the interface selected by the CFG[2:0] input pins.
The rising edge of the INITn samples the CFG[2:0] inputs, allowing the FPGA to determine how it is to be configured.
• INITn can be asserted low by an external agent before the tICFG time period has elapsed in order to prevent the
FPGA from reading configuration bits. This is useful when there are multiple FPGA's chained together. The
FPGA with the longest tICFG time can hold all other FPGA's in the chain from starting to get data until it is ready
itself.
DONE
CFG[2:0] 1
INITN
PROGRAMN
t
PRGMRJ
t
ICFG
t
DPPINIT
t
DPPDONE
1. The CFG pins are normally static (hard wired).
Valid
t
DINIT
t
SUCFG t
HCFG
t
SUCFG t
HCFG
Valid15-10
LatticeECP3 sysCONFIG Usage Guide
• The last function provided by INITn is to signal an error during the time configuration data is being read. Once
t
ICFG has elapsed, and the INITn pin has gone high, any INITn assertion signals the FPGA has detected an error
during configuration.
The following conditions will cause INITN to become active, indicating the Initialization state is active:
• Power has just been applied
• PROGRAMN falling edge occurred
• The IEEE 1532 Refresh command has been sent using a slave configuration port (JTAG, SSPI, etc.).
If the INITN pin is asserted due to an error condition, the error can be cleared by correcting the configuration bitstream and forcing the FPGA into the Initialization state.
Figure 15-4. Configuration Error Notification
DONE
The DONE pin is a dedicated bi-directional open drain with a weak pull-up that signals the FPGA is in User mode.
DONE is first able to indicate entry into User mode only after the internal DONE pin is asserted. The intenal DONE
signal defines the beginning of the FPGA Wake-Up state.
The DONE output pin is controlled by the DONE_EX configuration parameter. The default state of this pin is OFF.
The default mode causes the LatticeECP3 to start immediately after the internal DONE bit is asserted. The FPGA
does not stall waiting for the DONE pin to be asserted high.
The FPGA can be held from entering User mode indefinitely by having an external agent keep the DONE pin
asserted low. In order to use DONE to stall entering user mode the DONE_EX configuration preference must be
set ON. A common reason for keeping DONE driven low is to allow multiple FPGAs to be completely configured.
As each FPGA reaches the DONE state, it is ready to begin operation. The last FPGA to configure can cause all
FPGAs to start in unison.
It is critical that DONE be asserted low when the LatticeECP3 is in a chain of FPGAs. The LatticeECP3 continues
to pass configuration clock pulses to FPGAs attached downstream as long as DONE is de-assserted. Any FPGA
permitted to assert DONE and enter User mode will only pass a few hundred more configuration clock cycles.
Downstream FPGAs will never complete their configuration process if this occurs.
The DONE pin drives low in tandem with the INITN pin when the FPGA enters Initialization mode. As described
earlier, this condition happens when power is applied, PROGRAMN is asserted, or an IEEE 1532 Refresh command is received via a slave configuration port.
Sampling the DONE pin is a good way for an external device to tell if the FPGA has finished configuration. However, when using IEEE 1532 JTAG to configure SRAM the DONE pin is driven by a boundary scan cell, so the state
of the DONE pin has no meaning during IEEE 1532 JTAG configuration (once configuration is complete, DONE
takes on the behavior defined by the DONE_EX configuration parameter).
Configuration Clock (CCLK)
The CCLK is a dedicated input-only whose purpose is to provide a reference clock for the FPGA when one of the
slave configuration modes is selected by the CFG[2:0] inputs.
DONE
INITN
PROGRAMN
t
INITL
Configuration
Error
Configuration
Started15-11
LatticeECP3 sysCONFIG Usage Guide
Please refer to the LatticeECP3 AC Timing information in the LatticeECP3 Family Data Sheet for information about
maximum clock rates, and data setup and hold parameters.
When the LatticeECP3 is in a chain of FPGAs it is necessary to continue to drive CCLK until all of the FPGAs have
received their configuration data. It is recommended the CCLK continue to be toggled until the DONE signal is
active.
Dual-Purpose sysCONFIG Pins
The Dual-Purpose sysCONFIG pins, depending on the configuration mode selected by the CFG[2:0] input pins,
provide special configuration functions during the Configuration phase of the device wake-up process. The dualpurpose pins can be recovered for your use once the FPGA enters User mode. Successful recovery of the dualpurpose pins relies on following the guidelines described in the “Configuration Pins” section of this document.
The dual-purpose configuration pins are located in the same I/O bank as the dedicated configuration pins. The
configuration pins in the LatticeECP3 are powered by the VCCIO8 voltage rail.
Master Clock (MCLK)
The MCLK provides a reference clock for synchronous non-volatile memories attached to the FPGA. MCLK is only
active when the FPGA CFG[2:0] inputs select a master configuration mode. See Table 15-4 for a full description of
the available configuration modes selectable by the CFG[2:0] input pins. MCLK acts as a general purpose I/O if the
FPGA is in a slave configuration mode.
The LatticeECP3 generates MCLK from an internal oscillator. The initial output frequency of the MCLK is approximately 2.5MHz. The MCLK frequency can be altered using the MCCLK_FREQ parameter. You can select the
MCCLK_FREQ using the Diamond Spreadsheet View. For a complete list of the supported MCLK frequencies, see
Table 15-8.
During the initial stages of device configuration the frequency value specified using MCCLK_FREQ is loaded into
the FPGA. Once the FPGA accepts the new MCLK_FREQ value the MCLK output begins driving the selected frequency. Make certain that when selecting the MCLK_FREQ that you do not exceed the frequency specification of
your configuration memory, or of your PCB. Lattice recommends reviewing the LatticeECP3 AC specifications in
the LatticeECP3 Family Data Sheet when making MCLK_FREQ decisions.
The LatticeECP3 provides the ability to be configured from a bitstream that is encrypted. There are additional
requirements on the MCCLK_FREQ selection that you must adhere to when configuring the LatticeECP3 with an
encrypted bitstream. These conditions are discussed in the “Bitstream Encryption/Decryption Flow” section of this
document.
DI/CSSPI0N
The DI/CSSPI0N configuration pin provides one of two functions depending on the FPGA’s configuration mode.
When the FPGA is in Serial Configuration Mode the pin is set to DI (Data Input) mode. When the FPGA is in SPI
Master or SPI Master Multiboot mode, the pin is set to CSSPI0N (Chip Select SPI 0).
When the FPGA is in Serial Configuration Mode the DI pin receives incoming configuration data. See the Serial
Configuration Mode section of this document for more information.
When the FPGA is in SPI Master or SPI Master Multiboot mode the CSSPI0N is the chip select strobe to the
attached SPI memory that contains the FPGA’s configuration bits. The FPGA asserts this pin active low during the
Configuration phase of the wake-up process.
An external pull-up resistor is required on CSSPI0N in SPI and SPIm modes of operation. Some SPI memory
devices require the CSn input to rise in tandem with their input voltage. The internal pull-up on CSSPI0N does not
become active until the FPGA determines all input voltage rails are stable. This does not meet the requirements of
some SPI memory vendors.15-12
LatticeECP3 sysCONFIG Usage Guide
DOUT/CSON
The DOUT/CSON configuration pin is used only when placing the LatticeECP3 into a chain of FPGAs requiring
configuration.
The DOUT/CSON pin is an output from the LatticeECP3 and is only active when the FPGA is connected to another
FPGA in a daisy chain.
When in a daisy chain, the pin may act as either a data output (DOUT) or a chip select (CSON). The behavior is
described in detail in the Configuring Multiple FPGA Devices section of this document.
For serial and parallel configuration modes, when Bypass mode is selected, this pin becomes DOUT (see
Figure 15-10). When the device is fully configured a Bypass instruction in the bitstream is executed and the data on
DI, or D[0:7] in the case of a parallel configuration mode, will then be routed to the DOUT pin. This allows data to
be passed, serially, to the next device. In a parallel configuration mode D0 will be shifted out first followed by D1,
D2, and so on.
Daisy chaining the Parallel devices can be implemented with the Flowthrough attribute. This attribute allows the
CSON pin to be driven when the done bit is set and configuration of the first part is complete. The CSON of the first
part will drive the CSN of the second part.
You will find this attribute in the ispLEVER Generate Bitstream Data property under Chain Mode or in the Diamond
Bitstream options window. See Appendix B for more information on setting these options in Diamond.
The DOUT/CSON drives out a high on power-up and will continue to do so until the execution of the Bypass
instruction within the bitstream, or until the I/O Type is changed by your code.
CSN/SN
The CSN/SN is a bidirectional pin that is active in Slave Parallel Configuration mode, or in Slave SPI mode. The pin
is a chip select that gates the incoming configuration data.
Detailed information about using the chip select pin can be found in the “Slave Parallel Mode (SPCM)” and “Slave
SPI (SSPI)” configuration sections of this document.
CS1N/HOLDN
The CS1N/HOLDN configuration pin is active only in Slave Parallel Configuration mode or in Slave SPI mode.
When the LatticeECP3 is in a Slave Parallel Configuration mode the pin acts as a chip select that works in conjunction with CSN. Information detailing the interaction of these two pins is described in the Parallel Configuration mode
section of this document.
The configuration pin takes on the HOLDN function when the LatticeECP3 is in Slave SPI Configuration mode.
Assertion of the HOLDN input causes the FPGA to ignore the SPI SCLK. Details for using HOLDN are provided in
the Slave SPI Configuration section.
When CSN or CS1N is high, the D[0:7], and BUSY pins are tri-stated. CSN and CS1N are interchangeable when
controlling the D[0:7], and BUSY pins.
WRITEN
The WRITEN configuration pin is an input pin that is active in Slave Parallel Configuration mode. It is a write enable
strobe that controls the direction data flows on the D[0:7] data bus pins. When WRITEN is asserted active low the
FPGA D[0:7] pins are tri-stated to allow an external bus master to write data into the FPGA.
BUSY/SISPI
The BUSY/SISPI configuration pin is active in Slave Parallel Configuration mode and in SPI Master modes.
When the LatticeECP3 is in a Slave Parallel Configuration mode, the pin is a tri-state output pin. When the FPGA
parallel bus is active due to the assertion of CSN/CS1N the BUSY pin indicates the FPGA’s ability to accept a byte
of configuration data. The FPGA is able to accept another configuration byte when this output is driven low.15-13
LatticeECP3 sysCONFIG Usage Guide
When the LatticeECP3 is in SPI Master mode the pin is connected to the data input of the SPI PROM that contains
the configuration data. SISPI is an output used by the LatticeECP3 to transmit commands to the SPI PROM.
D[0]/SPIFASTN
The D[0]/SPIFASTN configuration pin is available in Slave Parallel Configuration and SPI Master configuration
modes.
In Slave Parallel Configuration mode the D[0] pin is the most-significant data bit in the combined D[0:7] parallel
data bus.
In SPI Master configuration modes it becomes the SPIFASTN input. The input is sampled at the rising edge of the
INITN output.
The SPIFASTN selects the Read Opcode transmitted to the SPI PROM. When SPIFASTN is deasserted (i.e.
driven to Vih) the FPGA requests a Read Operation using the 03 hex Read Opcode. When SPIFASTN is asserted
(i.e. driven to Vil) the FPGA requests a Read Operation using the 0B hex Read Opcode. A SPI PROM that accepts
the 0B Read Opcode is able to operate at higher serial clock rates. Consult the SPI memory vendor’s data sheet for
the exact capabilities of the SPI memory device.
Do not leave this input floating when a SPI Master mode is selected.
In parallel mode this pin is D[0] and operates in the same way as D[1:6] below. Taken together D[0:7] form the parallel data bus, D[0] is the most significant bit in the byte. The D[0:7] data bus are open-drain I/O without a pullup
resistor during the time that power is applied to the FPGA. They also remain in this state until the FPGA is fully configured. When the FPGA is configured the D[0:7] I/O take on the attributes defined in your HDL source code, or
using the Spreadsheet View preference editor.
As with D[1:6], if SRAM (configuration memory) needs to be accessed using the parallel pins while the part is in
user mode (the DONE pin is high) then the PERSISTENT control cell must be set to preserve this pin as D[0]. Note
that SRAM may only be read using JTAG or Slave Parallel mode.
D[1], D[2], D[5] and D[6]
These configuration pins are only available in Slave Parallel Configuration mode and are intermediary data bits for
the parallel data bus made up of bits D[0:7].
Remember that D[0] is the most-significant data bit and D[7] is the least-significant.
D[3]/SI
The D[3]/SI configuration pin is only available in Slave Parallel Configuration or in Slave SPI Configuration mode.
When the LatticeECP3 is in Slave Parallel Configuration mode the pin acts as D[3].
In Slave SPI Configuration mode the pin acts as the Serial Input pin for data supplied by a SPI Master Controller.
D[4]/SO
The D[4]/SO configuration pin is only available in Slave Parallel Configuration or in Slave SPI Configuraiton mode.
When the LatticeECP3 is in Slave Parallel Configuration mode the pin acts as D[4].
In Slave SPI Configuration mode the pin acts as the Serial Output pin for data transmitted from the FPGA back to
the SPI Master Controller.
D[7]/SPID0
The D[7]/SPID0 configuration pin is only available in Slave Parallel Configuration or in Master SPI Configuration
mode.
When the LatticeECP3 is in Slave Parallel Configuration mode the pin acts as D[7]. This is the least-significant-bit
of the D[0:7] data bus.15-14
LatticeECP3 sysCONFIG Usage Guide
In Master SPI Configuration mode the pin acts as the SPI Data Input pin receiving data from an attached SPI
PROM.
Configuration Modes
LatticeECP3 devices support many different configuration modes, utilizing either serial or parallel data paths. The
configuration method used by the LatticeECP3 is selected by driving the CFG[2:0] input pins. The CFG[2:0] input
pins are sampled at the falling edge of INITN to determine if the part is in a master or a slave configuration mode.
The pins are sampled a second time at the rising edge of INITN to determine the specific configuration mode.
The LatticeECP3 starts the configuration process in one of three ways:
• Initial application of power
• Assertion of the PROGRAMN input pin
• Reception of a REFRESH command form a configuration port (JTAG, Slave SPI, Slave Parallel)
SPI Interface
The Serial Peripheral Interface (SPI) is a four-wire de facto bus standard used to transmit and receive serial data.
The LatticeECP3 can use a SPI data bus to retrieve its configuration data from most SPI ROMs.
The amount of ROM storage required depends on the number of Look Up Tables (LUTs) in the LatticeECP3 device
you have selected. Figure 15-5 shows how many bits of configuration data are required for each member of the
LatticeECP3 family.
Table 15-5. Maximum Configuration Bits – SPI Flash Mode Bitstream File1
The estimated configuration time can be calculated by dividing the bitstream size (in bits) from Table 15-5 by the
configuration clock (MCLK or CCLK) frequency. The MCLK frequency is modified using the Global Preferences tab
within the Diamond Spreadsheet View or in the ispLEVER Design Planner.
The LatticeECP3 provides the following three SPI configuration modes:
• SPI Master (SPI)
• SPI Master Multiboot (SPIm)
• Slave SPI (SSPI)
SPI Master Mode
The simplest SPI configuration consists of one SPI Serial Flash connected to one LatticeECP3, as shown in
Figure 15-5. In this configuration the LatticeECP3 is the master of the SPI bus. The FPGA controls the chip select
and the MCLK, and receives the configuration data on the SPID0 input.
During FPGA configuration the SISPI output sends a command sequence to reset the SPI PROM’s internal
address pointer. The SPIFASTN informs the FPGA which SPI Read Command to send to the SPI PROM. When
Device Bitstream Size1
SPI Flash
Dual Boot SPI
Flash Units
ECP3-17 4.5 8 16 Mb
ECP3-35 8.2 16 32 Mb
ECP3-70 22.5 32 64 Mb
ECP3-95 22.5 32 64 Mb
ECP3-150 35.7 64 128 Mb
1. The Bitstream Size column is the maximum number of bits the FPGA may require. This number
takes into account the pre-initialization of all Embedded Block RAMs.15-15
LatticeECP3 sysCONFIG Usage Guide
the SPIFASTN input is driven high, the FPGA sends a 03 Hex Read Opcode. When it is asserted active low, the
FPGA sends a 0B Hex Read Opcode to the SPI PROM.
As mentioned in the section describing the MCLK behavior, the configuration clock frequency can be altered. The
MCLK frequency must not exceed the clock input frequency of the SPI PROM.
Figure 15-5. One FPGA, One SPI Serial Flash
In order to configure properly, the LatticeECP3 must transmit at least 128 clock pulses before it receives the preamble code (BDB3 hex for unencrypted bitstreams, and BAB3 for encrypted bitstreams). It is required that the data in
the SPI PROM be padded to account for these extra clocks. The bitstream generation tool automatically adds the
necessary padding information.
SPI Master Multiboot (SPIm) Mode
SPI Master Multiboot mode is an enhancement to the SPI Master boot mode. The SPI memory is attached to the
FPGA in exactly the same way as SPI Master mode. SPIm enables you to partition the SPI PROM to store two configuration bitstreams. The FPGA will attempt to configure from the Primary image, and if the FPGA fails to configure from the primary image it tries to load a fail-safe Golden bitstream. Figure 15-6 shows the concept from a high
level.
Lattice FPGA
SPI Mode
MCLK
DI/CSSPI0N
BUSY/SISPI
D7/SPID0 DOUT
CFG1
CFG0
SPIFASTN
SPI Serial
Flash
Q
C
CFG2
D0/SPIFASTN
PROGRAMN
DONE
Note: The board-level pull-down on MCLK should have a 1-3 Kohms
resistance. This counteracts the weak internal pull-up on MCLK and
prevents an unintentional rising edge at power-up.
D
/CS15-16
LatticeECP3 sysCONFIG Usage Guide
Figure 15-6. SPIm Mode for Dual-Boot Capability
Internally, SPIm mode adds logic to detect a configuration failure and the ability to reattempt configuration from a
different address within the SPI Flash device. While SPI mode treats the SPI Flash device as a single block of storage starting at address zero, SPIm mode allows segmentation of the Flash device for the golden bitstream.
In SPIm mode, the primary bitstream is stored at address offset 0x010000. When configuring, the LatticeECP3
device automatically reads the data beginning at this address first. If after 2*14 clocks the device still does not
receive the pre-amble code or a bitstream error is encountered after receiving the pre-amble code, the configuration logic resets and loads the data located at address offset 0xFFFF00.
The LatticeECP3 uses a 24-bit addressing scheme to access the SPI memory array. The amount of storage
remaining in the SPI starting at address 0xFFFF00 is only 256 bytes. This is not enough to store a complete
LatticeECP3 configuration bitstream. The LatticeECP3 configuration bitstream is stored elsewhere in the SPI
PROM. The data retrieved by the FPGA at address 0xFFFF00 is an instruction pointing to the start of the failsafe
configuration data.
An example of the SPI Flash memory organization for SPIm mode is shown in Table 15-6.
LatticeECP3
MCLK
DI/CSSPI0N
BUSY/SISPI
D7/SPID0
CFG1
CFG0
SPIFASTN
CFG2
D0/SPIFASTN
PROGRAMN
DONE
SPI Serial Flash
Golden Image
Primary Image15-17
LatticeECP3 sysCONFIG Usage Guide
Table 15-6. SPIm Mode Data Map1, 2, 3
Slave SPI (SSPI)
The LatticeECP3 can be configured by a SPI Master controller. Using the CFG[2:0] inputs to select SSPI configuration mode the FPGA becomes a SPI Slave device, receiving data from a SPI Master controller. The FPGA can be
accessed using Mode 0 and Mode 3 bus transactions.
The slave SPI interface allows for a the following functions to be performed:
• Configuration of the FPGA
• Readback of the FPGA configuration bitstream
• Forcing the device to REFRESH as if PROGRAMN were asserted
• Read/Write access to a SPI PROM attached to the SPI Master configuration pins
• Clearing the FPGA configuration
• Reading the FPGA ID code
• Reading the FPGA User ID code
Block (512Kb) SPI Flash Address Contents
0 0x000000 Unused
1
2
3
.
.
.
18
0x010000
0x020000
0x030000
.
.
.
0x120000
Primary Bitstream
32
33
34
.
.
.
49
0x200000
0x210000
0x220000
.
.
.
0x310000
Golden Bitstream
N
0xFF0000
0xFFFF00 Jump instruction to 0x200000
1. The bitstream sizes shown are examples. Actual sizes and address boundaries vary with device
density.
2. After the golden bitstream is written into the SPI Flash device, the top half of the SPI Flash can be
write-protected to secure the golden bitstream from alterations.
3. When the SPI Flash device reaches the address 0xFFFFFF, it rolls over to address 0x000000. If
the last page is un-programmed, the device can read the jump instruction programmed on address
0x000000 effectively implementing a multiple patterns support for board development or debugging need.15-18
LatticeECP3 sysCONFIG Usage Guide
Table 15-7. Slave SPI Pins
The chip select pin (SN) is a chip select input to the FPGA. The LatticeECP3 responds on the falling and rising
edges of the SN input. SN is not a level sensitive input. When the SN falling edge occurs the FPGA is ready to
accept commands from a SPI Master Controller. A rising edge on the SN input resets the internal state machine
and tri-states the SO output pin. The only exception to this is when the FPGA has received a SPI_PROGRAM command. This command can only be interrupted by the assertion of the PROGRAMN input.
The HOLDN pin is provided to allow a SPI Master Controller to pause transactions on the Slave SPI port. When
HOLDN is asserted low the FPGA tri-states the SO output and ignores the SCLK input. This allows the SPI Master
Controller to interact with another SPI device and then resume transactions to the LatticeECP3. Encrypted bitstreams must be sent without interruption. You are not permitted to assert HOLDN or deassert SN once an
encrypted bitstream transmission has begun.
Figure 15-7. Slave SPI Example
Figure 15-7 illustrates how an on-board CPU can be connected to the LatticeECP3 using the Slave SPI programming interface. The CPU can fetch configuration data from the attached SPI PROM. The CPU is not required to deassert the SN input to the FPGA. When the CPU asserts the CS1N to access the SPI PROM the FPGA HOLDN is
asserted causing it to ignore SCLK transitions. The HOLDN input can not be asserted when transferring an
encrypted bitstream.
Full details on using Slave SPI mode on the LatticeECP3 are provided in TN1222, LatticeECP3 Slave SPI Port
User’s Guide.
Slave Serial Configuration Mode (SCM)
Slave Serial Configuration mode provides a simple, low pin count method for configuring one or more FPGAs. Data
is presented to the FPGA on the Data Input pin DI at every CCLK rising edge.
Signal Name Type Description Function
SN Active Low Input Chip Select
A falling edge on SN causes the FPGA to enter Command
State. A rising edge on SN causes the FPGA to enter Reset
State.
SI Input Serial Input Data Serial input for command and data.
SO Tri-state Output Serial Output Data Serial output data to the SPI Master.
SCK Clock Input Serial Data Clock Serial input clock for command and data.
HOLDN Asynchronous Active
Low Input Put the Device on Hold
Tri-state SO and set the device into the suspension state by
ignoring the CCLK. Do not assert when loading encrypted
bitstreams.
CS1N
CS0N
DI
DO
CLK SPI Port
CPU FPGA
SSP
Interface
HOLDN
SN
SI
SO
SCK
SPI
Flash
CCLK
CFG0
CFG1 SSPI
Mode
Slave SPI Port
CFG215-19
LatticeECP3 sysCONFIG Usage Guide
Figure 15-8. Slave Serial Block Diagram
The bitstream data generated by Lattice Diamond is formatted so that it is ready to shift into the FPGA. Left shift
the data out of the file in order for it to be correctly received by the FPGA.
The FPGA synchronizes itself on either a 0xBDB3 or 0xBAB3 code word. It is critical that any data presented on
DIN not be recognized as one of these two synchronization words early. To guarantee proper recognition of the
synchronization word it is recommended that the synchronization word always be preceded by a minimum of 128
‘1’ bits. Presenting any other bitstream data, Programmer generated header information for example, risks the
being misinterpreted due to bit slippage.
Slave Serial Configuration Mode can be used to configure a chain of FPGAs. Details about configuring a chain of
devices is discussed in “Combining Configuration Modes” on page 36 of this document.
Slave Parallel Mode (SPCM)
The LatticeECP3 can be configured using Slave Parallel Configuration Mode. Slave Parallel permits an external
master to configure the FPGA using an 8-bit synchronous SRAM bus interface. Slave Parallel Configuration Mode
is a flexible method for configuring one or more FPGAs. It is also the fastest mode available for configuring the
LatticeECP3.
The slave parallel interface allows for a multitude of different functions to be performed:
• Configuration of the FPGA
• Readback of the FPGA configuration bitstream
• Reading the device CRC
• Reading the programming status register
• Reading the FPGA ID code
• Reading the FPGA User ID code
To next
FPGA
(optional)
FPGA
CFG2
CFG1
CFG0
DI DO
CCLK
DONE
INITN
CPU\Serial
Interface
DOUT
CLK
IN1
IN215-20
LatticeECP3 sysCONFIG Usage Guide
Figure 15-9. Slave Parallel Block Diagram
Figure 15-9 shows the typical Slave Parallel Configuration Mode usage. Configuration data can be written to the
LatticeECP3 immediately following the INITN rising edge. The LatticeECP3 data bus bit ordering is denoted using
a big-endian nomenclature. This means that D0 receives the MSBit, and D7 receives the LSBit. One byte of data
can be sent to the FPGA on each rising CCLK edge as long as CSN, CS1N, and WRITEN are asserted. When the
LatticeECP3 is the only device being configured the FPGA can receive configuration data at the full CCLK rate.
The master device is not required to monitor the BUSY pin in this situation, because the configuration bitstreams
are padded to avoid BUSY assertion.
Sending an encrypted bitstream must be done atomically, i.e. without interruption. The bus master is not permitted
to pause the transfer of an encrypted bitstream by deasserting the CSN or CS1N inputs. The CCLK pin can be
stretched or stopped if desired, but the CSN and CS1N pins must remain asserted.
Slave Parallel mode can also be to read status registers and the configuration bitstream. In order for the Slave Parallel port to be used to perform read operations the FPGA must have the PERSISTENT preference set to
SLAVE_PARALLEL mode. See the Configuration Pin Management section of this document for more information.
Figure 15-10. Parallel Port Write Timing Diagram
JTAG Mode (IEEE 1149.1 and IEEE 1532)
The LatticeECP3 provides an IEEE 1532 compliant interface. The IEEE 1532 specification, a superset of the IEEE
1149.1 JTAG specification, describes a standard methodology for configuring programmable logic devices. The
FPGA
CFG2
CFG1
CFG0
WRITEN
CCLK
DONE
INITN
CPU/Parallel
Interface
WRn
CLK
IN1
IN2
CSN CSN
CS1N
D[7:0] D[0:7]
IN3 BUSY
D[0:7]
INITN
PROGRAMN
WRITEN
CCLK
BUSY
Current Command
Note: The BUSY pin cannot go high while both CS1N and CSN are low. The second BUSY high shown
is OK since CS1N or CSN was low previously.
Write Write
BUSY is tristated
with pull-up.
Next Command
CSN
CS1N
………15-21
LatticeECP3 sysCONFIG Usage Guide
LatticeECP3 only requires the four IEEE 1149.1 control signals (TCK, TMS, TDI, and TDO) in order to initiate and
complete programming operations. The LatticeECP3 JTAG port is always available for use, regardless of the configuration mode selected.
Programming the LatticeECP3 using the JTAG port is typically accomplished in one of several ways:
• You can use Lattice Diamond Programmer software in combination with a Lattice download cable
• You can use Automatic Test Equipment that can read Serial Vector Format (SVF), In-System Configuration (ISC),
STAPL/JAM, or ATE vector files
• You can use an embedded microprocessor to run Lattice's ispVM Embedded configuration software
Lattice Diamond Programmer’s Fast Program
The Lattice Diamond development tools translate your design into a bitstream containing an optional header, mandatory preamble, and the device configuration data. The configuration data includes its own preamble, fuse data,
and finally a trailing CRC. This basic structure is used for all of the configuration modes supported by the
LatticeECP3. The IEEE 1532 mode adds some additional operations to the device configuration process.
Prior to sending the configuration data the FPGA’s Boundary Scan I/O Cells are placed in a high-impedance state,
and the FPGA’s configuration memory is cleared. Because the I/O are tri-stated the DONE and INITn output signals do not provide status information while the configuration data is being written to the FPGA. The JTAG configuration mode uses an internal status register to confirm the FPGA DONE and INITn status signals indicate the
device configured correctly. After the internal DONE and INITn controls are confirmed, the Boundary Scan I/O
Cells are re-enabled, and all I/O take on the function assigned to them.
The JTAG interface, because it can control the Boundary Scan I/O Cells, can also be used to configure the
LatticeECP3 without putting the I/O into a high-impedance state. During device configuration the I/O cells can be
locked in their last known active state. This mode of operation is called TransFR Programming. A full description of
how to use TransFR is provided in TN1087, Minimizing System Interruption During Configuration Using TransFR
Technology.
JTAG Configuration Data Read and Save
The JTAG interface can be used to read the configuration data stored in the FPGA’s SRAM array. There are two
modes available to retrieve the data, foreground mode or background mode.
Foreground readback is accessed using IEEE 1532 mode. When using this method the JTAG Boundary Scan Cells
are placed in a high-impedance state, and the configuration data read. Once the configuration data is retrieved the
Boundary Scan Cells are restored, and the FPGA returns to normal operation.
The Background Read and Save operation allows you to read the content of the device while the device remains in
operation. All I/O, as well at the non-JTAG configuration pins, continue normal operation during the Background
Read and Save operation. You must not violate the following conditions when using the Background Read and
Save function:
• The Soft Error Detection system must not be running. De-assert the SEDENABLE pin to prevent the SED circuit
from interfering with the Background Read and Save operation. It is recommended that you wait at least one full
SEDSTART to SEDDONE time period after the deassertion of the SEDENABLE to make sure the SED circuit
has discontinued operation. Alternately monitor the SEDINPROG output, and wait for it to de-assert.
• Write operations to distributed RAM blocks must be suspended. Write operations that occur at the same time the
SRAM cell is being read are non-deterministic. It is possible for the SRAM to receive, or retain, incorrect RAM
data.
Regardless of which read and save mode is used the configuration data will not include the EBR or the distributed
RAM contents. Distributed RAM contents will always be return zeroes.15-22
LatticeECP3 sysCONFIG Usage Guide
Boundary Scan and Boundary Scan Description Language (BSDL) Files
The LatticeECP3, as mentioned previously, provides an IEEE 1149.1 compliant JTAG interface. The JTAG interface
can be controlled by Automatic Test Equipment (ATE) that uses Boundary Scan Description Language (BSDL)
files. Lattice makes BSDL files available for the LatticeECP3 on the Lattice Semiconductor website.
The boundary scan ring covers all of the I/O pins, as well as the dedicated and dual-purpose sysCONFIG pins.
Note that PROGRAMN, CCLK, and the CFG pins are observe only (BC4, JTAG read-only) boundary scan cells.
When performing JTAG 1149.1 EXTEST instructions, the SERDES CML termination for both Tx and Rx is set to 50
ohm pull-ups. This allows the high-speed channels to operate properly if DC data is sent or received. During JTAG
EXTEST, the termination will be set to 50 ohm. This overrides the termination resistance programmed into the
SERDES logic.
Bitstream Generation Software Usage
This section describes the settings for bitstream generation performed by the Diamond software program that generates a bitstream. These options are controlled through the Global Preferences of the Diamond Spreadsheet View
and the property settings of the Bit Generation Software tool. To set the Global Preferences and properties in Diamond, see Appendix B. By setting the proper parameter in the Lattice design software the selected configuration
options are set in the generated bitstream. As the bitstream is loaded into the device the selected configuration
options take effect. These options are described in the following sections.
Bit Generation takes a fully routed Physical Design (.ncd file) as input and produces a configuration bitstream (bit
images). The bitstream file contains all of the configuration information from the Physical Design defining the internal logic and interconnections of the FPGA, as well as device-specific information from other files associated with
the target device. The data in the bitstream can then be downloaded directly into the FPGA memory cells or used
to generate files for PROM programming (using a separate program, ispVM). Please refer to the ispVM documentation for details on creating PROM image files.
Configuration Options
Several configuration options are available for each configuration mode. These options are controlled from the
Spreadsheet View for each Strategy. They include the following items.
• When daisy chaining multiple FPGA devices an overflow option is provided for serial and parallel configuration
modes
• When using SPI or SPIm mode, the master clock frequency can be set
• A security bit can be set to prevent SRAM readback
• The Persistent option can be set
• Configuration pins can be protected
• DONE pin options can be selected
By setting the proper parameter in the Lattice design software the selected configuration options are set in the generated bitstream. As the bitstream is loaded into the device the selected configuration options take effect. These
options are described in the following sections.
Master Clock
If the CFG pins indicate an SPI or SPIm mode, the MCLK pin will become an output with a default frequency, or
one selected when you added preferences to your design. The default Master Clock Frequency is 2.5 MHz. For a
complete list of the supported Master Clock frequencies, please see the LatticeECP3 Family Data Sheet. When
using the LatticeECP3 devices, the available frequencies are restricted, as shown in the data sheet.
You can change the Master Clock frequency by setting the MCCLK_FREQ global preference in the Diamond
Spreadsheet view tool. During configuration one of the first pieces of information loaded is the MCCLK_FREQ 15-23
LatticeECP3 sysCONFIG Usage Guide
parameter. When this parameter is loaded the master clock frequency changes to the selected value without glitching. Care should be exercised not to exceed the frequency specification of the slave devices or the signal integrity
capabilities of the PCB layout.
Configuration time is computed by dividing the maximum number of configuration bits, as given in Table 15-5
above, by the Master Clock frequency.
Table 15-8. Selectable Master Clock (MCCLK) Frequencies During Configuration (Nominal)
Security Bit
Setting the CONFIG_SECURE option to ON prevents readback of the SRAM from JTAG or the sysCONFIG pins.
When CONFIG_SECURE is set to ON the only operations available are erase and write. The security control bit is
updated as the last operation of SRAM configuration. If a secured device is read it will output all ones.
For LatticeECP3 devices the CONFIG_SECURE option is accessed via the Design Planner in ispLEVER. To set
this option in Diamond, see Appendix B. The default is OFF.
Persistent Option
The PERSISTENT option is used to direct the place and route tools about how it can use the sysCONFIG pins. By
default the PERSISTENT option is turned OFF, which allows the place and route tools to reclaim most of the configuration pins as general purpose input/output. Changing the PERSISTENT configuration option from its default
state prevents the place and route tools from either the Slave SPI or the Slave Parallel configuration ports from
becoming general purpose I/O.
Enabling the dedicated sysCONFIG ports is useful for performing additional capabilities while the FPGA is in user
mode.
You use the SLAVE_PARALLEL setting when:
• You want to read back the FPGAs SRAM contents. The LatticeECP3 provides a command set and access protocol that allows the configuration SRAM to be read from the FPGA. The Slave Parallel port can read all of the configuration data, except the EBR and the distributed RAM contents.
• You have a LatticeECP3, configured as a SPI Master, in series of FPGAs in a device chain. The SPI Master
FPGA must keep the MCLK pin active in order to provide a configuration clock for all of the chained FPGAs.
Table 15-3 describes the configuration pins that are preserved. The MCLK output is only preserved Slave Parallel configuration mode. If PERSISTENT is set to OFF, or SSPI the MCLK output tri-states after the lead FPGA is
configured, which prevents chained FPGAs from configuring.
Use the SSPI PERSISTENT setting when:
• You want to access a SPI PROM attached to the SPI Master configuration pins. You can attach a SPI memory
controller and using a custom command you can perform erase, program, and verify sequences on the SPI
PROM while the FPGA is in operation. Table 15-3 describes the configuration pins that are preserved. InformaMCCLK (MHz) MCCLK (MHz)
2.51
10
13
4.3 152
5.4 20
6.9 26
8.1
9.2 333
1. Software default MCLK frequency. Hardware default is 3.1MHz.
2. Maximum MCCLK with encryption enabled.
3. Maximum MCCLK without encryption15-24
LatticeECP3 sysCONFIG Usage Guide
tion about the Slave SPI transactions are published in TN1222 LatticeECP3 Slave SPI Port User's Guide. You
can also use the SSPI Embedded device programming software provided by Lattice.
Configuration Mode
The CONFIG_MODE option tells the software which configuration port the hardware is using to program the
FPGA. Setting this parameter permits the design software to check to make sure configuration port pins are not
oversubscribed. The oversubscription is only flagged as a warning. In some cases it is acceptable to oversubscribe
the configuration port. For example it is acceptable to have the FPGA in SPI Master configuration mode and use
the SISPI, SPID0,a nd SPICS pins as general purpose I/O.
The CONFIG_MODE is also used to make sure encrypted bitstreams are generated correctly. To guarantee correct
operation of encrypted bitstreams you need to set the CONFIG_MODE parameter.
DONE EX
During configuration the DONE output pin is low. Once configuration is complete, indicated by assertion of an internal DONE bit, the device wake-up sequence takes place. The external DONE pin is able to operate in one of two
modes during the wake up sequence. The default behavior, set when DONE_EX = OFF, is for it to actively drive to
VIL. When DONE_EX is set ON, the external DONE pin becomes an open-drain output. The LatticeECP3 wake up
sequence will stall until the external DONE pin is pulled high. Set DONE_EX to ON when you want to synchronize
the when a chain of FPGAs wakes up. Make sure you place a pullup resistor that is able to drive all of the DONE
pins.
Device Wake-Up
When configuration is complete the device will wake up in a predictable fashion. Wake-Up occurs after successful
configuration, without errors, and provides the transition from Configuration Mode to User Mode. The Wake-Up process begins when the internal DONE bit is set.
Table 15-9 provides a list of the Wake-Up sequences supported by the LatticeECP3; Figure 15-11 shows the
Wake-Up timing. The default Wake-Up sequence works fine for most single device applications.
Table 15-9. Wake-Up Options
Sequence Phase T0 Phase T1 Phase T2 Phase T3
1 DONE GOE, GWDIS, GSR
2 DONE GOE, GWDIS, GSR
3 DONE GOE, GWDIS, GSR
4
1 DONE GOE GWDIS, GSR
5 DONE GOE GWDIS, GSR
6 DONE GOE GWDIS GSR
7 DONE GOE GSR GWDIS
8 DONE GOE, GWDIS, GSR
9 DONE GOE, GWDIS, GSR
10 DONE GWDIS, GSR GOE
11 DONE GOE GWDIS, GSR
12 DONE GOE, GWDIS, GSR
13 GOE, GWDIS, GSR DONE
14 GOE DONE GWDIS, GSR
15 GOE, GWDIS DONE GSR
16 GWDIS DONE GOE, GSR
17 GWDIS, GSR DONE GOE
18 GOE, GSR DONE GWDIS
19 GOE, GWDIS, GSR DONE15-25
LatticeECP3 sysCONFIG Usage Guide
Figure 15-11. Wake-Up Timing Diagram
Synchronizing Wake-Up
The LatticeECP3 is, in most cases, configured using one of the master configuration modes. The FPGA, when in
master configuration mode, is driving the configuration clock. The configuration clock is used for stepping through
the final four Wake-Up states described in the previous section.
The LatticeECP3 has the ability to use an external clock source to control the final state transitions in the Wake_Up
process. There are three possible sources for the clock. The JTAG TCK, the Slave Configuration CCLK, and a general-purpose input.
Start_Up Clock Selection
Once the FPGA is configured, it enters the start-up state, which is the transition between the configuration and
operational states. This sequence is synchronized to a clock source, which defaults to CCLK when a slave configuration mode is used, or TCK when JTAG is used.
If desired, a user-defined clock source can be used instead of CCLK/TCK. You need to specify this clock signal,
and instantiate the STRTUP library element in your design. The example shown below shows the proper syntax of
instantiating the STRTUP library element.
20 GOE, GWDIS, GSR DONE
212 GOE GWDIS, GSR DONE
22 GOE, GWDIS GSR DONE
23 GWDIS GOE, GSR DONE
24 GWDIS, GSR GOE DONE
25 GOE, GSR GWDIS DONE
1. Default when DONE_EX=ON.
2. Default when DONE_EX=OFF.
Table 15-9. Wake-Up Options (Continued)
Sequence Phase T0 Phase T1 Phase T2 Phase T3
CCLK/TCK
DONE BIT
GLOBAL OUTPUT ENABLE
GLOBAL SET/RESET
GLOBAL WRITE DISABLE
DONE PIN
T0 T1 T2 T315-26
LatticeECP3 sysCONFIG Usage Guide
Verilog
STRTUP u1 (.UCLK()) /* synthesis syn_noprune=1 */;
VHDL
component STRTUP
port(STRTUP: in STD_ULOGIC );
end component;
attribute syn_noprune: boolean ;
attribute syn_noprune of STRTUP: component is true;
begin
u1: STRTUP port map (UCLK =>);
Synchronous to Internal DONE Bit
If the LatticeECP3 is the only device in the configuration chain, or the last device in the chain, DONE_EX should be
set to the default value (OFF). The Wake-Up process will be initiated by setting of the internal DONE bit on successful completion of configuration.
Synchronous to External DONE Pin
The DONE pin can be used to synchronize Wake-Up to other devices in a configuration chain. If DONE_EX (see
the DONE EX section above) is ON then the DONE pin is an open-drain bi-directional pin. If an external device
drives the DONE pin low then the Wake-Up sequence stalls until DONE is active high. Once the DONE pin goes
high the device will follow the selected WAKE_UP sequence.
In a configuration chain, a chain of devices configuring from one source (such as Figure 15-17), it is usually desirable, or even necessary, to delay wake-up of all of the devices until the last device finishes configuration. This is
accomplished by setting DONE_EX to OFF on the last device while setting DONE_EX to ON for the other devices.
Wake-up Sequence Options
The wake-up sequence options determine the order of application for three internal signals, GSR, GWDIS, and
GOE, and one external signal, DONE.
• GSR is used to set and reset the core of the device. GSR is asserted (low) during configuration and de-asserted
(high) in the Wake-Up sequence.
• When the GWDIS signal is low it safeguards the integrity of the RAM Blocks and LUTs in the device. This signal
is low before the device wakes up. The GWDIS signal is internal to the FPGA, and does not appear on any FPGA
I/O. During the time it is driven low all EBR and LUT RAM elements are safe from being modified.
• During initialization and configuration the FPGA I/O are placed in a high impedance state. The GOE control controls when the FPGA I/O leave the high impedance state. The I/O are Hi-Z when GOE is asserted low.
• The DONE pin, when high, indicates that FPGA has completed configuration and is in user mode. DONE will
only be high if DONE_EX=ON, the output driver is released, and the external pin is pulled up.
If DONE_EX (see DONE EX above) is OFF then sequence 21 is the default, but you can select any sequence from
8 to 25; if DONE_EX is ON the default sequence is 4, but you can select any sequence from 1 to 7.
WAKE_ON_LOCK
The wake-up sequence can be delayed until the selected PLLs have a chance to lock. The WAKE_ON_LOCK attribute selects which PLLs will delay the wake-up sequence until the PLL locks. If you choose an external signal for
PLL feedback rather than an internal clock signal, wake-up must occur without waiting for PLL lock because all I/Os
are tri-stated until the device wakes up, preventing the PLL from locking.
Using the default mode of operation, the device PLLs do not have to be locked for wake-up to commence. You can
choose to make the wake-up sequence dependent on any of the PLLs. If multiple PLLs are included in the design,
all PLLs in the design have to be locked to satisfy the wake-up sequence.15-27
LatticeECP3 sysCONFIG Usage Guide
Bitstream Generation Property Options
Run DRC (T/F)
When the Run DRC option is set to TRUE, a physical design rule check will be run prior to generating a bitstream.
The output will be saved to the Bit Generation report (.bgn file). Running DRC before a bitstream is produced will
detect any errors that could cause the FPGA to function improperly. If no fatal errors are detected, it will produce a
bitstream file. The default is True and will run DRC. When this option is set to False, a design rule check (DRC) will
not be run prior to generating a bitstream.
Create Bitfile (T/F)
This option allows you to decide whether or not to generate an output bitstream. The default setting is to create a
bitstream.
Bitstream File Formats
• Bit file (binary)
• Raw bit file
• Mask & Readback file (ASCII)
• Mask & Readback file (binary)
These options allow you to chose the format of a bitstream file. The Raw Bit option causes the Bitstream Generator
to create a Raw Bit (.rbt) file instead of a binary file (.bit). A binary .bit file can be viewed with a binary editor.
The Raw Bit File is a text file containing ASCII ones and zeros representing the bits in the bitstream file. If you are
using a microprocessor to configure a single FPGA, you can include the Raw Bit file in the source code as a text file
to represent the configuration data. The sequence of characters in the Raw Bit file is the same as the bit sequence
that will be written into the FPGA. This file is a large file.
A Mask file (.msk) can be generated in either an ASCII formatted file or binary file. The Mask file is used to compare relevant bit locations for executing a readback of configuration data contained in an operating FPGA. You can
compare readback data from the device to the mask file after downloading the bitstream. The ASCII mask file will
contain 1’s and 0’s, and X’s. The file contains all FPGA data frames. It contains no header, ID frames, address
frames and no preloaded frames.
No Header (T/F)
The generated bitstream contains no header. The default will be false and will always produce a bitstream file
including all the header information.
Bitstream Encryption/Decryption Flow
The LatticeECP3 supports both encrypted and non-encrypted bitstreams. The encrypted flow adds only two steps
to the normal FPGA design flow, encryption of the configuration bitstream and programming the encryption key into
the LatticeECP3 devices.
Encrypting the Bitstream
As with any other Lattice FPGA design flow, the engineer must first create the design using a device and version of
ispLEVER or Diamond which supports the encryption feature. You must obtain the Encryption Installer from Lattice
prior to using Encryption capabilities. The design is synthesized, mapped, placed and routed, and verified. Once
the engineer is satisfied with the design a bitstream is created and loaded into the FPGA for final debug. After the
design has been debugged it is time to secure the design.
The bitstream can be encrypted using an appropriate version of ispLEVER by going to the Tools pull-down menu
and selecting Security features or by using the Universal File Writer (UFW), which is part of the Lattice ispVM™ 15-28
LatticeECP3 sysCONFIG Usage Guide
System tool suite. The file is encrypted using ispVM as follows. To encrypt the bitstream in Diamond, see Appendix
B.
Figure 15-12. ispVM Main Window
1. Start ispVM. You can start ispVM from the Tools menu in ispLEVER or from the Start -> Programs menu
in Windows. ispVM is not accessible from the Tools menu in Diamond. You should see a window that looks
similar to Figure 15-12. Click on the UFW button on the toolbar. You will see a window similar to Figure 15-
13.
Figure 15-13. Universal File Writer (Encryption Option)
2. Double click on Input Data File and browse to the non-encrypted bitstream created using ispLEVER or
Diamond. Double-click on Output Data File and select an output file name. Right-click on Encryption and
select ON. Right-click on Configuration Mode and select the type of device the FPGA will be configuring
from, such as SPI Serial Flash. Right-click on Encryption Key and select Edit Encryption Key. You will
see a window that looks similar to Figure 15-14.15-29
LatticeECP3 sysCONFIG Usage Guide
Figure 15-14. Encryption Key Dialog Window
3. Enter the desired 128-bit key. The key can be entered in Hexadecimal or ASCII. Hex supports 0 through f
and is not case sensitive. ASCII supports all alphanumeric characters, as well as spaces, and is case sensitive. Note: be sure to remember this key. Lattice cannot recover an encrypted file if the key is lost. Click
on OK to go back to the main UFW window.
4. From the menu bar, click on Project -> Generate to create the encrypted bitstream file.
5. The bitstream can now be loaded directly into non-volatile configuration storage (such as SPI Serial Flash)
using a Lattice ispDOWNLOAD®
Cable, a third-party programmer, or any other method normally used to
program a non-encrypted bitstream. However, before the LatticeECP3 can configure from the encrypted
file the 128-bit key used to encrypt the file must be programmed into the one-time programmable cells on
the FPGA.
Programming the 128-bit Key
The next step is to program the 128-bit encryption key into the one-time programmable cells on the LatticeECP3.
This is done through the device JTAG interface. Note that this step is separated from file encryption to allow flexibility in the manufacturing flow. For instance, the board manufacturer might program the encrypted file into the SPI
Serial Flash, but the key might be programmed at your facility. This flow adds to design security and it allows you to
control over-building of a design. Over-building occurs when a third party builds more boards than are authorized
and sells them to grey market customers. If the key is programmed at the factory, then the factory controls the number of working boards that enter the market. The LatticeECP3 will only configure from a file that has been
encrypted with the same 128-bit key that is programmed into the FPGA.
To program the key into the LatticeECP3, proceed as follows.
1. Attach a Lattice ispDOWNLOAD cable from a PC to the JTAG connector wired to the LatticeECP3 (note
that the 128-bit key can only be programmed into the LatticeECP3 using the JTAG port). Apply power to
the board.
2. Start the ispVM System software. ispVM can be started from within the ispLEVER Tools menu or from the
Start -> Programs menu in Windows. ispVM cannot be invoked from the Tools menu in Diamond. You
should see a window that looks similar to Figure 15-12. If the window does not show the board’s JTAG
chain then proceed as follows. Otherwise, proceed to step 3.
a. Click the SCAN button in the toolbar to find all Lattice devices in the JTAG chain. The chain shown
in Figure 15-12 has only one device, the LatticeECP3. 15-30
LatticeECP3 sysCONFIG Usage Guide
Figure 15-15. Device Information Window (Encryption Option)
3. Double-click on the line in the chain containing the LatticeECP3. This will open the Device Information window (see Figure 15-17). From the Device Access Options drop-down box select Security Mode, then click
on the Security Key button to the right. The window will look similar to Figure 15-16.
Figure 15-16. Enter the Encryption Key15-31
LatticeECP3 sysCONFIG Usage Guide
4. Enter the desired 128-bit key. The key can be entered in Hexadecimal or ASCII. Hex supports 0 through f
and is not case sensitive. ASCII supports all alphanumeric characters, as well as spaces, and is case sensitive. This key must be the same as the key used to encrypt the bitstream. The LatticeECP3 will only configure from an encrypted file whose encryption key matches the one loaded into the FPGA’s one-time
programmable cells. Note: be sure to remember this key. Once the Key Lock is programmed, Lattice Semiconductor cannot read back the one-time programmable key.
a. The key can be saved to a file using the Save to File button. The key will be encrypted using an 8-
character password that you select. The name of the file will be .bek. In the future,
instead of entering the 128-bit key, simply click on Load from File and provide the password.
5. Programming the Key Lock secures the 128-bit encryption key. Once the Key Lock is programmed and the
device is power cycled, the 128-bit encryption key cannot be read out of the device. When satisfied, type
Yes to confirm, then click Apply.
6. From the main ispVM window (Figure 15-12) click on the green GO button on the toolbar to program the
key into the LatticeECP3 one-time programmable cells. When complete, the LatticeECP3 will only configure from a bitstream encrypted with a key that exactly matches the one just programmed.
Verifying a Configuration
As an additional security step when an encrypted bitstream is used, the readback path from the SRAM fabric is
automatically blocked. In this case, for all ports, a read operation will produce all 1's. However, even when the configuration bitstream has been encrypted and readback disabled, there are still ways to verify that the bitstream was
successfully downloaded into the FPGA.
If the SRAM fabric is programmed directly, the data is first decrypted and then the FPGA performs a cyclic redundancy code (CRC) on the data. (CRC) circuitry is used to validate each configuration data frame (sequence of data
bits) as it is loaded into the target device. If all CRCs pass, configuration was successful. If a CRC does not pass,
the DONE pin will stay low and INITN will go from high to low.
If the encrypted data is stored in non-volatile configuration memory, such as SPI Serial Flash, the data is stored
encrypted. A bit-for-bit verify can be performed between the encrypted configuration file and the stored data.
File Formats
The base binary file format is the same for all non-encrypted, non-1532 configuration modes. Different file types
(hex, binary, ASCII, etc.) may ultimately be used to configure the device, but the data in the file is the same.
Table 15-10 shows the format of a non-encrypted bitstream. The bitstream consists of a comment field, a header,
the preamble, and the configuration setup and data.15-32
LatticeECP3 sysCONFIG Usage Guide
Table 15-10. Non-Encrypted Configuration Data
Table 15-11 shows a bitstream that is built for encryption but has not yet been encrypted. The highlighted areas will
be encrypted. The changes between Table 15-10 and Table 15-11 include the following:
• The Program Security frame (readback disable) has been moved to the beginning of the file so that readback is
turned off at the very beginning of configuration. This is an important security feature that prevents someone
from interrupting the configuration before completion and reading back unsecured data.
• A copy of the usercode is placed in the non-encrypted comment string. This has been done to allow you a
method to identify an encrypted file. For example, the usercode could be used as a file index. Note that the usercode itself, while encrypted in the configuration data file, is not encrypted on the device. At configuration the
usercode is decrypted and placed in the JTAG Usercode register. This allows you a method to identify the data in
the device. The JTAG Usercode register can be read back at any time, even when all SRAM readback paths
have been turned off. The usercode can be set to any 32-bit value. For information on how to set usercode, see
the ispLEVER or Diamond help facility.
• A copy of CONFIG_MODE, one of the global preferences, is placed in the non-encrypted comment string.
CONFIG_MODE can be SPI/SPIm, SSPI, Slave SCM, Slave PCM, Master PCM, or JTAG.
Frame Contents Description
Comments (Comment String) ASCII Comment (Argument) String and Terminator
Header
1111...1111 16 Dummy bits
1011110110110011 16-bit Standard Bitstream Preamble (0xBDB3)
Verify ID 64 bits of command and data
Control Register 0 64 bits of command and data
Reset Address 32 bits of command and data
Write Increment 32 bits of command and data
Data 0 Data, 16-bit CRC, and Stop bits
Data 1 Data, 16-bit CRC, and Stop bits
.
.
.
.
.
.
.
.
.
Data n-1 Data, 16-bit CRC, and Stop bits
End 1111...1111 Terminator bits and 16-bit CRC
Usercode 64 bits of command and data
SED CRC 64 bits of command and data
Program Security 32 bits of command and data
Program Done 32 bits of command and data, 16-bit CRC
NOOP 1111...1111 64 bits of NOOP data
End 1111...1111 32-bit Terminator (all ones)
Note: The data in this table is intended for reference only.15-33
LatticeECP3 sysCONFIG Usage Guide
Table 15-11. Configuration File Just Before Encryption
Once encrypted, besides the obvious encryption of the data itself, the file will have additional differences from a
non-encrypted file (refer to Tables 15-12, 15-13, and 15-14).
• There are three preambles, the encryption preamble, alignment preamble, and the bitstream preamble. The
alignment preamble marks the beginning of the encrypted data. The entire original bitstream, including the bitstream preamble are all encrypted, per Table 15-11. The comment string, the encryption preamble, dummy data,
and alignment preamble are not encrypted.
• The decryption engine within the FPGA takes some time to perform its task; extra time is provided in one of two
ways. For master configuration modes (SPI and SPIm) the FPGA drives the configuration clock, so when extra
time is needed the FPGA stops sending configuration clocks. For slave configuration modes (Bitstream-Burst,
Slave Serial, and Slave Parallel) the data must be padded to create the extra time. Because of this there are several different file formats for encrypted data (see Tables 15-12, 15-13, and 15-14). Note that because of the time
needed to decrypt the bitstream it takes longer to configure from an encrypted data file than it does from a nonencrypted file. The bitstream sizes may vary depending on the configuration mode.
Frame Contents Description
Comments (Comment String) ASCII Comment (Argument) String and Terminator
Header
1111...1111 16 Dummy Bits
16-bit Standard Bitstream Preamble
Verify ID 64 bits of Command and Data
Control Register 0 64 bits of Command and Data
Program Security 32 bits of Command and Data
Reset Address 32 bits of Command and Data
Write Increment 32 bits of Command and Data
Data 0 Data, 16-bit CRC, and Stop Bits
Data 1 Data, 16-bit CRC, and Stop Bits
.
.
.
.
.
.
.
.
.
Data n-1 Data, 16-bit CRC and Stop Bits
End 1111...1111 Terminator Bits and 16-bit CRC
Usercode 64 Bits of Command and Data
SED CRC 64 Bits of Command and Data
Program Done 32 Bits of Command and Data, 16-bit CRC
NOOP 1111...1111 64 bits of NOOP data
End 1111...1111 32-bit Terminator (All Ones).
Note: The data in this table is intended for reference only. The shaded areas will be encrypted.15-34
LatticeECP3 sysCONFIG Usage Guide
Table 15-12. Encrypted File Format for a Master Mode
Table 15-13. Encrypted File Format for a Slave Serial Mode
Frame Contents Description
Comments (Comment String) ASCII Comment (Argument) String and Terminator.
Header
1111...1111 16 Dummy bits.
16-bit Encryption Preamble.
30,000 Filler Bits This allows time for the device to load and hash the 128-bit encryption key.
Alignment Preamble
16-bit Alignment Preamble.
1 1-bit Dummy Data.
Data
There are no dummy filler bits when the bitstream is generated for master programming modes. The CCLK of the master device stops the clock when it needs time to
decrypt the data. It resumes the clock when ready for new data - Encrypted.
Program Done 32-bit Program Done Command - Encrypted.
End 1111...1111 32-bit Terminator (all ones) - Encrypted.
Filler Bits Filler to meet the bound requirement.
Dummy Data 1111...1111 200 bits of Dummy Data (all ones). Provides a delay to turn off the decryption
engine.
Note:The data in this table is intended for reference only. The shaded area is encrypted data.
Frame Contents Description
Comments (Comment String) ASCII Comment (Argument) String and Terminator.
Header
1111...1111 2 Dummy Bytes.
16-bit Encryption Preamble
30,000 Filler Bits This allows time for the device to load and hash the 128-bit encryption key.
Alignment Preamble
16-bit Alignment Preamble.
1 1-bit Dummy Data.
Data
128 bits of Configuration Data.
64 bits of all ones data. Provides a delay for the decryption engine to decrypt the
128 bits of data just received. If the peripheral device can provide the needed 64
clocks while pausing data, then the 64 bits of dummy data are not required, saving
file size.
...
Last 128 bits of the last Frame of Configuration Data.
64 bits of all ones data. Provides a delay for the decryption engine to decrypt the
128 bits of data just received. If the peripheral device can provide the needed 64
clocks while pausing data, then the 64 bits of dummy data are not required, saving
file size.
Program Done 32-bit Program Done Command - Encrypted.
End 32-bit Terminator (all ones) - Encrypted.
Filler Bits Filler to meet the bound requirement.
Delay 64 bits of all ones data. Delay to decrypt the Program Done command and the filler.
Dummy Data 1111...1111 200 bits of Dummy Data (all ones), to provide delay to turn off the decryption
engine.
Note:The data in this table is intended for reference only. The shaded area is encrypted data.15-35
LatticeECP3 sysCONFIG Usage Guide
Table 15-14. Encrypted File Format for a Slave Parallel Mode
Decryption Flow
Compared to the encryption flow just discussed, the decryption flow is much simpler.
When data comes into the FPGA the decoder starts looking for the preamble and all information before the preamble is ignored. The preamble determines the path of the configuration data.
If the decoder detects a standard bitstream preamble in the bitstream it knows that this is a non-encrypted data file.
The decoder then selects the Raw data path.
If the decoder detects an encryption preamble in the bitstream it knows that this is an encrypted data file. If an
encryption key has not been programmed, the encrypted data is blocked and configuration fails (the DONE pin
stays low), if the proper key has been programmed then configuration can continue. The next block read contains
30,000 clocks of filler data. This delay allows time for the FPGA to read the key cells and prepare the decryption
engine. The decoder keeps reading the filler data looking for the alignment preamble. Once found, it knows that the
following data needs to go through the decryption engine. It first looks for the standard preamble. Once found, then
the SRAM cells’ programming begins.
But what happens if the key in the FPGA does not match the key used to encrypt the file? Once the data is
decrypted, the FPGA expects to find a valid standard bitstream preamble (BDB3), along with proper commands
and data that pass CRC checks. If the keys do not match then the decryption engine will not produce a proper configuration bitstream; either configuration will not start because the preamble was not found (the INITN pin stays
high and the DONE pin stays low) or CRC errors will occur, causing the INITN pin to go low to indicate the error.
Frame Contents Description
Comments (Comment String) ASCII Comment (Argument) String and Terminator.
Header
1111...1111 2 Dummy Bytes.
2-byte Encryption Preamble.
30,000 Filler Bytes This allows time for the device to load and hash the 128-bit encryption key.
Alignment Preamble
2-byte Alignment Preamble.
11111111 1-byte Dummy Data.
Data
16 bytes of Configuration Data.
64 bytes (clocks) of all ones data. Provides a delay for the decryption engine to
decrypt the 16 bytes of data just received. If the peripheral device can provide the
needed 64 clocks while pausing data, then the 64 bytes of dummy data are not
required, saving file size.
...
16 bytes of Configuration Data.
64 bytes (clocks) of all ones data. Provides a delay for the decryption engine to
decrypt the 16 bytes of data just received. If the peripheral device can provide the
needed 64 clocks while pausing data, then the 64 bytes of dummy data are not
required, saving file size.
Program Done 4-byte Program Done Command - Encrypted.
End 4-byte Terminator (all ones) - Encrypted.
Filler Bits Filler to meet the bound requirement.
Delay 64 bytes of all ones data. Delay to decrypt the Program Done command and the
filler.
Dummy Data 1111...1111 200 bytes of Dummy Data (all ones), to provide delay to turn off the decryption
engine.
Note:The data in this table is intended for reference only. The shaded area is encrypted data.15-36
LatticeECP3 sysCONFIG Usage Guide
Combining Configuration Modes
Multiple FPGAs, One SPI Flash
With a sufficiently large SPI Flash, multiple FPGAs can be configured as shown in Figure 15-17. The first FPGA is
configured in SPI mode; the following FPGAs are configured in Slave Serial mode.
Figure 15-17. Multiple FPGAs, One SPI Serial Flash
Figure 15-18. Slave SPI Example 1
The system diagram shown in Figure 15-18 illustrates one application of the Slave SPI interface, where the FPGA
selects the SPI Flash as the primary boot source. The modern CPU has the capability to program the SPI Flash
boot PROM as well as to command the FPGA to re-boot from the SPI Flash by toggling the PROGRAMN pin. This
requirement can only be met if the CPU drives the CCLK, and the MCLK is driven is by the FPGA for the SPI Flash
boot PROM as shown in Figure 15-18.
CS1N/HOLDN: When Slave SPI mode is used, this pin is an asynchronous active Low Input that tri-states the
serial read out data of the SPI port and sets the device to the suspend state by ignoring the clock. Set the SSPI
PERSISTENT to on to retain the pin as HOLDN pin to access the Slave SPI port in user mode.
Lattice FPGA
SPI Mode
MCLK
DI/CSSPI0N
BUSY/SISPI
D7/SPID0 DOUT
CFG1
CFG0
SPIFASTN
SPI Serial
Flash
Q
C
CFG2
D0/SPIFASTN
PROGRAMN
DONE
D
/CS
Lattice FPGA
Slave Serial
CCLK
DI/CSSPI0N
CFG1
CFG0
CFG2
DOUT
CPU
SPI
Mode
CSN
DI
DO
CLK
HOLDN
SN
SI
SO
SCK
GPIO PROGRAMn
CCLK
CSSPI0N
SISPI
SPID0
SCLK MCLK
CFG0
CFG2
Master
SPI Port
Slave
SPI Port
CFG1
FPGA
SPI
Flash
SPI Port15-37
LatticeECP3 sysCONFIG Usage Guide
Figure 15-19. Slave Parallel with Flowthrough
Chain Mode Options
The LatticeECP3 can be one of many FPGAs in a chain that each need to get configuration data. The Bypass and
Flowthrough options control how each FPGA in the chain of devices pass configuration bits to the other devices in
the chain. Successful configuration of a chain of FPGAs depends on a thorough understanding of the Bypass and
Flowthrough features.
Bypass Option
This option is used when you are configuring a chain of FPGAs in either parallel or serial daisy chain configurations. The Bypass option, when enabled, adds an additional command to the end of the configuration bitstream
being sent to the LatticeECP3. The LatticeECP3 receives all of the configuration bits, and upon reception of the
BYPASS command it enables a serial bypass register. This bypass register passes all incoming configuration bits
to the DOUT pin for use by the next FPGA in the chain. Prior to the LatticeECP3 receiving the BYPASS command
the internal bypass register is initialized to ‘1’. Any FPGA receiving data from the DOUT pin will see a long string of
ones until the BYPASS command is accepted by the LatticeECP3.
The following conditions must be met when Bypass is enabled:
• The PERSISTENT option must be set to Slave Parallel mode
• The bitstream can not be encrypted
• The LatticeECP3 can not be in SPIm mode
The Bypass Option is DISABLED by default.
Flowthrough Option
The Flowthrough option is used when you are configuring a chain of FPGAs in Slave Parallel Configuration mode.
It is not applicable to any other configuration mode. The Flowthrough option, when enabled, adds a
FLOWTHROUGH command to the end of the bitstream for the LatticeECP3. The LatticeECP3 receives all of the
configuration data over the Slave Parallel data bus. When it receives the FLOWTHROUGH command it asserts the
CSON output pin driving the parallel bus chip select input of the next FPGA in the chain. Until reception of the
Lattice FPGA
Slave Parallel
CCLK
D[0:7]
DONE
INITN
CSON
CFG1
CFG0
CFG2
CS1N
PROGRAM
BUSY
WRITEN
CSN
PROGRAMN
Lattice FPGA
Slave Parallel
CCLK
D[0:7]
DONE
INITN
CFG1
CFG0
CFG2
CS1N
BUSY
WRITEN
CSN
PROGRAMN
CSON
INITN
DONE
D[0:7]
CCLK
BUSY
WRITEN
FT_RESET
SELECTN15-38
LatticeECP3 sysCONFIG Usage Guide
FLOWTHROUGH command the CSON pin is deasserted high, which prevents any downstream FPGA from loading the incoming data bytes.
The following conditions must be met to use the Flowthrough option:
• The PERSISTENT option must be set to Slave Parallel
• The bitstream can not be encrypted
• The CONFIG_MODE must be Slave Parallel Configuration mode
The Flowthrough option is DISABLED by default.
Reset Configuration RAM in Reconfiguration (T/F)
When this switch is set to true, it directs the bitstream to reinitialize the device when configuration starts. When the
switch is set to false, it directs the bitstream to program the device to retain the current configuration and allows for
additional bitstream configuration. The default is true. Use of the feature requires you to be aware of potential contention issues with the prior configuration loaded into the FPGA.
References
• Federal Information Processing Standard Publication 197, Nov. 26, 2001. Advanced Encryption Standard (AES)
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
February 2009 01.0 Initial release.
June 2009 01.1 Added SSPI command table. Major changes to SPI support.
October 2009 01.2 Added clarification for dual boot function.
November 2009 01.3 Compression support removed.
January 2010 01.4 Updated SPI Flash mode.
March 2010 01.5 Updated Parallel Port Write Timing diagram.
June 2010 01.6 Updated for Lattice Diamond design software support.
December 2010 01.7 Removed EBR_READ command from the Slave SPI Commands table.
March 2011 01.8 Updated Selectable Master Clock (MCCLK) Frequencies During Configuration (Nominal) table.
August 2011 01.9 Added footnote to “One FPGA, One SPI Serial Flash” figure.
September 2011 02.0 Added new table to Appendix A: Maximum Configuration Bits - Serial
and Parallel Mode Bitstream Files.
February 2012 02.1 Updated document with new corporate logo.
August 2012 02.2 Added recommendation to pull up CSSPI0N.
April 2013 02.3 Added pins and footnote to the PERSISTENT Setting and Affected Pins
table.
May 2013 02.4 Updated the PERSISTENT Setting and Affected Pins table.15-39
LatticeECP3 sysCONFIG Usage Guide
Appendix A. Configuration Memory Requirements
Table 15-15. Bitstream Memory
Description Number of Bits
Header 16
Preamble 16
Verify ID 64
Reserved 136
CReg0 64
NOOP 8
Reset address 32
Write inc 32
Data frames (by device)
-35 2067
-70/95 2819
-150 3607
Bits per frame (by device)
-35 3416
-70/95 6728
-150 8384
Total data frame bits (by device) Data frames multiplied by bits per frame
CRC bits per frame 16
Stop bits per frame 32
End frame 160
CRC 16
Usercode 64
SED CRC 64
Program security 32
EBR frames Device and user design specified
Write command 32
EBR data 18432
CRC 16
Stop bits 32
CRC 16
EBR bits per frame 18528
Total EBR frame bits Equal to EBR Frames multiplied by EBR bits per frame
Program done 48
End 3215-40
LatticeECP3 sysCONFIG Usage Guide
Table 15-16. Maximum Configuration Bits – Serial and Parallel Mode Bitstream Files
Device
All Modes Slave Serial Mode Slave Parallel Mode
Units
Unencrypted
Bitstream Size
Encrypted
Bitstream Size
Encrypted
Bitstream Size
LatticeECP3-17 No EBR 3.88 5.84 19.60 Mb
LatticeECP3-17 Max EBR 4.41 6.64 22.26 Mb
LatticeECP3-35 No EBR 6.83 10.28 34.38 Mb
LatticeECP3-35 Max EBR 8.10 12.18 40.74 Mb
LatticeECP3-95 No EBR 18.22 27.36 91.32 Mb
LatticeECP3-95 Max EBR 22.46 33.72 112.53 Mb
LatticeECP3-150 No EBR 29.01 43.54 145.27 Mb
LatticeECP3-150 Max EBR 35.58 53.40 178.13 Mb15-41
LatticeECP3 sysCONFIG Usage Guide
Appendix B. Lattice Diamond Usage Overview
This appendix discusses the use of Lattice Diamond design software for projects that include the LatticeECP2M
SERDES/PCS module .
For general information about the use of Lattice Diamond, refer to the Lattice Diamond Tutorial.
If you have been using ispLEVER software for your FPGA design projects, Lattice Diamond may look like a big
change. But if you look closer, you will find many similarities because Lattice Diamond is based on the same toolset
and work flow as ispLEVER. The changes are intended to provide a simpler, more integrated, and more enhanced
user interface.
Converting an ispLEVER Project to Lattice Diamond
Design projects created in ispLEVER can easily be imported into Lattice Diamond. The process is automatic
except for the ispLEVER process properties, which are similar to the Diamond strategy settings, and PCS modules.
After importing a project, you need to set up a strategy for it and regenerate any PCS modules.
Importing an ispLEVER Design Project
Make a backup copy of the ispLEVER project or make a new copy that will become the Diamond project.
1. In Diamond, choose File > Open > Import ispLEVER Project.
2. In the ispLEVER Project dialog box, browse to the project’s .syn file and open it.
3. If desired, change the base file name or location for the Diamond project. If you change the location, the
new Diamond files will go into the new location, but the original source files will not move or be copied. The
Diamond project will reference the source files in the original location.
The project files are converted to Diamond format with the default strategy settings.
Adjusting PCS Modules
PCS modules created with IPexpress have an unusual file structure and need additional adjustment when importing a project from ispLEVER. There are two ways to do this adjustment. The preferred method is to regenerate the
module in Diamond. However this may upgrade the module to a more recent version. An upgrade is usually desirable but if, for some reason, you do not want to upgrade the PCS module, you can manually adjust the module by
copying its .txt file into the implementation folder. If you use this method, you must remember to copy the .txt file
into any future implementation folders.
Regenerate PCS Modules
1. Find the PCS module in the Input Files folder of File List view. The module may be represented by an .lpc,
.v, or .vhd file.
2. If the File List view shows the Verilog or VHDL file for the module, and you want to regenerate the module,
import the module’s .lpc file:
a. In the File List view, right-click the implementation folder ( ) and choose Add > Existing File.
b. Browse for the module’s .lpc file, .lpc, and select it.
c. Click Add. The .lpc file is added to the File List view.
d. Right-click the module’s Verilog or VHDL file and choose Remove.
3. In File List, double-click the module’s .lpc file. The module’s IPexpress dialog box opens.
4. In the bottom of the dialog box, click Generate. The Generate Log tab is displayed. Check for errors and
close.15-42
LatticeECP3 sysCONFIG Usage Guide
In File List, the .lpc file is replaced with an .ipx file. The IPexpress manifest (.ipx) file is new with Diamond. The .ipx
file keeps track of the files needed for complex modules.
Using IPexpress with Lattice Diamond
Using IPexpress with Lattice Diamond is essentially same as with ispLEVER.
The configuration GUI tabs are all the same except for the Generation Options tab. Figure 15-20 shows the Generation Options tab window.
Figure 15-20. Generation Options Tab
Table 15-17. SERDES_PCS GUI Attributes – Generation Options Tab
GUI Text Description
Automatic Automatically generates the HDL and configuration(.txt) files as needed. Some
changes do not require regenerating both files.
Force Module and Settings Generation Generates both the HDL and configuration files.
Force Settings Generation Only Generates only the attributes file. You get an error message if the HDL file also
needs to be generated.
Force Place & Route Process Reset Resets the Place & Route Design process, forcing it to be run again with the
newly generated PCS module.
Force Place & Route Trace Process Reset Resets the Place & Route Trace process, forcing it to be run again with the newly
generated PCS module.
Note:
Automatic is set as the default option. If either Automatic or Force Settings Generation Only and no sub-options (Process Reset Options) are
checked and the HDL module is not generated, the reset pointer is set to Bitstream generation automatically.
After the Generation is finished, the reset marks in the process window will be reset accordingly.15-43
LatticeECP3 sysCONFIG Usage Guide
Creating a New Simulation Project Using Simulation Wizard
This section describes how to use the Simulation Wizard to create a simulation project (.spf) file so you can import
it into a standalone simulator.
1. In Project Navigator, click Tools > Simulation Wizard. The Simulation Wizard opens.
2. In the Preparing the Simulator Interface page click Next.
3. In the Simulator Project Name page, enter the name of your project in the Project Name text box and
browse to the file path location where you want to put your simulation project using the Project Location
text box and Browse button.
When you designate a project name in this wizard page, a corresponding folder will be created in the file
path you choose. Click Yes in the popup dialog that asks you if you wish to create a new folder.
4. Click either the Active-HDL®
or ModelSim®
simulator check box and click Next.
5. In the Process Stage page choose which type of Process Stage of simulation project you wish to create
Valid types are RTL, Post-Synthesis Gate-Level, Post-Map Gate-Level, and Post-Route Gate-level+Timing.
Only those process stages that are available are activated.
Note that you can make a new selection for the current strategy if you have more than one defined in your
project.
The software supports multiple strategies per project implementation which allow you to experiment with
alternative optimization options across a common set of source files. Since each strategy may have been
processed to different stages, this dialog allows you to specify which stage you wish to load.
6. In the Add Source page, select from the source files listed in the Source Files list box or use the browse
button on the right to choose another desired source file. Note that if you wish to keep the source files in
the local simulation project directory you just created, check the Copy Source to Simulation Directory
option.
7. Click Next and a Summary page appears and provides information on the project selections including the
simulation libraries. By default, the Run Simulator check box is enabled and will launch the simulation tool
you chose earlier in the wizard in the Simulator Project Name page.
8. Click Finish.
The Simulation Wizard Project (.spf) file and a simulation script DO file are generated after running the wizard. You
can import the DO file into your current project if desired. If you are using Active-HDL, the wizard will generate an
.ado file and if you are using ModelSim, it creates and .mdo file.
Note: PCS configuration file, (.txt) must be added in step 6.
Setting Global Preferences in Diamond
To set any of the Global preferences in Table 15-18, do the following in Diamond:
• Invoke the Spreadsheet View by selecting Tools > Spreadsheet View.
• Select the Global Preferences Tab beneath the Spreadsheet View pane as shown in Figure 15-21.
• Right-click on the Preference Value to be set. In the drop-down menu, select the desired value. 15-44
LatticeECP3 sysCONFIG Usage Guide
Table 15-18. Global Preferences
Preference Name Values
PERSISTENT
OFF
SLAVE_PARALLEL
SSPI
CONFIG_MODE
SPI
SLAVE_SERIAL
JTAG
SLAVE_PARALLEL
SPIm
MASTER_PARALLEL
SSPI
DONE_EX OFF
ON
MCCLK_FREQ
2.5
4.3
5.4
6.9
8.1
9.2
10
13
15
20
26
30
34
41
45
55
60
130
CONFIG_SECURE OFF
ON
WAKE_UP
1
4
6
7
10
14
17
21
22
23
24
25
WAKE_ON_LOCK OFF
ON
ENABLE_NDR OFF
ON
CONFIG_IOVOLTAGE
2.5
1.2
1.5
1.8
3.3
STRTUP
EXTERNAL
TCLK
CCLK
MCLK15-45
LatticeECP3 sysCONFIG Usage Guide
Figure 15-21. Global Preferences Tab
Setting Bitstream Generation Options in Diamond
To set any of the Bitstream Generation options listed in Table 15-19, do the following:
• In the File List pane, double-click the left mouse button on a Strategy to invoke the Strategy settings window.
• In the Process pane, left-click on Bitstream. All options related to generating a bitstream can be set in this window.15-46
LatticeECP3 sysCONFIG Usage Guide
Table 15-19. Bitstream Generation Options
Figure 15-22. Bitstream Options
• Double-click the left mouse button on the Value you want to set. Select the desired value from the drop-down
menu.
Note: An explanation of the option is displayed at the bottom of the window. The Help button also invokes
online help for the option
• Select OK. You can then run the Bitstream File process.
Preference Name Values
Chain Mode
Bypass
Disable
Flowthrough
Create bit file True
False
No Header False
True
Output Format
Bit File (Binary)
Mask and Readback File (ASCII)
Mask and Radback File (Binary)
Raw Bit file (ASCII)
PROM Data Output Format Intel Hex 32-bit
Motorola Hex 32-bit
Reset Config RAM in re-configuration True
False
Run DRC True
False
Search Path (Enter a value or browse to specify the search path)15-47
LatticeECP3 sysCONFIG Usage Guide
Setting Security Options in Diamond
Prior to setting security options in Diamond, you must have installed the Encryption Control Pack. You must also
have selected an encrypted device in your project.
To Set Security Settings, do the following:
• Select the Tools > Security Setting option. The following dialog box appears:
• If desired, select Change and enter a password.
• Select OK. A dialog window appears to enter an encryption key.
• If you do not want to enable an encryption key, select OK.
• If you do want to enable an encryption key, select the Advanced Security Settings checkbox, enter the Key
Format, and then enter the Encryption Key.
• Select OK to create the encryption files.
www.latticesemi.com 17-1 tn1246_01.3
April 2013 Technical Note TN1246
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
This reference guide supplements TN1205, Using User Flash Memory and Hardened Control Functions in
MachXO2™ Devices Usage Guide which explains the software usage. In this document you will find:
• WISHBONE Protocol
• EFB Register Map
• Command Sequences
• Examples
As an overview, the MachXO2 FPGA family combines a high-performance, low power, FPGA fabric with built-in,
hardened control functions and on-chip User Flash Memory (UFM). The hardened control functions ease design
implementation and save general purpose resources such as LUTs, registers, clocks and routing. The hardened
control functions are physically located in the Embedded Function Block (EFB). All MachXO2 devices include an
EFB module. The EFB block includes the following control functions:
• Two I2
C Cores
• One SPI Core
• One 16-bit Timer/Counter
• Interface to Flash Memory which includes:
– User Flash Memory for MachXO2-640 and higher densities
– Configuration Logic
• Interface to Dynamic PLL configuration settings
• Interface to On-chip Power Controller through I2
C and SPI
Figure 17-1 shows the EFB architecture and the interface to the FPGA core logic.
Using User Flash Memory and
Hardened Control Functions in
MachXO2 Devices Reference Guide17-2
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-1. Embedded Function Block (EFB)
EFB Register Map
The EFB module has a Register Map to allow the service of the hardened functions through the WISHBONE bus
interface read/write operations. Each hardened function has dedicated 8-bit Data and Control registers, with the
exception of the Flash Memory (UFM/Configuration), which are accessed through the same set of registers.
Table 17-1 documents the register map of the EFB module. The PLL registers are located in the MachXO2 PLL
modules, but they are accessed through EFB WISHBONE read/write cycles.
Table 17-1. EFB Register Map
Address spaces that are not defined in Table 17-1 are invalid and will result in non-deterministic results. It is the
responsibility of the designer to ensure valid addresses are presented to the EFB WISHBONE slave interface.
Address (Hex) Hardened Function
0x00-0x1F PLL0 Dynamic Access1
0x20-0x3F PLL1 Dynamic Access1
0x40-0x49 I2
C Primary
0x4A-0x53 I2
C Secondary
0x54-0x5D SPI
0x5E-0x6F Timer/Counter
0x70-0x75 Flash Memory (UFM/Configuration)
0x76-0x77 EFB Interrupt Source
1. There can be up to two PLLs in a MachXO2 device. PLL0 has
an address range from 0x00 to 0x1F. PLL1 (if present) has an
address range from 0x20 to 0x3F. Reference TN1199,
MachXO2 sysCLOCK PLL Design and Usage Guide, for details
on PLL configuration registers and recommended usage.
Configuration
(including
USERCODE)
UFM
Flash Command Interface
Flash Memory
EFB Register Map
Configuration
Master/Slave
User
Master/Slave
WISHBONE Interface
SPI Port
EFB
Power
Controller
Secondary
I
2
C Port
Primary
I
2
C Port
PLL0/
PLL1
Timer/
Counter
Configuration
OR
Slave
User
Master/Slave
User
Master/Slave User Logic
User Logic
JTAG
Feature Row
(including
TraceID)17-3
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
WISBONE Bus Interface
The WISHBONE Bus in the MachXO2 is compliant with the WISHBONE standard from OpenCores. It provides
connectivity between FPGA user logic and the EFB functional blocks. The user can implement a WISHBONE Master interface to interact with the EFB WISHBONE slave interface or a LatticeMico8™ soft processor core can be
used to interact with the EFB WISHBONE.
The block diagram in Figure 17-2 shows the supported WISHBONE bus signals between the FPGA core and the
EFB. Table 17-2 provides a detailed definition of the supported signals.
Figure 17-2. WISHBONE Bus Interface Between the FPGA Core and the EFB Module
Table 17-2. WISHBONE Slave Interface Signals of the EFB Module
Signal Name I/O Width Description
wb_clk_i Input 1 Positive edge clock used by WISHBONE Interface registers and hardened functions
within the EFB module. Supports clock speeds up to 133 MHz.
wb_rst_i Input 1
Active-high, synchronous reset signal that will only reset the WISHBONE interface
logic. This signal will not affect the contents of any registers. It will only affect ongoing
bus transactions. Wait 1us after de-assertion before starting any subsequent WISHBONE transactions.
wb_cyc_i Input 1 Active-high signal, asserted by the WISHBONE master, indicates a valid bus cycle is
present on the bus.
wb_stb_i Input 1
Active-high strobe, input signal, indicating the WISHBONE slave is the target for the
current transaction on the bus. The EFB module asserts an acknowledgment in
response to the assertion of the strobe.
wb_we_i Input 1 Level sensitive Write/Read control signal. Low indicates a Read operation, and High
indicates a Write operation.
wb_adr_i Input 8 8-bit wide address used to select a specific register from the register map of the EFB
module.
wb_dat_i Input 8 8-bit input data path used to write a byte of data to a specific register in the register
map of the EFB module.
wb_dat_o Output 8 8-bit output data path used to read a byte of data from a specific register in the register map of the EFB module.
wb_ack_o Output 1 Active-high, transfer acknowledge signal asserted by the EFB module, indicating the
requested transfer is acknowledged.
EFB Register Map
WISHBONE Slave Interface
EFB
wb_clk_i WISHBONE Master (User Logic)
wb_rst_i
wb_cyc_i
wb_stb_i
wb_we_i
wb_addr_i[31:0]
wb_dat_i[31:0]
wb_dat_o[31:0]
wb_ack_o
MachXO2
User Logic17-4
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
To interface to the EFB you must create a WISHBONE Master controller in the User Logic. In a multiple-Master
configuration, the WISHBONE Master outputs are multiplexed in a user-defined arbiter. A LatticeMico8 soft processor can also be utilized along with the Mico System Builder (MSB) platform which can implement multi-Master bus
configurations. If two Masters request the bus in the same cycle, only the outputs of the arbitration winner reach the
Slave interface.
The EFB WISHBONE bus supports the “Classic” version of the WISHBONE standard. Given that the WISHBONE
bus is an open source standard, not all features of the standard are implemented or required:
• Tags are not supported in the WISHBONE Slave interface of the EFB module. Given that the EFB is a hardened
block, these signals cannot be added by the user.
• The Slave WISHBONE bus interface of the EFB module does not require the byte select signals (sel_i or sel_o),
since the data bus is only a single byte wide.
• The EFB WISHBONE slave interface does not support the optional error and retry access termination signals. If
the slave receives an access to an invalid address, it will simply respond by asserting wb_ack_o signal. It is the
responsibility of the user to stay within the valid address range.
WISHBONE Write Cycle
Figure 17-3 shows the waveform of a Write cycle from the perspective of the EFB WISHBONE Slave interface. During a single Write cycle, only one byte of data is written to the EFB block from the WISHBONE Master. A Write
operation requires a minimum three clock cycles.
On clock Edge 0, the Master updates the address, data and asserts control signals. During this cycle:
• The Master updates the address on the wb_adr_i[7:0] address lines
• Updates the data that will be written to the EFB block, wb_dat_i[7:0] data lines
• Asserts the write enable wb_we_i signal, indicating a write cycle
• Asserts the wb_cyc_i to indicate the start of the cycle
• Asserts the wb_stb_i, selecting a specific slave module
On clock Edge 1, the EFB WISHBONE Slave decodes the input signals presented by the master. During this cycle:
• The Slave decodes the address presented on the wb_adr_i[7:0] address lines
• The Slave prepares to latch the data presented on the wb_dat_i[7:0] data lines
• The Master waits for an active-high level on the wb_ack_o line and prepares to terminate the cycle on the next
clock edge, if an active-high level is detected on the wb_ack_o line
• The EFB may insert wait states before asserting wb_ack_o, thereby allowing it to throttle the cycle speed. Any
number of wait states may be added
• The Slave asserts wb_ack_o signal
The following occurs on clock Edge 2:
• The Slave latches the data presented on the wb_dat_i[7:0] data lines
• The Master de-asserts the strobe signal, wb_stb_i, the cycle signal, wb_cyc_i, and the write enable signal,
wb_we_i
• The Slave de-asserts the acknowledge signal, wb_ack_o, in response to the Master de-assertion of the strobe
signal17-5
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-3. WISHBONE Bus Write Operation
WISHBONE Read Cycle
Figure 17-4 shows the waveform of a Read cycle from the perspective of the EFB WISHBONE Slave interface.
During a single Read cycle, only one byte of data is read from the EFB block by the WISHBONE master. A Read
operation requires a minimum three clock cycles.
On clock Edge 0, the Master updates the address, data and asserts control signals. The following occurs during
this cycle:
• The Master updates the address on the wb_adr_i[7:0] address lines
• De-asserts the write enable wb_we_i signal, indicating a Read cycle
• Asserts the wb_cyc_i to indicate the start of the cycle
• Asserts the wb_stb_i, selecting a specific Slave module
On clock Edge 1, the EFB WISHBONE slave decodes the input signals presented by the master. The following
occurs during this cycle:
• The Slave decodes the address presented on the wb_adr_i[7:0] address lines
• The Master prepares to latch the data presented on wb_dat_o[7:0] data lines from the EFB WISHBONE slave on
the following clock edge
• The Master waits for an active-high level on the wb_ack_o line and prepares to terminate the cycle on the next
clock edge, if an active-high level is detected on the wb_ack_o line
• The EFB may insert wait states before asserting wb_ack_o, thereby allowing it to throttle the cycle speed. Any
number of wait states may be added.
• The Slave presents valid data on the wb_dat_o[7:0] data lines
• The Slave asserts wb_ack_o signal in response to the strobe, wb_stb_i signal
wb_clk_i
wb_rst_i
wb_cyc_i
wb_stb_i
wb_we_i
wb_adr_i [7:0]
wb_dat_i [7:0]
wb_dat_o [7:0]
wb_ack_o
VALID ADDRESS
VALID DATA
Edge 0 Edge 1 Edge 217-6
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
The following occurs on clock Edge 2:
• The Master latches the data presented on the wb_dat_o[7:0] data lines
• The Master de-asserts the strobe signal, wb_stb_i, and the cycle signal, wb_cyc_i
• The Slave de-asserts the acknowledge signal, wb_ack_o, in response to the master de-assertion of the strobe
signal
Figure 17-4. WISHBONE Bus Read Operation
WISHBONE Reset Cycle
Figure 17-5 shows the waveform of the synchronous wb_rst_i signal. Asserting the reset signal will only reset the
WISHBONE interface logic. This signal will not affect the contents of any registers in the EFB register map. It will
only affect ongoing bus transactions.
Figure 17-5. EFB WISHBONE Interface Reset
The wb_rst_i signal can be asserted for any length of time.
wb_clk_i
wb_rst_i
wb_cyc_i
wb_stb_i
wb_we_i
wb_adr_i [7:0]
wb_dat_i [7:0]
wb_dat_o [7:0]
wb_ack_o
VALID ADDRESS
VALID DATA
Edge 0 Edge 1 Edge 2
wb_clk_i
wb_rst_i
wb_cyc_i
wb_stb_i
Edge 0 Edge 117-7
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Hardened I2
C IP Cores
I
2
C is a widely used two-wire serial bus for communication between devices on the same board. Every MachXO2
device contains two hardened I2
C IP cores designated as the “Primary” and “Secondary” I2
C IP cores. Either of the
two cores can be operated as an I2
C Master or as an I2
C Slave. The difference between the two cores is that the
Primary core has pre-assigned I/O pins while the ports of the secondary core can be assigned by designers to any
general purpose I/O. In addition, the Primary I2
C core can be used for accessing the User Flash Memory (UFM)
and for programming the Configuration Flash. However, the Primary I2
C port cannot be used for both UFM/Config
access and user functions in the same design.
I
2
C Registers
Both I2
C cores communicate with the EFB WISHBONE interface through a set of control, command, status and
data registers. Table 17-3 shows the register names and their functions. These registers are a subset of the EFB
register map.
Table 17-3. I2
C Registers
Table 17-4. I2
C Control (Primary/Secondary)
I2CEN I2
C System Enable Bit – This bit enables the I2
C core functions. If I2CEN is cleared,
the 2
C core is disabled and forced into idle state.
0: I2
C function is disabled
1: I2
C function is enabled
GCEN Enable bit for General Call Response – Enables the general call response in slave
mode.
0: Disable
1: Enable
The General Call address is defined as 0000000 and works with either 7- or 10-bit
addressing
I
2
C Primary
Register Name
I
2
C Secondary
Register Name
Register
Function
Address
I
2
C Primary
Address
I
2
C Secondary Access
I2C_1_CR I2C_2_CR Control 0x40 0x4A Read/Write
I2C_1_CMDR I2C_2_CMDR Command 0x41 0x4B Read/Write
I2C_1_BR0 I2C_2_BR0 Clock Pre-scale 0x42 0x4C Read/Write
I2C_1_BR1 I2C_2_BR1 Clock Pre-scale 0x43 0x4D Read/Write
I2C_1_TXDR I2C_2_TXDR Transmit Data 0x44 0x4E Write
I2C_1_SR I2C_2_SR Status 0x45 0x4F Read
I2C_1_GCDR I2C_2_GCDR General Call 0x46 0x50 Read
I2C_1_RXDR I2C_2_RXDR Receive Data 0x47 0x51 Read
I2C_1_IRQ I2C_2_IRQ IRQ 0x48 0x52 Read/Write
I2C_1_IRQEN I2C_2_IRQEN IRQ Enable 0x49 0x53 Read/Write
Note: Unless otherwise specified, all reserved bits in writable registers shall be written ‘0’.
I2C_1_CR / I2C_2_CR 0x40/0x4A
Bit 7 6 5 4 3 2 1 0
Name I2CEN GCEN WKUPEN (Reserved) SDA_DEL_SEL[1:0] (Reserved)
Default 0 0 0 000 0 0
Access R/W R/W R/W — R/W R/W — —
Note: A write to this register will cause the I2
C core to reset.17-8
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
WKUPEN Wake-up from Standby/Sleep (by Slave Address matching) Enable Bit – When this bit
is enabled the, I2
C core can send a wake-up signal to the on-chip power manager to
wake the device up from standby/sleep. The wake-up function is activated when the
MachXO2 Slave Address is matched during standby/sleep mode.
0: Disable
1: Enable
SDA_DEL_SEL[1:0] SDA Output Delay (Tdel) Selection (see Figure 17-14)
00: 300ns
01: 150ns
10: 75ns
11: 0ns
Table 17-5. I2
C Command (Pri/Sec)
STA Generate START (or Repeated START) condition (Master operation)
STO Generate STOP condition (Master operation)
RD Indicate Read from slave (Master operation)
WR Indicate Write to slave (Master operation)
ACK Acknowledge Option – when receiving, ACK transmission selection
0: Send ACK
1: Send NACK
CKSDIS Clock Stretching Disable. The I2
C cores support a “wait state” or clock stretching from
the slave, meaning the slave can enforce a wait state if it needs time to finish the task.
Bit CKSDIS disables the clock stretching if desired by the user. In this case, the overflow flag must be monitored. For Master operations, set this bit to ‘0’. Clock stretching
will be used by the MachXO2 EFB I2
C Slave during both ‘read’ and ‘write’ operations
(from the Master perspective) when I2
C Command Register bit CKSDIS=0.
During a read operation (Slave transmitting), clock stretching occurs when TXDR is
empty (under-run condition). During a write operation (Slave receiving) clock stretching occurs when RXDR is full (over-run condition).
Translated into I2
C Status register bits, the I2
C clock-stretches if TRRDY=1. The decision to enable clock stretching is done on the 8TH SCL + 2 WISHBONE clocks.
0: Enabled
1: Disabled
I2C_1_CMDR / I2C_2_CMDR 0x41/0x4B
Bit 7 6 5 4 3 2 1 0
Name STA STO RD WR ACK CKSDIS (Reserved)
Default 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W — —17-9
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-6. I2
C Clock Prescale 0 (Primary/Secondary)
Table 17-7. I2
C Register Clock Prescale 1 (Primary/Secondary)
I2C_PRESCALE[9:0] I2
C Clock Prescale value. A write operation to I2CBR [9:8] will cause an I2
C core reset.
The WISHBONE clock frequency is divided by (I2C_PRESCALE*4) to produce the
Master I2
C clock frequency supported by the I2
C bus (50KHz, 100KHz, 400KHz).
Note: Different from transmitting a Master, the practical limit for Slave I2
C bus speed support is (WISHBONE
clock)/2048. For example, the maximum WISHBONE clock frequency to support a 50 KHz Slave I2
C operation is
102 MHz.
Note: The digital value is calculated by IPexpress™ when the I2
C core is configured in the I2
C tab of the EFB GUI.
The calculation is based on the WISHBONE Clock Frequency and the I2
C Frequency, both entered by the user. The
digital value of the divider is programmed in the MachXO2 device during device programming. After power-up or
device reconfiguration, the data is loaded onto the I2C_1_BR1/0 and I2C_2_BR1/0 registers.
Registers I2C_1_BR1/0 and I2C_2_BR1/0 have Read/Write access from the WISHBONE interface. Designers can
update these clock pre-scale registers dynamically during device operation; however, care must be taken to not violate the I2
C bus frequencies.
Table 17-8. I2
C Transmit Data Register (Primary/Secondary)
I2C_Transmit_Data[7:0] I2
C Transmit Data. This register holds the byte that will be transmitted on the I2
C bus
during the Write Data phase. Bit 0 is the LSB and will be transmitted last. When transmitting the slave address, Bit 0 represents the Read/Write bit.
I2C_1_BR0 / I2C_2_BR0 0x42/0x4C
Bit 7 6 5 4 3 2 1 0
Name I2C_PRESCALE[7:0]
Default1
00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
1. Hardware default value may be overridden by EFB component instantiation parameters. See discussion below.
I2C_1_BR1 / I2C_2_BR1 0x43/0x4D
Bit 7 6 5 4 3 2 1 0
Name (Reserved) I2C_PRESCALE[9:8]
Default1
0 0 0 0 0 000
Access — — — — — — R/W R/W
1. Hardware default value may be overridden by EFB component instantiation parameters. See discussion below.
I2C_1_TXDR / I2C_2_TXDR 0x44/0x4E
Bit 7 6 5 4 3 2 1 0
Name I2C_Transmit_Data[7:0]
Default 0 0 0 0 0 0 0 0
Access W W W W W W W W17-10
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-9. I2
C Status (Primary/Secondary)
TIP Transmit In Progress. The current data byte is being transferred. Note that the TIP flag
will suffer one-half SCL cycle latency right after the START condition because of the
signal synchronization. Also note that this bit could be high after configuration wakeup and before the first valid I2
C transfer start (when BUSY is low), and it is not indicating byte in transfer, but an invalid indicator.
1: Byte transfer in progress
0: Byte transfer complete
BUSY I2
C Bus busy. The I2
C bus is involved in transaction. This is set at START condition and
cleared at STOP. Note only when this bit is set should all other I2
C SR bits be treated
as valid indicators for a valid transfer.
1: I2
C bus busy
0: I2
C bus not busy
RARC Received Acknowledge. An acknowledge response from the addressed slave (during
master write) or from receiving master (during master read) was received.
1: No acknowledge received
0: Acknowledge received
SRW Slave Read/Write. Indicates transmit or receive mode.
1: Master receiving / slave transmitting
0: Master transmitting / slave receiving
ARBL Arbitration Lost. The core has lost arbitration in Master mode. This bit is capable of
generating an interrupt.
1: Arbitration Lost
0: Normal
TRRDY Transmitter or Receiver Ready. The I2
C Transmit Data register is ready to receive
transmit data, or the I2
C Receive Data Register contains receive data (dependent
upon master/slave mode and SRW status). This bit is capable of generating an interrupt.
1: Transmitter or Receiver is ready
0: Transmitter of Receiver is not ready
TROE Transmitter/Receiver Overrun Error or NACK received. A transmit or receive overrun
error has occurred (dependent upon master/slave mode and SRW status), or a No
Acknowledge was received (only when RARC also set). This bit is capable of generating an interrupt.
1: Transmitter or Receiver Overrun detected or NACK received
0: Normal
HGC Hardware General Call Received. A hardware general call has been received in slave
mode. The corresponding command byte will be available in the General Call Data
Register. This bit is capable of generating an interrupt.
I2C_1_SR / I2C_2_SR 0x45/0x4F
Bit 7 6 5 4 3 2 1 0
Name TIP1
BUSY1
RARC SRW ARBL TRRDY TROE HGC
Default — — — — — — — —
Access R R R R R R R R
1. These bits exhibit 0.5 SCK period latency before valid in R1 devices. For more details on the R1 to Standard migration refer to AN8086,
Designing for Migration from MachXO2-1200-R1 to Standard (Non-R1) Devices.17-11
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
1: General Call Received in slave mode
0: Normal
Figure 17-6. I2
C General Call Data Register (Primary/Secondary)
I2C_ GC _Data[7:0] I2
C General Call Data. This register holds the second (command) byte of the General
Call transaction on the I2
C bus.
Table 17-10. I2
C Receive Data Register (Primary/Secondary)
I2C_ Receive _Data[7:0] I2
C Receive Data. This register holds the byte captured from the I2
C bus during the
Read Data phase. Bit 0 is LSB and was received last.
Table 17-11. I2
C Interrupt Status (Primary/Secondary)
IRQARBL Interrupt Status for Arbitration Lost.
When enabled, indicates ARBL was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Arbitration Lost Interrupt
0: No interrupt
IRQTRRDY Interrupt Status for Transmitter or Receiver Ready.
When enabled, indicates TRRDY was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Transmitter or Receiver Ready Interrupt
0: No interrupt
IRQTROE Interrupt Status for Transmitter/Receiver Overrun or NACK received.
When enabled, indicates TROE was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Transmitter or Receiver Overrun or NACK received Interrupt
0: No interrupt
IRQHGC Interrupt Status for Hardware General Call Received.
When enabled, indicates HGC was asserted. Write a ‘1’ to this bit to clear the interrupt.
I2C_1_GCDR / I2C_2_GCDR 0x46/0x50
Bit 7 6 5 4 3 2 1 0
Name I2C_GC_Data[7:0]
Default — — — — — — — —
Access R R R R R R R R
I2C_1_RXDR / I2C_2_RXDR 0x47/0x51
Bit 7 6 5 4 3 2 1 0
Name I2C_Receive_Data[7:0]
Default — — — — — — — —
Access R R R R R R R R
I2C_1_IRQ / I2C_2_ IRQ 0x48/0x52
Bit 7 6 5 4 3 2 1 0
Name (Reserved) IRQARBL IRQTRRDY IRQTROE IRQHGC
Default — — — —————
Access — — — — R/W R/W R/W R/W17-12
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
1: General Call Received in slave mode Interrupt
0: No interrupt
Table 17-12. I2
C Interrupt Enable (Primary/Secondary)
IRQARBLEN Interrupt Enable for Arbitration Lost
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQTRRDYEN Interrupt Enable for Transmitter or Receiver Ready
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQTROEEN Interrupt Enable for Transmitter/Receiver Overrun or NACK Received
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQHGCEN Interrupt Enable for Hardware General Call Received
1: Interrupt generation enabled
0: Interrupt generation disabled
Figure 17-7 shows a flow diagram for controlling Master I2
C reads and writes initiated via the WISHBONE interface.
The following sequence is for the Primary I2
C but the same sequence applies to the Secondary I2
C.
I2C_1_ IRQEN / I2C_2_IRQEN 0x49/0x53
Bit 7 6 5 4 3 2 1 0
Name (Reserved) IRQARBLEN IRQTRRDYEN IRQTROEEN IRQHGCEN
Default 0 0 0 00 0 00
Access — — — — R/W R/W R/W R/W17-13
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-7. I2
C Master Read/Write Example (via WISHBONE)
Start
TXDR <= I2
C addr + ‘W’
CMDR <= 0x90 (STA+WR)
Wait for TRRDY
TXDR <= WRITE_DATA
CMDR <=0x10 (WR)
Write more data?
Read data?
CMDR <= 0x40 (STOP)
Done
TXDR <= I2
C addr + ‘R’
CMDR <= 0x90 (STA+WR)
Wait for SRW
CMDR <= 0x20 (RD)
Last Read?
Wait for TRRDY
READ_DATA <= RXDR
Wait *
CMDR <= 0x68
(RD+NACK+STOP)
Wait for TRRDY
READ_DATA <= RXDR
Y
N
Y
N
*Real-Time Delay Requirement
Read only 1 byte: min < wait < max
Read last of 2+ bytes: 0 < wait < max
where:
min = 2 * (1/fSCL)
max = 7 * (1/fSCL)
Y
N17-14
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-8 shows a flow diagram for reading and writing from an I2
C Slave device via the WISHBONE interface.
The following sequence is for the Primary I2
C but the same sequence applies to the Secondary I2
C.
Figure 17-8. I2
C Slave Read/Write Example (via WISHBONE)
Start
wait for not BUSY
CMDR <=0x04 (CKSDIS)
IRQEN <= 0x00
Read more data?
wait for SRW
Y
N
* Required only for IRQ
driven algorithms
discard <= RXDR
discard <= RXDR
CMDR <=0x00 (CKSEN)
IRQEN <= 0x04 (TRRDY)*
Idle
wait for TRRDY
IN_DATA <= RXDR
IRQ <= 0x04*
Write reply data?
TXDR <= OUT_DATA
wait for TRRDY
Write more data?
TXDR <= OUT_DATA
IRQ <= 0x04*
N
N
Y
Y17-15
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
I
2
C Framing
Each command string sent to the I2
C EFB port must be correctly “framed” using the protocol defined for each interface. In the case of I2
C, the protocol is well known and defined by the industry as shown below.
Table 17-13. Command Framing Protocol, by Interface
Figure 17-9. I2
C Read Device ID Example
Interface Pre-op (+) Command String Post-op (-)
I
2
C Start (Command/Operands/Data) Stop
SCL
SDA A6 A5 A4 A3 A2 0 W 11100000 00000000
SCL
(continued)
SDA 00000000
(continued)
00000000
0
...
...
...
...
Start By
Master
ACK By
MachXO2
ACK By
MachXO2
ACK By
MachXO2
Frame 1 I2
C Slave Address Byte Frame 2 CMD Byte Frame 3 Op Byte 1
Frame 4 Op Byte 2
ACK By
MachXO2
Frame 5 Op Byte 3
ACK By
XO2
A6 A5 A4 A3 A2 0 R 00000001 00101011
ID 0000 01000011
0
...
...
Restart
By Master
ACK By
MachXO2
ACK By
Master
ACK By
Master
Frame 6 I2
C Slave Address Byte Frame 7 Read ID Byte 1 Frame 8 Read ID Byte 2
Frame 9 Read ID Byte 3
ACK By
Master
Frame 10 Read ID Byte 4
NACK By
Master
Stop By
Master
SCL
(continued)
SDA
(continued)
SCL
(continued)
SDA
(continued)
ID ID ID17-16
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-10. EFB Master – I2
C Write Figure 17-11. EFB Master – I2
C Read
AD[(6:0),W]
AD6
SCL
AD5 AD4 AD3 AD2 AD1 AD0 Write
1 9 1 9 1 9
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Master Start
Ack from
Slave
Ack from
Slave
Ack from
Slave
Master Stop
I2C_1_SR[BUSY]
I2C_1_SR[SRW]
I2C_1_SR[TRRDY]
Write IRQTRRDY
I2C_1_IRQ[IRQTRRDY]
W
W
rite IRQTRRDY
rite I2C_1_TXDR Write I2C_1_TXDR
I2C_1_SR[RARC]
Write IRQTRRDY
I2C_1_CMDR 0x10(WR) 0x10(WR)
I2C_1_TXDR D[7:0] D[7:0]
0x90(Start+WR) 0x40(STOP)
Idle
AD[(6:0),W]
0x90 (START+WR)
D[7:0]
0x68 (RD+NACK+STOP)
Stop from
Master
SCL
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Read
1 91 91 9
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Master Start/
Restart
Ack from
Slave
Ack from
Master
Nack from
Master
I2C_1_SR[BUSY]
I2C_1_SR[SRW]
I2C_1_SR[TRRDY]
Read I2C1_RXDR
Write IRQTRRDY
I2C_1_IRQ[IRQTRRDY]
Write IRQTRRDY
I2C_1_CMDR
I2C_1_TXDR
I2C_1_RXDR D[7:0]
0x20 (RD)
Write IRQTRRDY
Read I2C1_RXDR
I
2
C Functional Waveforms17-17
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-12. EFB Slave – I2
C Write Figure 17-13. EFB Slave – I2
C Read
SCL
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write
1 91 91 9
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Start from
Master
Ack from
Slave
Ack from
Slave
Ack from
Slave
Stop from
Master
I2C_1_SR[BUSY]
I2C_1_SR[SRW]
I2C_1_SR[TRRDY]
Write IRQTRRDY
I2C_1_IRQ[IRQTRRDY]
Read I2C_1_RXDR
Write IRQTRRDY
I2C_1_TXDR
I2C_1_RXDR
Read I2C_1_RXDR
D[7:0] D[7:0]
SCL
AD6 AD5 AD4 AD3 AD2 AD1 AD0
1 9 1 9 1 9
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Start from
Master
I2C_1_SR[BUSY]
I2C_1_SR[SRW]
I2C_1_SR[TRRDY]
Write IRQTRRDY
I2C_1_IRQ[IRQTRRDY]
Write IRQTRRDY
Write I2C_1_TXDR Write I2C_1_TXDR
I2C_1_SR[RARC]
I2C_1_TXDR
I2C_1_RXDR
D[7:0] D[7:0]
Write IRQTRRDY
Read
Ack from
Slave
Ack from
Master
No Ack from
Master
Stop from
Master17-18
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
I
2
C Timing Diagram
Figure 17-14. I2
C Bit Transfer Timing
I
2
C Simulation Model
The I2
C EFB Register Map translation to the MachXO2 EFB software simulation model is provided in below.
Table 17-14. I2
C Primary Simulation Mode
I
2
C Primary
Register Name
Register
Size/Bit
Location
Register
Function
Address I2
C
Primary Access
Simulation Model
Register Name Simulation Model Register Path
I2C_1_CR [7:0] Control 0x40 Read/Write i2ccr1[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2CEN 7 i2c_en ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
GCEN 6 i2c_gcen ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
WKUPEN 5 i2c_wkupen ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
SDA_DEL_SEL[1:0] [3:2] sda_del_sel ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_1_CMDR [7:0] Command 0x41 Read/Write i2ccmdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
STA 7 i2c_sta ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
STO 6 i2c_sto ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
RD 5 i2c_rd ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
WR 4 i2c_wt ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
ACK 3 i2c_nack ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
CKSDIS 2 i2c_cksdis ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_1_BR0 [7:0] Clock Pre-scale 0x42 Read/Write i2cbr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_PRESCALE[7:0] [7:0] i2cbr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_1_BR1 [7:0] Clock Pre-scale 0x43 Read/Write i2cbr[9:8] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_PRESCALE[9:8] [1:0] i2cbr[9:8] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_1_TXDR [7:0] Transmit Data 0x44 Write i2ctxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_Transmit_Data[7:0] [7:0] i2ctxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_1_SR [7:0] Status 0x45 Read i2csr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
data line
stable;
data valid
change
of data
allowed
t
SDA_DEL
SCL
SDA17-19
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
TIP 7 i2c_tip_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
BUSY 6 i2c_busy_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
RARC 5 i2c_rarc_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
SRW 4 i2c_srw_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
ARBL 3 i2c_arbl ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
TRRDY 2 i2c_trrdy ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
TROE 1 i2c_troe ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
HGC 0 i2c_hgc ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_1_GCDR [7:0] General Call 0x46 Read i2cgcdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_GC_Data[7:0] [7:0] i2cgcdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_1_RXDR [7:0] Receive Data 0x47 Read i2crxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_Receive_Data[7:0] [7:0] i2crxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_1st/
I2C_1_IRQ [7:0] IRQ 0x48 Read/Write
{1'b0, 1'b0, 1'b0, 1'b0,
i2csr_1st_irqsts_3,
i2csr_1st_irqsts_2,
i2csr_1st_irqsts_1,
i2csr_1st_irqsts_0}
../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQARBL 3 i2csr_1st_irqsts_3 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTRRDY 2 i2csr_1st_irqsts_2 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTROE 1 i2csr_1st_irqsts_1 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQHGC 0 i2csr_1st_irqsts_0 ../efb_top/efb_pll_sci_inst/u_efb_sci/
I2C_1_IRQEN [7:0] IRQ Enable 0x49 Read/Write
{1'b0, 1'b0, 1'b0, 1'b0,
i2csr_1st_irqena_3,
i2csr_1st_irqena_2,
i2csr_1st_irqena_1,
i2csr_1st_irqena_0}
../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQARBLEN 3 i2csr_1st_irqena_3 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTRRDYEN 2 i2csr_1st_irqena_2 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTROEEN 1 i2csr_1st_irqena_1 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQHGCEN 0 i2csr_1st_irqena_0 ../efb_top/efb_pll_sci_inst/u_efb_sci/
Table 17-15. I2
C Secondary Simulation Model
I
2
C Secondary
Register Name
Register
Size/Bit
Location
Register
Function
Address I2
C
Secondary Access
Simulation Model
Register Name Simulation Model Register Path
I2C_2_CR [7:0] Control 0x4A Read/Write i2ccr1[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2CEN 7 i2c_en ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
GCEN 6 i2c_gcen ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
WKUPEN 5 i2c_wkupen ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
SDA_DEL_SEL[1:0] [3:2] sda_del_sel ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_2_CMDR [7:0] Command 0x4B Read/Write i2ccmdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
STA 7 i2c_sta ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
Table 17-14. I2
C Primary Simulation Mode (Continued)
I
2
C Primary
Register Name
Register
Size/Bit
Location
Register
Function
Address I2
C
Primary Access
Simulation Model
Register Name Simulation Model Register Path17-20
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
STO 6 i2c_sto ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
RD 5 i2c_rd ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
WR 4 i2c_wt ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
ACK 3 i2c_nack ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
CKSDIS 2 i2c_cksdis ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_2_BR0 [7:0] Clock Pre-scale 0x4C Read/Write i2cbr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_PRESCALE[7:0] [7:0] i2cbr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_2_BR1 [7:0] Clock Pre-scale 0x4D Read/Write i2cbr[9:8] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_PRESCALE[9:8] [1:0] i2cbr[9:8] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_2_TXDR [7:0] Transmit Data 0x4E Write i2ctxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_Transmit_Data[7:0] [7:0] i2ctxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_2_SR [7:0] Status 0x4F Read i2csr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
TIP 7 i2c_tip_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
BUSY 6 i2c_busy_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
RARC 5 i2c_rarc_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
SRW 4 i2c_srw_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
ARBL 3 i2c_arbl ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
TRRDY 2 i2c_trrdy ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
TROE 1 i2c_troe ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
HGC 0 i2c_hgc ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_2_GCDR [7:0] General Call 0x50 Read i2cgcdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_GC_Data[7:0] [7:0] i2cgcdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_2_RXDR [7:0] Receive Data 0x51 Read i2crxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_Receive_Data[7:0] [7:0] i2crxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/i2c_2nd/
I2C_2_IRQ [7:0] IRQ 0x52 Read/Write
{1'b0, 1'b0, 1'b0, 1'b0,
i2csr_2nd_irqsts_3,
i2csr_2nd_irqsts_2,
i2csr_2nd_irqsts_1,
i2csr_2nd_irqsts_0}
../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQARBL 3 i2csr_2nd_irqsts_3 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTRRDY 2 i2csr_2nd_irqsts_2 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTROE 1 i2csr_2nd_irqsts_1 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQHGC 0 i2csr_2nd_irqsts_0 ../efb_top/efb_pll_sci_inst/u_efb_sci/
I2C_2_IRQEN [7:0] IRQ Enable 0x53 Read/Write
{1'b0, 1'b0, 1'b0, 1'b0,
i2csr_2nd_irqena_3,
i2csr_2nd_irqena_2,
i2csr_2nd_irqena_1,
i2csr_2nd_irqena_0}
../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQARBLEN 3 i2csr_2nd_irqena_3 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTRRDYEN 2 i2csr_2nd_irqena_2 ../efb_top/efb_pll_sci_inst/u_efb_sci/
Table 17-15. I2
C Secondary Simulation Model (Continued)
I
2
C Secondary
Register Name
Register
Size/Bit
Location
Register
Function
Address I2
C
Secondary Access
Simulation Model
Register Name Simulation Model Register Path17-21
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Hardened SPI IP Core
The MachXO2 EFB contains a hard SPI IP core that can be configured as a SPI Master or Slave. When the SPI
core is configured as a Master it is able to control other devices with Slave SPI interfaces that are connected to the
SPI bus. When the SPI core is configured as a Slave, it is able to interface to an external SPI Master device.
SPI Registers
The SPI core communicates with the WISHBONE interface through a set of control, command, status and data
registers. Table 17-16 shows the register names and their functions. These registers are a subset of the EFB register map.
Table 17-16. SPI Registers
Table 17-17. SPI Control 0
TIdle_XCNT[1:0] Idle Delay Count. Specifies the minimum interval prior to the Master Chip Select low
assertion (Master Mode only), in SCK periods.
00: ½
01: 1
10: 1.5
11: 2
TTrail_XCNT[2:0] Trail Delay Count. Specifies the minimum interval between the last edge of SCK and
the high deassertion of Master Chip Select (Master Mode only), in SCK periods.
000: ½
001: 1
IRQTROEEN 1 i2csr_2nd_irqena_1 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQHGCEN 0 i2csr_2nd_irqena_0 ../efb_top/efb_pll_sci_inst/u_efb_sci/
SPI Register Name Register Function Address Access
SPICR0 Control Register 0 0x54 Read/Write
SPICR1 Control Register 1 0x55 Read/Write
SPICR2 Control Register 2 0x56 Read/Write
SPIBR Clock Pre-scale 0x57 Read/Write
SPICSR Master Chip Select 0x58 Read/Write
SPITXDR Transmit Data 0x59 Write
SPISR Status 0x5A Read
SPIRXDR Receive Data 0x5B Read
SPIIRQ Interrupt Request 0x5C Read/Write
SPIIRQEN Interrupt Request Enable 0x5D Read/Write
Note: Unless otherwise specified, all Reserved bits in writable registers shall be written ‘0’.
SPICR0 0x54
Bit 7 6 5 4 3 2 1 0
Name TIdle_XCNT[1:0] TTrail_XCNT[2:0] TLead_XCNT[2:0]
Default 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: A write to this register will cause the SPI core to reset.
Table 17-15. I2
C Secondary Simulation Model (Continued)
I
2
C Secondary
Register Name
Register
Size/Bit
Location
Register
Function
Address I2
C
Secondary Access
Simulation Model
Register Name Simulation Model Register Path17-22
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
010: 1.5
…
111: 4
TLead_XCNT[2:0] Lead Delay Count. Specifies the minimum interval between the Master Chip Select
low assertion and the first edge of SCK (Master Mode only), in SCK periods.
000: ½
001: 1
010: 1.5
…
111: 4
Table 17-18. SPI Control 1
SPE This bit enables the SPI core functions. If SPE is cleared, SPI is disabled and forced
into idle state.
0: SPI disabled
1: SPI enabled, port pins are dedicated to SPI functions.
WKUPEN_USER Wake-up Enable via User. Enables the SPI core to send a wake-up signal to the onchip Power Controller to wake the part from Standby mode when the User slave SPI
chip select (spi_scsn) is driven low.
0: Wakeup disabled
1: Wakeup enabled.
WKUPEN_CFG Wake-up Enable Configuration. Enables the SPI core to send a wake-up signal to the
on-chip power controller to wake the part from standby mode when the Configuration
slave SPI chip select (ufm_sn) is driven low.
0: Wakeup disabled
1: Wakeup enabled.
TXEDGE Data Transmit Edge. Enables Lattice proprietary extension to the SPI protocol. Selects
which clock edge to transmit SPI data. Refer to Figures 17-25 through 17-28.
0: Transmit data on the MCLK edge defined by SPICR2[CPOL] and
SPICR2[CPHA]
1: Transmit data ½ MCLK earlier than defined by SPICR2[CPOL] and
SPICR2[CPHA]
Table 17-19. SPI Control 2
SPICR1 0x55
Bit 7 6 5 4 3 2 1 0
Name SPE WKUPEN_USER WKUPEN_CFG TXEDGE (Reserved)
Default 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W — — — —
Note: A write to this register will cause the SPI core to reset.
SPICR2 0x56
Bit 7 6 5 4 3 2 1 0
Name MSTR MCSH SDBRE (Reserved) (Reserved) CPOL CPHA LSBF
Default 0 0 0 0 0000
Access R/W R/W R/W — — R/W R/W R/W
Note: A write to this register will cause the SPI core to reset.17-23
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
MSTR SPI Master/Slave Mode. Selects the Master/Slave operation mode of the SPI core.
Changing this bit forces the SPI system into idle state.
0: SPI is in Slave mode
1: SPI is in Master mode
MCSH SPI Master CSSPIN Hold. Holds the Master chip select active when the host is busy,
to halt the data transmission without de-asserting chip select.
Note: This mode must be used only when the WISHBONE clock has been divided by
a value greater than four (4) (greater than six (6) for R1 devices). For more details on
the R1 to Standard migration refer to AN8086, Designing for Migration from
MachXO2-1200-R1 to Standard (Non-R1) Devices.
0: Master running as normal
1: Master holds chip select low even if there is no data to be transmitted
SDBRE Slave Dummy Byte Response Enable. Enables Lattice proprietary extension to the
SPI protocol. For use when the internal support circuit (e.g. WISHBONE host) cannot
respond with initial data within the time required, and to make the slave read out data
predictably available at high SPI clock rates.
When enabled, dummy 0xFF bytes will be transmitted in response to a SPI slave read
(while SPISR[TRDY]=1) until an initial write to SPITXDR. Once a byte is written into
SPITXDR by the WISHBONE host, a single byte of 0x00 will be transmitted then followed immediately by the data in SPITXDR. In this mode, the external SPI master
should scan for the initial 0x00 byte when reading the SPI slave to indicate the beginning of actual data. Refer to Figure 17-19.
0: Normal Slave SPI operation
1: Lattice proprietary Slave Dummy Byte Response Enabled
Note: This mechanism only applies for the initial data delay period. Once the initial
data is available, subsequent data must be supplied to SPITXDR at the required SPI
bus data rate.
CPOL SPI Clock Polarity. Selects an inverted or non-inverted SPI clock. To transmit data
between SPI modules, the SPI modules must have identical SPICR2[CPOL] values. In
master mode, a change of this bit will abort a transmission in progress and force the
SPI system into idle state. Refer to Figures 17-25 through 17-28.
0: Active-high clocks selected. In idle state SCK is low.
1: Active-low clocks selected. In idle state SCK is high.
CPHA SPI Clock Phase. Selects the SPI clock format. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state. Refer to
Refer to Figures 17-25 through 17-28.
0: Data is captured on a leading (first) clock edge, and propagated on the
opposite clock edge.
1: Data is captured on a trailing (second) clock edge, and propagated on the
opposite clock edge*.
Note: When CPHA=1, the user must explicitly place a pull-up or pull-down on SCK
pad corresponding to the value of CPOL (e.g. when CPHA=1 and CPOL=0 place a
pull-down on SCK). When CPHA=0, the pull direction may be set arbitrarily.
Slave SPI Configuration mode supports default setting only for CPOL, CPHA.
LSBF LSB-First. LSB appears first on the SPI interface. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state. Refer to 17-24
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figures 17-25 through 17-28.
Note: This bit does not affect the position of the MSB and LSB in the data register.
Reads and writes of the data register always have the MSB in bit 7.
0: Data is transferred most significant bit (MSB) first
1: Data is transferred least significant bit (LSB) first
Table 17-20. SPI Clock Prescale
DIVIDER[5:0] SPI Clock Prescale value. The WISHBONE clock frequency is divided by
(DIVIDER[5:0] + 1) to produce the desired SPI clock frequency. A write operation to
this register will cause a SPI core reset. DIVIDER must be >= 1.
Note: The digital value is calculated by IPexpress when the SPI core is configured in
the SPI tab of the EFB GUI. The calculation is based on the WISHBONE Clock Frequency and the SPI Frequency, both entered by the user. The digital value of the
divider is programmed in the MachXO2 device during device programming. After
power-up or device reconfiguration, the data is loaded onto the SPIBR register.
Register SPIBR has Read/Write access from the WISHBONE interface. Designers
can update the clock pre-scale register dynamically during device operation.
Table 17-21. SPI Master Chip Select
CSN_[7:0] SPI Master Chip Selects. Used in master mode for asserting a specific Master Chip
Select (MCSN) line. The register has eight bits, enabling the SPI core to control up to
eight external SPI slave devices Each bit represents one master chip select line
(Active-Low). Bits [7:1] may be connected to any I/O pin via the FPGA fabric. Bit 0 has
a pre-assigned pin location. The register has Read/Write access from the WISHBONE
interface. A write operation on this register will cause the SPI core to reset.
Table 17-22. SPI Transmit Data Register
SPIBR 0x57
Bit 7 6 5 4 3 2 1 0
Name (Reserved) DIVIDER[5:0]
Default1
0 0000000
Access — — R/W R/W R/W R/W R/W R/W
1. Hardware default value may be overridden by EFB component instantiation parameters. See discussion below.
SPICSR 0x58
Bit 7 6 5 4 3 2 1 0
Name CSN_7 CSN_6 CSN_5 CSN_4 CSN_3 CSN_2 CSN_1 CSN_0
Default 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
SPITXDR 0x59
Bit 7 6 5 4 3 2 1 0
Name SPI_Transmit_Data[7:0]
Default — — — — — — — —
Access W W W W W W W W17-25
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
SPI_Transmit_Data[7:0] SPI Transmit Data. This register holds the byte that will be transmitted on the SPI bus.
Bit 0 in this register is LSB, and will be transmitted last when SPICR2[LSBF]=0 or first
when SPICR2[LSBF]=1.
Note: When operating as a Slave, SPITXDR must be written when SPISR[TRDY] is '1'
and at least 0.5 CCLKs before the first bit is to appear on SO. For example, when
CPOL = CPHA = TXEDGE = LSBF = 0, SPITXDR must be written prior to the CCLK
rising edge used to sample the LSB (bit 0) of the previous byte. See Figure 17-25.
This timing requires at least one protocol dummy byte be included for all slave SPI
read operations.
Table 17-23. SPI Status
TIP SPI Transmitting In Progress. Indicates the SPI port is actively transmitting/receiving
data.
0: SPI Transmitting complete
1: SPI Transmitting in progress*
Note: This bit is non-functional in R1 devices. For more details on the R1 to Standard
migration refer to AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (Non-R1) Devices.
TRDY SPI Transmit Ready. Indicates the SPI transmit data register (SPITXDR) is empty. This
bit is cleared by a write to SPITXDR. This bit is capable of generating an interrupt.
0: SPITXDR is not empty
1: SPITXDR is empty
RRDY SPI Receive Ready. Indicates the receive data register (SPIRXDR) contains valid
receive data. This bit is cleared by a read access to SPIRXDR. This bit is capable of
generating an interrupt.
0: SPIRXDR does not contain data
1: SPIRXDR contains valid receive data
ROE Receive Overrun Error. Indicates SPIRXDR received new data before the previous
data was read. The previous data is lost. This bit is capable of generating an interrupt.
0: Normal
1: Receiver Overrun detected
MDF Mode Fault. Indicates the Slave SPI chip select (spi_scsn) was driven low while
SPICR2[MSTR]=1. This bit is cleared by any write to SPICR0, SPICR1 or SPICR2.
This bit is capable of generating an interrupt.
0: Normal
1: Mode Fault detected
SPISR 0x5A
Bit 7 6 5 4 3 2 1 0
Name TIP (Reserved) TRDY RRDY (Reserved) ROE MDF
Default 0 — —0 0 —0 0
Access R — —RR —RR17-26
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-24. SPI Receive Data Register
SPI_Receive_Data[7:0] SPI Receive Data. This register holds the byte captured from the SPI bus. Bit 0 in this
register is LSB and was received last when LSBF=0 or first when LSBF=1.
Table 17-25. SPI Interrupt Status
IRQTRDY Interrupt Status for SPI Transmit Ready.
When enabled, indicates SPISR[TRDY] was asserted. Write a ‘1’ to this bit to clear the
interrupt.
1: SPI Transmit Ready Interrupt
0: No interrupt
IRQRRDY Interrupt Status for SPI Receive Ready.
When enabled, indicates SPISR[RRDY] was asserted. Write a ‘1’ to this bit to clear
the interrupt.
1: SPI Receive Ready Interrupt
0: No interrupt
IRQROE Interrupt Status for Receive Overrun Error.
When enabled, indicates ROE was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Receive Overrun Error Interrupt
0: No interrupt
IRQMDF Interrupt Status for Mode Fault.
When enabled, indicates MDF was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Mode Fault Interrupt
0: No interrupt
Table 17-26. SPI Interrupt Enable
IRQTRDYEN Interrupt Enable for SPI Transmit Ready.
1: Interrupt generation enabled
0: Interrupt generation disabled
SPIRXDR 0x5B
Bit 7 6 5 4 3 2 1 0
Name SPI_Receive_Data[7:0]
Default 0 0 0 0 0 0 0 0
Access R R R R R R R R
SPIIRQ 0x5C
Bit 7 6 5 4 3 2 1 0
Name (Reserved) IRQTRDY IRQRRDY (Reserved) IRQROE IRQMDF
Default — — —0 0 —0 0
Access — — — R/W R/W — R/W R/W
SPIIRQEN 0x5D
Bit 7 6 5 4 3 2 1 0
Name (Reserved) IRQTRDYEN IRQRRDYEN (Reserved) IRQROEEN IRQMDFEN
Default 0 0 000 000
Access — — — R/W R/W — R/W R/W17-27
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
IRQRRDYEN Interrupt Enable for SPI Receive Ready
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQROEEN Interrupt Enable for Receive Overrun Error
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQMDFEN Interrupt Enable for Mode Fault
1: Interrupt generation enabled
0: Interrupt generation disabled
Figure 17-15 shows a flow diagram for controlling Master SPI reads and writes initiated via the WISHBONE interface.17-28
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-15. SPI Master Read/Write Example (via WISHBONE) – Production Silicon
Start
CR2 <= 0xC0
wait for TRDY
Done?
Read data?
TXDR <= SPI Write Data TXDR <= 0x00
wait for RRDY
SPI Read Data <= RXDR
Y
N
Y
N
wait for RRDY
Discard Data <= RXDR
Last Read?
CR2 <= 0x80
Y
N
wait for not TIP
Done17-29
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-16. SPI Master Read/Write Example (via WISHBONE) – R1 Silicon
Note: For more details on the R1 to Standard migration refer to AN8086, Designing for Migration from MachXO2-
1200-R1 to Standard (Non-R1) Devices.
Start
CR2 <= 0xC0
wait for TRDY
TXDR <= SPI Command Byte
Done?
Read data?
TXDR <= SPI Write Data
Done
Discard Data <= RXDR
TXDR <= 0x00
wait for RRDY
TXDR <= 0x00
wait for RRDY
SPI Read Data <= RXDR
Y
N
Y
N
Y
N
wait for RRDY
Discard Data <= RXDR Last Read?
CR2 <= 0x80 17-30
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
SPI Framing
Each command string sent to the SPI EFB port must be correctly ‘framed’ using the protocol defined for each interface. In the case of SSPI the protocol is well known and defined by the industry as shown below:
Table 17-27. Command Framing Protocol, by Interface
Figure 17-17. SSPI Read Device ID Example
Interface Pre-op (+) Command String Post-op (-)
SPI Assert CS (Command/Operands/Data) De-assert CS
111000000000000000000000
CMD Byte Op Byte 1 Op Byte 2
SN
CCLK
SI
SO
...
...
...
...
00000000
Op Byte 3 Read ID Byte 1 Read ID Byte 2
SN
(continued)
CCLK
(continued)
SI
(continued)
SO
(continued)
...
...
...
...
ID ID ID ID 0 0 0 0 0 1 0 0 0 0 1 1
Read ID Byte 3 Read ID Byte 4
SN
(continued)
CCLK
(continued)
SI
(continued)
SO
(continued)
000000010010101 117-31
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
SPI Functional Waveforms
Figure 17-18. Fully Specified SPI Transaction
Figure 17-19. Minimally Specified SPI Transaction
R1 from SI
to SPIRXDR
(auto)
T1 written to
SPITXDR via
WISHBONE
(user)
T1 from
SPITXDR to SO
(auto)
T1 T2 T3 T4 T5 T6 T7 T8
T1 T2 T3 T4 T5 T6 T7 T8
R1 R2 R3 R4 R5 R6 R7 R8
R1 R2 R3 R4 R5 R6 R7 R8
SPISR[RRDY]
SPIRXDR
SPISR[TIP]
SI
SO
SCSN
SPITXDR
SPISR[TRDY]
R1 read from
SPIRXDR via
WISHBONE
(user)
Addr read from
SPIRXDR via
WISHBONE
(user)
Flush SPIRXDR
via WISHBONE
(user)
Quit reading SPIRXDR (data is “don’t care”)
CMD read from
SPIRXDR via
WISHBONE
(user)
0x08 addr dum
0x08 addr dum
old
old dum1 dum2 D1 D2 D3 D4 D5
FF* dum2 D1 D2 D3 D4 D5
Command Reply to Command
After SPISR[TIP] detected,
write dummy to SPITXDR
(user)
After CMD/Addr decode,
write good to SPITXDR
(user)
*Note: If SPITXDR is ‘empty’ at the start of a transaction,
the second byte will be ‘FF’ (silicon limitation).
Must write dummy byte in first byte period to get
good Tx data in third period (dummy data may be
overwritten in second period if necessary).
SPISR[TRDY]
SPISR[TRDY]
SPIRXDR
SPISR[TIP]
SI
SO
SCSN
SPITXDR
SPISR[TRDY]17-32
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
SPI Timing Diagrams
Figure 17-20. SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=0)
Figure 17-21. SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=0)
MCLK/CCLK
(CPOL=0)
MCLK/CCLK
(CPOL=1)
SPISO or SI
SISPI or SO
CSSPIN/SCSN/SN
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
bit6
bit1
bit5
bit2
bit4
bit3
bit3
bit4
bit2
bit5
bit1
bit6 MSB
LSB
tL tT tI tL
tL = TLead_XCNT
tT = TTrail_XCNT
tL = Tidle_XCNT
sample instants
*Note: MachXO2 SPI configuration modes only support
CPHA = CPOL = LSBF = TXEDGE = 0
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
bit6
bit1
bit5
bit2
bit4
bit3
bit3
bit4
bit2
bit5
bit1
bit6 MSB
LSB
tL tT tI tL
tL = TLead_XCNT
tT = TTrail_XCNT
tL = Tidle_XCNT
sample instants
MCLK/CCLK
(CPOL=0)
MCLK/CCLK
(CPOL=1)
SPISO or SI
SISPI or SO
CSSPIN or SCSN17-33
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-22. SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=1)
Figure 17-23. SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=1)
Figure 17-24. Slave SPI Dummy Byte Response (SPICR2[SDBRE]) Timing
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
bit6
bit1
bit5
bit2
bit4
bit3
bit3
bit4
bit2
bit5
bit1
bit6 MSB
LSB
tL tT tI tL
tL = TLead_XCNT
tT = TTrail_XCNT
tL = Tidle_XCNT
sample instants
MCLK/CCLK
(CPOL=0)
MCLK/CCLK
(CPOL=1)
SPISO or SI
SISPI or SO
CSSPIN or SCSN
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
bit6
bit1
bit5
bit2
bit4
bit3
bit3
bit4
bit2
bit5
bit1
bit6 MSB
LSB
tL tT tI tL
tL = TLead_XCNT
tT = TTrail_XCNT
tL = Tidle_XCNT
sample instants
MCLK/CCLK
(CPOL=0)
MCLK/CCLK
(CPOL=1)
SPISO or SI
SISPI or SO
CSSPIN or SCSN
SI(MOSI)
SO(MISO)
CS(SS)
FF FF FF FF FF
CMD OP1 OP2 OP3 FF FF FF FF FF FF
FF 00 D1 D2 D3
Receiving Read Command SPITXDR
NOT Ready
SPITXDR
Ready DATA Read Out17-34
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
SPI Simulation Model
The SPI EFB Register Map translation to the MachXO2 EFB software simulation model is provided below.
Table 17-28. SPI Simulation Model
SPI Register Name
Register
Size/Bit
Location Register Function Address Access
Simulation
Model
Register Name Simulation Model Register Path
SPICR0 [7:0] Control Register 0 0x54 Read/Write spicr0[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
TIdle_XCNT[1:0] [7:6] spicr0[7:6] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
TTrail_XCNT[2:0] [5:3] spicr0[5:3] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
TLead_XCNT[2:0] [2:0] spicr0[2:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPICR1 [7:0] Control Register 1 0x55 Read/Write spicr1[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPE 7 spi_en ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
WKUPEN_USER 6 spi_wkup_usr ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
WKUPEN_CFG 5 spi_wkup_cfg ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
TXEDGE 4 spi_tx_edge ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPICR2 [7:0] Control Register 2 0x56 Read/Write spicr2[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
MSTR 7 spi_mstr ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
MCSH 6 spi_mcsh ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SDBRE 5 spi_srme ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CPOL 2 spi_cpol ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CPHA 1 spi_cpha ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
LSBF 0 spi_lsbf ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPIBR [7:0] Clock Pre-scale 0x57 Read/Write spibr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
DIVIDER[5:0] [5:0] spibr[5:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPICSR [7:0] Master Chip Select 0x58 Read/Write spicsr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CSN_7 7 spicsr[7] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CSN_6 6 spicsr[6] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CSN_5 5 spicsr[5] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CSN_4 4 spicsr[4] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CSN_3 3 spicsr[3] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CSN_2 2 spicsr[2] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CSN_1 1 spicsr[1] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
CSN_0 0 spicsr[0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPITXDR [7:0] Transmit Data 0x59 Write spitxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPI_Transmit_Data[7:0] [7:0] spitxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/17-35
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
SPISR [7:0] Status 0x5A Read spisr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
TIP 7 spi_tip_sync ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
TRDY 4 spi_trdy ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
RRDY 3 spi_rrdy ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
ROE 1 spi_roe ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
MDF 0 spi_mdf ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPIRXDR [7:0] Receive Data 0x5B Read spirxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPI_Receive_Data[7:0] [7:0] spirxdr[7:0] ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/
njport_unit/spi_port/
SPIIRQ [7:0] Interrupt Request 0x5C Read/Write
{1'b0, 1'b0, 1'b0,
spisr_irqsts_4,
spisr_irqsts_3,
spisr_irqsts_2,
spisr_irqsts_1,
spisr_irqsts_0}
../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTRDY 4 spisr_irqsts_4 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQRRDY 3 spisr_irqsts_3 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQROE 1 spisr_irqsts_1 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQMDF 0 spisr_irqsts_0 ../efb_top/efb_pll_sci_inst/u_efb_sci/
SPIIRQEN [7:0] Interrupt Request Enable 0x5D Read/Write
{1'b0, 1'b0, 1'b0,
spisr_irqena_4,
spisr_irqena_3,
spisr_irqena_2,
spisr_irqena_1,
spisr_irqena_0}
../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQTRDYEN 4 spisr_irqena_4 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQRRDYEN 3 spisr_irqena_3 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQROEEN 1 spisr_irqena_1 ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQMDFEN 0 spisr_irqena_0 ../efb_top/efb_pll_sci_inst/u_efb_sci/
Table 17-28. SPI Simulation Model
SPI Register Name
Register
Size/Bit
Location Register Function Address Access
Simulation
Model
Register Name Simulation Model Register Path17-36
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Hardened Timer/Counter PWM
The MachXO2 EFB contains a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional,
16-bit Timer/Counter module with independent output compare units and PWM support.
Timer/Counter Registers
The Timer/Counter communicates with the FPGA logic through the WISHBONE interface, by utilizing a set of control, status and data registers. Table 17-29 shows the register names and their functions. These registers are a
subset of the EFB register map. Refer to the EFB register map for specific addresses of each register.
Table 17-29. Timer/Counter Registers
Table 17-30. Timer/Counter Control 0
RSTEN Enables the reset signal (tc_rstn) to enter the Timer/Counter core from the PLD logic.
1: External reset enabled
0: External reset disabled
PRESCALE[2:0] Used to divide the clock input to the Timer/Counter
000: Static (clock disabled)
001: Divide by 1
010: Divide by 8
011: Divide by 64
Timer/Counter
Register Name Register Function Address Access
TCCR0 Control Register 0 0x5E Read/Write
TCCR1 Control Register 1 0x5F Read/Write
TCTOPSET0 Set Top Counter Value [7:0] 0x60 Write
TCTOPSET1 Set Top Counter Value [15:8] 0x61 Write
TCOCRSET0 Set Compare Counter Value [7:0] 0x62 Write
TCOCRSET1 Set Compare Counter Value [15:8] 0x63 Write
TCCR2 Control Register 2 0x64 Read/Write
TCCNT0 Counter Value [7:0] 0x65 Read
TCCNT1 Counter Value [15:8] 0x66 Read
TCTOP0 Current Top Counter Value [7:0] 0x67 Read
TCTOP1 Current Top Counter Value [15:8] 0x68 Read
TCOCR0 Current Compare Counter Value [7:0] 0x69 Read
TCOCR1 Current Compare Top Counter Value [15:8] 0x6A Read
TCICR0 Current Capture Counter Value [7:0] 0x6B Read
TCICR1 Current Capture Counter Value [15:8] 0x6C Read
TCSR0 Status Register 0x6D Read
TCIRQ Interrupt Request 0x6E Read/Write
TCIRQEN Interrupt Request Enable 0x6F Read/Write
Note: Unless otherwise specified, all Reserved bits in writable registers shall be written ‘0’.
TCCR0 0x5E
Bit 7 6 5 4 3 2 1 0
Name RSTEN (Reserved) PRESCALE[2:0] CLKEDGE CLKSEL (Reserved)
Default 0 0 0 00 0
Access R/W — R/W R/W R/W R/W17-37
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
100: Divide by 256
101: Divide by 1024
110: (Reserved setting)
111: (Reserved setting)
CLKEDGE Used to select the edge of the input clock source. The Timer/Counter will update
states on the edge of the input clock source.
0: Rising Edge
1: Falling Edge
CLKSEL Defines the source of the input clock.
0: Clock Tree
1: On-chip Oscillator
Table 17-31. Timer/Counter Control 1
SOVFEN Enables the overflow flag to be used with the interrupt output signal. It is set when the
Timer/Counter is standalone, with no WISHBONE interface.
0: Disabled
1: Enabled
Note: When this bit is set, other flags such as the OCRF and ICRF will not be routed to
the interrupt output signal.
ICEN Enables the ability to perform a capture operation of the counter value. Users can
assert the “tc_ic” signal and load the counter value onto the TCICR0/1 registers. The
captured value can serve as a timer stamp for a specific event.
0: Disabled
1: Enabled
TSEL Enables the auto-load of the counter with the value from TCTOPSET0/1. When disabled, the value 0xFFFF is auto-loaded.
0: Disabled
1: Enabled
OCM[1:0] Select the function of the output signal of the Timer/Counter. The available functions
are Static, Toggle, Set/Clear and Clear/Set.
All Timer/Counter modes:
00: The output is static low
In non-PWM modes:
01: Toggle on TOP match
In Fast PWM mode:
10: Clear on TOP match, Set on OCR match
11: Set on TOP match, Clear on OCR match
In Phase and Frequency Correct PWM mode:
10: Clear on OCR match when the counter is incrementing
TCCR1 0x5F
Bit 7 6 5 4 3 2 1 0
Name (Reserved) SOVFEN ICEN TSEL OCM[1:0] TCM[1:0]
Default 0000 0 0
Access — R/W R/W R/W R/W R/W17-38
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Set on OCR match when counter is decrementing
11: Set on OCR match when the counter is incrementing
Clear on OCR match when the counter is decrementing
TCM[1:0] Timer Counter Mode. Defines the mode of operation for the Timer/Counter.
00: Watchdog Timer Mode
01: Clear Timer on Compare Match Mode
10: Fast PWM Mode
11: Phase and Frequency Correct PWM Mode
Table 17-32. Timer/Counter Set Top Counter Value 0
Table 17-33. Timer/Counter Set Top Counter Value 1
The value from TCTOPSET0/1 is loaded to the TCTOP0/1 registers once the counter has completed the current
counting cycle. Refer to the Timer/Counter Modes of Operation section for usage details.
TCTOPSET0 register holds the lower eight bits [7:0] of the top value. TCTOPSET1 register holds the upper eight
bits [15:8] of the top value.
Table 17-34. Timer/Counter Set Compare Counter Value 0
Table 17-35. Timer/Counter Set Compare Counter Value 1
TCTOPSET0 0x60
Bit 7 6 5 4 3 2 1 0
Name TCTOPSET[7:0]
Default1
11111111
Access R/W R/W R/W R/W R/W R/W R/W R/W
1. Hardware default value may be overridden by EFB component instantiation parameters.
TCTOPSET1 0x61
Bit 7 6 5 4 3 2 1 0
Name TCTOPSET[15:8]
Default1
11111111
Access R/W R/W R/W R/W R/W R/W R/W R/W
1. Hardware default value may be overridden by EFB component instantiation parameters.
TCOCRSET0 0x62
Bit 7 6 5 4 3 2 1 0
Name TCOCRSET[7:0]
Default1
11111111
Access R/W R/W R/W R/W R/W R/W R/W R/W
1. Hardware default value may be overridden by EFB component instantiation parameters.
TCOCRSET1 0x63
Bit 7 6 5 4 3 2 1 0
Name TCOCRSET[15:8]
Default1
11111111
Access R/W R/W R/W R/W R/W R/W R/W R/W
1. Hardware default value may be overridden by EFB component instantiation parameters.17-39
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
The value from TCOCRSET0/1 is loaded to the TCOCR0/1 registers once the counter has completed the current
counting cycle. Refer to the Timer/Counter Modes of Operation section for usage details.
TCOCRSET0 register holds the lower 8 bits [7:0] of the compare value. TCOCRSET1 register holds the upper
eight bits [15:8] of the compare value.
Table 17-36. Timer/Counter Control 2
WBFORCE In non-PWM modes, forces the output of the counter, as if the counter value matched
the compare (TCOCR) value or it matched the top value (TCTOP).
0: Disabled
1: Enabled
WBRESET Reset the counter from the WISHBONE interface by writing a '1' to this bit. Manually
reset to ‘0’. The rising edge is detected in the WISHBONE clock domain, and the
counter is reset synchronously on the next tc_clki. Due to the clock domain crossing,
there is a one-clock uncertainty when the reset is effective. This bit has higher priority
then WBPAUSE.
0: Disabled
1: Enabled
WBPAUSE Pause the 16-bit counter
1: Pause
0: Normal
Table 17-37. Timer/Counter Counter Value 0
Table 17-38. Timer/Counter Counter Value 1
Registers TCCNT0 and TCCNT1 are 8-bit registers, which combined, hold the counter value. The WISHBONE
host has read-only access to these registers.
TCCNT0 register holds the lower 8-bit value [7:0] of the counter value. TCCNT1 register holds the upper 8-bit value
[15:8] of the counter value.
TCCR2 0x64
Bit 7 6 5 4 3 2 1 0
Name (Reserved) WBFORCE WBRESET WBPAUSE
Default 0 0 0 0 0000
Access — — — — — R/W R/W R/W
TCCNT0 0x65
Bit 7 6 5 4 3 2 1 0
Name TCCNT[7:0]
Default 0 0 0 0 0 0 0 0
Access R R R R R R R R
TCCNT1 0x66
Bit 7 6 5 4 3 2 1 0
Name TCCNT[15:8]
Default 0 0 0 0 0 0 0 0
Access R R R R R R R R17-40
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-39. Timer/Counter Current Top Counter Value 0
Table 17-40. Timer/Counter Current Top Counter Value 1
Registers TCTOP0 and TCTOP1 are 8-bit registers, which combined, receive a 16-bit value from the TCTOPSET0/1. The data stored in these registers represents the top value of the counter. The registers update once the
counter has completed the current counting cycle. The WISHBONE host has read-only access to these registers.
Refer to the Timer/Counter Modes of Operation section for usage details.
TCTOP0 register holds the lower 8-bit value [7:0] of the top value. TCTOP1 register holds the upper 8-bit value
[15:8] of the top value.
Table 17-41. Timer/Counter Current Compare Counter Value 0
Table 17-42. Timer/Counter Current Compare Counter Value 1
Registers TCOCR0 and TCOCR1 are 8-bit registers, which combined, receive a 16-bit value from the TCOCRSET0/1. The data stored in these registers represents the compare value of the counter. The registers update
once the counter has completed the current counting cycle. The WISHBONE host has read-only access to these
registers. Refer to the Timer/Counter Modes of Operation section for usage details.
TCOCR0 register holds the lower 8-bit value [7:0] of the compare value. TCOCR1 register holds the upper 8-bit
value [15:8] of the compare value.
TCTOP0 0x67
Bit 7 6 5 4 3 2 1 0
Name TCTOP[7:0]
Default 1 1 1 1 1 1 1 1
Access R R R R R R R R
TCTOP1 0x68
Bit 7 6 5 4 3 2 1 0
Name TCTOP[15:8]
Default 1 1 1 1 1 1 1 1
Access R R R R R R R R
TCOCR0 0x69
Bit 7 6 5 4 3 2 1 0
Name TCOCR[7:0]
Default 1 1 1 1 1 1 1 1
Access R R R R R R R R
TCOCR1 0x6A
Bit 7 6 5 4 3 2 1 0
Name TCOCR[15:8]
Default 1 1 1 1 1 1 1 1
Access R R R R R R R R17-41
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-43. Timer/Counter Current Capture Counter Value 0
Table 17-44. Timer/Counter Current Capture Counter Value 1
Registers TCICR0 and TCICR1 are 8-bit registers, which combined, can hold the counter value. The counter value
is loaded onto these registers once a trigger event, tc_ic IP signal, is asserted. The capture value is commonly
used as a time-stamp for a specific system event. The WISHBONE host has read-only access to these registers.
TCICR0 register holds the lower 8-bit value [7:0] of the counter value. TCICR1 register holds the upper 8-bit value
[15:8] of the counter value.
Table 17-45. Timer/Counter Status Register
BTF Bottom Flag. Asserted when the counter reaches value zero. A write operation to this
register clears this flag.
1: Counter reached zero value
0: Counter has not reached zero
ICRF Capture Counter Flag. Asserted when the user asserts the TC_IC input signal. The
counter value is captured into the TCICR0/1 registers. A write operation to this register
clears this flag. This bit is capable of generating an interrupt.
1: TC_IC signal asserted.
0: Normal
OCRF Compare Match Flag. Asserted when counter matches the TCOCR0/1 register value.
A write operation to this register clears this flag. This bit is capable of generating an
interrupt.
1: Counter match
0: Normal
OVF Overflow Flag. Asserted when the counter matches the TCTOP0/1 register value. A
write operation to this register clears this flag. This bit is capable of generating an
interrupt.
1: Counter match
0: Normal
TCICR0 0x6B
Bit 7 6 5 4 3 2 1 0
Name TCICR[7:0]
Default 0 0 0 0 0 0 0 0
Access R R R R R R R R
TCICR1 0x6C
Bit 7 6 5 4 3 2 1 0
Name TCICR[15:8]
Default 0 0 0 0 0 0 0 0
Access R R R R R R R R
TCSR 0x6D
Bit 7 6 5 4 3 2 1 0
Name (Reserved) BTF ICRF OCRF OVF
Default — — — —0 0 0 0
Access — — — —R RRR17-42
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-46. Timer/Counter Interrupt Status
IRQICRF Interrupt Status for Capture Counter Flag.
When enabled, indicates ICRF was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Capture Counter Flag Interrupt
0: No interrupt
IRQOCRF Interrupt Status for Compare Match Flag.
When enabled, indicates OCRF was asserted. Write a ‘1’ to this bit to clear the interrupt. Note the interrupt line is asserted for only 1 clock cycle.
1: Compare Match Flag Interrupt
0: No interrupt
IRQOVF Interrupt Status for Overflow Flag.
When enabled, indicates OVF was asserted. Write a ‘1’ to this bit to clear the interrupt.
Note the interrupt line is asserted for only 1 clock cycle.
1: Overflow Flag Interrupt
0: No interrupt
Table 17-47. Timer/Counter Interrupt Enable
IRQICRFEN Interrupt Enable for Capture Counter Flag.
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQOCRFEN Interrupt Enable for Compare Match Flag.
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQOVFEN Interrupt Enable for Overflow Flag.
1: Interrupt generation enabled
0: Interrupt generation disabled
TCIRQ 0x6E
Bit 7 6 5 4 3 2 1 0
Name (Reserved) IRQICRF IRQOCRF IRQOVF
Default 0 0 0 0 0000
Access — — — — — R/W R/W R/W
TCIRQEN 0x6F
Bit 7 6 5 4 3 2 1 0
Name (Reserved) IRQICRFEN IRQOCRFEN IRQOVFEN
Default 0 0 0 0 00 0 0
Access — — — — — R/W R/W R/W17-43
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Timer Counter Simulation Model
The Timer Counter EFB Register Map translation to the MachXO2 EFB software simulation model is provided
below.
Table 17-48. Timer/Counter Simulation Mode
Timer/Counter
Register Name
Register
Size/Bit
Location
Register
Function Address Access
Simulation Model Register
Name Simulation Model Register Path
TCCR0 [7:0] Control Register 0 0x5E Read/Write {tc_rstn_ena, tc_gsrn_dis,
tc_cclk_sel[2:0], tc_sclk_sel[2:0]} ../efb_top/efb_pll_sci_inst/u_efb_sci/
RSTEN 7 tc_rstn_ena ../efb_top/efb_pll_sci_inst/u_efb_sci/
PRESCALE[2:0] [5:3] tc_cclk_sel[2:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
CLKEDGE 2 tc_sclk_sel[2] ../efb_top/efb_pll_sci_inst/u_efb_sci/
CLKSEL 1 tc_sclk_sel[1] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCCR1 [7:0] Control Register 1 0x5F Read/Write
{1'b0, tc_ovf_ena, tc_ic_ena,
tc_top_sel, tc_oc_mode[1:0],
tc_mode[1:0]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
SOVFEN 6 tc_ivf_ena ../efb_top/efb_pll_sci_inst/u_efb_sci/
ICEN 5 tc_ic_ena ../efb_top/efb_pll_sci_inst/u_efb_sci/
TSEL 4 tc_top_sel ../efb_top/efb_pll_sci_inst/u_efb_sci/
OCM[1:0] [3:2] tc_oc_mode[1:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCM[1:0] [1:0] tc_mode[1:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCTOPSET0 [7:0] Set Top Counter Value [7:0] 0x60 Write
{tc_top_set[7], tc_top_set[6],
tc_top_set[5], tc_top_set[4],
tc_top_set[3], tc_top_set[2],
tc_top_set[1], tc_top_set[0]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
TCTOPSET[7:0] [7:0]
{tc_top_set[7], tc_top_set[6],
tc_top_set[5], tc_top_set[4],
tc_top_set[3], tc_top_set[2],
tc_top_set[1], tc_top_set[0]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
TCTOPSET1 [7:0] Set Top Counter Value [15:8] 0x61 Write
{tc_top_set[15], tc_top_set[14],
tc_top_set[13], tc_top_set[12],
tc_top_set[11], tc_top_set[10],
tc_top_set[9], tc_top_set[8]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
TCTOPSET[15:8] [7:0]
{tc_top_set[15], tc_top_set[14],
tc_top_set[13], tc_top_set[12],
tc_top_set[11], tc_top_set[10],
tc_top_set[9], tc_top_set[8]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
TCOCRSET0 [7:0] Set Compare Counter Value [7:0] 0x62 Write
{tc_ocr_set[7], tc_ocr_set[6],
tc_ocr_set[5], tc_ocr_set[4],
tc_ocr_set[3], tc_ocr_set[2],
tc_ocr_set[1], tc_ocr_set[0]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
TCOCRSET[7:0] [7:0]
{tc_ocr_set[7], tc_ocr_set[6],
tc_ocr_set[5], tc_ocr_set[4],
tc_ocr_set[3], tc_ocr_set[2],
tc_ocr_set[1], tc_ocr_set[0]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
TCOCRSET1 [7:0] Set Compare Counter Value [15:8] 0x63 Write
{tc_ocr_set[15], tc_ocr_set[14],
tc_ocr_set[13], tc_ocr_set[12],
tc_ocr_set[11], tc_ocr_set[10],
tc_ocr_set[9], tc_ocr_set[8]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
TCOCRSET[15:8] [7:0]
{tc_ocr_set[15], tc_ocr_set[14],
tc_ocr_set[13], tc_ocr_set[12],
tc_ocr_set[11], tc_ocr_set[10],
tc_ocr_set[9], tc_ocr_set[8]}
../efb_top/efb_pll_sci_inst/u_efb_sci/
TCCR2 [7:0] Control Register 2 0x64 Read/Write
{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
tc_oc_force, tc_cnt_reset,
tc_cnt_pause}
../efb_top/efb_pll_sci_inst/u_efb_sci/
WBFORCE 2 tc_oc_force ../efb_top/efb_pll_sci_inst/u_efb_sci/
WBRESET 1 tc_cnt_reset ../efb_top/efb_pll_sci_inst/u_efb_sci/
WBPAUSE 0 tc_cnt_pause ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCCNT0 [7:0] Counter Value [7:0] 0x65 Read tc_cnt_sts[7:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCCNT[7:0] [7:0] tc_cnt_sts[7:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCCNT1 [7:0] Counter Value [15:8] 0x66 Read tc_cnt_sts[15:8] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCCNT[15:8] [7:0] tc_cnt_sts[15:8] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCTOP0 [7:0] Current Top Counter Value [7:0] 0x67 Read tc_top_sts[7:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCTOP[7:0] [7:0] tc_top_sts[7:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/17-44
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Flash Memory (UFM/Configuration) Access
Designers can access the Flash Memory Configuration Logic interface using the JTAG, SPI, I2
C, or WISHBONE
interfaces. The MachXO2 Flash Memory consists of two sectors:
• User Flash Memory (UFM)
– MachXO2-640 and higher density devices provide one sector of User Flash Memory (UFM).
• Configuration
– Configuration consists of two sectors Configuration Flash and the Feature Row.
The UFM is a Flash sector which is organized in pages. The UFM is not byte addressable. Each page has 128 bits
(16 bytes).
TCTOP1 [7:0] Current Top Counter Value [15:8] 0x68 Read tc_top_sts[15:8] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCTOP[15:8] [7:0] tc_top_sts[15:8] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCOCR0 [7:0] Current Compare Counter Value
[7:0] 0x69 Read tc_ocr_sts[7:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCOCR[7:0] [7:0] tc_ocr_sts[7:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCOCR1 [7:0] Current Compare Top Counter
Value [15:8] 0x6A Read tc_ocr_sts[15:8] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCOCR[15:8] [7:0] tc_ocr_sts[15:8] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCICR0 [7:0] Current Capture Counter Value
[7:0] 0x6B Read tc_icr_sts[7:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCICR[7:0] [7:0] tc_icr_sts[7:0] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCICR1 [7:0] Current Capture Counter Value
[15:8] 0x6C Read tc_icr_sts[15:8] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCICR[15:8] [7:0] tc_icr_sts[15:8] ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCSR0 [7:0] Status Register 0x6D Read {1'b0, 1'b0, 1'b0, 1'b0, tc_btf_sts,
tc_icrf_sts, tc_ocrf_sts, tc_ovf_sts} ../efb_top/efb_pll_sci_inst/u_efb_sci/
BTF 3 tc_btf_sts ../efb_top/efb_pll_sci_inst/u_efb_sci/
ICRF 2 tc_icrf_sts ../efb_top/efb_pll_sci_inst/u_efb_sci/
OCRF 1 tc_ocrf_sts ../efb_top/efb_pll_sci_inst/u_efb_sci/
OVF 0 tc_ovf_sts ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCIRQ [7:0] Interrupt Request 0x6E Read/Write
{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
tc_icrf_irqsts, tc_ocrf_irqsts,
tc_ovf_irqsts}
../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQICRF 2 tc_icrf_irqsts ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQOCRF 1 tc_ocrf_irqsts ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQOVF 0 tc_ovf_irqsts ../efb_top/efb_pll_sci_inst/u_efb_sci/
TCIRQEN [7:0] Interrupt Request Enable 0x6F Read/Write
{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
tc_icrf_irqena, tc_ocrf_irqena,
tc_ovf_irqena}
../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQICRFEN 2 tc_icrf_irqena ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQOCRFEN 1 tc_ocrf_irqena ../efb_top/efb_pll_sci_inst/u_efb_sci/
IRQOVFEN 0 tc_ovf_irqena ../efb_top/efb_pll_sci_inst/u_efb_sci/
Table 17-48. Timer/Counter Simulation Mode (Continued)
Timer/Counter
Register Name
Register
Size/Bit
Location
Register
Function Address Access
Simulation Model Register
Name Simulation Model Register Path17-45
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Flash Memory (UFM/Configuration) Access Ports
Designers can access the UFM Sector via JTAG port (compliant with the IEEE 1149.1 and IEEE 1532 specifications), external Slave SPI port and external I2
C Primary port and the internal WISHBONE interface of the EFB
module. Figure 17-25 illustrates the interfaces to the UFM and Configuration Memory sectors.
Figure 17-25. Interfaces to the UFM/Configuration Sectors
The configuration logic arbitrates access from the interfaces by the following priority. When higher priority ports are
enabled Flash Memory access by lower priority ports will be blocked.
1. JTAG Port
2. Slave SPI Port
3. I2
C Primary Port
4. WISHBONE Slave Interface
Note: Enabling Flash Memory (UFM/Configuration) Interface using Enable Configuration Interface command 0x74
Transparent Mode will temporarily disable certain features of the device including:
• Power Controller
• GSR
• Hardened User SPI port
Functionality is restored after the Flash Memory (UFM/Configuration) Interface is disabled using Disable Configuration Interface command 0x26 followed by Bypass command 0xFF.
Configuration
(including
USERCODE)
UFM
Flash Command Interface
Flash Memory
EFB Register Map
WISHBONE Interface
User Logic EFB
Feature Row
(including
TraceID)
Primary I2
C Port
(Address yyyxxxxx00)
JTAG
Configuration
Slave
Configuration
Master/Slave
SPI Port
ufm_sn17-46
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Control Functions in MachXO2 Devices Reference Guide
Flash Memory (UFM/Configuration) Access through WISHBONE Slave Interface
The WISHBONE Slave interface of the EFB module enables designers to access the Flash Memory (UFM/Configuration) directly from the FPGA core logic. The WISHBONE bus signals, described earlier in this document, are utilized by a WISHBONE host that designers can implement using the general purpose FPGA resources. In addition
to the WISHBONE bus signals, an interrupt request output signal is brought to the FPGA fabric. The IP signal is
“wbc_ufm_irq”, and it functions as an interrupt request to the internal WISHBONE host, based on the data
Read/Write FIFO status or arbitration error.
Note: To access the Flash Memory (UFM/Configuration) via WISHBONE in R1 devices, the hard SPI port or the
primary I2
C port must be enabled. For more details, refer to AN8086, Designing for Migration from MachXO2-1200-
R1 to Standard (Non-R1) Devices.
The WISHBONE Interface communicates to the Configuration Logic through a set of data, control and status registers. Table 17-49 shows the register names and their functions. These registers are a subset of the EFB register
map. Refer to the EFB register map for specific addresses of each register.
Table 17-49. WISHBONE to Flash Memory (CFG) Logic Registers
Table 17-50. Flash Memory (UFM/Configuration) Control
WBCE WISHBONE Connection Enable. Enables the WISHBONE to establish the read/write
connection to the Flash Memory (UFM/Configuration) logic. This bit must be set prior
to executing any command through the WISHBONE port. Likewise, this bit must be
cleared to terminate the command. See “WISHBONE Framing” on page 50 for more
information on framing WISHBONE commands.
1: Enabled
0: Disabled
RSTE WISHBONE Connection Reset. Resets the input/output FIFO logic. The reset logic is
level sensitive. After setting this bit to '1' it must be cleared to '0' for normal operation.
1: Reset
0: Normal operation
WISHBONE to CFG
Register Name Register Function Address Access
CFGCR Control 0x70 Read/Write
CFGTXDR Transmit Data 0x71 Write
CFGSR Status 0x72 Read
CFGRXDR Receive Data 0x73 Read
CFGIRQ Interrupt Request 0x74 Read/Write
CFGIRQEN Interrupt Request Enable 0x75 Read/Write
Note: Unless otherwise specified, all Reserved bits in writable registers shall be written ‘0’.
CFGCR 0x70
Bit 7 6 5 4 3 2 1 0
Name WBCE RSTE (Reserved)
Default 0 0 0 0 0 0 0 0
Access R/W R/W — — — — — —17-47
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-51. Flash Memory (UFM/Configuration) Transmit Data
CFG_Transmit_Data[7:0] CFG Transmit Data. This register holds the byte that will be written to the Flash Memory (UFM/Configuration) logic. Bit 0 is LSB.
Figure 17-26. Flash Memory (UFM/Configuration) Status
WBCACT WISHBONE Bus to Configuration Logic Active. Indicates that the WISHBONE to configuration interface is active and the connection is established.
1: WISHBONE Active
0: WISHBONE not Active
TXFE Transmit FIFO Empty. Indicates that the Transmit Data register is empty. This bit is
capable of generating an interrupt.
1: FIFO empty
0: FIFO not empty
TXFF Transmit FIFO Full. Indicates that the Transmit Data register is full. This bit is capable
of generating an interrupt.
1: FIFO full
0: FIFO not full
RXFE Receive FIFO Empty. Indicates that the Receive Data register is empty. This bit is
capable of generating an interrupt.
1: FIFO empty
0: FIFO not empty
RXFF Receive FIFO Full. Indicates that the Transmit Data register is full. This bit is capable
of generating an interrupt.
1: FIFO full
0: FIFO not full
SSPIACT Slave SPI Active. Indicates the Slave SPI port has started actively communicating with
the Configuration Logic while WBCE was enabled. This port has priority over the I2
C
and WISHBONE ports and will pre-empt any existing, and prohibit any new, lower priority transaction. This bit is capable of generating an interrupt.
1: Slave SPI port active
0: Slave SPI port not active
I2CACT I2
C Active. Indicates the I2
C port has started actively communicating with the Configuration Logic while WBCE was enabled. This port has priority over the WISHBONE
ports and will pre-empt any existing, and prohibit any new WISHBONE transaction.
This bit is capable of generating an interrupt.
CFGTXDR 0x71
Bit 7 6 5 4 3 2 1 0
Name CFG_Transmit_Data[7:0]
Default 0 0 0 0 0 0 0 0
Access W W W W W W W W
CFGSR 0x72
Bit 7 6543210
Name WBCACT (Reserved) TXFE TXFF RXFE RXFF SSPIACT I2CACT
Default 0 0000000
Access R —RRRRRR17-48
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
1: I2
C port active
0: I2
C port not active
Table 17-52. Flash Memory (UFM/Configuration) Receive Data
CFG_Receive_Data[7:0] CFG Receive Data. This register holds the byte read from the Flash Memory
(UFM/Configuration) logic. Bit 0 in this register is LSB.
Table 17-53. Flash Memory (UFM/Configuration) Interrupt Status
IRQTXFE Interrupt Status for Transmit FIFO Empty.
When enabled, indicates TXFE was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Transmit FIFO Empty Interrupt
0: No interrupt
IRQTXFF Interrupt Status for Transmit FIFO Full.
When enabled, indicates TXFF was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Transmit FIFO Full Interrupt
0: No interrupt
IRQRXFE Interrupt Status for Receive FIFO Empty.
When enabled, indicates RXFE was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Receive FIFO Empty Interrupt
0: No interrupt
IRQRXFF Interrupt Status for Receive FIFO Full.
When enabled, indicates RXFF was asserted. Write a ‘1’ to this bit to clear the interrupt.
1: Receive FIFO Full Interrupt
0: No interrupt
IRQSSPIACT Interrupt Status for Slave SPI Active.
When enabled, indicates SSPIACT was asserted. Write a ‘1’ to this bit to clear the
interrupt.
1: Slave SPI Active Interrupt
0: No interrupt
IRQI2CACT Interrupt Status for I2
C Active.
When enabled, indicates I2CACT was asserted. Write a ‘1’ to this bit to clear the interrupt.
CFGRXDR 0x73
Bit 7 6 5 4 3 2 1 0
Name CFG_Receive_Data[7:0]
Default 0 0 0 0 0 0 0 0
Access R R R R R R R R
CFGIRQ 0x74
Bit 7 6 5 4 3 2 1 0
Name (Reserved) IRQTXFE IRQTXFF IRQRXFE IRQRXFF IRQSSPIACT IRQI2CACT
Default 0 00000 0 0
Access — — R/W R/W R/W R/W R/W R/W17-49
Using User Flash Memory and Hardened
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1: I2
C Active Interrupt
0: No interrupt
Table 17-54. Flash Memory (UFM/Configuration) Interrupt Enable
IRQTXFEEN Interrupt Enable for Transmit FIFO Empty
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQTXFFEN Interrupt Enable for Transmit FIFO Full
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQRXFEEN Interrupt Enable for Receive FIFO Empty
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQRXFFEN Interrupt Enable for Receive FIFO Full
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQSSPIACTEN Interrupt Enable for Slave SPI Active
1: Interrupt generation enabled
0: Interrupt generation disabled
IRQI2CACTEN Interrupt Enable for I2
C Active
1: Interrupt generation enabled
0: Interrupt generation disabled
Table 17-55. Unused (Reserved) Register
Table 17-56. EFB Interrupt Source
UFMCFG_INT Flash Memory (UFM/Configuration) Interrupt Source. Indicates EFB interrupt source
is from the UFM/Configuration Block. Use CFGIRQ for further source resolution.
1: A bit is set in register CFGIRQ
CFGIRQEN 0x75
Bit 7 6 5 4 3 2 1 0
Name (Reserved) IRQTXFEEN IRQTXFFEN IRQRXFEEN IRQRXFFEN IRQSSPIACTEN IRQI2CACTEN
Default 0 00 0 0 0 0 0
Access — — R/W R/W R/W R/W R/W R/W
UNUSED 0x76
Bit 7 6 5 4 3 2 1 0
Name (Reserved)
Default 0 0 0 0 0 0 0 0
Access — — — — — — — —
EFBIRQ 0x77
Bit 7 6 5 4 3 2 1 0
Name (Reserved) UFMCFG_INT TC_INT SPI_INT I2C2_INT I2C1_INT
Default 0 0 0 0 0000
Access R R R R RRRR17-50
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
0: No interrupt
TC_INT Timer/Counter Interrupt Source. Indicates EFB interrupt source is from the
Timer/Counter Block. Use TCIRQ for further source resolution.
1: A bit is set in register TCIRQ
0: No interrupt
SPI_INT SPI Interrupt Source. Indicates EFB interrupt source is from the SPI Block. Use SPIIRQ for further source resolution.
1: A bit is set in register SPIIRQ
0: No interrupt
I2C2_INT I2C2 Interrupt Source. Indicates EFB interrupt source is from the Secondary I2
C
Block. Use I2C_2_ IRQ for further source resolution.
1: A bit is set in register I2C_2_ IRQ
0: No interrupt
I2C1_INT I2C1 Interrupt Source. Indicates EFB interrupt source is from the Primary I2
C Block.
Use I2C_1_ IRQ for further source resolution.
1: A bit is set in register I2C_1_ IRQ
0: No interrupt
WISHBONE Framing
To access the Flash Memory (UFM/Configuration) each command string sent to the WISHBONE EFB ports must
be correctly ‘framed’ using the protocol defined for each interface. In the case of the internal WISHBONE port,
each command string is preceded by setting CFGCR[WBCE]. Similarly, each command string is followed by clearing the CFGCR[WBCE] bit.
Table 17-57. Command Framing Protocol, by Interface
Figure 17-27. WISHBONE Read Device ID Example (-1200 HC Device)
Command and Data Transfers to Flash Memory (UFM/Configuration) Space
The command and data transfers to the Flash Memory (UFM/Configuration) are identical for all the access ports,
regardless of their different physical interfaces. The Flash Memory (UFM/Configuration) is organized in pages.
Therefore, users address a specific page for Read or Write operations to that page. Each page has 128 bits (16
bytes). The transfers are based on a set of instructions and page addresses. The Flash memory is composed of
two sectors, Configuration Memory (sector 0) and UFM (sector 1). The Erase operations are sector based.
Interface Pre-op (+) Command String Post-op (-)
WISHBONE Assert CFGCR[WBCE] (Command/Operands/Data) De-assert CFGCR[WBCE]
70 71 71 71 71 73 73 73 73 70
80 E0 00 00 00 00
wb_adr_i
wb_dat_i
wb_dat_o 01 2B A0 43
wb_we_i
wb_str_i
wb_ack_o
wb_clk_i17-51
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Command Summary by Application
Table 17-58. UFM (Sector 1) Commands
Command Name
Command
MSB LSB SVF Command Name Description
Read Status Register 0x3C LSC_READ_STATUS Read the 4-byte Configuration Status Register
Check Busy Flag 0xF0 LSC_CHECK_BUSY Read the Configuration Busy Flag status
Bypass 0xFF ISC_NOOP Null operation.
Enable Configuration Interface
(Transparent Mode) 0x74 ISC_ENABLE_X
Enable Transparent UFM access – All user I/Os
(except the hardened user SPI and primary user
I
2
C ports) are governed by the user logic, the
device remains in User mode. (The subsequent
commands in this table require the interface to
be enabled.)
Enable Configuration Interface
(Offline Mode) 0xC6 ISC_ENABLE
Enable Offline UFM access – All user I/Os
(except persisted sysCONFIG ports) are tristated. User logic ceases to function, UFM
remains accessible, and the device enters
'Offline' access mode. (The subsequent commands in this table require the interface to be
enabled.)
Disable Configuration Interface 0x26 ISC_DISABLE Disable the configuration (UFM) access.
Set Address 0xB4 LSC_WRITE_ADDRESS Set the UFM sector 14-bit Address Register
Reset UFM Address 0x47 LSC_INIT_ADDR_UFM Reset the address to point to Sector 1, Page 0
of the UFM.
Read UFM 0xCA LSC_READ_TAG
Read the UFM data. Operand specifies number
pages to read. Address Register is post-incremented.
Erase UFM 0xCB LSC_ERASE_TAG Erase the UFM sector only.
Program UFM Page 0xC9 LSC_PROG_TAG Write one page of data to the UFM. Address
Register is post-incremented.
Table 17-59. Configuration Flash (Sector 0) Commands
Command Name
Command
MSB LSB SVF Command Name Description
Read Device ID 0xE0 IDCODE_PUB Read the 4-byte Device ID (0x01 2b 20 43)
Read USERCODE 0xC0 USERCODE Read 32-bit USERCODE
Read Status Register 0x3C LSC_READ_STATUS Read the 4-byte Configuration Status Register
Read Busy Flag 0xF0 LSC_CHECK_BUSY Read the Configuration Busy Flag status
Refresh1
0x79 LSC_REFRESH Launch boot sequence (same as toggling PROGRAMN pin).
STANDBY 0x7D LSC_DEVICE_CTRL Triggers the Power Controller to enter or wake
from standby mode
Bypass 0xFF ISC_NOOP Null operation.
Enable Configuration Interface
(Transparent Mode) 0x74 ISC_ENABLE_X
Enable Transparent Configuration Flash access
– All user I/Os (except the hardened user SPI
and primary user I2
C ports) are governed by the
user logic, the device remains in User mode.
(The subsequent commands in this table require
the interface to be enabled.)17-52
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-60. Non-Volatile Register (NVR) Commands
When using the WISHBONE bus interface, the commands, operand and data are written to the CFGTXDR Register. The Slave SPI or I2
C interface shift the most significant bit (MSB) first into the MachXO2 device. This is required
only when communicating with the configuration logic inside the MachXO2 device.
In order to perform a Write, Read or Erase operation with the UFM or Configuration Flash, it is required that the
interface is enabled using Command 0x74. Affected commands are noted in the Command Description as “EN
Required.” Once the modification operations are completed, the interface can be disabled using commands 0x26
and 0xFF.
Enable Configuration Interface
(Offline Mode) 0xC6 ISC_ENABLE
Enable Offline Configuration Flash access – All
user I/Os (except persisted sysCONFIG ports)
are tri-stated. User logic ceases to function,
UFM remains accessible, and the device enters
‘Offline’ access mode. (The subsequent commands in this table require the interface to be
enabled.)
Disable Configuration Interface 0x26 ISC_DISABLE Exit access mode.
Set Configuration Flash
Address 0xB4 LSC_WRITE_ADDRESS Set the Configuration Flash 14-bit Page Address
Verify Device ID 0xE2 VERIFY_ID Verify device ID with 32-bit input, set Fail flag if
mismatched.
Reset Configuration Flash
Address 0x46 LSC_INIT_ADDRESS Reset the address to point to Sector 0, Page 0
of the Configuration Flash.
Read Flash 0x73 LSC_READ_INCR_NV
Read the Flash data. Operand specifies number
pages to read. Address Register is post-incremented.
Erase 0x0E ISC_ERASE Erase the Config Flash, Done bit, Security bits
and USERCODE
Program Page 0x70 LSC_PROG_INCR_NV
Write 1 page of data to the Flash Memory (Configuration/UFM). Address Register is post-incremented.
Program DONE 0x5E ISC_PROGRAM_DONE Program the Done bit
Program SECURITY 0xCE ISC_PROGRAM_SECURITY Program the Security bit (Secures CFG Flash
sector)
Program SECURITY PLUS 0xCF ISC_PROGRAM_SECPLUS
Program the Security Plus bit (Secures CFG
and UFM Sectors). Note: SECURITY and
SECURITY PLUS commands are mutually
exclusive.
Program USERCODE 0xC2 ISC_PROGRAM_USERCODE Program 32-bit USERCODE
Read Feature Row 0xE7 LSC_READ_FEATURE Read Feature Row
Program Feature Row 0xE4 LSC_PROG_FEATURE Program Feature Row
Read FEABITS 0xFB LSC_READ_FEABITS Read FEA bits
Program FEABITs 0xF8 LSC_PROG_FEABITS Program the FEA bits
1. The Refresh commands are not supported by the software simulation model.
Command Name
Command
msb lsb SVF Command Name Description
Read Trace ID code 0x19 UIDCODE_PUB Read 64-bit TraceID.
Table 17-59. Configuration Flash (Sector 0) Commands (Continued)
Command Name
Command
MSB LSB SVF Command Name Description17-53
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Command Descriptions by Command Code
Table 17-61. Erase Flash (0x0E)
Operand: 0000 ucfs 0000 0000 0000 0000(binary)
where: u: Erase UFM sector
0: No action
1: Erase
c: Erase CFG sector (Config Flash, DONE, security bits, USERCODE)
0: No action
1: Erase
f: Erase Feature sector (Slave I2
C address, sysCONFIG port persistence, Boot
mode, OTP, etc.)
0: No action
1: Erase
s: Erase SRAM
0: No action
1: Erase
Notes: Poll the BUSY bit (or wait, see Table 17-93) after issuing this command for erasure to
complete before issuing a subsequent command other than Read Status or Check
Busy.
Erased condition for Flash bits = 0
Examples: 0x0E 04 00 00
Erase CFG sector
0x0E 08 00 00
Erase UFM sector
0x0E 0C 00 00
Erase UFM and CFG sectors
Table 17-62. Read TraceID Code (0x19)
Example: 0x19 00 00 00
Read 8-byte TraceID
Note: First byte read is user portion. Next seven bytes are unique to each silicon die.
Table 17-63. Disable Configuration Interface (0x26)
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data
Format
x x Y 0E See below — — —
UFM CFG NVR
EN
Required CMD (Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x N 19 00 00 00 R 8B —
UFM CFG NVR
EN
Required CMD (Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x x — 26 00 00 — — —17-54
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Example: 0x26 00 00
Disable Flash Memory (UFM/configuration) interface for change access
Notes: Must have only two operands
The interface cannot be disabled while the Configuration Status Register Busy bit is
asserted. After commands (e.g. Erase, Program) verify Busy is clear before issuing
the Disable command.
This command should be followed by Command 0xFF (BYPASS) to complete the Disable operation. The BYPASS command is required to restore Power Controller, GSR,
Hardened User SPI and I2
C port operation.
SRAM must be erased before exiting Offline (0xC6) Mode
Table 17-64. Read Status Register (0x3C)
Data Format: Most significant byte of SR is received first, LSB last.
D bit 8 Flash or SRAM Done Flag
When C = 0 SRAM Done bit has been programmed
• D = 1 Successful Flash to SRAM transfer
• D = 0 Failure in the Flash to SRAM transfer
When C=1 Flash Done bit has been programed
• D = 1 Programmed
• D = 0 Not Programmed
C bit 9 Enable Configuration Interface (1=Enable, 0=Disable)
B bit 12: Busy Flag (1 = busy)
F bit 13: Fail Flag (1 = operation failed)
I I=0 Device verified correct, I=1 Device failed to verify
EEE bits[25:23]: Configuration Check Status
000: No Error
001: ID ERR
010: CMD ERR
011: CRC ERR
100: Preamble ERR
101: Abort ERR
110: Overflow ERR
111: SDM EOF
(all other bits reserved)
Usage: The BUSY bit should be checked following all Enable, Erase or Program operations.
Note: Wait at least 1us after power-up or asserting wb_rst_i before accessing the EFB.
Example: 0x3C 00 00 00
Read 4-byte Status Register e.g. 0x00 00 20 00 (fail flag set)
Table 17-65. Reset CFG Address (0x46)
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex)
Data
Mode
Data
Size Data Format (Binary)
x x N 3C 00 00 00 R 4B xxxx IxEE Exxx xxxx xxFB xxCD xxxx xxxx
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data
Format
x Y 46 00 00 00 — — —17-55
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Example: 0x46 00 00 00
Set Address register to Configuration Sector 0, page 0
Table 17-66. Reset UFM Address (0x47)
Example: 0x47 00 00 00
Set Address register to UFM Sector 1, page 0
Table 17-67. Program DONE (0x5E)
Example: 0x5E 00 00 00
Set the DONE bit
Note: Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.
Table 17-68. Program Configuration Flash (0x70)
Example: 0x70 00 00 01 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
Write one page of data, pointed to by Address Register
Notes: 16 data bytes must be written following the command and operand bytes to ensure
proper data alignment. The Address Register is auto-incremented following the page
write.
Operands (0x00 00 00) are equivalent to (0x00 00 01).
Use 0x0E to erase CFG sector prior to executing this command.
Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.
Table 17-69. Read Configuration Flash (0x73) (WISHBONE/SPI)
Note: This applies when Configuration Flash is read through WISHBONE or SPI
*Operand: 0001 0000 00pp pppp pppp pppp (binary)
pp..pp: num_pages Number of CFG pages to read when num_pages = 1
Number of CFG pages to read +1 when num_pages > 1
**Data Size: (num_pages * 16) bytes
UFM CFG NVR
EN
Required CMD (Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x Y 47 00 00 00 — — —
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data
Format
x Y 5E 00 00 00 — — —
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex)
Data
Mode Data Size Data Format
x Y 70 00 00 01 W 16B 16 bytes UFM write data
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x Y 73 * (below) R ** (below) *** (below)17-56
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Note: Read CFG may be aborted at any time. Any data remaining in the read FIFO will be
discarded. Any read data beyond the prescribed read size will be indeterminate. The
Address Register is auto-incremented after each page read.
***Examples: 0x73 10 00 01
0 bytes dummy followed by one page of CFG data (16 bytes total)
0x73 10 00 04
Read 1 page dummy followed by three pages of CFG data (4 pages total)
Note: The maximum speed which one page of data (num_page=1) can be read through the
WISHBONE is 36 MHz. There is no restriction on SPI speeds besides the port limitations.
Table 17-70. Read Configuration Flash (0x73) (I2
C/WISHBONE/SPI)
Note: This applies when Configuration Flash is read through I2
C, WISHBONE or SPI
*Operand: 0000 0000 00pp pppp pppp pppp (binary)
pp..pp: num_pages Number of CFG pages to read when num_pages = 1
Number of CFG pages to read +1 when num_pages > 1
**Data Size: (num_pages * 16) bytes when num_pages=1
32 bytes + (num_pages * 16 + 4) bytes when num_pages>1
Note: Read CFG may be aborted at any time. Any data remaining in the read FIFO will be
dis-carded. Any read data beyond the prescribed read size will be indeterminate. The
Address Register is auto-incremented after each page read.
***Examples: 0x73 00 00 01
0 bytes dummy followed by 1 page CFG data (16 bytes total)
0x73 00 00 04
Read 2 pages dummy, followed by three (1 page CFG data, followed by 4 bytes
dummy) (5 pages and 12 bytes total)
Note: The maximum speed which one page of data (num_page=1) can be read through the
WISHBONE is 36 MHz. There is no restriction on I2
C and SPI speeds besides the port
limitations.
Table 17-71. Enable Configuration Interface (Transparent) (0x74)
Notes: This command is required to enable modification of the UFM, configuration Flash, or
non-volatile registers (NVR). Terminate this command with command 0x26 followed by
command 0xFF.
Exercising this command will temporarily disable certain features of the device, notably GSR, user SPI port, primary user I2
C port and Power Controller. These features
are restored when the command is terminated.
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x Y 73 * (below) R ** (below) *** (below)
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x x — 74 08 00 00 — — —17-57
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Poll the BUSY bit (or wait 5us) after issuing this command for the Flash pumps to fully
charge.
Example: 0x74 08 00 00
Enable UFM/configuration interface for change access
Table 17-72. Refresh (0x79)
Example: 0x79 00 00
Issue Refresh command
Note: The Refresh command will Launch Boot sequence
Must have only two operands
After completing the Refresh command (e.g. SPI SN deassertion or I2
C stop), further
bus accesses are prohibited for the duration of tREFRESH. Violating this requirement
will cause the Refresh process to abort and leave the MachXO2 device in an unprogrammed state.
Occasionally, following a device REFRESH or PROGRAMN pin toggle, the secondary
I
2
C port may be left in an undefined (non-idle) state. The likely hood of this condition is
design and route dependent. To positively return the Secondary I2
C port to the idle
state, write a value of 0x40 to register I2C_2_CMDR via WISHBONE immediately
after device reset is released. This will cause a short low-pulse on SCK as the hardblock signals a STOP on the bus then returns to the idle state. Failure to manually
return the Secondary I2
C port to the idle state may result in an I2
C bus lock-up condition. Normal I2
C activity can be commenced without additional delay
Table 17-73. STANDBY (0x7D)
Example: 0x7D 0y 00
y:2 Triggers the Power Controller to enter standby mode
y:8 Triggers the Power Controller to wakeup from standby mode
Notes: Must have only two operands.
The MachXO2 Power Controller needs to be included in the design.
Additionally the following can be used to trigger the Power Controller to wakeup from
standby mode (if the user logic standby signal has not been enabled):
1. I2
C has the following ways:
a. Primary I2
C Configuration port – Address match to the I2
C Configuration
address (No other settings required)
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
(Binary)
79 00 00 — — —
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
(Binary)
x N 7D 0y 00 — — —17-58
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
b. Primary or Secondary I2
C User port – Address match the I2
C User
address. Must have I2C_1_CR[WKUPEN] or I2C_1_CR[WKUPEN] set
c. General Call – Send the General Call Wakeup command (0xF3). Must
have General Calls enabled (I2C_1_CR[GCEN] or I2C_2_CR[GCEN] set)
and use the General Call address
2. SPI from the assertion of either Slave Configuration (ufm_sn) or User
(spi_scsn) chip select, as long as the appropriate control register bit is set:
a. Configuration: SPICR1[WKUPEN_CFG]
b. User: SPICR[WKUPEN_USER]
For more information on the Power Controller refer to TN1198, Power Estimation and
Management for MachXO2 Devices.
Table 17-74. Set Address (0xB4)
Data Format: s: sector
0: Configuration
1: UFM
aa..aa:address14-bit page address
Example: 0xB4 00 00 00 40 00 00 0A
Set Address register to UFM sector, page 10 decimal
Table 17-75. Read USERCODE (0xC0)
Example: 0xC0 00 00 00
EN Required = Y Read 4-byte USERCODE from CFG sector
EN Required = N Read 4-byte USERCODE from SRAM
Table 17-76. Program USERCODE (0xC2)
Example: 0xC2 00 00 00 10 20 30 40
Sets USERCODE with 32-bit input 0x10 20 30 40
Note: Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.
Table 17-77. Enable Configuration Interface (Offline) (0xC6))
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex)
Data
Mode
Data
Size Data Format (Binary)
x x Y B4 00 00 00 W 4B 0s00 0000 0000 0000 00aa aaaa aaaa aaaa
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format (Hex)
x Y/N C0 00 00 00 R 4B —
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format (Hex)
x Y C2 00 00 00 W 4B —
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data
Format
x C6 08 00 00 — — —17-59
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Example: 0xC6 08 00 00 Enable Flash Memory (UFM/configuration) interface for offline change
access.
Notes: Use this command to enable offline modification of the UFM, Configuration Flash, or
non-volatile registers (NVR). SRAM must be erased exiting Offline mode. When exiting Offline mode follow the command 0x26 with the command 0xFF. Exercising this
command will tri-state all user I/Os (except persisted sysCONFIG ports). User logic
ceases to function. UFM remains accessible.
Poll the BUSY bit (or wait 5us) after issuing this command for the Flash pumps to fully
charge.
Table 17-78. Program UFM (0xC9)
Example: 0xC9 00 00 01 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
Write one page of data, pointed to by Address Register
Notes: 16 data bytes must be written following the command and operand bytes to ensure
proper data alignment. The Address Register is auto-incremented following the page
write.
Use 0x0E or 0xCB to erase UFM sector prior to executing this command.
Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.
Table 17-79. Read UFM (0xCA) (WISHBONE/SPI)
*Operand: 0001 0000 00pp pppp pppp pppp (binary)
where: pp..pp: num_pages – Number of UFM pages to read
**Data Size (num_pages * 16) bytes
Note: Read UFM may be aborted at any time. Any data remaining in the read fifo will be discarded. Any read data beyond the prescribed read size will be indeterminate. The
Address Register is auto-incremented after each page read.
***Examples: 0xCA 10 00 01
Read 0 bytes dummy followed by 1 page UFM data (16 bytes total)
0xCA 10 00 04
Read 1 page dummy followed by 3 pages UFM data (4 pages total)
Note: The maximum speed which one page of data (num_page=1) can be read using
WISHBONE and no wait states is 16.6MHz. Faster WISHBONE clock speeds are supported by inserting WB wait states to observe the retrieval delay timing requirement.
For more information, refer to the Reading Flash Pages section of TN1204, MachXO2
UFM CFG NVR
EN
Required CMD (Hex)
Operands
(Hex) Data Mode Data Size
Data
Format
x Y C9 00 00 01 W 16B 16 bytes UFM write
data
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x Y CA *(below) R **(below) ***(below)17-60
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Programming and Configuration Usage Guide. SPI transactions in MachXO2 always
meet the minimum retrieval delay requirement. No special timing is necessary for SPI.
Table 17-80. Read UFM (0xCA) (WISHBONE/SPI/I2
C)
*Operand: 0000 0000 00pp pppp pppp pppp (binary)
where: pp..pp: num_pages Number of UFM pages to read when num_pages=1
Number of UFM pages +1 to read when num_pages>1
**Data Size (num_pages * 16) byteswhen num_pages=1
32 bytes + (num_pages * 16 + 4) bytes when num_pages>1
Note: Read UFM may be aborted at any time. Any data remaining in the read fifo will be discarded. Any read data beyond the prescribed read size will be indeterminate. The Address Register is auto-incremented after each page read.
***Examples: 0xCA 00 00 01
Read 0 bytes dummy followed by 1 page UFM data (16 bytes total)
0xCA 00 00 04
Read 2 pages dummy followed by 3 (1 page UFM data, followed by 4 bytes dummy) (5
pages total and 12 bytes)
Note: The maximum speed which one page of data (num_page=1) can be read using
WISHBONE and no wait states is 16.6MHz. Faster WISHBONE clock speeds are supported by inserting WB wait states to observe the retrieval delay timing requirement.
For more information, refer to the Reading Flash Pages section of TN1204, MachXO2
Programming and Configuration Usage Guide. SPI and I2
C transactions in MachXO2
always meet the minimum retrieval delay requirement. No special timing is necessary
for SPI or I2
C.
Table 17-81. Erase UFM (0xCB)
Notes: Erased condition for UFM bits = ‘0’
Poll the BUSY bit (or wait, see Table 17-93) after issuing this command for erasure to
complete before issuing a subsequent command other than Read Status or Check
Busy.
Example: 0xCB 00 00 00
Erase UFM sector
Table 17-82. Program SECURITY (0xCE)
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x Y CA *(below) R **(below) ***(below)
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data
Format
x Y CB 00 00 00 — — —
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x Y CE 00 00 00 — — —17-61
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Example: 0xCE 00 00 00
Set the SECURITY bit
Note: Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.
SECURITY and SECURITY PLUS commands are mutually exclusive.
Table17-83. Program SECURITY PLUS (0xCF)
Example: 0xCF 00 00 00
Set the SECURITY PLUS bit
Note: Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.
SECURITY and SECURITY PLUS commands are mutually exclusive.
Table 17-84. Read Device ID Code (0xE0)
Example: 0xE0 00 00 00
Read 4-byte device ID
Table 17-85. Device ID Table
Example: 0xE0 00 00 00
Read 4-byte device ID
Table 17-86. Verify Device ID Code (0xE2)
Example: 0xE2 00 00 00 01 2B 20 43
Verify device ID with 32-bit input, sets ID Error bit 27 in SR if mismatched
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
x Y CF 00 00 00 — — —
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
(Hex)
x N E0 00 00 00 R 4B See Table 17-85
Device Name HE/ZE Devices HC Devices
MachXO2-256 0x01 2B 00 43 0x01 2B 80 43
MachXO2-640 0x01 2B 10 43 0x01 2B 90 43
MachXO2-1200/MachXO2-640U 0x01 2B 20 43 0x01 2B A0 43
MachXO2-2000/MachXO2-1200U 0x01 2B 30 43 0x01 2B B0 43
MachXO2-4000/MachXO2-2000U 0x01 2B 40 43 0x01 2B C0 43
MachXO2-7000 0x01 2B 50 43 0x01 2B D0 43
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
(Hex)
x Y E2 00 00 00 W 4B See Table 17-
8517-62
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-87. Program Feature Row (0xE4)
Data Format: ss: 8 bits for the user programmable I2
C Slave Address
uu: 8 bits for the user programmable TraceID
cc cc cc cc: 32 bits of Custom ID code
Note: It is not recommended to reprogram the Feature Row once it has been program the
first time.
Example: 0xE4 00 00 00 00 00 01 00 00 00 12 34
Program Feature Row with User I2
C address set to 1, default user TraceID string, Custom ID code of 12 34
Table 17-88. Read Feature Row (0xE7)
Data Format: ss: 8 bits for the user programmable I2
C Slave Address
uu: 8 bits for the user programmable TraceID
cc cc cc cc: 32 bits of Custom ID code
Example: 0xE7 00 00 00
Reads the Feature Row
Table 17-89. Check Busy Flag (0xF0)
Data Format: B: bit 7: Busy Flag (1= busy)
(all other bits reserved)
Example: 0xF0 00 00 00
Read one byte, e.g. 0x80 (busy flag set)
Table 17-90. Program FEABITs (0xF8)
Data Format: bb: Boot Sequence
1. If b=00 (Default) and m=0 then Single Boot from Configuration Flash
2. If b=00 and m=1 then Dual Boot from Configuration Flash then External if
there is a failure
3. If b=01 and m=1 then Single Boot from External Flash
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
(Hex)
Y E4 00 00 00 8B 00 00 ss uu cc
cc cc cc
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
(Hex)
x Y E7 00 00 00 R 8B 00 00 ss uu cc
cc cc cc
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
(Binary)
x x N F0 00 00 00 R 1B Bxxx xxxx
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size Data Format (Binary)
x Y F8 00 00 00 W 2B 00 bb mi sj di pa 00 0017-63
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
m: Master SPI Port Persistence
0=Disabled (Default), 1=Enabled
i: I2
C Port Persistence
0=Enabled (Default), 1=Disabled
s: Slave SPI Port Persistence
0=Enabled (Default), 1=Disabled
j: JTAG Port Persistence
0=Enabled (Default), 1=Disabled
d: DONE Persistence
0=Disabled (Default), 1=Enabled
i: INITN Persistence
0=Disabled (Default), 1=Enabled
p: PROGRAMN Persistence
0=Enabled (Default), 1=Disabled
a: my_ASSP Enabled
0=Disabled (Default), 1=Enabled
Note: It is not recommended to reprogram the FEABITs once they have been programmed
the first time.
Example: 0xF8 00 00 00 0D 20
Programs the FEABITs
Table 17-91. Read FEABITs (0xFB)
Data Format: bb: Boot Sequence
1. If b=00 (Default) and m=0 then Single Boot from Configuration Flash
2. If b=00 and m=1 then Dual Boot from Configuration Flash then External if
there is a failure
3. If b=01 and m=1 then Single Boot from External Flash
m: Master SPI Port Persistence
0=Disabled (Default), 1=Enabled
i: I2
C Port Persistence
0=Enabled (Default), 1=Disabled
s: Slave SPI Port Persistence
0=Enabled (Default), 1=Disabled
j: JTAG Port Persistence
0=Enabled (Default), 1=Disabled
d: DONE Persistence
0=Disabled (Default), 1=Enabled
i: INITN Persistence
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size Data Format (Binary)
x Y FB 00 00 00 R 2B 00 bb mi sj di pa 00 0017-64
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
0=Disabled (Default), 1=Enabled
p: PROGRAMN Persistence
0=Enabled (Default), 1=Disabled
a: my_ASSP Enabled
0=Disabled (Default), 1=Enabled
Table 17-92. Bypass (Null Operation) (0xFF)
Note: Operands are optional
Example: 0xFF FF FF FF Bypass
Interface to Configuration Flash
The WISHBONE interface of the EFB module allows a WISHBONE host to access the configuration resources of
the MachXO2 devices. This can be particularly useful for reading data from configuration resources such as
USERCODE and TraceID. Most importantly, this feature allows users to update the Configuration Flash array of the
devices while the device is in operation mode. This is a self-configuration operation. Upon power-up or a configuration refresh operation, the new content of the Configuration Flash is loaded into the Configuration SRAM and the
device continues operation with a new configuration.
The data transfer and execution of operations is the same as the one documented in the UFM section of this document. This is due to the fact that the UFM is also a Flash Memory resource and the communication between the
WISHBONE host and the configuration logic is performed through the same command, status and data registers.
Please see Tables 17-49 to 17-57 for information on these registers.
Figure 17-28 shows a basic flow diagram for implementing a Configuration Flash Update initiated via any of the
sysCONFIG ports (I2
C, SPI, or WISHBONE).
For detailed information on MachXO2 programming and configuration, see TN1204, MachXO2 Programming and
Configuration Usage Guide.
UFM CFG NVR
EN
Required
CMD
(Hex)
Operands
(Hex) Data Mode Data Size
Data Format
(Binary)
x x x N FF FF FF FF — — —17-65
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Figure 17-28. Basic Configuration Flash Update Example
Start
Enable Transparent
Configuration (0x74)
Ensure unused Configuration
Ports are Inactive
Write more data?
Set Flash DONE bit (0x5E)
Y
N
Write 1 Page Config Data
(0x70)
Wait for !BUSY (0xF0)
then verify !FAIL (0x3C)
(optional)
Set USERCODE (0xC2)
Set SECURITY (0xCE, 0xCF)
N
Y
Erase Configuration Flash
Sector (0x0E)
Wait for !BUSY (0xF0)
then verify !FAIL (0x3C)
Set Address to 0 (0x46)
Wait for !BUSY (0xF0)
then verify !FAIL (0x3C)
Issue REFRESH (0x79)
Wait for tREFRESH
then verify DONE (0x3C)
Configure via
WISHBONE?
Done
N
Disable Configuration (0x26)
Wait for !BUSY (0xF0)
then verify !FAIL (0x3C)17-66
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Flash Memory Erase and Program Performance
Table 17-93. Flash Memory (UFM/Configuration) Performance in MachXO2 Devices1
Erase/Program/Verify Time Calculation Example
Using the data above, it is possible to roughly calculate the time required to perform an Erase/Program/Verify operation. The calculation assumes nearly 100% bus utilization. Overhead required by bus master processes, if any, is
not accounted for in the equation below.
E/P/V time (us): tEPV = tE + tP + tV
where: tE = tECFG + tEUFM1
tP = 0.2us * number of Pages to program2
tV = (8 * number of Pages programmed) * BusEff * tBUSCLK
UFM Write and Read Examples
The UFM and Configuration sectors support page-oriented read and write operations while erase operations are
sector-based. Consistent with many Flash memory devices, byte-oriented operations are not supported. Also, as
typical with Flash memory devices, attempting to modify a previously written location in Flash requires a read-modify-write operation on the smallest erasable Flash unit. In the case of MachXO2, the smallest erasable unit is the
entire UFM sector or the entire Configuration Sector.
For example, to arbitrarily modify a byte value in the UFM, the user must:
1. Read and save all UFM data to an alternate location (e.g. EBR);
2. Erase the UFM sector;
3. Modify the selected byte; and
4. Program the UFM page by page.
MachXO2
-256
MachXO2
-640
MachXO2
-640U
MachXO2
-1200
MachXO2
-1200U
MachXO2
-2000
MachXO2
-2000U
MachXO2
-4000
MachXO2
-7000
CFG Erase
Min. 400 600 800 800 1100 1100 1800 1800 2800
Max. 700 1100 1400 1400 1900 1900 3100 3100 4800
CFG Program
All 130 270 500 500 740 740 1400 1400 2200
1 page 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2
UFM Erase
Min. — 300 400 400 500 500 600 600 900
Max. — 600 700 700 900 900 1000 1000 1600
UFM Program
All — 40 110 110 140 140 180 180 480
1 page — 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2
1. All times are averages, in (ms). SRAM erase times are < 0.1ms.
Table 17-94. E/P/V Calculation parameters
BusEff
(Single Page Read)
BusEff3
(Multi Page Read) tBUSCLK
I
2
C 14 >12 2.5us min
SPI 12 > 8 0.015us min
WB 5.25 > 3 0.020us min
1. Sector erase times are additive. If a sector (e.g. CFG) is not erased, its erase time is 0.
2. Data transfer time is insignificant to tP for high-speed data protocols. To account for slow bus speeds (E.g. I2
C) multiply tV by 2.
3. Bus efficiency approaches this value as number of read pages increases. 17-67
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
In some applications it may be appropriate to keep a working copy of the UFM contents in volatile Embedded Block
RAM and update the non-volatile UFM at appropriate intervals. The following examples show the sequence of commands for writing and reading from UFM.
Table 17-95. Write Two UFM Pages
Instruction
Number R/W1 CMD2 Operand Data Comment
+ Open frame
1 W 74 08 00 00 — Enable Configuration Interface
- Close frame
+
2 W 3C 00 00 00 — Poll Configuration Status Register
R xx xx bx xx
-
(Repeat until Busy Flag not set, or
wait 5us if not polling)
+
3 W 47 00 00 00 — Init UFM Address to 0000
-
+
4 W C9 00 00 01
00 01 02 03
04 05 06 07
08 09 0A 0B
0C 0D 0E 0F
Write UFM Page 0 Data
-
+
5 W 3C 00 00 00 — Poll Configuration Status Register
R xx xx bx xx
-
(repeat until Busy Flag not set, or
wait 200us if not polling)
+
6 W C9 00 00 01
10 11 12 13
14 15 16 17
18 19 1A 1B
1C 1D 1E 1F
Write UFM Page 1 Data
(Note: Address automatically incremented)
-
+
7 W 3C 00 00 00 — Poll Configuration Status Register
R xx xx bx xx
-
(poll until Busy Flag clear, or wait
200us if not polling)
+
8 W 26 00 00 — Disable Configuration Interface
-
+
9 W FF — — Bypass (NOP)
-
1. When accessing UFM/Configuration Flash via WISHBONE use CFGTXDR (0x71) to write data and CFDRXDR (0x73) to read data.
2. ‘+’ and ‘-’ refer to the command framing protocol appropriate for the interface, discussed in “WISHBONE Framing” on page 50. 17-68
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-96. Read One UFM Page (All Devices, WISHBONE/SPI)
Instruction
Number R/W1 CMD2 Operand Data Comment
+ Open frame
1 W 74 08 00 00 — Enable Configuration Interface
- Close frame
+
2 W 3C 00 00 00 — Poll Configuration Status Register
R xx xx bx xx
-
(Repeat until Busy Flag not set, or
wait 5us if not polling)
+
3 W B4 00 00 00 40 00 00 01 Set UFM Address to 0001
-
+
4 W CA 10 00 01 Read one page UFM (page 1) data
R
10 11 12 13
14 15 16 17
18 19 1A 1B
1C 1D 1E 1F
-
+
5 W 26 00 00 — Disable Configuration Interface
-
+
6 W FF — — Bypass (NOP)
-
1. When accessing UFM/Configuration Flash via WISHBONE use CFGTXDR (0x71) to write data and CFDRXDR (0x73) to read data.
2. ‘+’ and ‘-’ refer to the command framing protocol appropriate for the interface, discussed in “WISHBONE Framing” on page 50. 17-69
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Table 17-97. Read Two UFM Pages (WISHBONE/SPI)
Instruction
Number R/W1 CMD2 Operand Data Comment
+ Open frame
1 W 74 08 00 00 — Enable Configuration Interface
- Close frame
+
2 W 3C 00 00 00 — Poll Configuration Status Register
R xx xx bx xx
-
(Repeat until Busy Flag not set, or
wait 5us if not polling)
+
3 W 47 00 00 00 — Init UFM address to 0000
-
+
4 W CA 10 00 03 Read two pages of UFM data, after
one page of dummy bytes.3
R
xx xx xx xx
xx xx xx xx
xx xx xx xx
xx xx xx xx
00 01 02 03
04 05 06 07
08 09 0A 0B
0C 0D 0E 0F
10 11 12 13
14 15 16 17
18 19 1A 1B
1C 1D 1E 1F
-
+
5 W 26 00 00 — Disable Configuration Interface
-
+
6 W FF — — Bypass (NOP)
-
1. When accessing UFM/Configuration Flash via WISHBONE use CFGTXDR (0x71) to write data and CFDRXDR (0x73) to read data.
2. ‘+’ and ‘-’ refer to the command framing protocol appropriate for the interface
3. num_pages count must include dummy page.17-70
Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices Reference Guide
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
June 2012 01.0 Initial release.
August 2012 01.1 Timer/Counter Control 1 table – Corrected names of four LSBs.
Program Feature Row (0xE4) table – Updated Data Size and Data Format (Hex) columns and text below table for ss, uu and cc cc cc cc.
Added example.
Read Feature Row (0xE7) table – Updated CMD (Hex) column.
Read FEABITs (0xFB) table – Removed example below table.
Read USERCODE (0xC0) table – Data Size column updated. EN
Required” value changed from “N” to “Y/N” and example text updated.
Updated Timer/Counter Control 0 table and Timer/Counter Control 1
table.
Updated Basic Configuration Flash Update Example diagram.
Device ID Table – Updated Device Name column.
Read Status Register (0x3C) table – Updated Data Format column.
Verify Device ID Code (0xE2) table – “EN Required” value changed
from “N” to “Y” and example text updated.
October 2012 01.2 Added restriction: Primary port can be used as Configuration/UFM port
or as a user port, but not both.
Added restriction: Primary I2
C port is unavailable while in
ISC_ENABLE_X (transparent) configuration access mode.
April 2013 01.3 Read Configuration Flash (0x73) (I2
C/WISHBONE/SPI) table – Corrected table title.
Read Feature Row (0xE7) table – Updated Data Format in the table and
description.
Updated information in the I2
C Master Read/Write Example (via WISHBONE) figure.
Updated examples in the Read UFM (0xCA) (WISHBONE/SPI/I2
C)
table.
Added note: SECURITY and SECURITY PLUS commands are mutually
exclusive.
Added Erase/Program/Verify time calculation example.
Updated (decreased) the maximum WISHBONE clock rate for page
reads from 36MHz to 16.6MHz.
Corrected BUSY wait times (1000ns -> 200ns) in Write Two UFM Pages
table.
Updated Basic Configuration Flash Update Example, changed "Wait for
!BUSY" to "Wait for tREFRESH" in last step.
Added Wait for tREFRESH caution to Refresh command description.
Clarified Secondary I2
C non-idle reset issue after REFRESH.
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Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective
companies.
February 2013 #PB1334B
Lattice Ordering Guidelines for Standard Product
Lattice requests, at a minimum, that devices be purchased at the tube/tray quantity level and
recommend full box quantities as the optimal quantity level when volumes warrant it. Shipping in
full tube, tray and box quantities contributes significantly to the quality and accuracy of our
shipments buy eliminating the handling associated with partial box, tube or tray shipments. This
reduced handling minimizes device damage, moisture exposure and count errors.
Product Quantities Per Device Carrier
Package Type Package Size
(mm)
Package Pitch
(mm)
Device per
Tube / Tray
Tubes / Trays
per Box
Devices
per Box
20-Pin PDIP 6.4x26.2 2.54 18 / Tube 20 360
20-Pin CERDIP 7.3x24.1 2.54 19 / Tube 20 380
20-Pin PLCC 8.6x8.6 1.27 46 / Tube 10 460
20-Pin Ceramic LCC 9.1x9.1 2.54 56 / Tube 10 560
24-Pin CERDIP 7.3x31.8 2.54 15 / Tube 20 300
24-Pin PDIP 6.4x31.8 2.54 15 / Tube 20 300
24-Pin QFNS 4x4 0.5 560 / Tray 5 2,800
28-Pin PLCC 11.4x11.4 1.27 37 / Tube 10 370
28-Pin Ceramic LCC 11.7x11.7 1.27 42 / Tube 10 420
28-Pin SSOP 10.2x5.3 0.65 47 / Tube 10 470
32-Pin QFNS 5x5 0.5 490 / Tray 5 2,450
44-Pin Ceramic LCC 16.5x16.5 1.27 26 / Tube 30 780
44-Pin PLCC 16.5x16.5 1.27 26 / Tube 30 780
44-Pin TQFP 10x10 0.8 160 / Tray 5 800
48-Pin TQFP 7x7 0.5 250 / Tray 5 1,250
48-Pin QFNS 7x7 0.5 260 / Tray 5 1,300
64-Pin TQFP 10x10 0.5 160 / Tray 5 800
64-Pin QFNS 9x9 0.5 260 / Tray 5 1,300
68-Pin Ceramic LCC 24.1x24.1 1.27 21 / Tube 5 105
68-Pin PLCC 24.1x24.1 1.27 18 / Tube 30 540
84-Pin Ceramic PGA 29.2x29.2 2.54 10 / Tray 5 50
84-Pin PLCC 29.2x29.2 1.27 15 / Tube 30 450
100-Pin PQFP 14x20 0.65 66 / Tray 5 330
100-Pin TQFP 14x14 0.5 90 / Tray 5 450
120-Pin PQFP 28x28 0.8 24 / Tray 5 120
128-Pin PQFP 28x28 0.8 24 / Tray 5 120
128-Pin TQFP 14x14 0.4 90 / Tray 5 450
133-Pin Ceramic PGA 37.6x37.6 2.54 10 / Tray 5 50
144-Pin TQFP 20x20 0.5 60 / Tray 5 300
160-Pin PQFP 28x28 0.65 24 / Tray 5 120
176-Pin TQFP 24x24 0.5 40 / Tray 5 200
208-Pin PQFP 28x28 0.5 24 / Tray 5 120
Lead-Frame Packages
Product
BulletinLattice Semiconductor Home Page: http://w w w .latticesemi.com Applications & Literature Hotline: 1-800-LATTICE
Copyright 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corporation and Lattice (design) are either registered trademarks or trademarks of Lattice
Semiconductor Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective
companies.
Product Quantities Per Device Carrier (Cont’d)
Package Type Package Size
(mm)
Package Pitch
(mm)
Device per
Tube / Tray
Minimum Buy
(in Boxes)
Tubes / Trays /
Reels
per Box
Devices
per Box
25-Ball WLCSP ("TR") 2.5x2.5 0.4 5,000 / Reel 1 1 5,000
25-Ball WLCSP ("TR1K") 2.5x2.5 0.4 1,000 / Reel 1 1 1,000
25-Ball WLCSP ("TR50") 2.5x2.5 0.4 50 / Reel 1 1 50
49-Ball caBGA 7x7 0.8 416 / Tray 1 5 2,080
56-Ball csBGA 6x6 0.5 360 / Tray 1 5 1,800
64-Ball csBGA 5x5 0.5 490 / Tray 1 5 2,450
64-Ball ucBGA 4x4 0.4 490 / Tray 1 5 2,450
100-Ball caBGA 10x10 0.8 184 / Tray 1 5 920
100-Ball csBGA 8x8 0.5 360 / Tray 1 5 1,800
100-Ball fpBGA 11x11 1.0 176 / Tray 1 5 880
132-Ball csBGA 8x8 0.5 360 / Tray 1 5 1,800
132-Ball ucBGA 6x6 0.4 360 / Tray 1 5 1,800
144-Ball csBGA 7x7 0.5 360 / Tray 1 5 1,800
144-Ball fpBGA 13x13 1.0 160 / Tray 1 5 800
184-Ball csBGA 8x8 0.5 360 / Tray 1 5 1,800
208-Ball ftBGA 17x17 1.0 90 / Tray 1 5 450
208-Ball fpBGA 17x17 1.0 90 / Tray 1 5 450
256-Ball BGA 27x27 1.27 40 / Tray 1 5 200
256-Ball fpBGA 17x17 1.0 90 / Tray 1 5 450
256-Ball caBGA 14x14 0.8 119 / Tray 1 5 595
256-Ball ftBGA 17x17 1.0 90 / Tray 1 5 450
256-Ball SBGA 27x27 1.27 40 / Tray 1 5 200
272-Ball BGA 27x27 1.27 40 / Tray 1 5 200
320-Ball SBGA 31x31 1.27 27 / Tray 1 5 135
324-Ball ftBGA 19x19 1.0 84 / Tray 1 5 420
332-Ball caBGA 17x17 0.8 90 / Tray 1 5 450
352-Ball BGA 35x35 1.27 24 / Tray 1 5 120
352-Ball SBGA 35x35 1.27 24 / Tray 1 5 120
388-Ball BGA 35x35 1.27 24 / Tray 1 5 120
388-Ball fpBGA 23x23 1.0 60 / Tray 1 5 300
416-Ball fpBGA 27x27 1.0 40 / Tray 1 5 200
432-Ball SBGA 40x40 1.27 21 / Tray 1 5 105
484-Ball fpBGA 23x23 1.0 60 / Tray 1 5 300
516-Ball fpBGA 31x31 1.0 27 / Tray 1 5 135
672-Ball fpBGA 27x27 1.0 40 / Tray 1 5 200
676-Ball fpBGA 31x31 1.0 27 / Tray 1 5 135
680-Ball fpBGA 35x35 1.0 24 / Tray 1 5 120
680-Ball fpSBGA 40x40 1.0 21 / Tray 1 5 105
900-Ball fpBGA 31x31 1.0 27 / Tray 1 5 135
1020-Ball fcBGA 33x33 1.0 24 / Tray 1 3 72
1152-Ball fcBGA 35x35 1.0 24 / Tray 1 3 72
1152-Ball fpBGA 35x35 1.0 24 / Tray 1 5 120
1156-Ball fpBGA 35x35 1.0 24 / Tray 1 5 120
1704-Ball fcBGA 42.5x42.5 1.0 12 / Tray 1 3 36
Ball Gird Array Package (BGA)
MachXO2™ Family Data Sheet
DS1035 Version 02.0, January 2013www.latticesemi.com 1-1 DS1035 Introduction_01.6
January 2013 Data Sheet DS1035
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Features
Flexible Logic Architecture
• Six devices with 256 to 6864 LUT4s and
19 to 335 I/Os
Ultra Low Power Devices
• Advanced 65 nm low power process
• As low as 19 µW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options
Embedded and Distributed Memory
• Up to 240 Kbits sysMEM™ Embedded Block
RAM
• Up to 54 Kbits Distributed RAM
• Dedicated FIFO control logic
On-Chip User Flash Memory
• Up to 256 Kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I2
C and
JTAG interfaces
• Can be used as soft processor PROM or as
Flash memory
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with
DQS support
High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
Flexible On-Chip Clocking
• Eight primary clocks
• Up to two edge clocks for high-speed I/O
interfaces (top and bottom sides only)
• Up to two analog PLLs per device with
fractional-n frequency synthesis
– Wide input frequency range (10 MHz to
400 MHz)
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I2
C
• Supports background programming of non-volatile memory
• Optional dual boot with external SPI memory
TransFR™ Reconfiguration
• In-field logic update while system operates
Enhanced System Level Support
• On-chip hardened functions: SPI, I2
C, timer/
counter
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating
range
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
Broad Range of Package Options
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,
fpBGA, QFN package options
• Small footprint package options
– As small as 2.5x2.5mm
• Density migration supported
• Advanced halogen-free packaging
MachXO2 Family Data Sheet
Introduction1-2
Introduction
MachXO2 Family Data Sheet
Table 1-1. MachXO2™ Family Selection Guide
Introduction
The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from
256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature
Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and
hardened versions of commonly used functions such as SPI controller, I2
C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.
The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs
XO2-256 XO2-640 XO2-640U1
XO2-1200 XO2-1200U1
XO2-2000 XO2-2000U1
XO2-4000 XO2-7000
LUTs 256 640 640 1280 1280 2112 2112 4320 6864
Distributed RAM (Kbits) 2 5 5 10 10 16 16 34 54
EBR SRAM (Kbits) 0 18 64 64 74 74 92 92 240
Number of EBR SRAM
Blocks (9 Kbits/block)
Device Options
0 277 8 8 10 10 26
UFM (Kbits) 0 24 64 64 80 80 96 96 256
Number of PLLs
Packages I/Os
0
HC2
HE3
ZE4
0 1 1 11 2 22
Hardened Functions:
I
2
C
SPI
Timer/Counter
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
25 WLCSP5
(2.5 x 2.5mm, 0.4mm)
32 QFN
6
(5 x 5mm, 0.5mm)
18
64 ucBGA
(4 x 4mm, 0.4mm) 44
21
100 TQFP
(14 x 14mm)
132 csBGA
(8 x 8mm, 0.5mm)
144 TQFP
(20 x 20mm)
256 caBGA
(14 x 14mm, 0.8mm)
256 ftBGA
(17 x 17mm, 1.0mm)
332 caBGA
(17 x 17mm, 0.8mm)
484 fpBGA
(23 x 23mm, 1.0mm)
1. Ultra high I/O device.
2. High performance with regulator – VCC = 2.5V, 3.3V
3. High performance without regulator – VCC = 1.2V
4. Low power without regulator – VCC = 1.2V
5. WLCSP package only available for ZE devices.
6. QFN package only available for HC and ZE devices.
7. 184 csBGA package only available for HE devices.
278 278 334
274 278
206 206 206 206
206 206 206
107 107 111 114 114
55 79 104 104 104
55 78 79 79
184 csBGA7
(8 x 8mm, 0.5mm) 1501-3
Introduction
MachXO2 Family Data Sheet
and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low
static power for all members of the family.
The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE)
devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Similarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC
devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3V or 2.5V. ZE
and HE devices only accept 1.2V as the external VCC supply voltage. With the exception of power supply voltage
all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.
The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space
saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same
package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.
The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range
of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.
The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pulldown and bus-keeper features are controllable on a “per-pin” basis.
A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may
be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and similar state machines.
The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These
devices can also configure themselves from external SPI Flash or be configured by an external master through the
JTAG test access port or through the I2
C port. Additionally, MachXO2 devices support dual-boot capability (using
external Flash memory) and remote field upgrade (TransFR) capability.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the
MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice
design tools use the synthesis tool output along with the user-specified preferences and constraints to place and
route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into
the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of
reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft
core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.www.latticesemi.com 2-1 DS1035 Architecture_01.5
January 2013 Data Sheet DS1035
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Architecture Overview
The MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The
larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM
(EBRs). Figures 2-1 and 2-2 show the block diagrams of the various family members.
Figure 2-1. Top View of the MachXO2-1200 Device
Figure 2-2. Top View of the MachXO2-4000 Device
sysMEM Embedded
Block RAM (EBR)
sysCLOCK PLL
PIOs Arranged into
sysIO Banks
Programmable Function Units
with Distributed RAM (PFUs)
Embedded Function
Block (EFB)
User Flash Memory
(UFM)
On-chip Configuration
Flash Memory
Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a lower LUT count and no PLL or EBR blocks.
MachXO2-640 has no PLL, a lower LUT count and two EBR blocks. MachXO2-640U has a lower LUT count, one PLL and seven EBR blocks.
sysMEM Embedded
Block RAM (EBR)
Programmable Function Units
with Distributed RAM (PFUs)
On-chip Configuration
Flash Memory
sysCLOCK PLL
PIOs Arranged into
sysIO Banks
Embedded
Function Block(EFB)
User Flash
Memory (UFM)
Note: MachXO2-1200U, MachXO2-2000/U and MachXO2-7000 are similar to MachXO2-4000. MachXO2-1200U and MachXO2-2000 have a lower LUT count,
one PLL, and eight EBR blocks. MachXO2-2000U has a lower LUT count, two PLLs, and 10 EBR blocks. MachXO2-7000 has a higher LUT count, two PLLs,
and 26 EBR blocks.
MachXO2 Family Data Sheet
Architecture2-2
Architecture
MachXO2 Family Data Sheet
The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are
located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic,
RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports
operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing
channel resources. The place and route software tool automatically allocates these routing resources.
In the MachXO2 family, the number of sysIO banks varies by device. There are different types of I/O buffers on the
different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast
memory blocks; these blocks are found in MachXO2-640/U and larger devices. These blocks can be configured as
RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT
usage.
The MachXO2 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on MachXO2-
640U, MachXO2-1200/U and larger devices. These blocks are located at the ends of the on-chip Flash block. The
PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks.
MachXO2 devices provide commonly used hardened functions such as SPI controller, I2
C controller and timer/
counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These hardened
functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also
be accessed through the SPI, I2
C and JTAG ports.
Every device in the family has a JTAG port that supports programming and configuration of the device as well as
access to the user logic. The MachXO2 devices are available for operation from 3.3V, 2.5V and 1.2V power supplies, providing easy integration into the overall system.
PFU Blocks
The core of the MachXO2 device consists of PFU blocks, which can be programmed to perform logic, arithmetic,
distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0
to 3 as shown in Figure 2-3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs
associated with each PFU block.
Figure 2-3. PFU Block Diagram
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
FCIN FCO
D
FF/
Latch
D
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
From
Routin g
To
Routin g
Slice 3
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D 2-3
Architecture
MachXO2 Family Data Sheet
Slices
Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1
shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU
contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8.
The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chipselect and wider RAM/ROM functions.
Table 2-1. Resources and Modes Available per Slice
Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the
carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the
adjacent PFU). Table 2-2 lists the signals associated with Slices 0-3.
Figure 2-4. Slice Diagram
Slice
PFU Block
Resources Modes
Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM
Slice 1 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM
Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM
Slice 3 2 LUT4s and 2 Registers Logic, Ripple, ROM
LUT4 &
Carry
Slice
Flip-flop/
Latch
OFX0
F0
Q0
CI
CO
LUT4 &
Carry
CI
CO
OFX1
F1
Q1
F/SUM
F/SUM D
D
FCI From
Different
Slice/PFU
Memory &
Control
Signals
FCO To Different Slice/PFU
LUT5
From Mux
Routing
To
Routing
For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
• WCK is CLK
• WRE is from LSR
• DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
• WAD [A:D] is a 4-bit address from slice 2 LUT input
A0
C0
D0
A1
B1
C1
D1
CE
CLK
LSR
M1
M0
FXB
FXA
B0
Flip-flop/
Latch2-4
Architecture
MachXO2 Family Data Sheet
Table 2-2. Slice Signal Descriptions
Modes of Operation
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
Logic Mode
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16
possible input combinations. Any four input logic functions can be generated by programming this lookup table.
Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as
LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four
slices.
Ripple Mode
Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following functions can be implemented by each slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Up/down counter with asynchronous clear
• Up/down counter with preload (sync)
• Ripple mode multiplier building block
• Multiplier support
• Comparator functions of A and B inputs
– A greater-than-or-equal-to B
– A not-equal-to B
– A less-than-or-equal-to B
Function Type Signal Names Description
Input Data signal A0, B0, C0, D0 Inputs to LUT4
Input Data signal A1, B1, C1, D1 Inputs to LUT4
Input Multi-purpose M0/M1 Multi-purpose input
Input Control signal CE Clock enable
Input Control signal LSR Local set/reset
Input Control signal CLK System clock
Input Inter-PFU signal FCIN Fast carry in1
Output Data signals F0, F1 LUT4 output register bypass signals
Output Data signals Q0, Q1 Register outputs
Output Data signals OFX0 Output of a LUT5 MUX
Output Data signals OFX1 Output of a LUT6, LUT7, LUT82
MUX depending on the slice
Output Inter-PFU signal FCO Fast carry out1
1. See Figure 2-3 for connection details.
2. Requires two PFUs.2-5
Architecture
MachXO2 Family Data Sheet
Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices.
RAM Mode
In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0
and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. A 16x2-bit
Pseudo Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice as the read-only port.
MachXO2 devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of slices required to implement different distributed RAM primitives. For more information about
using RAM in MachXO2 devices, please see TN1201, Memory Usage Guide for MachXO2 Devices.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
ROM Mode
ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through
the programming interface during PFU configuration.
For more information on the RAM and ROM modes, please refer to TN1201, Memory Usage Guide for MachXO2
Devices.
Routing
There are many resources provided in the MachXO2 devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2
(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions.
The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and
route tool is completely automatic, although an interactive routing editor is available to optimize the design.
Clock/Control Distribution Network
Each MachXO2 device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins
each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These
eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to
drive the clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly.
The MachXO2 architecture has three types of clocking resources: edge clocks, primary clocks and secondary high
fanout nets. MachXO2-640U, MachXO2-1200/U and higher density devices have two edge clocks each on the top
and bottom edges. Lower density devices have no edge clocks. Edge clocks are used to clock I/O registers and
have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge
outputs and CIB sources.
SPR 16x4 PDPR 16x4
Number of slices 3 3
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM2-6
Architecture
MachXO2 Family Data Sheet
The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks
for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals,
MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such
as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the
global clock network for internally-generated global clocks and control signals.
The maximum frequency for the primary clock network is shown in the MachXO2 External Switching Characteristics table.
The primary clock signals for the MachXO2-256 and MachXO2-640 are generated from eight 17:1 muxes The
available clock sources include eight I/O sources and 9 routing inputs. Primary clock signals for the MachXO2-
640U, MachXO2-1200/U and larger devices are generated from eight 27:1 muxes The available clock sources
include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs.
Figure 2-5. Primary Clocks for MachXO2 Devices
8 11
Clock Pads
Routing
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
Primary Clock 4
Primary Clock 5
Primary Clock 6
8
Edge Clock
Divider
Primary clocks for MachXO2-640U, MachXO2-1200/U and larger devices.
Note: MachXO2-640 and smaller devices do not have inputs from the Edge Clock Divider or PLL
and fewer routing inputs. These devices have 17:1 muxes instead of 27:1 muxes.
Primary Clock 7
Dynamic
Clock
Enable
Dynamic
Clock
Enable
Dynamic
Clock
Enable
Dynamic
Clock
Enable
Dynamic
Clock
Enable
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
Up to 8
PLL Outputs
Dynamic
Clock
Enable
Dynamic
Clock
Enable
Dynamic
Clock
Enable
Clock
Switch
Clock
Switch2-7
Architecture
MachXO2 Family Data Sheet
Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2-6. One of the eight
inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven
come from internal routing. The maximum frequency for the secondary clock network is shown in MachXO2 External Switching Characteristics table.
Figure 2-6. Secondary High Fanout Nets for MachXO2 Devices
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The MachXO2-640U, MachXO2-1200/U
and larger devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its
source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which
can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output.
The MachXO2 sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency synthesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more
information about using the PLL with Fractional-N synthesis, please see TN1199, MachXO2 sysCLOCK PLL
Design and Usage Guide.
Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The
output dividers can have a value from 1 to 128. The CLKOS2 and CLKOS3 dividers may also be cascaded together
to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the
MachXO2 clock distribution network directly or general purpose routing resources can be used.
1 7
8:1
8:1
8:1
8:1
8:1
8:1
8:1
8:1
Clock Pads Routing
Secondary High
Fanout Net 0
Secondary High
Fanout Net 1
Secondary High
Fanout Net 2
Secondary High
Fanout Net 3
Secondary High
Fanout Net 4
Secondary High
Fanout Net 5
Secondary High
Fanout Net 6
Secondary High
Fanout Net 72-8
Architecture
MachXO2 Family Data Sheet
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is
detected. A block diagram of the PLL is shown in Figure 2-7.
The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2,
and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock.
This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode,
the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the
t
LOCK parameter has been satisfied.
The MachXO2 also has a feature that allows the user to select between two different reference clock sources
dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are
shown in the table.
The MachXO2 PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be
dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the
design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are
updated through the WISHBONE port the PLL may lose lock and not relock until the tLOCK parameter has been satisfied. The timing parameters for the PLL are shown in the table.
For more details on the PLL and the WISHBONE interface, see TN1199, MachXO2 sysCLOCK PLL Design and
Usage Guide.
Figure 2-7. PLL Diagram
CLKOP, CLKOS, CLKOS2, CLKOS3
REFCLK
Internal Feedback
FBKSEL
CLKOP
CLKOS
4
CLKOS2
CLKOS3
REFCLK
Divider
M (1 - 40)
LOCK
ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3
RST, RESETM, RESETC, RESETD
CLKFB
CLKI
Dynamic
Phase
Adjust
PHASESEL[1:0]
PHASEDIR
PHASESTEP
FBKCLK
Divider
N (1 - 40)
Fractional-N
Synthesizer
Phase detector,
VCO, and
loop filter.
CLKOS3
Divider
(1 - 128)
CLKOS2
Divider
(1 - 128)
Phase
Adjust
Phase
Adjust
Phase
Adjust/
Edge Trim
CLKOS
Divider
(1 - 128)
CLKOP
Divider
(1 - 128)
Lock
Detect
ClkEn
Synch
ClkEn
Synch
ClkEn
Synch
ClkEn
Synch
PLLDATO[7:0] , PLLACK PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]
A0
B0
C0
D0 D1
Mux
A2
Mux
B2
Mux
C2
Mux
D2
Mux
DPHSRC
Phase
Adjust/
Edge Trim STDBY2-9
Architecture
MachXO2 Family Data Sheet
Table 2-4 provides signal descriptions of the PLL block.
sysMEM Embedded Block RAM Memory
The MachXO2-640/U and larger devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a
9-Kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes
including data buffering, PROM for the soft processor and FIFO.
sysMEM Memory Block
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be
used in a variety of depths and widths as shown in Table 2-5.
Table 2-4. PLL Signal Descriptions
Port Name I/O Description
CLKI I Input clock to PLL
CLKFB I Feedback clock
PHASESEL[1:0] I Select which output is affected by Dynamic Phase adjustment ports
PHASEDIR I Dynamic Phase adjustment direction
PHASESTEP I Dynamic Phase step – toggle shifts VCO phase adjust by one step.
CLKOP O Primary PLL output clock (with phase shift adjustment)
CLKOS O Secondary PLL output clock (with phase shift adjust)
CLKOS2 O Secondary PLL output clock2 (with phase shift adjust)
CLKOS3 O Secondary PLL output clock3 (with phase shift adjust)
LOCK O PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and feedback signals.
DPHSRC O Dynamic Phase source – ports or WISHBONE is active
STDBY I Standby signal to power down the PLL
RST I PLL reset without resetting the M-divider. Active high reset.
RESETM I PLL reset - includes resetting the M-divider. Active high reset.
RESETC I Reset for CLKOS2 output divider only. Active high reset.
RESETD I Reset for CLKOS3 output divider only. Active high reset.
ENCLKOP I Enable PLL output CLKOP
ENCLKOS I Enable PLL output CLKOS when port is active
ENCLKOS2 I Enable PLL output CLKOS2 when port is active
ENCLKOS3 I Enable PLL output CLKOS3 when port is active
PLLCLK I PLL data bus clock input signal
PLLRST I PLL data bus reset. This resets only the data bus not any register values.
PLLSTB I PLL data bus strobe signal
PLLWE I PLL data bus write enable signal
PLLADDR [4:0] I PLL data bus address
PLLDATI [7:0] I PLL data bus data input
PLLDATO [7:0] O PLL data bus data output
PLLACK O PLL data bus acknowledge signal2-10
Architecture
MachXO2 Family Data Sheet
Table 2-5. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be
loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero
pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO2 devices have been designed such
that multiple EBRs share the same initialization memory space if they are initialized to the same pattern.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual, Pseudo-Dual Port and FIFO Modes
Figure 2-8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM
modes, the input data and addresses for the ports are registered at the input of the memory array. The output data
of the memory is optionally registered at the memory array output.
Memory Mode Configurations
Single Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
True Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
Pseudo Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
FIFO
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 182-11
Architecture
MachXO2 Family Data Sheet
Figure 2-8. sysMEM Memory Primitives
Table 2-6. EBR Signal Descriptions
Port Name Description Active State
CLK Clock Rising Clock Edge
CE Clock Enable Active High
OCE1
Output Clock Enable Active High
RST Reset Active High
BE1
Byte Enable Active High
WE Write Enable Active High
AD Address Bus —
DI Data In —
DO Data Out —
CS Chip Select Active High
AFF FIFO RAM Almost Full Flag —
FF FIFO RAM Full Flag —
AEF FIFO RAM Almost Empty Flag —
EF FIFO RAM Empty Flag —
RPRST FIFO RAM Read Pointer Reset —
1. Optional signals.
2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.
3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respectively.
4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).
5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the
read port chip select, ORE is the output read enable.
DI[17:0]
CLKW
WE
FIFO RAM
DO[17:0]
RST
FULLI
AFF
FF
AEF
EF
CLKR
RE
CSR[1:0]
ORE
RPRST
CSW[1:0] EMPTYI
ROM
DO[17:0]
AD[12:0]
CLK
CE
RST
CS[2:0]
OCE EBR EBR
AD[12:0]
DI[8:0]
DO[8:0]
CLK
CE
RST
WE
CS[2:0]
OCE
Single-Port RAM
ADA[12:0]
DIA[8:0]
CLKA
CEA
RSTA
WEA
CSA[2:0]
DOA[8:0]
OCEA
ADB[12:0]
DI[8:0]
CLKB
CEB
RSTB
WEB
CSB[2:0]
DOB[8:0]
OCEB
True Dual Port RAM
ADW[8:0]
DI[17:0]
CLKW
CEW
RST
CSW[2:0]
ADR[12:0]
CLKR
CER
DO[17:0]
CSR[2:0]
OCER
BE[1:0]
Pseudo Dual Port RAM
EBR EBR EBR2-12
Architecture
MachXO2 Family Data Sheet
The EBR memory supports three forms of write behavior for single or dual port operation:
1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – A copy of the input data appears at the output of the same port. This mode is supported for
all data widths.
3. Read-Before-Write – When new data is being written, the old contents of the address appears at the output.
FIFO Configuration
The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out,
RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The
Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.
Table 2-7 shows the range of programming values for these flags.
Table 2-7. Programmable FIFO Flag Ranges
The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset
that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset
state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is
in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from
the FIFO.
Memory Core Reset
The memory core contains data output latches for ports A and B. These are simple latches that can be reset synchronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with
port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and
associated resets for both ports are as shown in Figure 2-9.
Figure 2-9. Memory Core Reset
Flag Name Programming Range
Full (FF) 1 to max (up to 2N
-1)
Almost Full (AF) 1 to Full-1
Almost Empty (AE) 1 to Full-1
Empty (EF) 0
N = Address bit width.
Q
SET D
Output Data
Latches
Memory Core Port A[18:0]
Q
SET D Port B[18:0]
RSTB
GSRN
Programmable Disable
RSTA2-13
Architecture
MachXO2 Family Data Sheet
For further information on the sysMEM EBR block, please refer to TN1201, Memory Usage Guide for MachXO2
Devices.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before
the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-10. The GSR input
to the EBR is always asynchronous.
Figure 2-10. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device wake up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-10. The reset timing
rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST
and RPReset are always asynchronous EBR inputs. For more details refer to TN1201, Memory Usage Guide for
MachXO2 Devices.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
Programmable I/O Cells (PIC)
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysIO buffers and pads. On the MachXO2 devices, the PIO cells are assembled into groups of four PIO cells
called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.
On all the MachXO2 devices, two adjacent PIOs can be combined to provide a complementary output driver pair.
The MachXO2-640U, MachXO2-1200/U and higher density devices contain enhanced I/O capability. All PIO pairs
on these larger devices can implement differential receivers. Half of the PIO pairs on the top edge of these devices
can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these higher density devices
have on-chip differential termination and also provide PCI support.
Reset
Clock
Clock
Enable 2-14
Architecture
MachXO2 Family Data Sheet
Figure 2-11. Group of Four Programmable I/O Cells
1 PIC
PIO A
Output
Register Block
& Tristate
Register Block
Pin
A
Input Register
Block
PIO B
Output
Register Block
& Tristate
Register Block
Pin
B
Input Register
Block
PIO C
Output
Register Block
& Tristate
Register Block
Pin
C
Input Register
Block
Notes:
1. Input gearbox is available only in PIC on the bottom edge of MachXO2-640U, MachXO2-1200/U and larger devices.
2. Output gearbox is available only in PIC on the top edge of MachXO2-640U, MachXO2-1200/U and larger devices.
PIO D
Output
Register Block
& Tristate
Register Block
Pin
D
Input Register
Block
Core Logic/
Routing
Input
Gearbox
Output
Gearbox2-15
Architecture
MachXO2 Family Data Sheet
PIO
The PIO contains three blocks: an input register block, output register block and tri-state register block. These
blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic.
Table 2-8. PIO Signal List
Input Register Block
The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. In addition to this functionality, the input
register blocks for the PIOs on the right edge include built-in logic to interface to DDR memory.
Figure 2-12 shows the input register block for the PIOs located on the left, top and bottom edges. Figure 2-13
shows the input register block for the PIOs on the right edge.
Left, Top, Bottom Edges
Input signals are fed from the sysIO buffer to the input register block (as signal D). If desired, the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK).
If an input delay is desired, users can select a fixed delay. I/Os on the bottom edge also have a dynamic delay,
DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input
block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK)
by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to
sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams.
Pin Name I/O Type Description
CE Input Clock Enable
D Input Pin input from sysIO buffer.
INDD Output Register bypassed input.
INCK Output Clock input
Q0 Output DDR positive edge input
Q1 Output Registered input/DDR negative edge input
D0 Input Output signal from the core (SDR and DDR)
D1 Input Output signal from the core (DDR)
TD Input Tri-state signal from the core
Q Output Data output signals to sysIO Buffer
TQ Output Tri-state output signals to sysIO Buffer
DQSR901 Input DQS shift 90-degree read clock
DQSW901 Input DQS shift 90-degree write clock
DDRCLKPOL1 Input DDR input register polarity control signal from DQS
SCLK Input System clock for input and output/tri-state blocks.
RST Input Local set reset signal
1. Available in PIO on right edge only.2-16
Architecture
MachXO2 Family Data Sheet
Figure 2-12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges)
Right Edge
The input register block on the right edge is a superset of the same block on the top, bottom, and left edges. In
addition to the modes described above, the input register block on the right edge also supports DDR memory
mode.
In DDR memory mode, two registers are used to sample the data on the positive and negative edges of the modified DQS (DQSR90) in the DDR Memory mode creating two data streams. Before entering the core, these two data
streams are synchronized to the system clock to generate two data streams.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred to the system clock domain from the DQS domain. The DQSR90 and
DDRCLKPOL signals are generated in the DQS read-write block.
Figure 2-13. MachXO2 Input Register Block Diagram (PIO on Right Edge)
Output Register Block
The output register block registers signals from the core of the device before they are passed to the sysIO buffers.
Left, Top, Bottom Edges
In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type
register or latch.
SCLK
INCK
Q1
Q0
INDD
D
Q0
Q1
D Q
Programmable
Delay Cell D/L Q D Q
D Q
Q1
Q0
INDD
D
DQSR90
Q0
Q1
SCLK
S0
S1
DDRCLKPOL
Programmable
Delay Cell D/L Q
INCK
D Q
D Q D Q
D Q D Q D Q
D Q 2-17
Architecture
MachXO2 Family Data Sheet
In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling
edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to
switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.
Figure 2-14 shows the output register block on the left, top and bottom edges.
Figure 2-14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)
Right Edge
The output register block on the right edge is a superset of the output register on left, top and bottom edges of the
device. In addition to supporting SDR and Generic DDR modes, the output register blocks for PIOs on the right
edge include additional logic to support DDR-memory interfaces. Operation of this block is similar to that of the output register block on other edges.
In DDR memory mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling
edge the registered D1 input is registered into the register Q1. A multiplexer running off the DQSW90 signal is used
to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.
Figure 2-15 shows the output register block on the right edge.
Output path
D/L Q TQ
TD
Tri-state path
Q
D1 D Q D Q Q1
D/L Q
Q0
D0
SCLK 2-18
Architecture
MachXO2 Family Data Sheet
Figure 2-15. MachXO2 Output Register Block Diagram (PIO on the Right Edges)
Tri-state Register Block
The tri-state register block registers tri-state control signals from the core of the device before they are passed to
the sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that
then feeds the output.
The tri-state register blocks on the right edge contain an additional register for DDR memory operation. In DDR
memory mode, the register TS input is fed into another register that is clocked using the DQSW90 signal. The output of this register is used as a tri-state control.
Input Gearbox
Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed
as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2-9 shows the
gearbox signals.
Table 2-9. Input Gearbox Signal List
Name I/O Type Description
D Input High-speed data input after programmable delay in PIO A
input register block
ALIGNWD Input Data alignment signal from device core
SCLK Input Slow-speed system clock
ECLK[1:0] Input High-speed edge clock
RST Input Reset
Q[7:0] Output Low-speed data to device core:
Video RX(1:7): Q[6:0]
GDDRX4(1:8): Q[7:0]
GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7
GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3
D1 D Q D Q Q1
D/L Q
Q0
D0
DQSW90
Q
SCLK
D/L Q D Q TQ TD T0
Output Register Block
Tristate Register Block 2-19
Architecture
MachXO2 Family Data Sheet
These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by
the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment
based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the
data to the device core synchronized to the low-speed system clock. Figure 2-16 shows a block diagram of the
input gearbox.
Figure 2-16. Input Gearbox
D Q
D
ECLK0/1 SCLK
Q21
Q0_
S2
S0
D Q
D Q T2
T0
Q0
Q2
D Q
D Q
CE
D Q
CE
D Q
Q65
Q43
S6
S4
D Q
D Q T6
T4 D Q
cdn
D Q
CE
D Q
cdn
CE
D Q
Q54
Q_6
S3
S5
D
D
T3
T5
Q6
D Q
D Q
CE
D Q
CE
D Q
Q10
Q32
S1
D
T1
D Q
D Q
CE
Q65
Q65
Q43
Q43
Q21
Q10
Q21
Q32
Q54
Q_6
Q54
Q32
SEL0
Q4
Q5
Q1
Q3
S7
D Q
T7
D Q
CE
Q7
UPDATE
Q_6 2-20
Architecture
MachXO2 Family Data Sheet
More information on the input gearbox is available in TN1203, Implementing High-Speed Interfaces with MachXO2
Devices.
Output Gearbox
Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed
as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2-10 shows the
gearbox signals.
Table 2-10. Output Gearbox Signal List
The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the
low-speed system clock. The second stage registers transfer data from the low-speed clock registers to the highspeed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the
high-speed data out to the sysIO buffer. Figure 2-17 shows the output gearbox block diagram.
Name I/O Type Description
Q Output High-speed data output
D[7:0] Input Low-speed data from device core
Video TX(7:1): D[6:0]
GDDRX4(8:1): D[7:0]
GDDRX2(4:1)(IOL-A): D[3:0]
GDDRX2(4:1)(IOL-C): D[7:4]
SCLK Input Slow-speed system clock
ECLK [1:0] Input High-speed edge clock
RST Input Reset 2-21
Architecture
MachXO2 Family Data Sheet
Figure 2-17. Output Gearbox
More information on the output gearbox is available in TN1203, Implementing High-Speed Interfaces with
MachXO2 Devices.
DDR Memory Support
Certain PICs on the right edge of MachXO2-640U, MachXO2-1200/U and larger devices, have additional circuitry
to allow the implementation of DDR memory interfaces. There are two groups of 14 or 12 PIOs each on the right
edge with additional circuitry to implement DDR memory interfaces. This capability allows the implementation of up
to 16-bit wide memory interfaces. One PIO from each group contains a control element, the DQS Read/Write
D4
D0
D3
D1 T1 S1
S0
QC
ODDRx2_A
ODDRx2_C
ODDRx2_C
ECLK0/1
Q45
Q67
S4
S6 D Q
D Q
T4
T6 D6 D Q
D Q
CE
D Q
CE
0
1
0
1
Q01
Q23
S0
S2
T0
T2
Q32
Q10
S5
S3
Q D T5
T3
CE
0
1
D Q
Q76
Q54
S7 Q D T7
D Q
D Q
D Q
CE
0
1
S2
S4
GND
S7
S6
S5
S3 D2
D7
D5
SCLK
0
1
0
1
0
1
1
0
1
Q34
Q56
Q67
GND
Q45
S1
Q12
SEL /0
UPDATE
Q23
Q/QA
D Q
D Q
D Q
D Q
D Q D Q
D Q
D Q
D Q
D Q
D Q
0
1
0
1
0
1
0
1
0
1
0
CE
CE
D Q
CE
D Q
CE
0
1
0
1
CDN2-22
Architecture
MachXO2 Family Data Sheet
Block, to facilitate the generation of clock and control signals (DQSR90, DQSW90, DDRCLKPOL and DATAVALID).
These clock and control signals are distributed to the other PIO in the group through dedicated low skew routing.
DQS Read Write Block
Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock
(referred to as DQS) is not free-running so this approach cannot be used. The DQS Read Write block provides the
required clock alignment for DDR memory interfaces. DQSR90 and DQSW90 signals are generated by the DQS
Read Write block from the DQS input.
In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the read cycle) is unknown. The MachXO2 family contains dedicated circuits to
transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS
(delayed) and the system clock, a clock polarity selector is used. This circuit changes the edge on which the data is
registered in the synchronizing registers in the input register block. This requires evaluation at the start of each
read cycle for the correct clock polarity. Prior to the read operation in DDR memories, DQS is in tri-state (pulled by
termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit in the
DQS Read Write block detects the first DQS rising edge after the preamble state and generates the DDRCLKPOL
signal. This signal is used to control the polarity of the clock to the synchronizing registers.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
signals (6-bit bus) from a DLL on the right edge of the device. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of
standards that are found in today’s systems including LVCMOS, TTL, PCI, SSTL, HSTL, LVDS, BLVDS, MLVDS
and LVPECL.
Each bank is capable of supporting multiple I/O standards. In the MachXO2 devices, single-ended output buffers,
ratioed input buffers (LVTTL, LVCMOS and PCI), differential (LVDS) and referenced input buffers (SSTL and HSTL)
are powered using I/O supply voltage (VCCIO). Each sysIO bank has its own VCCIO. In addition, each bank has a
voltage reference, VREF, which allows the use of referenced input buffers independent of the bank VCCIO.
MachXO2-256 and MachXO2-640 devices contain single-ended ratioed input buffers and single-ended output buffers with complementary outputs on all the I/O banks. Note that the single-ended input buffers on these devices do
not contain PCI clamps. In addition to the single-ended I/O buffers these two devices also have differential and referenced input buffers on all I/Os. The I/Os are arranged in pairs, the two pads in the pair are described as “T” and
“C”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer.
MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 devices contain three
types of sysIO buffer pairs.
1. Left and Right sysIO Buffer Pairs
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers and
two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the left and
right of the devices also have differential and referenced input buffers.
2. Bottom sysIO Buffer Pairs
The sysIO buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the bottom also have
differential and referenced input buffers. Only the I/Os on the bottom banks have programmable PCI clamps 2-23
Architecture
MachXO2 Family Data Sheet
and differential input termination. The PCI clamp is enabled after VCC and VCCIO are at valid operating levels
and the device has been configured.
3. Top sysIO Buffer Pairs
The sysIO buffer pairs in the top bank of the device consist of two single-ended output drivers and two singleended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differential and referenced I/O buffers. Half of the sysIO buffer pairs on the top edge have true differential outputs.
The sysIO buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output
driver. The referenced input buffer can also be configured as a differential input buffer.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined
in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the
POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all
V
CCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that
are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pulldown to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default functionality). The I/O pins will maintain the blank configuration until VCC and VCCIO (for I/O banks containing configuration I/Os) have reached VPORUP levels at which time the I/Os will take on the user-configured settings only after a
proper download/configuration.
There are various ways a user can ensure that there are no spurious signals on critical outputs as the device powers up. These are discussed in more detail in TN1202, MachXO2 sysIO Usage Guide.
Supported Standards
The MachXO2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS, LVTTL, and PCI. The buffer supports the LVTTL, PCI, LVCMOS 1.2, 1.5, 1.8, 2.5,
and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive
strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS,
MLVDS and LVPECL output emulation is supported on all devices. The MachXO2-640U, MachXO2-1200/U and
higher devices support on-chip LVDS output buffers on approximately 50% of the I/Os on the top bank. Differential
receivers for LVDS, BLVDS, MLVDS and LVPECL are supported on all banks of MachXO2 devices. PCI support is
provided in the bottom bank of theMachXO2-640U, MachXO2-1200/U and higher density devices. Table 2-11 summarizes the I/O characteristics of the MachXO2 PLDs.
Tables 2-11 and 2-12 show the I/O standards (together with their supply and reference voltages) supported by the
MachXO2 devices. For further information on utilizing the sysIO buffer to support a variety of standards please see
TN1202, MachXO2 sysIO Usage Guide.
Table 2-11. I/O Support Device by Device
MachXO2-256,
MachXO2-640
MachXO2-640U,
MachXO2-1200
MachXO2-1200U
MachXO2-2000/U,
MachXO2-4000,
MachXO2-7000
Number of I/O Banks 4 4 6
Type of Input Buffers
Single-ended (all I/O banks)
Differential Receivers (all I/O
banks)
Single-ended (all I/O banks)
Differential Receivers (all I/O
banks)
Differential input termination
(bottom side)
Single-ended (all I/O banks)
Differential Receivers (all I/O
banks)
Differential input termination
(bottom side)2-24
Architecture
MachXO2 Family Data Sheet
Table 2-12. Supported Input Standards
Types of Output Buffers
Single-ended buffers with
complementary outputs (all I/O
banks)
Single-ended buffers with
complementary outputs (all I/O
banks)
Differential buffers with true
LVDS outputs (50% on top
side)
Single-ended buffers with
complementary outputs (all I/O
banks)
Differential buffers with true
LVDS outputs (50% on top
side)
Differential Output Emulation
Capability All I/O banks All I/O banks All I/O banks
PCI Clamp Support No Clamp on bottom side only Clamp on bottom side only
VCCIO (Typ.)
Input Standard 3.3V 2.5V 1.8V 1.5 1.2V
Single-Ended Interfaces
LVTTL 2
2
2
LVCMOS33 2
2
2
LVCMOS25
2
2
2
LVCMOS18
2
2
2
LVCMOS15
2
2
2
2
LVCMOS12
2
2
2
2
PCI1
SSTL18 (Class I, Class II)
SSTL25 (Class I, Class II)
HSTL18 (Class I, Class II)
Differential Interfaces
LVDS
BLVDS, MVDS, LVPECL, RSDS
Differential SSTL18 Class I, II
Differential SSTL25 Class I, II
Differential HSTL18 Class I, II
1. Bottom banks of MachXO2-640U, MachXO2-1200/U and higher density devices only.
2. Reduced functionality. Refer to TN1202, MachXO2 sysIO Usage Guide for more detail.
MachXO2-256,
MachXO2-640
MachXO2-640U,
MachXO2-1200
MachXO2-1200U
MachXO2-2000/U,
MachXO2-4000,
MachXO2-70002-25
Architecture
MachXO2 Family Data Sheet
Table 2-13. Supported Output Standards
sysIO Buffer Banks
The numbers of banks vary between the devices of this family. MachXO2-1200U, MachXO2-2000/U and higher
density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side).
The MachXO2-1200 and lower density devices have four banks (one bank per side). Figures 2-18 and 2-19 show
the sysIO banks and their associated supplies for all devices.
Output Standard VCCIO (Typ.)
Single-Ended Interfaces
LVTTL 3.3
LVCMOS33 3.3
LVCMOS25 2.5
LVCMOS18 1.8
LVCMOS15 1.5
LVCMOS12 1.2
LVCMOS33, Open Drain —
LVCMOS25, Open Drain —
LVCMOS18, Open Drain —
LVCMOS15, Open Drain —
LVCMOS12, Open Drain —
PCI33 3.3
SSTL25 (Class I) 2.5
SSTL18 (Class I) 1.8
HSTL18(Class I) 1.8
Differential Interfaces
LVDS1, 2 2.5, 3.3
BLVDS, MLVDS, RSDS 2
2.5
LVPECL2
3.3
Differential SSTL18 1.8
Differential SSTL25 2.5
Differential HSTL18 1.8
1. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers.
2. These interfaces can be emulated with external resistors in all devices.2-26
Architecture
MachXO2 Family Data Sheet
Figure 2-18. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 Banks
Figure 2-19. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks
Bank 0
Bank 1
Bank 2 Bank 3 Bank 4 Bank 5
VCCIO0
GND VCCIO2
GND
VCCIO1
GND
GND
GND
GND
VCCIO5
VCCIO4
VCCIO3
Bank 0
Bank 1
Bank 2
Bank 3
VCCIO0
GND VCCIO2
GND
VCCIO1
GND
VCCIO3
GND2-27
Architecture
MachXO2 Family Data Sheet
Hot Socketing
The MachXO2 devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of
the system. These capabilities make the MachXO2 ideal for many multiple power supply and hot-swap applications.
On-chip Oscillator
Every MachXO2 device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock
tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be
divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The
oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is
nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes
place:
1. Device powers up with a nominal MCLK frequency of 2.08 MHz.
2. During configuration, users select a different master clock frequency.
3. The MCLK frequency changes to the selected frequency once the clock configuration bits are received.
4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of 2.08 MHz.
Table 2-14 lists all the available MCLK frequencies.
Table 2-14. Available MCLK Frequencies
Embedded Hardened IP Functions and User Flash Memory
All MachXO2 devices provide embedded hardened functions such as SPI, I2
C and Timer/Counter. MachXO2-640/U
and higher density devices also provide User Flash Memory (UFM). These embedded blocks interface through the
WISHBONE interface with routing as shown in Figure 2-20.
MCLK (MHz, Nominal) MCLK (MHz, Nominal) MCLK (MHz, Nominal)
2.08 (default) 9.17 33.25
2.46 10.23 38
3.17 13.3 44.33
4.29 14.78 53.2
5.54 20.46 66.5
7 26.6 88.67
8.31 29.56 1332-28
Architecture
MachXO2 Family Data Sheet
Figure 2-20. Embedded Function Block Interface
Hardened I2
C IP Core
Every MachXO2 device contains two I2
C IP cores. These are the primary and secondary I2
C IP cores. Either of the
two cores can be configured either as an I2
C master or as an I2
C slave. The only difference between the two IP
cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.
When the IP core is configured as a master it will be able to control other devices on the I2
C bus through the interface. When the core is configured as the slave, the device will be able to provide I/O expansion to an I2
C Master.
The I2
C cores support the following functionality:
• Master and Slave operation
• 7-bit and 10-bit addressing
• Multi-master arbitration support
• Clock stretching
• Up to 400 KHz data transfer speed
• General call support
• Interface to custom logic through 8-bit WISHBONE interface
Embedded Function Block (EFB)
Core
Logic/
Routing EFB
WISHBONE
Interface
I
2
C (Primary)
I
2
C (Secondary)
SPI
Timer/Counter
PLL0 PLL1
Configuration
Logic
UFM
I/Os for I2
C
(Primary)
I/Os for SPI
I/Os for I2
C
(Secondary)
Indicates connection
through core logic/routing.
Power
Control2-29
Architecture
MachXO2 Family Data Sheet
Figure 2-21. I2
C Core Block Diagram
Table 2-15 describes the signals interfacing with the I2
C cores.
Table 2-15. I2
C Core Signal Description
Hardened SPI IP Core
Every MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core
is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core
is configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on
MachXO2 devices supports the following functions:
• Configurable Master and Slave modes
• Full-Duplex data transfer
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• LSB First or MSB First Data Transfer
• Interface to custom logic through 8-bit WISHBONE interface
Signal Name I/O Description
i2c_scl Bi-directional
Bi-directional clock line of the I2
C core. The signal is an output if the I2
C core is in master
mode. The signal is an input if the I2
C core is in slave mode. MUST be routed directly to the
pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for
detailed pad and pin locations of I2
C ports in each MachXO2 device.
i2c_sda Bi-directional
Bi-directional data line of the I2
C core. The signal is an output when data is transmitted from
the I2
C core. The signal is an input when data is received into the I2
C core. MUST be routed
directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this
document for detailed pad and pin locations of I2
C ports in each MachXO2 device.
i2c_irqo Output
Interrupt request output signal of the I2
C core. The intended usage of this signal is for it to be
connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and
request an interrupt when a specific condition is met. These conditions are described with
the I2
C register definitions.
cfg_wake Output
Wake-up signal – To be connected only to the power module of the MachXO2 device. The
signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2
C
Tab.
cfg_stdby Output
Stand-by signal – To be connected only to the power module of the MachXO2 device. The
signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2
C
Tab.
EFB
SCL
SDA
Configuration
Logic
Core
Logic/
Routing
Power
Control
I
2
C
Registers
EFB
WISHBONE
Interface
Control
Logic
I
2
C Function2-30
Architecture
MachXO2 Family Data Sheet
There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes:
• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology (Appendix B)
• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
Figure 2-22. SPI Core Block Diagram
Table 2-16 describes the signals interfacing with the SPI cores.
Table 2-16. SPI Core Signal Description
Hardened Timer/Counter
MachXO2 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional,
16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter supports the following functions:
Signal Name I/O Master/Slave Description
spi_csn[0] O Master SPI master chip-select output
spi_csn[1..7] O Master Additional SPI chip-select outputs (total up to eight slaves)
spi_scsn I Slave SPI slave chip-select input
spi_irq O Master/Slave Interrupt request
spi_clk I/O Master/Slave SPI clock. Output in master mode. Input in slave mode.
spi_miso I/O Master/Slave SPI data. Input in master mode. Output in slave mode.
spi_mosi I/O Master/Slave SPI data. Output in master mode. Input in slave mode.
ufm_sn I Slave Configuration Slave Chip Select (active low), dedicated for selecting the
User Flash Memory (UFM).
cfg_stdby O Master/Slave
Stand-by signal – To be connected only to the power module of the MachXO2
device. The signal is enabled only if the “Wakeup Enable” feature has been
set within the EFB GUI, SPI Tab.
cfg_wake O Master/Slave
Wake-up signal – To be connected only to the power module of the MachXO2
device. The signal is enabled only if the “Wakeup Enable” feature has been
set within the EFB GUI, SPI Tab.
EFB
SPI Function
Core
Logic/
Routing
EFB
WISHBONE
Interface
SPI
Registers
Control
Logic
Configuration
Logic
MISO
MOSI
SCK
MCSN
SCSN2-31
Architecture
MachXO2 Family Data Sheet
• Supports the following modes of operation:
– Watchdog timer
– Clear timer on compare match
– Fast PWM
– Phase and Frequency Correct PWM
• Programmable clock input source
• Programmable input clock prescaler
• One static interrupt output to routing
• One wake-up interrupt to on-chip standby mode controller.
• Three independent interrupt sources: overflow, output compare match, and input capture
• Auto reload
• Time-stamping support on the input capture unit
• Waveform generation on the output
• Glitch-free PWM waveform generation with variable PWM period
• Internal WISHBONE bus access to the control and status registers
• Stand-alone mode with preloaded control registers and direct reset input
Figure 2-23. Timer/Counter Block Diagram
Table 2-17. Timer/Counter Signal Description
For more details on these embedded functions, please refer to TN1205, Using User Flash Memory and Hardened
Control Functions in MachXO2 Devices.
Port I/O Description
tc_clki I Timer/Counter input clock signal
tc_rstn I Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled
tc_ic I Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If
enabled, a rising edge of this signal will be detected and synchronized to capture tc_cnt value
into tc_icr for time-stamping.
tc_int O Without WISHBONE – Can be used as overflow flag
With WISHBONE – Controlled by three IRQ registers
tc_oc O Timer counter output signal
EFB Timer/Counter
Core
Logic
Routing
PWM EFB
WISHBONE
Interface
Timer/
Counter
Registers
Control
Logic2-32
Architecture
MachXO2 Family Data Sheet
User Flash Memory (UFM)
MachXO2-640/U and higher density devices provide a User Flash Memory block, which can be used for a variety of
applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a
general purpose user Flash memory. The UFM block connects to the device core through the embedded function
block WISHBONE interface. Users can also access the UFM block through the JTAG, I2
C and SPI interfaces of the
device. The UFM block offers the following features:
• Non-volatile storage up to 256Kbits
• 100K write cycles
• Write access is performed page-wise; each page has 128 bits (16 bytes)
• Auto-increment addressing
• WISHBONE interface
For more information on the UFM, please refer to TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices.
Standby Mode and Power Saving Options
MachXO2 devices are available in three options for maximum flexibility: ZE, HC and HE devices. The ZE devices
have ultra low static and dynamic power consumption. These devices use a 1.2V core voltage that further reduces
power consumption. The HC and HE devices are designed to provide high performance. The HC devices have a
built-in voltage regulator to allow for 2.5V VCC and 3.3V VCC while the HE devices operate at 1.2V VCC.
MachXO2 devices have been designed with features that allow users to meet the static and dynamic power
requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset
circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings,
MachXO2 devices support an ultra low power Stand-by mode. While most of these features are available in all
three device types, these features are mainly intended for use with MachXO2 ZE devices to manage power consumption.
In the stand-by mode the MachXO2 devices are powered on and configured. Internal logic, I/Os and memories are
switched on and remain operational, as the user logic waits for an external input. The device enters this mode
when the standby input of the standby controller is toggled or when an appropriate I2
C or JTAG instruction is issued
by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry etc can be
configured such that they are automatically turned “off” or go into a low power consumption state to save power
when the device enters this state.2-33
Architecture
MachXO2 Family Data Sheet
Table 2-18. MachXO2 Power Saving Features Description
For more details on the standby mode refer to TN1198, Power Estimation and Management for MachXO2 Devices.
Power On Reset
MachXO2 devices have power-on reset circuitry to monitor VCCINT and VCCIO voltage levels during power-up and
operation. At power-up, the POR circuitry monitors VCCINT and VCCIO0 (controls configuration) voltage levels. It
then triggers download from the on-chip configuration Flash memory after reaching the VPORUP level specified in
the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For devices
without voltage regulators (ZE and HE devices), VCCINT is the same as the VCC supply voltage. For devices with
voltage regulators (HC devices), VCCINT is regulated from the VCC supply voltage. From this voltage reference, the
time taken for configuration and entry into user mode is specified as Flash Download Time (tREFRESH) in the DC
and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os are held in tristate. I/Os are released to user functionality once the device has finished configuration. Note that for HC devices, a
separate POR circuit monitors external VCC voltage in addition to the POR circuit that monitors the internal postregulated power supply voltage level.
Once the device enters into user mode, the POR circuitry can optionally continue to monitor VCCINT levels. If
V
CCINT drops below VPORDNBG level (with the bandgap circuitry switched on) or below VPORDNSRAM level (with the
bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation
the POR issues a reset and begins monitoring the VCCINT and VCCIO voltage levels. VPORDNBG and VPORDNSRAM
are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data
sheet.
Note that once a ZE or HE device enters user mode, users can switch off the bandgap to conserve power. When
the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a minimal, low power POR circuit is still operational (this corresponds to the VPORDNSRAM reset point described in the
paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched
on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells
flip. If users are concerned about the VCC supply dropping below VCC (min) they should not shut down the bandgap
or POR circuit.
Device Subsystem Feature Description
Bandgap
The bandgap can be turned off in standby mode. When the Bandgap is turned off, analog circuitry such as the POR, PLLs, on-chip oscillator, and referenced and differential
I/O buffers are also turned off. Bandgap can only be turned off for 1.2V devices.
Power-On-Reset (POR)
The POR can be turned off in standby mode. This monitors VCC levels. In the event of
unsafe VCC drops, this circuit reconfigures the device. When the POR circuitry is turned
off, limited power detector circuitry is still active. This option is only recommended for applications in which the power supply rails are reliable.
On-Chip Oscillator The on-chip oscillator has two power saving features. It may be switched off if it is not
needed in your design. It can also be turned off in Standby mode.
PLL
Similar to the on-chip oscillator, the PLL also has two power saving features. It can be
statically switched off if it is not needed in a design. It can also be turned off in Standby
mode. The PLL will wait until all output clocks from the PLL are driven low before powering off.
I/O Bank Controller
Referenced and differential I/O buffers (used to implement standards such as HSTL,
SSTL and LVDS) consume more than ratioed single-ended I/Os such as LVCMOS and
LVTTL. The I/O bank controller allows the user to turn these I/Os off dynamically on a
per bank selection.
Dynamic Clock Enable for Primary
Clock Nets Each primary clock net can be dynamically disabled to save power.
Power Guard
Power Guard is a feature implemented in input buffers. This feature allows users to
switch off the input buffer when it is not needed. This feature can be used in both clock
and data paths. Its biggest impact is that in the standby mode it can be used to switch off
clock inputs that are distributed using general routing resources.2-34
Architecture
MachXO2 Family Data Sheet
Configuration and Testing
This section describes the configuration and testing features of the MachXO2 family.
IEEE 1149.1-Compliant Boundary Scan Testability
All MachXO2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with VCCIO
Bank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.
For more details on boundary scan test, see AN8066, Boundary Scan Testability with Lattice sysIO Capability and
TN1087, Minimizing System Interruption During Configuration Using TransFR Technology.
Device Configuration
All MachXO2 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I2
C or
SPI. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532
In-System Configuration specification. There are various ways to configure a MachXO2 device:
1. Internal Flash Download
2. JTAG
3. Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory
4. System microprocessor to drive a serial slave SPI port (SSPI mode)
5. Standard I2
C Interface to system microprocessor
Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a
configuration port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be
activated any time after power-up by sending the appropriate command through the TAP port. Optionally the device can run a CRC check upon entering the user mode. This will ensure that the device was configured correctly.
The sysCONFIG port has 10 dual-function pins which can be used as general purpose I/Os if they are not required
for configuration. See TN1204, MachXO2 Programming and Configuration Usage Guide for more information
about using the dual-use pins as general purpose I/Os.
Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO2
devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technology is unable to compress bitstreams to fit into the amount of on-chip Flash memory, there are a variety of techniques that can be utilized to allow the bitstream to fit in the on-chip Flash memory. For more details, refer to
TN1204, MachXO2 Programming and Configuration Usage Guide.
The Test Access Port (TAP) has five dual purpose pins (TDI, TDO, TMS and TCK). These pins are dual function
pins - TDI, TDO, TMS and TCK can be used as general purpose I/O if desired. For more details, refer to TN1204,
MachXO2 Programming and Configuration Usage Guide.
TransFR (Transparent Field Reconfiguration)
TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a simple push-button solution. For more details refer to TN1087, Minimizing System Interruption During Configuration Using TransFR Technology for details.
Security and One-Time Programmable Mode (OTP)2-35
Architecture
MachXO2 Family Data Sheet
For applications where security is important, the lack of an external bitstream provides a solution that is inherently
more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO2 devices contain
security bits that, when set, prevent the readback of the SRAM configuration and non-volatile Flash memory
spaces. The device can be in one of two modes:
1. Unlocked – Readback of the SRAM configuration and non-volatile Flash memory spaces is allowed.
2. Permanently Locked – The device is permanently locked.
Once set, the only way to clear the security bits is to erase the device. To further complement the security of the
device, a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to
erase or re-program the Flash and SRAM OTP portions of the device. For more details, refer to TN1204, MachXO2
Programming and Configuration Usage Guide.
Dual Boot
MachXO2 devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the primary
bitstream is found to be corrupt while being downloaded into the SRAM, the device shall then automatically re-boot
from the golden bitstream. Note that the primary bitstream must reside in the on-chip Flash. The golden image
MUST reside in an external SPI Flash. For more details, refer to TN1204, MachXO2 Programming and Configuration Usage Guide.
Soft Error Detection
The SED feature is a CRC check of the SRAM cells after the device is configured. This check ensures that the
SRAM cells were configured successfully. This feature is enabled by a configuration bit option. The Soft Error
Detection can also be initiated in user mode via an input to the fabric. The clock for the Soft Error Detection circuit
is generated using a dedicated divider. The undivided clock from the on-chip oscillator is the input to this divider.
For low power applications users can switch off the Soft Error Detection circuit. For more details, refer to TN1206,
MachXO2 Soft Error Detection Usage Guide.
TraceID
Each MachXO2 device contains a unique (per device), TraceID that can be used for tracking purposes or for IP
security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits
are factory-programmed. The TraceID is accessible through the EFB WISHBONE interface and can also be
accessed through the SPI, I2
C, or JTAG interfaces.
Density Shifting
The MachXO2 family has been designed to enable density migration within the same package. Furthermore, the
architecture ensures a high success rate when performing design migration from lower density devices to higher
density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density
device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. For more details refer to the MachXO2 migration files.www.latticesemi.com 3-1 DS1035 DC and Switching_01.8
January 2013 Data Sheet DS1035
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Absolute Maximum Ratings1, 2, 3, 4
MachXO2 ZE/HE (1.2V) MachXO2 HC (2.5V/3.3V)
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V
Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
I/O Tri-state Voltage Applied5
. . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
Dedicated Input Voltage Applied . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
Storage Temperature (Ambient). . . . . . . . . . . . . . -55°C to 125°C . . . . . . . . . . . . . -55°C to 125°C
Junction Temperature (TJ
) . . . . . . . . . . . . . . . . . . -40°C to 125°C . . . . . . . . . . . . . -40°C to 125°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
5. The dual function I2
C pins SCL and SDA are limited to -0.25V to 3.75V or to -0.3V with a duration of <20ns.
Recommended Operating Conditions1
Power Supply Ramp Rates1
Symbol Parameter Min. Max. Units
V
CC
1
Core Supply Voltage for 1.2V Devices 1.14 1.26 V
Core Supply Voltage for 2.5V/3.3V Devices 2.375 3.465 V
V
CCIO
1, 2, 3 I/O Driver Supply Voltage 1.14 3.465 V
t
JCOM Junction Temperature Commercial Operation 0 85 °C
t
JIND Junction Temperature Industrial Operation -40 100 °C
1. Like power supplies must be tied together. For example, if VCCIO and VCC are both the same voltage, they must also be the same
supply.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
Symbol Parameter Min. Typ. Max. Units
t
RAMP Power supply ramp rates for all power supplies. 0.01 — 100 V/ms
1. Assumes monotonic ramp rates.
MachXO2 Family Data Sheet
DC and Switching Characteristics3-2
DC and Switching Characteristics
MachXO2 Family Data Sheet
Power-On-Reset Voltage Levels1, 2, 3, 4
Programming/Erase Specifications
Hot Socketing Specifications1, 2, 3
ESD Performance
Please refer to the MachXO2 Product Family Qualification Summary for complete qualification data, including ESD
performance.
Symbol Parameter Min. Typ. Max. Units
VPORUP
Power-On-Reset ramp up trip point (band gap based circuit
monitoring VCCINT and VCCIO)
0.9 — 1.06 V
VPORUPEXT
Power-On-Reset ramp up trip point (band gap based circuit
monitoring external VCC power supply) 1.5 — 2.1 V
VPORDNBG
Power-On-Reset ramp down trip point (band gap based circuit
monitoring VCCINT)
— — 0.93 V
VPORDNSRAM
Power-On-Reset ramp down trip point (SRAM based circuit
monitoring VCCINT)
— 0.6 — V
1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions.
2. For devices without voltage regulators VCCINT is the same as the VCC supply voltage. For devices with voltage regulators, VCCINT is regulated from the VCC supply voltage.
3. Note that VPORUP (min.) and VPORDNBG (max.) are in different process corners. For any given process corner VPORDNBG (max.) is always
12.0mV below VPORUP (min.).
4. VPORUPEXT is for HC devices only. In these devices a separate POR circuit monitors the external VCC power supply.
Symbol Parameter Min. Max.1
Units
NPROGCYC
Flash Programming cycles per tRETENTION — 10,000
Cycles
Flash functional programming cycles — 100,000
t
RETENTION
Data retention at 100°C junction temperature 10 —
Years
Data retention at 85°C junction temperature 20 —
1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product.
Symbol Parameter Condition Max. Units
I
DK Input or I/O leakage Current 0 < VIN < VIH (MAX) +/-1000 µA
1. Insensitive to sequence of VCC and VCCIO. However, assumes monotonic rise/fall rates for VCC and VCCIO.
2. 0 < VCC < VCC (MAX), 0 < VCCIO < VCCIO (MAX).
3. IDK is additive to IPU, IPD or IBH.3-3
DC and Switching Characteristics
MachXO2 Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
I
IL, IIH
1, 4 Input or I/O Leakage
Clamp OFF and VCCIO < VIN < VIH (MAX) — — +175 µA
Clamp OFF and VIN = VCCIO -10 — 10 µA
Clamp OFF and VCCIO - 0.97V < VIN <
V
CCIO
-175 — — µA
Clamp OFF and 0V < VIN < VCCIO - 0.97V — — 10 µA
Clamp OFF and VIN = GND — — 10 µA
Clamp ON and 0V < VIN < VCCIO — — 10 µA
I
PU I/O Active Pull-up Current 0 < VIN < 0.7 VCCIO -30 — -309 µA
I
PD
I/O Active Pull-down
Current VIL (MAX) < VIN < VCCIO 30 — 305 µA
I
BHLS
Bus Hold Low sustaining
current VIN = VIL (MAX) 30 — — µA
I
BHHS
Bus Hold High sustaining
current VIN = 0.7VCCIO -30 — — µA
I
BHLO
Bus Hold Low Overdrive
current 0 VIN V
CCIO — — 305 µA
I
BHHO
Bus Hold High Overdrive
current 0 VIN V
CCIO — — -309 µA
VBHT
3
Bus Hold Trip Points VIL
(MAX) —
VIH
(MIN) V
C1 I/O Capacitance2
V
CCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
V
CC = Typ., VIO = 0 to VIH (MAX) 3 5 9 pf
C2 Dedicated Input
Capacitance2
V
CCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
V
CC = Typ., VIO = 0 to VIH (MAX) 3 5.5 7 pf
V
HYST
Hysteresis for Schmitt
Trigger Inputs5
V
CCIO = 3.3V, Hysteresis = Large — 450 — mV
V
CCIO = 2.5V, Hysteresis = Large — 250 — mV
V
CCIO = 1.8V, Hysteresis = Large — 125 — mV
V
CCIO = 1.5V, Hysteresis = Large — 100 — mV
V
CCIO = 3.3V, Hysteresis = Small — 250 — mV
V
CCIO = 2.5V, Hysteresis = Small — 150 — mV
V
CCIO = 1.8V, Hysteresis = Small — 60 — mV
V
CCIO = 1.5V, Hysteresis = Small — 40 — mV
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. TA 25°C, f = 1.0MHz.
3. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document.
4. When VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the high-tolow transition. For true LVDS output pins in MachXO2-640U, MachXO2-1200/U and larger devices, VIH must be less than or equal to VCCIO.
5. With bus keeper circuit turned on. For more details, refer to TN1202, MachXO2 sysIO Usage Guide.3-4
DC and Switching Characteristics
MachXO2 Family Data Sheet
Static Supply Current – ZE Devices1, 2, 3, 6
Static Power Consumption Contribution of Different Components –
ZE Devices
The table below can be used for approximating static power consumption. For a more accurate power analysis for
your design please use the Power Calculator tool.
Symbol Parameter Device Typ.4
Units
I
CC Core Power Supply
LCMXO2-256ZE 18 µA
LCMXO2-640ZE 28 µA
LCMXO2-1200ZE 56 µA
LCMXO2-2000ZE 80 µA
LCMXO2-4000ZE 124 µA
LCMXO2-7000ZE 189 µA
I
CCIO
Bank Power Supply5
V
CCIO = 2.5V All devices 0 mA
1. For further information on supply current, please refer to TN1198, Power Estimation and Management for MachXO2 Devices.
2. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO
or GND, on-chip oscillator is off, on-chip PLL is off. To estimate the impact of turning each of these items on, please refer to the following
table or for more detail with your specific design use the Power Calculator tool.
3. Frequency = 0 MHz.
4. TJ
= 25°C, power supplies at nominal voltage.
5. Does not include pull-up/pull-down.
6. To determine the MachXO2 peak start-up current data, use the Power Calculator tool.
Symbol Parameter Typ. Units
I
DCBG Bandgap DC power contribution 101 µA
I
DCPOR POR DC power contribution 38 µA
I
DCIOBANKCONTROLLER DC power contribution per I/O bank controller 143 µA3-5
DC and Switching Characteristics
MachXO2 Family Data Sheet
Static Supply Current – HC/HE Devices1, 2, 3, 6
Programming and Erase Flash Supply Current – ZE Devices1, 2, 3, 4
Symbol Parameter Device Typ.4
Units
I
CC Core Power Supply
LCMXO2-256HC 1.15 mA
LCMXO2-640HC 1.84 mA
LCMXO2-640UHC 3.48 mA
LCMXO2-1200HC 3.49 mA
LCMXO2-1200UHC 4.80 mA
LCMXO2-2000HC 4.80 mA
LCMXO2-2000UHC 8.44 mA
LCMXO2-4000HC 8.45 mA
LCMXO2-7000HC 12.87 mA
LCMXO2-2000HE 1.39 mA
LCMXO2-4000HE 2.55 mA
LCMXO2-7000HE 4.06 mA
I
CCIO
Bank Power Supply5
V
CCIO = 2.5V All devices 0 mA
1. For further information on supply current, please refer to TN1198, Power Estimation and Management for MachXO2 Devices.
2. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or
GND, on-chip oscillator is off, on-chip PLL is off.
3. Frequency = 0 MHz.
4. TJ
= 25°C, power supplies at nominal voltage.
5. Does not include pull-up/pull-down.
6. To determine the MachXO2 peak start-up current data, use the Power Calculator tool.
Symbol Parameter Device Typ.5
Units
I
CC Core Power Supply
LCMXO2-256ZE 13 mA
LCMXO2-640ZE 14 mA
LCMXO2-1200ZE 15 mA
LCMXO2-2000ZE 17 mA
LCMXO2-4000ZE 18 mA
LCMXO2-7000ZE 20 mA
I
CCIO Bank Power Supply6
All devices 0 mA
1. For further information on supply current, please refer to TN1198, Power Estimation and Management for MachXO2 Devices.
2. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
3. Typical user pattern.
4. JTAG programming is at 25 MHz.
5. TJ = 25°C, power supplies at nominal voltage.
6. Per bank. VCCIO = 2.5V. Does not include pull-up/pull-down.3-6
DC and Switching Characteristics
MachXO2 Family Data Sheet
Programming and Erase Flash Supply Current – HC/HE Devices1, 2, 3, 4
Symbol Parameter Device Typ.5
Units
I
CC Core Power Supply
LCMXO2-256HC 14.6 mA
LCMXO2-640HC 16.1 mA
LCMXO2-640UHC 18.8 mA
LCMXO2-1200HC 18.8 mA
LCMXO2-1200UHC 22.1 mA
LCMXO2-2000HC 22.1 mA
LCMXO2-2000UHC 26.8 mA
LCMXO2-4000HC 26.8 mA
LCMXO2-7000HC 33.2 mA
LCMXO2-2000HE 18.3 mA
LCMXO2-2000UHE 20.4 mA
LCMXO2-4000HE 20.4 mA
LCMXO2-7000HE 23.9 mA
I
CCIO Bank Power Supply6
All devices 0 mA
1. For further information on supply current, please refer to TN1198, Power Estimation and Management for MachXO2 Devices.
2. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
3. Typical user pattern.
4. JTAG programming is at 25 MHz.
5. TJ
= 25°C, power supplies at nominal voltage.
6. Per bank. VCCIO = 2.5V. Does not include pull-up/pull-down.3-7
DC and Switching Characteristics
MachXO2 Family Data Sheet
sysIO Recommended Operating Conditions
Standard
V
CCIO (V) VREF (V)
Min. Typ. Max. Min. Typ. Max.
LVCMOS 3.3 3.135 3.3 3.465 — — —
LVCMOS 2.5 2.375 2.5 2.625 — — —
LVCMOS 1.8 1.71 1.8 1.89 — — —
LVCMOS 1.5 1.425 1.5 1.575 — — —
LVCMOS 1.2 1.14 1.2 1.26 — — —
LVTTL 3.135 3.3 3.465 — — —
PCI3
3.135 3.3 3.465 — — —
SSTL25 2.375 2.5 2.625 1.15 1.25 1.35
SSTL18 1.71 1.8 1.89 0.833 0.9 0.969
HSTL18 1.71 1.8 1.89 0.816 0.9 1.08
LVDS251, 2 2.375 2.5 2.625 — — —
LVDS331, 2 3.135 3.3 3.465 — — —
LVPECL1
3.135 3.3 3.465 — — —
BLVDS1
2.375 2.5 2.625 — — —
RSDS1
2.375 2.5 2.625 — — —
SSTL18D 1.71 1.8 1.89 — — —
SSTL25D 2.375 2.5 2.625 — — —
HSTL18D 1.71 1.8 1.89 — — —
1. Inputs on-chip. Outputs are implemented with the addition of external resistors.
2. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers
3. Input on the bottom bank of the MachXO2-640U, MachXO2-1200/U and larger devices only.3-8
DC and Switching Characteristics
MachXO2 Family Data Sheet
sysIO Single-Ended DC Electrical Characteristics1, 2
Input/Output
Standard
VIL VIH V
OL Max.
(V)
V
OH Min.
(V)
I
OL Max.4
(mA)
I
OH Max.4
Min. (V) (mA) 3
Max. (V) Min. (V) Max. (V)
LVCMOS 3.3
LVTTL -0.3 0.8 2.0 3.6
0.4 VCCIO - 0.4
4 -4
8 -8
12 -12
16 -16
24 -24
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 2.5 -0.3 0.7 1.7 3.6
0.4 VCCIO - 0.4
4 -4
8 -8
12 -12
16 -16
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 1.8 -0.3 0.35VCCIO 0.65VCCIO 3.6
0.4 VCCIO - 0.4
4 -4
8 -8
12 -12
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 1.5 -0.3 0.35VCCIO 0.65VCCIO 3.6
0.4 VCCIO - 0.4
4 -4
8 -8
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 1.2 -0.3 0.35VCCIO 0.65VCCIO 3.6
0.4 VCCIO - 0.4
4 -2
8 -6
0.2 VCCIO - 0.2 0.1 -0.1
PCI -0.3 0.3VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 -0.5
SSTL25 Class I -0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 8 8
SSTL25 Class II -0.3 VREF - 0.18 VREF +0.18 3.6 NA NA NA NA
SSTL18 Class I -0.3 VREF - 0.125 VREF +0.125 3.6 0.40 VCCIO - 0.40 8 8
SSTL18 Class II -0.3 VREF - 0.125 VREF +0.125 3.6 NA NA NA NA
HSTL18 Class I -0.3 VREF - 0.1 VREF +0.1 3.6 0.40 VCCIO - 0.40 8 8
HSTL18 Class II -0.3 VREF - 0.1 VREF +0.1 3.6 NA NA NA NA
1. MachXO2 devices allow LVCMOS inputs to be placed in I/O banks where VCCIO is different from what is specified in the applicable JEDEC
specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC specification. The cases where MachXO2 devices do not meet the relevant JEDEC specification are documented in the table below.
2. MachXO2 devices allow for LVCMOS referenced I/Os which follow applicable JEDEC specifications. For more details about mixed mode
operation please refer to please refer to TN1202, MachXO2 sysIO Usage Guide.
3. The dual function I2
C pins SCL and SDA are limited to a VIL min of -0.25V or to -0.3V with a duration of <10ns.
4. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
Input Standard VCCIO (V) VIL Max. (V)
LVCMOS 33 1.5 0.685
LVCMOS 25 1.5 1.687
LVCMOS 18 1.5 1.1643-9
DC and Switching Characteristics
MachXO2 Family Data Sheet
sysIO Differential Electrical Characteristics
The LVDS differential output buffers are available on the top side of MachXO2-640U, MachXO2-1200/U and higher
density devices in the MachXO2 PLD family.
LVDS
Over Recommended Operating Conditions
Parameter
Symbol Parameter Description Test Conditions Min. Typ. Max. Units
VINP, VINM
Input Voltage VCCIO = 3.3 0 — 2.605 V
V
CCIO = 2.5 0 — 2.05 V
VTHD Differential Input Threshold ±100 — mV
V
CM Input Common Mode Voltage
V
CCIO = 3.3V 0.05 — 2.6 V
V
CCIO = 2.5V 0.05 — 2.0 V
I
IN Input current Power on — — ±10 µA
V
OH Output high voltage for VOP or VOM RT
= 100 Ohm — 1.375 — V
V
OL Output low voltage for VOP or VOM RT
= 100 Ohm 0.90 1.025 — V
V
OD Output voltage differential (VOP - VOM), RT
= 100 Ohm 250 350 450 mV
V
OD Change in VOD between high and low — — 50 mV
V
OS Output voltage offset (VOP - VOM)/2, RT
= 100 Ohm 1.125 1.20 1.395 V
V
OS Change in VOS between H and L — — 50 mV
I
OSD Output short circuit current VOD = 0V driver outputs shorted — — 24 mA3-10
DC and Switching Characteristics
MachXO2 Family Data Sheet
LVDS Emulation
MachXO2 devices can support LVDS outputs via emulation (LVDS25E). The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in
Figure 3-1 is one possible solution for LVDS standard implementation. Resistor values in Figure 3-1 are industry
standard values for 1% resistors.
Figure 3-1. LVDS Using External Resistors (LVDS25E)
Table 3-1. LVDS25E DC Conditions
Over Recommended Operating Conditions
Parameter Description Typ. Units
Z
OUT Output impedance 20 Ohms
RS
Driver series resistor 158 Ohms
RP
Driver parallel resistor 140 Ohms
RT
Receiver termination 100 Ohms
V
OH Output high voltage 1.43 V
V
OL Output low voltage 1.07 V
V
OD Output differential voltage 0.35 V
V
CM Output common mode voltage 1.25 V
Z
BACK Back impedance 100.5 Ohms
I
DC DC output current 6.03 mA
158
158
Zo = 100
140 100
On-chip On-chip Off-chip Off-chip
VCCIO = 2.5
8mA
8mA
Note: All resistors are ±1%.
VCCIO = 2.5
+
-
Emulated
LVDS
Buffer 3-11
DC and Switching Characteristics
MachXO2 Family Data Sheet
BLVDS
The MachXO2 family supports the BLVDS standard through emulation. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is supported by
the LVDS differential input buffer. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Table 3-2. BLVDS DC Conditions1
Over Recommended Operating Conditions
Symbol Description
Nominal
Zo = 45 Zo = 90 Units
Z
OUT Output impedance 10 10 Ohms
RS
Driver series resistance 80 80 Ohms
RTLEFT Left end termination 45 90 Ohms
RTRIGHT Right end termination 45 90 Ohms
V
OH Output high voltage 1.376 1.480 V
V
OL Output low voltage 1.124 1.020 V
V
OD Output differential voltage 0.253 0.459 V
V
CM Output common mode voltage 1.250 1.250 V
I
DC DC output current 11.236 10.204 mA
1. For input buffer, see LVDS table.
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
80
80
80 80 80 80
45-90 ohms 45-90 ohms
80
2.5V
2.5V
2.5V 2.5V 2.5V 2.5V
2.5V
+
-
. . .
+
-
+
-
+
-
16mA
16mA 16mA 16mA 16mA
16mA
16mA 16mA3-12
DC and Switching Characteristics
MachXO2 Family Data Sheet
LVPECL
The MachXO2 family supports the differential LVPECL standard through emulation. This output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the
devices. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Differential LVPECL is one possible solution for point-to-point signals.
Figure 3-3. Differential LVPECL
Table 3-3. LVPECL DC Conditions1
Over Recommended Operating Conditions
For further information on LVPECL, BLVDS and other differential interfaces please see details of additional technical documentation at the end of the data sheet.
Symbol Description Nominal Units
Z
OUT Output impedance 10 Ohms
RS
Driver series resistor 93 Ohms
RP
Driver parallel resistor 196 Ohms
RT
Receiver termination 100 Ohms
V
OH Output high voltage 2.05 V
V
OL Output low voltage 1.25 V
V
OD Output differential voltage 0.80 V
V
CM Output common mode voltage 1.65 V
Z
BACK Back impedance 100.5 Ohms
I
DC DC output current 12.11 mA
1. For input buffer, see LVDS table.
Transmission line, Zo = 100 ohm differential
100 ohms
93 ohms
16mA
16mA
93 ohms
On-chip Off-chip
V
CCIO = 3.3V
V
CCIO = 3.3V +
-
196 ohms
Off-chip On-chip 3-13
DC and Switching Characteristics
MachXO2 Family Data Sheet
RSDS
The MachXO2 family supports the differential RSDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The RSDS input
standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.
Figure 3-4. RSDS (Reduced Swing Differential Standard)
Table 3-4. RSDS DC Conditions
Parameter Description Typical Units
Z
OUT Output impedance 20 Ohms
RS
Driver series resistor 294 Ohms
RP
Driver parallel resistor 121 Ohms
RT
Receiver termination 100 Ohms
V
OH Output high voltage 1.35 V
V
OL Output low voltage 1.15 V
V
OD Output differential voltage 0.20 V
V
CM Output common mode voltage 1.25 V
Z
BACK Back impedance 101.5 Ohms
I
DC DC output current 3.66 mA
100
294
294
On-chip Off-chip On-chip
Emulated
RSDS Buffer
VCCIO = 2.5V
VCCIO = 2.5V
8mA
8mA
Zo = 100
+
-
121
Off-chip3-14
DC and Switching Characteristics
MachXO2 Family Data Sheet
Typical Building Block Function Performance – HC/HE Devices1
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Register-to-Register Performance
Function -6 Timing Units
Basic Functions
16-bit decoder 8.9 ns
4:1 MUX 7.5 ns
16:1 MUX 8.3 ns
Function -6 Timing Units
Basic Functions
16:1 MUX 412 MHz
16-bit adder 297 MHz
16-bit counter 324 MHz
64-bit counter 161 MHz
Embedded Memory Functions
1024x9 True-Dual Port RAM
(Write Through or Normal, EBR output registers) 183 MHz
Distributed Memory Functions
16x4 Pseudo-Dual Port RAM (one PFU) 500 MHz
1. The above timing numbers are generated using the Diamond design tool. Exact performance may vary
with device and tool version. The tool uses internal parameters that have been characterized but are not
tested on every device.3-15
DC and Switching Characteristics
MachXO2 Family Data Sheet
Typical Building Block Function Performance – ZE Devices1
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Register-to-Register Performance
Derating Logic Timing
Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage.
Function -3 Timing Units
Basic Functions
16-bit decoder 13.9 ns
4:1 MUX 10.9 ns
16:1 MUX 12.0 ns
Function -3 Timing Units
Basic Functions
16:1 MUX 191 MHz
16-bit adder 134 MHz
16-bit counter 148 MHz
64-bit counter 77 MHz
Embedded Memory Functions
1024x9 True-Dual Port RAM
(Write Through or Normal, EBR output registers) 90 MHz
Distributed Memory Functions
16x4 Pseudo-Dual Port RAM (one PFU) 214 MHz
1. The above timing numbers are generated using the Diamond design tool. Exact performance may vary
with device and tool version. The tool uses internal parameters that have been characterized but are not
tested on every device.3-16
DC and Switching Characteristics
MachXO2 Family Data Sheet
Maximum sysIO Buffer Performance
I/O Standard Max. Speed Units
LVDS25 400 MHz
LVDS25E 150 MHz
RSDS25 150 MHz
RSDS25E 150 MHz
BLVDS25 150 MHz
BLVDS25E 150 MHz
MLVDS25 150 MHz
MLVDS25E 150 MHz
LVPECL33 150 MHz
LVPECL33E 150 MHz
SSTL25_I 150 MHz
SSTL25_II 150 MHz
SSTL25D_I 150 MHz
SSTL25D_II 150 MHz
SSTL18_I 150 MHz
SSTL18_II 150 MHz
SSTL18D_I 150 MHz
SSTL18D_II 150 MHz
HSTL18_I 150 MHz
HSTL18_II 150 MHz
HSTL18D_I 150 MHz
HSTL18D_II 150 MHz
PCI33 134 MHz
LVTTL33 150 MHz
LVTTL33D 150 MHz
LVCMOS33 150 MHz
LVCMOS33D 150 MHz
LVCMOS25 150 MHz
LVCMOS25D 150 MHz
LVCMOS25R33 150 MHz
LVCMOS18 150 MHz
LVCMOS18D 150 MHz
LVCMOS18R33 150 MHz
LVCMOS18R25 150 MHz
LVCMOS15 150 MHz
LVCMOS15D 150 MHz
LVCMOS15R33 150 MHz
LVCMOS15R25 150 MHz
LVCMOS12 91 MHz
LVCMOS12D 91 MHz3-17
DC and Switching Characteristics
MachXO2 Family Data Sheet
MachXO2 External Switching Characteristics – HC/HE Devices1, 2, 3, 4, 5, 6, 7
Over Recommended Operating Conditions
Parameter Description Device
-6 -5 -4
Min. Max. Min. Max. Min. Max. Units
Clocks
Primary Clocks
f
MAX_PRI
8
Frequency for Primary Clock
Tree All MachXO2 devices — 388 — 323 — 269 MHz
t
W_PRI
Clock Pulse Width for Primary
Clock All MachXO2 devices 0.5 — 0.6 — 0.7 — ns
t
SKEW_PRI
Primary Clock Skew Within a
Device
MachXO2-256HC-HE — 912 — 939 — 975 ps
MachXO2-640HC-HE — 844 — 871 — 908 ps
MachXO2-1200HC-HE — 868 — 902 — 951 ps
MachXO2-2000HC-HE — 867 — 897 — 941 ps
MachXO2-4000HC-HE — 865 — 892 — 931 ps
MachXO2-7000HC-HE — 902 — 942 — 989 ps
Edge Clock
f
MAX_EDGE
8
Frequency for Edge Clock MachXO2-1200 and
larger devices — 400 — 333 — 278 MHz
Pin-LUT-Pin Propagation Delay
t
PD
Best case propagation delay
through one LUT-4 All MachXO2 devices — 6.72 — 6.96 — 7.24 ns
General I/O Pin Parameters (Using Primary Clock without PLL)
t
CO
Clock to Output - PIO Output
Register
MachXO2-256HC-HE — 7.13 — 7.30 — 7.57 ns
MachXO2-640HC-HE — 7.15 — 7.30 — 7.57 ns
MachXO2-1200HC-HE — 7.44 — 7.64 — 7.94 ns
MachXO2-2000HC-HE — 7.46 — 7.66 — 7.96 ns
MachXO2-4000HC-HE — 7.51 — 7.71 — 8.01 ns
MachXO2-7000HC-HE — 7.54 — 7.75 — 8.06 ns
t
SU
Clock to Data Setup - PIO
Input Register
MachXO2-256HC-HE -0.06 — -0.06 — -0.06 — ns
MachXO2-640HC-HE -0.06 — -0.06 — -0.06 — ns
MachXO2-1200HC-HE -0.17 — -0.17 — -0.17 — ns
MachXO2-2000HC-HE -0.20 — -0.20 — -0.20 — ns
MachXO2-4000HC-HE -0.23 — -0.23 — -0.23 — ns
MachXO2-7000HC-HE -0.23 — -0.23 — -0.23 — ns
t
H
Clock to Data Hold - PIO Input
Register
MachXO2-256HC-HE 1.75 — 1.95 — 2.16 — ns
MachXO2-640HC-HE 1.75 — 1.95 — 2.16 — ns
MachXO2-1200HC-HE 1.88 — 2.12 — 2.36 — ns
MachXO2-2000HC-HE 1.89 — 2.13 — 2.37 — ns
MachXO2-4000HC-HE 1.94 — 2.18 — 2.43 — ns
MachXO2-7000HC-HE 1.98 — 2.23 — 2.49 — ns3-18
DC and Switching Characteristics
MachXO2 Family Data Sheet
t
SU_DEL
Clock to Data Setup - PIO
Input Register with Data Input
Delay
MachXO2-256HC-HE 1.42 — 1.59 — 1.96 — ns
MachXO2-640HC-HE 1.41 — 1.58 — 1.96 — ns
MachXO2-1200HC-HE 1.63 — 1.79 — 2.17 — ns
MachXO2-2000HC-HE 1.61 — 1.76 — 2.13 — ns
MachXO2-4000HC-HE 1.66 — 1.81 — 2.19 — ns
MachXO2-7000HC-HE 1.53 — 1.67 — 2.03 — ns
t
H_DEL
Clock to Data Hold - PIO Input
Register with Input Data Delay
MachXO2-256HC-HE -0.24 — -0.24 — -0.24 — ns
MachXO2-640HC-HE -0.23 — -0.23 — -0.23 — ns
MachXO2-1200HC-HE -0.24 — -0.24 — -0.24 — ns
MachXO2-2000HC-HE -0.23 — -0.23 — -0.23 — ns
MachXO2-4000HC-HE -0.25 — -0.25 — -0.25 — ns
MachXO2-7000HC-HE -0.21 — -0.21 — -0.21 — ns
f
MAX_IO
Clock Frequency of I/O and
PFU Register All MachXO2 devices — 388 — 323 — 269 MHz
General I/O Pin Parameters (Using Edge Clock without PLL)
t
COE
Clock to Output - PIO Output
Register
MachXO2-1200HC-HE — 7.53 — 7.76 — 8.10 ns
MachXO2-2000HC-HE — 7.53 — 7.76 — 8.10 ns
MachXO2-4000HC-HE — 7.45 — 7.68 — 8.00 ns
MachXO2-7000HC-HE — 7.53 — 7.76 — 8.10 ns
t
SUE
Clock to Data Setup - PIO
Input Register
MachXO2-1200HC-HE -0.19 — -0.19 — -0.19 — ns
MachXO2-2000HC-HE -0.19 — -0.19 — -0.19 — ns
MachXO2-4000HC-HE -0.16 — -0.16 — -0.16 — ns
MachXO2-7000HC-HE -0.19 — -0.19 — -0.19 — ns
t
HE
Clock to Data Hold - PIO Input
Register
MachXO2-1200HC-HE 1.97 — 2.24 — 2.52 — ns
MachXO2-2000HC-HE 1.97 — 2.24 — 2.52 — ns
MachXO2-4000HC-HE 1.89 — 2.16 — 2.43 — ns
MachXO2-7000HC-HE 1.97 — 2.24 — 2.52 — ns
t
SU_DELE
Clock to Data Setup - PIO
Input Register with Data Input
Delay
MachXO2-1200HC-HE 1.56 — 1.69 — 2.05 — ns
MachXO2-2000HC-HE 1.56 — 1.69 — 2.05 — ns
MachXO2-4000HC-HE 1.74 — 1.88 — 2.25 — ns
MachXO2-7000HC-HE 1.66 — 1.81 — 2.17 — ns
t
H_DELE
Clock to Data Hold - PIO Input
Register with Input Data Delay
MachXO2-1200HC-HE -0.23 — -0.23 — -0.23 — ns
MachXO2-2000HC-HE -0.23 — -0.23 — -0.23 — ns
MachXO2-4000HC-HE -0.34 — -0.34 — -0.34 — ns
MachXO2-7000HC-HE -0.29 — -0.29 — -0.29 — ns
General I/O Pin Parameters (Using Primary Clock with PLL)
t
COPLL
Clock to Output - PIO Output
Register
MachXO2-1200HC-HE — 5.97 — 6.00 — 6.13 ns
MachXO2-2000HC-HE — 5.98 — 6.01 — 6.14 ns
MachXO2-4000HC-HE — 5.99 — 6.02 — 6.16 ns
MachXO2-7000HC-HE — 6.02 — 6.06 — 6.20 ns
t
SUPLL
Clock to Data Setup - PIO
Input Register
MachXO2-1200HC-HE 0.36 — 0.36 — 0.65 — ns
MachXO2-2000HC-HE 0.36 — 0.36 — 0.63 — ns
MachXO2-4000HC-HE 0.35 — 0.35 — 0.62 — ns
MachXO2-7000HC-HE 0.34 — 0.34 — 0.59 — ns
Parameter Description Device
-6 -5 -4
Min. Max. Min. Max. Min. Max. Units3-19
DC and Switching Characteristics
MachXO2 Family Data Sheet
t
HPLL
Clock to Data Hold - PIO Input
Register
MachXO2-1200HC-HE 0.41 — 0.48 — 0.55 — ns
MachXO2-2000HC-HE 0.42 — 0.49 — 0.56 — ns
MachXO2-4000HC-HE 0.43 — 0.50 — 0.58 — ns
MachXO2-7000HC-HE 0.46 — 0.54 — 0.62 — ns
t
SU_DELPLL
Clock to Data Setup - PIO
Input Register with Data Input
Delay
MachXO2-1200HC-HE 2.88 — 3.19 — 3.72 — ns
MachXO2-2000HC-HE 2.87 — 3.18 — 3.70 — ns
MachXO2-4000HC-HE 2.96 — 3.28 — 3.81 — ns
MachXO2-7000HC-HE 3.05 — 3.35 — 3.87 — ns
t
H_DELPLL
Clock to Data Hold - PIO Input
Register with Input Data Delay
MachXO2-1200HC-HE -0.83 — -0.83 — -0.83 — ns
MachXO2-2000HC-HE -0.83 — -0.83 — -0.83 — ns
MachXO2-4000HC-HE -0.87 — -0.87 — -0.87 — ns
MachXO2-7000HC-HE -0.91 — -0.91 — -0.91 — ns
Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned9
t
DVA Input Data Valid After CLK
All MachXO2 devices,
all sides
— 0.317 — 0.344 — 0.368 UI
t
DVE Input Data Hold After CLK 0.742 — 0.702 — 0.668 — UI
f
DATA DDRX1 Input Data Speed — 300 — 250 — 208 Mbps
f
DDRX1 DDRX1 SCLK Frequency — 150 — 125 — 104 MHz
Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered9
t
SU Input Data Setup Before CLK
All MachXO2 devices,
all sides
0.566 — 0.560 — 0.538 — ns
t
HO Input Data Hold After CLK 0.778 — 0.879 — 1.090 — ns
f
DATA DDRX1 Input Data Speed — 300 — 250 — 208 Mbps
f
DDRX1 DDRX1 SCLK Frequency — 150 — 125 — 104 MHz
Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned9
t
DVA Input Data Valid After CLK
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
— 0.316 — 0.342 — 0.364 UI
t
DVE Input Data Hold After CLK 0.710 — 0.675 — 0.679 — UI
f
DATA
DDRX2 Serial Input Data
Speed — 664 — 554 — 462 Mbps
f
DDRX2 DDRX2 ECLK Frequency — 332 — 277 — 231 MHz
f
SCLK SCLK Frequency — 166 — 139 — 116 MHz
Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered9
t
SU Input Data Setup Before CLK
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
0.233 — 0.219 — 0.198 — ns
t
HO Input Data Hold After CLK 0.287 — 0.287 — 0.344 — ns
f
DATA
DDRX2 Serial Input Data
Speed — 664 — 554 — 462 Mbps
f
DDRX2 DDRX2 ECLK Frequency — 332 — 277 — 231 MHz
f
SCLK SCLK Frequency — 166 — 139 — 116 MHz
Parameter Description Device
-6 -5 -4
Min. Max. Min. Max. Min. Max. Units3-20
DC and Switching Characteristics
MachXO2 Family Data Sheet
Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned9
t
DVA Input Data Valid After ECLK
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
— 0.290 — 0.320 — 0.345 UI
t
DVE Input Data Hold After ECLK 0.739 — 0.699 — 0.703 — UI
f
DATA
DDRX4 Serial Input Data
Speed — 756 — 630 — 524 Mbps
f
DDRX4 DDRX4 ECLK Frequency — 378 — 315 — 262 MHz
f
SCLK SCLK Frequency — 95 — 79 — 66 MHz
Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered9
t
SU Input Data Setup Before ECLK
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
0.233 — 0.219 — 0.198 — ns
t
HO Input Data Hold After ECLK 0.287 — 0.287 — 0.344 — ns
f
DATA
DDRX4 Serial Input Data
Speed — 756 — 630 — 524 Mbps
f
DDRX4 DDRX4 ECLK Frequency — 378 — 315 — 262 MHz
f
SCLK SCLK Frequency — 95 — 79 — 66 MHz
7:1 LVDS Inputs (GDDR71_RX.ECLK.7:1)9
t
DVA Input Data Valid After ECLK
MachXO2-640U,
MachXO2-1200/U and
larger devices, bottom
side only
— 0.290 — 0.320 — 0.345 UI
t
DVE Input Data Hold After ECLK 0.739 — 0.699 — 0.703 — UI
f
DATA
DDR71 Serial Input Data
Speed — 756 — 630 — 524 Mbps
f
DDR71 DDR71 ECLK Frequency — 378 — 315 — 262 MHz
f
CLKIN
7:1 Input Clock Frequency
(SCLK) (minimum limited by
PLL)
— 108 — 90 — 75 MHz
Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned9
t
DIA
Output Data Invalid After CLK
Output
All MachXO2 devices,
all sides
— 0.520 — 0.550 — 0.580 ns
t
DIB
Output Data Invalid Before
CLK Output — 0.520 — 0.550 — 0.580 ns
f
DATA DDRX1 Output Data Speed — 300 — 250 — 208 Mbps
f
DDRX1 DDRX1 SCLK frequency — 150 — 125 — 104 MHz
Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered9
t
DVB
Output Data Valid Before CLK
Output
All MachXO2 devices,
all sides
1.210 — 1.510 — 1.870 — ns
t
DVA
Output Data Valid After CLK
Output 1.210 — 1.510 — 1.870 — ns
f
DATA DDRX1 Output Data Speed — 300 — 250 — 208 Mbps
f
DDRX1
DDRX1 SCLK Frequency
(minimum limited by PLL) — 150 — 125 — 104 MHz
Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned9
t
DIA
Output Data Invalid After CLK
Output
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only
— 0.200 — 0.215 — 0.230 ns
t
DIB
Output Data Invalid Before
CLK Output — 0.200 — 0.215 — 0.230 ns
f
DATA
DDRX2 Serial Output Data
Speed — 664 — 554 — 462 Mbps
f
DDRX2 DDRX2 ECLK frequency — 332 — 277 — 231 MHz
f
SCLK SCLK Frequency — 166 — 139 — 116 MHz
Parameter Description Device
-6 -5 -4
Min. Max. Min. Max. Min. Max. Units3-21
DC and Switching Characteristics
MachXO2 Family Data Sheet
Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered9
t
DVB
Output Data Valid Before CLK
Output
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only
0.535 — 0.670 — 0.830 — ns
t
DVA
Output Data Valid After CLK
Output 0.535 — 0.670 — 0.830 — ns
f
DATA
DDRX2 Serial Output Data
Speed — 664 — 554 — 462 Mbps
f
DDRX2
DDRX2 ECLK Frequency
(minimum limited by PLL) — 332 — 277 — 231 MHz
f
SCLK SCLK Frequency — 166 — 139 — 116 MHz
Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned9
t
DIA
Output Data Invalid After CLK
Output
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only
— 0.200 — 0.215 — 0.230 ns
t
DIB
Output Data Invalid Before
CLK Output — 0.200 — 0.215 — 0.230 ns
f
DATA
DDRX4 Serial Output Data
Speed — 756 — 630 — 524 Mbps
f
DDRX4 DDRX4 ECLK Frequency — 378 — 315 — 262 MHz
f
SCLK SCLK Frequency — 95 — 79 — 66 MHz
Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered9
t
DVB
Output Data Valid Before CLK
Output
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only
0.455 — 0.570 — 0.710 — ns
t
DVA
Output Data Valid After CLK
Output 0.455 — 0.570 — 0.710 — ns
f
DATA
DDRX4 Serial Output Data
Speed — 756 — 630 — 524 Mbps
f
DDRX4
DDRX4 ECLK Frequency
(minimum limited by PLL) — 378 — 315 — 262 MHz
f
SCLK SCLK Frequency — 95 — 79 — 66 MHz
7:1 LVDS Outputs – GDDR71_TX.ECLK.7:19
t
DVB
Output Data Valid Before CLK
Output
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only.
— 0.160 — 0.180 — 0.200 ns
t
DVA
Output Data Valid After CLK
Output — 0.160 — 0.180 — 0.200 ns
f
DATA
DDR71 Serial Output Data
Speed — 756 — 630 — 524 Mbps
f
DDR71 DDR71 ECLK Frequency — 378 — 315 — 262 MHz
f
CLKOUT
7:1 Output Clock Frequency
(SCLK) (minimum limited by
PLL)
— 108 — 90 — 75 MHz
Parameter Description Device
-6 -5 -4
Min. Max. Min. Max. Min. Max. Units3-22
DC and Switching Characteristics
MachXO2 Family Data Sheet
LPDDR9
t
DVADQ
Input Data Valid After DQS
Input
MachXO2-1200/U and
larger devices, right
side only.
— 0.369 — 0.395 — 0.421 UI
t
DVEDQ
Input Data Hold After DQS
Input 0.529 — 0.530 — 0.527 — UI
t
DQVBS
Output Data Invalid Before
DQS Output 0.25 — 0.25 — 0.25 — UI
t
DQVAS
Output Data Invalid After DQS
Output 0.25 — 0.25 — 0.25 — UI
f
DATA
MEM LPDDR Serial Data
Speed — 280 — 250 — 208 Mbps
f
SCLK SCLK Frequency — 140 — 125 — 104 MHz
f
LPDDR LPDDR Data Transfer Rate 0 280 0 250 0 208 Mbps
DDR9
t
DVADQ
Input Data Valid After DQS
Input
MachXO2-1200/U and
larger devices, right
side only.
— 0.350 — 0.387 — 0.414 UI
t
DVEDQ
Input Data Hold After DQS
Input 0.545 — 0.538 — 0.532 — UI
t
DQVBS
Output Data Invalid Before
DQS Output 0.25 — 0.25 — 0.25 — UI
t
DQVAS
Output Data Invalid After DQS
Output 0.25 — 0.25 — 0.25 — UI
f
DATA MEM DDR Serial Data Speed — 300 — 250 — 208 Mbps
f
SCLK SCLK Frequency — 150 — 125 — 104 MHz
f
MEM_DDR MEM DDR Data Transfer Rate N/A 300 N/A 250 N/A 208 Mbps
DDR29
t
DVADQ
Input Data Valid After DQS
Input
MachXO2-1200/U and
larger devices, right
side only.
— 0.360 — 0.378 — 0.406 UI
t
DVEDQ
Input Data Hold After DQS
Input 0.555 — 0.549 — 0.542 — UI
t
DQVBS
Output Data Invalid Before
DQS Output 0.25 — 0.25 — 0.25 — UI
t
DQVAS
Output Data Invalid After DQS
Output 0.25 — 0.25 — 0.25 — UI
f
DATA MEM DDR Serial Data Speed — 300 — 250 — 208 Mbps
f
SCLK SCLK Frequency — 150 — 125 — 104 MHz
f
MEM_DDR2
MEM DDR2 Data Transfer
Rate N/A 300 N/A 250 N/A 208 Mbps
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other
operating conditions, including industrial, can be extracted from the Diamond software.
2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.
3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.
5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).
6. For Generic DDRX1 mode tSU = tHO = (tDVE - tDVA - 0.03ns)/2.
7. The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 105ps (-6), 113ps (-5), 120ps (-4).
8. This number for general purpose usage. Duty cycle tolerance is +/-10%.
9. Duty cycle is +/- 5% for system usage.
10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.
Parameter Description Device
-6 -5 -4
Min. Max. Min. Max. Min. Max. Units3-23
DC and Switching Characteristics
MachXO2 Family Data Sheet
MachXO2 External Switching Characteristics – ZE Devices1, 2, 3, 4, 5, 6, 7
Over Recommended Operating Conditions
Parameter Description Device
-3 -2 -1
Min. Max. Min. Max. Min. Max. Units
Clocks
Primary Clocks
f
MAX_PRI
8
Frequency for Primary Clock
Tree All MachXO2 devices — 150 — 125 — 104 MHz
t
W_PRI
Clock Pulse Width for Primary
Clock All MachXO2 devices 1.00 — 1.20 — 1.40 — ns
t
SKEW_PRI
Primary Clock Skew Within a
Device
MachXO2-256ZE — 1250 — 1272 — 1296 ps
MachXO2-640ZE — 1161 — 1183 — 1206 ps
MachXO2-1200ZE — 1213 — 1267 — 1322 ps
MachXO2-2000ZE — 1204 — 1250 — 1296 ps
MachXO2-4000ZE — 1195 — 1233 — 1269 ps
MachXO2-7000ZE — 1243 — 1268 — 1296 ps
Edge Clock
f
MAX_EDGE
8
Frequency for Edge Clock MachXO2-1200 and
larger devices — 210 — 175 — 146 MHz
Pin-LUT-Pin Propagation Delay
t
PD
Best case propagation delay
through one LUT-4 All MachXO2 devices — 9.35 — 9.78 — 10.21 ns
General I/O Pin Parameters (Using Primary Clock without PLL)
t
CO
Clock to Output - PIO Output
Register
MachXO2-256ZE — 10.46 — 10.86 — 11.25 ns
MachXO2-640ZE — 10.52 — 10.92 — 11.32 ns
MachXO2-1200ZE — 11.24 — 11.68 — 12.12 ns
MachXO2-2000ZE — 11.27 — 11.71 — 12.16 ns
MachXO2-4000ZE — 11.28 — 11.78 — 12.28 ns
MachXO2-7000ZE — 11.22 — 11.76 — 12.30 ns
t
SU
Clock to Data Setup - PIO
Input Register
MachXO2-256ZE -0.21 — -0.21 — -0.21 — ns
MachXO2-640ZE -0.22 — -0.22 — -0.22 — ns
MachXO2-1200ZE -0.25 — -0.25 — -0.25 — ns
MachXO2-2000ZE -0.27 — -0.27 — -0.27 — ns
MachXO2-4000ZE -0.31 — -0.31 — -0.31 — ns
MachXO2-7000ZE -0.33 — -0.33 — -0.33 — ns
t
H
Clock to Data Hold - PIO Input
Register
MachXO2-256ZE 3.96 — 4.25 — 4.65 — ns
MachXO2-640ZE 4.01 — 4.31 — 4.71 — ns
MachXO2-1200ZE 3.95 — 4.29 — 4.73 — ns
MachXO2-2000ZE 3.94 — 4.29 — 4.74 — ns
MachXO2-4000ZE 3.96 — 4.36 — 4.87 — ns
MachXO2-7000ZE 3.93 — 4.37 — 4.91 — ns3-24
DC and Switching Characteristics
MachXO2 Family Data Sheet
t
SU_DEL
Clock to Data Setup - PIO
Input Register with Data Input
Delay
MachXO2-256ZE 2.62 — 2.91 — 3.14 — ns
MachXO2-640ZE 2.56 — 2.85 — 3.08 — ns
MachXO2-1200ZE 2.30 — 2.57 — 2.79 — ns
MachXO2-2000ZE 2.25 — 2.50 — 2.70 — ns
MachXO2-4000ZE 2.39 — 2.60 — 2.76 — ns
MachXO2-7000ZE 2.17 — 2.33 — 2.43 — ns
t
H_DEL
Clock to Data Hold - PIO Input
Register with Input Data Delay
MachXO2-256ZE -0.44 — -0.44 — -0.44 — ns
MachXO2-640ZE -0.43 — -0.43 — -0.43 — ns
MachXO2-1200ZE -0.28 — -0.28 — -0.28 — ns
MachXO2-2000ZE -0.31 — -0.31 — -0.31 — ns
MachXO2-4000ZE -0.34 — -0.34 — -0.34 — ns
MachXO2-7000ZE -0.21 — -0.21 — -0.21 — ns
f
MAX_IO
Clock Frequency of I/O and
PFU Register All MachXO2 devices — 150 — 125 — 104 MHz
General I/O Pin Parameters (Using Edge Clock without PLL)
t
COE
Clock to Output - PIO Output
Register
MachXO2-1200ZE — 11.10 — 11.51 — 11.91 ns
MachXO2-2000ZE — 11.10 — 11.51 — 11.91 ns
MachXO2-4000ZE — 10.89 — 11.28 — 11.67 ns
MachXO2-7000ZE — 11.10 — 11.51 — 11.91 ns
t
SUE
Clock to Data Setup - PIO
Input Register
MachXO2-1200ZE -0.23 — -0.23 — -0.23 — ns
MachXO2-2000ZE -0.23 — -0.23 — -0.23 — ns
MachXO2-4000ZE -0.15 — -0.15 — -0.15 — ns
MachXO2-7000ZE -0.23 — -0.23 — -0.23 — ns
t
HE
Clock to Data Hold - PIO Input
Register
MachXO2-1200ZE 3.81 — 4.11 — 4.52 — ns
MachXO2-2000ZE 3.81 — 4.11 — 4.52 — ns
MachXO2-4000ZE 3.60 — 3.89 — 4.28 — ns
MachXO2-7000ZE 3.81 — 4.11 — 4.52 — ns
t
SU_DELE
Clock to Data Setup - PIO
Input Register with Data Input
Delay
MachXO2-1200ZE 2.78 — 3.11 — 3.40 — ns
MachXO2-2000ZE 2.78 — 3.11 — 3.40 — ns
MachXO2-4000ZE 3.11 — 3.48 — 3.79 — ns
MachXO2-7000ZE 2.94 — 3.30 — 3.60 — ns
t
H_DELE
Clock to Data Hold - PIO Input
Register with Input Data Delay
MachXO2-1200ZE -0.29 — -0.29 — -0.29 — ns
MachXO2-2000ZE -0.29 — -0.29 — -0.29 — ns
MachXO2-4000ZE -0.46 — -0.46 — -0.46 — ns
MachXO2-7000ZE -0.37 — -0.37 — -0.37 — ns
General I/O Pin Parameters (Using Primary Clock with PLL)
t
COPLL
Clock to Output - PIO Output
Register
MachXO2-1200ZE — 7.95 — 8.07 — 8.19 ns
MachXO2-2000ZE — 7.97 — 8.10 — 8.22 ns
MachXO2-4000ZE — 7.98 — 8.10 — 8.23 ns
MachXO2-7000ZE — 8.02 — 8.14 — 8.26 ns
t
SUPLL
Clock to Data Setup - PIO
Input Register
MachXO2-1200ZE 0.85 — 0.85 — 0.89 — ns
MachXO2-2000ZE 0.84 — 0.84 — 0.86 — ns
MachXO2-4000ZE 0.84 — 0.84 — 0.85 — ns
MachXO2-7000ZE 0.83 — 0.83 — 0.81 — ns
Parameter Description Device
-3 -2 -1
Min. Max. Min. Max. Min. Max. Units3-25
DC and Switching Characteristics
MachXO2 Family Data Sheet
t
HPLL
Clock to Data Hold - PIO Input
Register
MachXO2-1200ZE 0.66 — 0.68 — 0.80 — ns
MachXO2-2000ZE 0.68 — 0.70 — 0.83 — ns
MachXO2-4000ZE 0.68 — 0.71 — 0.84 — ns
MachXO2-7000ZE 0.73 — 0.74 — 0.87 — ns
t
SU_DELPLL
Clock to Data Setup - PIO
Input Register with Data Input
Delay
MachXO2-1200ZE 5.14 — 5.69 — 6.20 — ns
MachXO2-2000ZE 5.11 — 5.67 — 6.17 — ns
MachXO2-4000ZE 5.27 — 5.84 — 6.35 — ns
MachXO2-7000ZE 5.15 — 5.71 — 6.23 — ns
t
H_DELPLL
Clock to Data Hold - PIO Input
Register with Input Data Delay
MachXO2-1200ZE -1.36 — -1.36 — -1.36 — ns
MachXO2-2000ZE -1.35 — -1.35 — -1.35 — ns
MachXO2-4000ZE -1.43 — -1.43 — -1.43 — ns
MachXO2-7000ZE -1.41 — -1.41 — -1.41 — ns
Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned9
t
DVA Input Data Valid After CLK
All MachXO2
devices, all sides
— 0.382 — 0.401 — 0.417 UI
t
DVE Input Data Hold After CLK 0.670 — 0.684 — 0.693 — UI
f
DATA DDRX1 Input Data Speed — 140 — 116 — 98 Mbps
f
DDRX1 DDRX1 SCLK Frequency — 70 — 58 — 49 MHz
Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered9
t
SU Input Data Setup Before CLK
All MachXO2
devices, all sides
1.319 — 1.412 — 1.462 — ns
t
HO Input Data Hold After CLK 0.717 — 1.010 — 1.340 — ns
f
DATA DDRX1 Input Data Speed — 140 — 116 — 98 Mbps
f
DDRX1 DDRX1 SCLK Frequency — 70 — 58 — 49 MHz
Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned9
t
DVA Input Data Valid After CLK
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
— 0.361 — 0.346 — 0.334 UI
t
DVE Input Data Hold After CLK 0.602 — 0.625 — 0.648 — UI
f
DATA
DDRX2 Serial Input Data
Speed — 280 — 234 — 194 Mbps
f
DDRX2 DDRX2 ECLK Frequency — 140 — 117 — 97 MHz
f
SCLK SCLK Frequency — 70 — 59 — 49 MHz
Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered9
t
SU Input Data Setup Before CLK
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
0.472 — 0.672 — 0.865 — ns
t
HO Input Data Hold After CLK 0.363 — 0.501 — 0.743 — ns
f
DATA
DDRX2 Serial Input Data
Speed — 280 — 234 — 194 Mbps
f
DDRX2 DDRX2 ECLK Frequency — 140 — 117 — 97 MHz
f
SCLK SCLK Frequency — 70 — 59 — 49 MHz
Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Aligned9
t
DVA Input Data Valid After ECLK
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
— 0.307 — 0.316 — 0.326 UI
t
DVE Input Data Hold After ECLK 0.662 — 0.650 — 0.649 — UI
f
DATA
DDRX4 Serial Input Data
Speed — 420 — 352 — 292 Mbps
f
DDRX4 DDRX4 ECLK Frequency — 210 — 176 — 146 MHz
f
SCLK SCLK Frequency — 53 — 44 — 37 MHz
Parameter Description Device
-3 -2 -1
Min. Max. Min. Max. Min. Max. Units3-26
DC and Switching Characteristics
MachXO2 Family Data Sheet
Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered9
t
SU Input Data Setup Before ECLK
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
0.434 — 0.535 — 0.630 — ns
t
HO Input Data Hold After ECLK 0.385 — 0.395 — 0.463 — ns
f
DATA
DDRX4 Serial Input Data
Speed — 420 — 352 — 292 Mbps
f
DDRX4 DDRX4 ECLK Frequency — 210 — 176 — 146 MHz
f
SCLK SCLK Frequency — 53 — 44 — 37 MHz
7:1 LVDS Inputs – GDDR71_RX.ECLK.7.19
t
DVA Input Data Valid After ECLK
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
— 0.307 — 0.316 — 0.326 UI
t
DVE Input Data Hold After ECLK 0.662 — 0.650 — 0.649 — UI
f
DATA
DDR71 Serial Input Data
Speed — 420 — 352 — 292 Mbps
f
DDR71 DDR71 ECLK Frequency — 210 — 176 — 146 MHz
f
CLKIN
7:1 Input Clock Frequency
(SCLK) (minimum limited by
PLL)
— 60 — 50 — 42 MHz
Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned9
t
DIA
Output Data Invalid After CLK
Output
All MachXO2
devices, all sides
— 0.850 — 0.910 — 0.970 ns
t
DIB
Output Data Invalid Before
CLK Output — 0.850 — 0.910 — 0.970 ns
f
DATA DDRX1 Output Data Speed — 140 — 116 — 98 Mbps
f
DDRX1 DDRX1 SCLK frequency — 70 — 58 — 49 MHz
Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered9
t
DVB
Output Data Valid Before CLK
Output
All MachXO2
devices, all sides
2.720 — 3.380 — 4.140 — ns
t
DVA
Output Data Valid After CLK
Output 2.720 — 3.380 — 4.140 — ns
f
DATA DDRX1 Output Data Speed — 140 — 116 — 98 Mbps
f
DDRX1
DDRX1 SCLK Frequency
(minimum limited by PLL) — 70 — 58 — 49 MHz
Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned9
t
DIA
Output Data Invalid After CLK
Output
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
— 0.270 — 0.300 — 0.330 ns
t
DIB
Output Data Invalid Before
CLK Output — 0.270 — 0.300 — 0.330 ns
f
DATA
DDRX2 Serial Output Data
Speed — 280 — 234 — 194 Mbps
f
DDRX2 DDRX2 ECLK frequency — 140 — 117 — 97 MHz
f
SCLK SCLK Frequency — 70 — 59 — 49 MHz
Parameter Description Device
-3 -2 -1
Min. Max. Min. Max. Min. Max. Units3-27
DC and Switching Characteristics
MachXO2 Family Data Sheet
Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered9
t
DVB
Output Data Valid Before CLK
Output
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
1.445 — 1.760 — 2.140 — ns
t
DVA
Output Data Valid After CLK
Output 1.445 — 1.760 — 2.140 — ns
f
DATA
DDRX2 Serial Output Data
Speed — 280 — 234 — 194 Mbps
f
DDRX2
DDRX2 ECLK Frequency
(minimum limited by PLL) — 140 — 117 — 97 MHz
f
SCLK SCLK Frequency — 70 — 59 — 49 MHz
Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned9
t
DIA
Output Data Invalid After CLK
Output
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
— 0.270 — 0.300 — 0.330 ns
t
DIB
Output Data Invalid Before
CLK Output — 0.270 — 0.300 — 0.330 ns
f
DATA
DDRX4 Serial Output Data
Speed — 420 — 352 — 292 Mbps
f
DDRX4 DDRX4 ECLK Frequency — 210 — 176 — 146 MHz
f
SCLK SCLK Frequency — 53 — 44 — 37 MHz
Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered9
t
DVB
Output Data Valid Before CLK
Output
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
0.873 — 1.067 — 1.319 — ns
t
DVA
Output Data Valid After CLK
Output 0.873 — 1.067 — 1.319 — ns
f
DATA
DDRX4 Serial Output Data
Speed — 420 — 352 — 292 Mbps
f
DDRX4
DDRX4 ECLK Frequency
(minimum limited by PLL) — 210 — 176 — 146 MHz
f
SCLK SCLK Frequency — 53 — 44 — 37 MHz
7:1 LVDS Outputs – GDDR71_TX.ECLK.7:19
t
DVB
Output Data Valid Before CLK
Output
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only.
— 0.240 — 0.270 — 0.300 ns
t
DVA
Output Data Valid After CLK
Output — 0.240 — 0.270 — 0.300 ns
f
DATA
DDR71 Serial Output Data
Speed — 420 — 352 — 292 Mbps
f
DDR71 DDR71 ECLK Frequency — 210 — 176 — 146 MHz
f
CLKOUT
7:1 Output Clock Frequency
(SCLK) (minimum limited by
PLL)
— 60 — 50 — 42 MHz
Parameter Description Device
-3 -2 -1
Min. Max. Min. Max. Min. Max. Units3-28
DC and Switching Characteristics
MachXO2 Family Data Sheet
LPDDR9
t
DVADQ
Input Data Valid After DQS
Input
MachXO2-1200/U
and larger devices,
right side only.
— 0.349 — 0.381 — 0.396 UI
t
DVEDQ
Input Data Hold After DQS
Input 0.665 — 0.630 — 0.613 — UI
t
DQVBS
Output Data Invalid Before
DQS Output 0.25 — 0.25 — 0.25 — UI
t
DQVAS
Output Data Invalid After DQS
Output 0.25 — 0.25 — 0.25 — UI
f
DATA
MEM LPDDR Serial Data
Speed — 120 — 110 — 96 Mbps
f
SCLK SCLK Frequency — 60 — 55 — 48 MHz
f
LPDDR LPDDR Data Transfer Rate 0 120 0 110 0 96 Mbps
DDR9
t
DVADQ
Input Data Valid After DQS
Input
MachXO2-1200/U
and larger devices,
right side only.
— 0.347 — 0.374 — 0.393 UI
t
DVEDQ
Input Data Hold After DQS
Input 0.665 — 0.637 — 0.616 — UI
t
DQVBS
Output Data Invalid Before
DQS Output 0.25 — 0.25 — 0.25 — UI
t
DQVAS
Output Data Invalid After DQS
Output 0.25 — 0.25 — 0.25 — UI
f
DATA MEM DDR Serial Data Speed — 140 — 116 — 98 Mbps
f
SCLK SCLK Frequency — 70 — 58 — 49 MHz
f
MEM_DDR MEM DDR Data Transfer Rate N/A 140 N/A 116 N/A 98 Mbps
DDR29
t
DVADQ
Input Data Valid After DQS
Input
MachXO2-1200/U
and larger devices,
right side only.
— 0.372 — 0.394 — 0.410 UI
t
DVEDQ
Input Data Hold After DQS
Input 0.690 — 0.658 — 0.618 — UI
t
DQVBS
Output Data Invalid Before
DQS Output 0.25 — 0.25 — 0.25 — UI
t
DQVAS
Output Data Invalid After DQS
Output 0.25 — 0.25 — 0.25 — UI
f
DATA MEM DDR Serial Data Speed — 140 — 116 — 98 Mbps
f
SCLK SCLK Frequency — 70 — 58 — 49 MHz
f
MEM_DDR2
MEM DDR2 Data Transfer
Rate N/A 140 N/A 116 N/A 98 Mbps
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other
operating conditions, including industrial, can be extracted from the Diamond software.
2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.
3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.
5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).
6. For Generic DDRX1 mode tSU = tHO = (tDVE - tDVA - 0.03ns)/2.
7. The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 167ps (-3), 182ps (-2), 195ps (-1).
8. This number for general purpose usage. Duty cycle tolerance is +/-10%.
9. Duty cycle is +/- 5% for system usage.
10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.
Parameter Description Device
-3 -2 -1
Min. Max. Min. Max. Min. Max. Units3-29
DC and Switching Characteristics
MachXO2 Family Data Sheet
Figure 3-5. Receiver RX.CLK.Aligned and MEM DDR Input Waveforms
Figure 3-6. Receiver RX.CLK.Centered Waveforms
Figure 3-7. Transmitter TX.CLK.Aligned Waveforms
Figure 3-8. Transmitter TX.CLK.Centered and MEM DDR Output Waveforms
t
DVA or tDVADQ
t
DVE or tDVEDQ
RX.Aligned
RX CLK Input
or DQS Input
RX Data Input
or DQ Input
t
SU t
HO t
SU t
HO
RX.Centered
RX CLK Input
RX Data Input
TX CLK Output
t
DIA
TX Data Output
t
DIB
TX.Aligned
t
DIB t
DIA
TX CLK Output
or DQS Output
t
DVA or
t
DQVAS
TX Data Output
or DQ Output
t
DVB or
t
DQVBS
TX.Centered
t
DVA or
t
DQVAS
t
DVB or
t
DQVBS3-30
DC and Switching Characteristics
MachXO2 Family Data Sheet
Figure 3-9. GDDR71 Video Timing Waveforms
Figure 3-10. Receiver GDDR71_RX. Waveforms
Figure 3-11. Transmitter GDDR71_TX. Waveforms
756 Mbps
Data Out
756 Mbps
Clock Out
125 MHz
Clock In
125 MHz
t
DVA
t
DVE
0 123456 0
t
DIA
t
DIB
0 123456 03-31
DC and Switching Characteristics
MachXO2 Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter Descriptions Conditions Min. Max. Units
f
IN Input Clock Frequency (CLKI, CLKFB) 7 400 MHz
f
OUT
Output Clock Frequency (CLKOP, CLKOS,
CLKOS2) 1.5625 400 MHz
f
OUT2
Output Frequency (CLKOS3 cascaded from
CLKOS2) 0.0122 400 MHz
f
VCO PLL VCO Frequency 200 800 MHz
f
PFD Phase Detector Input Frequency 7 400 MHz
AC Characteristics
t
DT Output Clock Duty Cycle Without duty trim selected3
45 55 %
t
DT_TRIM
7
Edge Duty Trim Accuracy -75 75 %
t
PH
4
Output Phase Accuracy -6 6 %
t
OPJIT
1, 8
Output Clock Period Jitter
f
OUT > 100MHz — 150 ps p-p
f
OUT < 100MHz — 0.007 UIPP
Output Clock Cycle-to-cycle Jitter
f
OUT > 100MHz — 180 ps p-p
f
OUT < 100MHz — 0.009 UIPP
Output Clock Phase Jitter
f
PFD > 100MHz — 160 ps p-p
f
PFD < 100MHz — 0.011 UIPP
Output Clock Period Jitter (Fractional-N)
f
OUT > 100MHz — 230 ps p-p
f
OUT < 100MHz — 0.12 UIPP
Output Clock Cycle-to-cycle Jitter
(Fractional-N)
f
OUT > 100MHz — 230 ps p-p
f
OUT < 100MHz — 0.12 UIPP
t
SPO Static Phase Offset Divider ratio = integer -120 120 ps
t
W Output Clock Pulse Width At 90% or 10%3
0.9 — ns
t
LOCK
2, 5 PLL Lock-in Time — 15 ms
t
UNLOCK PLL Unlock Time — 50 ns
t
IPJIT
6
Input Clock Period Jitter
f
PFD 20 MHz — 1,000 ps p-p
f
PFD < 20 MHz — 0.02 UIPP
t
HI Input Clock High Time 90% to 90% 0.5 — ns
t
LO Input Clock Low Time 10% to 10% 0.5 — ns
t
STABLE
5
STANDBY High to PLL Stable — 15 ms
t
RST RST/RESETM Pulse Width 1 — ns
t
RSTREC RST Recovery Time 1 — ns
t
RST_DIV RESETC/D Pulse Width 10 — ns
t
RSTREC_DIV RESETC/D Recovery Time 1 — ns
t
ROTATE-SETUP PHASESTEP Setup Time 10 — ns3-32
DC and Switching Characteristics
MachXO2 Family Data Sheet
t
ROTATE_WD PHASESTEP Pulse Width 4 — VCO Cycles
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over
1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See TN1199, MachXO2 sysCLOCK PLL
Design and Usage Guide for more details.
5. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed.
6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be
transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table.
7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default
value of none.
8. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in the presence
of SSO noise.
sysCLOCK PLL Timing (Continued)
Over Recommended Operating Conditions
Parameter Descriptions Conditions Min. Max. Units3-33
DC and Switching Characteristics
MachXO2 Family Data Sheet
MachXO2 Oscillator Output Frequency
MachXO2 Standby Mode Timing – ZE Devices
MachXO2 Standby Mode Timing – HC/HE Devices
Symbol Parameter Min. Typ. Max Units
f
MAX
Oscillator Output Frequency (Commercial Grade Devices,
0 to 85°C) 125.685 133 140.315 MHz
Oscillator Output Frequency (Industrial Grade Devices,
-40 to 100°C) 124.355 133 141.645 MHz
t
DT Output Clock Duty Cycle 43 50 57 %
t
OPJIT
1
Output Clock Period Jitter 0.01 0.012 0.02 UIPP
t
STABLEOSC STDBY Low to Oscillator Stable 0.01 0.05 0.1 µs
1. Output Clock Period Jitter specified at 133MHz. The values for lower frequencies will be smaller UIPP. The typical value for 133MHz is 95ps
and for 2.08MHz the typical value is 1.54ns.
Symbol Parameter Device Min. Typ. Max Units
t
PWRDN USERSTDBY High to Stop All — — 13 ns
t
PWRUP USERSTDBY Low to Power Up
LCMXO2-256 — µs
LCMXO2-640 — µs
LCMXO2-1200 20 — 50 µs
LCMXO2-2000 — µs
LCMXO2-4000 — µs
LCMXO2-7000 — µs
t
WSTDBY USERSTDBY Pulse Width All 19 — — ns
t
BNDGAPSTBL USERSTDBY High to Bandgap Stable All — — 15 ns
Symbol Parameter Device Min. Typ. Max Units
t
PWRDN USERSTDBY High to Stop All — — 9 ns
t
PWRUP USERSTDBY Low to Power Up
LCMXO2-256 — µs
LCMXO2-640 — µs
LCMXO2-640U — µs
LCMXO2-1200 20 — 50 µs
LCMXO2-1200U — µs
LCMXO2-2000 — µs
LCMXO2-2000U — µs
LCMXO2-4000 — µs
LCMXO2-7000 — µs
t
WSTDBY USERSTDBY Pulse Width All 18 — — ns
USERSTDBY
t
PWRUP
USERSTDBY Mode
t
PWRDN
t
WSTDBY
BG, POR3-34
DC and Switching Characteristics
MachXO2 Family Data Sheet
Flash Download Time1, 2
JTAG Port Timing Specifications
Symbol Parameter Device Typ. Units
t
REFRESH POR to Device I/O Active
LCMXO2-256 0.6 ms
LCMXO2-640 1.0 ms
LCMXO2-640U 1.9 ms
LCMXO2-1200 1.9 ms
LCMXO2-1200U 1.4 ms
LCMXO2-2000 1.4 ms
LCMXO2-2000U 2.4 ms
LCMXO2-4000 2.4 ms
LCMXO2-7000 3.8 ms
1. Assumes sysMEM EBR initialized to an all zero pattern if they are used.
2. The Flash download time is measured starting from the maximum voltage of POR trip point.
Symbol Parameter Min. Max. Units
f
MAX TCK clock frequency — 25 MHz
t
BTCPH TCK [BSCAN] clock pulse width high 20 — ns
t
BTCPL TCK [BSCAN] clock pulse width low 20 — ns
t
BTS TCK [BSCAN] setup time 10 — ns
t
BTH TCK [BSCAN] hold time 8 — ns
t
BTCO TAP controller falling edge of clock to valid output — 10 ns
t
BTCODIS TAP controller falling edge of clock to valid disable — 10 ns
t
BTCOEN TAP controller falling edge of clock to valid enable — 10 ns
t
BTCRS BSCAN test capture register setup time 8 — ns
t
BTCRH BSCAN test capture register hold time 20 — ns
t
BUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns
t
BTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns
t
BTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns 3-35
DC and Switching Characteristics
MachXO2 Family Data Sheet
Figure 3-12. JTAG Port Timing Waveforms
TMS
TDI
TCK
TDO
Data to be
captured
from I/O
Data to be
driven out
to I/O
Valid Data Valid Data
Valid Data Valid Data
Data Captured
t
BTCPH t
BTCPL
t
BTCOEN
t
BTCRS
t
BTUPOEN t
BUTCO t
BTUODIS
t
BTCRH
t
BTCO t
BTCODIS
t
BTS t
BTH
t
BTCP3-36
DC and Switching Characteristics
MachXO2 Family Data Sheet
sysCONFIG Port Timing Specifications
I
2
C Port Timing Specifications1, 2
SPI Port Timing Specifications1
Symbol Parameter Min. Max. Units
All Configuration Modes
t
PRGM PROGRAMN low pulse accept 55 — ns
t
PRGMJ PROGRAMN low pulse rejection — 25 ns
t
INITL INITN low time — 55 us
t
DPPINIT PROGRAMN low to INITN low — 70 ns
t
DPPDONE PROGRAMN low to DONE low — 80 ns
t
IODISS PROGRAMN low to I/O disable — 120 ns
Slave SPI
f
MAX CCLK clock frequency — 66 MHz
t
CCLKH CCLK clock pulse width high 7.5 — ns
t
CCLKL CCLK clock pulse width low 7.5 — ns
t
STSU CCLK setup time 2 — ns
t
STH CCLK hold time 0 — ns
t
STCO CCLK falling edge to valid output — 10 ns
t
STOZ CCLK falling edge to valid disable — 10 ns
t
STOV CCLK falling edge to valid enable — 10 ns
t
SCS Chip select high time 25 — ns
t
SCSS Chip select setup time 3 — ns
t
SCSH Chip select hold time 3 — ns
Master SPI
f
MAX MCLK clock frequency — 133 MHz
t
MCLKH MCLK clock pulse width high 3.75 — ns
t
MCLKL MCLK clock pulse width low 3.75 — ns
t
STSU MCLK setup time 5 — ns
t
STH MCLK hold time 1 — ns
t
CSSPI INITN high to chip select low 100 200 ns
t
MCLK INITN high to first MCLK edge 0.75 1 us
Symbol Parameter Min. Max. Units
f
MAX Maximum SCL clock frequency — 400 KHz
1. MachXO2 supports the following modes:
• Standard-mode (Sm), with a bit rate up to 100 kbit/s (user and configuration mode)
• Fast-mode (Fm), with a bit rate up to 400 kbit/s (user and configuration mode)
2. Refer to the I2
C specification for timing requirements.
Symbol Parameter Min. Max. Units
f
MAX Maximum SCK clock frequency — 45 MHz
1. Applies to user mode only. For configuration mode timing specifications, refer to sysCONFIG Port Timing Specifications
table in this data sheet.3-37
DC and Switching Characteristics
MachXO2 Family Data Sheet
Switching Test Conditions
Figure 3-13 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-5.
Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards
Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces
Note: Output test conditions for all other interfaces are determined by the respective standards.
Test Condition R1 CL Timing Ref. VT
LVTTL and LVCMOS settings (L -> H, H -> L) 0pF
LVTTL, LVCMOS 3.3 = 1.5V —
LVCMOS 2.5 = VCCIO/2 —
LVCMOS 1.8 = VCCIO/2 —
LVCMOS 1.5 = VCCIO/2 —
LVCMOS 1.2 = VCCIO/2 —
LVTTL and LVCMOS 3.3 (Z -> H)
188 0pF
1.5 VOL
LVTTL and LVCMOS 3.3 (Z -> L) 1.5 VOH
Other LVCMOS (Z -> H) VCCIO/2 VOL
Other LVCMOS (Z -> L) VCCIO/2 VOH
LVTTL + LVCMOS (H -> Z) VOH - 0.15 VOL
LVTTL + LVCMOS (L -> Z) VOL - 0.15 VOH
DUT
V T
R1
CL
Test Poi n twww.latticesemi.com 4-1 DS1035 Pinout Information_01.7
January 3013 Data Sheet DS1035
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Signal Descriptions
Signal Name I/O Descriptions
General Purpose
P[Edge] [Row/Column
Number]_[A/B/C/D] I/O
[Edge] indicates the edge of the device on which the pad is located. Valid edge designations
are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on which the PIO
Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When
Edge is L (Left) or R (Right), only need to specify Column Number.
[A/B/C/D] indicates the PIO within the group to which the pad is connected.
Some of these user-programmable pins are shared with special function pins. When not used
as special function pins, these pins can be programmed as I/Os for user logic.
During configuration of the user-programmable I/Os, the user has an option to tri-state the
I/Os and enable an internal pull-up, pull-down or buskeeper resistor. This option also applies
to unused pins (or those not bonded to a package pin). The default during configuration is for
user-programmable I/Os to be tri-stated with an internal pull-down resistor enabled. When the
device is erased, I/Os will be tri-stated with an internal pull-down resistor enabled. Some pins,
such as PROGRAMN and JTAG pins, default to tri-stated I/Os with pull-up resistors enabled
when the device is erased.
NC — No connect.
GND — GND – Ground. Dedicated pins. It is recommended that all GNDs are tied together.
VCC — V
CC – The power supply pins for core logic. Dedicated pins. It is recommended that all VCCs
are tied to the same supply.
VCCIOx — VCCIO – The power supply pins for I/O Bank x. Dedicated pins. It is recommended that all
VCCIOs located in the same bank are tied to the same supply.
PLL and Clock Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)
[LOC]_GPLL[T, C]_IN — Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left
PLL) and R (Right PLL). T = true and C = complement.
[LOC]_GPLL[T, C]_FB — Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L (Left
PLL) and R (Right PLL). T = true and C = complement.
PCLK [n]_[2:0] — Primary Clock pads. One to three clock pads per side.
Test and Programming (Dual function pins used for test access port and during sysCONFIG™)
TMS I Test Mode Select input pin, used to control the 1149.1 state machine.
TCK I Test Clock input pin, used to clock the 1149.1 state machine.
TDI I Test Data input pin, used to load data into the device using an 1149.1 state machine.
TDO O Output pin – Test Data output pin used to shift data out of the device using 1149.1.
JTAGENB I
Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the
JTAG pins (TDI, TDO, TMS, TCK) as general purpose I/O, then:
If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O.
If JTAGENB is high: TDI, TDO, TMS and TCK function as JTAG pins.
For more details, refer to TN1204, MachXO2 Programming and Configuration Usage Guide.
Configuration (Dual function pins used during sysCONFIG)
PROGRAMN I Initiates configuration sequence when asserted low. This pin always has an active pull-up.
INITN I/O Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up
is enabled.
MachXO2 Family Data Sheet
Pinout Information4-2
Pinout Information
MachXO2 Family Data Sheet
DONE I/O Open Drain pin. Indicates that the configuration sequence is complete, and the start-up
sequence is in progress.
MCLK/CCLK I/O Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration
Clock for configuring an FPGA in SPI and SPIm configuration modes.
SN I Slave SPI active low chip select input.
CSSPIN I/O Master SPI active low chip select output.
SI/SISPI I/O Slave SPI serial data input and master SPI serial data output.
SO/SPISO I/O Slave SPI serial data output and master SPI serial data input.
SCL I/O Slave I2
C clock input and master I2
C clock output.
SDA I/O Slave I2
C data input and master I2
C data output.
Signal Name I/O Descriptions
General Purpose4-3
Pinout Information
MachXO2 Family Data Sheet
Pin Information Summary
MachXO2-256 MachXO2-640 MachXO2-640U
32 QFN1
64 ucBGA 100 TQFP 132 csBGA 100 TQFP 132 csBGA 144 TQFP
General Purpose I/O per Bank
Bank 0 8 9 13 13 18 19 27
Bank 1 2 12 14 14 20 20 26
Bank 2 9 11 14 14 20 20 28
Bank 3 2 12 14 14 20 20 26
Bank 4 0 0 0 0 0 0 0
Bank 5 0 0 0 0 0 0 0
Total General Purpose Single Ended
I/O 21 44 55 55 78 79 107
Differential I/O per Bank
Bank 0 4 5 7 7 9 10 14
Bank 1 1 6 7 7 10 10 13
Bank 2 4 5 7 7 10 10 14
Bank 3 1 6 7 7 10 10 13
Bank 4 0 0 0 0 0 0 0
Bank 5 0 0 0 0 0 0 0
Total General Purpose Differential I/O 10 22 28 28 39 40 54
Dual Function I/O 22 27 29 29 29 29 33
High-speed Differential I/O
Bank 0 0 0 0 0 0 0 7
Gearboxes
Number of 7:1 or 8:1 Output Gearbox
Available (Bank 0) 00 0 0 0 0 7
Number of 7:1 or 8:1 Input Gearbox
Available (Bank 2) 00 0 0 0 0 7
DQS Groups
Bank 1 0 0 0 0 0 0 2
VCCIO Pins
Bank 0 2 2 2 2 2 2 3
Bank 1 1 2 2 2 2 2 3
Bank 2 2 2 2 2 2 2 3
Bank 3 1 2 2 2 2 2 3
Bank 4 0 0 0 0 0 0 0
Bank 5 0 0 0 0 0 0 0
VCC 2 2 2 2 2 2 4
GND 2 8 8 8 8 10 12
NC 0 1 26 58 3 32 8
Total Count of Bonded Pins 31 62 73 73 96 99 135
1. Lattice recommends soldering the central thermal pad onto the top PCB ground for improved thermal resistance.4-4
Pinout Information
MachXO2 Family Data Sheet
MachXO2-1200 MachXO2-1200U
100 TQFP 132 csBGA 144 TQFP 25 WLCSP 256 ftBGA
General Purpose I/O per Bank
Bank 0 18 25 27 11 50
Bank 1 21 26 26 0 52
Bank 2 20 28 28 7 52
Bank 3 20 25 26 0 16
Bank 4 0 0 0 0 16
Bank 5 0 0 0 0 20
Total General Purpose Single Ended I/O 79 104 107 18 206
Differential I/O per Bank
Bank 0 9 13 14 5 25
Bank 1 10 13 13 0 26
Bank 2 10 14 14 2 26
Bank 3 10 12 13 0 8
Bank 4 0 0 0 0 8
Bank 5 0 0 0 0 10
Total General Purpose Differential I/O 39 52 54 7 103
Dual Function I/O 31 33 33 18 33
High-speed Differential I/O
Bank 0 4 7 7 0 14
Gearboxes
Number of 7:1 or 8:1 Output Gearbox Available
(Bank 0) 4 7 7 0 14
Number of 7:1 or 8:1 Input Gearbox Available
(Bank 2) 5 7 7 0 14
DQS Groups
Bank 1 1 2 2 0 2
VCCIO Pins
Bank 0 2 3 3 1 4
Bank 1 2 3 3 0 4
Bank 2 2 3 3 1 4
Bank 3 3 3 3 0 1
Bank 4 0 0 0 0 2
Bank 5 0 0 0 0 1
VCC 2 4 4 2 8
GND 8 10 12 2 24
NC 1 1 8 0 1
Total Count of Bonded Pins 98 130 135 24 2544-5
Pinout Information
MachXO2 Family Data Sheet
MachXO2-2000 MachXO2-2000U
100
TQFP
132
csBGA
144
TQFP
256
caBGA
256
ftBGA 484 ftBGA
General Purpose I/O per Bank
Bank 0 18 25 27 50 50 70
Bank 1 21 26 28 52 52 68
Bank 2 20 28 28 52 52 72
Bank 3 6 7 8 16 16 24
Bank 4 6 8 10 16 16 16
Bank 5 8 10 10 20 20 28
Total General Purpose Single-Ended I/O 79 104 111 206 206 278
Differential I/O per Bank
Bank 0 9 13 14 25 25 35
Bank 1 10 13 14 26 26 34
Bank 2 10 14 14 26 26 36
Bank 3 3 3 4 8 8 12
Bank 4 3 4 5 8 8 8
Bank 5 4 5 5 10 10 14
Total General Purpose Differential I/O 39 52 56 103 103 139
Dual Function I/O 31 33 33 33 33 37
High-speed Differential I/O
Bank 0 4 8 9 14 14 18
Gearboxes
Number of 7:1 or 8:1 Output Gearbox
Available (Bank 0) 4 8 9 14 14 18
Number of 7:1 or 8:1 Input Gearbox
Available (Bank 2) 10 14 14 14 14 18
DQS Groups
Bank 1 1 2 2 2 2 2
VCCIO Pins
Bank 0 2 3 3 4 4 10
Bank 1 2 3 3 4 4 10
Bank 2 2 3 3 4 4 10
Bank 3 1 1 1 1 1 3
Bank 4 1 1 1 2 2 4
Bank 5 1 1 1 1 1 3
VCC 2 4 4 8 8 12
GND 8 10 12 24 24 48
NC 1 1 4 1 1 105
Total Count of Bonded Pins 98 130 139 254 254 3784-6
Pinout Information
MachXO2 Family Data Sheet
MachXO2-4000
132
csBGA
144
TQFP
184
csBGA
256
caBGA
256
ftBGA
332
caBGA
484
fpBGA
General Purpose I/O per Bank
Bank 0 25 27 37 50 50 68 70
Bank 1 26 29 37 52 52 68 68
Bank 2 28 29 39 52 52 70 72
Bank 3 7 9 10 16 16 24 24
Bank 4 8 10 12 16 16 16 16
Bank 5 10 10 15 20 20 28 28
Total General Purpose Single Ended I/O 104 114 150 206 206 274 278
Differential I/O per Bank
Bank 0 13 14 18 25 25 34 35
Bank 1 13 14 18 26 26 34 34
Bank 2 14 14 19 26 26 35 36
Bank 3 3 4 4 8 8 12 12
Bank 4 4 5 6 8 8 8 8
Bank 5 5 5 7 10 10 14 14
Total General Purpose Differential I/O 52 56 72 103 103 137 139
Dual Function I/O 37 37 37 37 37 37 37
High-speed Differential I/O
Bank 0 8 9 8 18 18 18 18
Gearboxes
Number of 7:1 or 8:1 Output Gearbox
Available (Bank 0) 8 9 9 18 18 18 18
Number of 7:1 or 8:1 Input Gearbox
Available (Bank 2) 14 14 12 18 18 18 18
DQS Groups
Bank 1 2 2 2 2 2 2 2
VCCIO Pins
Bank 0 3 3 3 4 4 4 10
Bank 1 3 3 3 4 4 4 10
Bank 2 3 3 3 4 4 4 10
Bank 3 1 1 1 1 1 2 3
Bank 4 1 1 1 2 2 1 4
Bank 5 1 1 1 1 1 2 3
VCC 4 4 4 8 8 8 12
GND 10 12 16 24 24 27 48
NC 1 1 1 1 1 5 105
Total Count of Bonded Pins 130 142 182 254 254 326 3784-7
Pinout Information
MachXO2 Family Data Sheet
MachXO2-7000
144 TQFP 256 caBGA 256 ftBGA 332 caBGA 484 fpBGA
General Purpose I/O per Bank
Bank 0 27 50 50 68 82
Bank 1 29 52 52 70 84
Bank 2 29 52 52 70 84
Bank 3 9 16 16 24 28
Bank 4 10 16 16 16 24
Bank 5 10 20 20 30 32
Total General Purpose Single Ended I/O 114 206 206 278 334
Differential I/O per Bank
Bank 0 14 25 25 34 41
Bank 1 14 26 26 35 42
Bank 2 14 26 26 35 42
Bank 3 4 8 8 12 14
Bank 4 5 8 8 8 12
Bank 5 5 10 10 15 16
Total General Purpose Differential I/O 56 103 103 139 167
Dual Function I/O 37 37 37 37 37
High-speed Differential I/O
Bank 0 9 20 20 21 21
Gearboxes
Number of 7:1 or 8:1 Output Gearbox
Available (Bank 0) 9 20 20 21 21
Number of 7:1 or 8:1 Input Gearbox
Available (Bank 2) 14 20 20 21 21
DQS Groups
Bank 1 2 2 2 2 2
VCCIO Pins
Bank 0 3 4 4 4 10
Bank 1 3 4 4 4 10
Bank 2 3 4 4 4 10
Bank 3 1 1 1 2 3
Bank 4 1 2 2 1 4
Bank 5 1 1 1 2 3
VCC 4 8 8 8 12
GND 12 24 24 27 48
NC 1 1 1 1 49
Total Count of Bonded Pins 142 254 254 330 4344-8
Pinout Information
MachXO2 Family Data Sheet
For Further Information
For further information regarding logic signal connections for various packages please refer to the MachXO2
Device Pinout Files.
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Users must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package
specific thermal values.
For Further Information
For further information regarding Thermal Management, refer to the following:
• Thermal Management document
• TN1198, Power Estimation and Management for MachXO2 Devices
• The Power Calculator tool is included with the Lattice design tools, or as a standalone download from
www.latticesemi.com/softwarewww.latticesemi.com 5-1 DS1035 Order Info_01.9
January 2013 Data Sheet DS1035
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
MachXO2 Part Number Description
LCMXO2 – XXXX X X X – X XXXXXX X XX XX
Device Status
Blank = Production Device
ES = Engineering Sample
R1 = Production Release 1 Device
50 = WLCSP package, 50 parts per reel
Shipping Method
Blank = Trays
TR = Tape and Reel
Grade
C = Commercial
I = Industrial
Logic Capacity
256 = 256 LUTs
640 = 640 LUTs
1200 = 1280 LUTs
2000 = 2112 LUTs
4000 = 4320 LUTs
7000 = 6864 LUTs
Power/Performance
Z = Low Power
H = High Performance
I/O Count
Blank = Standard Device
U = Ultra High I/O Device
Supply Voltage
C = 2.5V/3.3V
E = 1.2V
Speed
1 = Slowest
2
3 = Fastest
4 = Slowest
5
6 = Fastest
Low Power
High Performance
Package
UWG25 = 25-Ball Halogen-Free WLCSP
(0.4 mm Pitch)
SG32 = 32-Pin Halogen-Free QFN
(0.5 mm Pitch)
UMG64 = 64-Ball Halogen-Free ucBGA
(0.4 mm Pitch)
TG100 = 100-Pin Halogen-Free TQFP
TG144 = 144-Pin Halogen-Free TQFP
MG132 = 132-Ball Halogen-Free csBGA
(0.5 mm Pitch)
MG184 = 184-Ball Halogen-Free csBGA
(0.5mm Pitch)
BG256 = 256-Ball Halogen-Free caBGA
(0.8 mm Pitch)
FTG256 = 256-Ball Halogen-Free ftBGA
(1.0 mm Pitch)
BG332 = 332-Ball Halogen-Free caBGA
FG484 = 484-Ball Halogen-Free fpBGA
(1.0 mm Pitch)
Device Family
MachXO2 PLD
Ordering Information
MachXO2 devices have top-side markings, for commercial and industrial grades, as shown below:
Notes:
1. Markings are abbreviated for small packages.
2. See PCN 05A-12 for information regarding a change to the top-side mark logo.
LCMXO2-1200ZE
1TG100C
Datecode
LCMXO2
256ZE
1UG64C
Datecode
MachXO2 Family Data Sheet
Ordering Information5-2
Ordering Information
MachXO2 Family Data Sheet
Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-256ZE-1SG32C 256 1.2V -1 Halogen-Free QFN 32 COM
LCMXO2-256ZE-2SG32C 256 1.2V -2 Halogen-Free QFN 32 COM
LCMXO2-256ZE-3SG32C 256 1.2V -3 Halogen-Free QFN 32 COM
LCMXO2-256ZE-1UMG64C 256 1.2V -1 Halogen-Free ucBGA 64 COM
LCMXO2-256ZE-2UMG64C 256 1.2V -2 Halogen-Free ucBGA 64 COM
LCMXO2-256ZE-3UMG64C 256 1.2V -3 Halogen-Free ucBGA 64 COM
LCMXO2-256ZE-1TG100C 256 1.2V -1 Halogen-Free TQFP 100 COM
LCMXO2-256ZE-2TG100C 256 1.2V -2 Halogen-Free TQFP 100 COM
LCMXO2-256ZE-3TG100C 256 1.2V -3 Halogen-Free TQFP 100 COM
LCMXO2-256ZE-1MG132C 256 1.2V -1 Halogen-Free csBGA 132 COM
LCMXO2-256ZE-2MG132C 256 1.2V -2 Halogen-Free csBGA 132 COM
LCMXO2-256ZE-3MG132C 256 1.2V -3 Halogen-Free csBGA 132 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-640ZE-1TG100C 640 1.2V -1 Halogen-Free TQFP 100 COM
LCMXO2-640ZE-2TG100C 640 1.2V -2 Halogen-Free TQFP 100 COM
LCMXO2-640ZE-3TG100C 640 1.2V -3 Halogen-Free TQFP 100 COM
LCMXO2-640ZE-1MG132C 640 1.2V -1 Halogen-Free csBGA 132 COM
LCMXO2-640ZE-2MG132C 640 1.2V -2 Halogen-Free csBGA 132 COM
LCMXO2-640ZE-3MG132C 640 1.2V -3 Halogen-Free csBGA 132 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200ZE-1TG100C 1280 1.2V -1 Halogen-Free TQFP 100 COM
LCMXO2-1200ZE-2TG100C 1280 1.2V -2 Halogen-Free TQFP 100 COM
LCMXO2-1200ZE-3TG100C 1280 1.2V -3 Halogen-Free TQFP 100 COM
LCMXO2-1200ZE-1MG132C 1280 1.2V -1 Halogen-Free csBGA 132 COM
LCMXO2-1200ZE-2MG132C 1280 1.2V -2 Halogen-Free csBGA 132 COM
LCMXO2-1200ZE-3MG132C 1280 1.2V -3 Halogen-Free csBGA 132 COM
LCMXO2-1200ZE-1TG144C 1280 1.2V -1 Halogen-Free TQFP 144 COM
LCMXO2-1200ZE-2TG144C 1280 1.2V -2 Halogen-Free TQFP 144 COM
LCMXO2-1200ZE-3TG144C 1280 1.2V -3 Halogen-Free TQFP 144 COM5-3
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000ZE-1TG100C 2112 1.2V -1 Halogen-Free TQFP 100 COM
LCMXO2-2000ZE-2TG100C 2112 1.2V -2 Halogen-Free TQFP 100 COM
LCMXO2-2000ZE-3TG100C 2112 1.2V -3 Halogen-Free TQFP 100 COM
LCMXO2-2000ZE-1MG132C 2112 1.2V -1 Halogen-Free csBGA 132 COM
LCMXO2-2000ZE-2MG132C 2112 1.2V -2 Halogen-Free csBGA 132 COM
LCMXO2-2000ZE-3MG132C 2112 1.2V -3 Halogen-Free csBGA 132 COM
LCMXO2-2000ZE-1TG144C 2112 1.2V -1 Halogen-Free TQFP 144 COM
LCMXO2-2000ZE-2TG144C 2112 1.2V -2 Halogen-Free TQFP 144 COM
LCMXO2-2000ZE-3TG144C 2112 1.2V -3 Halogen-Free TQFP 144 COM
LCMXO2-2000ZE-1BG256C 2112 1.2V -1 Halogen-Free caBGA 256 COM
LCMXO2-2000ZE-2BG256C 2112 1.2V -2 Halogen-Free caBGA 256 COM
LCMXO2-2000ZE-3BG256C 2112 1.2V -3 Halogen-Free caBGA 256 COM
LCMXO2-2000ZE-1FTG256C 2112 1.2V -1 Halogen-Free ftBGA 256 COM
LCMXO2-2000ZE-2FTG256C 2112 1.2V -2 Halogen-Free ftBGA 256 COM
LCMXO2-2000ZE-3FTG256C 2112 1.2V -3 Halogen-Free ftBGA 256 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-4000ZE-1MG132C 4320 1.2V -1 Halogen-Free csBGA 132 COM
LCMXO2-4000ZE-2MG132C 4320 1.2V -2 Halogen-Free csBGA 132 COM
LCMXO2-4000ZE-3MG132C 4320 1.2V -3 Halogen-Free csBGA 132 COM
LCMXO2-4000ZE-1TG144C 4320 1.2V -1 Halogen-Free TQFP 144 COM
LCMXO2-4000ZE-2TG144C 4320 1.2V -2 Halogen-Free TQFP 144 COM
LCMXO2-4000ZE-3TG144C 4320 1.2V -3 Halogen-Free TQFP 144 COM
LCMXO2-4000ZE-1BG256C 4320 1.2V -1 Halogen-Free caBGA 256 COM
LCMXO2-4000ZE-2BG256C 4320 1.2V -2 Halogen-Free caBGA 256 COM
LCMXO2-4000ZE-3BG256C 4320 1.2V -3 Halogen-Free caBGA 256 COM
LCMXO2-4000ZE-1FTG256C 4320 1.2V -1 Halogen-Free ftBGA 256 COM
LCMXO2-4000ZE-2FTG256C 4320 1.2V -2 Halogen-Free ftBGA 256 COM
LCMXO2-4000ZE-3FTG256C 4320 1.2V -3 Halogen-Free ftBGA 256 COM
LCMXO2-4000ZE-1BG332C 4320 1.2V -1 Halogen-Free caBGA 332 COM
LCMXO2-4000ZE-2BG332C 4320 1.2V -2 Halogen-Free caBGA 332 COM
LCMXO2-4000ZE-3BG332C 4320 1.2V -3 Halogen-Free caBGA 332 COM
LCMXO2-4000ZE-1FG484C 4320 1.2V -1 Halogen-Free fpBGA 484 COM
LCMXO2-4000ZE-2FG484C 4320 1.2V -2 Halogen-Free fpBGA 484 COM
LCMXO2-4000ZE-3FG484C 4320 1.2V -3 Halogen-Free fpBGA 484 COM5-4
Ordering Information
MachXO2 Family Data Sheet
High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free
(RoHS) Packaging
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-7000ZE-1TG144C 6864 1.2V -1 Halogen-Free TQFP 144 COM
LCMXO2-7000ZE-2TG144C 6864 1.2V -2 Halogen-Free TQFP 144 COM
LCMXO2-7000ZE-3TG144C 6864 1.2V -3 Halogen-Free TQFP 144 COM
LCMXO2-7000ZE-1BG256C 6864 1.2V -1 Halogen-Free caBGA 256 COM
LCMXO2-7000ZE-2BG256C 6864 1.2V -2 Halogen-Free caBGA 256 COM
LCMXO2-7000ZE-3BG256C 6864 1.2V -3 Halogen-Free caBGA 256 COM
LCMXO2-7000ZE-1FTG256C 6864 1.2V -1 Halogen-Free ftBGA 256 COM
LCMXO2-7000ZE-2FTG256C 6864 1.2V -2 Halogen-Free ftBGA 256 COM
LCMXO2-7000ZE-3FTG256C 6864 1.2V -3 Halogen-Free ftBGA 256 COM
LCMXO2-7000ZE-1BG332C 6864 1.2V -1 Halogen-Free caBGA 332 COM
LCMXO2-7000ZE-2BG332C 6864 1.2V -2 Halogen-Free caBGA 332 COM
LCMXO2-7000ZE-3BG332C 6864 1.2V -3 Halogen-Free caBGA 332 COM
LCMXO2-7000ZE-1FG484C 6864 1.2V -1 Halogen-Free fpBGA 484 COM
LCMXO2-7000ZE-2FG484C 6864 1.2V -2 Halogen-Free fpBGA 484 COM
LCMXO2-7000ZE-3FG484C 6864 1.2V -3 Halogen-Free fpBGA 484 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200ZE-1TG100CR11
1280 1.2V -1 Halogen-Free TQFP 100 COM
LCMXO2-1200ZE-2TG100CR11
1280 1.2V -2 Halogen-Free TQFP 100 COM
LCMXO2-1200ZE-3TG100CR11
1280 1.2V -3 Halogen-Free TQFP 100 COM
LCMXO2-1200ZE-1MG132CR11
1280 1.2V -1 Halogen-Free csBGA 132 COM
LCMXO2-1200ZE-2MG132CR11
1280 1.2V -2 Halogen-Free csBGA 132 COM
LCMXO2-1200ZE-3MG132CR11
1280 1.2V -3 Halogen-Free csBGA 132 COM
LCMXO2-1200ZE-1TG144CR11
1280 1.2V -1 Halogen-Free TQFP 144 COM
LCMXO2-1200ZE-2TG144CR11
1280 1.2V -2 Halogen-Free TQFP 144 COM
LCMXO2-1200ZE-3TG144CR11
1280 1.2V -3 Halogen-Free TQFP 144 COM
1. Specifications for the “LCMXO2-1200ZE-speed package CR1” are the same as the “LCMXO2-1200ZE-speed package C” devices respectively, except as specified in the R1 Device Specifications section on page 5-18 of this data sheet.
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-256HC-4SG32C 256 2.5V/3.3V -4 Halogen-Free QFN 32 COM
LCMXO2-256HC-5SG32C 256 2.5V/3.3V -5 Halogen-Free QFN 32 COM
LCMXO2-256HC-6SG32C 256 2.5V/3.3V -6 Halogen-Free QFN 32 COM
LCMXO2-256HC-4UMG64C 256 2.5V/3.3V -4 Halogen-Free ucBGA 64 COM
LCMXO2-256HC-5UMG64C 256 2.5V/3.3V -5 Halogen-Free ucBGA 64 COM
LCMXO2-256HC-6UMG64C 256 2.5V/3.3V -6 Halogen-Free ucBGA 64 COM
LCMXO2-256HC-4TG100C 256 2.5V/3.3V -4 Halogen-Free TQFP 100 COM
LCMXO2-256HC-5TG100C 256 2.5V/3.3V -5 Halogen-Free TQFP 100 COM
LCMXO2-256HC-6TG100C 256 2.5V/3.3V -6 Halogen-Free TQFP 100 COM
LCMXO2-256HC-4MG132C 256 2.5V/3.3V -4 Halogen-Free csBGA 132 COM
LCMXO2-256HC-5MG132C 256 2.5V/3.3V -5 Halogen-Free csBGA 132 COM
LCMXO2-256HC-6MG132C 256 2.5V/3.3V -6 Halogen-Free csBGA 132 COM5-5
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-640HC-4TG100C 640 2.5V/3.3V -4 Halogen-Free TQFP 100 COM
LCMXO2-640HC-5TG100C 640 2.5V/3.3V -5 Halogen-Free TQFP 100 COM
LCMXO2-640HC-6TG100C 640 2.5V/3.3V -6 Halogen-Free TQFP 100 COM
LCMXO2-640HC-4MG132C 640 2.5V/3.3V -4 Halogen-Free csBGA 132 COM
LCMXO2-640HC-5MG132C 640 2.5V/3.3V -5 Halogen-Free csBGA 132 COM
LCMXO2-640HC-6MG132C 640 2.5V/3.3V -6 Halogen-Free csBGA 132 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-640UHC-4TG144C 640 2.5V/3.3V -4 Halogen-Free TQFP 144 COM
LCMXO2-640UHC-5TG144C 640 2.5V/3.3V -5 Halogen-Free TQFP 144 COM
LCMXO2-640UHC-6TG144C 640 2.5V/3.3V -6 Halogen-Free TQFP 144 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200HC-4TG100C 1280 2.5V/3.3V -4 Halogen-Free TQFP 100 COM
LCMXO2-1200HC-5TG100C 1280 2.5V/3.3V -5 Halogen-Free TQFP 100 COM
LCMXO2-1200HC-6TG100C 1280 2.5V/3.3V -6 Halogen-Free TQFP 100 COM
LCMXO2-1200HC-4MG132C 1280 2.5V/3.3V -4 Halogen-Free csBGA 132 COM
LCMXO2-1200HC-5MG132C 1280 2.5V/3.3V -5 Halogen-Free csBGA 132 COM
LCMXO2-1200HC-6MG132C 1280 2.5V/3.3V -6 Halogen-Free csBGA 132 COM
LCMXO2-1200HC-4TG144C 1280 2.5V/3.3V -4 Halogen-Free TQFP 144 COM
LCMXO2-1200HC-5TG144C 1280 2.5V/3.3V -5 Halogen-Free TQFP 144 COM
LCMXO2-1200HC-6TG144C 1280 2.5V/3.3V -6 Halogen-Free TQFP 144 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200UHC-4FTG256C 1280 2.5V/3.3V -4 Halogen-Free ftBGA 256 COM
LCMXO2-1200UHC-5FTG256C 1280 2.5V/3.3V -5 Halogen-Free ftBGA 256 COM
LCMXO2-1200UHC-6FTG256C 1280 2.5V/3.3V -6 Halogen-Free ftBGA 256 COM5-6
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000HC-4TG100C 2112 2.5V/3.3V -4 Halogen-Free TQFP 100 COM
LCMXO2-2000HC-5TG100C 2112 2.5V/3.3V -5 Halogen-Free TQFP 100 COM
LCMXO2-2000HC-6TG100C 2112 2.5V/3.3V -6 Halogen-Free TQFP 100 COM
LCMXO2-2000HC-4MG132C 2112 2.5V/3.3V -4 Halogen-Free csBGA 132 COM
LCMXO2-2000HC-5MG132C 2112 2.5V/3.3V -5 Halogen-Free csBGA 132 COM
LCMXO2-2000HC-6MG132C 2112 2.5V/3.3V -6 Halogen-Free csBGA 132 COM
LCMXO2-2000HC-4TG144C 2112 2.5V/3.3V -4 Halogen-Free TQFP 144 COM
LCMXO2-2000HC-5TG144C 2112 2.5V/3.3V -5 Halogen-Free TQFP 144 COM
LCMXO2-2000HC-6TG144C 2112 2.5V/3.3V -6 Halogen-Free TQFP 144 COM
LCMXO2-2000HC-4BG256C 2112 2.5V/3.3V -4 Halogen-Free caBGA 256 COM
LCMXO2-2000HC-5BG256C 2112 2.5V/3.3V -5 Halogen-Free caBGA 256 COM
LCMXO2-2000HC-6BG256C 2112 2.5V/3.3V -6 Halogen-Free caBGA 256 COM
LCMXO2-2000HC-4FTG256C 2112 2.5V/3.3V -4 Halogen-Free ftBGA 256 COM
LCMXO2-2000HC-5FTG256C 2112 2.5V/3.3V -5 Halogen-Free ftBGA 256 COM
LCMXO2-2000HC-6FTG256C 2112 2.5V/3.3V -6 Halogen-Free ftBGA 256 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000UHC-4FG484C 2112 2.5V/3.3V -4 Halogen-Free fpBGA 484 COM
LCMXO2-2000UHC-5FG484C 2112 2.5V/3.3V -5 Halogen-Free fpBGA 484 COM
LCMXO2-2000UHC-6FG484C 2112 2.5V/3.3V -6 Halogen-Free fpBGA 484 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-4000HC-4MG132C 4320 2.5V/3.3V -4 Halogen-Free csBGA 132 COM
LCMXO2-4000HC-5MG132C 4320 2.5V/3.3V -5 Halogen-Free csBGA 132 COM
LCMXO2-4000HC-6MG132C 4320 2.5V/3.3V -6 Halogen-Free csBGA 132 COM
LCMXO2-4000HC-4TG144C 4320 2.5V/3.3V -4 Halogen-Free TQFP 144 COM
LCMXO2-4000HC-5TG144C 4320 2.5V/3.3V -5 Halogen-Free TQFP 144 COM
LCMXO2-4000HC-6TG144C 4320 2.5V/3.3V -6 Halogen-Free TQFP 144 COM
LCMXO2-4000HC-4BG256C 4320 2.5V/3.3V -4 Halogen-Free caBGA 256 COM
LCMXO2-4000HC-5BG256C 4320 2.5V/3.3V -5 Halogen-Free caBGA 256 COM
LCMXO2-4000HC-6BG256C 4320 2.5V/3.3V -6 Halogen-Free caBGA 256 COM
LCMXO2-4000HC-4FTG256C 4320 2.5V/3.3V -4 Halogen-Free ftBGA 256 COM
LCMXO2-4000HC-5FTG256C 4320 2.5V/3.3V -5 Halogen-Free ftBGA 256 COM
LCMXO2-4000HC-6FTG256C 4320 2.5V/3.3V -6 Halogen-Free ftBGA 256 COM
LCMXO2-4000HC-4BG332C 4320 2.5V/3.3V -4 Halogen-Free caBGA 332 COM
LCMXO2-4000HC-5BG332C 4320 2.5V/3.3V -5 Halogen-Free caBGA 332 COM
LCMXO2-4000HC-6BG332C 4320 2.5V/3.3V -6 Halogen-Free caBGA 332 COM
LCMXO2-4000HC-4FG484C 4320 2.5V/3.3V -4 Halogen-Free fpBGA 484 COM
LCMXO2-4000HC-5FG484C 4320 2.5V/3.3V -5 Halogen-Free fpBGA 484 COM
LCMXO2-4000HC-6FG484C 4320 2.5V/3.3V -6 Halogen-Free fpBGA 484 COM5-7
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-7000HC-4TG144C 6864 2.5V/3.3V -4 Halogen-Free TQFP 144 COM
LCMXO2-7000HC-5TG144C 6864 2.5V/3.3V -5 Halogen-Free TQFP 144 COM
LCMXO2-7000HC-6TG144C 6864 2.5V/3.3V -6 Halogen-Free TQFP 144 COM
LCMXO2-7000HC-4BG256C 6864 2.5V/3.3V -4 Halogen-Free caBGA 256 COM
LCMXO2-7000HC-5BG256C 6864 2.5V/3.3V -5 Halogen-Free caBGA 256 COM
LCMXO2-7000HC-6BG256C 6864 2.5V/3.3V -6 Halogen-Free caBGA 256 COM
LCMXO2-7000HC-4FTG256C 6864 2.5V/3.3V -4 Halogen-Free ftBGA 256 COM
LCMXO2-7000HC-5FTG256C 6864 2.5V/3.3V -5 Halogen-Free ftBGA 256 COM
LCMXO2-7000HC-6FTG256C 6864 2.5V/3.3V -6 Halogen-Free ftBGA 256 COM
LCMXO2-7000HC-4BG332C 6864 2.5V/3.3V -4 Halogen-Free caBGA 332 COM
LCMXO2-7000HC-5BG332C 6864 2.5V/3.3V -5 Halogen-Free caBGA 332 COM
LCMXO2-7000HC-6BG332C 6864 2.5V/3.3V -6 Halogen-Free caBGA 332 COM
LCMXO2-7000HC-4FG484C 6864 2.5V/3.3V -4 Halogen-Free fpBGA 484 COM
LCMXO2-7000HC-5FG484C 6864 2.5V/3.3V -5 Halogen-Free fpBGA 484 COM
LCMXO2-7000HC-6FG484C 6864 2.5V/3.3V -6 Halogen-Free fpBGA 484 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200HC-4TG100CR11
1280 2.5V/3.3V -4 Halogen-Free TQFP 100 COM
LCMXO2-1200HC-5TG100CR11
1280 2.5V/3.3V -5 Halogen-Free TQFP 100 COM
LCMXO2-1200HC-6TG100CR11
1280 2.5V/3.3V -6 Halogen-Free TQFP 100 COM
LCMXO2-1200HC-4MG132CR11
1280 2.5V/3.3V -4 Halogen-Free csBGA 132 COM
LCMXO2-1200HC-5MG132CR11
1280 2.5V/3.3V -5 Halogen-Free csBGA 132 COM
LCMXO2-1200HC-6MG132CR11
1280 2.5V/3.3V -6 Halogen-Free csBGA 132 COM
LCMXO2-1200HC-4TG144CR11
1280 2.5V/3.3V -4 Halogen-Free TQFP 144 COM
LCMXO2-1200HC-5TG144CR11
1280 2.5V/3.3V -5 Halogen-Free TQFP 144 COM
LCMXO2-1200HC-6TG144CR11
1280 2.5V/3.3V -6 Halogen-Free TQFP 144 COM
1. Specifications for the “LCMXO2-1200HC-speed package CR1” are the same as the “LCMXO2-1200HC-speed package C” devices respectively, except as specified in the R1 Device Specifications section on page 5-18 of this data sheet. 5-8
Ordering Information
MachXO2 Family Data Sheet
High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free
(RoHS) Packaging
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000HE-4TG100C 2112 1.2V -4 Halogen-Free TQFP 100 COM
LCMXO2-2000HE-5TG100C 2112 1.2V -5 Halogen-Free TQFP 100 COM
LCMXO2-2000HE-6TG100C 2112 1.2V -6 Halogen-Free TQFP 100 COM
LCMXO2-2000HE-4TG144C 2112 1.2V -4 Halogen-Free TQFP 144 COM
LCMXO2-2000HE-5TG144C 2112 1.2V -5 Halogen-Free TQFP 144 COM
LCMXO2-2000HE-6TG144C 2112 1.2V -6 Halogen-Free TQFP 144 COM
LCMXO2-2000HE-4MG132C 2112 1.2V -4 Halogen-Free csBGA 132 COM
LCMXO2-2000HE-5MG132C 2112 1.2V -5 Halogen-Free csBGA 132 COM
LCMXO2-2000HE-6MG132C 2112 1.2V -6 Halogen-Free csBGA 132 COM
LCMXO2-2000HE-4BG256C 2112 1.2V -4 Halogen-Free caBGA 256 COM
LCMXO2-2000HE-5BG256C 2112 1.2V -5 Halogen-Free caBGA 256 COM
LCMXO2-2000HE-6BG256C 2112 1.2V -6 Halogen-Free caBGA 256 COM
LCMXO2-2000HE-4FTG256C 2112 1.2V -4 Halogen-Free ftBGA 256 COM
LCMXO2-2000HE-5FTG256C 2112 1.2V -5 Halogen-Free ftBGA 256 COM
LCMXO2-2000HE-6FTG256C 2112 1.2V -6 Halogen-Free ftBGA 256 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000UHE-4FG484C 2112 1.2V -4 Halogen-Free fpBGA 484 COM
LCMXO2-2000UHE-5FG484C 2112 1.2V -5 Halogen-Free fpBGA 484 COM
LCMXO2-2000UHE-6FG484C 2112 1.2V -6 Halogen-Free fpBGA 484 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-4000HE-4TG144C 4320 1.2V -4 Halogen-Free TQFP 144 COM
LCMXO2-4000HE-5TG144C 4320 1.2V -5 Halogen-Free TQFP 144 COM
LCMXO2-4000HE-6TG144C 4320 1.2V -6 Halogen-Free TQFP 144 COM
LCMXO2-4000HE-4MG132C 4320 1.2V -4 Halogen-Free csBGA 132 COM
LCMXO2-4000HE-5MG132C 4320 1.2V -5 Halogen-Free csBGA 132 COM
LCMXO2-4000HE-6MG132C 4320 1.2V -6 Halogen-Free csBGA 132 COM
LCMXO2-4000HE-4BG256C 4320 1.2V -4 Halogen-Free caBGA 256 COM
LCMXO2-4000HE-4MG184C 4320 1.2V -4 Halogen-Free csBGA 184 COM
LCMXO2-4000HE-5MG184C 4320 1.2V -5 Halogen-Free csBGA 184 COM
LCMXO2-4000HE-6MG184C 4320 1.2V -6 Halogen-Free csBGA 184 COM
LCMXO2-4000HE-5BG256C 4320 1.2V -5 Halogen-Free caBGA 256 COM
LCMXO2-4000HE-6BG256C 4320 1.2V -6 Halogen-Free caBGA 256 COM
LCMXO2-4000HE-4FTG256C 4320 1.2V -4 Halogen-Free ftBGA 256 COM
LCMXO2-4000HE-5FTG256C 4320 1.2V -5 Halogen-Free ftBGA 256 COM
LCMXO2-4000HE-6FTG256C 4320 1.2V -6 Halogen-Free ftBGA 256 COM
LCMXO2-4000HE-4BG332C 4320 1.2V -4 Halogen-Free caBGA 332 COM
LCMXO2-4000HE-5BG332C 4320 1.2V -5 Halogen-Free caBGA 332 COM
LCMXO2-4000HE-6BG332C 4320 1.2V -6 Halogen-Free caBGA 332 COM5-9
Ordering Information
MachXO2 Family Data Sheet
Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging
LCMXO2-4000HE-4FG484C 4320 1.2V -4 Halogen-Free fpBGA 484 COM
LCMXO2-4000HE-5FG484C 4320 1.2V -5 Halogen-Free fpBGA 484 COM
LCMXO2-4000HE-6FG484C 4320 1.2V -6 Halogen-Free fpBGA 484 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-7000HE-4TG144C 6864 1.2V -4 Halogen-Free TQFP 144 COM
LCMXO2-7000HE-5TG144C 6864 1.2V -5 Halogen-Free TQFP 144 COM
LCMXO2-7000HE-6TG144C 6864 1.2V -6 Halogen-Free TQFP 144 COM
LCMXO2-7000HE-4BG256C 6864 1.2V -4 Halogen-Free caBGA 256 COM
LCMXO2-7000HE-5BG256C 6864 1.2V -5 Halogen-Free caBGA 256 COM
LCMXO2-7000HE-6BG256C 6864 1.2V -6 Halogen-Free caBGA 256 COM
LCMXO2-7000HE-4FTG256C 6864 1.2V -4 Halogen-Free ftBGA 256 COM
LCMXO2-7000HE-5FTG256C 6864 1.2V -5 Halogen-Free ftBGA 256 COM
LCMXO2-7000HE-6FTG256C 6864 1.2V -6 Halogen-Free ftBGA 256 COM
LCMXO2-7000HE-4BG332C 6864 1.2V -4 Halogen-Free caBGA 332 COM
LCMXO2-7000HE-5BG332C 6864 1.2V -5 Halogen-Free caBGA 332 COM
LCMXO2-7000HE-6BG332C 6864 1.2V -6 Halogen-Free caBGA 332 COM
LCMXO2-7000HE-4FG484C 6864 1.2V -4 Halogen-Free fpBGA 484 COM
LCMXO2-7000HE-5FG484C 6864 1.2V -5 Halogen-Free fpBGA 484 COM
LCMXO2-7000HE-6FG484C 6864 1.2V -6 Halogen-Free fpBGA 484 COM
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-256ZE-1SG32I 256 1.2V -1 Halogen-Free QFN 32 IND
LCMXO2-256ZE-2SG32I 256 1.2V -2 Halogen-Free QFN 32 IND
LCMXO2-256ZE-3SG32I 256 1.2V -3 Halogen-Free QFN 32 IND
LCMXO2-256ZE-1UMG64I 256 1.2V -1 Halogen-Free ucBGA 64 IND
LCMXO2-256ZE-2UMG64I 256 1.2V -2 Halogen-Free ucBGA 64 IND
LCMXO2-256ZE-3UMG64I 256 1.2V -3 Halogen-Free ucBGA 64 IND
LCMXO2-256ZE-1TG100I 256 1.2V -1 Halogen-Free TQFP 100 IND
LCMXO2-256ZE-2TG100I 256 1.2V -2 Halogen-Free TQFP 100 IND
LCMXO2-256ZE-3TG100I 256 1.2V -3 Halogen-Free TQFP 100 IND
LCMXO2-256ZE-1MG132I 256 1.2V -1 Halogen-Free csBGA 132 IND
LCMXO2-256ZE-2MG132I 256 1.2V -2 Halogen-Free csBGA 132 IND
LCMXO2-256ZE-3MG132I 256 1.2V -3 Halogen-Free csBGA 132 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-640ZE-1TG100I 640 1.2V -1 Halogen-Free TQFP 100 IND
LCMXO2-640ZE-2TG100I 640 1.2V -2 Halogen-Free TQFP 100 IND
LCMXO2-640ZE-3TG100I 640 1.2V -3 Halogen-Free TQFP 100 IND
LCMXO2-640ZE-1MG132I 640 1.2V -1 Halogen-Free csBGA 132 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.5-10
Ordering Information
MachXO2 Family Data Sheet
LCMXO2-640ZE-2MG132I 640 1.2V -2 Halogen-Free csBGA 132 IND
LCMXO2-640ZE-3MG132I 640 1.2V -3 Halogen-Free csBGA 132 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-4000HE-4MG184I 4320 1.2V -4 Halogen-Free csBGA 184 IND
LCMXO2-4000HE-5MG184I 4320 1.2V -5 Halogen-Free csBGA 184 IND
LCMXO2-4000HE-6MG184I 4320 1.2V -6 Halogen-Free caBGA 184 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.5-11
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200ZE-1UWG25ITR1
1280 1.2V -1 Halogen-Free WLCSP 25 IND
LCMXO2-1200ZE-1UWG25ITR502
1280 1.2V -1 Halogen-Free WLCSP 25 IND
LCMXO2-1200ZE-1TG100I 1280 1.2V -1 Halogen-Free TQFP 100 IND
LCMXO2-1200ZE-2TG100I 1280 1.2V -2 Halogen-Free TQFP 100 IND
LCMXO2-1200ZE-3TG100I 1280 1.2V -3 Halogen-Free TQFP 100 IND
LCMXO2-1200ZE-1MG132I 1280 1.2V -1 Halogen-Free csBGA 132 IND
LCMXO2-1200ZE-2MG132I 1280 1.2V -2 Halogen-Free csBGA 132 IND
LCMXO2-1200ZE-3MG132I 1280 1.2V -3 Halogen-Free csBGA 132 IND
LCMXO2-1200ZE-1TG144I 1280 1.2V -1 Halogen-Free TQFP 144 IND
LCMXO2-1200ZE-2TG144I 1280 1.2V -2 Halogen-Free TQFP 144 IND
LCMXO2-1200ZE-3TG144I 1280 1.2V -3 Halogen-Free TQFP 144 IND
1. This part number has a tape and reel quantity of 5,000 units with a minimum order quantity of 10,000 units. Order quantities must be in
increments of 10,000 units. For example, a 10,000 unit order will be shipped in two reels with one reel containing 5,000 units and the other
reel with less than 5,000 units (depending on test yields). Unserviced backlog will be canceled.
2. This part number has a tape and reel quantity of 50 units with a minimum order quantity of 50. Order quantities must be in increments of 50
units. For example, a 1000 unit order will be shipped as 20 reels of 50 units each.
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000ZE-1TG100I 2112 1.2V -1 Halogen-Free TQFP 100 IND
LCMXO2-2000ZE-2TG100I 2112 1.2V -2 Halogen-Free TQFP 100 IND
LCMXO2-2000ZE-3TG100I 2112 1.2V -3 Halogen-Free TQFP 100 IND
LCMXO2-2000ZE-1MG132I 2112 1.2V -1 Halogen-Free csBGA 132 IND
LCMXO2-2000ZE-2MG132I 2112 1.2V -2 Halogen-Free csBGA 132 IND
LCMXO2-2000ZE-3MG132I 2112 1.2V -3 Halogen-Free csBGA 132 IND
LCMXO2-2000ZE-1TG144I 2112 1.2V -1 Halogen-Free TQFP 144 IND
LCMXO2-2000ZE-2TG144I 2112 1.2V -2 Halogen-Free TQFP 144 IND
LCMXO2-2000ZE-3TG144I 2112 1.2V -3 Halogen-Free TQFP 144 IND
LCMXO2-2000ZE-1BG256I 2112 1.2V -1 Halogen-Free caBGA 256 IND
LCMXO2-2000ZE-2BG256I 2112 1.2V -2 Halogen-Free caBGA 256 IND
LCMXO2-2000ZE-3BG256I 2112 1.2V -3 Halogen-Free caBGA 256 IND
LCMXO2-2000ZE-1FTG256I 2112 1.2V -1 Halogen-Free ftBGA 256 IND
LCMXO2-2000ZE-2FTG256I 2112 1.2V -2 Halogen-Free ftBGA 256 IND
LCMXO2-2000ZE-3FTG256I 2112 1.2V -3 Halogen-Free ftBGA 256 IND
1. Samples can be ordered in minimum order quantities and increments of 50 units. Production volumes can be ordered in minimum order
quantities and increments of 10,000 units for the LCMXO2-1200ZE in the 25-ball WLCSP package.5-12
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-4000ZE-1MG132I 4320 1.2V -1 Halogen-Free csBGA 132 IND
LCMXO2-4000ZE-2MG132I 4320 1.2V -2 Halogen-Free csBGA 132 IND
LCMXO2-4000ZE-3MG132I 4320 1.2V -3 Halogen-Free csBGA 132 IND
LCMXO2-4000ZE-1TG144I 4320 1.2V -1 Halogen-Free TQFP 144 IND
LCMXO2-4000ZE-2TG144I 4320 1.2V -2 Halogen-Free TQFP 144 IND
LCMXO2-4000ZE-3TG144I 4320 1.2V -3 Halogen-Free TQFP 144 IND
LCMXO2-4000ZE-1BG256I 4320 1.2V -1 Halogen-Free caBGA 256 IND
LCMXO2-4000ZE-2BG256I 4320 1.2V -2 Halogen-Free caBGA 256 IND
LCMXO2-4000ZE-3BG256I 4320 1.2V -3 Halogen-Free caBGA 256 IND
LCMXO2-4000ZE-1FTG256I 4320 1.2V -1 Halogen-Free ftBGA 256 IND
LCMXO2-4000ZE-2FTG256I 4320 1.2V -2 Halogen-Free ftBGA 256 IND
LCMXO2-4000ZE-3FTG256I 4320 1.2V -3 Halogen-Free ftBGA 256 IND
LCMXO2-4000ZE-1BG332I 4320 1.2V -1 Halogen-Free caBGA 332 IND
LCMXO2-4000ZE-2BG332I 4320 1.2V -2 Halogen-Free caBGA 332 IND
LCMXO2-4000ZE-3BG332I 4320 1.2V -3 Halogen-Free caBGA 332 IND
LCMXO2-4000ZE-1FG484I 4320 1.2V -1 Halogen-Free fpBGA 484 IND
LCMXO2-4000ZE-2FG484I 4320 1.2V -2 Halogen-Free fpBGA 484 IND
LCMXO2-4000ZE-3FG484I 4320 1.2V -3 Halogen-Free fpBGA 484 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-7000ZE-1TG144I 6864 1.2V -1 Halogen-Free TQFP 144 IND
LCMXO2-7000ZE-2TG144I 6864 1.2V -2 Halogen-Free TQFP 144 IND
LCMXO2-7000ZE-3TG144I 6864 1.2V -3 Halogen-Free TQFP 144 IND
LCMXO2-7000ZE-1BG256I 6864 1.2V -1 Halogen-Free caBGA 256 IND
LCMXO2-7000ZE-2BG256I 6864 1.2V -2 Halogen-Free caBGA 256 IND
LCMXO2-7000ZE-3BG256I 6864 1.2V -3 Halogen-Free caBGA 256 IND
LCMXO2-7000ZE-1FTG256I 6864 1.2V -1 Halogen-Free ftBGA 256 IND
LCMXO2-7000ZE-2FTG256I 6864 1.2V -2 Halogen-Free ftBGA 256 IND
LCMXO2-7000ZE-3FTG256I 6864 1.2V -3 Halogen-Free ftBGA 256 IND
LCMXO2-7000ZE-1BG332I 6864 1.2V -1 Halogen-Free caBGA 332 IND
LCMXO2-7000ZE-2BG332I 6864 1.2V -2 Halogen-Free caBGA 332 IND
LCMXO2-7000ZE-3BG332I 6864 1.2V -3 Halogen-Free caBGA 332 IND
LCMXO2-7000ZE-1FG484I 6864 1.2V -1 Halogen-Free fpBGA 484 IND
LCMXO2-7000ZE-2FG484I 6864 1.2V -2 Halogen-Free fpBGA 484 IND
LCMXO2-7000ZE-3FG484I 6864 1.2V -3 Halogen-Free fpBGA 484 IND5-13
Ordering Information
MachXO2 Family Data Sheet
High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS)
Packaging
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200ZE-1TG100IR11
1280 1.2V -1 Halogen-Free TQFP 100 IND
LCMXO2-1200ZE-2TG100IR11
1280 1.2V -2 Halogen-Free TQFP 100 IND
LCMXO2-1200ZE-3TG100IR11
1280 1.2V -3 Halogen-Free TQFP 100 IND
LCMXO2-1200ZE-1MG132IR11
1280 1.2V -1 Halogen-Free csBGA 132 IND
LCMXO2-1200ZE-2MG132IR11
1280 1.2V -2 Halogen-Free csBGA 132 IND
LCMXO2-1200ZE-3MG132IR11
1280 1.2V -3 Halogen-Free csBGA 132 IND
LCMXO2-1200ZE-1TG144IR11
1280 1.2V -1 Halogen-Free TQFP 144 IND
LCMXO2-1200ZE-2TG144IR11
1280 1.2V -2 Halogen-Free TQFP 144 IND
LCMXO2-1200ZE-3TG144IR11
1280 1.2V -3 Halogen-Free TQFP 144 IND
1. Specifications for the “LCMXO2-1200ZE-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respectively, except as specified in the R1 Device Specifications section on page 5-18 of this data sheet.
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-256HC-4SG32I 256 2.5V/3.3V -4 Halogen-Free QFN 32 IND
LCMXO2-256HC-5SG32I 256 2.5V/3.3V -5 Halogen-Free QFN 32 IND
LCMXO2-256HC-6SG32I 256 2.5V/3.3V -6 Halogen-Free QFN 32 IND
LCMXO2-256HC-4UMG64I 256 2.5V/3.3V -4 Halogen-Free ucBGA 64 IND
LCMXO2-256HC-5UMG64I 256 2.5V/3.3V -5 Halogen-Free ucBGA 64 IND
LCMXO2-256HC-6UMG64I 256 2.5V/3.3V -6 Halogen-Free ucBGA 64 IND
LCMXO2-256HC-4TG100I 256 2.5V/3.3V -4 Halogen-Free TQFP 100 IND
LCMXO2-256HC-5TG100I 256 2.5V/3.3V -5 Halogen-Free TQFP 100 IND
LCMXO2-256HC-6TG100I 256 2.5V/3.3V -6 Halogen-Free TQFP 100 IND
LCMXO2-256HC-4MG132I 256 2.5V/3.3V -4 Halogen-Free csBGA 132 IND
LCMXO2-256HC-5MG132I 256 2.5V/3.3V -5 Halogen-Free csBGA 132 IND
LCMXO2-256HC-6MG132I 256 2.5V/3.3V -6 Halogen-Free csBGA 132 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-640HC-4TG100I 640 2.5V/3.3V -4 Halogen-Free TQFP 100 IND
LCMXO2-640HC-5TG100I 640 2.5V/3.3V -5 Halogen-Free TQFP 100 IND
LCMXO2-640HC-6TG100I 640 2.5V/3.3V -6 Halogen-Free TQFP 100 IND
LCMXO2-640HC-4MG132I 640 2.5V/3.3V -4 Halogen-Free csBGA 132 IND
LCMXO2-640HC-5MG132I 640 2.5V/3.3V -5 Halogen-Free csBGA 132 IND
LCMXO2-640HC-6MG132I 640 2.5V/3.3V -6 Halogen-Free csBGA 132 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-640UHC-4TG144I 640 2.5V/3.3V -4 Halogen-Free TQFP 144 IND
LCMXO2-640UHC-5TG144I 640 2.5V/3.3V -5 Halogen-Free TQFP 144 IND
LCMXO2-640UHC-6TG144I 640 2.5V/3.3V -6 Halogen-Free TQFP 144 IND5-14
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200HC-4TG100I 1280 2.5V/3.3V -4 Halogen-Free TQFP 100 IND
LCMXO2-1200HC-5TG100I 1280 2.5V/3.3V -5 Halogen-Free TQFP 100 IND
LCMXO2-1200HC-6TG100I 1280 2.5V/3.3V -6 Halogen-Free TQFP 100 IND
LCMXO2-1200HC-4MG132I 1280 2.5V/3.3V -4 Halogen-Free csBGA 132 IND
LCMXO2-1200HC-5MG132I 1280 2.5V/3.3V -5 Halogen-Free csBGA 132 IND
LCMXO2-1200HC-6MG132I 1280 2.5V/3.3V -6 Halogen-Free csBGA 132 IND
LCMXO2-1200HC-4TG144I 1280 2.5V/3.3V -4 Halogen-Free TQFP 144 IND
LCMXO2-1200HC-5TG144I 1280 2.5V/3.3V -5 Halogen-Free TQFP 144 IND
LCMXO2-1200HC-6TG144I 1280 2.5V/3.3V -6 Halogen-Free TQFP 144 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200UHC-4FTG256I 1280 2.5V/3.3V -4 Halogen-Free ftBGA 256 IND
LCMXO2-1200UHC-5FTG256I 1280 2.5V/3.3V -5 Halogen-Free ftBGA 256 IND
LCMXO2-1200UHC-6FTG256I 1280 2.5V/3.3V -6 Halogen-Free ftBGA 256 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000HC-4TG100I 2112 2.5V/3.3V -4 Halogen-Free TQFP 100 IND
LCMXO2-2000HC-5TG100I 2112 2.5V/3.3V -5 Halogen-Free TQFP 100 IND
LCMXO2-2000HC-6TG100I 2112 2.5V/3.3V -6 Halogen-Free TQFP 100 IND
LCMXO2-2000HC-4MG132I 2112 2.5V/3.3V -4 Halogen-Free csBGA 132 IND
LCMXO2-2000HC-5MG132I 2112 2.5V/3.3V -5 Halogen-Free csBGA 132 IND
LCMXO2-2000HC-6MG132I 2112 2.5V/3.3V -6 Halogen-Free csBGA 132 IND
LCMXO2-2000HC-4TG144I 2112 2.5V/3.3V -4 Halogen-Free TQFP 144 IND
LCMXO2-2000HC-5TG144I 2112 2.5V/3.3V -5 Halogen-Free TQFP 144 IND
LCMXO2-2000HC-6TG144I 2112 2.5V/3.3V -6 Halogen-Free TQFP 144 IND
LCMXO2-2000HC-4BG256I 2112 2.5V/3.3V -4 Halogen-Free caBGA 256 IND
LCMXO2-2000HC-5BG256I 2112 2.5V/3.3V -5 Halogen-Free caBGA 256 IND
LCMXO2-2000HC-6BG256I 2112 2.5V/3.3V -6 Halogen-Free caBGA 256 IND
LCMXO2-2000HC-4FTG256I 2112 2.5V/3.3V -4 Halogen-Free ftBGA 256 IND
LCMXO2-2000HC-5FTG256I 2112 2.5V/3.3V -5 Halogen-Free ftBGA 256 IND
LCMXO2-2000HC-6FTG256I 2112 2.5V/3.3V -6 Halogen-Free ftBGA 256 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000UHC-4FG484I 2112 2.5V/3.3V -4 Halogen-Free fpBGA 484 IND
LCMXO2-2000UHC-5FG484I 2112 2.5V/3.3V -5 Halogen-Free fpBGA 484 IND
LCMXO2-2000UHC-6FG484I 2112 2.5V/3.3V -6 Halogen-Free fpBGA 484 IND5-15
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-4000HC-4TG144I 4320 2.5V/3.3V -4 Halogen-Free TQFP 144 IND
LCMXO2-4000HC-5TG144I 4320 2.5V/3.3V -5 Halogen-Free TQFP 144 IND
LCMXO2-4000HC-6TG144I 4320 2.5V/3.3V -6 Halogen-Free TQFP 144 IND
LCMXO2-4000HC-4MG132I 4320 2.5V/3.3V -4 Halogen-Free csBGA 132 IND
LCMXO2-4000HC-5MG132I 4320 2.5V/3.3V -5 Halogen-Free csBGA 132 IND
LCMXO2-4000HC-6MG132I 4320 2.5V/3.3V -6 Halogen-Free csBGA 132 IND
LCMXO2-4000HC-4BG256I 4320 2.5V/3.3V -4 Halogen-Free caBGA 256 IND
LCMXO2-4000HC-5BG256I 4320 2.5V/3.3V -5 Halogen-Free caBGA 256 IND
LCMXO2-4000HC-6BG256I 4320 2.5V/3.3V -6 Halogen-Free caBGA 256 IND
LCMXO2-4000HC-4FTG256I 4320 2.5V/3.3V -4 Halogen-Free ftBGA 256 IND
LCMXO2-4000HC-5FTG256I 4320 2.5V/3.3V -5 Halogen-Free ftBGA 256 IND
LCMXO2-4000HC-6FTG256I 4320 2.5V/3.3V -6 Halogen-Free ftBGA 256 IND
LCMXO2-4000HC-4BG332I 4320 2.5V/3.3V -4 Halogen-Free caBGA 332 IND
LCMXO2-4000HC-5BG332I 4320 2.5V/3.3V -5 Halogen-Free caBGA 332 IND
LCMXO2-4000HC-6BG332I 4320 2.5V/3.3V -6 Halogen-Free caBGA 332 IND
LCMXO2-4000HC-4FG484I 4320 2.5V/3.3V -4 Halogen-Free fpBGA 484 IND
LCMXO2-4000HC-5FG484I 4320 2.5V/3.3V -5 Halogen-Free fpBGA 484 IND
LCMXO2-4000HC-6FG484I 4320 2.5V/3.3V -6 Halogen-Free fpBGA 484 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-7000HC-4TG144I 6864 2.5V/3.3V -4 Halogen-Free TQFP 144 IND
LCMXO2-7000HC-5TG144I 6864 2.5V/3.3V -5 Halogen-Free TQFP 144 IND
LCMXO2-7000HC-6TG144I 6864 2.5V/3.3V -6 Halogen-Free TQFP 144 IND
LCMXO2-7000HC-4BG256I 6864 2.5V/3.3V -4 Halogen-Free caBGA 256 IND
LCMXO2-7000HC-5BG256I 6864 2.5V/3.3V -5 Halogen-Free caBGA 256 IND
LCMXO2-7000HC-6BG256I 6864 2.5V/3.3V -6 Halogen-Free caBGA 256 IND
LCMXO2-7000HC-4FTG256I 6864 2.5V/3.3V -4 Halogen-Free ftBGA 256 IND
LCMXO2-7000HC-5FTG256I 6864 2.5V/3.3V -5 Halogen-Free ftBGA 256 IND
LCMXO2-7000HC-6FTG256I 6864 2.5V/3.3V -6 Halogen-Free ftBGA 256 IND
LCMXO2-7000HC-4BG332I 6864 2.5V/3.3V -4 Halogen-Free caBGA 332 IND
LCMXO2-7000HC-5BG332I 6864 2.5V/3.3V -5 Halogen-Free caBGA 332 IND
LCMXO2-7000HC-6BG332I 6864 2.5V/3.3V -6 Halogen-Free caBGA 332 IND
LCMXO2-7000HC-4FG484I 6864 2.5V/3.3V -4 Halogen-Free fpBGA 484 IND
LCMXO2-7000HC-5FG484I 6864 2.5V/3.3V -5 Halogen-Free fpBGA 484 IND
LCMXO2-7000HC-6FG484I 6864 2.5V/3.3V -6 Halogen-Free fpBGA 484 IND5-16
Ordering Information
MachXO2 Family Data Sheet
High Performance Industrial Grade Devices Without Voltage Regulator, Halogen Free
(RoHS) Packaging
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-1200HC-4TG100IR11
1280 2.5V/3.3V -4 Halogen-Free TQFP 100 IND
LCMXO2-1200HC-5TG100IR11
1280 2.5V/3.3V -5 Halogen-Free TQFP 100 IND
LCMXO2-1200HC-6TG100IR11
1280 2.5V/3.3V -6 Halogen-Free TQFP 100 IND
LCMXO2-1200HC-4MG132IR11
1280 2.5V/3.3V -4 Halogen-Free csBGA 132 IND
LCMXO2-1200HC-5MG132IR11
1280 2.5V/3.3V -5 Halogen-Free csBGA 132 IND
LCMXO2-1200HC-6MG132IR11
1280 2.5V/3.3V -6 Halogen-Free csBGA 132 IND
LCMXO2-1200HC-4TG144IR11
1280 2.5V/3.3V -4 Halogen-Free TQFP 144 IND
LCMXO2-1200HC-5TG144IR11
1280 2.5V/3.3V -5 Halogen-Free TQFP 144 IND
LCMXO2-1200HC-6TG144IR11
1280 2.5V/3.3V -6 Halogen-Free TQFP 144 IND
1. Specifications for the “LCMXO2-1200HC-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respectively, except as specified in the R1 Device Specifications section on page 5-18 of this data sheet.
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000HE-4TG100I 2112 1.2V -4 Halogen-Free TQFP 100 IND
LCMXO2-2000HE-5TG100I 2112 1.2V -5 Halogen-Free TQFP 100 IND
LCMXO2-2000HE-6TG100I 2112 1.2V -6 Halogen-Free TQFP 100 IND
LCMXO2-2000HE-4MG132I 2112 1.2V -4 Halogen-Free csBGA 132 IND
LCMXO2-2000HE-5MG132I 2112 1.2V -5 Halogen-Free csBGA 132 IND
LCMXO2-2000HE-6MG132I 2112 1.2V -6 Halogen-Free csBGA 132 IND
LCMXO2-2000HE-4TG144I 2112 1.2V -4 Halogen-Free TQFP 144 IND
LCMXO2-2000HE-5TG144I 2112 1.2V -5 Halogen-Free TQFP 144 IND
LCMXO2-2000HE-6TG144I 2112 1.2V -6 Halogen-Free TQFP 144 IND
LCMXO2-2000HE-4BG256I 2112 1.2V -4 Halogen-Free caBGA 256 IND
LCMXO2-2000HE-5BG256I 2112 1.2V -5 Halogen-Free caBGA 256 IND
LCMXO2-2000HE-6BG256I 2112 1.2V -6 Halogen-Free caBGA 256 IND
LCMXO2-2000HE-4FTG256I 2112 1.2V -4 Halogen-Free ftBGA 256 IND
LCMXO2-2000HE-5FTG256I 2112 1.2V -5 Halogen-Free ftBGA 256 IND
LCMXO2-2000HE-6FTG256I 2112 1.2V -6 Halogen-Free ftBGA 256 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-2000UHE-4FG484I 2112 1.2V -4 Halogen-Free fpBGA 484 IND
LCMXO2-2000UHE-5FG484I 2112 1.2V -5 Halogen-Free fpBGA 484 IND
LCMXO2-2000UHE-6FG484I 2112 1.2V -6 Halogen-Free fpBGA 484 IND5-17
Ordering Information
MachXO2 Family Data Sheet
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-4000HE-4MG132I 4320 1.2V -4 Halogen-Free csBGA 132 IND
LCMXO2-4000HE-5MG132I 4320 1.2V -5 Halogen-Free csBGA 132 IND
LCMXO2-4000HE-6MG132I 4320 1.2V -6 Halogen-Free csBGA 132 IND
LCMXO2-4000HE-4TG144I 4320 1.2V -4 Halogen-Free TQFP 144 IND
LCMXO2-4000HE-5TG144I 4320 1.2V -5 Halogen-Free TQFP 144 IND
LCMXO2-4000HE-6TG144I 4320 1.2V -6 Halogen-Free TQFP 144 IND
LCMXO2-4000HE-4BG256I 4320 1.2V -4 Halogen-Free caBGA 256 IND
LCMXO2-4000HE-5BG256I 4320 1.2V -5 Halogen-Free caBGA 256 IND
LCMXO2-4000HE-6BG256I 4320 1.2V -6 Halogen-Free caBGA 256 IND
LCMXO2-4000HE-4FTG256I 4320 1.2V -4 Halogen-Free ftBGA 256 IND
LCMXO2-4000HE-5FTG256I 4320 1.2V -5 Halogen-Free ftBGA 256 IND
LCMXO2-4000HE-6FTG256I 4320 1.2V -6 Halogen-Free ftBGA 256 IND
LCMXO2-4000HE-4BG332I 4320 1.2V -4 Halogen-Free caBGA 332 IND
LCMXO2-4000HE-5BG332I 4320 1.2V -5 Halogen-Free caBGA 332 IND
LCMXO2-4000HE-6BG332I 4320 1.2V -6 Halogen-Free caBGA 332 IND
LCMXO2-4000HE-4FG484I 4320 1.2V -4 Halogen-Free fpBGA 484 IND
LCMXO2-4000HE-5FG484I 4320 1.2V -5 Halogen-Free fpBGA 484 IND
LCMXO2-4000HE-6FG484I 4320 1.2V -6 Halogen-Free fpBGA 484 IND
Part Number LUTs Supply Voltage Grade Package Leads Temp.
LCMXO2-7000HE-4TG144I 6864 1.2V -4 Halogen-Free TQFP 144 IND
LCMXO2-7000HE-5TG144I 6864 1.2V -5 Halogen-Free TQFP 144 IND
LCMXO2-7000HE-6TG144I 6864 1.2V -6 Halogen-Free TQFP 144 IND
LCMXO2-7000HE-4BG256I 6864 1.2V -4 Halogen-Free caBGA 256 IND
LCMXO2-7000HE-5BG256I 6864 1.2V -5 Halogen-Free caBGA 256 IND
LCMXO2-7000HE-6BG256I 6864 1.2V -6 Halogen-Free caBGA 256 IND
LCMXO2-7000HE-4FTG256I 6864 1.2V -4 Halogen-Free ftBGA 256 IND
LCMXO2-7000HE-5FTG256I 6864 1.2V -5 Halogen-Free ftBGA 256 IND
LCMXO2-7000HE-6FTG256I 6864 1.2V -6 Halogen-Free ftBGA 256 IND
LCMXO2-7000HE-4BG332I 6864 1.2V -4 Halogen-Free caBGA 332 IND
LCMXO2-7000HE-5BG332I 6864 1.2V -5 Halogen-Free caBGA 332 IND
LCMXO2-7000HE-6BG332I 6864 1.2V -6 Halogen-Free caBGA 332 IND
LCMXO2-7000HE-4FG484I 6864 1.2V -4 Halogen-Free fpBGA 484 IND
LCMXO2-7000HE-5FG484I 6864 1.2V -5 Halogen-Free fpBGA 484 IND
LCMXO2-7000HE-6FG484I 6864 1.2V -6 Halogen-Free fpBGA 484 IND5-18
Ordering Information
MachXO2 Family Data Sheet
R1 Device Specifications
The LCMXO2-1200ZE/HC “R1” devices have the same specifications as their Standard (non-R1) counterparts
except as listed below. For more details on the R1 to Standard migration refer to AN8086, Designing for Migration
from MachXO2-1200-R1 to Standard Non-R1) Devices.
• The User Flash Memory (UFM) cannot be programmed through the internal WISHBONE interface. It can still be
programmed through the JTAG/SPI/I2
C ports.
• The on-chip differential input termination resistor value is higher than intended. It is approximately 200 as
opposed to the intended 100. It is recommended to use external termination resistors for differential inputs. The
on-chip termination resistors can be disabled through Lattice design software.
• Soft Error Detection logic may not produce the correct result when it is run for the first time after configuration. To
use this feature, discard the result from the first operation. Subsequent operations will produce the correct result.
• Under certain conditions, IIH exceeds data sheet specifications. The following table provides more details:
• The user SPI interface does not operate correctly in some situations. During master read access and slave write
access, the last byte received does not generate the RRDY interrupt.
• In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch in the output under certain conditions, leading to possible loss of synchronization.
• When using the hard I2
C IP core, the I2
C status registers I2C_1_SR and I2C_2_SR may not update correctly.
• PLL Lock signal will glitch high when coming out of standby. This glitch lasts for about 10µsec before returning
low.
• Dual boot only available on HC devices, requires tying VCC and VCCIO2 to the same 3.3V or 2.5V supply.
Condition Clamp
Pad Rising
IIH Max.
Pad Falling
IIH Min.
Steady State Pad
High IIH
Steady State Pad
Low IIL
VPAD > VCCIO OFF 1mA -1mA 1mA 10µA
VPAD = VCCIO ON 10µA -10µA 10µA 10µA
VPAD = VCCIO OFF 1mA -1mA 1mA 10µA
VPAD < VCCIO OFF 10µA -10µA 10µA 10µAApril 2012 Data Sheet DS1035
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 6-1 DS1035 Further Info_01.3
For Further Information
A variety of technical notes for the MachXO2 family are available on the Lattice web site.
• TN1198, Power Estimation and Management for MachXO2 Devices
• TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide
• TN1201, Memory Usage Guide for MachXO2 Devices
• TN1202, MachXO2 sysIO Usage Guide
• TN1203, Implementing High-Speed Interfaces with MachXO2 Devices
• TN1204, MachXO2 Programming and Configuration Usage Guide
• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
• TN1206, MachXO2 SRAM CRC Error Detection Usage Guide
• TN1207, Using TraceID in MachXO2 Devices
• TN1074, PCB Layout Recommendations for BGA Packages
• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology
• AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (non-R1) Devices
• AN8066, Boundary Scan Testability with Lattice sysIO Capability
• MachXO2 Device Pinout Files
• Thermal Management document
• Lattice design tools
For further information on interface standards, refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, LVDS, DDR, DDR2, LPDDR): www.jedec.org
• PCI: www.pcisig.com
MachXO2 Family Data Sheet
Supplemental InformationJanuary 2013 Data Sheet DS1035
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 7-1 DS1035 Revision History
Date Version Section Change Summary
November 2010 01.0 — Initial release.
January 2011 01.1 All Included ultra-high I/O devices.
DC and Switching
Characteristics
Recommended Operating Conditions table – Added footnote 3.
DC Electrical Characteristics table – Updated data for IIL, IIH. VHYST typical values updated.
Generic DDRX2 Outputs with Clock and Data Aligned at Pin
(GDDRX2_TX.ECLK.Aligned) Using PCLK Pin for Clock Input tables –
Updated data for TDIA and TDIB.
Generic DDRX4 Outputs with Clock and Data Aligned at Pin
(GDDRX4_TX.ECLK.Aligned) Using PCLK Pin for Clock Input tables –
Updated data for TDIA and TDIB.
Power-On-Reset Voltage Levels table - clarified note 3.
Clarified VCCIO related recommended operating conditions specifications.
Added power supply ramp rate requirements.
Added Power Supply Ramp Rates table.
Updated Programming/Erase Specifications table.
Removed references to VCCP.
Pinout Information Included number of 7:1 and 8:1 gearboxes (input and output) in the pin
information summary tables.
Removed references to VCCP.
April 2011 01.2 — Data sheet status changed from Advance to Preliminary.
Introduction Updated MachXO2 Family Selection Guide table.
Architecture Updated Supported Input Standards table.
Updated sysMEM Memory Primitives diagram.
Added differential SSTL and HSTL IO standards.
DC and Switching
Characteristics
Updates following parameters: POR voltage levels, DC electrical characteristics, static supply current for ZE/HE/HC devices, static power
consumption contribution of different components – ZE devices, programming and erase Flash supply current.
Added VREF specifications to sysIO recommended operating conditions.
Updating timing information based on characterization.
Added differential SSTL and HSTL IO standards.
Ordering Information Added Ordering Part Numbers for R1 devices, and devices in WLCSP
packages.
Added R1 device specifications.
May 2011 01.3 Multiple Replaced “SED” with “SRAM CRC Error Detection” throughout the document.
DC and Switching
Characteristics
Added footnote 1 to Program Erase Specifications table.
Pinout Information Updated Pin Information Summary tables.
Signal name SO/SISPISO changed to SO/SPISO in the Signal Descriptions table.
MachXO2 Family Data Sheet
Revision History7-2
Revision History
MachXO2 Family Data Sheet
August 2011 01.4 Architecture Updated information in Clock/Control Distribution Network and sysCLOCK Phase Locked Loops (PLLs).
DC and Switching
Characteristics
Updated IIL and IIH conditions in the DC Electrical Characteristics table.
Pinout Information Included number of 7:1 and 8:1 gearboxes (input and output) in the pin
information summary tables.
Updated Pin Information Summary table: Dual Function I/O, DQS
Groups Bank 1, Total General Purpose Single-Ended I/O, Differential
I/O Per Bank, Total Count of Bonded Pins, Gearboxes.
Added column of data for MachXO2-2000 49 WLCSP.
Ordering Information Updated R1 Device Specifications text section with information on
migration from MachXO2-1200-R1 to Standard (non-R1) devices.
Corrected Supply Voltage typo for part numbers: LCMX02-2000UHE-
4FG484I, LCMX02-2000UHE-5FG484I, LCMX02-2000UHE-6FG484I.
Added footnote for WLCSP package parts.
Supplemental
Information
Removed reference to Stand-alone Power Calculator for MachXO2
Devices. Added reference to AN8086, Designing for Migration from
MachXO2-1200-R1 to Standard (non-R1) Devices.
August 2011 01.5 DC and Switching
Characteristics
Updated ESD information.
Ordering Information Updated footnote for ordering WLCSP devices.
February 2012 01.6 — Data sheet status changed from preliminary to final.
Introduction MachXO2 Family Selection Guide table – Removed references to
49-ball WLCSP.
DC and Switching
Characteristics
Updated Flash Download Time table.
Modified Storage Temperature in the Absolute Maximum Ratings section.
Updated IDK max in Hot Socket Specifications table.
Modified Static Supply Current tables for ZE and HC/HE devices.
Updated Power Supply Ramp Rates table.
Updated Programming and Erase Supply Current tables.
Updated data in the External Switching Characteristics table.
Corrected Absolute Maximum Ratings for Dedicated Input Voltage
Applied for LCMXO2 HC.
DC Electrical Characteristics table – Minor corrections to conditions for
I
IL, IIH.
Pinout Information Removed references to 49-ball WLCSP.
Signal Descriptions table – Updated description for GND, VCC, and
VCCIOx.
Updated Pin Information Summary table – Number of VCCIOs, GNDs,
VCCs, and Total Count of Bonded Pins for MachXO2-256, 640, and
640U and Dual Function I/O for MachXO2-4000 332caBGA.
Ordering Information Removed references to 49-ball WLCSP
February 2012 01.7 All Updated document with new corporate logo.
March 2012 01.8 Introduction Added 32 QFN packaging information to Features bullets and MachXO2
Family Selection Guide table.
DC and Switching
Characteristics
Changed ‘STANDBY’ to ‘USERSTDBY’ in Standby Mode timing diagram.
Pinout Information Removed footnote from Pin Information Summary tables.
Date Version Section Change Summary7-3
Revision History
MachXO2 Family Data Sheet
March 2012
(cont.)
01.8
(cont.)
Pinout Information
(cont.)
Added 32 QFN package to Pin Information Summary table.
Ordering Information Updated Part Number Description and Ordering Information tables for
32 QFN package.
Updated topside mark diagram in the Ordering Information section.
April 2012 01.9 Architecture Removed references to TN1200.
Ordering Information Updated the Device Status portion of the MachXO2 Part Number
Description to include the 50 parts per reel for the WLCSP package.
Added new part number and footnote 2 for LCMXO2-1200ZE-
1UWG25ITR50.
Updated footnote 1 for LCMXO2-1200ZE-1UWG25ITR.
Supplemental
Information
Removed references to TN1200.
January 2013 02.0 Introduction Updated the total number IOs to include JTAGENB.
Architecture Supported Output Standards table – Added 3.3 VCCIO (Typ.) to LVDS
row.
Changed SRAM CRC Error Detection to Soft Error Detection.
DC and Switching
Characteristics
Power Supply Ramp Rates table – Updated Units column for tRAMP
symbol.
Added new Maximum sysIO Buffer Performance table.
sysCLOCK PLL Timing table – Updated Min. column values for fIN, fOUT,
f
OUT2 and fPFD parameters. Added tSPO parameter. Updated footnote 6.
MachXO2 Oscillator Output Frequency table – Updated symbol name
for tSTABLEOSC.
DC Electrical Characteristics table – Updated conditions for IIL, IIH symbols.
Corrected parameters tDQVBS and tDQVAS
Corrected MachXO2 ZE parameters tDVADQ and tDVEDQ
Pinout Information Included the MachXO2-4000HE 184 csBGA package.
Ordering Information Updated part number.
Date Version Section Change Summary
Page 1
Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE
Copyright 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation and Lattice (design) are either registered trademarks or trademarks of Lattice Semiconductor
Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies.
PCN# Issue Date Description
05A-12 February 27, 2012 Initial release
05B-12 February 25, 2013 Removing the Shipping Box/Label Change (2b) The return address on all
boxes will now be Lattice Singapore Pte. Ltd.
February 25, 2013
Subject: PCN# 05B-12 Notification of Change in Lattice Logo affecting Device Topside Mark and
Shipping Box/Label Design
Dear Lattice Customer,
Lattice is providing this notification of our intent to change the Lattice logo. The logo change is part of a
rebranding effort at Lattice and will result in changes to topside marking on most devices as well as changes to
all shipping boxes/labels. The conversion to the new device topside mark, shipping boxes/labels will be a gradual
transition until existing inventories have been exhausted. Shown below are images of current and new Lattice
logos.
A description of each of the changes follows:
1. Device Topside Marking: The device topside marking on most Lattice products will now carry the new
Lattice logo in one of the formats listed below depending on package size constraints. A list of all current
logo formats and corresponding new logo formats can be found in Exhibit “A”. Custom device topside
marks which utilize the current Lattice logo will also transition to the new logo. A comparison of device
topside marks using the current and new logos in the full and short formats are shown below.
Full Form Logo Device Topside Mark Example
LCMXO2-7000ZE
1FG484I
DATECODE
LCMXO2-7000ZE
1FG484I
DATECODE
Current Logo on Device Topside
Mark
New Logo on Device Topside
Mark
PCN#05B-12 issued on February 25, 2013 will supersede
PCN#05A-12 issued on February 27, 2012. Page 2
Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE
Copyright 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation and Lattice (design) are either registered trademarks or trademarks of Lattice Semiconductor
Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies.
Short Form Logo Device Topside Mark Eaxmple
2. Shipping Box/Label Changes:
a. The color of the shipping boxes will change from white to brown and carry the new logo
b. A patent statement will be added
c. Elimination of phrases such as “Silicon Forest”, “ISP Products” and “LSC Products”
d. All standard Lattice labels will incorporate the new logo
Physical dimensions and properties of the boxes are unchanged. Shown below are the current and new logos in
the full and short forms as they would appear on shipping boxes/labels.
Logo Format Current Logo New Logo
Full Form
Short Form
TIMING
This change is effective immediately. As mentioned earlier, specific conversions will be a function of existing
inventories.
RESPONSE
No response is required.
Lattice PCNs are available on the Lattice website. Please sign up to receive e-mail PCN alerts by registering
here. If you already have a Lattice web account and wish to receive PCN alerts, you can do so by logging into
your account and making edits to your subscription options.
New Logo on Device Topside
Mark
Current Logo on Device Topside
Mark
LC4032ZE
5MN-7I
DATECODE
LC4032ZE
5MN-7I
DATECODEPage 3
Lattice Semiconductor Home Page: http://www.latticesemi.com Applications & Literature Hotline: 1-800-LATTICE
Copyright 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L(stylized) Lattice Semiconductor Corporation and Lattice (design) are either registered trademarks or trademarks of Lattice Semiconductor
Corporation in the United States and/or other countries. Other product names used in this publications are for identification purposes only and may be the trademarks of their respective companies.
CONTACT
If you have any questions or require additional information, please contact pcn@latticesemi.com.
Sincerely,
Lattice Semiconductor PCN Administration Page 4
EXHIBIT “A” – CURRENT AND NEW LOGO FORMATS
Current Logo Format New Logo FormatPage 5
Current Logo Format New Logo Format
No change No change
5555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347
Internet: http:///www.latticesemi.com
Rev. Q
March 7, 2013
Registration, Evaluation, Authorisation and Restriction of Chemicals (REACH)
REACH is a European Community Regulation on chemicals and their safe use (EC 1907/2006).
It deals with the Registration, Evaluation, Authorisation and Restriction of CHemical
substances. The law entered into force on 1 June 2007. The aim of REACH is to improve the
protection of human health and the environment through the better and earlier identification of
the intrinsic properties of chemical substances. More information may be found at
http://ec.europa.eu/environment/chemicals/reach/reach_intro.htm.
Lattice is a supplier of “articles” as defined in REACH. The “substances” contained in these
articles are not intentionally released, nor do the articles contain any of the substances on the
updated SVHC Candidate List of 138 substances published on December 19, 2012:
# Substance Name CAS # SVHC
Published Date
1 4,4'- Diaminodiphenylmethane (MDA) 101-77-9 10/28/2008
2 5-tert-butyl-2,4,6-trinitro-m-xylene (musk
xylene) 81-15-2 10/28/2008
3 Alkanes, C10-13, chloro (Short Chain
Chlorinated Paraffins) 85535-84-8 10/28/2008
4 Anthracene 120-12-7 10/28/2008
5 Benzyl butyl phthalate (BBP) 85-68-7 10/28/2008
6 Bis (2-ethylhexyl)phthalate (DEHP) 117-81-7 10/28/2008
7 Bis(tributyltin)oxide (TBTO) 56-35-9 10/28/2008
8 Cobalt dichloride 7646-79-9
10/28/2008
6/20/2011
9 Diarsenic pentaoxide 1303-28-2 10/28/2008
10 Diarsenic trioxide 1327-53-3 10/28/2008
11 Dibutyl phthalate (DBP) 84-74-2 10/28/2008
12
Hexabromocyclododecane (HBCDD) and all
major diastereoisomers identified: 25637-99-4
10/28/2008
Alpha-hexabromocyclododecane 3194-55-6
Beta-hexabromocyclododecane (134237-50-6)
Gamma-hexabromocyclododecane (134237-51-7)
(134237-52-8)
13 Lead hydrogen arsenate 7784-40-9 10/28/2008
14 Sodium dichromate
7789-12-0
10/28/2008
10588-01-9
15 Triethyl arsenate 15606-95-8 10/28/2008
16 2,4-Dinitrotoluene 121-14-2 1/13/20105555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347
Internet: http:///www.latticesemi.com
Rev. Q
17 Anthracene oil 90640-80-5 1/13/2010
18 Anthracene oil, anthracene paste 90640-81-6 1/13/2010
19 Anthracene oil, anthracene paste, anthracene
fraction 91995-15-2 1/13/2010
20 Anthracene oil, anthracene paste,distn. lights 91995-17-4 1/13/2010
21 Anthracene oil, anthracene-low 90640-82-7 1/13/2010
22 Diisobutyl phthalate 84-69-5 1/13/2010
23 Lead chromate 7758-97-6 1/13/2010
24 Lead chromate molybdate sulphate red (C.I.
Pigment Red 104) 12656-85-8 1/13/2010
25 Lead sulfochromate yellow (C.I. Pigment
Yellow 34) 1344-37-2 1/13/2010
26 Pitch, coal tar, high temp. 65996-93-2 1/13/2010
27 Tris(2-chloroethyl)phosphate 115-96-8 1/13/2010
28 Acrylamide 79-06-1 3/30/2010
29 Ammonium dichromate 7789-09-5 6/18/2010
30 Boric acid
10043-35-3
6/18/2010
11113-50-1
31 Disodium tetraborate, anhydrous
1303-96-4
1330-43-4 6/18/2010
12179-04-3
32 Potassium chromate 7789-00-6 6/18/2010
33 Potassium dichromate 7778-50-9 6/18/2010
34 Sodium chromate 7775-11-3 6/18/2010
35 Tetraboron disodium heptaoxide, hydrate 12267-73-1 6/18/2010
36 Trichloroethylene 79-01-6 6/18/2010
37 2-Ethoxyethanol 110-80-5 12/15/2010
38 2-Methoxyethanol 109-86-4 12/15/2010
39
Chromic acid, 7738-94-5
Oligomers of chromic acid and dichromic acid, - 12/15/2010
Dichromic acid 13530-68-2
40 Chromium trioxide 1333-82-0 12/15/2010
41 Cobalt(II) carbonate 513-79-1 12/15/2010
42 Cobalt(II) diacetate 71-48-7 12/15/2010
43 Cobalt(II) dinitrate 10141-05-6 12/15/2010
44 Cobalt(II) sulphate 10124-43-3 12/15/2010
45 1,2,3-Trichloropropane 96-18-4 6/20/2011
46 1,2-Benzenedicarboxylic acid, di-C6-8-branched
alkyl esters, C7-rich 71888-89-6 6/20/2011
47 1,2-Benzenedicarboxylic acid, di-C7-11-
branched and linear alkyl esters 68515-42-4 6/20/20115555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347
Internet: http:///www.latticesemi.com
Rev. Q
48 1-Methyl-2-pyrrolidone 872-50-4 6/20/2011
49 2-Ethoxyethyl acetate 111-15-9 6/20/2011
50 Hydrazine
302-01-2
6/20/2011
7803-57-8
51 Strontium chromate 7789-06-2 6/20/2011
52 Dichromium tris(chromate) 24613-89-6 12/19/2011
53 Potassium hydroxyoctaoxodizincatedi-chromate 11103-86-9 12/19/2011
54 Pentazinc chromate octahydroxide 49663-84-5 12/19/2011
55 Aluminosilicate Refractory Ceramic Fibres
(RCF) - 12/19/2011
56 Zirconia Aluminosilicate Refractory Ceramic
Fibres (Zr-RCF) - 12/19/2011
57 Formaldehyde, oligomeric reaction products
with aniline (technical MDA) 25214-70-4 12/19/2011
58 Bis(2-methoxyethyl) phthalate 117-82-8 12/19/2011
59 2-Methoxyaniline; o-Anisidine 90-04-0 12/19/2011
60 4-(1,1,3,3-tetramethyl butyl)phenol, (4-tertOctylphenol) 140-66-9 12/19/2011
61 1,2-Dichloroethane 107-06-2 12/19/2011
62 Bis(2-methoxyethyl) ether 111-96-6 12/19/2011
63 Arsenic acid 7778-39-4 12/19/2011
64 Calcium arsenate 7778-44-1 12/19/2011
65 Trilead diarsenate 3687-31-8 12/19/2011
66 N,N-dimethylacetamide (DMAC) 127-19-5 12/19/2011
67 2,2'-dichloro-4,4'-methylenedianiline (MOCA) 101-14-4 12/19/2011
68 Phenolphthalein 77-09-8 12/19/2011
69 Lead azide, Lead diazide 13424-46-9 12/19/2011
70 Lead styphnate 15245-44-0 12/19/2011
71 Lead dipicrate 6477-64-1 12/19/2011
72
α,α-Bis[4-(dimethylamino)phenyl]-4
(phenylamino)naphthalene-1-methanol 6786-83-0 6/18/2012
(C.I. Solvent Blue 4)
73 N,N,N',N'-tetramethyl-4,4'-methylenedianiline
(Michler's base) 101-61-1 6/18/2012
74
β-TGIC (1,3,5-tris[(2S and 2R)-2,3-
epoxypropyl]-1,3,5-triazine-2,4,6-(1H,3H,5H)-
trione)
59653-74-6 6/18/2012
75 Diboron trioxide 1303-86-2 6/18/2012
76 1,2-bis(2-methoxyethoxy)ethane (TEGDME;
triglyme) 112-49-2 6/18/2012
77 4,4'-bis(dimethylamino)-4''-(methylamino)trityl
alcohol 561-41-1 6/18/20125555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347
Internet: http:///www.latticesemi.com
Rev. Q
78 Lead(II) bis(methanesulfonate) 17570-76-2 6/18/2012
79 Formamide 75-12-7 6/18/2012
80
[4-[4,4'-bis(dimethylamino)
benzhydrylidene]cyclohexa-2,5-dien-1-
ylidene]dimethylammonium chloride
548-62-9 6/18/2012
81 1,2-dimethoxyethane; ethylene glycol dimethyl
ether (EGDME) 110-71-4 6/18/2012
82
[4-[[4-anilino-1-naphthyl][4-
(dimethylamino)phenyl]methylene]cyclohexa-
2,5-dien-1-ylidene] dimethylammonium chloride
2580-56-5 6/18/2012
83 TGIC (1,3,5-tris(oxiranylmethyl)-1,3,5-triazine-
2,4,6(1H,3H,5H)-trione) 2451-62-9 6/18/2012
84
4,4'-bis(dimethylamino)benzophenone
90-94-8 6/18/2012
(Michler's ketone)
85 Bis(pentabromophenyl) ether
(decabromodiphenyl ether; DecaBDE) 1163-19-5 12/19/2012
86 Pentacosafluorotridecanoic acid 72629-94-8 12/19/2012
87 Tricosafluorododecanoic acid 307-55-1 12/19/2012
88 Henicosafluoroundecanoic acid 2058-94-8 12/19/2012
89 Heptacosafluorotetradecanoic acid 376-06-7 12/19/2012
90 Diazene-1,2-dicarboxamide (C,C'-
azodi(formamide)) 123-77-3 12/19/2012
91
Cyclohexane-1,2-dicarboxylic anhydride [1]
85-42-7,
13149-00-3,
14166-21-3
12/19/2012
cis-cyclohexane-1,2-dicarboxylic anhydride [2]
trans-cyclohexane-1,2-dicarboxylic anhydride
[3]
[The individual cis- [2] and trans- [3] isomer
substances and all possible combinations of the
cis- and trans-isomers [1] are covered by this
entry].
92
Hexahydromethylphthalic anhydride [1],
25550-51-0,
19438-60-9,
48122-14-1,
57110-29-9
12/19/2012
Hexahydro-4-methylphthalic anhydride [2],
Hexahydro-1-methylphthalic anhydride [3],
Hexahydro-3-methylphthalic anhydride [4]
[The individual isomers [2], [3] and [4]
(including their cis- and trans- stereo isomeric
forms) and all possible combinations of the
isomers [1] are covered by this entry]
93
4-Nonylphenol, branched and linear
- 12/19/2012
[substances with a linear and/or branched alkyl
chain with a carbon number of 9 covalently
bound in position 4 to phenol, covering also
UVCB- and well-defined substances which
include any of the individual isomers or a
combination thereof] 5555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347
Internet: http:///www.latticesemi.com
Rev. Q
94
4-(1,1,3,3-tetramethylbutyl)phenol, ethoxylated
[covering well-defined substances and UVCB - 12/19/2012
substances, polymers and homologues]
95 Methoxyacetic acid 625-45-6 12/19/2012
96 N,N-dimethylformamide 68-12-2 12/19/2012
97 Dibutyltin dichloride (DBTC) 683-18-1 12/19/2012
98 Lead monoxide (Lead oxide) 1317-36-8 12/19/2012
99 Orange lead (Lead tetroxide) 1314-41-6 12/19/2012
100 Lead bis(tetrafluoroborate) 13814-96-5 12/19/2012
101 Trilead bis(carbonate)dihydroxide 1319-46-6 12/19/2012
102 Lead titanium trioxide 12060-00-3 12/19/2012
103 Lead titanium zirconium oxide 12626-81-2 12/19/2012
104 Silicic acid, lead salt 11120-22-2 12/19/2012
105
Silicic acid (H2Si2O5), barium salt (1:1), leaddoped
68784-75-8 12/19/2012
[with lead (Pb) content above the applicable
generic concentration limit for 'toxicity for
reproduction' Repr. 1A (CLP) or category 1
(DSD); the substance is a member of the group
entry of lead compounds, with index number
082-001-00-6 in Regulation (EC) No
1272/2008]
106 1-bromopropane (n-propyl bromide) 106-94-5 12/19/2012
107 Methyloxirane (Propylene oxide) 75-56-9 12/19/2012
108 1,2-Benzenedicarboxylic acid, dipentylester,
branched and linear 84777-06-0 12/19/2012
109 Diisopentylphthalate (DIPP) 605-50-5 12/19/2012
110 N-pentyl-isopentylphthalate 776297-69-9 12/19/2012
111 1,2-diethoxyethane 629-14-1 12/19/2012
112 Acetic acid, lead salt, basic 51404-69-4 12/19/2012
113 Lead oxide sulfate 12036-76-9 12/19/2012
114 [Phthalato(2-)]dioxotrilead 69011-06-9 12/19/2012
115 Dioxobis(stearato)trilead 12578-12-0 12/19/2012
116 Fatty acids, C16-18, lead salts 91031-62-8 12/19/2012
117 Lead cynamidate 20837-86-9 12/19/2012
118 Lead dinitrate 10099-74-8 12/19/2012
119 Pentalead tetraoxide sulphate 12065-90-6 12/19/2012
120 Pyrochlore, antimony lead yellow 8012-00-8 12/19/2012
121 Sulfurous acid, lead salt, dibasic 62229-08-7 12/19/2012
122 Tetraethyllead 78-00-2 12/19/2012
123 Tetralead trioxide sulphate 12202-17-4 12/19/2012
124 Trilead dioxide phosphonate 12141-20-7 12/19/2012
125 Furan 110-00-9 12/19/20125555 Northeast Moore Court • Hillsboro, Oregon 97124 • Phone (503) 268-8000 • FAX (503) 268-8347
Internet: http:///www.latticesemi.com
Rev. Q
126 Diethyl sulphate 64-67-5 12/19/2012
127 Dimethyl sulphate 77-78-1 12/19/2012
128 3-ethyl-2-methyl-2-(3-methylbutyl)-1,3-
oxazolidine 143860-04-2 12/19/2012
129 Dinoseb (6-sec-butyl-2,4-dinitrophenol) 88-85-7 12/19/2012
130 4,4'-methylenedi-o-toluidine 838-88-0 12/19/2012
131 4,4'-oxydianiline and its salts 101-80-4 12/19/2012
132 4-aminoazobenzene 60-09-3 12/19/2012
133 4-methyl-m-phenylenediamine (toluene-2,4-
diamine) 95-80-7 12/19/2012
134 6-methoxy-m-toluidine (p-cresidine) 120-71-8 12/19/2012
135 Biphenyl-4-ylamine 92-67-1 12/19/2012
136 o-aminoazotoluene [(4-o-tolylazo-o-toluidine)] 97-56-3 12/19/2012
137 o-toluidine 95-53-4 12/19/2012
138 N-methylacetamide 79-16-3 12/19/2012
While our products do not currently fall within the scope of REACH’s registration requirement,
we continue to monitor the EU regulation for changes that may require our attention.
Lattice is fully supportive of the various industry efforts throughout the world to phase out the
use of undesirable elements from electronic equipment materials and manufacturing processes.
Lattice remains committed to continually reducing its impact on the world's natural environment,
and we work closely with our customers and suppliers to identify and rapidly eliminate
hazardous substances from our products.
Be assured that your business is greatly valued by Lattice Semiconductor and that we will do
everything within our power to provide you with the highest level of service and support and
with the broadest portfolio of high performance Field Programmable Gate Arrays (FPGAs), Field
Programmable System Chips (FPSCs), ispPAC Mixed Signal devices and high-performance
ISPTM programmable logic devices (PLDs).
Regards,
Chris Leonhard
Sr. Customer Requirements Administrator
Lattice Semiconductor Corp.
custreq@latticesemi.com
LatticeSC Family Data Sheet
Version 01.0, February 2006February 2006 Preliminary Data Sheet
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 1-1 Introduction_01.0
Features
■ High Performance FPGA Fabric
• 15K to 115K four input Look-up Tables (LUT4s)
• 132 to 942 I/Os
• 700MHz global clock; 1GHz edge clocks
■ 8 to 32 High Speed SERDES and flexiPCS™
(per Device)
• Performance ranging from 622Mbps to 3.4Gbps
• Excellent Rx jitter tolerance (0.8UI at
3.125Gbps)
• Low Tx jitter (0.29UI at 3.125Gbps)
• Built-in Pre-emphasis and equalization
• Low power (typically 100mW per channel)
• Embedded Physical Coding Sublayer (PCS)
provides pre-engineered implementation for the
following standards:
– GbE, XAUI, PCI Express, SONET, Serial
RapidIO, 1G Fibre Channel, 2G Fibre Channel
■ 2Gbps High Performance PURESPEED™ I/O
• Supports the following performance bandwidths
– Differential I/O up to 2Gbps DDR (1GHz
Clock)
– Single-ended memory interfaces up to
800Mbps
• 144 Tap programable Input Delay (INDEL) block
on every I/O dynamically aligns data to clock for
robust performance
– Dynamic bit Adaptive Input Logic (AIL) monitoring and control circuitry per pin that automatically ensures proper set-up and hold
– Dynamic bus: uses control bus from DLL
– Static per bit
• Electrical standards supported:
– LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL
– SSTL 3/2/18 I, II; HSTL 18/15 I, II
– PCI, PCI-X
– LVDS, Mini-LVDS, Bus-LVDS, MLVDS,
LVPECL, RSDS, Hypertransport
• Programmable On Die Termination (ODT)
– Includes Thevenin Equivalent and low
power VTT termination options
■ Memory Intensive FPGA
• sysMEM™ embedded Block RAM
– 1 to 7.8 Mbits memory
– True Dual Port/Pseudo Dual Port/Single
Port
– Dedicated FIFO logic for all block RAM
– 500MHz performance
• Additional 240K to 1.8Mbits distributed RAM
■ sysCLOCK™ Network
• Eight analog PLLs per device
– Frequency range from 15MHz to 1GHz
– Spread spectrum support
• 12 DLLs per device with direct control of I/O
delay
– Frequency range from 100MHz to 700MHz
• Extensive clocking network
– 700MHz primary and 325 MHz secondary
clocks
– 1GHz I/O-connected edge clocks
• Precision Clock Divider
– Phase matched x2 and x4 division of incoming clocks
• Dynamic Clock Select (DCS)
– Glitch free clock MUX
■ Masked Array for Cost Optimization
(MACO™) Blocks
• On-chip structured ASIC Blocks provide preengineered IP for low power, low cost system
level integration
■ High Performance System Bus
• Ties FPGA elements together with a standard
bus framework
– Connects to peripheral user interfaces for
run-time dynamic configuration
■ System Level Support
• IEEE standard 1149.1 Boundary Scan, plus
ispTRACY™ internal logic analyzer
• IEEE Standard 1532 in-system configuration
• 1.2V and 1.0V operation
• Onboard oscillator for initialization and general
use
• Embedded PowerPC microprocessor interface
• Low cost wire-bond and high pin count flip-chip
packaging
• Low cost SPI Flash RAM configuration
LatticeSC Family Data Sheet
IntroductionIntroduction
Lattice Semiconductor LatticeSC Family Data Sheet
1-2
Table 1-1. LatticeSC Family Selection Guide
The LatticeSCM devices add MACO-enabled IP functionality to the base LatticeSC devices. Table 1-2 shows the
type and number of each pre-engineered IP core.
Table 1-2. LatticeSCM Family – Current
Introduction
The LatticeSC family of FPGA combines a high-performance FPGA fabric, high-speed SERDES, high-performance I/Os and large embedded RAM in a single industry leading architecture. This FPGA family is fabricated in a
state of the art technology to provide one of the highest performing FPGAs in the industry.
This family of devices includes features to meet the needs of today’s communication network systems. These features include SERDES with embedded advance PCS (Physical Coding sub-layer), up to 7.8 Mbits of sysMEM
embedded block RAM, dedicated logic to support system level standards such as RAPIDIO, HyperTransport,
SPI4.2, SFI-4, UTOPIA, XGMII and CSIX. The devices in this family feature clock multiply, divide and phase shift
PLLs, numerous DLLs and dynamic glitch free clock MUXs which are required in today’s high end system designs.
High speed, high bandwidth I/O make this family ideal for high throughput systems.
The ispLEVER®
design tool from Lattice allows large complex designs to be efficiently implemented using the LatticeSC family of FPGA devices. Synthesis library support for LatticeSC is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and backannotates it into the design for timing verification.
Device SC15 SC25 SC40 SC80 SC115
LUT4s (K) 15.2 25.4 40.4 80.1 115.2
sysMEM Blocks (18Kb) 56 104 216 308 424
Embedded Memory (Mbits) 1.03 1.92 3.98 5.68 7.8
Max. Distributed Memory (Mbits) 0.24 0.41 0.65 1.28 1.84
Number of 3.4G SERDES (Max.) 8 16 16 32 32
DLLs 12 12 12 12 12
Analog PLLs 88888
MACO Blocks 4 6 10 10 12
Package I/O/SERDES Combinations (1mm ball pitch)
256-ball fpBGA (17 x 17mm) 139/4
900-ball fpBGA (31 x 31mm) 300/8 378/8
1020-ball ffBGA (33 x 33mm) 484/16 562/16
1152-ball fcBGA (35 x 35mm) 660/16 660/16
1704-ball fcBGA (42.5 x 42.5mm) 904/32 942/32
Device SCM15 SCM25 SCM40 SCM80 SCM115
flexiMAC Blocks
• 1GbE Mode
• 10GbE Mode
• PCI Express Mode
12224
SPI4.2 Blocks 12222
Memory Controller Blocks
• DDR1 DRAM Mode
• DDR2 DRAM Mode
• QDR2 SRAM Mode
12222Introduction
Lattice Semiconductor LatticeSC Family Data Sheet
1-3
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeSC family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
Innovative high-performance FPGA architecture, high-speed SERDES with PCS support, sysMEM embedded
memory and high performance I/O are combined in the LatticeSC to provide excellent performance for today’s
leading edge systems designs. Table 1-3 details the performance of several common functions implemented within
the LatticeSC.
Table1-3. Speed Performance for Typical Functions1
Functions Performance (MHz)2
32-bit Address Decoder 455
64-bit Address Decoder 405
32:1 Multiplexer 507
64-bit Adder (ripple) 325
32x8 Distributed Single Port (SP) RAM 748
64-bit Counter (up or down counter, non-loadable) 355
True Dual-Port 1024x18 bits 359
FIFO Port A: x36 bits, B: x9 bits 361
1. For additional information, see Typical Building BLock Function Performance table
in this data sheet.
2. Advance information (-7 speed grade).February 2006 Preliminary Data Sheet
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 2-1 Architecture_01.0
Architecture Overview
The LatticeSC architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR). The upper left and
upper right corners of the devices contain SERDES blocks and their associated PCS blocks, as show in Figure 2-1.
Top left and top right corner of the device contain blocks of SERDES. Each block of SERDES contains four channels (quad). Each channel contains a single serializer and de-serializer, synchronization and word alignment logic.
The SERDES quad connects with Physical Coding Sub-layer (PCS) block that contain logic to simultaneously perform alignment, coding, de-coding and other functions. The SERDES quad block has separate supply, ground and
reference voltage pins.
The PICs contain logic to facilitate the conditioning of signals to and from the I/O before they leave or enter the
FPGA fabric. The block provides DDR and shift register capabilities that act as a gearbox between high speed I/O
and the FPGA fabric. The blocks also contain programmable Adaptive Input Logic that adjusts the delay applied to
signals as they enter the device to optimize setup and hold times and ensure robust performance.
sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM, ROM or FIFO. These
blocks have dedicated logic to simplify the implementation of FIFOs.
The PFU, PIC and EBR blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. These blocks are connected with many vertical and horizontal routing channel resources. The place
and route software tool automatically allocates these routing resources.
The corners contain the sysCLOCK Analog Phase Locked Loop (PLL) and Delay Locked Loop (DLL) Blocks. The
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeSC architecture provides eight analog PLLs per device and 12 DLLs. The DLLs provide a simple
delay capability and can also be used to calibrate other delays within the device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™
port which allows for serial or parallel device configuration. The system bus simplifies the connections of the external microprocessor to the device for tasks such as SERDES and PCS configuration or interface to the general
FPGA logic. The LatticeSC devices use 1.2V as their core voltage operation with 1.0V operation also possible.
LatticeSC Family Data Sheet
Architecture2-2
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-1. Simplified Block Diagram (Top Level)
Programmable
Function
Unit (PFU)
sysMEM Embedded
Block RAM (EBR)
Structured ASIC
Block (MACO)
Quad SERDES
Physical Coding
Sublayer (PCS)
Quad SERDES
Programmable
I/O Cell (PIC) includes
PURESPEED I/O Interface
sysCLOCK
Analog PLLs
sysCLOCK DLLs
sysCLOCK
Analog PLLs
sysCLOCK DLLs
Each PIC
contains four
Programmable
I/Os (PIO)
Three PICs
per four PFUs2-3
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
PFU Blocks
The core of the LatticeSC devices consists of PFU blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnections to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to implement 5, 6, 7 and 8 Input LUTs (LUT5, LUT6,
LUT7 and LUT8). There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic
of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are seven outputs: six to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated with each slice.
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
From
Routing
To
Routing
Slice 3
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D2-4
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-3. Slice Diagram
Table 2-1. Slice Signal Descriptions
Function Type Signal Names Description
Input Data signal A0, B0, C0, D0 Inputs to LUT4
Input Data signal A1, B1, C1, D1 Inputs to LUT4
Input Multi-purpose M0 Multipurpose Input
Input Multi-purpose M1 Multipurpose Input
Input Control signal CE Clock Enable
Input Control signal LSR Local Set/Reset
Input Control signal CLK System Clock
Input Inter-PFU signal FCIN Fast Carry In1
Output Data signals F0, F1 LUT4 output register bypass signals
Output Data signals Q0, Q1 Register Outputs
Output Data signals OFX0 Output of a LUT5 MUX
Output Data signals OFX1 Output of a LUT6, LUT7, LUT82
MUX depending on the slice
Output Inter-PFU signal FCO For the right most PFU the fast carry chain output2
1. See Figure 2-2 for connection details.
2. Requires two PFUs.
LUT4 &
CARRY
LUT4 &
CARRY
Slice
A0
B0
C0
D0
FF/
Latch
OFX0
F0
Q0
A1
B1
C1
D1
CI
CI
CO
CO
F
CE
CLK
LSR
FF/
Latch
OFX1
F1
Q1
F
D
D
M1
To / From
Different slice / PFU
To / From
Different slice / PFU
LUT
Expansion
Mux
M0
OFX0
From
Routing
To
Routing
Control Signals
selected and
inverted per
slice in routing
Note: some interslice
signals not shown.2-5
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. Table 2-2 lists the modes and the
capability of the Slice blocks.
Table 2-2. Slice Modes
Logic Mode
In this mode, the LUTs in each Slice are configured as combinatorial lookup tables. A LUT4 can have 16 possible
input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since
there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6,
LUT7 and LUT8 can be constructed by concatenating other Slices in the PFU.
Ripple Mode
Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice:
• Addition 2-bit
• Subtraction 2-bit
• Up counter 2-bit
• Down counter 2-bit
• Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode
In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the Slice. Table 2-3
shows the number of Slices required to implement different distributed RAM primitives. Dual port memories involve
the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the readonly port. For more information on RAM mode, please see details of additional technical documentation at the end
of this data sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
ROM Mode
The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration.
Logic Ripple RAM ROM
PFU Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit SPR 16x2
DPR 16x2 ROM 16x1
SPR16x2 DPR16x2
Number of Slices 1 2
Note: SPR = Single Port RAM, DPR = Dual Port RAM2-6
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Routing
There are many resources provided in the LatticeSC devices to route signals individually or as busses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU)
resources. The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal
directions. All connections are buffered to ensure high-speed operation even with long high-fanout connections.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
sysCLOCK Network
The LatticeSC devices have three distinct clock networks for use in distributing high-performance clocks within the
device, primary clocks, secondary clocks and edge clocks. In addition to these dedicated clock networks, users are
free to route clocks within the device using the general purpose routing. Figure 2-4 shows the clock resources
available to each slice.
Figure 2-4. Slice Clock Selection
Primary Clock Sources
LatticeSC devices have a wide variety of primary clock sources available. Primary clocks sources consists of the
following:
• Primary clock input pins
• Edge clock input pins
• Two outputs per DLL
Logic Ripple RAM ROM
LUT 4x8 or
MUX 2x1 x 8 2-bit Add x 4 SPR 16x2 x 4
DPR 16x2 x 2 ROM 16x1 x 8
LUT 5x4 or
MUX 4x1 x 4 2-bit Sub x 4 SPR 16x4 x 2
DPR 16x4 x 1 ROM 16x2 x 4
LUT 6x2 or
MUX 8x1 x 2 2-bit Counter x 4 SPR 16x8 x 1 ROM 16x4 x 2
LUT 7x1 or
MUX 16x1 x 1 2-bit Comp x 4 ROM 16x8 x1
Primary Clock
Secondary Clock
Routing Clock to Slice
GND
12
6
Note: GND is available to switch off the network.2-7
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
• Two outputs per PLL
• Clock divider outputs
• Digital Clock Select (DCS) block outputs
• Three outputs per SERDES quad
Figure 2-5 shows the arrangement of the primary clock sources.
Figure 2-5. Clock Sources
Primary Clock Routing
The clock routing structure in LatticeSC devices consists of 12 Primary Clock lines per quadrant. The primary
clocks are generated from 64:1 MUXs located in each quadrant. Three of the inputs to each 64:1 MUX comes from
local routing, one is connected to GND and rest of the 60 inputs are from the primary clock sources. Figure 2-6
shows this clock routing.
SERDES
PLL
DCS
DCS
DCS DCS
DCS DCS
DLL
DLL
DLL
DLL
DLL
DLL
DCS
Primary/
Edge Clock
PIOs
DCS
PLL
PLL
(3 per SERDES Channel)
(3 per SERDES Channel)
4
8
24 24
Primary Clock Sources
PLL
PLL
DLL
DLL
DLL
DLL
PLL
DLL
DLL
PLL
PLL SERDES
Primary/
Edge Clock
PIOs
Edge Clock
PIOs
Clock Dividers
Clock Dividers Clock Dividers
Clock
Dividers
Clock
Dividers Primary/
Edge Clock
PIOs
Primary/
Edge Clock
PIOs
Primary/
Edge Clock
PIOs
Edge
Clock
PIOs
Edge
Clock
PIOs
Primary/
Edge Clock
PIOs
Edge
Clock
PIOs
Primary/
Edge Clock
PIOs
Edge Clock
PIOs2-8
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-6. Per Quadrant Clock Selection
Secondary Clocks
In addition to the primary clock network and edge clocks the LatticeSC devices also contain a secondary clock network. Built of X6 style routing elements this secondary clock network is ideal for routing slower speed clock and
control signals throughout the device preserving high-speed clock networks for the most timing critical signals.
Edge Clocks
LatticeSC devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are eight edge clocks per bank for the top and bottom of the device. The
left and right sides have eight edge clocks per side for both banks located on that side. Figure 2-7 shows the
arrangement of edge clocks.
Edge clock resources can be driven from a variety of sources. Edge clock resources can be driven from:
• Edge clock PIOs in the same bank
• Primary clock PIOs in the same bank
• Routing
• Adjacent PLLs and DLLs
• ELSR output from the clock divider
12 Primary Clock per Quadrants
12 feedlines per quadrants times 4 + 12 feedlines from upper and lower half
12 Primary Clocks
60 Primary Clock Sources
GND
60
3 3 GND GND
From Local
Routing
From Local
Routing
From Local
Routing 60 60
3
Note: GND is available to switch off the network.2-9
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-7. Edge Clock Resources
Precision Clock Divider
Each set of edge clocks has four high-speed dividers associated with it. These are intended for generating a slower
speed system clock from the high-speed edge clock. The block operates in a X2 or X4 mode and maintains a
known phase relationship between the divided down clock and high-speed clock based on the release of its reset
signal. The clock dividers can be fed from selected PIOs, PLLs and routing. The clock divider outputs serve as primary clock sources. This circuit also generates an edge local set/reset (ELSR) signal which is fed to the PIOs via
the edge clock network and is used for the rest of the I/O gearing logic.
Figure 2-8. Clock Divider Circuit
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
SERDES SERDES
Bank 1
Bank 5 Bank 4
Bank 7 Bank 6
Bank 2 Bank 3
Edge clock
S/R S/R S/R S/R
Divided clock
Clock derived
from selected
PIOs, PLLs and
routing
LSR
Register chain to synchronize LSR to clock input
ELSR2-10
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-9 illustrates the
DCS Block diagram.
Figure 2-9. DCS Block Diagram
Figure 2-10 shows timing waveforms for one of the DCS operating modes. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-10. DCS Waveforms
Clock Boosting
There are programmable delays available in the clock signal paths in the PFU, PIC and EBR blocks. These allow
setup and clock-to-output times to be traded to meet critical timing without slowing the system clock. If this feature
is enabled then the design tool automatically uses these delays to improve timing performance.
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider and two clock output dividers. The input divider is used to divide the
input clock signal, while the feedback divider is used to multiply the input clock signal.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either programmed during configuration or can be adjusted dynamically.
The Phase Select block can modify the phase of the clock signal if desired. The Spread Spectrum block supports
the modulation of the PLL output frequency. This reduces the peak energy in the fundamental and its harmonics
providing for lower EMI (Electro Magnetic Interference).
The sysCLOCK PLL can be configured at power-up and then, if desired, reconfigured dynamically through the
serial memory interface bus which connects with the on-chip system bus. For example, the user can select inputs,
loop filters, divider setting, delay settings and phase shift settings. The user can also directly access the SMI bus
through the routing.
The PLL clock input, from pin or routing, feeds into an input divider. There are four sources of feedback signal to the
feedback divider: from the clock net, directly from the voltage controlled oscillator (VCO) output, from the routing or
DCS
CLK0
CLK1 DCSOUT
SEL
CLK0
SEL
DCSOUT
CLK12-11
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
from an external pin. The signal from the input clock divider and the feedback divider are passed through the programmable delay before entering the phase frequency detector (PFD) unit. The output of this PFD is used to control the voltage controlled oscillator. There is a PLL_LOCK signal to indicate that VCO has locked on to the input
clock signal. Figure 2-11 shows the sysCLOCK PLL diagram.
Figure 2-11. PLL Diagram
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Digital Locked Loop (DLLs)
In addition to PLLs, the LatticeSC devices have up to 12 DLLs per device. DLLs assist in the management of clocks
and strobes. DLLs are well suited to applications where the clock may be stopped or transferring jitter from input to
output is important, for example forward clocked interfaces. PLLs are good for applications requiring the lowest output jitter or jitter filtering. All DLL outputs are routed as primary/edge clock sources.
The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the
outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output
to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45,
22.5 or 11.25 degrees relative to its normal position. LOCK output signal is asserted when the DLL is locked. The
ALU HOLD signal setting allows users to freeze the DLL at its current delay setting.
There is a Digital Control (DCNTL) bus available from the DLL block. This Digital Control bus is available to the
delay lines in the PIC blocks in the adjacent banks. The UDDCNTL signal allows the user to latch the current value
on the digital control bus.
Figure 2-12 shows the DLL block diagram of the DLL inputs and outputs. The output of the phase frequency detector controls an arithmetic logic unit (ALU) to add or subract one delay tap. The digital output of this ALU is used to
control the delay value of the delay chain and this digital code is transmitted via the DCNTL bus.
The sysCLOCK DLL can be configured at power-up, then, if desired, reconfigured dynamically through the Serial
Memory Interface bus which interfaces with the on-chip Microprocessor Interface (MPI) bus. In addition, users can
drive the SMI interface from routing if desired.
The user can configure the DLL for many common functions such as clock injection match and single delay cell.
Lattice provides primitives in its design for time reference delay (DDR memory) and clock injection delay removal.
CLKI
CLKFB
CLKOP
CLKOS
VCO/
Loop Filter
Phase
Adjust
PFD
LOCK
Div
Div
Prog
Delay
Prog
Delay
Prog
Delay
Div
Div
Optional Internal Feedback RSTN
From PFD2-12
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-12. DLL Diagram
PLL/DLL Cascading
The LatticeSC devices have been designed to allow certain combinations of PLL and DLL cascading. The allowable combinations are as follows:
• PLL to PLL Supported
• PLL to DLL Supported
• DLL to DLL Supported
• DLL to PLL Not supported
DLLs are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency
synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applications to utilize the unique benefits of both DLL and PLLs.
For further information on the DLL, please see details of additional technical documentation at the end of this data
sheet.
sysMEM Memory Block
The sysMEM block can implement single port, true dual port, pseudo dual port or FIFO memories. Dedicated FIFO
support logic allows the LatticeSC devices to efficiently implement FIFOs without consuming LUTs or routing
resources for flag generation. Each block can be used in a variety of depths and widths as shown in Table 2-5.
Memory with ranges from x1 to x18 in all modes: single port, pseudo-dual port and FIFO also providing x36.
CLKI
CLKFB
CLKOP
CLKOS
UDDCNTL
ALUHOLD
DCNTL
Delay
Chain
ALU
Duty50
Phase Adj Duty50
PFD
DCNTL
Gen
LOCK
Phase Adj
RSTN2-13
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Table 2-5. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output. A clock is required even in asynchronous read mode.
The EBR memory supports three forms of write behavior for dual port operation:
1. Normal — data on the output appears only during a read cycle. During a write cycle, the data (at the current
address) does not appear on the output.
2. Write Through — a copy of the input data appears at the output of the same port.
3. Read-Before-Write — when new data is being written, the old content of the address appears at the output.
FIFO Configuration
The FIFO has a write port with Data-in, WCE, WE and WCLK signals. There is a separate read port with Data-out,
RCE, RE and RCLK signals. The FIFO internally generates Almost Full, Full, Almost Empty, and Empty Flags. The
Full and Almost Full flags are registered with WCLK. The Empty and Almost Empty flags are registered with RCLK.
The range of program values for these flags are in Table 2-6.
Memory Mode Configurations
Single Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
512 x 36
True Dual Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
Pseudo Dual Port
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
512 x 36
FIFO
16,384 x 1
8,192 x 2
4,096 x 4
2,048 x 9
1,024 x 18
512 x 362-14
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Table 2-6. Programmable FIFO Flag Ranges
The FIFO state machine supports two types of reset signals. The first reset signal is a global reset that clears the
contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in initial reset state. The second
reset signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO.
Programmable I/O Cells (PIC)
Each PIC contains four PIOs connected to their respective PURESPEED I/O Buffer which are then connected to
the PADs as shown in Figure 2-13. The PIO Block supplies the output data (DO) and the Tri-state control signal
(TO) to PURESPEED I/O buffer, and receives input (DI) from the buffer. The PIO contains advanced capabilities to
allow the support of speeds up to 2Gbps. These include dedicated shift and DDR logic and adaptive input logic.
The dedicated resources simplify the design of robust interfaces.
Flag Name Programming Range
Full (FF) 1 to (up to 2N
-1)
Almost Full (AF) 1 to Full-1
Almost Empty (AE) 1 to Full-1
Empty (EF) 0
Note: N = Address bit width.2-15
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-13. PIC Diagram
The A/B PIOs on the left and the right of the device can be paired to form a differentiated driver. The A/B and C/D
PIOs on all sides of the device can be paired to form differential receivers. Either A or C PIOs on all sides except
the one on top also contain an adaptive input logic capability that facilitates the implementation of high-speed interPIO B
PADA
TO
DO
DI
"T"
PADB
“C”
OPOS2
ONEG2
OPOS3
ONEG3
TD
INCK
INDD
INFF
IPOS0
INEG0
IPOS1
INEG1
IPOS2
INEG2
IPOS3
INEG3
RUNAIL
LOCK
UPDATE
*AIL only on A or C pads located on the left, right and bottom of the device.
CLK
CE
LSR
GSRN
HCLKOUT
GSR
LCLKOUT
LSRO
HCLKIN
LCLKIN
PIO A
PURESPEED
I/O Buffer
Control
Muxes
CEO
LSRO
ELSR
ECLK
IOLT0
POS Update
NEG Update
DI
DO
Tristate
Register Block
Input
Register Block
(including
delay and
AIL elements*)
Update Block
Output
Register Block
PIO C PADC
“T”
PIO D
PADD
“C”
OPOS0
ONEG0
OPOS1
ONEG12-16
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
faces in the LatticeSC devices. Figure 2-14 shows how differential receivers and drivers are arranged between
PIOs.
Figure 2-14. Differential Drivers and Receivers
PIO
The PIO contains five blocks: an input register block, output register block, tristate register block, update block, and
a control logic block. These blocks contain registers for both single data rate (SDR), double data rate (DDR), and
shift register operation along with the necessary clock and selection logic.
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-16 show the diagram of the input register block. The signal from the PURESPEED I/O buffer (DI) enters the input register block and can be used for three purposes, as a source for the combinatorial (INDD) and clock outputs (INCK), the input into the SDR register/latch block and the input to the delay
block. The output of the delay block can be used as combinatorial (INDD) and clock (INCK) outputs, an input to the
DDR/Shift Register Block or an input into the SDR register block.
Input SDR Register/Latch Block
The SDR register/latch block has a latch and a register/latch that can be used in a variety of combinations to provide a registered or latched output (INFF). The latch operates off high-speed input clocks and latches data on the
positive going edge. The register/latch operates off the low-speed input clock and registers/latches data on the positive going edge. Both the latch and the register/latch have a clock enable input that is driven by the input clock
enable. In addition both have a variety of programmable options for set/reset including, set or reset, asynchronous
or synchronous Local Set Reset LSR (LSR has precedence over CE) and Global Set Reset GSR enable or disable.
The register and latch LSR inputs are driven from LSRI, which is generated from the PIO control MUX. The GSR
inputs are driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on
a PIO basis.
Input Delay Block
The delay block uses 144 tapped delay lines to obtain coarse and fine delay resolution. These delays can be
adjusted during configuration or automatically via DLL or AIL blocks. The Adaptive Input Logic (AIL) uses this delay
block to adjust automatically the delay in the data path to ensure that it has sufficient setup and hold time.
The delay line in this block matches the delay line that is used in the 12 on-chip DLLs. The delay line can be set via
configuration bits or driven from a calibration bus that allows the setting to be controlled either from one of the onchip DLLs or user logic. Controlling the delay from one of the on-chip DLLs allow the delay to be calibrated to the
DLL clock and hence compensated for the variations in process, voltage and temperature.
PIO D
PIO C PADC "T"
PADD "C"
PIO A PADA "T"
PIO B PADB "C"
*Differential Driver only available on right and left of the device.2-17
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Adaptive Input Logic (AIL) Block
The AIL block is available in the A or C pads of each PIO on the left, right and bottom of the chip. This logic automatically adjusts the delay in the data path on a signal-by-signal basis to ensure that it has sufficient set-up and
hold. This capability simplifies the system level design of high-speed interfaces and ultimately allows higher overall
speeds to be achieved.
The AIL block receives data from nine taps in the delay line present in the input delay block. These signals are fed
to 18 registers. The registers operate off the high-speed input clock (9 on the positive edge and 9 on the negative
edge.) The output of these registers, along with the high speed input clock and RUNAIL signal are inputs to the AIL
control logic. If RUNAIL is enabled then the AIL control logic will determine if the delay needs to be adjusted in
order to avoid data transitions within a user specified margin. The margin can be a specified as 2, 4, 6 or 8 delay
increments. The LOCK output indicates that transitions are not occurring within the specified margin of the clock
edge. The AIL logic is automatically configured by the Lattice design tools dependent on the primitives that are
specified. Figure 2-15 shows the arrangement of the adaptive input logic.
Figure 2-15. Adaptive Input Logic and Delay Block
Input DDR/Shift Block
The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the
high-speed clock and the associated transfer to the low-speed clock domain. It functions as a gearbox allowing
high-speed incoming data to be passed into the FPGA fabric. Each PIO supports DDR and x2 shift functions. If
desired PIOs A and B or C and D can be combined to form x4 shift functions. The PIOs A and C on the left, right
and bottom of the device also contain an optional Adaptive Input Logic (AIL) element. This logic automatically
aligns incoming data with the clock allowing for easy design of high-speed interfaces. Figure 2-16 shows a simpliDelay tap n+16
Delay tap n+14
Delay tap n+12
Delay tap n+10
Delay tap n+8
Delay tap n+6
Delay tap n+4
Delay tap n+2
Delay tap n
Delay
Line
(96 Steps)
Coarse
Select
(47 Steps)
Fine
Select
Mux
From DLL or
configuration bits
Fine
Select
Muxes
Delay Block To
IOL
DI from
input buffer
AIL Control Logic
Delay tap n+16
Delay tap n+14
Delay tap n+12
Delay tap n+10
Delay tap n+8
Delay tap n+6
Delay tap n+4
Delay tap n+2
Delay tap n
To DDR/Shift Register Block
AIL Block
HCLKIN
RUNAIL
LOCK
7-bit
Control
Bus2-18
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
fied block diagram of the shift register block. The shift block in conjunction with the update and clock divider blocks
automatically handles the hand off between the low-speed and high-speed clock domains.
Figure 2-16. Input Register Block1
DDR/Shift Register Block
Optional
Adaptive
Input
Logic2
• DDR
• DDR + half clock
• DDR + shift x1
• DDR + shift x2
• DDR + shift x43
• Shift x1
• Shift x2
• Shift x43
To
Routing
INFF
INDD
INCK
IPOS0
CLKDISABLE
CLKENABLE
IPOS1
INEG0
INEG1
LCLKIN (ECLK/SCLK)
HCLKIN (ECLK/SCLK)
Latch
D-Type/
Latch
Delay
Block
LOCK
RUNAIL
DI
(from
PURESPEED
I/O Buffer)
DCNTL[0:8]
(From DLL)
1. UPDATE, Set and Reset not shown for clarity
2. Adaptive input logic is only available in selected PIO
3. By four shift modes utilize DDR/shift register block from paired PIO.
4. CLKDISABLE is used to block the transitions on the DQS pin during post-amble. Its main use is to
disable DQS (typically found in DDR memory interfaces) or other clock signals. It can also be used
to disable any/all input signals to save power.
SDR Register/Latch Block2-19
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-17. Input DDR/Shift Register Block
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of registers for DDR
and shift register operation. The output signal (DO) can be derived directly from one of the inputs (bypass mode),
the SDR register or the DDR/shift register block. Figure 2-18 shows the diagram of the Output Register Block.
Output SDR Register/Latch Block
The SDR register operates on the positive edge of the high-speed clock. It has clock enable that is driven by the
clock enable output signal generated by the control MUX. In addition it has a variety of programmable options for
set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR (LSR has precedence over
CE) and Global Set Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated
from the PIO control MUX. The GSR inputs is driven from the GSR output of the PIO control MUX, which allows the
global set-reset to be disabled on a PIO basis.
Output DDR/Shift Block
The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the
high-speed clock and the associated transfer from the low-speed clock domain. It functions as a gearbox allowing
low-speed parallel data from the FPGA fabric be output as a higher speed serial stream. Each PIO supports DDR
and x2 shift functions. If desired PIOs A and B or C and D can be combined to form x4 shift functions. Figure 2-18
shows a simplified block diagram of the shift register block.
Data Input
(From Delay Block)
HCLKIN
LCLKIN
POS Update
IPOS0
(Can act as IPOS2
when paired)
IPOS1
(Can act as IPOS3
when paired)
INEG0
(Can act as INEG2
when paired)
INEG1
(Can act as INEG3
when paired)
NEG Update
Used for DDR with
Half Clock Transfer
To paired PIO
for wide muxing
To paired PIO
for wide muxing
Bypass used for DDR
Bypass used for DDR
From paired PIO
for wide muxing
From paired PIO
for wide muxing2-20
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-18. Output Register Block1
Figure 2-19. Output/Tristate DDR/Shift Register Block
DDR/Shift Register Block
• DDR
• DDR + half clock
• DDR + shift x2
• DDR + shift x42
• Shift x2
• Shift x42
Notes:
1. CE, Update, Set and Reset not shown for clarity.
2. By four shift modes utilizes DDR/Shift register block from paired PIO.
3. DDR/Shift register block shared with tristate block.
HCLKOUT
LCLKOUT
OPOS0
From
Routing
To
Tri-state
Block
DO
(to PURESPEED
I/O Buffer)
From
Control
MUX
ONEG0
OPOS1
ONEG1
SDR
Register
Bypass Used for
DDR/DDRX Modes
Shift x2 / x4
Output
LCLKOUT
HCLKOUT
From paired PIO
( x4 shift modes)
To paired PIO
(x4 shift modes)
POS Update
OPOS0
(Can act as OPOS2
when paired)
NEG Update
OPOS1
(Can act as OPOS3
when paired)
Bypass Used for
DDR/DDRX Modes
From paired PIO
( x4 shift modes)
To paired PIO
(x4 shift modes)
ONEG0
(Can act as ONEG2
when paired)
ONEG1
(Can act as ONEG3
when paired)
TSDDR/DDRX
ODDR/DDR/
X2/X42-21
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of
three registers for DDR and shift register operation. The output signal tri-state control signal (TO) can be derived
directly from one of the inputs (bypass mode), the SDR shift register, the DDR registers or the data associated with
the buffer (for open drain emulation). Figure 2-20 shows the diagram of the Tristate Register Block.
Tristate SDR Register/Latch Block
The SDR register operates on the positive edge of the high-speed clock. In it has a variety of programmable
options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR and Global Set
Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated from the PIO control
MUX. The GSR input is driven from the GSR output of the PIO control MUX, which allows the global set-reset to be
disabled on a PIO basis.
Tristate DDR/Shift Register Block
The DDR/Shift block is shared with the output block allowing DDR support using the high-speed clock and the
associated transfer from the low-speed clock domain. It functions as a gearbox allowing low–speed parallel data
from the FPGA fabric to provide a high-speed tri-state control stream.
There is a special mode for DDR-II memory interfaces where the termination is controlled by the output tristate signal. During WRITE cycle when the FPGA is driving the lines, the parallel terminations are turned off. During READ
cycle when the FPGA is receiving data, the parallel terminations are turned on.
Figure 2-20. Tristate Register Block1
Control Logic Block
The control logic block allows the modification of control signals selected by the routing before they are used in the
PIO. It can optionally invert all signals passing through it except the Global Set/Reset. Global Set/Reset can be
enabled or disabled. It can route either the edge clock or the clock to the high-speed clock nets. The clock provided
to the PIO by routing is used as the slow-speed clocks. In addition this block contains delays that can be inserted in
the clock nets to enable Lattice’s unique cycle boosting capability.
Update Block
The update block is used to generate the POS update and NEG update signals used by the DDR/Shift register
blocks within the PIO. Note the update block is only required in shift modes. This is required in order to do the high
speed to low speed handoff. One of these update signals is also selected and output from the PIC as the signal
UPDATE. It consists of a shift chain that operates off either the high-speed input or output clock. The values of each
DDR/Shift Register Block2
• DDR
• DDR + half clock
HCLKOUT
LCLKOUT
From
Routing TO
(To PURESPEED
I/O Buffer)
From
Control
MUX
From Output
OPOS1
VCC
GND
TD
ONEG1
Notes:
1. CE, Update, Set and Reset not shown for clarity.
2. DDR/Shift Register Block shared with output register block. 2-22
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
register in the chain are set or reset depending on the desired mode of operation. The set/reset signal is generated
from either the edge reset ELSR or the local reset LSR. These signals are optionally inverted by the Control Logic
Block and provided to the update block as ELSRUP and LSRUP. The Lattice design tools automatically configure
and connect the update block when one of the DDR or shift register primitives is used.
Figure 2-21. Update Block
PURESPEED I/O Buffer
Each I/O is associated with a flexible buffer referred to as PURESPEED I/O buffer. These buffers are arranged
around the periphery of the device in seven groups referred to as Banks. The PURESPEED I/O buffers allow users
to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL,
LVDS and LVPECL. The availability of programmable on-chip termination for both input and output use, further
enhances the utility of these buffers.
PURESPEED I/O Buffer Banks
LatticeSC devices have seven PURESPEED I/O buffer banks; each is capable of supporting multiple I/O standards. Each PURESPEED I/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and
V
REF2 resources allowing each bank to be completely independent from each other. Figure 2-22 shows the seven
banks and their associated supplies. Table 2-7 lists the maximum number of I/Os per bank for the whole LatticeSC
family.
In the LatticeSC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI33 and PCIX33)
are powered using VCCIO. In addition to the bank VCCIO supplies, the LatticeSC devices have a VCC core logic power
supply, and a VCCAUX supply that power all differential and referenced buffers. VCCAUX also powers a predriver of
single-ended output buffers to enhance buffer performance.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the referenced input buffers. In the LatticeSC devices any I/O pin in a bank can be configured to be a dedicated reference
voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages.
Differential drivers have user selectable internal or external bias. External bias is brought in by the VREF1 pin in the
bank. External bias for differential buffers is needed for applications that requires tighter than standard output common mode range.
Since a bank can have only one external bias circuit for differential drivers, LVDS and RSDS differential outputs can
be mixed in a bank but not with HYPT (HyperTransport).
If a differential driver is configured in a bank, one pin in that bank becomes a DIFFR pin. This DIFFR pin must be
connected to ground via an external 1K +/-1% ohm resistor.
POS Update
NEG Update
HCLKUP
ESLRUP
LSRUP
LCLKUP
UPDATE
÷1/2/42-23
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
In addition, there are dedicated Terminating Supply (VTT) pins to be used as terminating voltage for one of the two
ways to perform parallel terminations. These VTT pins are available in banks 2-7, these pins are not available in
some packages. When these pins are not used they should be left unconnected. There are further restrictions on
the use of VTT pins, for additional details refer to technical information at the end of this data sheet.
Figure 2-22. LatticeSC Banks
Table 2-7. Maximum Number of I/Os Per Bank in LatticeSC Family
The LatticeSC devices contain three types of PURESPEED I/O buffers:
1. Left and Right Sides (Banks 2, 3, 6 and 7)
These buffers can support LVCMOS standards up to 2.5V. A differential driver is provided on all primary PIO
pairs (A and B) and differential receivers are available on all pairs. Adaptive input logic is available on PIOs A or
C.
Device LFSC15 LFSC25 LFSC40 LFSC80 LFSC115
Bank1 104 80 136 80 136
Bank2 28 36 60 96 136
Bank3 60 84 96 132 156
Bank4 72 100 124 184 208
Bank5 72 100 124 184 208
Bank6 60 84 96 132 156
Bank7 28 36 60 96 136
Note: Not all the I/Os of the Banks are available in all the packages
Bank 2 Bank 3
V
REF1[7]
GND
Bank 7
V
CCIO7
VTT7
V
REF2[7]
V
REF1[6]
GND
V
CCIO6
VTT6
V
REF2[6]
V
REF1[2]
GND
V
CCIO2
VTT2
V
REF2[2]
V
REF1[5]
V
GND
CCIO5
VTT5
V
REF2[5]
V
REF1[4]
V
GND
CCIO4
VTT4
V
REF2[4]
V
REF2[1]
GND
V
CCIO1
V
REF1[1]
V
REF1[3]
GND
V
CCIO3
VTT[3] Bank 6
V
REF2[3]
Bank 4
SERDES SERDES
Bank 5
Bank 12-24
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
2. Top Side (Bank 1)
These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential
receivers are provided on all PIO pairs but differential drivers are not available. Adaptive input logic is not available on this side.
3. Bottom Side (Banks 4 and 5)
These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential
receivers are provided on all PIO pairs but differential drivers are not available. Adaptive input logic is available
on PIOs A or C.
Table 2-8 lists the standards supported by each side.
Table 2-8. I/O Standards Supported by Different Banks
Supported Standards
The LatticeSC PURESPEED I/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 12, 15, 18, 25 and 33 standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable
options for drive strength, termination resistance, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper
latch) and open drain. Other single-ended standards supported include SSTL, HSTL, GTL (input only), GTL+ (input
only), PCI33, PCIX33, PCIX15, AGP-1X33 and AGP-2X33. Differential standards supported include LVDS, RSDS,
Description
Top Side
Banks 1
Right Side
Banks 2-3
Bottom Side
Banks 4-5
Left Side
Banks 6-7
I/O Buffer Type Single-ended,
Differential Receiver
Single-ended, Differential Receiver and Driver
Single-ended,
Differential Receiver
Single-ended, Differential Receiver and Driver
Output Standards
Supported
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18_I
SSTL25_ I, II
SSTL33_ I, II
HSTL15_I, II, III1
, IV1
HSTL18_I, II,III1
, IV1
SSTL18D_I, II
SSTL25D_I, II
SSTL33D_I, II
HSTL15D_I, II
HSTL18D_I, II
PCI33
PCIX15
PCIX33
AGP1X33
AGP2X33
MLVDS/BLVDS
GTL2
, GTL+2
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18_I
SSTL25_ I, II
HSTL15_I,III
HSTL18_I,II,III
PCIX15
SSTL18D_I, II
SSTL25D_I, II
HSTL15D_I, II
HSTL18D_I, II
LVDS/RSDS/HYPT
Mini-LVDS
MLVDS/BLVDS
GTL2
, GTL+2
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18_I
SSTL25_ I, II
SSTL33_ I, II
HSTL15_I, II, III1
, IV1
HSTL18_I, II,III1
, IV1
SSTL18D_I, II
SSTL25D_I, II
SSTL33D_I, II
HSTL15D_I, II
HSTL18D_I, II
PCI33
PCIX15
PCIX33
AGP1X33
AGP2X33
MLVDS/BLVDS
GTL2
, GTL+2
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18_I
SSTL25_ I, II
HSTL15_I,III
HSTL18_I,II,III
PCIX15
SSTL18D_I, II
SSTL25D_I, II
HSTL15D_I, II
HSTL18D_I, II
LVDS/RSDS/HYPT
Mini-LVDS
MLVDS/BLVDS
GTL2
, GTL+2
Input Standards
Supported
Single-ended,
Differential
Single-ended,
Differential
Single-ended,
Differential
Single-ended,
Differential
Clock Inputs Single-ended,
Differential
Single-ended,
Differential
Single-ended,
Differential
Single-ended,
Differential
Differential Output
Support via Emulation
LVDS/MLVDS/BLVDS/
LVPECL
MLVDS/BLVDS/
LVPECL
LVDS/MLVDS/BLVDS/
LVPECL
MLVDS/BLVDS/
LVPECL
AIL Support No Yes Yes Yes
1. Input only.
2. Input only. Outputs supported by bussing multiple outputs together.2-25
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
BLVDS, MLVDS, LVPECL, HyperTransport, differential SSTL and differential HSTL. Tables 12 and 13 show the I/O
standards (together with their supply and reference voltages) supported by the LatticeSC devices. The tables also
provide the available internal termination schemes. For further information on utilizing the PURESPEED I/O buffer
to support a variety of standards please see details of additional technical documentation at the end of this data
sheet.
Table 2-9. Supported Input Standards
Input Standard VREF (Nom.) VCCIO
1
(Nom.) On-chip Termination
Single Ended Interfaces
LVTTL333
— 3.3 None
LVCMOS 33, 25, 18, 15, 123
— 3.3/2.5/1.8/1.5/1.2 None
PCI33, PCIX33, AGP1X333
— 3.3 None
PCIX15 0.75 1.52
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
AGP2X33 1.32 — None
HSTL18_I, II 0.9 1.82
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
HSTL18_III, IV 1.08 1.82
None / VCCIO: 50
HSTL15_I, II 0.75 1.52
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
HSTL15_III, IV 0.9 1.52
None / VCCIO: 50
SSTL33_I, II 1.5 3.3 None
SSTL25_I, II 1.25 2.52
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
SSTL18_I, II 0.9 1.82
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
GTL+, GTL 1.0 / 0.8 1.5 / 1.22
None / VCCIO: 50
Differential Interfaces
SSTL18D_I, II — 1.82
None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,
220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
SSTL25D_I, II — 2.52
None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,
220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
SSTL33D_I, II — 3.3 None
HSTL15D_I, II — 1.52
None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,
220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
HSTL18D_I, II — 1.82
None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,
220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
LVDS — — None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,
220, 240
Mini-LVDS — — None / Diff: 120, 150 / Diff to VCMT: 120, 150
BLVDS25 — — None
MLVDS25 — — None
HYPT (Hyper Transport) — — None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,
220, 240
RSDS — — None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,
220, 240
LVPECL33 — — None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,
220, 240
1. When not specified VCCIO can be set anywhere in the valid operating range.
2. VCCIO needed for on-chip termination to VCCIO/2 or VCCIO only. VCCIO is not specified for off-chip termination.
3. All ratioed input buffers and dedicated pin input buffers include hysteresis with a typical value of 50mV.2-26
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Table 2-10. Supported Output Standards4
Output Standard Drive VCCIO (Nom) On-chip Output Termination
Single-ended Interfaces
LVTTL/D1
8mA, 16mA, 24mA 3.3 None.
LVCMOS33/D1
8mA, 16mA, 24mA 3.3 None
LVCMOS25/D1, 2 4mA, 8mA, 12mA, 16mA, 2.5 None, series: 25, 33, 50, 100
LVCMOS18/D1, 2 4mA, 8mA, 12mA, 16mA, 1.8 None, series: 25, 33, 50, 100
LVCMOS15/D1, 2 4mA, 8mA, 12mA, 16mA, 1.5 None, series: 25, 33, 50, 100
LVCMOS12/D1, 2 2mA, 4mA, 8mA, 12mA 1.2 None, series: 25, 33, 50, 100
PCIX15 N/A 1.5 None
PCI33, PCIX33, AGP1X33,
AGP2X33 N/A 3.3 None
HSTL18_I N/A 1.8 None, series: 50
HSTL18_II N/A 1.8 None, series: 25, series + parallel to VCCIO/2:
25 + 60
HSTL15_I N/A 1.5 None, series: 50
HSTL15_II N/A 1.5 None, series: 25, series + parallel to VCCIO/2:
25 + 60
SSTL33_I N/A 3.3 None
SSTL33_II N/A 3.3 None
SSTL25_I N/A 2.5 None, series: 50
SSTL25_II N/A 2.5 None, series: 33, series + parallel to VCCIO/2:
33+ 60
SSTL18_ I N/A 1.8 None, series: 33
SSTL18_II N/A 1.8 None, series: 33, series + parallel to VCCIO/2:
33+ 60
Differential Interfaces
SSTL18D_I N/A 1.8 None, series: 33
SSTL25D_I N/A 2.5 None, series: 50
SSTL18D_II, SSTL25D_II N/A 1.2/2.5/3.3 None, series: 33, series + parallel to VCCIO/2:
33+ 60
SSTL33D_I, II N/A 3.3 None
HSTL15D_I, HSTL18D_I N/A 1.5/1.8 None, series: 50
HST15D_II, HSTL18D_II N/A 1.5/1.8 None, series: 25, series + parallel to VCCIO/2:
25 + 60
LVDS 2mA, 3.5mA, 4mA, 6mA 2.5 None
Mini-LVDS 3.5mA, 4mA, 6mA 2.5 None
BLVDS25 N/A 2.5 None
MLVDS25 N/A 2.5 None
LVPECL333
N/A 3.3 None
HYPT (Hyper Transport) 3.5mA, 4mA, 6mA 2.5 None
RSDS 2mA, 3.5mA, 4mA, 6mA 2.5 None
1. D refers to open drain capability.
2. User can select either drive current or driver impedances but not both.
3. Emulated with external resistors.
4. No GTL or GTL+ support.2-27
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
PCI Clamp
A programmable PCI clamp is available on the top and bottom banks of the device. The PCI clamp can be turned
“ON” or “OFF” on each pin independently. The PCI clamp is used when implementing a 3.3V PCI interface. The PCI
Specification, Revision 2.2 requires the use of clamping diodes for 3.3V operation. For more information on the PCI
interface, please refer to the PCI Specification, Revision 2.2.
Programmable Slew Rate Control
All output and bidirectional buffers have an optional programmable output slew rate control that can be configured
for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows
designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling
edges.
Programmable Termination
Many of the I/O standards supported by the LatticeSC devices require termination at the transmitter, receiver or both.
The SC devices provide the capability to implement many kinds of termination on-chip, minimizing stub lengths and
hence improving performance. Utilizing this feature also has the benefit of reducing the number of discrete components required on the circuit board. The termination schemes can be split into two categories single-ended and differential.
Single Ended Termination
Single Ended Outputs: The SC devices support a number of different terminations for single ended outputs:
• Series
• Parallel to VCCIO or GND
• Parallel to VCCIO/2
• Parallel to VCCIO/2 combined with series
Figure 2-23 shows the single ended output schemes that are supported. The nominal values of the termination resistors are shown in Table 2-10.2-28
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-23. Output Termination Schemes
Termination Type Discrete Off-Chip Solution Lattice On-Chip Solution
Series termination
(controlled output
impedance)
Parallel termination to
V
CCIO,
or parallel
driving end
Combined series +
parallel termination to
V
CCIO/2 at driving end
(only series termination
moved on-chip)
Combined series +
parallel to VCCIO/2
driving end
Parallel termination to
V
CCIO/2 driving end
ON-chip
Zo Zo
Zo
OFF-chip OFF-chip ON-chip
ON-chip
Zo
OFF-chip
ON-chip
VCCIO or GND VCCIO or GND
Zo Zo
Zo
OFF-chip
Zo
Rs
Rs
Rs
ON-chip OFF-chip
Zo
ON-chip OFF-chip
Zo
ON-chip
VCCIO/2
Zo
Zo
OFF-chip
VCCIO/2
Zo
ON-chip
Zo
OFF-chip
Rs
VCCIO/2
Zo
VCCIO/2
Zo
VCCIO
GND
2Zo
2Zo
ON-chip OFF-chip
Zo
VCCIO
GND
2Zo
2Zo
ON-chip OFF-chip
Zo2-29
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Single Ended Inputs: The SC devices support a number of different termination schemes for single ended inputs:
• Parallel to VCCIO or GND
• Parallel to VCCIO/2
• Parallel to VTT
Figure 2-24 shows the single ended input schemes that are supported. The nominal values of the termination resistors are shown in Table 2-9.
Figure 2-24. Input Termination Schemes
In many situations designers can chose whether to use Thevenin or parallel to VTT termination. The Thevenin
approach has the benefit of not requiring a termination voltage to be applied to the device. The parallel to VTT
approach consumes less power.
VTT Termination Resources
Each I/O bank, except bank 1, has a number of VTT pins that must be connected if VTT is used. Note VTT pins can
sink or source current and the power supply they are connected to must be able to handle the relatively high currents
associated with the termination circuits. Note: VTT is not available in all package styles.
On-chip parallel termination to VTT is supported at the receiving end only. On-chip parallel output termination to VTT is
not supported.
The VTT internal bus is also connected to the internal VCMT node. Thus in one bank designers can implement either
VTT termination or VCMT termination for differential inputs.
DDRII/RLDRAMII Termination Support
The DDR II memory and RLDRAMII (in Bidirection Data mode) standards require that the on-chip termination to VTT
be turned on when a pin is an input and off when the pin is an output. The LatticeSC devices contain the required circuitry to support this behavior. For additional detail refer to technical information at the end of the data sheet.
Termination Type Discrete Off-Chip Solution Lattice On-Chip Solution
Parallel termination to
V
CCIO/2 receiving end
Parallel termination to
to VCCIO, or parallel to
GND receiving end
VCCIO or GND
OFF-chip ON-chip
Zo
Zo
VCCIO2
OFF-chip ON-chip
Zo
Zo
VTT
OFF-chip ON-chip
Zo
Zo
OFF-chip ON-chip
Zo
VTT
Zo
VCCIO or GND
OFF-chip ON-chip
Zo
Zo
VCCIO
GND
OFF-chip ON-chip
2Zo
2Zo
Zo
Parallel termination to
VTT at receiving end2-30
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Differential Input Termination
The LatticeSC device allows two types of differential termination. The first is a single resistor across the differential
inputs. The second is a center-tapped system where each input is terminated to the on-chip termination bus VCMT.
The VCMT bus is DC-coupled through an internal capacitor to ground.
Figure 2-25 shows the differential termination schemes and Table 2-9 shows the nominal values of the termination
resistors.
Figure 2-25. Differential Termination Scheme
Calibration
There are two calibration sources that are associated with the termination scheme used in the LatticeSC devices:
• DIFFR – This pin occurs in each bank and must be connected through a 1K+/-1% resistor to ground if differential outputs are used.
• XRES – There is one of these pins per device. It is used for several functions including calibrating on-chip
termination. This pin should always be connected through a 1K+/-1% resistor to ground.
The LatticeSC devices support two modes of calibration:
• Continuous – In this mode the SC devices continually calibrate the termination resistances. Calibration happens several times a second. Using this mode ensures that termination resistances remain calibrated as
the silicon junction temperature changes.
• User Request – In this mode the calibration circuit operates continuously. However, the termination resistor
values are only updated on the assertion of the calibration_update signal available to the core logic.
For more information on calibration, refer to the details of additional technical documentation at the end of this data
sheet.
Hot Socketing
The LatticeSC devices have been carefully designed to ensure predictable behavior during power-up and powerdown. To ensure proper power sequencing, care must be taken during power-up and power-down as described
below. During power-up and power-down sequences, the I/Os remain in tristate until the power supply voltage is
high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits,
Termination Type Discrete Off-Chip Solution Lattice On-Chip Solution
Differential termination
Differential and common
mode termination
OFF-chip ON-chip
+
-
2Zo
Zo
Zo
OFF-chip ON-chip
GND +
-
Zo
Zo
Zo
Zo
OFF-chip ON-chip
+
-
2Zo
Zo
Zo
OFF-chip ON-chip
GND
VCMT +
-
Zo
Zo
Zo
Zo2-31
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
this allows for easy integration with the rest of the system. These capabilities make the LatticeSC ideal for many
multiple power supply and hot-swap applications.
Power-Up Requirements
To prevent high power supply and input pin currents, each VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies must have a monotonic ramp up time of 75 ms or less to reach its minimum operating voltage. Apart from VCC
and VCC12, which have an additional requirement, and VCCIO and VCCAUX, which also have an additional
requirement, the VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies can ramp up in any order, with no
restriction on the time between them. However, the ramp time for each must be 75 ms or less. Configuration of the
device will not proceed until the last power supply has reached its minimum operating voltage.
Additional Requirement for VCC and VCC12
VCC12 must always be higher than VCC. This condition must be maintained at ALL times, including during powerup and power-down. Note that for 1.2V only operation, it is advisable to source both of these supplies from the
same power supply.
Additional Requirement for VCCIO and VCCAUX
If any VCCIOs are 1.2/1.5/1.8V, then VCCAUX MUST be applied before them. If any VCCIO is 1.2/1.5/1.8V and is
powered up before VCCAUX, then when VCCAUX is powered up, it may drag VCCIO up with it as it crosses
through the VCCIO value. (Note: If the VCCIO supply is capable of sinking current, as well as the more usual sourcing capability, this behavior is eliminated. However, the amount of current that the supply needs to sink is unknown
and is likely to be in the hundreds of milliamps range).
Power-Down Requirements
To prevent high power supply and input pin currents, power must be removed monotonically from either VCC or
VCCAUX (and must reach the power-down trip point of 0.5V for VCC, 0.95V for VCCAUX) before power is removed
monotonically from VCC12, any of the VCCIOs, or VCCJ. Note that VCC12 can be removed at the same time as
VCC, but it cannot be removed earlier. In many applications, VCC and VCC12 will be sourced from the same power
supply and so will be removed together. For systems where disturbance of the user pins is a don't care condition,
the power supplies can be removed in any order as long as they power down monotonically within 200ms of each
other.
Additionally, if any banks have VCCIO=3.3V nominal (potentially banks 1, 4, 5) then VCCIO for those banks must
not be lower than VCCAUX during power-down. The normal variation in ramp-up times of power supplies and voltage regulators is not a concern here.
Note: The SERDES power supplies are NOT included in these requirements and have no specific sequencing
requirements. However, when using the SERDES with VDDIB or VDDOB that is greater than 1.2V (1.5V nominal
for example), the SERDES should not be left in a steady state condition with the 1.5V power applied and the 1.2V
power not applied. Both the 1.2V and 1.5V power should be applied to the SERDES at nominally the same time.
The normal variation in the ramp-up times of power supplies and voltage regulators is not a concern here.
Supported Source Synchronous Interfaces
The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify
the implementation of Source Synchronous interfaces. Table 2-11 lists Source Synchronous and DDR/QDR standards supported in the LatticeSC. For additional detail refer to technical information at the end of the data sheet.2-32
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Table 2-11. Source Synchronous Standards Table1
flexiPCS™ (Physical Coding Sublayer Block)
flexiPCS Functionality
The LatticeSC family combines a high-performance FPGA fabric, high-performance I/Os and large embedded
RAM in a single industry leading architecture. LatticeSC devices also feature up to 32 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The flexiPCS logic can be configured to support
numerous industry standard high-speed data transfer protocols.
Each channel of flexiPCS logic contains dedicated transmit and receive SERDES for high-speed, full-duplex serial
data transfers at data rates up to 3.4 Gbps. The PCS logic in each channel can be configured to support an array of
popular data protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10 Gbps or
above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X specification), 1.02 or 2.04 Gbps Fibre Channel,
PCI-Express, and Serial RapidIO. In addition, the protocol based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface.
Protocols requiring data rates above 3.4 Gbps can be accommodated by dedicating either one pair or all four channels in one flexiPCS quad block to one data link. One quad can support full-duplex serial data transfers at data
rates up to 13.6 Gbps. A single flexiPCS quad can be configured to support 10Gb Ethernet (with a fully compliant
XAUI interface), 10Gb Fibre Channel, and x4 PCI-Express and 4x RapidIO.
The flexiPCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the
FPGA logic which can also be geared to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Each
SERDES pin can be DC coupled independently and can allow for both high-speed and low-speed operation down
to DC rates on the same SERDES pin, as required by some Serial Digital Video applications.
The ispLEVER design tools from Lattice support all modes of the flexiPCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow a user to
define their own operation. With ispLEVER, the user can define the mode for each quad in a design. Nine modes
are currently supported by the ispLEVER design flow:
• 8-bit SERDES Only
• 10-bit SERDES Only
• SONET (STS-12/STS-48)
• Gigabit Ethernet
• Fibre Channel
• XAUI
• Serial RapidIO
Source Synchronous Standard Clocking Speeds (MHz) Data Rate (Mbps)
RapidIO DDR 500 1000
HyperTransport DDR 400 800
SPI4.2 (POS-PHY4)/NPSI DDR 650 1300
SFI4/XSBI DDR
SDR
334
667
667
XGMII DDR 156.25 312
CSIX SDR 250 250
QDRII memory interface DDR 300 600
DDR memory interface DDR 240 480
DDRII memory interface DDR 400 800
RLDRAM memory interface DDR 400 800
1. Memory width is dependent on the system design and limited by the number of I/Os in the device.2-33
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
• PCI-Express
• Generic 8b10b
flexiPCS Quad
The flexiPCS logic is arranged in quads containing logic for four independent full-duplex data channels. Each
device in the LatticeSC family has up to eight quads of flexiPCS logic. The LatticeSC Family Selection Guide table
on the first page of this data sheet contains the number of flexiPCS channels present on the chip. Note that in
some packages (particularly lower pin count packages), not all channels from all quads on a given device may be
bonded to package pins.
Each quad supports up to four channels of full-duplex data and can be programmed into any one of several protocol based modes. Each quad requires its own reference clock which can be sourced externally or from the FPGA
logic. The user can utilize between one and four channels in a quad, depending on the application.
Figure 2-26 shows an example of four flexiPCS quads in a LatticeSC device. Quads are labeled according to the
address of their software controlled registers.
Figure 2-26. LatticeSC flexiPCS
Since each quad has its own reference clock, different quads can support different standards on the same chip.
This feature makes the LatticeSC family of devices ideal for bridging between different standards.
flexiPCS quads are not dedicated solely to industry standard protocols. Each quad (and each channel within a
quad) can be programmed for many user defined data manipulation modes. For example, modes governing userdefined word alignment and multi-channel alignment can be programmed for non-standard protocol applications.
For more information on the functions and use of the flexiPCS, refer to the LatticeSC flexiPCS Data Sheet.
SERDES Interface
FPGA Logic
Channel 0 PCS Logic
Channel 1 PCS Logic
Channel 2 PCS Logic
Channel 3 PCS Logic
FPGA Logic I/Os
FPGA Logic I/Os
FPGA Logic I/Os
flexiPCS
Quad 360
PCS/FPGA
Interface
flexiPCS
Quad 360
High Speed
Serial Data
FPGA Logic I/Os
SERDES Interface
Channel 0 PCS Logic
Channel 1 PCS Logic
Channel 2 PCS Logic
Channel 3 PCS Logic
flexiPCS
Quad 361
PCS/FPGA
Interface
flexiPCS
Quad 361
High Speed
Serial Data
SERDES Interface
Channel 3 PCS Logic
Channel 2 PCS Logic
Channel 1 PCS Logic
Channel 0 PCS Logic
flexiPCS
Quad 3E1
PCS/FPGA
Interface
flexiPCS
Quad 3E1
High Speed
Serial Data
SERDES Interface
Channel 3 PCS Logic
Channel 2 PCS Logic
Channel 1 PCS Logic
Channel 0 PCS Logic
flexiPCS
Quad 3E0
PCS/FPGA
Interface
flexiPCS
Quad 3E0
High Speed
Serial Data2-34
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
System Bus
Each LatticeSC device connects the FPGA elements with a standardized bus framework referred to as a System
Bus. Multiple bus masters optimize system performance by sharing resources between different bus masters such
as the MPI and configuration logic. The wide data bus configuration of 32 bits with 4-bit parity supports high-bandwidth, data intensive applications.
There are two types of interfaces on the System Bus, master and slave. A master interface has the ability to perform actions on the bus, such as writes and reads to and from a specific address. A slave interface responds to the
actions of a master by accepting data and address on a write and providing data on a read. The System Bus has a
memory map which describes each of the slave peripherals that is connected on the bus. Using the addresses
listed in the memory map, a master interface can access each of the slave peripherals on the System Bus. Any and
all peripherals on the System Bus can be used at the same time. Table 2-12 list all of the available user peripherals
on the System Bus after device power-up.
Table 2-12. System Bus User Peripherals
The peripherals listed in Table 2-12 can be added when the System Bus module is created using Module IP/Manager (ispLEVER Module/IP Manager).
Figure 2-27 also lists the existing peripherals on the System Bus. The gray boxes are available only during configuration. Refer to Lattice technical note TN1080, LatticeSC sysCONFIG Usage Guide, for configuration options. The
Status and Config box refers to internal System Bus registers. This document presents all the interfaces listed in
Table 2-12 in detail to help the user utilize the desired functions of the System Bus.
Figure 2-27. LatticeSC System Bus Interfaces
Several interfaces exist between the System Bus and other FPGA elements. The MPI interface acts as a bridge
between the external microprocessor bus and System Bus. The MPI may work in an independent clock domain
from the System Bus if the System Bus clock is not sourced from the external microprocessor clock. Pipelined
Peripheral Name Interface Type
Micro Processor Interface MPI Master
User Master Interface UMI Master
User Slave Interface USI Slave
Serial Management Interface (PLL, DLL, User Logic) SMI Slave
Physical Coding Sublayer PCS Slave
Direct FPGA Access DFA Slave
DFA
(Direct Access
from MPI)
SMI
(PLL, DLL,
USER LOGIC)
STATUS and
CONFIG
(SYS REG)
CONFIG
(MASTER)
System Bus
USI
(SLAVE)
UMI
(MASTER)
EBR INIT
(WRITE)
MPI
(MASTER)
PCS (LEFT, RIGHT
and INTER-QUAD)
(SLAVE)2-35
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
operation allows high-speed memory interface to the EBR and peripheral access without the requirement for additional cycles on the bus. Burst transfers allow optimal use of the memory interface by giving advance information of
the nature of the transfers.
Details for the majority of the peripherals can be found in the associated technical documentation, see details at
the end of this data sheet. Additional details of the MPI are provided below.
Microprocessor Interface (MPI)
The LatticeSC family devices have a dedicated synchronous MPI function block. The MPI is programmable to operate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or
32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for configuration
and read-back of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions.
The control portion of the MPI is available following power-up of the FPGA if the mode pins specify MPI mode, even
if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus
can be 1-, 2-, or 4-bit. In configuration mode the data and parity bus width are related to the state of the M[0:3]
mode pins. For post-configuration use, the MPI must be included in the configuration bit stream by using an MPI
library element in your design from the ispLEVER primitive library, or by setting the bit of the MPI configuration control register prior to the start of configuration. The user can also enable and disable the parity bus through the con-
figuration bit stream. These pads can be used as general I/O when they are not needed for MPI use.
The MPI block also provides the capability to interface directly to the FPGA fabric with a databus after configuration.The bus protocol is still handled by the MPI block but the direct FPGA access allows high-speed block data
transfers such as DMA transactions. Figure 2-28 shows one of the ways a PowerPC is connected to MPI.
Figure 2-28. PowerPCI and MPI Schematic
Bus
Controller
LatticeSC FPGA
To DaisyChained
Devices
PowerPC
DOUT
DONE
HDC
INIT
LDC
CCLK
RETRY MPI_RTRY
MPI_ACK
BDIP MPI_BDIP
IRQx MPI_IRQ
TS MPI_STRB
CS0
TSZ[0:1] MPI_TSZ[0:1]
A[14:31] PPC_A[14:31]
CLKOUT MPI_CLK
RD/WR MPI_RW
TA
DP[0:m]
1, 2, 4
8, 16, 32
DP[0:m]
D[0:n] D[0:n]
CS1
TEA MPI_TEA
BURST MPI_BURST2-36
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Configuration and Testing
The following section describes the configuration and testing features of the LatticeSC family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeSC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can
operate with LVCMOS33, 25 and 18 standards. For additional detail refer to technical information at the end of the
data sheet.
Device Configuration
All LatticeSC devices contain three possible ports that can be used for device configuration. The serial port, which
supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial configuration.
The MPI port supports 8-bit, 16-bit or 32-bit configuration.
The serial port supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System
Configuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins
and the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for general purpose I/O. All I/Os for the sysCONFIG and MPI ports are in I/O bank #1.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a
configuration port is selected, that port is locked and another configuration port cannot be activated until the next
re-initialization sequence. For additional detail refer to technical information at the end of the data sheet.
Internal Logic Analyzer Capability (ispTRACY)
All LatticeSC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile
time. For additional detail refer to technical information at the end of the data sheet.
Temperature Sensing
Lattice provides a way to monitor the die temperature by using a temperature-sensing diode that is designed into
every LatticeSC device. The difference in VBE of the diode at two different forward currents varies with temperature.
This relationship is shown in Figure 2-29.
This temperature-sensing diode is designed to work with an external temperature sensor such as the Maxim
1617A. The Maxim 1617A is configured to measure difference in VBE (of the temperature-sensing diode) at 10µA
and at 100µA. This difference in VBE voltage varies with temperature at approximately 1.64 mV/°C. A typical device
with a 85°C junction temperature will measure approximately 593mV. For additional detail refer to technical information at the end of the data sheet.2-37
Architecture
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 2-29. Sensing Diode Typical Characteristics
Oscillator
Every LatticeSC device has an internal CMOS oscillator, which is used as a master serial clock for configuration
and is also available as a potential general purpose clock (MCK) for the FPGA core. There is a K divider (divide by
2/4/8/16/32/64/128) available with this oscillator to get lower MCK frequencies. This clock is available as a general
purpose clock signal to the software routing tool. For additional detail refer to technical information at the end of the
data sheet.
Density Shifting
The LatticeSC family has been designed to ensure that different density devices in the same package have the
same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from
lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
0.50
-50 50 75 100 125 -25 25
100μA
10μA
Junction Temperature (°C)
Voltage
0
0.55
0.65
0.65
0.70
0.75
0.80
0.88
VBE difference
increases with
temperatureFebruary 2006 Preliminary Data Sheet
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 3-1 DC and Switching_01.0
Absolute Maximum Ratings
Supply Voltage VCC, VCC12, VDDIB, V
DDOB, V
DDRX, V
DDTX, V
DDP . . . . . . . . . . -0.5 to 1.6V
Supply Voltage VCCAUX, VDDAX25, VTT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V
Supply Voltage VCCJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Supply Voltage VCCIO (Banks 1, 4, 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Supply Voltage VCCIO (Banks 2, 3, 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V
Input or I/O Tristate Voltage Applied (Banks 1, 4, 5) . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input or I/O Tristate Voltage Applied (Banks 2, 3, 6, 7) . . . . . . . . . . . . . . . . -0.5 to 2.75V
Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Notes:
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and Undershoot of -2V to (VIHMAX +2) volts is permitted for a duration of <20ns.
Recommended Operating Conditions
Symbol Parameter Min. Max. Units
V
CC Core Supply Voltage (Nominal 1.2V Operation) 0.95 1.26 V
V
CCAUX Programmable I/O Auxiliary Supply Voltage 2.375 2.625 V
V
CCIO
1, 2 Programmable I/O Driver Supply Voltage (Banks 1, 4, 5) 1.14 3.45 V
V
CCIO
1, 2 Programmable I/O Driver Supply Voltage (Banks 2, 3, 6, 7) 1.14 2.625 V
V
CC12
4 Internal 1.2V Configuration Logic and FPGA PLL Power Supply
Voltage for Configuration Logic and FPGA PLL 1.14 1.26 V
V
DDP SERDES PLL Power Supply Voltage 1.14 1.26 V
V
DDTX, VDDRX SERDES Analog Supply Voltage 1.14 1.26 V
V
DDIB SERDES Input Buffer Supply Voltage 1.14 1.575 V
V
DDOB SERDES Output Buffer Supply Voltage 1.14 1.575 V
V
DDAX25 SERDES Termination Auxiliary Supply Voltage 2.375 2.625 V
V
CCJ
1
Supply Voltage for IEEE 1149.1 Test Access Port 1.71 3.45 V
VTT
2, 3 Programmable I/O Termination Power Supply 0.5 VCCAUX - 0.5 V
t
JCOM Junction Commercial Operation 0 +85 C
t
JIND Junction Industrial Operation -40 105 C
1. If VCCIO or VCCJ is set to 2.5V, they must be connected to the same power supply as VCCAUX.
2. See recommended voltages by I/O standard in subsequent table.
3. If VTT termination and CTAP function is not used in a bank, VTT can be tied to ground.
4. VCC12 cannot be lower than VCC at any time. For 1.2V operation, it is recommended that the VCC and VCC12 supplies be tied together with
proper noise decoupling between the digital VCC and analog VCC12 supplies.
LatticeSC Family Data Sheet
DC and Switching Characteristics3-2
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Hot Socketing Specifications
DC Electrical Characteristics5
Over Recommended Operating Conditions
Symbol Parameter Condition Min. Typ. Max Units
I
DK
Programmable and dedicated Input or I/O leakage
current1, 2, 3, 4, 5 0 <= VIN <= VIH (MAX) — — +/-1500 µA
SERDES average input current when device powered
down and inputs driven6 — — 4 mA
1. Assumes monotonic rise/fall rates for all power supplies.
2. Sensitive to power supply sequencing as described in hot socketing section.
3. Assumes power supplies are between 0 and maximum recommended operations conditions.
4. IDK is additive to IPU, IPD or IBH.
5. Represents DC conditions. For the first 20ns after hot insertion, current specification is 8 mA.
6. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed
VDDOB of 1.575V, 8b/10b data and internal AC coupling.
Symbol Parameter Condition Min.3
Typ. Max. Units
I
IL, IIH
1
Input or I/O Low leakage 0 ≤ VIN ≤ VIH (MAX) — — 10 µA
I
PU I/O Active Pull-up Current 0 ≤ VIN ≤ 0.7 VCCIO -30 — -210 µA
I
PD
I/O Active Pull-down Current VIL (MAX) ≤ VIN ≤ VIH (MAX) 30 — 210 µA
I
BHLS
Bus Hold Low Sustaining
Current VIN = VIL (MAX) 30 — — µA
I
BHHS
Bus Hold High Sustaining
Current VIN = 0.7VCCIO -30 — — µA
I
BHLO
Bus Hold Low Overdrive
Current 0 ≤ VIN ≤ VIH (MAX) — — 210 µA
I
BHLH
Bus Hold High Overdrive
Current 0 ≤ VIN ≤ VIH (MAX) — — -210 µA
I
CL PCI Low Clamp Current -3 < VIN ≤ -1 -25 + (VIN + 1)/0.015 — — mA
I
CH PCI High Clamp Current VCC + 4 > VIN ≥ VCC + 1 25 + (VIN - VCC -1)/
0.015 — — mA
VBHT Bus Hold trip Points 0 ≤ VIN ≤ VIH (MAX) VIL (MAX) — VIH (MIN) V
C1 I/O Capacitance2
V
CCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
V
CC = 1.2V, VCCIP2 = 1.2V,
V
CCAUX = 2.5, VIO = 0 to VIH (MAX)
— 8 — pf
C32
Dedicated Input
Capacitance2
V
CCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
V
CC = 1.2V, VCCIP2 = 1.2V,
V
CCAUX = 2.5, VIO = 0 to VIH (MAX)
— 6 — pf
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. TA 25°C, f = 1.0MHz
3. IPU, IPD, IBHLS and I
BHHS have minimum values of 15 or -15µA if VCCIO is set to 1.2V nominal.
4. This table does not apply to SERDES pins.
5. For programmable I/Os.3-3
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Initialization and Standby Supply Current1, 2, 3
Over Recommended Operating Conditions
Symbol Parameter Device 25 o
C 105 o
C Units
I
CC
Core Operating Power Supply Current
(for VCC + VCC12)
LFSC15 mA
LFSC25 210 1500 mA
LFSC40 mA
LFSC80 mA
LFSC115 mA
I
CCAUX Auxiliary Operating Power Supply Current
LFSC15 mA
LFSC25 5 35 mA
LFSC40 mA
LFSC60 mA
LFSC80 mA
LFSC115 mA
I
CCIO Bank Power Supply Current4
LFSC15 mA
LFSC25 0.2 1 mA
LFSC40 mA
LFSC80 mA
LFSC115 mA
Notes:
1. For further information on supply current, please see the details of additional technical documentation at the end of this data
sheet.
2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
3. SERDES supply current is detailed in the SERDES section.
4. Includes ICCJ.3-4
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
PURESPEED I/O Recommended Operating Conditions
V
CCIO V
REF (V)
Standard Min. Typ. Max. Min. Typ. Max.
LVCMOS 33 3.135 3.3 3.465 — — —
LVCMOS 25 2.375 2.5 2.625 — — —
LVCMOS 18 1.71 1.8 1.89 — — —
LVCMOS 15 1.425 1.5 1.575 — — —
LVCMOS 12 1.14 1.2 1.26 — — —
LVTTL 3.135 3.3 3.465 — — —
PCI33 3.135 3.3 3.465 — — —
PCIX33 3.135 3.3 3.465 — — —
PCIX15 1.425 1.5 1.575 0.49VCCIO 0.5VCCIO 0.51VCCIO
AGP1X33 3.135 3.3 3.465 — — —
AGP2X33 3.135 3.3 3.465 0.39VCCIO 0.4VCCIO 0.41VCCIO
SSTL18_I, II3
1.71 1.8 1.89 0.833 0.9 0.969
SSTL25_I, II3
2.375 2.5 2.625 1.15 1.25 1.35
SSTL33_I, II3
3.135 3.3 3.465 1.3 1.5 1.7
HSTL15_I, II3
1.425 1.5 1.575 0.68 0.75 0.9
HSTL15_III1, 3 and IV1, 3 1.425 1.5 1.575 0.68 0.9 0.9
HSTL 18_I3
, II3
1.71 1.8 1.89 0.816 0.9 1.08
HSTL 18_ III1, 3, IV1, 3 1.71 1.8 1.89 0.816 1.08 1.08
GTL121, 3, GTLPLUS151, 3 — — — 0.882 1.0 1.122
LVDS — — — — — —
Mini-LVDS ——————
RSDS ——————
HYPT (Hyper Transport) ——————
LVPECL332, 3 3.135 3.3 3.465 — — —
BLVDS252, 3 2.375 2.5 2.625 — — —
MLVDS252, 3 2.375 2.5 2.625 — — —
SSTL18D_I3
, II3
1.71 1.8 1.89 — — —
SSTL25D_I3
, II3
2.375 2.5 2.625 — — —
SSTL33D_I3
, II3
3.135 3.3 3.465 — — —
HSTL15D_I3
, II3
1.425 1.5 1.575 — — —
HSTL18D_I3
, II3
1.71 1.8 1.89 — — —
1. Input only.
2. Inputs on chip. Outputs are implemented with the addition of external resisters.
3. Input for this standard does not depend on the value of VCCIO.3-5
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
PURESPEED I/O Single-Ended DC Electrical Characteristics
Over Recommended Operating Conditions
Input/Output
Standard
VIL VIH V
OL Max.
(V)
V
OH Min.
(V)
I
OL
(mA)
I
OH
Min. (V) Max. (V) Min. (V) Max. (V) (mA)
LVCMOS 33 -0.3 0.8 2 3.6 0.4 2.4 24, 16, 8 -24, -16, -8
0.2 VCCIO - 0.2 0.1 -0.1
LVTTL -0.3 0.8 2 3.6 0.4 2.4 24, 16, 8 -24, -16, -8
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 25 -0.3 0.7 1.7 2.65 0.4 VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 18 -0.3 0.35VCCIO 0.65VCCIO 2.65 0.4 VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 15 -0.3 0.35VCCIO 0.65VCCIO 2.65 0.4 VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4
0.2 VCCIO - 0.2 0.1 -0.1
LVCMOS 12 -0.3 0.35VCCIO 0.65VCCIO 2.65 0.3 VCCIO - 0.3 12, 8, 4, 2 -12, -8, -4, -2
0.2 VCCIO - 0.2 0.1 -0.1
PCIX15 -0.3 0.3VCCIO 0.5VCCIO 1.5 0.1VCCIO 0.9VCCIO 1.5 -0.5
PCI33 -0.3 0.3VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 -0.5
PCIX33 -0.3 0.35VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 -0.5
AGP-1X, AGP-2X -0.3 0.3VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 -0.5
SSTL3_I -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCIO - 1.1 8 -8
SSTS3_I OST2
-0.3 VREF - 0.2 VREF + 0.2 3.6 0.9 VCCIO - 1.3 8 -8
SSTL3_II -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCIO - 0.9 16 -16
SSTL3_II OST2
-0.3 VREF - 0.2 VREF + 0.2 3.6 0.9 VCCIO - 0.13 16 -16
SSTL2_I -0.3 VREF - 0.18 VREF + 0.18 2.65 0.54 VCCIO - 0.62 7.6 -7.6
SSTL2_I OST2
-0.3 VREF - 0.18 VREF + 0.18 2.65 0.73 VCCIO - 0.81 7.6 -7.6
SSTL2_II -0.3 VREF - 0.18 VREF + 0.18 2.65 0.35 VCCIO - 0.43 15.2 -15.2
SSTL2_II OST2
-0.3 VREF - 0.18 VREF + 0.18 2.65 0.73 VCCIO - 0.81 15.2 -15.2
SSTL18_I -0.3 VREF - 0.125 VREF + 0.125 2.65 0.28 VCCIO - 0.28 13.4 -13.4
SSTL18_II -0.3 VREF - 0.125 VREF + 0.125 2.65 0.28 VCCIO - 0.28 13.4 -13.4
HSTL15_I -0.3 VREF - 0.1 VREF + 0.1 2.65 0.4 VCCIO - 0.4 8 -8
HSTL15_II -0.3 VREF - 0.1 VREF + 0.1 2.65 0.4 VCCIO - 0.4 16 -16
HSTL15_III1 -0.3 VREF - 0.1 VREF + 0.1 2.65 N/A N/A N/A N/A
HSTL15_IV1 -0.3 VREF - 0.1 VREF + 0.1 2.65 N/A N/A N/A N/A
HSTL18_I -0.3 VREF - 0.1 VREF + 0.1 2.65 0.4 VCCIO - 0.4 9.6 -9.6
HSTL18_II -0.3 VREF - 0.1 VREF + 0.1 2.65 0.4 VCCIO - 0.4 19.2 -19.2
HSTL18_III1 -0.3 VREF - 0.1 VREF + 0.1 2.65 N/A N/A N/A N/A
HSTL18_IV1 -0.3 VREF - 0.1 VREF + 0.1 2.65 N/A N/A N/A N/A
GTL121
,
GTLPLUS151 -0.3 VREF - 0.2 VREF + 0.2 N/A N/A N/A N/A N/A
1. Input only.
2. Input with on-chip series termination.3-6
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
PURESPEED I/O Differential Electrical Characteristics
LVDS
Over Recommended Operating Conditions
Hyper Transport
Over Recommended Operating Conditions
Parameter
Symbol Parameter Description Test Conditions Min. Typ. Max. Units
VINP, VINM Input voltage 0 — 2.4 V
VTHD Differential input threshold +/-100 — — mV
V
CM Input common mode voltage 0.05 1.2 2.35 V
I
IN Input current Power on or power off — — +/-10 µA
V
OH Output high voltage for VOP or VOM RT
= 100 Ohm — 1.38 1.60 V
V
OL Output low voltage for VOP or VOM RT
= 100 Ohm 0.9V 1.03 — V
V
OD Output voltage differential (VOP - VOM), RT
= 100 Ohm 250 350 450 mV
ΔV
OD
Change in VOD between high and
low — — 50 mV
V
OS Output voltage offset (VOP - VOM)/2, RT
= 100 Ohm 1.125 1.20 1.375 V
ΔV
OS Change in VOS between H and L — — 50 mV
I
SAB Output short circuit current V
OD = 0V Driver outputs
shorted — — 12 mA
Note: Data is for 3.5mA differential current drive. Other differential driver current options are available.
Parameter Symbol Description Min. Typ. Max. Units
V
OD Differential output voltage 500 600 700 mV
ΔV
OD Change in VOD magnitude -15 — 15 mV
V
OCM Output common mode voltage 560 600 640 mV
ΔV
OCM Change in VOCM magnitude -15 — 15 mV
VID Input differential voltage 500 600 700 mV
ΔVID Input differential voltage -15 — 15 mV
VICM Input common mode voltage 500 600 700 mV
ΔVICM Change in VICM magnitude -15 — 15 mV
Note: Data is for 6mA differential current drive. Other differential driver current options are available.3-7
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Mini-LVDS
Over Recommended Operating Conditions
RSDS
Over Recommended Operating Conditions
Parameter Symbol Description Min. Typ. Max. Units
Z
O Single-ended PCB trace impedance 30 50 75 ohms
RT
Differential termination resistance 60 100 150 ohms
V
OD Output voltage, differential, |VOP - VOM| 300 — 600 mV
V
OS Output voltage, common mode, |VOP + VOM|/2 1 1.2 1.4 V
ΔV
OD Change in VOD, between H and L — — 50 mV
ΔVID Change in VOS, between H and L — — 50 mV
VTHD Input voltage, differential, |VINP - VINM| 200 — 600 mV
V
CM Input voltage, common mode, |VINP + VINM|/2 0.3+(VTHD/2) — 2.1-(VTHD/2)
T
R, TF
Output rise and fall times, 20% to 80% — — 500 ps
T
ODUTY Output clock duty cycle 45 — 55 %
TIDUTY Input clock duty cycle 40 — 60 %
Note: Data is for 6mA differential current drive. Other differential driver current options are available.
Parameter Symbol Description Min. Typ. Max. Units
V
OD Output voltage, differential, RT
= 100 ohms 100 200 600 mV
V
OS Output voltage, common mode 0.5 1.2 1.5 V
I
RSDS Differential driver output current 1 2 6 mA
VTHD Input voltage differential 100 — — mV
V
CM Input common mode voltage 0.3 — 1.5 V
T
R, TF
Output rise and fall times, 20% to 80% — 500 — ps
T
ODUTY Output clock duty cycle 45 50 55 %
Note: Data is for 2mA drive. Other differential driver current options are available.3-8
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode.
MLVDS
The LatticeSC devices support the MLVDS standard. This industry standard is emulated using controlled impedance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs.
MLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The
scheme shown in Figure 3-1 is one possible solution for bi-directional multi-point differential signals.
Figure 3-1. MLVDS Multi-Point Output Example
Table 3-1. MLVDS DC Conditions1
Over Recommended Operating Conditions
Nominal
Symbol Description Zo = 50 Zo = 70 Units
Z
OUT Output impedance 50 50 ohm
RTLEFT Left end termination 50 70 ohm
RTRIGHT Right end termination 50 70 ohm
V
OH Output high voltage 1.50 1.575 V
V
OL Output low voltage 1.00 0.925 V
V
OD Output differential voltage 0.50 0.65 V
V
CM Output common mode voltage 1.25 1.25 V
I
DC DC output current 20.0 18.5 mA
1. For input buffer, see LVDS table.
Heavily loaded backplane, effective Zo ~ 50 to 70 ohms differential
50 50
2.5V 2.5V
50 50
2.5V 2.5V
50
50
2.5V
2.5V
+
-
50
50
2.5V
2.5V
+
-
. . .
50-70 ohms, +/- 1% 50-70 ohms, +/- 1%
+ + - -
+
-
. . .3-9
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
BLVDS
The LatticeSC devices support BLVDS standard. This standard is emulated using controlled impedance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is
intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown
in Figure 3-2 is one possible solution for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Table 3-2. BLVDS DC Conditions1
Over Recommended Operating Conditions
Nominal
Symbol Description Zo = 45 Zo = 90 Units
Z
OUT Output impedance 100 100 ohm
RTLEFT Left end termination 45 90 ohm
RTRIGHT Right end termination 45 90 ohm
V
OH Output high voltage 1.375 1.48 V
V
OL Output low voltage 1.125 1.02 V
V
OD Output differential voltage 0.25 0.46 V
V
CM Output common mode voltage 1.25 1.25 V
I
DC DC output current 11.2 10.2 mA
1. For input buffer, see LVDS table.
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
100 100
2.5V 2.5V
100 100
2.5V 2.5V
100
100
2.5V
2.5V
+
-
100
100
2.5V
2.5V
+
-
. . .
45-90 ohms, +/- 1% 45-90 ohms, +/- 1%
+ -
+
-
. . .
% -
+ -3-10
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
LVPECL
The LatticeSC devices support differential LVPECL standard. This standard is emulated using controlled impedance complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme
shown in Figure 3-3 is one possible solution for point-to-point signals.
Figure 3-3. Differential LVPECL
Table 3-3. LVPECL DC Conditions1
Over Recommended Operating Conditions
For further information on LVPECL, BLVDS, MLVDS and other differential interfaces please see details of additional
technical documentation at the end of this data sheet.
On-die Differential Common Mode Termination
Symbol Description Nominal Units
Z
OUT Output impedance 16 ohm
RS
Driver series resistor 85 ohm
RP
Driver parallel resistor 150 ohm
RT
Receiver termination 100 ohm
V
OH Output high voltage 2.03 V
V
OL Output low voltage 1.27 V
V
OD Output differential voltage 0.76 V
V
CM Output common mode voltage 1.65 V
Z
BACK Back impedance 86 ohm
I
DC DC output current 12.6 mA
1. For input buffer, see LVDS table.
Symbol Description Min. Typ. Max. Units
CCMT Capacitance VCMT to GND — 40 — pF
Transmission line, Zo = 100 ohm differential
100
ohms
150
ohms
ON-chip OFF-chip
3.3V
3.3V
24mA
~16 ohms
24mA
~16 ohms
+
85 ohms
+/-1%
85 ohms
+/-1%
Zback
-3-11
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Typical Building Block Function Performance
Pin to Pin Performance (LVCMOS25 12 mA Drive)
Register-to-Register Performance
Switching Characteristics
All devices are 100% functionally tested. Listed below are representative values of internal and external timing
parameters. For more specific, more precise, and worst-case guaranteed data at a particular temperature and voltage use the values reported by the static timing analyzer in the ispLEVER design tool from Lattice and back-annotate to the simulation net list.
Function -7 -6 -5 Units
Basic Functions
32-bit Decoder 6.02 6.49 7.00 ns
Combinatorial (Pin to LUT to Pin) 4.91 5.24 5.56 ns
Embedded Memory Functions (Single Port RAM)
Pin to EBR Input Register Setup (Global Clock) 1.42 1.50 1.58 ns
EBR Output Clock to Pin (Global Clock) 7.72 8.53 9.67 ns
Distributed (PFU) RAM (Single Port RAM)
Pin to PFU RAM Register Setup (Global Clock) 1.70 1.84 2.05 ns
PFU RAM Clock to Pin (Global Clock) 5.66 6.19 6.73 ns
Function -7 -6 -5 Units
Basic Functions
32-Bit Decoder 455 432 398 MHz
64-Bit Decoder 405 381 368 MHz
16:1 MUX 524 487 447 MHz
32:1 MUX 507 458 424 MHz
16-Bit Adder 567 477 481 MHz
64-Bit Adder 325 296 270 MHz
16-Bit Counter 690 622 565 MHz
64-Bit Counter 355 320 291 MHz
32x8 SP RAM (PFU, Output Registered) 748 686 602 MHz
128x8 SP RAM (PFU, Output Registered) 544 472 471 MHz
Embedded Memory Functions
Single Port RAM (512x36 Bits) 359 341 325 MHz
True Dual Port RAM 1024x18 Bits (No EBR Out Reg) 314 279 265 MHz
True dual port RAM 1024x18 Bits (EBR Reg) 359 341 325 MHz
FIFO port (A: x36 bits, B: x9 Bits, No EBR Out Reg) 315 290 243 MHz
FIFO port (A: x36 bits, B: x9 Bits, EBR Reg) 361 342 325 MHz
True DP RAM Width Cascading (1024x72) 346 285 280 MHz
DSP Functions
9x9 1-stage Multiplier 196 176 158 MHz
18x18 1-Stage Mutiplier 140 126 109 MHz
9x9 3-Stage Pipelined Multiplier 347 332 281 MHz
18x18 4-Stage Pipelined Mutiplier 298 280 250 MHz
9x9 Constant Multiplier 359 341 325 MHz3-12
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
LatticeSC External Switching Characteristics4
Over Recommended Operating Conditions
Parameter Description
-7 -6 -5
Min. Max. Min. Max. Min. Max. Units
General I/O Pin Parameters (Using Primary Clock without PLL)2
t
CO
Global Clock Input to Output - PIO Output Register — 5.00 — 5.54 — 6.08 ns
t
SU
Global Clock Input Setup - PIO Input Register
without fixed input delay 0.00 — 0.00 — 0.00 — ns
t
H
Global Clock Input Hold - PIO Input Register without fixed input delay 1.14 — 1.14 — 1.14 — ns
t
SU_IDLY
Global Clock Input Setup - PIO Input Register
with input delay 0.68 — 0.83 — 0.73 — ns
t
H_IDLY
Global Clock Input Hold - PIO Input Register with
input delay 0.00 — 0.00 — 0.00 — ns
f
MAX_PFU Global Clock frequency of PFU register — 700 — 700 — 700 MHz
f
MAX_IO Global Clock frequency of I/O register — 1000 — 1000 — 1000 MHz
t
GC_SKEW Global Clock skew 89 — 103 — 116 — ps
General I/O Pin Parameters (Using Primary Clock with PLL)1, 2
t
CO
Global Clock Input to Output - PIO Output Register — 4.02 — 4.42 — 4.83 ns
t
SU
Global Clock Input Setup - PIO Input Register
without fixed input delay 0.00 — 0.00 — 0.00 — ns
t
H
Global Clock Input Hold - PIO Input Register without fixed input delay 0.60 — 0.60 — 0.60 — ns
* Note: No PLL delay tuning (clock injection removal mode), system clock feedback.
General I/O Pin Parameters (Using Edge Clock without PLL)2
t
CO Edge Clock Input to Output - PIO Output Register — 4.14 — 4.60 — 5.08 ns
t
SU
Edge Clock Input Setup - PIO Input Register without fixed input delay 0.00 — 0.00 — 0.00 — ns
t
H
Edge Clock Input Hold - PIO Input Register without fixed input delay 0.48 — 0.48 — 0.48 — ns
t
SU_IDLY
Edgel Clock Input Setup - PIO Input Register with
input delay 0.53 — 0.66 — 0.78 — ns
t
H_IDLY
Edge Clock Input Hold - PIO Input Register with
input delay 0.00 — 0.00 — 0.00 — ns
t
EC_SKEW Edge Clock skew 28 — 32 — 36 — ps
General I/O Pin Parameters (Using Latch FF without PLL)2
t
SU
Latch FF, Input Setup - PIO Input Register without
fixed input delay 0.00 — 0.00 — 0.00 — ns
t
H
Latch FF, Input Hold - PIO Input Register without
fixed input delay 0.51 — 0.51 — 0.51 — ns
t
SU_IDLY
Latch FF, Input Setup - PIO Input Register with
input delay 0.71 — 0.83 — 0.96 — ns
t
H_IDLY
Latch FF, Input Hold - PIO Input Register with
input delay 0.00 — 0.00 — 0.00 — ns
1. No PLL delay tuning (clock injection removal mode, system clock feedback).
2. Using LVCMOS25 12mA I/O.
3. A complete listing of Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.
4. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0”
is listed, there is no positive hold time.3-13
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
LatticeSC Internal Timing Parameters1, 2
Over Recommended Operating Conditions
Parameter Symbol Description
-7 -6 -5
Min. Max. Min. Max. Min. Max. Units
PFU Logic Mode Timing
t
LUT4_PFU CTOF_DEL LUT4 delay (A to D inputs
to F output) — 0.046 — 0.050 — 0.054 ns
t
LUT5_PFU MTOOFX_DEL LUT5 delay (inputs to output) — 0.157 — 0.174 — 0.192 ns
t
LUT6_PFU CTOOFX_DEL LUT6 delay (A to D inputs
to OFX output) — 0.130 — 0.144 — 0.157 ns
t
LSR_PFU LSR_DEL Set/Reset to output
(asynchronous) — 0.393 — 0.433 — 0.474 ns
t
SUM_PFU M_SET Clock to Mux (M0,M1) input
setup time 0.118 — 0.133 — 0.148 — ns
t
HM_PFU M_HLD Clock to Mux (M0,M1) input
hold time 0.000 — 0.000 — 0.000 — ns
t
SUD_PFU DIN_SET Clock to D input setup time -0.025 — -0.026 — -0.027 — ns
t
HD_PFU DIN_HLD Clock to D input hold time 0.000 — 0.000 — 0.000 — ns
t
CK2Q_PFU REG_DEL Clock to Q delay, D-type
register configuration — 0.232 — 0.256 — 0.279 ns
t
LE2Q_PFU LTCH_DEL Clock to Q delay latch
configuration — 0.305 — 0.336 — 0.367 ns
t
LD2Q_PFU TLTCH_DEL D to Q throughput delay
when latch is enabled — 0.311 — 0.344 — 0.376 ns
PFU Memory Mode Timing
t
CORAM_PFU CLKTOF_DEL Clock to Output — 0.596 — 0.660 — 0.724 ns
t
SUDATA_PFU DIN_SET Data Setup Time -0.025 — -0.026 — -0.027 — ns
t
HDATA_PFU DIN_HLD Data Hold Time 0.000 — 0.000 — 0.000 — ns
t
SUADDR_PFU WAD_SET Address Setup Time -0.183 — -0.199 — -0.215 — ns
t
HADDR_PFU WAD_HLD Address Hold Time 0.114 — 0.126 — 0.138 — ns
t
SUWREN_PFU WE_SET Write/Read Enable Setup
Time 0.014 — 0.019 — 0.024 — ns
t
HWREN_PFU WE_HLD Write/Read Enable Hold
Time 0.081 — 0.087 — 0.094 — ns
PIC Timing
PIO Input/Output Buffer Timing
t
IN_PIO IN_DEL Input Buffer Delay
(LVCMOS25) 0.559 0.839 0.635 1.036 0.686 1.309 ns
t
OUT_PIO DOPADI_DEL Output Buffer Delay
(LVCMOS25) 1.946 4.254 2.154 5.436 2.362 6.619 ns
IOLOGIC Input/Output Timing
t
SUI_PIO DIN_SET Input Register Setup Time
(Data Before Clock) -0.073 — -0.077 — -0.082 — ns
t
HI_PIO DIN_HLD Input Register Hold Time
(Data after Clock) 0.000 — 0.000 — 0.000 — ns
t
COO_PIO CK_DEL Output Register Clock to
Output Delay — 0.532 — 0.580 — 0.639 ns
t
SUCE_PIO CE_SET Input Register Clock
Enable Setup Time — 0.000 — 0.000 — 0.000 ns3-14
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
t
HCE_PIO CE_HLD Input Register Clock
Enable Hold Time — 0.134 — 0.148 — 0.161 ns
t
SULSR_PIO LSR_SET Set/Reset Setup Time 0.059 — 0.061 — 0.063 — ns
t
HLSR_PIO LSR_HLD Set/Reset Hold Time 0.000 — 0.000 — 0.000 — ns
t
LE2Q_PIO CK_DEL Input Register Clock to Q
delay latch configuration — 0.348 — 0.379 — 0.410 ns
t
LD2Q_PIO DIN_DEL
Input Registe D to Q
throughput delay when
latch is enabled
— 0.600 — 0.658 — 0.717 ns
EBR Timing
t
CO_EBR CK_Q_DEL Clock (Read) to output from
Address or Data — 2.004 — 2.191 — 2.377 ns
t
COO_EBR CK_Q_DEL Clock (Write) to output from
EBR output Register — 2.004 — 2.191 — 2.377 ns
t
SUDATA_EBR D_CK_SET Setup Data to EBR Memory (Write clk) 0.095 — 0.088 — 0.082 — ns
t
HDATA_EBR D_CK_HLD Hold Data to EBR Memory
(Write clk) 0.219 — 0.254 — 0.289 — ns
t
SUADDR_EBR A_CK_SET Setup Address to EBR
Memroy (Write clk) 0.074 — 0.060 — 0.047 — ns
t
HADDR_EBR A_CK_HLD Hold Address to EBR Memory (Write clk) 0.218 — 0.255 — 0.291 — ns
t
SUWREN_EBR CE_CK_SET
Setup Write/Read Enable
to EBR Memory (Write/
Read clk)
0.233 — 0.230 — 0.226 — ns
t
HWREN_EBR CE_CK_HLD
Hold Write/Read Enable to
EBR Memory (write/read
clk)
0.076 — 0.096 — 0.116 — ns
t
SUCE_EBR CS_CK_SET
Clock Enable Setup Time to
EBR Output Register
(Read clk)
0.271 — 0.274 — 0.276 — ns
t
HCE_EBR CS_CK_HLD
Clock Enable Hold Time to
EBR Output Register
(Read clk)
0.024 — 0.040 — 0.055 — ns
t
RSTO_EBR RESET_Q_DEL
Reset To Output Delay
Time from EBR Output
Register (asynchronous)
— 0.663 — 0.736 — 0.809 ns
Cycle Boosting Timing
t
DEL1 DEL1 Cycle boosting delay 1
applies to PIO, PFU, EBR — 0.498 — 0.534 — 0.570 ns
t
DEL2 DEL2 Cycle boosting delay 2
applies to PIO, PFU, EBR — 0.956 — 1.022 — 1.090 ns
t
DEL3 DEL3 Cycle boosting delay 3
applies to PIO, PFU, EBR — 1.418 — 1.514 — 1.612 ns
1. A complete listing of Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.
2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0”
is listed, there is no positive hold time.
LatticeSC Internal Timing Parameters1, 2 (Continued)
Over Recommended Operating Conditions
Parameter Symbol Description
-7 -6 -5
Min. Max. Min. Max. Min. Max. Units3-15
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Timing Diagrams
PFU Timing Diagrams
Figure 3-4. Slice Single/Dual Port Write Cycle Timing
Notes:
• Rising Edge for latching WREN, WAD and DATAIN.
• WREN must continue past falling edge clock.
• Data output occurs on negative edge.
Figure 3-5. Slice Single/Dual Port Read Cycle Timing
D
D
AD
Old Data
CK
WRE
DI
DO
AD
D
AD
Old Data
CK
WRE
DO
AD3-16
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
EBR Memory Timing Diagrams
Figure 3-6. Read Mode
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.
Figure 3-7. Read Mode with Input Registers Only
A0 A1 A0 A1
D0 D1
A0
t
ACCESS t
ACCESS t
ACCESS t
ACCESS
t
SU t
H
D0 D1 D0
CLKA
CSA
WEA
ADA
DIA
DOA
A0 A1 A0 A1
D0 D1
Mem(n) data from previous read D0 D1
output is only updated during a read cycle
t
SU t
H
t
ACCESS t
ACCESS
CLKA
CSA
WEA
ADA
DIA
DOA3-17
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 3-8. Read Mode with Input and Output Registers
Figure 3-9. Read Before Write (SP Read/Write on Port A, Input Registers Only)
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.
A0 A1 A0 A0
D0 D1
D0 D0
output is only updated during a read cycle
A1
D1
Mem(n) data from previous read D0 D1
Mem(n) data from previous read
DOA
t
SU t
H
t
ACCESS t
ACCESS
CLKA
CSA
WEA
ADA
DIA
DOA
DOA (Registered)
A0 A1 A0 A1
D0 D1
D2
A0
D2 D3 D1
old A0 Data old A1 Data D0 D1
t
SU t
H
t
ACCESS t
ACCESS t
ACCESS t
ACCESS t
ACCESS
CLKA
CSA
WEA
ADA
DIA
DOA3-18
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 3-10. Write Through (SP Read/Write On Port A, Input Registers Only)
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.
Figure 3-11. FIFO Reset Waveform
Note: RE and WE must be deactivated tRSU before the Positive FIFO reset edge and enabled tRSH after the FIFO reset negative edge.
A0 A1 A0
D0 D1
D4
t
SU
t
ACCESS t
ACCESS t
ACCESS
t
H
D2 D3 D4
D0 D1 D2 Data from Prev Read
or Write
Three consecutive writes to A0
D3
t
ACCESS
CLKA
CSA
WEA
ADA
DIA
DOA
t
RW
t
RSU
t
RSU
t
RSF
t
RSF
t
RSH
Asynchronous RESET, RESET pulse width (tRW),
RESET to Flag valid (tRSF), RESET hold time (tRSH)
t
RSH
RE
RST
EF, AE flags
WE
FF, AF flags
DO3-19
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 3-12. Read Pointer Reset Waveform
Note: RE and WE must be deactivated tRSU before the Positive FIFO reset edge and enabled tRSH after the FIFO reset negative edge.
Figure 3-13. Waveforms First Read after Full Flag
t
RW
t
RSU
t
RSF
t
RSU t
RSH
t
ACCESS_F
t
ACCESS_E
t
RSH
RESET pulse width (tRW), RESET to Flag valid (tRSF),
RST_B RESET hold time (tRSH)
RE
RCLK
EF, AE flags
WE
WCLK
FF, AF flags
First Read
Last Write (FIFO FULL)
t
SU1
t
CO
t
CO
t
SU1 t
H1
t
SKEW
t
H1
WCLK
RE
RCLK
FF (flag)
WE
CS3-20
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Figure 3-14. Waveform First Write after Empty Flag
First Write
Last Read (FIFO Empty)
RCLK
WE
WCLK
EF (flag)
RE
CS
t
SU1
t
SU1
t
CO
t
SKEW t
CO
t
H1
t
H13-21
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
LatticeSC Family Timing Adders
Over Recommended Operating Conditions
Buffer Type Description
-7 -6 -5
Min. Max. Min. Max. Min. Max. Units
LVDS LVDS -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns
RSDS RSDS -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns
BLVDS25 BLVDS -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns
MLVDS25 MLVDS -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns
HYPT Hypertransport -0.021 -0.03 -0.002 -0.005 0.02 0.017 ns
LVPECL33 LVPECL -0.032 -0.032 -0.011 -0.011 0.009 0.009 ns
HSTL18_I HSTL_18 class I -0.013 -0.015 0.015 0.007 0.042 0.029 ns
HSTL18_II HSTL_18 class II -0.013 -0.015 0.015 0.007 0.042 0.029 ns
HSTL18_III HSTL_18 class III -0.017 -0.019 0.008 0.002 0.032 0.023 ns
HSTL18_IV HSTL_18 class IV -0.017 -0.019 0.008 0.002 0.032 0.023 ns
HSTL18D_I Differential HSTL 18 class I 0.005 0.001 0.029 0.024 0.052 0.046 ns
HSTL18D_II Differential HSTL 18 class II 0.005 0.001 0.029 0.024 0.052 0.046 ns
HSTL15_I HSTL_15 class I -0.006 -0.017 0.026 -0.001 0.057 0.014 ns
HSTL15_II HSTL_15 class II -0.006 -0.017 0.026 -0.001 0.057 0.014 ns
HSTL15_III HSTL_15 class III -0.013 -0.015 0.015 0.007 0.042 0.029 ns
HSTL15_IV HSTL_15 class IV -0.013 -0.015 0.015 0.007 0.042 0.029 ns
HSTL15D_I Differential HSTL 15 class I -0.022 -0.023 0 -0.01 0.022 0.003 ns
HSTL15D_II Differential HSTL 15 class II -0.022 -0.023 0 -0.01 0.022 0.003 ns
SSTL33_I SSTL_3 class I -0.037 -0.063 -0.182 -0.314 -0.326 -0.565 ns
SSTL33_II SSTL_3 class II -0.037 -0.063 -0.182 -0.314 -0.326 -0.565 ns
SSTL33D_I Differential SSTL_3 class I 0.012 0.012 0.034 0.028 0.055 0.043 ns
SSTL33D_II Differential SSTL_3 class II 0.012 0.012 0.034 0.028 0.055 0.043 ns
SSTL25_I SSTL_2 class I 0.003 -0.009 0.03 0.011 0.058 0.03 ns
SSTL25_II SSTL_2 class II 0.003 -0.009 0.03 0.011 0.058 0.03 ns
SSTL25D_I Differential SSTL_2 class I 0.005 0 0.031 0.023 0.056 0.046 ns
SSTL25D_II Differential SSTL_2 class II 0.005 0 0.031 0.023 0.056 0.046 ns
SSTL18_I SSTL_18 class I -0.013 -0.015 0.015 0.007 0.042 0.029 ns
SSTL18_II SSTL_18 class II -0.013 -0.015 0.015 0.007 0.042 0.029 ns
SSTL18D_I Differential SSTL_18 class I 0.005 0.001 0.029 0.024 0.052 0.046 ns
SSTL18D_II Differential SSTL_18 class II 0.005 0.001 0.029 0.024 0.052 0.046 ns
LVTTL33 LVTTL 0.035 0.035 -0.05 -0.05 -0.134 -0.134 ns
LVCMOS33 LVCMOS 3.3 0.035 0.035 -0.05 -0.05 -0.134 -0.134 ns
LVCMOS25 LVCMOS 2.5 0 0 0 0 0 0 ns
LVCMOS18 LVCMOS 1.8 -0.07 -0.07 -0.087 -0.087 -0.105 -0.105 ns
LVCMOS15 LVCMOS 1.5 -0.135 -0.135 -0.188 -0.188 -0.241 -0.241 ns
LVCMOS12 LVCMOS 1.2 -0.245 -0.245 -0.367 -0.367 -0.49 -0.49 ns
PCI33 PCI 0.035 -0.063 -0.05 -0.314 -0.134 -0.565 ns
PCIX33 PCI-X 3.3 0.035 -0.063 -0.05 -0.314 -0.134 -0.565 ns
PCIX15 PCI-X 1.5 -0.006 -0.017 0.026 -0.001 0.057 0.014 ns
AGP1X33 AGP-1X 3.3 0.035 -0.063 -0.05 -0.314 -0.134 -0.565 ns
AGP2X33 AGP-2X -0.037 -0.063 -0.182 -0.314 -0.326 -0.565 ns3-22
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
GTLPLUS15 GTLPLUS15 -0.013 -0.018 0.012 0.003 0.037 0.024 ns
GTL12 GTL12 -0.065 -0.074 -0.009 -0.049 0.056 -0.032 ns
LVDS LVDS 0.022 -1.3932 0.0255 -1.602 0.029 -1.81 ns
RSDS RSDS 0.022 -1.3932 0.0255 -1.602 0.029 -1.81 ns
BLVDS25 BLVDS 0.362 0.362 0.394 0.394 0.427 0.427 ns
MLVDS25 MLVDS 0.134 0.134 0.136 0.136 0.138 0.138 ns
LVPECL33 LVPECL -0.125 -6.5322 -0.1435 -7.512 -0.163 -8.491 ns
HYPT Hypertransport -0.007 -1.5752 -0.0085 -1.812 -0.009 -2.048 ns
HSTL18_I HSTL_18 class I 0.057 0.021 0.068 0.014 0.078 0.007 ns
HSTL18_II HSTL_18 class II 0.144 0.062 0.142 0.094 0.14 0.127 ns
HSTL18D_I Differential HSTL 18 class I 0.057 0.021 0.068 0.014 0.078 0.007 ns
HSTL18D_II Differential HSTL 18 class II 0.144 0.062 0.142 0.094 0.14 0.127 ns
HSTL15_I HSTL_15 class I 0.095 0.064 0.075 0.062 0.061 0.055 ns
HSTL15_II HSTL_15 class II 0.126 0.107 0.118 0.107 0.11 0.097 ns
HSTL15D_I Differential HSTL 15 class I 0.095 0.064 0.075 0.062 0.061 0.055 ns
HSTL15D_II Differential HSTL 15 class II 0.126 0.107 0.118 0.107 0.11 0.097 ns
SSTL33_I SSTL_3 class I 0.179 0.179 0.169 0.169 0.159 0.159 ns
SSTL33_II SSTL_3 class II 0.199 0.199 0.193 0.193 0.187 0.187 ns
SSTL33D_I Differential SSTL_3 class I 0.179 0.179 0.169 0.169 0.159 0.159 ns
SSTL33D_II Differential SSTL_3 class II 0.199 0.199 0.193 0.193 0.187 0.187 ns
SSTL25_I SSTL_2 class I 0.061 0.026 0.067 0.033 0.073 0.04 ns
SSTL25_II SSTL_2 class II 0.07 0.063 0.075 0.066 0.081 0.069 ns
SSTL25D_I Differential SSTL_2 class I 0.061 0.026 0.067 0.033 0.073 0.04 ns
SSTL25D_II Differential SSTL_2 class II 0.07 0.063 0.075 0.066 0.081 0.069 ns
SSTL18_I SSTL_2 class I 0.111 0.078 0.1 0.086 0.094 0.089 ns
SSTL18_II SSTL_2 class II 0.142 0.087 0.132 0.098 0.122 0.099 ns
SSTL18D_I Differential SSTL_2 class I 0.111 0.078 0.1 0.086 0.094 0.089 ns
SSTL18D_II Differential SSTL_2 class II 0.142 0.087 0.132 0.098 0.122 0.099 ns
LVTTL33_8mA LVTTL 8mA drive -0.112 -0.112 -0.203 -0.203 -0.293 -0.293 ns
LVTTL33_16mA LVTTL 16mA drive 0.094 0.094 0.034 0.034 -0.026 -0.026 ns
LVTTL33_24mA LVTTL 24mA drive 0.168 0.168 0.119 0.119 0.07 0.07 ns
LVCMOS33_8mA LVCMOS 3.3 8mA drive -0.112 -0.112 -0.203 -0.203 -0.293 -0.293 ns
LVCMOS33_16mA LVCMOS 3.3 16mA drive 0.094 0.094 0.034 0.034 -0.026 -0.026 ns
LVCMOS33_24mA LVCMOS 3.3 24mA drive 0.168 0.168 0.119 0.119 0.07 0.07 ns
LVCMOS25_4mA LVCMOS 2.5 4mA drive -0.144 -0.144 -0.154 -0.154 -0.163 -0.163 ns
LVCMOS25_8mA LVCMOS 2.5 8mA drive 0 0 0 0 0 0 ns
LVCMOS25_12mA LVCMOS 2.5 12mA drive 0.041 0.041 0.044 0.044 0.048 0.048 ns
LVCMOS25_16mA LVCMOS 2.5 16mA drive 0.065 0.065 0.07 0.07 0.075 0.075 ns
LVCMOS25_OD LVCMOS 2.5 open drain -0.022 -0.283 -0.014 -0.263 -0.006 -0.244 ns
LVCMOS18_4mA LVCMOS 1.8 4mA drive -0.135 -0.135 -0.173 -0.173 -0.211 -0.211 ns
LVCMOS18_8mA LVCMOS 1.8 8mA drive 0.006 0.006 0.001 0.001 -0.004 -0.004 ns
LatticeSC Family Timing Adders (Continued)
Over Recommended Operating Conditions
Buffer Type Description
-7 -6 -5
Min. Max. Min. Max. Min. Max. Units3-23
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
LVCMOS18_12mA LVCMOS 1.8 12mA drive 0.053 0.053 0.058 0.058 0.063 0.063 ns
LVCMOS18_16mA LVCMOS 1.8 16mA drive 0.082 0.082 0.086 0.086 0.091 0.091 ns
LVCMOS18_OD LVCMOS 1.8 open drain 0.032 -0.22 0.002 -0.26 0.001 -0.301 ns
LVCMOS15_4mA LVCMOS 1.5 4mA drive -0.081 -0.081 -0.167 -0.167 -0.252 -0.252 ns
LVCMOS15_8mA LVCMOS 1.5 8mA drive 0.062 0.062 0.014 0.014 -0.033 -0.033 ns
LVCMOS15_12mA LVCMOS 1.5 12mA drive 0.056 0.056 0.041 0.041 0.026 0.026 ns
LVCMOS15_16mA LVCMOS 1.5 16mA drive 0.085 0.085 0.073 0.073 0.061 0.061 ns
LVCMOS15_OD LVCMOS 1.5 open drain 0.04 -0.27 0.002 -0.305 -0.035 -0.34 ns
LVCMOS12_2mA LVCMOS 1.2 2mA drive -0.136 -0.136 -0.229 -0.229 -0.321 -0.321 ns
LVCMOS12_4mA LVCMOS 1.2 4mA drive 0.018 0.018 -0.042 -0.042 -0.101 -0.101 ns
LVCMOS12_8mA LVCMOS 1.2 8mA drive 0.08 0.08 0.02 0.02 -0.041 -0.041 ns
LVCMOS12_12mA LVCMOS 1.2 12mA drive 0.112 0.112 0.051 0.051 -0.011 -0.011 ns
LVCMOS12_OD LVCMOS 1.2 open drain -0.013 -0.366 -0.054 -0.39 -0.094 -0.413 ns
PCI33 PCI 0.0205 0.1589 0.0236 0.1822 0.027 0.206 ns
PCIX33 PCI-X 3.3 0.0205 0.1589 0.0236 0.1822 0.027 0.206 ns
PCIX15 PCI-X 1.5 0.107 0.107 0.107 0.107 0.108 0.108 ns
AGP1X33 AGP-1X 3.3 0.0205 0.1589 0.0236 0.1822 0.027 0.206 ns
AGP2X33 AGP-2X 0.0205 0.1589 0.0236 0.1822 0.027 0.206 ns
LatticeSC Family Timing Adders (Continued)
Over Recommended Operating Conditions
Buffer Type Description
-7 -6 -5
Min. Max. Min. Max. Min. Max. Units3-24
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter Description Conditions Min. Typ Max. Units
f
IN Input Clock Frequency (CLKI, CLKFB) 15 — 1000 MHz
f
OUT
Output Clock Frequency (CLKOP,
CLKOS) 1.5625 — 1000 MHz
f
VCO PLL VCO Frequency 100 — 1000 MHz
f
PFD Phase Detector Input Frequency 15 — 700 MHz
AC Characteristics
t
DT Output Clock Duty Cycle Default duty cycle selected
(at 50% levels) 45 — 55 %
t
OPJIT Output Clock Period Jitter
f
REF ≥ 50MHz — — 0.02 UI
f
REF < 50MHz — — 0.01m UI/VCO
(MHz) UI
t
CPJIT Output Clock Cycle-to-Cycle Jitter
Without feedback dividers — — 0.03 UI
With feedback dividers — — 150 ps
t
SKEW
Output Clock-to-Clock Skew (Between
Two Outputs with the Same Phase Setting)
— — 20 ps
t
LOCK PLL Lock-in Time — — 1 ms
t
IPJIT Input Clock Period Jitter — — +/- 250 ps
t
HI Input Clock High Time At 80% level 350 — — ps
t
LO Input Clock Low Time At 20% level 350 — — ps
t
RSWA Analog Reset Signal Pulse Width 100 — — ns
t
RSWD Digital Reset Signal Pulse Width 3 — — ns
t
DEL Timeshift Delay Step Size — 80 — ps
t
RANGE Timeshift Delay Range — +/- 560 — ps
f
SS Spread Spectrum Modulation Frequency 30 — 500 KHz
% Spread Percentage Downspread for SS Mode 1 — 3 %3-25
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
sysCLOCK DLL Timing
Over Recommended Operating Conditions
Parameter Description Conditions Min. Typ. Max. Units
f
IN Input Clock Frequency (CLKI, CLKFB) 100 — 700 MHz
f
OUTOP Output Clock Frequency (CLKOP) 100 — 700 MHz
f
OUTOS Output Clock Frequency (CLKOS) 25 — 700 MHz
AC Characteristics
t
DUTY Output Clock Duty Cycle
Output Clock Duty Cycle (at 50%
levels, 50% duty cycle input clock,
duty cycle correction turned off,
time reference delay mode)
38 — 62 %
t
DUTYRD Output Clock Duty Cycle
Output Clock Duty Cycle (at 50%
levels, arbitrary duty cycle input
clock, duty cycle correction turned
on, time reference delay mode)
45 — 55 %
t
DUTYCIR Output Clock Duty Cycle
Output Clock Duty Cycle (at 50%
levels, arbitrary duty cycle input
clock, duty cycle correction turned
on, clock injection removal mode)
40 — 60 %
t
OPJIT Output Clock Period Jitter — — 200 ps
t
CPJIT Output Clock Cycle-to-Cycle Jitter — — 200 ps
t
SKEW
Output Clock to Clock Skew (Between
Two Outputs with the Same Phase
Setting)
— — 100 ps
t
LOCK DLL Lock-in Time 8 — 18500 cycles
t
IPJIT Input Clock Period Jitter — — +/- 250 ps
t
HI Input Clock High Time At 80% level 500 — — ps
t
LO Input Clock Low Time At 20% level 500 — — ps
t
RSWD Reset Signal Pulse Width 3 — — ns
t
DEL Timeshift Delay Step Size 25 42 90 ps3-26
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
LatticeSC sysCONFIG Port Timing
Over Recommended Operating Conditions
Parameter Description Min. Max. Units
General Configuration Timing
t
SMODE M[3:0] Setup Time to INITN High 0 — ns
t
HMODE M[3:0] Hold Time from INITN High 600 — ns
t
RW RESETN Pulse Width Low to Start Reconfiguration (1.2 V) 50 (or 100 at
0.95V) — ns
t
PGW PROGRAMN Pulse Width Low to Start Reconfiguration (1.2 V) 50 (or 100 at
0.95V) — ns
f
ESB_CLK_FRQ System Bus ESB_CLK Frequency (No Wait States) — 133 MHz
sysCONFIG Master Serial Configuration Mode
t
SMS DIN Setup Time 4.4 — ns
t
HMS DIN Hold Time 0 — ns
f
CMS CCLK Frequency (No Divider) 90 190 MHz
f
C_DIV CCLK Frequency (Div 128) 0.70 1.48 MHz
t
D CCLK to DOUT Delay — 7.5 ns
sysCONFIG Master Parallel Configuration Mode
t
AVMP RCLK to Address Valid — 10 ns
t
SMP D[7:0] Setup Time to RCLK High 6 — ns
t
HMP D[7:0] Hold Time to RCLK High 0 — ns
t
CLMP RCLK Low Time 8 190 MHz
t
CHMP RCLK High Time 0.63 1.48 MHz
t
DMP CCLK to DOUT — 7.5 ns
sysCONFIG Asynchronous Peripheral Configuration Mode
t
WRAP WRN, CS0N and CS1 Pulse Width 5 - ns
t
SAP D[7:0] Setup Time 1.5 - ns
t
RDYAP RDY Delay — 8 ns
t
BAP RDY Low 1 8 CCLK
periods
t
WR2AP Earliest WRN After RDY Goes High 0 — ns
t
DENAP RDN to D[7:0] Enable/Disable — 7.5 ns
t
DAP CCLK to DOUT — 7.5 ns
sysCONFIG Slave Serial Configuration Mode
t
SSS DIN Setup Time 5.2 — ns
t
HSS DIN Hold Time 0 — ns
t
CHSS CCLK High Time 3.75 — ns
t
CLSS CCLK Low Time 3.75 — ns
f
CSS CCLK Frequency — 150 MHz
t
DSS CCLK to DOUT — 7.5 ns
sysCONFIG Slave Parallel Configuration Mode
t
S1SP CS0N, CS1, WRN Setup Time 5.2 — ns
t
H1SP CS0N, CS1, WRN Hold Time 0 — ns
t
S2SP D[7:0] Setup Time 5.2 — ns
t
H2SP D[7:0] Hold Time 0 — ns
t
CHSP CCLK High Time 3.75 — ns3-27
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
sysCONFIG MPI Port
t
CL CCLK Low Time 3.75 — ns
f
CSP CCLK Frequency — 150 MHz
sysCONFIG Readback Timing
t
SRB RDCFGN to CCLK Setup Time 5.2 — ns
t
RBA RDCFGN High Width to Abort Readback 2 — CCLK
Cycles
t
CLRB CCLK Low Time 3.33 — ns
t
CHRB CCLK High Time 3.33 — ns
f
CRB CCLK Frequency — 150 MHz
t
DRB CCLK to RDDATA Delay — 7.5 ns
Parameter Description
-7 -6 -5
Min. Max. Min. Max. Min. Max. Units
t
MPICTRL_SET
MPI Control (MPCSTRBN, MPCWRN,
MPCCLK, etc.) to MPCCLK Setup Time 4.9 — 5.2 — 5.5 — ns
t
MPIADR_SET MPI Address to MPCCLK Setup Time 3.9 — 4.2 — 4.5 — ns
t
MPIDAT_SET MPI Write Data to MPCCLK Setup Time 4.9 — 5.2 — 5.5 — ns
t
MPIDPAR_SET
MPI Write Parity Data to MPCCLK Setup
Time 3.9 — 4.2 — 4.5 — ns
t
MPI_HLD All Hold Times 0 — 0 — 0 — ns
t
MPICTRL_DEL
MPCCLK to MPI Control (MPCTA, MPCTEA, MPCRETRY) — 5.6 — 6.7 — 8.7 ns
t
MPIDAT_DEL MPCCLK to MPI Data — 5.6 — 6.7 — 8.7 ns
t
MPIDPAR_DEL MPCCLK to MPI Parity Data — 4.9 — 5.7 — 7.7 ns
f
MPI_CLK_FRQ MPCCLK Frequency — 100 — 83 — 66 MHz
LatticeSC sysCONFIG Port Timing (Continued)
Over Recommended Operating Conditions
Parameter Description Min. Max. Units3-28
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Boundary Scan Timing Specifications
Over Recommended Operating Conditions
Symbol Parameter Min. Max. Units
f
MAX — 25 MHz
t
BTCP TCK [BSCAN] Clock Pulse Width 40 — ns
t
BTCPH TCK [BSCAN] Clock Pulse Width High 50 — mV/ns
t
BTCPL TCK [BSCAN] Clock Pulse Width Low — 10 ns
t
BTS TCK [BSCAN] Setup Time — 10 ns
t
BTH TCK [BSCAN] Hold Time 8 — ns
t
BTRF TCK [BSCAN] Rise/Fall Time 10 — ns
t
BTCO TAP Controller Falling Edge of Clock to Valid Output 20 — ns
t
BTCODIS TAP Controller Falling Edge of Clock to Valid Disable 20 — ns
t
BTCOEN TAP Controller Falling Edge of Clock to Valid Enable — 10 ns
t
BTCRS BSCAN Test Capture Register Setup Time 8 — ns
t
BTCRH BSCAN Test Capture Register Hold Time 10 — ns
t
BUTCO
BSCAN Test Update Register, Falling Edge of Clock
to Valid Output — 25 ns
t
BTUODIS
BSCAN Test Update Register, Falling Edge of Clock
to Valid Disable — 25 ns
t
BTUPOEN
BSCAN Test Update Register, Falling Edge of Clock
to Valid Enable — 25 ns3-29
DC and Switching Characteristics
Lattice Semiconductor LatticeSC Family Data Sheet
Switching Test Conditions
Figure 3-15 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-4.
Figure 3-15. Output Test Load, LVTTL and LVCMOS Standards
Table 3-4. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition CL
Timing Ref. VT
LVTTL and other LVCMOS settings (L -> H, H -> L) 30pF
LVCMOS 3.3 = 1.5V —
LVCMOS 2.5 = VCCIO/2 —
LVCMOS 1.8 = VCCIO/2 —
LVCMOS 1.5 = VCCIO/2 —
LVCMOS 1.2 = VCCIO/2 —
LVCMOS 2.5 I/O (Z -> H)
30pF
V
CCIO/2 VOL
LVCMOS 2.5 I/O (Z -> L) VCCIO/2 VOH
LVCMOS 2.5 I/O (H -> Z) VOH - 0.15 VOL
LVCMOS 2.5 I/O (L -> Z) VOL + 0.15 VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
DUT
CL
Test PointFebruary 2006 Preliminary Data Sheet
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 4-1 Pinouts_01.0
Signal Descriptions
Signal Name I/O Description
General Purpose
P[Edge] [Row/Column Number*]_[A/B/C/D] I/O
[Edge] indicates the edge of the device on which the pad is located.
Valid edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PIC row or the column of the
device on which the PIC exists. When Edge is T (Top) or (Bottom),
only need to specify Row Number. When Edge is L (Left) or R (Right),
only need to specify Column Number.
[A/B/C/D] indicates the PIO within the PIC to which the pad is connected.
Some of these user programmable pins are shared with special function pins. These pin when not used as special purpose pins can be
programmed as I/Os for user logic.
During configuration the user-programmable I/Os are tri-stated with an
internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor
enabled after configuration.
VREF1_x, VREF2_x —
The reference supply pins for I/O bank x. Any I/O pin in a bank can be
assigned as a reference supply pin, but software defaults use designated pin.
NC — No connect.
Non-SERDES Power Supplies
VCCIOx — VCCIO - The power supply pins for I/O bank x. Dedicated pins.
VCC12 — 1.2V supply for configuration logic and PLLs.
VTT_x — Termination voltage for bank x.
GND — GND - Ground. Dedicated pins.
VCC — VCC - The power supply pins for core logic. Dedicated pins (1.2V/
1.0V).
VCCAUX — VCCAUX - Auxiliary power supply pin - powers all differential and
referenced input buffers. Dedicated pins (2.5V).
VCCJ — VCCJ - The power supply pin for JTAG Test Access Port.
PROBE_VCC — VCC signal - Used for feedback to control the power converter.
PROBE_GND — GND signal - Used for feedback to control the power converter.
PLL and Clock Functions (Used as user-programmable I/O pins when not in use for PLL, DLL or clock pins.)
[LOC]_PLL[T, C]_FB_[A/B] I
PLL feedback input. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the PLL is located in: ULC (upper
left), URC (upper right), LLC (lower left) and LRC (lower right). [T, C]
indicates whether input is true or complement. [A, B] indicates PLL reference within the corner.
[LOC]_DLL[T, C]_FB_[C, D, E, F] I
DLL feedback input. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the DLL is located in: ULC (upper
left), URC (upper right), LLC (lower left) and LRC (lower right). [T/C]
indicates whether input is true or complement. [C, D, E, F] indicates
DLL reference within a corner. Note: E and F are only available on the
lower corners.
LatticeSC Family Data Sheet
Pinout Information4-2
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
[LOC]_PLL[T, C]_IN[A/B] I
PLL reference clock input. Pull-ups are enabled on input pins during
configuration. [LOC] indicates the corner the PLL is located in: ULC
(upper left), URC (upper right), LLC (lower left) and LRC (lower right).
[T, C] indicates whether input is true or complement.[A, B] indicates
PLL reference within the corner.
[LOC]_DLL[T, C]_IN[C, D, E, F]
DLL reference clock inputs. Pull-ups are enabled on input pins during
configuration. [LOC] indicates the corner the DLL is located in: ULC
(upper left), URC (upper right), LLC (lower left) and LRC (lower right).
[T/C] indicates whether input is true or complement. [C, D, E, F] indicates DLL reference within a corner. Note: E and F are only available
on the lower corners.
PCLKxy_z
General clock inputs. x indicates whether T (true) or C (complement).
y indicates the I/O bank the clock is associated with. z indicates the
clock number within a bank.
Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.)
TMS I Test Mode Select input, used to control the 1149.1 state machine.
TCK I Test Clock input pin, used to clock the 1149.1 state machine.
TDI I
Test Data in pin, used to load data into device using 1149.1 state
machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration
port is selected it is locked. Another configuration port cannot be
selected until the power-up sequence).
TDO/RDDATA O
Output pin -Test Data out pin used to shift data out of device using
1149.1.
If used for serial read-back, RDDATA provides serial configuration data
out which is clocked out using CCLK.
Configuration Pads (Dedicated pins. Used during sysCONFIG.)
M[3:0] I Mode pins used to specify configuration modes values latched on rising edge of INITN.
INITN I/O Open Drain pin - Indicates the FPGA is ready to be configured. During
configuration, a pull-up is enabled.
PROGRAMN I Initiates configuration sequence when asserted low. This pin always
has an active pull-up.
DONE I/O Open Drain pin - Indicates that the configuration sequence is complete, and the startup sequence is in progress.
CCLK I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
RESETN
Reset. (Also sent to general routing). During configuration it resets the
configuration state machine. After configuration this pin can perform
the global set/reset (GSR) functions or can be used as a general input
pin.
CFGIRQN O
MPI Interrupt request active low signal is controlled by system bus
interrupt controller and may be sourced from any bus error or MPI con-
figuration error. It can be connected to one of MPC860 IRQ pins.
RDCFGN I Enables readback.
Configuration Pads (User I/O if not used. Used during sysCONFIG.)
HDC O
High During Configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not
complete.
LDCN O
Low During Configuration is output low until configuration is complete.
It is used as a control output, indicating that configuration is not complete.
Signal Descriptions (Continued)
Signal Name I/O Description4-3
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
DOUT O
Serial data output that can drive the D0/DIN of daisy-chained slave
devices. The data-stream from this output will propagate preamble bits
of the bitstream to daisy-chained devices. Data out on DOUT changes
on the rising edge of CCLK.
QOUT/CEON O
During daisy-chaining configuration, QOUT is the serial data output
that can drive the D0/DIN of daisy-chained slave devices that do not
propagate preamble bits. Data out on QOUT changes on the rising
edge of CCLK.
During parallel-chaining configuration, active low CEON enables the
cascaded slave device to receive bitstream data.
RDN I
Used in the asynchronous peripheral configuration mode. A low on
RDN changes D[7:3] into status outputs. WRN and RDN should not be
used simultaneously. If they are, the write strobe overrides.
WRN I When the FPGA is selected, a low on the write strobe, WRN, loads the
data on D[7:0] inputs into an internal data buffer.
CS0N CS1 I
Used in the asynchronous peripheral, slave parallel and MPI modes.
The FPGA is selected when CS0N is low and CS1 is high. During con-
figuration, a pull-up is enabled on both except with MPI DMA access
control.
A[21:0] I/O
In master parallel mode, A[21:0] is an output and will address the con-
figuration EPROMs up to 4 MB space. For MPI configuration mode,
A[17:0] will be the MPI address MPI_ADDR[31:14], A[19:18] will be
the transfer size and A[21:20] will be the burst mode and burst in process.
D[n:0] I/O
In parallel configuration modes, D[7:0] receives configuration data,
and each pin is pull-up enabled. For slave serial mode, D0 is the data
input.
D[7:3] is the output internal status for peripheral mode when RDN is
low.
D[7:0] is also the first byte of MPI data pins.
In MPI configuration mode, MPI selectable data bus width from 8 and
16-bit. Driven by a bus master in a write transaction. Driven by MPI in
a read transaction.
DP[m:0] I/O MPI selectable parity data bus width from 1, 2, and 3-bit DP[0] for
D[7:0], DP[1] for D[15:8], and DP[2] for D[23:16].
BUSYN/RCLK O
During configuration in peripheral mode, high on BUSYN/RCLK indicates another byte can be written to the FPGA. If a read operation is
done when the device is selected, the same status is also available on
D[7] in asynchronous peripheral mode.
During configuration in slave parallel mode, low on BUSYN/RCLK
inhibits the external host from sending new data.
During configuration in master parallel and master byte modes,
BUSYN/RCLK is a read clock output signal to an external memory.
The BUSYN/RCLK frequency is the same as CCLK when used with
uncompressed bitstreams. BUSYN/RCLK will be 1/8 the frequency of
CCLK when the bitstream is compressed.
During configuration in SPI mode, BUSYN/RCLK is generated by the
device and connected to the CLK input of the FLASH memory.
MPI Interface (Dedicated pin)
Signal Descriptions (Continued)
Signal Name I/O Description4-4
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
MPI_IRQ_N O
MPI Interrupt request active low signal is controlled by system bus
interrupt controller and may be sourced from any bus error or MPI con-
figuration error. It can be connected to one of MPC860 IRQ pins.
MPI Interface (User I/O if MPI is not used.)
MPI_CS0N MPI_CS1 I
MPI chip select pins, active low on MPI_CS0N while active high on
MPI_CS1. Both have to be active during the whole transfer data
phase. During transfer address phase, both can be inactive so that the
decoding for them from address can be slow. If they are active during
address phase, one cycle can be saved for sync read.
MPI_CLK I
This is the PowerPC bus clock. It can be a source of the clock for
embedded system bus. If MPI_CLK is used as system bus clock, MPI
will be set into sync mode by default. All of the operation on PowerPC
side of MPI are synchronized to the rising edge of this clock.
MPI_TSIZ[1:0] I Driven by a bus master to indicate the data transfer size for the transaction. 01 for byte, 10 for half-word, and 00 for word.
MPI_WR_N I Driven high indicates that a read access is in progress. Driven low
indicates that a write access is in process.
MPI_BURST I Driven active low indicates that a burst transfer is in progress. Driven
high indicates that the current transfer is not a burst.
MPI_BDIP I
Active low “Burst Data in Process” is driven by a PowerPC processor.
Asserted indicates that the second beat in front of the current one is
requested by the master. Negated before the burst transfer ends to
abort the burst data phase.
MPI_STRBN I Driven active low indicates the start of a transaction on the PowerPC
bus. MPI will strobe the address bus at next rising edge of clock.
MPI_ADDR[31:14] I
Address bus driven by a PowerPC bus master. Only 18-bit width is
needed. It has to be the least significant bit of the PowerPC 32-bit
address A[31:14].
MPI_DAT[n:0] I/O Selectable data bus width from 8, and 16-bit. Driven by a bus master
in a write transaction. Driven by MPI in a read transaction.
MPI_PAR[m:0] I/O
Selectable parity bus width from 1, 2, and 3-bit. MPI_DP[0] for
MPI_D[7:0], MPI_DP[1] for MPI_D[15:8] and MPI_DP[2] for
MPI_D[23:16].
MPI_TA O Transfer acknowledge. Driven active low indicates that MPI received
the data on the write cycle or returned data on the read cycle.
MPI_TEA O Transfer Error Acknowledge. Driven active low indicates that MPI
detects a bus error on the internal system bus for current transaction.
MPI_RETRY O Active low MPI Retry requests the MPC860 to relinquish the bus and
retry the cycle.
Multi-chip Alignment (User I/O if not used.)
MCA_DONE_OUT O Multi-chip alignment done output (to second MCA chip)
MCA_DONE_IN I Multi-chip alignment done input (from second MCA chip)
MCA_CLK_P[1:2]_OUT O Multi-chip alignment clock [1:2] output (sourced by MCA master chip)
MCA_CLK_P[1:2]_IN I Multi-chip alignment clock [1:2] input (from MCA master chip
TEMP — Temperature sensing diode pin. Dedicated pin.
Miscellaneous Dedicated Pins
XRES —
External reference resistor between this pin and ground. The reference resistor is used to calibrate the programmable terminating resistors used in the I/Os. Dedicated pin. Value: 1K ± 1% ohm.
DIFFRx —
Only used if a differential driver is used in a bank. This DIFFRx must
be connected to ground via an external 1K ±1% ohm resistor for all
banks that have a differential driver.
Signal Descriptions (Continued)
Signal Name I/O Description4-5
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
SERDES Block (Dedicated Pins)
A_HDINPx_[L/R] I
High-speed input (positive) channel x on left [L] or right [R] side of
device. PCS quad is defined in the dual function name column of the
Logic Signal Connection table.
A_HDINNx_[L/R] I
High-speed input (negative) channel x on left [L] or right [R] side of
device. PCS quad is defined in the dual function name column of the
Logic Signal Connection table.
A_HDOUTPx_[L/R] O
High-speed output (positive) channel x on left [L] or right [R] side of
device. PCS quad is defined in the dual function name column of the
Logic Signal Connection table.
A_HDOUTNx_[L/R] O
High-speed output (negative) channel x on left [L] or right [R] side of
device. PCS quad is defined in the dual function name column of the
Logic Signal Connection table.
A_REFCLKP_[L/R] I Ref clock input (positive), aux channel on left [L] or right [R] side of
device.
A_REFCLKN_[L/R] I Ref clock input (negative), aux channel on left [L] or right [R] side of
device.
A_RXREFCLKP_[L/R] I Ref clock input (positive), RX only on left [L] or right [R] side of device.
A_RXREFCLKN_[L/R] I Ref clock input (negative), RX only on left [L] or right [R] side of device.
A_VDDIBx_[L/R] — Input buffer power supply for channel x (1.2V/1.5V) on left [L] or right
[R] side of device.
A_VDDOBx_[L/R] — Output buffer power supply for channel x (1.2V/1.5V) on left [L] or right
[R] side of device.
A_VDDAX25_[L/R] — Auxiliary power for input and output termination (2.5V) on left [L] or
right [R] side of device.
A_VDDRXx_[L/R] — Receiver power supply for channel x (1.2V) on left [L] or right [R] side
of device.
A_VDDTXx_[L/R] — Transmitter power supply for channel x (1.2V) on left [L] or right [R]
side of device.
A_VDDP_[L/R] — Power supply for SERDES PLL (1.2V) on left [L] or right [R] side of
device.
Signal Descriptions (Continued)
Signal Name I/O Description4-6
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
Pin Information Summary
Pin Type 900 ffBGA
Single Ended User I/O 378
Differential Pair User I/O 182
LVDS Output Pairs 60
Configuration
Dedicated 11
User I/O / MPI sysBUS 55
JTAG (excluding VCCJ) 4
Dedicated pins 4
V
CC 46
V
CC12 17
V
CCAUX 36
V
CCIO
Bank1 18
Bank2 14
Bank3 15
Bank4 15
Bank5 15
Bank6 15
Bank7 16
VTT
Bank2 2
Bank3 3
Bank4 3
Bank5 3
Bank6 3
Bank7 2
GND 177
NC 26
Single Ended User/Differential
I/O per Bank
Bank1 63/30
Bank2 30/15
Bank3 62/29
Bank4 66/32
Bank5 65/32
Bank6 62/29
Bank7 30/15
LVDS Output Pairs per Bank
Bank2 9
Bank3 21
Bank6 21
Bank7 9
V
CCJ 1
SERDES (signal + power supply) 76
Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an
internal pull-up resistor enabled after configuration.4-7
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
Power Supply and NC Connections1, 3
Ball Function 900 ffBGA Ball Numbers
VCC
AA10, AA11, AA12, AA13, AA14, AA17, AA18,AA19, AA20, AA21, AA22,
AA9, AB10, AB21, J10, J21, J22, J9, K10, K11, K12, K13, K14, K17, K18,
K19, K20, K21, K22, K9, L10, L21, M10, M21, N10, N21, P10, P21, U10,
U21, V10, V21, W10, W21, Y10, Y21
VCC12 AB9, AB22, AC8, AC23, H8, H23, H15, R23, T8, E5, D4, AG4, AF5, AF26,
AG27, D27, E26
VCCIO1 H10, H21, H22, H9, J11, J12, J13, J14, J15, J16, J17, J18, J19, J20, F20,
C19, C12, F11
VCCIO2 J23, J24, K23, K24, L22, L23, M22, N22, P22, R22, G30, J29, K27, N25
VCCIO3 AA23, AA24, AB23, AB24, T22, U22, V22, W22, Y22, Y23, Y24, AC29, AA26,
Y28, AA29
VCCIO4 AB16, AB17, AB18, AB19, AB20, AC20, AC21, AC22, AD20, AD21, AD22,
AJ23, AG20, AJ26, AG23
VCCIO5 AB11, AB12, AB13, AB14, AB15, AC10, AC11, AC9, AD10, AD11, AD9,
AE7, AH6, AG11, AJ9
VCCIO6 AA7, AA8, AB7, AB8, T9, U9, V9, W9, Y7, Y8, Y9, AB2, AD1, W4, AA4
VCCIO7 J7, J8, K7, K8, L8, L9, M9, N9, P9, R9, H2, N4, N6, J2, L2, H4
VCCJ J25
VCCAUX
H11, H12, H19, H20, M23, M24, N23, N24, U23, U24, V23, V24, W23, W24,
AC17, AC18, AC19, AD17, AD18, AD19, AC12, AC13, AC14, AD12, AD13,
AD14, U7, U8, V7, V8, W7, W8, M7, M8, N7, N8
GND
A1, A30, AA15, AA16, AK1, AK30, K15, K16, L11, L12, L13, L14, L15, L16,
L17, L18, L19, L20, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20,
N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, P11, P12, P13, P14,
P15, P16, P17, P18, P19, P20, R10, R11, R12, R13, R14, R15, R16, R17,
R18, R19, R20, R21, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20,
T21, U11, U12, U13, U14, U15, U16, U17, U18, U19, U20, V11, V12, V13,
V14, V15, V16, V17, V18, V19, V20, W11, W12, W13, W14, W15, W16, W17,
W18, W19, W20, Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y19, Y20, H1, L4,
M3, N5, K2, M2, P6, G4, H3, AC2, AA3, AE1, Y4, AB4, AA5, AE6, AE8, AH5,
AG9, AG6, AF11, AG12, AJ10, AK26, AJ22, AF20, AJ25, AJ27, AF23, AF22,
AE27, AA27, AB29, Y26, AC30, Y29, F30, E27, F27, P25, H29, K29, R24,
M28, J27, N26, E20, E21, F21, F23, G23, D21, D20, E18, C20, C11, A12,
E11, F8, G8, D11, D10, H7, F10, E10
NC2
M4, P5, J3, AB3, AH9, AG10, AF12, AG7, AK27, AJ24, AB30, AA28, P24,
K28, P23, L28, E19, G21, G20, G19, F9, A11, G7, AC16, A2, A29
1. All grounds must be electrically connected at the board level.
2. NC pins should not be connected to any active signals, VCC or GND.
3. SERDES power supply pins not shown, see Logic Signal Connections table for details.4-8
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
VTT
Ball Function VCCIO Bank 900 ffBGA Ball Numbers
VTT_2 2 L24, T23
VTT_3 3 AC24, T25, W25
VTT_4 4 AD24, AE17, AE18
VTT_5 5 AC15, AD16, AE9
VTT_6 6 AA6, T7, W6
VTT_7 7 L7, P74-9
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA
A_VDDAX25_L I - - F7
A_REFCLKP_L I - - B1
A_REFCLKN_L I - - C1
A_VDDP_L I - - D5
A_RXREFCLKP_L I - - B2
A_RXREFCLKN_L I - - C2
NC - - - A2
VCC12 VCC12 - - E5
VCC12 VCC12 - - D4
RESETN I 1 0 H5
RDCFGN I 1 0 H6
DONE IO 1 0 G6
INITN IO 1 0 G5
M0 I 1 0 F5
M1 I 1 0 F6
M2 I 1 0 F4
M3 I 1 0 E4
PL16A IO 7 2 ULC_PLLT_IN_A/ULC_PLLT_FB_B D3
PL16B IO 7 2 ULC_PLLC_IN_A/ULC_PLLC_FB_B D2
PL16C IO 7 2 J6
PL16D IO 7 2 J5
PL17A IO 7 2 ULC_DLLT_IN_C/ULC_DLLT_FB_D E3
PL17B IO 7 2 ULC_DLLC_IN_C/ULC_DLLC_FB_D E2
PL17C IO 7 2 ULC_PLLT_IN_B/ULC_PLLT_FB_A K4
PL17D IO 7 2 ULC_PLLC_IN_B/ULC_PLLC_FB_A J4
PL18A IO 7 2 ULC_DLLT_IN_D/ULC_DLLT_FB_C F3
PL18B IO 7 2 ULC_DLLC_IN_D/ULC_DLLC_FB_C G3
PL18C IO 7 2 K5
PL18D IO 7 2 VREF2_7 K6
PL20A IO 7 2 G2
PL20B IO 7 2 G1
PL21A IO 7 2 L5
PL21B IO 7 2 M5
PL22A IO 7 2 F2
PL22B IO 7 2 F1
PL22C IO 7 2 E1
PL22D IO 7 2 D1
PL25A IO 7 2 _ K3
PL25B IO 7 2 L3
PL25C IO 7 2 VREF1_7 L6
PL25D IO 7 2 DIFFR_7 M6
PL26A IO 7 2 PCLKT7_1 J1
PL26B IO 7 2 PCLKC7_1 K14-10
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PL27A IO 7 2 PCLKT7_0 L1
PL27B IO 7 2 PCLKC7_0 M1
PL27C IO 7 2 PCLKT7_2 P8
PL27D IO 7 2 PCLKC7_2 R8
PL29A IO 6 2 PCLKT6_0 N2
PL29B IO 6 2 PCLKC6_0 N1
PL29C IO 6 2 PCLKT6_1 R7
PL29D IO 6 2 PCLKC6_1 R6
PL30A IO 6 2 N3
PL30B IO 6 2 P3
PL30C IO 6 2 PCLKT6_3 P4
PL31A IO 6 2 P2
PL31B IO 6 2 R2
PL31C IO 6 2 PCLKT6_2 T3
PL31D IO 6 2 PCLKC6_2 R3
PL34A IO 6 2 P1
PL34B IO 6 2 R1
PL34C IO 6 2 VREF1_6 R5
PL34D IO 6 2 R4
PL35A IO 6 2 T2
PL35B IO 6 2 U2
PL35C IO 6 2 T6
PL36A IO 6 2 U3
PL36B IO 6 2 V3
PL38A IO 6 2 T1
PL38B IO 6 2 U1
PL39A IO 6 2 T5
PL39B IO 6 2 T4
PL40A IO 6 2 U4
PL40B IO 6 2 U5
PL42A IO 6 2 V1
PL42B IO 6 2 W1
PL42C IO 6 2 U6
PL42D IO 6 2 DIFFR_6 V6
PL43A IO 6 2 V2
PL43B IO 6 2 W2
PL43C IO 6 2 V5
PL43D IO 6 2 V4
PL44A IO 6 2 Y1
PL44B IO 6 2 AA1
PL47A IO 6 2 Y2
PL47B IO 6 2 AA2
PL47C IO 6 2 Y3
PL47D IO 6 2 W3
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-11
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PL48A IO 6 2 AB1
PL48B IO 6 2 AC1
PL48C IO 6 2 W5
PL49A IO 6 2 Y5
PL49B IO 6 2 Y6
PL51A IO 6 2 AD2
PL51B IO 6 2 AE2
PL51D IO 6 2 VREF2_6 AB5
PL52A IO 6 2 AC3
PL52B IO 6 2 AD3
PL53A IO 6 2 AC4
PL53B IO 6 2 AD4
PL55A IO 6 2 AF1
PL55B IO 6 2 AG1
PL55C IO 6 2 LLC_DLLT_IN_E/LLC_DLLT_FB_F AB6
PL55D IO 6 2 LLC_DLLC_IN_E/LLC_DLLC_FB_F AC5
PL56A IO 6 2 AE3
PL56B IO 6 2 AF3
PL57A IO 6 2 LLC_DLLT_IN_F/LLC_DLLT_FB_E AF2
PL57B IO 6 2 LLC_DLLC_IN_F/LLC_DLLC_FB_E AG2
PL57C IO 6 2 LLC_PLLT_IN_B/LLC_PLLT_FB_A AC6
PL57D IO 6 2 LLC_PLLC_IN_B/LLC_PLLC_FB_A AC7
XRES IO - - AE4
VCC12 VCC12 - - AG4
TEMP I 6 0 AD5
VCC12 VCC12 - - AF5
PB3A IO 5 4 LLC_PLLT_IN_A/LLC_PLLT_FB_B AH1
PB3B IO 5 4 LLC_PLLC_IN_A/LLC_PLLC_FB_B AJ1
PB3C IO 5 4 LLC_DLLT_IN_C/LLC_DLLT_FB_D AF4
PB3D IO 5 4 LLC_DLLC_IN_C/LLC_DLLC_FB_D AE5
PB4A IO 5 4 LLC_DLLT_IN_D/LLC_DLLT_FB_C AG3
PB4B IO 5 4 LLC_DLLC_IN_D/LLC_DLLC_FB_C AH2
PB4C IO 5 4 AD6
PB5A IO 5 4 AJ2
PB5B IO 5 4 AK2
PB5C IO 5 4 AD7
PB5D IO 5 4 VREF1_5 AD8
PB7A IO 5 4 AF7
PB7B IO 5 4 AF6
PB8A IO 5 4 AH4
PB8B IO 5 4 AG5
PB9A IO 5 4 AF8
PB9B IO 5 4 AG8
PB11A IO 5 4 AH3
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-12
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PB11B IO 5 4 AJ3
PB11C IO 5 4 AF9
PB11D IO 5 4 AE10
PB12A IO 5 4 AK3
PB12B IO 5 4 AJ4
PB13A IO 5 4 AE11
PB13B IO 5 4 AF10
PB15A IO 5 4 AH7
PB15B IO 5 4 AH8
PB15C IO 5 4 AE12
PB15D IO 5 4 AE13
PB16A IO 5 4 AK4
PB16B IO 5 4 AK5
PB17A IO 5 4 AJ5
PB17B IO 5 4 AJ6
PB19A IO 5 4 AJ7
PB19B IO 5 4 AJ8
PB20A IO 5 4 PCLKT5_3 AH10
PB20B IO 5 4 PCLKC5_3 AH11
PB20C IO 5 4 PCLKT5_4 AF13
PB20D IO 5 4 PCLKC5_4 AE14
PB21A IO 5 4 PCLKT5_5 AK6
PB21B IO 5 4 PCLKC5_5 AK7
PB21C IO 5 4 AF14
PB21D IO 5 4 AF15
PB23A IO 5 4 PCLKT5_0 AJ11
PB23B IO 5 4 PCLKC5_0 AJ12
PB23C IO 5 4 AG13
PB23D IO 5 4 VREF2_5 AH13
PB24A IO 5 4 PCLKT5_1 AK8
PB24B IO 5 4 PCLKC5_1 AK9
PB25A IO 5 4 PCLKT5_2 AH14
PB25B IO 5 4 PCLKC5_2 AG14
PB28A IO 5 4 AK10
PB28B IO 5 4 AK11
PB29A IO 5 4 AH15
PB29B IO 5 4 AG15
PB31A IO 5 4 AH12
PB31B IO 5 4 AJ13
PB31C IO 5 4 AD15
PB31D IO 5 4 AE15
PB32A IO 5 4 AK12
PB32B IO 5 4 AK13
PB33A IO 5 4 AJ14
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-13
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PB33B IO 5 4 AJ15
PB35A IO 5 4 AK14
PB35B IO 5 4 AK15
PB37A IO 4 4 AK16
PB37B IO 4 4 AK17
PB38A IO 4 4 AJ16
PB38B IO 4 4 AJ17
PB38C IO 4 4 AE16
PB38D IO 4 4 AF16
PB39A IO 4 4 AH16
PB39B IO 4 4 AG16
PB41A IO 4 4 AK18
PB41B IO 4 4 AK19
PB42A IO 4 4 AH17
PB42B IO 4 4 AH18
PB42C IO 4 4 AF17
PB42D IO 4 4 AG17
PB43A IO 4 4 AJ18
PB43B IO 4 4 AJ19
PB46A IO 4 4 PCLKT4_2 AK20
PB46B IO 4 4 PCLKC4_2 AK21
PB47A IO 4 4 PCLKT4_1 AF18
PB47B IO 4 4 PCLKC4_1 AG18
PB49A IO 4 4 PCLKT4_0 AJ20
PB49B IO 4 4 PCLKC4_0 AJ21
PB49C IO 4 4 VREF2_4 AG19
PB49D IO 4 4 AF19
PB51A IO 4 4 PCLKT4_5 AK22
PB51B IO 4 4 PCLKC4_5 AK23
PB51C IO 4 4 AH19
PB51D IO 4 4 AH20
PB52A IO 4 4 PCLKT4_3 AK24
PB52B IO 4 4 PCLKC4_3 AK25
PB52C IO 4 4 PCLKT4_4 AE19
PB52D IO 4 4 PCLKC4_4 AE20
PB53A IO 4 4 AE21
PB53B IO 4 4 AF21
PB55A IO 4 4 AG21
PB55B IO 4 4 AG22
PB56A IO 4 4 AH22
PB56B IO 4 4 AH23
PB56C IO 4 4 AH21
PB57A IO 4 4 AD23
PB57B IO 4 4 AE23
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-14
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PB59A IO 4 4 AH24
PB59B IO 4 4 AH25
PB60A IO 4 4 AK28
PB60B IO 4 4 AK29
PB60C IO 4 4 AE22
PB61A IO 4 4 AH26
PB61B IO 4 4 AH27
PB63A IO 4 4 AF24
PB63B IO 4 4 AG24
PB64A IO 4 4 AG25
PB64B IO 4 4 AF25
PB65A IO 4 4 AG26
PB65B IO 4 4 AF27
PB67A IO 4 4 AJ28
PB67B IO 4 4 AH28
PB67C IO 4 4 VREF1_4 AE24
PB67D IO 4 4 AE25
PB68A IO 4 4 LRC_DLLT_IN_C/LRC_DLLT_FB_D AJ29
PB68B IO 4 4 LRC_DLLC_IN_C/LRC_DLLC_FB_D AH29
PB68C IO 4 4 AE26
PB68D IO 4 4 AD25
PB69A IO 4 4 LRC_PLLT_IN_A/LRC_PLLT_FB_B AJ30
PB69B IO 4 4 LRC_PLLC_IN_A/LRC_PLLC_FB_B AH30
PB69C IO 4 4 LRC_DLLT_IN_D/LRC_DLLT_FB_C AG28
PB69D IO 4 4 LRC_DLLC_IN_D/LRC_DLLC_FB_C AG29
VCC12 VCC12 - - AF26
PROBE_VCC O - - AD27
VCC12 VCC12 - - AG27
PROBE_GND O - - AE28
PR57D IO 3 2 LRC_PLLC_IN_B/LRC_PLLC_FB_A AC25
PR57C IO 3 2 LRC_PLLT_IN_B/LRC_PLLT_FB_A AD26
PR57B IO 3 2 LRC_DLLC_IN_F/LRC_DLLC_FB_E AF28
PR57A IO 3 2 LRC_DLLT_IN_F/LRC_DLLT_FB_E AF29
PR56B IO 3 2 AD28
PR56A IO 3 2 AC27
PR55D IO 3 2 LRC_DLLC_IN_E/LRC_DLLC_FB_F AC26
PR55C IO 3 2 LRC_DLLT_IN_E/LRC_DLLT_FB_F AB26
PR55B IO 3 2 AG30
PR55A IO 3 2 AF30
PR53B IO 3 2 AE29
PR53A IO 3 2 AD29
PR52B IO 3 2 AC28
PR52A IO 3 2 AB28
PR51D IO 3 2 VREF2_3 AB27
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-15
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PR51B IO 3 2 AE30
PR51A IO 3 2 AD30
PR49B IO 3 2 AB25
PR49A IO 3 2 AA25
PR48C IO 3 2 Y25
PR48B IO 3 2 AA30
PR48A IO 3 2 Y30
PR47D IO 3 2 W27
PR47C IO 3 2 Y27
PR47B IO 3 2 W30
PR47A IO 3 2 V30
PR44B IO 3 2 W29
PR44A IO 3 2 V29
PR43D IO 3 2 W26
PR43C IO 3 2 V26
PR43B IO 3 2 U30
PR43A IO 3 2 T30
PR42D IO 3 2 DIFFR_3 V25
PR42C IO 3 2 U25
PR42B IO 3 2 W28
PR42A IO 3 2 V28
PR40B IO 3 2 T27
PR40A IO 3 2 R27
PR39B IO 3 2 V27
PR39A IO 3 2 U27
PR38B IO 3 2 R30
PR38A IO 3 2 P30
PR36B IO 3 2 U29
PR36A IO 3 2 T29
PR35C IO 3 2 T24
PR35B IO 3 2 N30
PR35A IO 3 2 M29
PR34D IO 3 2 U26
PR34C IO 3 2 VREF1_3 T26
PR34B IO 3 2 U28
PR34A IO 3 2 T28
PR31D IO 3 2 PCLKC3_2 M30
PR31C IO 3 2 PCLKT3_2 L29
PR31B IO 3 2 R29
PR31A IO 3 2 P29
PR30C IO 3 2 PCLKT3_3 P27
PR30B IO 3 2 N29
PR30A IO 3 2 N28
PR29D IO 3 2 PCLKC3_1 R25
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-16
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PR29C IO 3 2 PCLKT3_1 R26
PR29B IO 3 2 PCLKC3_0 R28
PR29A IO 3 2 PCLKT3_0 P28
PR27D IO 2 2 PCLKC2_2 N27
PR27C IO 2 2 PCLKT2_2 P26
PR27B IO 2 2 PCLKC2_0 L30
PR27A IO 2 2 PCLKT2_0 K30
PR26B IO 2 2 PCLKC2_1 J30
PR26A IO 2 2 PCLKT2_1 H30
PR25D IO 2 2 DIFFR_2 M26
PR25C IO 2 2 VREF1_2 M25
PR25B IO 2 2 G29
PR25A IO 2 2 F29
PR22D IO 2 2 H28
PR22C IO 2 2 J28
PR22B IO 2 2 E30
PR22A IO 2 2 E29
PR21B IO 2 2 M27
PR21A IO 2 2 L27
PR20B IO 2 2 H27
PR20A IO 2 2 G27
PR18D IO 2 2 VREF2_2 L26
PR18C IO 2 2 L25
PR18B IO 2 2 URC_DLLC_IN_D/URC_DLLC_FB_C F28
PR18A IO 2 2 URC_DLLT_IN_D/URC_DLLT_FB_C G28
PR17D IO 2 2 URC_PLLC_IN_B/URC_PLLC_FB_A K26
PR17C IO 2 2 URC_PLLT_IN_B/URC_PLLT_FB_A K25
PR17B IO 2 2 URC_DLLC_IN_C/URC_DLLC_FB_D D30
PR17A IO 2 2 URC_DLLT_IN_C/URC_DLLT_FB_D D29
PR16D IO 2 2 G26
PR16C IO 2 2 H26
PR16B IO 2 2 URC_PLLC_IN_A/URC_PLLC_FB_B E28
PR16A IO 2 2 URC_PLLT_IN_A/URC_PLLT_FB_B D28
VCCJ I - - J25
TDO O - - TDO/RDDATA H25
TMS I - - J26
TCK I - - G25
TDI I - - G24
PROGRAMN I 1 0 F26
MPIIRQN O 1 0 CFGIRQN/MPI_IRQ_N H24
CCLK IO 1 0 F25
VCC12 VCC12 - - D27
VCC12 VCC12 - - E26
NC - - - A29
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-17
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
A_RXREFCLKN_R I - - C29
A_RXREFCLKP_R I - - B29
A_VDDP_R I - - D26
A_REFCLKN_R I - - C30
A_REFCLKP_R I - - B30
A_VDDAX25_R I - - F24
A_VDDRX0_R I - - D25
A_VDDIB0_R I - - C28
A_HDINP0_R I - - PCS 3E0 CH 0 IN P B28
A_HDINN0_R I - - PCS 3E0 CH 0 IN N B27
A_VDDTX0_R I - - E25
A_HDOUTP0_R O - - PCS 3E0 CH 0 OUT P A28
A_VDDOB0_R I - - C27
A_HDOUTN0_R O - - PCS 3E0 CH 0 OUT N A27
A_VDDOB1_R I - - C26
A_HDOUTN1_R O - - PCS 3E0 CH 1 OUT N A26
A_VDDTX1_R I - - D24
A_HDOUTP1_R O - - PCS 3E0 CH 1 OUT P A25
A_HDINN1_R I - - PCS 3E0 CH 1 IN N B26
A_HDINP1_R I - - PCS 3E0 CH 1 IN P B25
A_VDDRX1_R I - - E24
A_VDDIB1_R I - - C25
A_VDDRX2_R I - - D23
A_VDDIB2_R I - - C24
A_HDINP2_R I - - PCS 3E0 CH 2 IN P B24
A_HDINN2_R I - - PCS 3E0 CH 2 IN N B23
A_VDDTX2_R I - - E23
A_HDOUTP2_R O - - PCS 3E0 CH 2 OUT P A24
A_VDDOB2_R I - - C23
A_HDOUTN2_R O - - PCS 3E0 CH 2 OUT N A23
A_VDDOB3_R I - - C22
A_HDOUTN3_R O - - PCS 3E0 CH 3 OUT N A22
A_VDDTX3_R I - - D22
A_HDOUTP3_R O - - PCS 3E0 CH 3 OUT P A21
A_HDINN3_R I - - PCS 3E0 CH 3 IN N B22
A_HDINP3_R I - - PCS 3E0 CH 3 IN P B21
A_VDDRX3_R I - - E22
A_VDDIB3_R I - - C21
PT49D IO 1 4 HDC G22
PT49C IO 1 4 LDCN F22
PT49B IO 1 4 D8/MPI_DATA8 B20
PT49A IO 1 4 CS1/MPI_CS1 B19
PT47D IO 1 4 D9/MPI_DATA9 A20
PT47C IO 1 4 D10/MPI_DATA10 A19
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-18
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PT47B IO 1 4 CS0N/MPI_CS0N D19
PT47A IO 1 4 RDN/MPI_STRB_N D18
PT46D IO 1 4 WRN/MPI_WR_N F19
PT46C IO 1 4 D7/MPI_DATA7 F18
PT46B IO 1 4 D6/MPI_DATA6 C18
PT46A IO 1 4 D5/MPI_DATA5 C17
PT45D IO 1 4 D4/MPI_DATA4 E17
PT45C IO 1 4 D3/MPI_DATA3 E16
PT45B IO 1 4 D2/MPI_DATA2 G18
PT45A IO 1 4 D1/MPI_DATA1 G17
PT43B IO 1 4 D0/MPI_DATA0 B18
PT43A IO 1 4 QOUT/CEON B17
PT42D IO 1 4 VREF2_1 G16
PT42B IO 1 4 DOUT A18
PT42A IO 1 4 MCA_DONE_IN A17
PT41B IO 1 4 MCA_CLK_P1_OUT H18
PT41A IO 1 4 MCA_CLK_P1_IN H17
PT39B IO 1 4 MCA_CLK_P2_OUT D17
PT39A IO 1 4 MCA_CLK_P2_IN D16
PT38D IO 1 4 MCA_DONE_OUT F17
PT38C IO 1 4 BUSYN/RCLK F16
PT38B IO 1 4 DP0/MPI_PAR0 C16
PT38A IO 1 4 MPI_TA C15
PT37B IO 1 4 PCLKC1_0 B16
PT37A IO 1 4 PCLKT1_0/MPI_CLK B15
PT35D IO 1 4 PCLKC1_4 H16
PT35B IO 1 4 MPI_RETRY A16
PT35A IO 1 4 A0/MPI_ADDR14 A15
PT33D IO 1 4 A1/MPI_ADDR15 G15
PT33C IO 1 4 A2/MPI_ADDR16 F15
PT33B IO 1 4 A3/MPI_ADDR17 E15
PT33A IO 1 4 A4/MPI_ADDR18 D15
PT32B IO 1 4 A5/MPI_ADDR19 C14
PT32A IO 1 4 A6/MPI_ADDR20 C13
PT31C IO 1 4 VREF1_1 H14
PT31B IO 1 4 A7/MPI_ADDR21 B14
PT31A IO 1 4 A8/MPI_ADDR22 B13
PT29B IO 1 4 A9/MPI_ADDR23 G14
PT29A IO 1 4 A10/MPI_ADDR24 F14
PT28B IO 1 4 A11/MPI_ADDR25 A14
PT28A IO 1 4 A12/MPI_ADDR26 A13
PT27D IO 1 4 D11/MPI_DATA11 G13
PT27C IO 1 4 D12/MPI_DATA12 H13
PT27B IO 1 4 A13/MPI_ADDR27 E14
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-19
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
PT27A IO 1 4 A14/MPI_ADDR28 E13
PT25D IO 1 4 A16/MPI_ADDR30 G12
PT25C IO 1 4 D13/MPI_DATA13 G11
PT25B IO 1 4 A15/MPI_ADDR29 D14
PT25A IO 1 4 A17/MPI_ADDR31 D13
PT24D IO 1 4 A19/MPI_TSIZ1 F12
PT24C IO 1 4 A20/MPI_BDIP F13
PT24B IO 1 4 A18/MPI_TSIZ0 B12
PT24A IO 1 4 MPI_TEA B11
PT23D IO 1 4 D14/MPI_DATA14 E12
PT23C IO 1 4 DP1/MPI_PAR1 D12
PT23B IO 1 4 A21/MPI_BURST G10
PT23A IO 1 4 D15/MPI_DATA15 G9
A_VDDIB3_L I - - C10
A_VDDRX3_L I - - E9
A_HDINP3_L I - - PCS 360 CH 3 IN P B10
A_HDINN3_L I - - PCS 360 CH 3 IN N B9
A_HDOUTP3_L O - - PCS 360 CH 3 OUT P A10
A_VDDTX3_L I - - D9
A_HDOUTN3_L O - - PCS 360 CH 3 OUT N A9
A_VDDOB3_L I - - C9
A_HDOUTN2_L O - - PCS 360 CH 2 OUT N A8
A_VDDOB2_L I - - C8
A_HDOUTP2_L O - - PCS 360 CH 2 OUT P A7
A_VDDTX2_L I - - E8
A_HDINN2_L I - - PCS 360 CH 2 IN N B8
A_HDINP2_L I - - PCS 360 CH 2 IN P B7
A_VDDIB2_L I - - C7
A_VDDRX2_L I - - D8
A_VDDIB1_L I - - C6
A_VDDRX1_L I - - E7
A_HDINP1_L I - - PCS 360 CH 1 IN P B6
A_HDINN1_L I - - PCS 360 CH 1 IN N B5
A_HDOUTP1_L O - - PCS 360 CH 1 OUT P A6
A_VDDTX1_L I - - D7
A_HDOUTN1_L O - - PCS 360 CH 1 OUT N A5
A_VDDOB1_L I - - C5
A_HDOUTN0_L O - - PCS 360 CH 0 OUT N A4
A_VDDOB0_L I - - C4
A_HDOUTP0_L O - - PCS 360 CH 0 OUT P A3
A_VDDTX0_L I - - E6
A_HDINN0_L I - - PCS 360 CH 0 IN N B4
A_HDINP0_L I - - PCS 360 CH 0 IN P B3
A_VDDIB0_L I - - C3
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-20
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
A_VDDRX0_L I - - D6
NC - - - M4
NC - - - J3
NC - - - P5
NC - - - AB3
NC - - - AH9
NC - - - AG10
NC - - - AF12
NC - - - AG7
NC - - - AK27
NC - - - AJ24
NC - - - AB30
NC - - - AA28
NC - - - P24
NC - - - K28
NC - - - P23
NC - - - L28
NC - - - E19
NC - - - G21
NC - - - G20
NC - - - G19
NC - - - F9
NC - - - A11
NC - - - G7
VCC12 VCC12 - - H8
VCC12 VCC12 - - T8
VCC12 VCC12 - - AB9
VCC12 VCC12 - - AC8
VCC12 VCC12 - - AB22
VCC12 VCC12 - - AC23
VCC12 VCC12 - - R23
VCC12 VCC12 - - H23
VCC12 VCC12 - - H15
VTT_2 VTT_2 - - L24
VTT_2 VTT_2 - - T23
VTT_3 VTT_3 - - AC24
VTT_3 VTT_3 - - T25
VTT_3 VTT_3 - - W25
VTT_4 VTT_4 - - AD24
VTT_4 VTT_4 - - AE17
VTT_4 VTT_4 - - AE18
VTT_5 VTT_5 - - AC15
VTT_5 VTT_5 - - AD16
VTT_5 VTT_5 - - AE9
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-21
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
VTT_6 VTT_6 - - AA6
VTT_6 VTT_6 - - T7
VTT_6 VTT_6 - - W6
VTT_7 VTT_7 - - L7
VTT_7 VTT_7 - - P7
VCC VCC - - AA10
VCC VCC - - AA11
VCC VCC - - AA12
VCC VCC - - AA13
VCC VCC - - AA14
VCC VCC - - AA17
VCC VCC - - AA18
VCC VCC - - AA19
VCC VCC - - AA20
VCC VCC - - AA21
VCC VCC - - AA22
VCC VCC - - AA9
VCC VCC - - AB10
VCC VCC - - AB21
VCC VCC - - J10
VCC VCC - - J21
VCC VCC - - K10
VCC VCC - - K11
VCC VCC - - K12
VCC VCC - - K13
VCC VCC - - K14
VCC VCC - - K17
VCC VCC - - K18
VCC VCC - - K19
VCC VCC - - K20
VCC VCC - - K21
VCC VCC - - K22
VCC VCC - - K9
VCC VCC - - L10
VCC VCC - - L21
VCC VCC - - M10
VCC VCC - - M21
VCC VCC - - N10
VCC VCC - - N21
VCC VCC - - P10
VCC VCC - - P21
VCC VCC - - U10
VCC VCC - - U21
VCC VCC - - V10
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-22
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
VCC VCC - - V21
VCC VCC - - W10
VCC VCC - - W21
VCC VCC - - Y10
VCC VCC - - Y21
VCCAUX VCCAUX - - H11
VCCAUX VCCAUX - - H12
VCCAUX VCCAUX - - H19
VCCAUX VCCAUX - - H20
VCCAUX VCCAUX - - M23
VCCAUX VCCAUX - - M24
VCCAUX VCCAUX - - N23
VCCAUX VCCAUX - - N24
VCCAUX VCCAUX - - U23
VCCAUX VCCAUX - - U24
VCCAUX VCCAUX - - V23
VCCAUX VCCAUX - - V24
VCCAUX VCCAUX - - W23
VCCAUX VCCAUX - - W24
VCCAUX VCCAUX - - AC17
VCCAUX VCCAUX - - AC18
VCCAUX VCCAUX - - AC19
VCCAUX VCCAUX - - AD17
VCCAUX VCCAUX - - AD18
VCCAUX VCCAUX - - AD19
VCCAUX VCCAUX - - AC12
VCCAUX VCCAUX - - AC13
VCCAUX VCCAUX - - AC14
VCCAUX VCCAUX - - AD12
VCCAUX VCCAUX - - AD13
VCCAUX VCCAUX - - AD14
VCCAUX VCCAUX - - U7
VCCAUX VCCAUX - - U8
VCCAUX VCCAUX - - V7
VCCAUX VCCAUX - - V8
VCCAUX VCCAUX - - W7
VCCAUX VCCAUX - - W8
VCCAUX VCCAUX - - M7
VCCAUX VCCAUX - - M8
VCCAUX VCCAUX - - N7
VCCAUX VCCAUX - - N8
VCCIO1 VCCIO1 - - H10
VCCIO1 VCCIO1 - - H21
VCCIO1 VCCIO1 - - H22
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-23
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
VCCIO1 VCCIO1 - - H9
VCCIO1 VCCIO1 - - J11
VCCIO1 VCCIO1 - - J12
VCCIO1 VCCIO1 - - J13
VCCIO1 VCCIO1 - - J14
VCCIO1 VCCIO1 - - J15
VCCIO1 VCCIO1 - - J16
VCCIO1 VCCIO1 - - J17
VCCIO1 VCCIO1 - - J18
VCCIO1 VCCIO1 - - J19
VCCIO1 VCCIO1 - - J20
VCCIO2 VCCIO2 - - J23
VCCIO2 VCCIO2 - - J24
VCCIO2 VCCIO2 - - K23
VCCIO2 VCCIO2 - - K24
VCCIO2 VCCIO2 - - L22
VCCIO2 VCCIO2 - - L23
VCCIO2 VCCIO2 - - M22
VCCIO2 VCCIO2 - - N22
VCCIO2 VCCIO2 - - P22
VCCIO2 VCCIO2 - - R22
VCCIO3 VCCIO3 - - AA23
VCCIO3 VCCIO3 - - AA24
VCCIO3 VCCIO3 - - AB23
VCCIO3 VCCIO3 - - AB24
VCCIO3 VCCIO3 - - T22
VCCIO3 VCCIO3 - - U22
VCCIO3 VCCIO3 - - V22
VCCIO3 VCCIO3 - - W22
VCCIO3 VCCIO3 - - Y22
VCCIO3 VCCIO3 - - Y23
VCCIO3 VCCIO3 - - Y24
VCCIO4 VCCIO4 - - AB16
VCCIO4 VCCIO4 - - AB17
VCCIO4 VCCIO4 - - AB18
VCCIO4 VCCIO4 - - AB19
VCCIO4 VCCIO4 - - AB20
VCCIO4 VCCIO4 - - AC20
VCCIO4 VCCIO4 - - AC21
VCCIO4 VCCIO4 - - AC22
VCCIO4 VCCIO4 - - AD20
VCCIO4 VCCIO4 - - AD21
VCCIO4 VCCIO4 - - AD22
VCCIO5 VCCIO5 - - AB11
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-24
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
VCCIO5 VCCIO5 - - AB12
VCCIO5 VCCIO5 - - AB13
VCCIO5 VCCIO5 - - AB14
VCCIO5 VCCIO5 - - AB15
VCCIO5 VCCIO5 - - AC10
VCCIO5 VCCIO5 - - AC11
VCCIO5 VCCIO5 - - AC9
VCCIO5 VCCIO5 - - AD10
VCCIO5 VCCIO5 - - AD11
VCCIO5 VCCIO5 - - AD9
VCCIO6 VCCIO6 - - AA7
VCCIO6 VCCIO6 - - AA8
VCCIO6 VCCIO6 - - AB7
VCCIO6 VCCIO6 - - AB8
VCCIO6 VCCIO6 - - T9
VCCIO6 VCCIO6 - - U9
VCCIO6 VCCIO6 - - V9
VCCIO6 VCCIO6 - - W9
VCCIO6 VCCIO6 - - Y7
VCCIO6 VCCIO6 - - Y8
VCCIO6 VCCIO6 - - Y9
VCCIO7 VCCIO7 - - J7
VCCIO7 VCCIO7 - - J8
VCCIO7 VCCIO7 - - K7
VCCIO7 VCCIO7 - - K8
VCCIO7 VCCIO7 - - L8
VCCIO7 VCCIO7 - - L9
VCCIO7 VCCIO7 - - M9
VCCIO7 VCCIO7 - - N9
VCCIO7 VCCIO7 - - P9
VCCIO7 VCCIO7 - - R9
GND GND - - A1
GND GND - - A30
GND GND - - AA15
GND GND - - AA16
GND GND - - AK1
GND GND - - AK30
GND GND - - K15
GND GND - - K16
GND GND - - L11
GND GND - - L12
GND GND - - L13
GND GND - - L14
GND GND - - L15
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-25
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
GND GND - - L16
GND GND - - L17
GND GND - - L18
GND GND - - L19
GND GND - - L20
GND GND - - M11
GND GND - - M12
GND GND - - M13
GND GND - - M14
GND GND - - M15
GND GND - - M16
GND GND - - M17
GND GND - - M18
GND GND - - M19
GND GND - - M20
GND GND - - N11
GND GND - - N12
GND GND - - N13
GND GND - - N14
GND GND - - N15
GND GND - - N16
GND GND - - N17
GND GND - - N18
GND GND - - N19
GND GND - - N20
GND GND - - P11
GND GND - - P12
GND GND - - P13
GND GND - - P14
GND GND - - P15
GND GND - - P16
GND GND - - P17
GND GND - - P18
GND GND - - P19
GND GND - - P20
GND GND - - R10
GND GND - - R11
GND GND - - R12
GND GND - - R13
GND GND - - R14
GND GND - - R15
GND GND - - R16
GND GND - - R17
GND GND - - R18
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-26
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
GND GND - - R19
GND GND - - R20
GND GND - - R21
GND GND - - T10
GND GND - - T11
GND GND - - T12
GND GND - - T13
GND GND - - T14
GND GND - - T15
GND GND - - T16
GND GND - - T17
GND GND - - T18
GND GND - - T19
GND GND - - T20
GND GND - - T21
GND GND - - U11
GND GND - - U12
GND GND - - U13
GND GND - - U14
GND GND - - U15
GND GND - - U16
GND GND - - U17
GND GND - - U18
GND GND - - U19
GND GND - - U20
GND GND - - V11
GND GND - - V12
GND GND - - V13
GND GND - - V14
GND GND - - V15
GND GND - - V16
GND GND - - V17
GND GND - - V18
GND GND - - V19
GND GND - - V20
GND GND - - W11
GND GND - - W12
GND GND - - W13
GND GND - - W14
GND GND - - W15
GND GND - - W16
GND GND - - W17
GND GND - - W18
GND GND - - W19
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-27
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
GND GND - - W20
GND GND - - Y11
GND GND - - Y12
GND GND - - Y13
GND GND - - Y14
GND GND - - Y15
GND GND - - Y16
GND GND - - Y17
GND GND - - Y18
GND GND - - Y19
GND GND - - Y20
VCCIO7 VCCIO7 - - H2
VCCIO7 VCCIO7 - - N4
VCCIO7 VCCIO7 - - N6
VCCIO7 VCCIO7 - - J2
VCCIO7 VCCIO7 - - L2
VCCIO7 VCCIO7 - - H4
VCCIO6 VCCIO6 - - AB2
VCCIO6 VCCIO6 - - AD1
VCCIO6 VCCIO6 - - W4
VCCIO6 VCCIO6 - - AA4
VCCIO5 VCCIO5 - - AE7
VCCIO5 VCCIO5 - - AH6
VCCIO5 VCCIO5 - - AG11
VCCIO5 VCCIO5 - - AJ9
VCCIO4 VCCIO4 - - AJ23
VCCIO4 VCCIO4 - - AG20
VCCIO4 VCCIO4 - - AJ26
VCCIO4 VCCIO4 - - AG23
VCCIO3 VCCIO3 - - AC29
VCCIO3 VCCIO3 - - AA26
VCCIO3 VCCIO3 - - Y28
VCCIO3 VCCIO3 - - AA29
VCCIO2 VCCIO2 - - G30
VCCIO2 VCCIO2 - - J29
VCCIO2 VCCIO2 - - K27
VCCIO2 VCCIO2 - - N25
VCCIO1 VCCIO1 - - F20
VCCIO1 VCCIO1 - - C19
VCCIO1 VCCIO1 - - C12
VCCIO1 VCCIO1 - - F11
GND GND - - H1
GND GND - - L4
GND GND - - M3
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-28
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
GND GND - - N5
GND GND - - K2
GND GND - - M2
GND GND - - P6
GND GND - - G4
GND GND - - H3
GND GND - - AC2
GND GND - - AA3
GND GND - - AE1
GND GND - - Y4
GND GND - - AB4
GND GND - - AA5
GND GND - - AE6
GND GND - - AE8
GND GND - - AH5
GND GND - - AG9
GND GND - - AG6
GND GND - - AF11
GND GND - - AG12
GND GND - - AJ10
GND GND - - AK26
GND GND - - AJ22
GND GND - - AF20
GND GND - - AJ25
GND GND - - AJ27
GND GND - - AF23
GND GND - - AF22
GND GND - - AE27
GND GND - - AA27
GND GND - - AB29
GND GND - - Y26
GND GND - - AC30
GND GND - - Y29
GND GND - - F30
GND GND - - E27
GND GND - - F27
GND GND - - P25
GND GND - - H29
GND GND - - K29
GND GND - - R24
GND GND - - M28
GND GND - - J27
GND GND - - N26
GND GND - - E20
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGA4-29
Pinout Information
Lattice Semiconductor LatticeSC Family Data Sheet
GND GND - - E21
GND GND - - F21
GND GND - - F23
GND GND - - G23
GND GND - - D21
GND GND - - D20
GND GND - - E18
GND GND - - C20
GND GND - - C11
GND GND - - A12
GND GND - - E11
GND GND - - F8
GND GND - - G8
GND GND - - D11
GND GND - - D10
GND GND - - H7
GND GND - - F10
GND GND - - E10
NC _ - - AC16
VCC VCC - - J22
VCC VCC - - J9
1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement).
LFSC25 Logic Signal Connections: 900-Ball ffBGA1
(Continued)
Ball Function I/O VCCIO Bank VREF Group Dual Function 900 ffBGAFebruary 2006 Preliminary Data Sheet
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 5-1 Ordering Information_01.0
Part Number Description
Ordering Information
Commercial
Industrial
Part Number I/Os Grade Package Balls Temp. LUTs (K)
LFSC3GA25E-7F900C 378 -7 fpBGA 900 COM 25.4
LFSC3GA25E-6F900C 378 -6 fpBGA 900 COM 25.4
LFSC3GA25E-5F900C 378 -5 fpBGA 900 COM 25.4
Part Number I/Os Grade Package Balls Temp. LUTs (K)
LFSCM3GA25EP1-7F900C 378 -7 fpBGA 900 COM 25.4
LFSCM3GA25EP1-6F900C 378 -6 fpBGA 900 COM 25.4
LFSCM3GA25EP1-5F900C 378 -5 fpBGA 900 COM 25.4
Part Number I/Os Grade Package Balls Temp. LUTs (K)
LFSC3GA25E-6F900I 378 -6 fpBGA 900 IND 25.4
LFSC3GA25E-5F900I 378 -5 fpBGA 900 IND 25.4
Part Number I/Os Grade Package Balls Temp. LUTs (K)
LFSCM3GA25EP1-6F900I 378 -6 fpBGA 900 IND 25.4
LFSCM3GA25EP1-5F900I 378 -5 fpBGA 900 IND 25.4
LF XXX XXX XX E PX – X XXXXXX X
Grade
C = Commercial
I = Industrial
SERDES Speed
3GA = 3.8G
Supply Voltage
E = 1.2V
Logic Capacity
15K LUTs
25K LUTs
40K LUTs
80K LUTs
115K LUTs
Device Family
LatticeSC FPGA
LatticeSCM FPGA
LF = Lattice FPGA
Package*
F256 = 256 fpBGA
F900 = 900 fpBGA
FF1020 = 1020 ffBGA
FC1152 = 1152 fcBGA
FC1704 = 1704 fcBGA
Speed Grade
-5 (Slowest)
-6
-7 (Fastest)
Predefined Function (LatticeSCM Only)
P1 = Initial MACO Option
*Note: fpBGA = 1.0mm pitch BGA, ffBGA = 1.0mm flip-chip BGA, fcBGA = 1.0mm ceramic flip-chip BGA
LatticeSC Family Data Sheet
Ordering InformationFebruary 2006 Preliminary Data Sheet
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 6-1 Further Information_01.0
For Further Information
A variety of technical notes for the LatticeSC family are available on the Lattice web site at www.latticesemi.com.
• PURESPEED I/O Usage Guide (TN1088)
• LatticeSC sysCLOCK and PLL/DLL User’s Guide (TN1098)
• On-Chip Memory Usage Guide for LatticeSC Devices (TN1094)
• LatticeSC DDR/DDR2 SDRAM Memory Interface User’s Guide (TN1099)
• LatticeSC QDR-II SRAM Memory Interface User’s Guide (TN1096)
• LatticeSC sysCONFIG Usage Guide (TN1080)
• LatticeSC MPI/System Bus (TN1085)
• Power Calculations and Considerations for LatticeSC Devices (TN1101)
For further information on Interface standards refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• Hyper Transport: www.hypertransport.org
• Optical Interface (SPI-4.2, XSBI, CSIX and XGMII): www.oiforum.com
• RAPIDIO: www.rapidio.org
• PCI/PCIX: ww.pcisig.com
LatticeSC Family Data Sheet
Supplemental Information
Power 2You A Guide to Power Supply Management and Control
Shyam Chandra
LEARN HOW TO:
» Reduce Power Management Costs
» Increase System Reliability
» Reduce the Risk of Circuit Board Respins
Board Power Management Functionsi
Power 2 You
A Guide to Power Supply
Management and Control
Shyam Chandraii
Copyright © 2010 Lattice Semiconductor Corporation, 5555 NE Moore Court, Hillsboro, Oregon 97124, USA. All
rights reserved.
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice
(design), LSC, ispPAC, PAC, PAC-Designer are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Revision History:
April 2010: First Edition
September 2010: Second Edition
While every precaution has been taken in the preparation of this book, the author assumes no responsibility for
errors or omissions, or for damages resulting from the use of the information contained herein.
ACKNOWLEDGEMENTS
It takes a team of hardworking professionals to take a collection of documents, ideas, and diagrams and turn them
into a finished book. Many thanks to Brian Kiernan, Buck Bartel, Chris Dix, Ed Coughlin, Ed Ramsden, Gordon
Hands, Jeff Davis, Jim Krebs, John Alberts, Mark van Wyk, Nancy Knowlton, Shoji Sugawara, Ted Marena, Troy
Scott, and Vesa Lauri. The contributions and efforts of these individuals helped to make the dream of this book a
reality.
ISBN: 978-0-578-06604-2iii
Chapter 1. Introduction .......................................................1-1
1.1 Power 2 You............................................................................................................................................ 1-1
What is Power Management?.............................................................................................................. 1-1
Typical Board Power Supply Architectures ........................................................................................ 1-2
Typical Power Management Implementations and Their Drawbacks................................................. 1-4
1.2 Lattice Power Manager II IC Family ...................................................................................................... 1-5
1.3 PAC-Designer Software.......................................................................................................................... 1-8
1.4 Summary of Chapters.............................................................................................................................. 1-8
Chapter 2. Solutions Summary ..........................................2-1
2.1 N-Supply Supervisor, Reset Generator and Watchdog Timer................................................................ 2-1
2.2 Power Supply Sequencing ...................................................................................................................... 2-3
Flexible N-Supply Sequencing............................................................................................................ 2-3
Sequencing with MOSFETs and DC-DC Enables .............................................................................. 2-4
2.3 Hot-Swap Controllers ............................................................................................................................. 2-6
Hot-Swap Controller Using Soft-Start Mechanism............................................................................. 2-6
Hot-Swap Controller with Hysteretic Current Limit Mechanism ....................................................... 2-7
12V/24V Hot-Swap Controller............................................................................................................ 2-8
Negative Supply Hot-Swap Controller................................................................................................ 2-9
CompactPCI Board Management...................................................................................................... 2-11
CompactPCI Express Board Management ........................................................................................ 2-12
2.4 Redundant Supply Management ........................................................................................................... 2-14
Two Rail 5V Power Supply OR’ing (Using MOSFETs) .................................................................. 2-14
Table of ContentsTable of Contents
iv
Power Supply OR’ing of N-Rails Using MOSFETS ........................................................................ 2-15
N-rail (12V/24V) OR’ing .................................................................................................................. 2-16
-48V Supply OR’ing Through MOSFETS........................................................................................ 2-17
2.5 Power Feed Controllers......................................................................................................................... 2-19
Dual Rail -48V Power Feed Controller ............................................................................................. 2-19
Three-Channels of a 6V-24V Power Feed System............................................................................ 2-20
Two-Channel +12V & 3.3V Power Feed With Diode OR’ing ......................................................... 2-21
2.6 Trimming and Margining...................................................................................................................... 2-23
Chapter 3. Reset Generators & Supervisors.....................3-1
3.1 Introduction............................................................................................................................................. 3-1
Reliable Reset Generation by Monitoring All Supply Rails ............................................................... 3-2
Parts of a Supervisor IC....................................................................................................................... 3-3
Effect of Monitoring Accuracy on System Functionality ................................................................... 3-4
Reduced Accuracy Results in Reducing the Power Supply Tolerance
Headroom ............................................................................................................................................ 3-6
Using a Supervisor IC With an Accuracy Of 1%................................................................................ 3-6
Effects of Fault Detection Delay ......................................................................................................... 3-6
If the Fault Detection Delay is 1ms:.................................................................................................... 3-7
If the Fault Detection Delay is 50µs:................................................................................................... 3-7
Supervisors Built Using ADC and a Microcontroller are Slow .......................................................... 3-8
Other Factors Contributing to Increased Reliability............................................................................ 3-8
3.2 N-Supply Supervisor, Reset Generator and Watchdog Timer.............................................................. 3-10
Circuit Operation ............................................................................................................................... 3-10
Reset Generator, Supervisor and Watchdog Timer Algorithm......................................................... 3-11
Parallel Equations of the Algorithm .................................................................................................. 3-11
Programmable Features ..................................................................................................................... 3-11
Additional Features That Can be Added to ProcessorPM-POWR605 ............................................. 3-11
Relevant Power Manager II ICs ........................................................................................................ 3-11
Chapter 4. Power Supply Sequencing...............................4-1
4.1 Introduction............................................................................................................................................. 4-1
Sequencing Power Supplies with Conflicting Sequencing
Requirements....................................................................................................................................... 4-1
Other Factors Adding Complexity to Sequencing Algorithm............................................................. 4-2
4.2 Flexible N-Supply Sequencing Using Power Manager II II Devices ..................................................... 4-3
Voltages are Monitored During/After Sequencing.............................................................................. 4-3
N-Supply Closed Loop Sequencing Algorithm................................................................................... 4-5
N-supply Closed Loop Sequencing with Failure Monitor Algorithm................................................. 4-6
Applying LogiBuilder Instructions to Sequencing Methods............................................................... 4-6
Advantages of Power Manager II-based Supply Sequencing ............................................................. 4-8 Table of Contents
v
Additional Power Management Functions that can be Integrated into Power Manager II ................. 4-8
Applicable Power Manager II Devices................................................................................................ 4-8
4.3 Sequencing With MOSFETs and DC-DC Converter Enables................................................................ 4-9
Circuit Operation ................................................................................................................................. 4-9
Power Sequencing Algorithm............................................................................................................ 4-10
Applicable Power Manager II Devices.............................................................................................. 4-10
Chapter 5. Hot-Swap Controllers .......................................5-1
5.1 What is a Hot-Swap Controller? ............................................................................................................. 5-1
Hot-Swap Circuit Design Considerations............................................................................................ 5-2
5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices .................... 5-2
Hot-Swap Controller Using Soft-start ................................................................................................. 5-3
Hot-Swap Controller with Hysteretic Current Limit Mechanism ....................................................... 5-4
12V/24V Hot-Swap Controller............................................................................................................ 5-8
5.3 Implementing a Negative Supply Hot-Swap Controller ....................................................................... 5-13
Controlling Current Inrush While Operating the MOSFET in its Safe Operating Area ................... 5-14
Customizing the -48V Hot-Swap Controller..................................................................................... 5-15
5.4 CompactPCI Board Management ......................................................................................................... 5-16
CompactPCI Express Board Management ........................................................................................ 5-19
Chapter 6. Power Supply OR’ing Controllers ...................6-1
6.1 What is Power Rail OR'ing? ................................................................................................................... 6-1
6.2 Challenges of Designing a MOSFET OR’ing Circuit .......................................................................... 6-2
6.3 +5v Power Supply OR’ing (Using MOSFETs) Circuit ......................................................................... 6-3
6.4 Power Supply OR’ing of Three or More 5V Supply Rails Using MOSFETS ....................................... 6-5
6.5 N-rail (12V/24V) OR’ing......................................................................................................................... 6-7
6.6 -48V Supply OR’ing Through MOSFETS ............................................................................................ 6-10
Chapter 7. Power Feed Controllers....................................7-1
7.1 What are Power Feed Controllers? ......................................................................................................... 7-1
7.2 Dual Rail -48V Supply Feed................................................................................................................... 7-1
Circuit Operation ................................................................................................................................. 7-2
Algorithm............................................................................................................................................. 7-3
Programmable Features of this Circuit................................................................................................ 7-4
Applicable devices:.............................................................................................................................. 7-4
7.3 Three Channels of a +12V Power Feed System ..................................................................................... 7-4
Circuit Operation ................................................................................................................................. 7-5
Dual Current Level Hysteretic Control ............................................................................................... 7-6
Algorithm for Each Power Feed Channel............................................................................................ 7-7
Programmable Features of Power Feed............................................................................................... 7-7Table of Contents
vi
Integrating Other Payload Power Management Functions into the ispPAC-POWR1014A Device ... 7-7
Applicable Power Manager II Devices................................................................................................ 7-8
7.4 2-Channel +12V & 3.3V Power Feed With MOSFET OR’ing .............................................................. 7-8
Circuit Operation ................................................................................................................................. 7-9
During Operation......................................................................................................................................... 7-
ispPAC-POWR1014A (MicroTCA) Power Feed Algorithm............................................................ 7-10
Programmable Features ............................................................................................................................. 7-
Other Functional Enhancements........................................................................................................ 7-11
Applicable Power Manager II Devices.............................................................................................. 7-11
Chapter 8. Margining and Trimming ..................................8-1
8.1 What is Voltage Margining? ................................................................................................................... 8-1
8.2 Voltage Margining Implementation........................................................................................................ 8-1
8.3 What is Trimming? ................................................................................................................................. 8-2
Typical Applications That Require Power Supply Trimming............................................................. 8-3
8.4 Trimming and Margining – Principle of Operation ................................................................................ 8-3
Power Manager II TrimCell Architecture ........................................................................................... 8-4
Power Manager II Integrates Multiple TrimCells ............................................................................... 8-6
Closed Loop Trim - Mode Operation of TrimCell.............................................................................. 8-7
Closed Loop Trim and Closed Loop Margining Using a Microcontroller.......................................... 8-8
Interfacing Power Manager II with a DC-DC converter ..................................................................... 8-9
Designing Trimming and Margining Networks using PAC-Designer Software............................... 8-11
Creating a DC-DC Converter Library Entry ..................................................................................... 8-11
Chapter 9. Design Tools for Power Manager II .................9-1
9.1 PAC-Designer: Power Management Design Tool .................................................................................. 9-1
Benefits of Software-Driven Programmable Hardware Design.......................................................... 9-2
9.2 PAC-Designer Overview ........................................................................................................................ 9-3
Selecting the Power Manager II Device from a Design Specification................................................ 9-3
Power Manager II Design Example..................................................................................................... 9-5
Design Flow......................................................................................................................................... 9-6
9.3 Example Design Resources..................................................................................................................... 9-6
9.4 Designing PCI-Express Add-on Card Power Management Using an ispPAC-POWR1014A Device ... 9-7CHAPTER
1
1-1
Introduction
1.1 Power 2 You
This book provides technical details and design considerations for implementing the common
circuit board power management functions shown as 3-D blocks in Figure 1-1 and Figure 1-2.
This book also provides generalized cost effective solutions for each of these functions that can
be customized to meet a circuit board’s specific voltage, current and control environment.
For readers viewing this document in .pdf format, the 3-D blocks in Figure 1-1 and Figure 1-2
are hyperlinked to the appropriate section of Chapter 2, where multiple circuit options are provided for that particular power management function. Each of the circuit options hyperlink to a
detailed description in the relevant chapters.
If you are already familiar with Lattice Semiconductor Power Manager II devices and need to
find a solution for a power management function:
1. Click on the required power management block in Figure 1-1.
2. You will automatically navigate to the section of Chapter 2 that provides multiple circuit
options for the selected power management function.
3. Click on the relevant circuit option.
4. You will automatically navigate to the detailed description of that circuit diagram.
If you wish to read about the general board power management blocks, the design criteria and
circuit options, read this chapter. After reading this chapter, you can skip Chapter 2 - “Solutions Summary” on page 2-1 and continue with Chapter 3 - “Reset Generators & Supervisors”
on page 3-1.
What is Power Management?
Every circuit board is powered from one or more sources called the input, or primary, power
supplies. And, every circuit board performs one or more functions using a number of ICs, such
as ASICs, CPUs, FPGAs, and so on. These ICs are called the payload ICs. The circuit board
generates multiple power rails from the input supplies to power these payload ICs, using board Power 2 You: A Guide to Power Supply Management and Control
1-2 Introduction
mounted supplies called primary and secondary supplies. The term ‘Power Management’ in this book
includes all power rail control functions implemented in a circuit board. Typically, input power rails are
controlled by power management functions such as hot-swap control and redundant power rail control.
On the payload side, power management functions include sequencing, monitoring, supervisory signal
generation, trimming and margining.
Typical Board Power Supply Architectures
Circuit boards can be broadly classified into two types:
1. Boards that derive input power supply from a backplane with its power always on and the boards
plugged into or extracted from the backplane without turning the power off – these are called hotswappable boards, shown in Figure 1-1.
2. Boards that derive power from an external power supply that is turned on after the board is connected
and is turned off before the board is disconnected – these are called non hot-swappable boards.
There are solutions to implement all of the critical power supply control functions. Advanced power supply designers can click on any of the hyperlinked functions to see the solution. To learn the background of
all these functions, continue reading this chapter.
Figure 1-1. Power Management in a Hot-Swappable Circuit Board. (If viewing this document in .pdf format,
click on any of the 3-D blocks to jump to implementation details.)
Figure 1-1 illustrates the power supply architecture of a circuit board with the common power management blocks shown in 3-D. A hot-swappable board derives its power from one or more supplies from the
backplane. There can be more than one set of supplies sourced from the backplane, so these boards are
operational even when one of the supplies fails. The backplane supplies in Figure 1-1 are also called the
primary supplies.
In systems that require high availability, such as telecom / datacom systems, backplanes provide redundant supplies called on-line and standby power. The Power Supply OR’ing Controller, also called the
redundant power supply controller, selects between the online and standby supplies to derive the
power to the board. (Refer to “2.4 Redundant Supply Management” on page 2-14.)
In order to extract and reinsert the boards from the backplane without disturbing the other boards plugged
into the same backplane, a hot-swap controller function is implemented on each of these circuit boards.
Hot-Swap
Controller DC-DC
Primary
Sequence
Control
Monitor
Voltage &
Current
Reset
Generation
DC-DC
Secondary
DC-DC
Secondary
DC-DC
Secondary
Power
Supply
OR’ing
Controller
DC-DC
Primary
DC-DC
Primary
Trimming
&
Margining
Backplane
Power
Payload ICs Sequencing
Thru MOSFETs
Chapter 6 Chapter 5
Chapter 4
Power Feed
to External
Chapter 7 Systems
Chapter 3
Chapter 8Power 2 You: A Guide to Power Supply Management and Control
Introduction 1-3
Introduction
(Refer to “2.3 Hot-Swap Controllers” on page 2-6.) In some cases, the supply rail output from the hotswap controller feeds one or more DC-DC converters, shown in Figure 1-1 as ‘DC-DC Primary’ supplies.
Primary supplies are used to derive one or more main payload supply rails, which are also called secondary supply rails and are shown in Figure 1-1 as the ‘DC-DC Secondary’ supplies. These secondary supplies may have to be sequenced either through the DC-DC converter enable signals or through
MOSFETs. Sequencing of these supplies is controlled by the sequence controller. (Refer to “2.2 Power
Supply Sequencing” on page 2-3.) After all supplies are sequenced, the reset generator starts the board’s
normal operation by releasing the reset signal to the CPU. (Refer to “2.1 N-Supply Supervisor, Reset
Generator and Watchdog Timer” on page 2-1.) The voltage and current are monitored for faults and
board shut down or reset generation functions are initiated as a result. (Refer to “2.1 N-Supply Supervisor, Reset Generator and Watchdog Timer” on page 2-1.) In addition, monitoring these lower voltages for
faults should take into consideration, and compensate for, other error sources such as the ground voltage
difference between the supply and the monitoring device. For example, the fault level of 1.2V is 1.2V *
5% = ±60mV. The ground voltage difference between different points in the circuit board can be be as
much as 20mV to 30mV. To compensate for the error, differential sensing, as shown in Figure 3-9 on
page 9, is used.
Modern ICs require lower core voltages (1.2V or lower) with high current capacity (10A or higher) with
reduced voltage tolerance. To meet these stringent supply requirements, a power supply trimming controller is often required. (Refer to “2.6 Trimming and Margining” on page 2-23.)
For quality assurance purposes, four-corner testing of boards (voltage and temperature) frequently
requires margining of supplies. These boards use margining controllers. (Refer to “2.6 Trimming and
Margining” on page 2-23.)
In some applications, such as GSM basestation boards, microwave boards and boards supporting hotpluggable mezzanine cards, it may be necessary to power an external unit, such as a remote radio head or
an outdoor antenna, or supply power to an AMC. To support these functions, the power feed controller
is required. (Refer to “2.5 Power Feed Controllers” on page 2-19.)
Figure 1-2 shows the power management requirements in a non hot-swappable circuit board. These
boards require primary and secondary power management controllers, as shown in Figure 1-2. The only
primary power management function that is not relevant in these non-hot-swappable boards is the hotswap controller. Systems that typically require non-hot-swappable boards include routers in “pizza-box”
form factor, personal computers and medical ultrasound systems.Power 2 You: A Guide to Power Supply Management and Control
1-4 Introduction
Figure 1-2. Power Management in a Non-Hot-Swappable Circuit Board. (If viewing this document in .pdf format, click on any of the 3-D blocks to jump to implementation details.)
Typical Power Management Implementations and Their Drawbacks
The power rails in a board currently are managed by simple, single function integrated circuits (ICs) on
both the primary and secondary sides. On the input side, each function shown in Figure 1-1 requires different ICs, depending on the rail voltage, board power and other control specifications.
Modern circuit boards with complex payload ICs typically require five or more secondary power rails.
Monitoring, sequencing and the generation of resets in these boards require multiple single function ICs.
Together, the power management section requires multiple types of single function power management
ICs in a given system. This results in a larger bill of materials (BOM), higher cost of inventory and
assembly, as well as reduced reliability.
The cost of the power management portion in a circuit board increases with the number of rails, and the
number of power management functions. Lower cost single function power management ICs are usually
less accurate in monitoring for faults, resulting in reduced board reliability.
In order to reduce the number of secondary power management ICs, some designs use microcontrollers
with an Analog-to-Digital (ADC) converter to monitor power supplies and use software to adapt to
board-specific requirements. These microcontrollers are too slow to respond to power supply faults (5 to
10ms) and are unreliable, as they use hundreds of lines of code to perform power management functions
and require a watchdog timer to monitor software flow. Microcontrollers are also used because the
changes to power management can be met simply by changing software, as opposed to modifying the circuit board layout. However, modifications to software are almost always avoided, as most companies
have strict control over software releases.
The ideal power management solution is the one that has the following characteristics:
1. Lower cost and reduced bill of material, and flexibility to meet individual board power management
needs.
2. Increased board reliability through increased supply fault monitoring accuracy.
DC-DC
Primary
Sequence
Control
Monitor
Voltage &
Current
Reset
Generation
DC-DC
Secondary
DC-DC
Secondary
DC-DC
Secondary
Power
Supply
OR’ing
Controller
DC-DC
Primary
DC-DC
Primary
Trimming
&
Margining
Input Supply
Payload ICs Sequencing
Thru MOSFETs
Chapter 6
Chapter 4
Power Feed
to External
Systems Chapter 7
Chapter 3
Chapter 8Power 2 You: A Guide to Power Supply Management and Control
Introduction 1-5
Introduction
3. Reduced risk of circuit board re-layout to board power management through programmability.
This book details how a Lattice Power Manager II device can integrate all of these functions. Because
these devices are in-system programmable, each device can be programmed to meet a wide variety of circuit board functions.
1.2 Lattice Power Manager II IC Family
There are five members in the Power Manager II family of devices: ispPAC®
-POWR1220AT8, ispPACPOWR1014A, ispPAC-POWR1014, ispPAC-POWR607 and ProcessorPM™-POWR605.
Figure 1-3 shows the part numbering convention of the Lattice Power Manager II product family.
Figure 1-3. Lattice Power Manager II Family Part Numbers Indicate I/O Resources
While the largest device, the ispPAC-POWR1220AT8, can be used to implement complex power management functions, the smallest device, the ProcessorPM-POWR605, can be used to implement power
management functions for a wide variety of microprocessors and DSPs. All Power Manager II devices
can be programmed in-system through the JTAG interface. The power management algorithm can be
designed using the PAC-Designer®
software tool that can be downloaded from the Lattice website free of
charge.
Figure 1-4 shows the architecture of the largest member of the family, the ispPAC-POWR1220AT8.
Figure 1-4. ispPAC-POWR1220AT8 Device Block Diagram
Digital Outputs
ispPAC-POWR XX YY A T 8
Trim Outputs
Trimming if Present
ADC if Present
Analog Inputs
4 X
High Voltage
MOSFET Driver
16 Open
Drain
Outputs
6
Digital Inputs
I
2
C Interface Timers &
Oscillator
ADC
(10-bit )
Non-Volatile
Configuration
JTAG
8X Margin/ Trim
Control
8 Margin/Trim
• Closed Loop Trim
• Precision Output Voltage
Control (<1%)
12 Voltage Monitors
• 2 Comparators Per Rail
• UV & OV
• Differential Voltage Sense
• Programmable Thresholds
• Range - 0.67V to 5.7V
• 368 Steps
• Accuracy 0.2% (Typ.)
20 Outputs
• 4 Programmable MOSFET Drivers
• 16 Digital Open-Drain Controls
100-pin TQFP Package
48
Macrocell
PLDPower 2 You: A Guide to Power Supply Management and Control
1-6 Introduction
This device can manage up to 12 supply rails and generate 20 outputs (including four programmable
MOSFET drive outputs) using its on-chip 48-macrocell ruggedized CPLD. All supply voltages can be
measured using the on-chip 10-bit ADC device via the I2
C interface. This device also supports trimming
and margining of up to eight DC-DC converters. Various time delays used in the power management
algorithm can be realized by four on-chip programmable hardware timers.
The ispPAC-POWR1220AT8 device can integrate the following power management functions:
• Power supply OR’ing
• Positive rail power feed to external system
• Hot-swap controller for positive voltage rail
• Sequencing
• Voltage and current monitoring
• Reset generation
• Trimming and margining
• Watchdog timer
Figure 1-5 is a block diagram of the next members of the Lattice Power Manager II family, the ispPACPOWR1014 and ispPAC-POWR1014A.
Figure 1-5. Block Diagram of ispPAC-POWR1014 & ispPAC-POWR1014A Devices
These devices can monitor up to 10 supply rails and generate 14 power management control outputs
(including two programmable MOSFET drivers) using an on-chip 24-macrocell PLD block. The ispPACPOWR1014A device provides a 10-bit ADC and an I2
C interface to measure all supply voltages. Various
time delays used in the power management algorithm can be realized by four on-chip programmable
hardware timers.
The ispPAC-POWR1014/A devices can integrate the following power management functions:
2 X
High Voltage
MOSFET Driver
12 Open
Drain
Outputs
4
Digital Inputs
I
2
C*
Interface
Timers &
Oscillator
ADC*
(10-bit )
Non-Volatile
Configuration
JTAG
* ADC and I2
C Interface in ispPAC-POWR1014A only.
10 Voltage Monitors
• 20 Precision Comparators
• Programmable Thresholds
• Range - 0.67V to 5.7V
• 368 Steps
• Accuracy 0.3% (Typ.)
14 Outputs
• 2 Programmable MOSFET Drivers
• 12 Digital Open-Drain Controls
48-pin TQFP Package
24
Macrocell
PLDPower 2 You: A Guide to Power Supply Management and Control
Introduction 1-7
Introduction
• Power Supply OR’ing
• Hot-swap controller for positive voltage rail
• Positive or negative power feed controller
• Sequencing
• Voltage and current monitoring
• Reset generation, sequencing
• Watchdog timer
The ispPAC-POWR607 device shown in Figure 1-6 can monitor up to six supplies and supports seven
outputs (including two MOSFET drivers) that are controlled by the on-chip 16-macrocell PLD. Various
time delays used in the power management algorithm can be realized by four on-chip programmable
hardware timers.
Figure 1-6. Block Diagram of an ispPAC-POWR607 Device
This device can be powered down using a digital signal. The ispPAC-POWR607 device can be used for
the following functions:
• Power Supply OR’ing
• Hot-swap controller for positive voltage rail
• Hot-swap controller for negative voltage rail
• Positive or negative power feed controller sequencing
• Reset generation
• Watchdog timer
Figure 1-7 shows the ProcessorPM-POWR605 device, which is ideal for implementing power management functions for any processor or DSP. This device can monitor up to six supplies and generate five
outputs that are controlled by the on-chip 16-macrocell PLD. Various time delays used in the power management algorithm can be realized by four on-chip programmable hardware timers.
2 X
High Voltage
MOSFET Driver
5 Open
Drain I/O
2
Digital Inputs
Timers &
Oscillator
Non-Volatile
Configuration
JTAG
Power Down Control
Powered-Down Mode < 10µA
6 Voltage Monitors
• Programmable Thresholds
• Range - 0.67V to 5.7V
• 192 Steps
• Accuracy 0.5% (Typ.)
7 Outputs
• 2 Programmable MOSFET Drivers
• 5 Digital Open-Drain I/O
32-pin QFN Package
16
Macrocell
PLDPower 2 You: A Guide to Power Supply Management and Control
1-8 Introduction
Figure 1-7. Architecture of the ProcessorPM-POWR605 Device
The ProcessorPM-POWR605 device can be used to integrate the following functions:
• Voltage supervision
• Reset generation
• Watchdog timer
1.3 PAC-Designer Software
Board-specific power management is implemented using the PAC-Designer software: an intuitive, userfriendly software tool set. The PAC-Designer software enables the following:
1. Configure voltage monitoring thresholds for a given voltage rail.
2. Configure MOSFET driver characteristics to meet turn on and off ramp rates.
3. Implement power management functions such as hot-swap controller, sequencer, reset generator
through LogiBuilder (simple configurable sequencer steps and logic equations).
4. Simulate the power management algorithm using either high-end tools such as Aldec®
Active-HDL™
or Mentor Graphics®
ModelSim™, or use the waveform simulator built into the software.
5. Calculate the resistor values to be connected between the Power Manager II devices and the DC-DC
converters for implementing Trimming and Margining functions.
6. Generate JEDEC files and SVF files for programming the device using standard programming
methods.
1.4 Summary of Chapters
This book has nine chapters. Chapter 3 to Chapter 8 each cover a power management function in detail.
Chapter 1 - “Introduction” on page 1-1 – summarizes the power management functions, explains drawbacks of traditional power management solutions, and provides a brief introduction to Lattice Power
Manager II products.
5 Open
Drain I/O
2
Digital Inputs
Timers &
Oscillator
Non-Volatile
Configuration
JTAG
Power Down Control
5 Outputs
• 5 Digital Open-Drain I/O
6 Voltage Monitors
• Programmable Thresholds
• Range - 0.67V to 5.7V
• 192 Steps
• Accuracy 0.5% (Typ.)
Powered-Down Mode < 10µA
24-pin QFN Package
16
Macrocell
PLDPower 2 You: A Guide to Power Supply Management and Control
Introduction 1-9
Introduction
Chapter 2 - “Solutions Summary” on page 2-1 – is a summary of all of the solutions provided for each of
the power management functions shown in Figure 1-1.
Chapter 3 - “Reset Generators & Supervisors” on page 3-1 – describes reset generator supervisor and
watchdog timer and identifies some of the common pitfalls to avoid in voltage supervision and reset generation in circuit boards with multiple power supplies.
Chapter 4 - “Power Supply Sequencing” on page 4-1 – shows how a flexible power supply sequencing
arrangement provides a solution. This section also describes software-based sequencing methodology.
Chapter 5 - “Hot-Swap Controllers” on page 5-1 – describes design considerations for implementing hotswap controllers and selecting MOSFETs. This chapter also provides hot-swap controller solutions for
positive rail, negative rail, and multiple backplane rails.
Chapter 6 - “Power Supply OR’ing Controllers” on page 6-1 – describes the design considerations and
provides N-rail positive and negative rail OR’ing solutions.
Chapter 7 - “Power Feed Controllers” on page 7-1 – provides design considerations for implementing
power feed controllers and selecting MOSFETs. N-supply positive and negative rail power feed, and
MicroTCA power module design, are also discussed.
Chapter 8 - “Margining and Trimming” on page 8-1 – describes the need for trimming and margining of
supplies, provides trimming and margining solutions, and describes how to implement these designs
using software.
Chapter 9 - “Design Tools for Power Manager II” on page 9-1 – describes the software flow, provides a
description of each of the steps, and describes software implementation of complex power management
designs.Power 2 You: A Guide to Power Supply Management and Control
1-10 Introduction
This page intentionally left blank.CHAPTER
2
2-1
Solutions Summary
2.1 N-Supply Supervisor, Reset Generator and
Watchdog Timer
Features of Supervisor, Reset Generator and Watchdog Timer in a
Power Manager II Device
• Monitors up to 12 rails for over-voltage / under-voltage faults
• Precision (0.2% typ.) programmable monitoring threshold from 0.67V to 5.8V
• Differential voltage sensing for monitoring low voltage, high current supplies
• Fast fault detection with glitch filtering – up to 64s
• Reset generation with programmable pulse stretch of up to hundreds of milliseconds
• Low voltage interrupt generation
• Manual reset input with programmable de-bounce period
• Watchdog timer with programmable time delay from hundreds of milliseconds to minutes
• Flexible watchdog timer interrupt / reset signal combinations
• All features can be changed after assembly through in-system programming
• Over-voltage protection and under-voltage lock-out
• Integrates additional functions such as sequencing, hot-swap, trimming and margining
• Measures voltage and current through I2
C. (A detailed circuit description of a design using
ProcessorPM-POWR605 device is provided in “3.2 N-Supply Supervisor, Reset Generator
and Watchdog Timer” on page 3-10.)Power 2 You: A Guide to Power Supply Management and Control
2-2 Solutions Summary
Figure 2-1. ProcessorPM-POWR605 Integrating 6-Supply Supervisor, Reset Generator and Watchdog Timer
Advantages of Supervisor, Reset Generator and Watchdog Timer in a
Power Manager II Device
• Lowers cost compared to multiple supervisor and reset ICs
• Reduces number of components – No resistors to set threshold, no capacitors to set time delay
• Increases functional reliability – Very fast fault detection, higher monitoring precision, fewer components
• Reduces spurious supply fault interrupts due to supervisor monitoring threshold accuracy and filtering
supply glitches
• Reduces risk – Accommodates changes to specs through programmability
• Reduces part types – Single chip can be used across a wide range of applications
• Protects board against over-voltage faults by initiating shut-down. (A detailed circuit description of a
design using ProcessorPM-POWR605 device is provided in “3.2 N-Supply Supervisor, Reset Generator and Watchdog Timer” on page 3-10.)
ProcessorPM-POWR605
V#1 V#2 V#6
CPU_Reset
WDT_Int
Reset_in
WDT_Trig
VMON1 to
VMON6
IN1
IN2
IN_OUT1
IN_OUT2Power 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-3
2.2 Power Supply Sequencing Solutions Summary
Flexible N-Supply Sequencing
Features of Sequencer Implementation in a Power Manager II Device
• Programmable power up and power down sequencing
• Shutdown can be initiated through supply fault or an external input
• Allows user to change supply turn-on sequence or fine-tune sequence timing in software
• Supports multiple types of supply turn-on/off sequencing algorithms
• Closed loop sequencing / time-based open loop sequencing / complete sequencing within a given
period
• Integrates additional functions such as supervision reset generation, watchdog timer, hot-swap, trimming and margining
• Measures voltage and current through through I2
C
• Sequencing of supplies can be changed after assembly through in-system programming through JTAG.
(A detailed circuit description is provided in “4.2 Flexible N-Supply Sequencing Using Power Manager II II Devices” on page 4-3.)
Figure 2-2. Flexible N-Supply Sequencing Using the ispPAC-POWR1014A Device
Advantages of Integrating Sequencer into a Power Manager II Device
• Reduces cost by integrating the sequencing function along with other board power management functions
• Minimizes the risk of board re-spin due to change of sequencing algorithm – Can adjust sequencing
ADC
ispPAC-POWR1014A
En
V
OUT
POWER_GOOD
Shut_Down
N
OUT 3
OUT 4
OUT 10
OUT 11
OUT 12
SCL
SDA
IN1
IN 2
VMON 1 to
VMON N
Recycle Power
En
V
OUT
DC-DC /
LDO #1
DC-DC /
LDO #2
En
V
OUT
DC-DC /
LDO #N
Sequence_FailPower 2 You: A Guide to Power Supply Management and Control
2-4 Solutions Summary
algorithm after board assembly
• Reduces first prototype board bring-up time – By providing additional debug flags such as sequence
incomplete, supply turn-on timeout, etc.
• Increases board reliability by reducing the number of components – Does not require resistors or capacitors for timing or sequencing threshold adjustment
• Reduces the number of ICs required for power management, including sequencing, by meeting the
sequencing requirements of a wide variety of boards. (A detailed circuit description is provided in
“4.2 Flexible N-Supply Sequencing Using Power Manager II II Devices” on page 4-3.)
Sequencing with MOSFETs and DC-DC Enables
Features of Sequencer Implementation in a Power Manager II Device
• Integrates multiple charge pumps to control high-side N-Channel MOSFETs
• Has unified sequencing algorithm using MOSFETs and DC-DC converter enables
• Programmable power-up and power-down sequencing
• Shutdown can be initiated through supply fault or an external input
• Allows user to change supply turn-on sequence or fine-tune sequence timing in software
• Supports multiple types of supply turn-on/off sequencing algorithms:
• Closed loop sequencing / time-based open-loop sequencing / complete sequencing within a given
period
• Integrates additional functions such as supervision reset generation, watchdog timer, hot-swap, trimming and margining
• Sequencing of supplies can be changed after assembly through in-system programming via JTAG
• Measures voltage and current through I2
C. (A detailed circuit description is provided in
“4.3 Sequencing With MOSFETs and DC-DC Converter Enables” on page 4-9.)Power 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-5
Solutions Summary
Figure 2-3. The ispPAC-POWR1014A Implementing Sequencing with MOSFET and DC-DC Enables
Advantages of Integrating Sequencer into a Power Manager II Device
• Lowers cost by reducing the number of DC-DC converters as well as integrating sequencing function
along with other board power management functions
• Minimizes the risk of board re-spin due to change of sequencing algorithm – Adjust sequencing algorithm after board assembly
• Reduces board bring-up time by providing additional debug flags such as sequence incomplete and
supply turn-on timeout
• Increases board reliability by reducing the number of components – Does not require resistors or capacitors for timing or sequencing threshold adjustment
• Reduces the number of ICs required for power management, including sequencing by meeting the
sequencing requirements of a wide variety of boards. (A detailed circuit description is provided in
“4.3 Sequencing With MOSFETs and DC-DC Converter Enables” on page 4-9.)
VMON 5
VMON1 to
HVOUT 1
OUT 3
OUT 4
OUT 5
Device #1
Device #2
Device #1 Sequence
1. 1.2V
2. 1.8V
3. 3.3V
Device #2 Sequence
1. 3.3V
2. 2.5V
3. 1.2V
1.8V
En
2.5V
En
1.2V
En
Shut_Dn
ispPAC-POWR1014A
OUT 6
OUT 7
SCL
SDA
3.3V
ADC
Power Good
Failed
Q1Power 2 You: A Guide to Power Supply Management and Control
2-6 Solutions Summary
2.3 Hot-Swap Controllers
Hot-Swap Controller Using Soft-Start Mechanism
Features of Hot-Swap Controller Implementation in a Power Manager II Device
• Allows safe insertion into backplane – Programmable contact de-bounce delay
• Over-voltage protection and under-voltage lockout
• Controls inrush current through programmable soft-start rate feature
• Retry on fault with programmable retry period
• Backplane voltage status flag to secondary side
• Isolates board from backplane due to faults on board. Ramp time can be customized to meet board turnon power requirements.
• Backplane voltage range 3V to 5V
• Integrate other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining
• Measure backplane voltage in addition to other board voltages and currents through I2
C
• Management of supplies can be changed after assembly through in-system programming via JTAG
• Hot-swap controller can be programmed independently of other ICs on the board. (A detailed circuit
description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power
Manager II Devices” on page 5-2.)
Figure 2-4. Hot-Swap Control Implemented Through MOSFET Ramp Rate Control
Advantages of Integrating Hot-Swap Controller into a Power Manager II Device
• Lowers cost by integrating other board management functions and reducing the number of power management ICs
• Minimizes fault propagation to other boards in the system due to a fault on a circuit board
• Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary
side
Inp_5V
Soft_start
Backplane
Q1 5V Load
Start_5V_Load
Out_5V
VMON1
VMON2
HVOUT1
OUT3
ADC ispPAC-POWR1014A I
2
CPower 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-7
Solutions Summary
• Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II devices. (A detailed circuit description is provided in
“5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on
page 5-2.)
Hot-Swap Controller with Hysteretic Current Limit Mechanism
Features of Hot-Swap Controller Implementation in a Power Manager II Device
• Limits the backplane current to a value during a current inrush event, minimizing power supply dip on
the backplane
• Two programmable over-current limits: hot-swap event and board operation
• Programmable contact de-bounce delay
• Over-voltage, over-current protection and under-voltage lockout
• Short circuit protection response < 1s
• Programmable retry period
• Retry on hot-swap fault / secondary supply fault
• Early warning about the backplane voltage status to secondary side
• Isolates board from backplane due to faults on board
• Integrates other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining
• Measures backplane voltage in addition to other board voltages and currents through I2
C
• Management of supplies can be changed after assembly through in-system programming via JTAG
• Hot-swap controller can be programmed independently of other ICs on the board. (A detailed circuit
description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power
Manager II Devices” on page 5-2.)
Figure 2-5. Hot-Swap Controller with Hysteretic Current Limit
Inp_5V
Hyst_Ctrl
Q1
Out_5V
I_In
Rs
+3.3V
R1
R2
Short_Ckt
IN1
Backplane
5V Load
Start_5V_Load
ADC ispPAC-POWR1014A
SCL
SDA
VMON1
VMON2
VMON3
OUT3
HVOUT1
IN1
CSA
Q2Power 2 You: A Guide to Power Supply Management and Control
2-8 Solutions Summary
Advantages of Hot-Swap Controller Integrated into a Power Manager II Device
• Reduces board cost by integrating other secondary board power management functions into Power
Manager II
• Reduces board space taken up by the hot-swap controller by using a smaller hold-off capacitor
• Increases system reliability by reducing the peak current during the hot-swap event and during board
fault
• Minimizes fault propagation to other boards in the system due to a fault on a circuit board
• Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary
side
• Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II device. (A detailed circuit description is provided in
“5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on
page 5-2.)
12V/24V Hot-Swap Controller
Features of Hot-Swap Controller Integrated into a Power Manager II Device
• Wide operating voltage range – 6V to 24V
• Can be used across a wide range of board power – 10W to 200W
• Limit the backplane current to a value during current inrush event to meet the safe operating area
(SOA) specifications of a MOSFET
• Programmable inrush and operating over-current limits independently
• Programmable contact de-bounce delay
• Over-voltage, over-current protection and under-voltage lockout
• Short circuit protection response < 1s
• Programmable retry period
• Retry on hot-swap fault/ secondary supply fault
• Backplane fault early warning
• Isolates board from backplane due to faults on board
• Integrates other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining.
• Measures backplane voltage in addition to other board voltages and currents through I2
C
• Management of supplies can be changed after assembly through in-system programming via JTAG
• Hot-swap controller can be programmed independently of other ICs on the board. (A detailed circuit
description is provided in “5.2 Implementing a Positive Supply Hot-Swap Controller Using Power
Manager II Devices” on page 5-2.)Power 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-9
Solutions Summary
Figure 2-6. 12V/24V Hot-Swap Controller Using an ispPAC-POWR1014A Device
Advantages of Hot-Swap Controller Integrated Into a Power Manager II Device
• Reduces board cost by integrating other secondary board power management functions into Power
Manager II, lower cost MOSFET and smaller hold-off capacitor
• Reduces board space due to smaller hold-off capacitor
• Increases system reliability by reducing the peak current during the hot-swap event as during board
fault
• Minimizes fault propagation to other boards in the system due to a fault on a circuit board
• Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary
side
• Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II device. (A detailed circuit description is provided in
“5.2 Implementing a Positive Supply Hot-Swap Controller Using Power Manager II Devices” on
page 5-2.)
Negative Supply Hot-Swap Controller
Features of the Negative Supply Hot-Swap Controller Implementation
• Wide operating voltage range: -35V to -80V
• Supports wide range of board power: 10W to 200W
• Deterministic current level during hot-swap to meet the SOA specifications of a MOSFET
• Programmable inrush current limit
• Programmable over-current limit
• Short circuit protection response time < 1s
Inp_12V
Backplane
Q1
Out_12V
I_In
Rs
+3.3V
R1
R2
Short_Ckt
+3.3V
D1
Q2
D2
C2
C1
12V Load
Start_12V_Load
C_Pmp
S_Dn
Q3
Ch
VMON1
VMON2
VMON3
OUT3
HVOUT1
OUT4
ADC
ispPAC-POWR1014A
SCL
IN1 SDA
CSAPower 2 You: A Guide to Power Supply Management and Control
2-10 Solutions Summary
• Programmable contact de-bounce delay
• Over-voltage protection and under-voltage lockout
• Enables load after the hot-swap event, further minimizing inrush current
• Programmable retry period
• Control of hot-swap from the secondary side.
• Early fault warning to secondary side
• Immune to 100V glitches. (A detailed circuit description is provided in “5.3 Implementing a Negative
Supply Hot-Swap Controller” on page 5-13.)
Figure 2-7. Hot-Swap Controller Circuit Using an ispPAC-POWR607 Device
Advantages of Hot-Swap Controller Integrated into a Power Manager II Device
Increases system reliability by:
• Limiting inrush current to the programmed value
• Limiting current due to secondary side faults to the programmed value
• Reducing current glitches on the backplane
• Reducing power stress on the MOSFET
• Minimizes fault propagation through the system from a faulty card
• Reducing overall system cost
-48V
43k
3.3k
6V
3.3k
6V
.01µF
.05(RS)
Voltage
Regulator
ispPAC-POWR607
100k
100
HVOUT2
HVOUT1
VMON6
VMON5
VMON4
VMON3
VMON2
VMON1
GND
VCC
Vin_High
Vin_OK
VDS_2
VDS_1
Isense_2
Isense_1
Gate_Drive_2
Gate_Drive_1
Ch
IN/OUT3
Enable_Load
43k
IN2
Q2 Q3
VCC_607
GND_607
VCC_607
VCC_607
GND_607
IN/OUT4
Shut_Dn
R2 R1
-48V
Return
Load
STB120NFPower 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-11
Solutions Summary
• Reducing board space due to smaller hold-off capacitor
• Reducing the number of hot-swap controller types across multiple projects. (A detailed circuit description is provided in “5.3 Implementing a Negative Supply Hot-Swap Controller” on page 5-13.)
CompactPCI Board Management
Features of CompactPCI Board Management Controller Integrated into a Power Manager
II Device
• Hot-swap for 3.3V, 5V, ±12V (CompactPCI hot-swap and board controller)
• Can be used across a wide range of board power – 10W to 200W
• Programmable inrush current per individual rail
• Programmable contact de-bounce delay on all supply inputs
• Over-voltage, over-current protection and under-voltage lockout
• Short circuit protection response < 1s
• Programmable retry period – Retry on hot-swap fault / secondary supply fault
• Backplane fault early warning
• Isolates board from backplane due to faults on board
• Integrate other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining.
• Measures backplane voltages in addition to other board voltages and currents through I2
C
• Management of supplies can be changed after assembly through in-system programming via JTAG. (A
detailed circuit description is provided in “5.4 CompactPCI Board Management” on page 5-16.)Power 2 You: A Guide to Power Supply Management and Control
2-12 Solutions Summary
Figure 2-8. An ispPAC-POWR1220AT8 Device – Complete CompactPCI Board Management
Advantages of CompactPCI Board Management Integrated into a Power Manager II
Device
• Reduces board cost by integrating other secondary board power management functions into Power
Manager II, lower cost MOSFET and smaller hold-off capacitor
• Increases system reliability by reducing the peak current during the hot-swap event as well as during
board fault
• Minimizes fault propagation to other boards in the system due to a fault on a circuit board
• Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary
side
• Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II device. (A detailed circuit description is provided in “5.4 CompactPCI
Board Management” on page 5-16.)
CompactPCI Express Board Management
Advantages of CompactPCI Express Board Management
• Hot-swap for 3.3V, 5V, +12V (CompactPCI Express, VME system board controller)
• Can be used across a wide range of board power – 10W to 200W
• Programmable inrush current per individual rail
• Programmable contact de-bounce delay on all supply inputs
+12V
+5V
Q1
Q2
Ch
1.8V
POL
2.5V
POL
BRD_SEL#
PCI_RST_b
Brown_Out
CPU_RSTb
12V
1.8V
2.5V
5V
3.3V
I_Sens3V3
FETDRV3V3
V_Sens3V3
I_Sens5V
FETDRV5V
V_Sens5V
V_In_12V
FETDRV12V
V_Sens12V
En_1V8
En_2V5
SCL
SDA
ispPAC-POWR1220AT8
-12V
+3.3V
En_Neg12
Healthy#
-12V
+3.3V
CSA
CSA
Q3Power 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-13
Solutions Summary
• Over-voltage, over-current protection and under-voltage lockout
• Short circuit protection response < 1s
• Programmable retry period – Retry on hot-swap fault / secondary supply fault
• Backplane fault early warning
• Isolates board from backplane due to faults on board
• Integrates other board management functions such as sequencing, reset generation, supervision, watchdog timer, trimming and margining.
• Measures backplane voltages in addition to other board voltages and currents through I2
C
• Management of supplies can be changed after assembly through in-system programming via JTAG. (A
detailed circuit description is provided in “5.4 CompactPCI Board Management” on page 5-16.)
Figure 2-9. Complete CompactPCI Express Board Power Management
Advantages of CompactPCI Express Board Management Implementation
• Reduces board cost by integrating other secondary board power management functions into Power
Manager II, lower cost MOSFET and smaller hold-off capacitor
• Increases system reliability by reducing the peak current during the hot-swap event as well as during
board fault
• Minimizes fault propagation to other boards in the system due to a fault on a circuit board
• Increases shut-down reliability – Ensures safe board shutdown through early warning to the secondary
side
• Reduces the number of power management ICs – Integrates the remaining power management functions into the Power Manager II device. (A detailed circuit description is provided in “5.4 CompactPCI
Board Management” on page 5-16.)
+12V
+5V
+3.3V
Q5
Q1
Q2
D2
C2
C_Pmp
S_Dn
Q3
Ch
3.3V
ATNSW#
PRSNT#
PWREN#
PERST#
MPWRGD
12V
1.8V
2.5V
5V
3.3V
I_Sens3V3
FETDRV3V3
V_Sens3V3
I_Sens5V
FETDRV5V
V_Sens5V
V_In_12V
I_Sens12V
FETDRV12V
Sh
V_Sens12V
ut_Dn
En_1V8
En_2V5
SCL
SDA
CSA
CSA
1.8V
POL
2.5V
POL
Q4
CSA
ispPAC-POWR1220AT8Power 2 You: A Guide to Power Supply Management and Control
2-14 Solutions Summary
2.4 Redundant Supply Management
Two Rail 5V Power Supply OR’ing (Using MOSFETs)
Features of Power Manager II-Based Implementation
• Low power loss replacement for diode
• Uses N-Channel MOSFET
• Proactive reverse current protection
• Under-voltage and over-voltage protection
• Individual branch current and voltage measurement through I2
C
• Integrates other board management functions such as hot-swap, supply sequencing, voltage supervision, reset generation, watchdog timer, trimming and margining. (A detailed circuit description is provided in “6.3 +5v Power Supply OR’ing (Using MOSFETs) Circuit ” on page 6-3.)
Figure 2-10. An ispPAC-POWR1014A Device Implementing Two-Rail 5V OR’ing Control
Advantages of Integrating Power OR’ing Control into a Power Manager II Device
• Increases board reliability through proactive reverse current protection
Inp_5Vb
Hyst_Ctrl
Q2
5V_Hot-swap
Inp_5Va
I_Inb
Rs
R2
Q1
Rs
R1
5V_a
Start 5V_Hot-swap
CSA
A
VMON1
VMON2
VMON3
VMON4
HVOUT1
OUT3
SCL
SDA
ispPAC-POWR1014A
5V_b
I_Ina
ADC
CSA
B
HVOUT2Power 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-15
Solutions Summary
• Lowers power management cost through integrating multiple power management functions into a single device
• Reduces the number of ICs required to implement the Power OR’ing feature. (A detailed circuit
description is provided in “6.3 +5v Power Supply OR’ing (Using MOSFETs) Circuit ” on page 6-3.)
Power Supply OR’ing of N-Rails Using MOSFETS
Features of Power Manager II-Based Implementation
• Single Power Manager II chip implements OR’ing up to six channels
• Low power loss replacement for diode
• Uses N-Channel MOSFET
• Proactive reverse current protection
• Under-voltage and over-voltage protection
• Individual branch current and voltage measurement through I2
C
• Integrate other board management functions such as hot-swap, supply sequencing, voltage supervision,
reset generation, watchdog timer, trimming and margining. (A detailed circuit description is provided
in “6.4 Power Supply OR’ing of Three or More 5V Supply Rails Using MOSFETS” on page 6-5.)Power 2 You: A Guide to Power Supply Management and Control
2-16 Solutions Summary
Figure 2-11. N-Channel OR’ing through MOSFETS
Advantages of Integrating Power OR’ing Control into a Power Manager II Device
• Increases board reliability through proactive reverse current protection
• Lowers power management cost through integrating multiple power management functions into a single device
• Reduces number of ICs required to implement Power OR’ing feature. (A detailed circuit description is
provided in “6.4 Power Supply OR’ing of Three or More 5V Supply Rails Using MOSFETS” on
page 6-5.)
N-rail (12V/24V) OR’ing
Features of Power Manager II-Based Implementation
• Wide operating voltage range: 6V to 24V
• Single Power Manager II chip implements OR’ing up to six channels
• Low power loss replacement for diode
• Uses N-Channel MOSFET
Inp_5Vb
Qn
5V_Hot-Swap
Inp_5Va
I_Inn
Rs
Rn
Q1
Rs
R1
5V_a
Start 5V_Hot-Swap
CSA
a
VMON1
VMON2
VMON3
VMON4
HVOUT1
OUT3
SCL
SDA
ispPAC-POWR1014A
5V_n
I_Ina
ADC
CSA
nPower 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-17
Solutions Summary
• Proactive reverse current protection
• Under-voltage and over-voltage protection
• Individual branch current and voltage measurement through I2
C
• Integrates other board management functions such as hot-swap, supply sequencing, voltage supervision, reset generation, watchdog timer, trimming and margining. (A detailed circuit description is provided in “6.5 N-rail (12V/24V) OR’ing” on page 6-7.)
Figure 2-12. N- 12V Rail OR’ing Through MOSFET Using an ispPAC-POWR1014A Device
Advantages of Integrating Power OR’ing Control into a Power Manager II Device
• Increases board reliability through proactive reverse current protection
• Lowers power management cost through integrating multiple power management functions into a single device
• Reduces number of ICs required to implement the Power OR’ing feature. (A detailed circuit description is provided in “6.5 N-rail (12V/24V) OR’ing” on page 6-7.)
-48V Supply OR’ing Through MOSFETS
Features of Power Manager II-Based Implementation
Inp_12Vb
Qn
12V_Hot-Swap
Inp_12Va
I_Inn
Rs
Rn
Q1
Rs
R1
12V_a
Start 12V_Hot-Swap
CSA
a
VMON1
VMON2
VMON3
VMON4
HVOUT1
OUT4
SCL
SDA
ispPAC-POWR1014A
12V_n
I_Ina
ADC
CSA
n
OUT3
OUT5Power 2 You: A Guide to Power Supply Management and Control
2-18 Solutions Summary
• Wide operating voltage range: -30V to -80V
• Low power loss replacement for diode
• Uses N-Channel MOSFET
• Hot-swappable
• Proactive reverse current protection
• Under-voltage and over-voltage protection
• Fuse fault detection
• Controls hot-swap controller. (A detailed circuit description is provided in “6.6 -48V Supply OR’ing
Through MOSFETS” on page 6-10.)
Figure 2-13. Dual -48V MOSFET OR’ing Circuit Using an ispPAC-POWR607 Device
Advantages of Integrating Power OR’ing Control into a Power Manager II Device
• Increases board reliability through proactive reverse current protection
• Lowers power management cost through integrating power OR’ing along with voltage monitoring and
contact de-bouncing
• Reduces number of ICs required to implement the Power OR’ing feature. (A detailed circuit description
is provided in “6.6 -48V Supply OR’ing Through MOSFETS” on page 6-10.)
-48VA
-48VB
10K
10K
A_Hi
B_Hi
A_On
B_On
Start_HS
Q1
Q2
R1
R2
R3
R4
To Hot-swap
Controller
BRD -48V
HVOUT2
GND
HVOUT1
VMON6
VMON5
OUT5
ispPACPOWR607
3K 3KPower 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-19
2.5 Power Feed Controllers Solutions Summary
Dual Rail -48V Power Feed Controller
Features of Power Manager II-Based Implementation
• Wide operating voltage range: -30V to -80V
• Safe MOSFETs operation (SOA)
• Individual channel current limiting
• Individual channel short circuit protection - < 1s response time
• No-current and over-current flags per output branch
• Individual channel enables
• Retry upon fault detection
• Filters out short period over-current glitches. (A detailed circuit description is provided in “7.2 Dual
Rail -48V Supply Feed” on page 7-1.)
Figure 2-14. An ispPAC-POWR607 Implements a Two-Channel -48V Power Feed Circuit
Advantages of Integrating 2-Channel -48V Power Feed into a Power Manager II
• Lowers cost by integrating two-channel power feed into a single chip
• Increases board reliability through current limiting and short circuit protection on a per-channel basis
• Reduces the number of ICs by being able to be customized across a wide range of power feed and protection requirements. (A detailed circuit description is provided in “7.2 Dual Rail -48V Supply Feed”
on page 7-1.)
SC_2
Fault_1
R1 R2
R3
R4
Rs1
Rs2
Q2
N1
N2
100K
100K
VMON 1
VMON 2
HVOUT1
VMON 3
VMON 4
HVOUT2
OUT3
OUT4
-48V_1
-48V_2
Fault_2
OUT6
OUT5
OC_SCb
OUT7
ispPAC-POWR607
-48V_IN
SC_1
GND
-48V_Rtn
3V3 Reg
Vcc
SC_2
SC_1
En_2
En_1
VMON 6
VMON 5
IN1
IN2
N3
N4
Q1Power 2 You: A Guide to Power Supply Management and Control
2-20 Solutions Summary
Three-Channels of a 6V-24V Power Feed System
Features of Power Manager II-Based implementation
• Wide operating voltage range: 6V to 24V
• Expandable up to four channels of power feed control
• Safe MOSFET operation (SOA)
• Individual channel current limiting
• Individual channel short circuit protection - < 1s response time
• No-current and over-current flags per output branch
• Individual channel enables
• Retry upon fault detection
• Filters out short period over-current glitches
• Individual channel current and voltage measurement through I2
C
• Integrates other board power management functions. (A detailed circuit description is provided in
“7.3 Three Channels of a +12V Power Feed System” on page 7-4.)
Figure 2-15. Three-Channel 12V Power Feed Circuit
Advantages of Integrating Multiple Channel Power Feed into a Power Manager II Device
• Reduces cost of implementation by reducing the number of ICs required for the entire power feed circuit
• Reduced number of power feed ICs – Customizable to meet power feed characteristics across a wide
variety of applications
Inp_12VIn
Rs3 Q3
Rs2 Q2
12V_In
Rs1 Q1
2
12V#1
12V#2
12V#3
CPOUT
I_12V_1,
Out_12V_1
SC_1
SC_2
SC_3
EN_1
EN_2
EN_3
SC_1,2,3
Fault_1, Fault_2, Fault_3
ADC
ispPAC-POWR1014A
VMON1
VMON2,3
VMON4,5
SCL
OUT3,4
HVOUT1
SDA
VMON6,8
OUT5,6
OUT7,8
VMON9
VMON10
IN1
IN2,3,4 OUT9,10,11
2
2
2
2
2Power 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-21
Solutions Summary
• Increased reliability of the board by integrating other board management functions such as sequencing,
reset generation, etc. (A detailed circuit description is provided in “7.3 Three Channels of a +12V
Power Feed System” on page 7-4.)
Two-Channel +12V & 3.3V Power Feed With Diode OR’ing
Features of the Power Feed Solution Integrated into Power Manager II
• Designed for use in MicroTCA Power Module – Two channels
• Feeds 3.3V and 12V with OR’ing support using MOSFET
• Turns off 12V power feed within 50s of AMC card extraction
• Programmable over-current protection
• MOSFET operates in safe operating area
• Supports OR’ing of payload power supply rails (+12V)
• Proactive reverse current protection
• Measures voltage and current through I2
C
• Monitors input 12V supply for over- and under-voltage conditions
• Expand up to four channels of power feed as well as trimming of 12V supply for power supply OR’ing
function. (A detailed circuit description is provided in “7.4 2-Channel +12V & 3.3V Power Feed With
MOSFET OR’ing” on page 7-8.)Power 2 You: A Guide to Power Supply Management and Control
2-22 Solutions Summary
Figure 2-16. One-Channel uTCA Power Feed Using Half of an ispPAC-POWR104A Device
Advantages of Two-Channel MicroTCA Power Feed Circuit Using a Power
Manager Device:
• Lowers cost of implementation
• Increased reliability through high precision voltage monitoring
• Integrates more channels of power feed circuitry along with trimming features. (A detailed circuit
description is provided in “7.4 2-Channel +12V & 3.3V Power Feed With MOSFET OR’ing” on
page 7-8.)
EMMC Alert
VMON
Open Drain
Digital Out
HVOUT1
OUT
VMON
OUT
EMMC Primary/
Redundant
Enable#
Payload On
Mgmt Power
Control
Current
Sensing
Pass
Device
OR’ing
Device
Q1 Q2
12V Payload
Power
to Load
100 100
4.7M
P1
4.7M 0.001µF
C2
MMBT
2222A
N1
47
D2 P2
0.01µF
C1
2.2K
Quick Shutoff
Output Monitor
Half of
ispPACPOWR1014A
OR-FET
Control
MMBT
2222A N2 Q3
3.3V Power
to Load
D1
Open Drain
Digital Out
Vcc
12V
3.3V
+
_
47M
3K
N3
6V 1K
MMBT2907
Primary
Power
SourcePower 2 You: A Guide to Power Supply Management and Control
Solutions Summary 2-23
2.6 Trimming and Margining Solutions Summary
(A detailed circuit description is provided in “8.4 Trimming and Margining – Principle of Operation” on
page 8-3.)
Features of Closed Loop Trimming and Margining Implemented in a Power Manager II
Device
• Ideally suited for trimming any low voltage (<1.2V) and high current analog DC-DC converter
• Output voltage accuracy = Set pin voltage ±10mV
• Single chip supports up to eight channels of trimming and margining
• Voltage margining support
• Differential voltage sensing
• Voltage scaling
• VID support through simple PLD
• Integrates trimming and margining along with voltage supervision, sequencing, reset generation and
hot-swap controller functions.
Figure 2-17. Low Cost Trimming and Margining Solution Using Power Manager II
Advantages of Implementing Trimming and Margining Using a Power Manager II Device
• Lowers cost of a DC-DC converter - No need for Digital DC-DC converter to support margining and
trimming
• Increases functional reliability through DC-DC converter precision output voltage control
• Reduces operating power through voltage scaling
• Reduces debug time by automated margining tests
PWM
Controller
Inductor &
Filters Switcher
Feedback
Any DC-DC Converter
ispPAC-POWR1220AT8/
ispPAC-POWR6AT6
Load
Differential Voltage Sense
I
2
C
2
Result: Voltage Error <1% At Load! (-40° to +85° C)
Set Point
+/-1
VIN
DAC
ADCPower 2 You: A Guide to Power Supply Management and Control
2-24 Solutions Summary
This page intentionally left blank.CHAPTER
3
3-1
Reset Generators & Supervisors
3.1 Introduction
One of the most important peripheral ICs required for a microprocessor is a reset generator and
a watchdog timer.
The functions of a reset generator are:
1. Hold the processor in a reset condition for an extended period of time during a power turn-on
event.
2. If any supply is faulty, activate the reset to prevent it from mis-executing instructions and/or
risk Flash memory corruption.
The functions of a watchdog timer are:
1. A monitor for software execution using the trigger generated by the software.
2. If the processor skips a trigger, activate an interrupt or reset the CPU to initiate a recovery
process.
Traditional reset generators monitor just one input supply to generate the reset signal. However, most modern processors operate using many supplies, as shown in Figure 3-1. Because a
fault on any of the supplies could result in the processor mis-executing instructions, reset generators that monitor only one supply are not adequate. Instead, reset generators are required
that monitor all the relevant supplies for faults in order to generate the CPU reset. Figure 3-1
illustrates this. In the example shown it is not clear which of the five supplies should be chosen
for reset.Power 2 You: A Guide to Power Supply Management and Control
3-2 Reset Generators & Supervisors
Figure 3-1. Single Rail Reset Generator Cannot Guarantee Reliable Reset Generation
In Figure 3-1, the processor requires 1.2V for its core, 1.8V and 0.9V for communicating with DDRII
memory and 3.3V for communicating with Flash memory and other peripherals. The processor operates
reliably only if all of its supply rails are within the datasheet-specified voltage limits; for example, the
acceptable tolerance for: 3.3V (±5%), 1.8V (±5%), 1.2V (±3%), and 0.9V (±5%). One common behavior
of a microprocessor when operating at a core voltage less than its specified low voltage level is the misinterpretation of instructions. When the instructions are misinterpreted (also called mis-executed), the program execution becomes unpredictable and the program can hang (not perform the intended task).
If the I/O voltage drops below the specified signaling threshold level, the instruction/data transferred
between the memory and the processor can be corrupted.
The misinterpretation of instructions, or proper execution of corrupted instructions, by a microprocessor
results in unpredictable behavior; in some cases, the microprocessor could overwrite the on-board Flash
memory, resulting in a failed circuit board. Imagine the circuit board failing just because it was extracted
from its sub-rack slot!
Unpredictable behavior under low voltage conditions is limited not only to microprocessors, but is also
true for any ASIC / FPGA on the board. For example, if the power supply voltage drops below the limit
for a networking ASIC, it might send a garbled packet. In some cases it might lose an internally buffered
acknowledged packet, resulting in a corrupt message.
Reliable Reset Generation by Monitoring All Supply Rails
To prevent the processor from operating when any of its supplies is faulty, one has to monitor all supplies.
Monitoring all the supplies for faults is known as supply supervision. Supervisor ICs are used to monitor
multiple supplies simultaneously. The following functions are typically performed by one or multiple
supervisor ICs:
1. Accurately monitor multiple supply rails for faults and quickly generate an interrupt
2. If the processor core or memory supplies fail, reset the processor
V = ?
3.3V 1.8V 1.2V 0.9V
Reset CPU
TMS320C6XXX DDR
1.8V 0.9V
Flash Memory
Reset ICReset Generators & Supervisors 3-3
Power 2 You: A Guide to Power Supply Management and Control
Reset Generators & Supervisors
Voltage Supervision Reliability Is Determined By the Supervisor IC’s Fault Detection Accuracy As
Well As Its Fault Detection Speed
Figure 3-2 shows the ProcessorPM-POWR605 supervisor and reset IC (replacing the reset IC in
Figure 3-1) to monitor all supplies on the circuit board and prevent Flash corruption due to supply faults.
Figure 3-2. The Most Reliable Reset Generator ICs Monitor All Supplies (Supervisor IC)
Parts of a Supervisor IC
Figure 3-3 shows a simple, single supply, voltage monitoring circuit.
Figure 3-3. Single Power Supply Voltage Monitoring Circuit
This circuit uses a voltage comparator to monitor the supply voltage. One limb of the comparator is held
at a constant reference voltage through the bandgap voltage reference. The monitored power supply voltage is attenuated using a resistor network such that the attenuated voltage is greater than the bandgap reference voltage as long as the supply voltage is above the fault level.
For example, the bandgap voltage is 2V, and the power supply should be monitored for 3.3V - 5%
(= 3.135V). The attenuator is selected such that the output of the attenuator is greater than 2V as long as
the monitored supply voltage is greater than 3.135V. The comparator output toggles when the monitored
voltage drops below 3.135V. reset generators, supervisors and voltage detectors use circuits similar to the
one shown in Figure 3-3.
Figure 3-4 shows the architecture of a device to monitor multiple power supply voltages. These devices
contain multiple comparators with individual attenuators to facilitate the simultaneous monitoring of dif-
3.3V 1.8V 1.2V 0.9V
Reset CPU
TMS320C6XXX DDR II / DDRIII
1.8V 0.9V
ProcessorPMPOWR605
(Supervisor +
Reset Generator)
Voltage
Comparator
Band-gap
Reference
Voltage
Monitored
Supply
Voltage
Logic Output
Interrupt/ Reset
Signal
AttenuatorPower 2 You: A Guide to Power Supply Management and Control
3-4 Reset Generators & Supervisors
ferent power supply voltages. The outputs of these comparators are logically combined to provide a single logic output to interrupt or reset the processor.
Figure 3-4. Block Diagram of a Three Power Supply Supervisor IC
Effect of Monitoring Accuracy on System Functionality
In the circuit shown in Figure 3-3, suppose we use an ideal bandgap reference source (output voltage is
always 2V), ideal attenuator (its output voltage is exactly 2V when the input voltage is 3.135V), and an
ideal comparator: then, the output of the comparator always toggles exactly when the monitored voltage
is 3.135V. But in reality, the bandgap reference voltage changes with temperature, the output voltage of
the attenuator varies from device to device and there are inaccuracies with the comparator. All these
result in a slight variation of the threshold voltages for each device and across temperature and voltage.
The accuracy of a supervisor is a measure of the variation of threshold with respect to the intended
threshold.
Many off-the-shelf supervisory ICs detect power faults with an accuracy of ±2%. This means that the
actual threshold can vary by as much as 2% of the threshold value across voltage and temperature, and
from device to device. Let’s examine the effect of this accuracy on system functionality and fault detection threshold selection.
Refer to Figure 3-5. If the device is specified at a threshold of 3.3V - 5% (3.135V) with a 2% accuracy,
that device can declare the power supply as faulty anywhere between 3.135 + 2% and 3.135 - 2% (3.2V to
3.072V), shown by points A and B.
Voltage
Comparator
Band-gap
Reference
Voltage
Logic Output
Interrupt/ Reset
Signal
Attenuator
Voltage
Comparator
Attenuator
Voltage
Comparator
Monitored
Supply
Voltage #1
Attenuator
Monitored Logic Supply
Voltage #2
Monitored
Supply
Voltage #3Reset Generators & Supervisors 3-5
Power 2 You: A Guide to Power Supply Management and Control
Reset Generators & Supervisors
Figure 3-5. Fault Detection with Supervisor Accuracy Of 2%
As can be seen, the supervisor can sometimes declare the power supply faulty when it is healthy, or
declare it healthy when it is faulty. The latter is a more serious error, because at lower than the desired
threshold voltage the processor can be mis-executing instructions, which defeats the purpose of using a
supervisor IC.
To avoid such problems, the supervisor threshold should be set such that the entire power supply fault
detect range lies within the operating voltage range of the processor. In this case, if the supervisor threshold is set at 3.2V, then the voltage range in which the supervisor can declare the power supply faulty is
between 3.14V to 3.26V, thus avoiding the condition under which the processor is operating at a voltage
less than its threshold (3.3V - 5%).
Figure 3-6. Fault Detection with Supervisor with Correct Threshold
In the example shown in Figure 3-6, the threshold value of the supervisor was set at 3.2V. The 3.2V
threshold value was actually calculated using the following equation:
Where VTSup - Supervisor Threshold
Vin - Power Supply Nominal Voltage
VinTol - Input Power Supply Tolerance
VTSup = Vin * (1-VinTol/100)/ (1-Asup/100)
3.3v - 5%
Processor Lower
Voltage Threshold
&
Supervisor Threshold
{
A
B
Supervisor Fault
Defect Range
3.3V – 5% = 3.14V
A = 3.2V, B = 3.07V
Typical Power Supply Voltage
3.3V
Typical Power Supply Voltage
3.3V
A
B
{
Supervisor Fault
Defect Range
Supervisor Threshold
= 3.2V
Processor Lower
Voltage Threshold
Power Supply
Tolerance
Headroom - 1.1%
3.3V – 5% = 3.14V
A = 3.26V, B = 3.14V
{
3.3V – 5%Power 2 You: A Guide to Power Supply Management and Control
3-6 Reset Generators & Supervisors
Asup - Accuracy of the Supervisor
In this example, Vin at 3.3V, VinTol - 5%, Asup - 2%. Substituting these values into the equation above,
VTSup = 3.3 * (1 - (5/100)) / (1 - (2/100)) = 3.2V.
By selecting the Supervisor IC with the threshold at 3.2V or above, the processor is guaranteed to be held
in reset when the power supply voltage is less than or equal to 3.3V - 5%.
Reduced Accuracy Results in Reducing the Power Supply Tolerance
Headroom
Power supply tolerance headroom is the maximum voltage swing allowed for the power supply, across
load and operating temperatures, before being declared faulty as shown in Figure 3-6.
Consider the power supply headroom while using a supervisor IC with an accuracy of 2%. According to
Figure 3-6, the power supply voltage variation should be higher than 3.26V (the highest voltage at which
the supervisor would declare the supply faulty) all the time, or a power supply head room of 1.1%! Typically, power supplies have an output tolerance of about 3% across load and temperature, or the power
supply voltage can swing from 3.2V to 3.4V. Clearly the choice for the user is either to use a more expensive supply with a power supply voltage variation of 1%, or use a supervisor with better accuracy.
Using a Supervisor IC With an Accuracy Of 1%
From the equation for the same system described above, but using an error of 1%, the supervisor selected
should have a threshold of 3.17V. The upper limit of the fault detect range is 3.19V and is still less than
the lowest output voltage of the power supply, -3.2V, and a power supply with a voltage variation of 3%
can be used.
The board can be operated reliably with a lower cost power supply with larger output voltage tolerance by
using a more accurate supervisor. The ispPAC-POWR1220AT8 device offers an accuracy of 0.2% (typical) and 0.7% (maximum).
Effects of Fault Detection Delay
Fault detection delay is the duration from the time the power supply voltage drops below the threshold of
the supervisor (with very high accuracy), to the time the output of the supervisor toggles, indicating the
fault.Reset Generators & Supervisors 3-7
Power 2 You: A Guide to Power Supply Management and Control
Reset Generators & Supervisors
Figure 3-7. Effect of Fault Detection Delay On Board Operation
In Figure 3-7, the 3.3V supply starts to fail. The power supply supervisor detects the power supply failure
and signals the processor. As can be seen from Figure 3-7, the longer the supervisor takes to report the
fault, the lower will be the power supply voltage.
For example, the power supply voltage is decaying at a rate of 1V per millisecond. The supervisor precision is very high, which allows the effects of the accuracy described above to be ignored and is set at the
threshold of 3.3V - 5%. Let us examine two cases: Fault detection delay is 1ms and 50s.
If the Fault Detection Delay is 1ms:
Because the power supply output voltage continues to drop, by the time the processor is reset its power
supply voltage would be much less than the low voltage threshold (about 2V), which means that the processor was executing code until the supply reached 2V! Most likely the processor was mis-executing
instructions or locked up. The purpose of the supervisor IC is defeated.
If the Fault Detection Delay is 50µs:
By the time the supervisor output is active, the processor voltage would have been reduced by about
50mV from its threshold of 3.3V-5%. Again, the processor operation is not guaranteed at this voltage.
Now, if the threshold was set 50mV above the 3.3V-5% level, the processor would be reset by the time
the power supply crossed the operational threshold.
As can be seen, in this application the fault detection delay of 1ms is unacceptable. But a fault detection
delay of about 50s requires the threshold to be set 50mV above the minimum operating power supply
voltage threshold.
The supervisor threshold for reliable operation should consider both the accuracy as well as the fault
detection delay. Many applications use over-voltage monitoring; that is, if the power supply voltage
reaches above the operating voltage range, either the faulty power supply itself is turned off, or a “crowbar” mechanism is turned on by shorting that power supply output voltage to ground, protecting the
devices on the circuit board. Speed of over-voltage detection, in this case, is even more important than the
under-voltage fault detection.
Supervisor
Output
3.3V – 5%
?
3.3V
Fault
Detection
DelayPower 2 You: A Guide to Power Supply Management and Control
3-8 Reset Generators & Supervisors
The previous example considered only one power supply voltage and used a very accurate supervisor IC.
In reality, the number of power supplies that the supervisor should monitor is more than one. The supervisor should be able to monitor all supplies simultaneously for fault and should be able to detect power supply faults with minimum fault detection delay.
Fault detection delay of 1ms or higher is typically seen in circuits that use a microcontroller to monitor
voltages using their on-chip ADC.
Supervisors Built Using ADC and a Microcontroller are Slow
Some applications use a microcontroller to monitor all the power supplies using an on-chip Analog to
Digital Converter and an analog multiplexer. The monitoring algorithm, which typically is initiated by an
interrupt once every 5 or 10ms, digitizes each power supply voltage, one supply at a time in a round robin
format. The ADC sample is compared with the internally stored threshold. If the ADC read value is lower
than the threshold, an output port pin (reset or interrupt pin) is toggled to indicate the power supply fault.
Because the voltage monitoring algorithm is activated by the real time interrupt, the speed of fault detection is also determined by the delay between interrupts (5ms to 10ms). This is too slow for power supply
fault detection. The only perceived advantage of a microcontroller is that it offers a flexible interface that
lets designers change the power management algorithm after the board is assembled. However, designers
typically avoid changing the microcontroller code. Because there are no software simulators available,
any change in the code requires extensive circuit board testing. Consequently, the perceived advantage of
flexibility is not real.
In order to meet the reliability needs, which include supply fault detection accuracy as well as speed of
fault detection, it is advisable to use hardware supervisors instead of microcontrollers. To meet the flexibility needs, the Lattice Power Manager II devices offer programmable analog and programmable digital
functions, while providing superior accuracy and fault detection speed. For example, the ispPACPOWR1220AT8 device monitors 12 power supplies simultaneously and has a fault detection delay of
16s.
Other Factors Contributing to Increased Reliability
The other factors to be considered for reliable power supply fault detection are:
Glitch filter – Power supplies are usually fairly noisy during the circuit board operation. The noise can
be due to power supply output ripple or to transient currents in the system due to device operation, etc.
This noise can result in a randomly toggling supervisor output. To prevent this, supervisors have a glitch
filter that generates a clean input to the threshold comparators. Power Manager II devices support a 64s
glitch filter for each input.
Hysteresis – A small amount of hysteresis is added to the threshold comparators to prevent the outputs
from toggling multiple times, due to power supply noise, when the power supply voltage is at its threshold. In Power Manager II devices, the hysteresis is set to 1% of the threshold voltage. The hysteresis does
not affect the accuracy of the threshold because the hysteresis transition requirement is applied after the
voltage crosses the threshold.
Differential Voltage Sensing on a Circuit Board – When monitoring voltage levels of 1.2V and below,
one has to use differential voltage sensing to meet the fault detection accuracy needs of the circuit board.Reset Generators & Supervisors 3-9
Power 2 You: A Guide to Power Supply Management and Control
Reset Generators & Supervisors
Figure 3-8. Ground Voltage Difference Adds Error at Supervisor Input
Figure 3-9. Ground Voltage Difference Error Nullified by Differential Sensing
Newer fabrication processes with smaller transistor geometries stipulate reduced core supply voltage and
range such as 1V with a ±50 mV range. If these voltage rails are monitored from a central location, one
should consider the ground voltage difference between the monitored node and the supervisor IC. For
example, in Figure 3-8, if the ground voltage difference between the CPU and the voltage monitoring
device using a single ended sensing method is about 20mV, and if the actual voltage as seen by the CPU
is 30mV, the supervisor IC sees a 30mV + 20mV = 50mV rise from the target value, which is a fault, and
interrupts the processor or holds the processor in reset even when it could operate.
If the ground voltage difference between the supervisor IC and the CPU is -20mV, the monitor IC does
not see a fault even when the supply voltage is lower than its minimum operating threshold level. This
results in an unreliable fault detection circuitry.
Circuit Board
Difference
Between Ground
Potentials = V
GG
1.2V CPU
Core
Supply
CPU
1.2V CPU
Core
Supply
Single Ended
Sensing
Supervisor IC
Sensed Voltage
= VCPU – VGG
V
CPU
Circuit Board
Difference
Between Ground
Potentials = V
GG
1.2V CPU
Core
Supply
CPU
1.2V CPU
Core
Supply
Differential
Sensing
Supervisor IC
Sensed Voltage
= VCPU
V
CPU
+
-
Differential Sensing
Cancels Error Due
to V
GGPower 2 You: A Guide to Power Supply Management and Control
3-10 Reset Generators & Supervisors
The safest solution is to use differential voltage sensing (Figure 3-9). Here the ground voltage difference
between the CPU and supervisor IC becomes a common mode voltage at the supervisor and its input difference amplifier cancels the common mode voltage before feeding it to the comparator.
Ensuring Deterministic Behavior Under Fault Conditions Through Simulation – The response of a
circuit board depends on the power supply failure. As a result, the supervisor is expected to perform different functions depending on the supply that failed. For example, if the core voltage of a CPU failed, the
supervisor has to activate the reset signal and start the board power shutdown. However, if one of the
redundant supplies failed, the supervisor has to interrupt the processor. To guarantee functional reliability,
one should ensure that the design implemented in the Supervisor IC responds to the supply faults correctly. The easiest method is to simulate the design with different types of faults using software, rather
than conduct the hardware regression tests.
3.2 N-Supply Supervisor, Reset Generator and Watchdog
Timer
The ProcessorPM-POWR605 device provides six precision programmable threshold comparators, five
I/Os, two digital inputs, four programmable timers and a 16-macrocell CPLD. This device is used to integrate the supervisor, the reset generator and a watchdog timer function. The ProcessorPM-POWR605
devices monitor supply rails with an accuracy of 0.7% and can identify faults within 12s.
Figure 3-10. ProcessorPM-POWR605 Integrating Six-Supply Supervisor, Reset Genenerator
& Watchdog TimerT
Circuit Operation
The ProcessorPM-POWR605 in the circuit diagram in Figure 3-10 monitors six supplies directly by configuring each of the monitoring comparator inputs to the fault threshold. Two digital outputs of the ProcessorPM-POWR605 device are configured as CPU_reset and WDT_Int. The CPU_Reset signal
supports programmable pulse stretching up to 2 seconds. For example, if the programmable delay is set to
200ms, the CPU_Reset signal will remain active for a period of 200ms after all supplies are above their
respective threshold levels. The CPU_Reset signal also gets activated if any of the supplies drops below
their respective threshold levels. The WDT_Int signal is activated if the WDT_Trig input is not toggled
before the watchdog timer expires. The watchdog timer delay can be programmed from 32s to 2.5 minutes. The reset_in input is used to activate the CPU_Reset signal from an external input such as a manual
reset input signal.
ProcessorPM-POWR605
V#1 V#2 V#6
CPU_Reset
WDT_Int
Reset_in
WDT_Trig
VMON1 to
VMON6
IN1
IN2
IN_OUT1
IN_OUT2Reset Generators & Supervisors 3-11
Power 2 You: A Guide to Power Supply Management and Control
Reset Generator, Supervisor and Watchdog Timer Algorithm Reset Generators & Supervisors
1. Activate Reset signal, deactivate WDT_Int signals and wait for all supply levels to reach a value above
their respective thresholds.
2. Wait for 200ms (time delay programmable).
3. Release Reset.
4. Wait for any supply to fail. If any supply fails, activate the reset signal and jump to step 1.
Parallel Equations of the Algorithm
1. Timer equation waits for WDT trig. If the negative edge of the WDT_Trig signal is not received before
the timer expires, activate WDT_Int signal.
2. If Reset_In signal is activated and remains active beyond the 50ms (programmable) de-bounce period,
activate the CPU_Reset signal.
Programmable Features
• The monitoring threshold for each of the 6 supplies can be individually set to monitor any supply voltage rail from 0.67V to 5.8V.
• Reset pulse stretch duration can be programmed from 32s to 2 seconds.
• Watchdog timer delay – Watchdog timer delay can be set from 32s to hours.
• The input reset switch de-bounce delay can be programmed from 32s to 2 seconds.
Additional Features That Can be Added to ProcessorPM-POWR605
• Three of the remaining I/O pins can be used to implement other input monitor features such as warm
reset input, software reset input, FPGA Done, etc., or output control features such as DC-DC enables
for sequencing, reset distribution to three other devices at different time intervals, etc.
• Over-voltage protection – any of the comparator thresholds can be set to monitor for over-voltage. This
configuration can be used to provide over-voltage protection.
Relevant Power Manager II ICs
Devices such as the ispPAC-POWR1014/A can be used to monitor up to 10 rails. These devices support
dual programmable threshold comparators for each of the inputs that enables them to monitor for both
over and under-voltages at the same time. The ispPAC-POWR1220AT8 device can be used to monitor up
to 12 rails. These devices also support differential sense inputs that can be used to monitor lower voltage
supply rails on a larger board more accurately.Power 2 You: A Guide to Power Supply Management and Control
3-12 Reset Generators & Supervisors
This page intentionally left blank.CHAPTER
4
4-1
Power Supply Sequencing
4.1 Introduction
The number of power supplies (DC-DC Converters, LDOs, Voltage References) in a circuit
board is determined by the number of multi-voltage devices used in its payload section. These
devices also determine power supply sequencing. Power supply sequencing indicates that all
supplies on the board should not be turned on arbitrarily at any time, but instead should be
turned on or off in a prescribed sequence.
For example, on a circuit board a device with 3 supplies of 3.3V, 1.8V and 1.2V, usually the
lowest voltage rail should be turned on first, followed by the larger voltages. The turn on
sequence is 1.2V, 1.8V and finally 3.3V. Turning these supplies on in this sequence can be
implemented easily by connecting the power good signal from the 1.2V supply to the enable
signal of the 1.8V supply, and finally connecting the 1.8V power good signal to the enable signal of the 3.3V supply. However, when there are multiple devices, each with its own sequencing requirements, the logic required for sequencing can become complex.
Sequencing Power Supplies with Conflicting Sequencing
Requirements
What if there is a second device on that same board with supplies of 3.3V, 2.5V and 1.2V, but
the supplies must be turned on starting with the highest voltage? This is further complicated by
the fact that 3.3V is the main input supply. Now the designer is required to implement sequencing using the fewest possible supplies.
In such cases, MOSFETs are used to gate the supplies that conflict with conventional sequencing. The circuit in Figure 4-1 shows one such arrangement.Power 2 You: A Guide to Power Supply Management and Control
4-2 Power Supply Sequencing
Figure 4-1. Sequencing Supplies to Meet Conflicting Sequencing Requirements
This circuit uses the 3.3V supply to generate the remaining supply rails on the board. Because Device 1
requires 3.3V last and Device 2 requires 3.3V first, the 3.3V is applied to Device 2 with the remaining
supplies. Then, the power sequencer enables 2.5V, followed by 1.2V, completing the powering up of
Device 2. Next, because the 1.2V for Device 1 is already on, the power sequencer turns on the 1.8V, followed by the 3.3V that is enabled through the MOSFET.
One could have implemented this sequencing by using one more 3.3V supply and turning it on only when
Device 1 needed it. However, that would increase the board cost. Adding a second multi-voltage device
with its own sequencing requirements can make the sequencing more complex.
There are other factors that contribute to increased supply sequencing complexity.
Other Factors Adding Complexity to Sequencing Algorithm
Number of Board-Mounted Supplies is Increasing
Modern circuit boards use several multi-voltage ICs such as ASICs, CPUs, memories, and FPGAs. Due
to the high level of integration, fabrication processes and support for multiple interface standards, each of
these devices can require three to five power supplies. Furthermore, some of these devices require a nonstandard, low voltage core supply. So, it is not uncommon for boards to require five to ten supplies!
Sequencing the power supplies to meet the needs of each of the devices can be quite complex.
Abort Sequencing if Any Supply Fails During Power-Up
Supplies usually fail when they are turning on, leaving some of the devices partially powered. Often
some of these devices can only withstand the partially powered condition for a limited time. To mitigate
such conditions, the sequencer is required to abort supply sequencing when any supply fails to turn on
within a given period. In this case, the sequencer is required to monitor supplies and monitor time during
the supply sequencing.
1.8V
2.5V
1.2V
3.3V
Device #1
Device #2
En
En
En
Power Sequencer
Device #1 Sequence
1. 1.2V
2. 1.8V
3. 3.3V
Device #2 Sequence
1. 3.3V
2. 2.5V
3. 1.2VPower 2 You: A Guide to Power Supply Management and Control
Power Supply Sequencing
Power Supply Sequencing 4-3
Power-Down Sequencing
Some devices require the power supplies to be turned off in the reverse order of the turn on sequence to
prevent undesirable side effects, such as excessive current consumption on one of the rails that can damage the circuitry. Removing power to all DC-DC converters at the same time may not guarantee safe shut
down in these cases, because the capacitors connected to the DC-DC converter outputs may not all discharge at the same time.
Minimum Duration Between Two Supplies During Turn On
This condition is usually discovered during the board debug phase, when a board does not turn on reliably. The best solution is to be able to easily increase and/or decrease the delay between sequencing
steps.
Accommodating Changes to Sequencing Observed During the Board Debug Phase
Board design engineers are required to meet the sequencing requirements of all devices on the board during the final phases of the board design. To prevent a board re-spin, power sequencing sections are
designed with ample provisions for additional components and 0Ω jumpers. This increases the number of
components but still may not avoid a jumper wire or two.
Power Supply Ramp-Rate Control
Some devices require that the supply be turned on with a slow ramp to minimize current in-rush. To meet
this requirement, designers feed the power through a MOSFET and the ramp-rate is controlled through
the gate of the MOSFET.
Turning Unused Power Domains Off to Save Power During Inactive Periods
In order to reduce overall board power dissipation, designers turn off sections of the board when they are
not in use. This means that when a power domain is turned on, the supplies in that domain need to be
turned on in a sequence. Sometimes, to avoid disruption to the operation of the rest of the board, a shut
down sequence may be required to minimize current glitches in the system.
4.2 Flexible N-Supply Sequencing Using Power Manager II
II Devices
Power Manager II devices offer an ideal set of features, such as a PLD, multiple programmable threshold
comparators, multiple programmable duration timers and multiple charge pumps, that can be used to turn
MOSFETs on/off with programmable ramp-rate control. The resulting power management algorithm is
very flexible because all features of the device, as well as the sequencing algorithm, can be controlled by
the LogiBuilder utility in the PAC-Designer software tool. The sequencing algorithm also can be simulated to ensure that the algorithm is able to handle all of the faulty conditions.
Figure 4-2 shows a typical power supply sequencing implementation using the ispPAC-POWR1014A
device. In this circuit, the DC-DC converters are controlled by the ispPAC-POWR1014A device. While it
is possible to interface with the active-low enable signals directly with the ispPAC-POWR1014A device
outputs, an external transistor may be necessary to interface with active high enable signals.
Voltages are Monitored During/After Sequencing
All DC-DC converter voltages are monitored by the programmable threshold comparators of the ispPACPOWR1014A device. In this circuit, the ispPAC-POWR1014A device uses a programmable algorithm
designed using the PAC-Designer software tool to turn the DC-DC converters on/off through the DC-DC Power 2 You: A Guide to Power Supply Management and Control
4-4 Power Supply Sequencing
converter’s enable pins. During supply sequencing, the ispPAC-POWR1014A device will monitor the
output voltage of each of the DC-DC converters using the on-chip programmable threshold precision
comparators.
The power supply sequencing is controlled by the open drain output pins of the ispPAC-POWR1014A.
These output pins are controlled by the on-chip PLD. The sequencing algorithm is implemented using the
LogiBuilder utility in the PAC-Designer software. Using the LogiBuilder utility, one can implement the
following sequencing methods:
1. No sequencing – Here all the supplies are turned on at the same time and no sequencing is necessary.
2. The ispPAC-POWR1014A device waits for all the supplies to reach their operating levels and then
generates a power good signal for the board to begin the initialization process. Operating voltage levels are higher than the lower voltage limit and less than the over-voltage limit.
3. Closed loop sequencing – This is a sequence where one supply is turned on only after the previous
supply has reached its operating levels.
4. Time-based sequencing – The power sequencer inserts a time delay between each of the supplies without first checking if the first supply reached its normal operating level.
5. Closed loop sequencing with time delay – The second supply is turned on a fixed time after the first
supply is on and is within its normal operating voltage level.
6. The supply reaches its normal operating condition within a period of time. Often, supplies fail during
turn on. To prevent the locking up of sequencing while waiting for this failed supply, the algorithm
turns the supply on and, if the supply does not reach its normal operating voltage levels within a specified time, then the supply is considered faulty and action for incomplete sequencing is initiated.
7. Turn on multiple supplies with a watchdog timer – In this case, supplies are turned on using any of the
previous methods. After all the supplies are turned on, the power sequencing algorithm ensures that all
supplies are on within the total watchdog timer period. If the watchdog timer expires, the faulty
sequence action is initiated.
Any or all of these sequencing methods can be implemented easily using the LogiBuilder utility within
the PAC-Designer software. LogiBuilder enables implementation of a power management program using
six types of intuitive, user friendly and powerful instructions. The user has the flexibility to apply these
turn-on rules to each supply, or for groups of supplies, simply by using the appropriate LogiBuilder
instructions to manage that supply.Power 2 You: A Guide to Power Supply Management and Control
Power Supply Sequencing
Power Supply Sequencing 4-5
N-Supply Closed Loop Sequencing Algorithm
This section describes a closed loop N-supply sequencing algorithm implemented in the ispPACPOWR1014A device, as shown in Figure 4-2. Table 4-1 provides a detailed explanation of LogiBuilder
instructions, along with the associated sequencing method.
Figure 4-2. Flexible N- Supply Sequencing using the ispPAC-POWR1014A Device
The power management algorithm is implemented in LogiBuilder in a sequence of steps using the LogiBuilder instructions. The Power Manager II device then executes these steps to sequence the supplies on
the board. In this example there are N supplies.
During each of the first N steps, the LogiBuilder instruction turns on a power supply and waits for the
voltage to reach its operating limit.
1. Turn on DC-DC/LDO #1, enable the converter and wait for its output voltage to reach the operating
range. The ispPAC-POWR1014A device uses two precision programmable threshold comparators to
monitor a given voltage rail. One comparator threshold is set to the lower voltage limit of that voltage
rail and the second comparator threshold is set to the over-voltage limit. A DC-DC converter is in its
operating limit when its voltage is between the over and the under-voltage limits.
2. Turn on the DC-DC/LDO #2 enable signal and wait for its voltage to reach operating range.
3. Turn on the DC-DC/LDO #3 enable signal and wait for its voltage to reach its operating range (Same
function as step 2).
4. Continue turning on supply #4 (Same function as step 2).
5. Continue turning on supply #5 (Same function as step 2).
ADC
ispPAC-POWR1014A
En
V
OUT
POWER_GOOD
Shut_Down
N
OUT 3
OUT 4
OUT 10
OUT 11
OUT 12
SCL
SDA
IN1
IN 2
VMON 1 to
VMON N
Recycle Power
En
V
OUT
DC-DC /
LDO #1
DC-DC /
LDO #2
En
V
OUT
DC-DC /
LDO #N
Sequence_FailPower 2 You: A Guide to Power Supply Management and Control
4-6 Power Supply Sequencing
N. Continue turning on supply #N (Same function as step 2).
O. If all the supplies are within the operating range, activate the power good signal. If any of the supplies
are faulty, turn all the supplies off and activate the Sequence_Fail signal.
P. Wait for the Recycle_Power to become active and then jump to step 1.
Q. Shut-Down Signal Interrupt Routine – When the shut down signal becomes active, jump to step O.
N-supply Closed Loop Sequencing with Failure Monitor Algorithm
In the N-supply closed loop sequencing algorithm shown above, a supply failure would hold up the
sequence forever. While this phenomenon may be acceptable for most applications, some ICs may be
sensitive to being in a partially powered state for extended periods. In that case, the algorithm can be
modified to include turn on with monitor mode. For example, if a device is sensitive to the duration of a
partial power condition at step 2 of the algorithm above, it can be changed to the following:
1. Turn on DC-DC #1, enable converter and wait for its output voltage to reach operating range.
2. Turn on DC-DC#2 enable signal and wait for its voltage to reach operating range within 5ms. If the
supply does not reach operating range within 5ms jump to step O or else proceed to turn off the rest of
the supplies.
3. Turn on DC-DC #3 enable converter and wait for its output voltage to reach operating range.
4. Continue turning on supply #4, similar to step 3.
5. Continue turning on supply #5 with fault monitor, similar to step 2.
N. Continue turning on supply #N, similar to step 3.
O. If all the supplies are within the operating range, activate the power good signal. If any of the supplies
are faulty, turn all the supplies off and activate the Sequence_Fail signal.
P. Wait for Recycle_Power to become active and then jump to step 1.
Applying LogiBuilder Instructions to Sequencing Methods
As stated earlier, the LogiBuilder utility in the PAC-Designer software tool provides instructions to
directly support different types of sequencing. Figure 4-3 shows the block diagram of a power sequencing
circuit. Table 4-1 lists different LogiBuilder instruction sequences to implement the different sequencing
methods used to enable the power to Device #1.Power 2 You: A Guide to Power Supply Management and Control
Power Supply Sequencing
Power Supply Sequencing 4-7
Figure 4-3. Three Supplies of a Device Managed by an ispPAC-POWR1014A Device
Device #1 specifies that the 1.2V should be the first supply to turn on, the second is 2.5V for I/O and
finally 3.3V for another set of I/Os. Table 4-1 describes the LogiBuilder instructions to implement different sequencing methods while meeting the sequencing requirements of Device #1.
Table 4-1. LogiBuilder Instructions Description for a Given Sequence Method
Sequence Method LogiBuilder Instruction (s) Output Description
Closed Loop
Sequencing with
1.2V followed by
2.5V & 3.3V
Wait for Core_1V2_OK En_1V2=1 The 1.2V DC-DC is enabled (Active high) and the instruction waits at this step until 1.2V is in regulation
Wait for IO_2V5_OK AND
IO_3V3_OK
En_2V5=0,
En_3V3=1,
The 2.5V DC-DC is enabled (Active low) and The 3.3V
DC-DC is also enabled (Active high). This instruction
waits at this step until 2.5 & 3.3V supplies are in regulation
Open Loop
Sequencing with
1.2V followed by
2.5V Separated by
5ms
En_1V2 = 1 The 1.2V DC-DC is enabled (Active high) and the instruction does not wait at this step until 1.2V is in regulation
Wait for 5ms using Timer 1 Waits for 5ms at this step before activating the next supply
En_2V5 = 0 The 2.5V DC-DC is enabled (Active low) and the instruction does not wait at this step until 2.5V is in regulation but
proceeds with the next instruction
Closed Loop
Sequencing with
1.2V followed by
2.5V Separated by
5ms
Wait for Core_1V2_OK En_1V2=1 The 1.2V DC-DC is enabled (Active high) and the instruction waits at this step until 1.2V is in regulation
Wait for 5ms using Timer 1 Waits for 5ms at this step before activating the next supply
Wait for IO_2V5_OK En_2V5=0 The 2.5V DC-DC is enabled (Active low) and the instruction waits at this step until 2.5V is in regulation but proceeds with the next instruction
Turn-on and ensure
that the supply turns
on within a short
period of time
Wait for Core_1V2_OK with
Timeout of 5ms using Timer1.
If Timer1 Go to Fault
En_1V2=1 The 1.2V DC-DC is enabled (Active high) and the instruction waits at this step until 1.2V is in regulation within 5ms
(determined by Timer 1), if Timer 1 expires, jump to Fault
routine
OUT 3
OUT 4
OUT 5
VMON1
VMON2
VMON3
En_3V3
En_2V5
En_1V2
ispPAC-POWR1014A
2.5V Device #1
3.3V
1.2V
VIN
2.5V
3.3V
1.2VPower 2 You: A Guide to Power Supply Management and Control
4-8 Power Supply Sequencing
Any of these sequencing methods can be used for any supply or group of supplies. The timer values can
be set to any value between 32s and 2 seconds.
Advantages of Power Manager II-based Supply Sequencing
The sequencing of supplies is completely programmable. Designers can adjust the turn on or turn off
sequence and the associated timing to provide reliable board start up after the board is assembled. No
board re-spin is needed. Once the supplies are sequenced the ispPAC-POWR1014A device monitors all
of the supplies for faults.
Additional Power Management Functions that can be Integrated into Power
Manager II
In this circuit, the ispPAC-POWR1014A device provides flexible sequencing. The other functions that
can be integrated into an ispPAC-POWR1014A device are:
1. Voltage supervision – Monitor all supplies after sequencing for fault and generate an interrupt signal
such as a low voltage detect.
2. Reset generation – After the sequence is complete, the ispPAC-POWR1014A device can be used to
release Reset for the CPU.
3. Hot-swap controller – If power supply sequencing is required in a positive voltage hot-swappable
board, the hot-swap function can also be integrated.
4. Voltage measurement – In addition to all of the supplies being monitored for faults, an external
microcontroller can measure individual voltages through the I2
C interface.
5. Fault logging – In case of a fault, the ispPAC-POWR1014A device can output the status of all comparators to an external PLD for logging into a non-volatile memory to aid debug.
Applicable Power Manager II Devices
Power Manager II devices that can be used for implementing sequencing are the ispPACPOWR1220AT8, ispPAC-POWR1014/A, ispPAC-POWR607 and ProcessorPM-POWR605.
Turn-on multiple supplies with a watchdog timer
Start Timer2 Timer 2 is the watchdog timer (eg., 20ms) this is started
before beginning the supply sequence
En_1V2 = 1, En_2V5=0 The 1.2V DC-DC & 2.5V DC-DC are enabled and the
instruction does not wait for both supplied to reach regulation
If Core_1V2_OK and
IO_2V5_OK Then next step
Else if Timer 2 Then jump to
Fault
Else Stay at this step
This step waits for both 1.2V and 2.5V supplies to turn on
within the 20ms timer. If the turn on, the control jumps to
next step. If they fail to turn on within 20ms, the control
jumps to fault routine
Table 4-1. LogiBuilder Instructions Description for a Given Sequence Method (Continued)
Sequence Method LogiBuilder Instruction (s) Output DescriptionPower 2 You: A Guide to Power Supply Management and Control
Power Supply Sequencing
Power Supply Sequencing 4-9
4.3 Sequencing With MOSFETs and DC-DC Converter
Enables
In some cases, to meet the device’s sequencing needs without using additional DC-DC converters, MOSFETs are required. Figure 4-4 shows one such circuit, where a ispPAC-POWR1014A device controls the
DC-DC converter’s enable signals as well as an N-Channel MOSFET. In this circuit the MOSFET is used
to enable 3.3V to Device 1 after all of its other supplies are turned on.
To turn-on an N-Channel MOSFET on a 3.3V rail, its gate potential should be at least 8V. Designers
either use the 12V supply (if available on the board) or a charge pump IC to generate 8V or higher. The
ispPAC-POWR1014A device integrates two MOSFET gate drivers based on integrated charge pumps
that can generate up to 12V. The charge pump voltage can be programmed to 6V, 8V, 10V or 12V. In addition, the MOSFET turn on ramp-rate also can be controlled using the programmable current source feature of the MOSFET driver. The gate drive source current can be set to 12.5A, 25A, 50A and 100A.
The higher the current setting, the faster the MOSFET turn-on time.
Circuit Operation
In the circuit shown in Table 4-4, the ispPAC-POWR1014A device is controlling the enable signals of
1.8V, 2.5V and 1.2V DC-DC converters. The MOSFET driver of the ispPAC-POWR1014 device is used
to turn the MOSFET Q1
on/off. The sequencing logic is implemented in the PLD using the LogiBuilder
utility in the PAC-Designer software tool.
After sequencing is complete, the ispPAC-POWR1014A activates the Power_Good signal. If the
sequencing fails to complete, the algorithm activates the failed (to complete the sequence) signal.
The Shut_Dn signal is used to turn the supplies off in reverse sequence.
Figure 4-4. An ispPAC-POWR1014A Device Implementing Sequencing with MOSFET and DC-DC Enables
VMON 5
VMON1 to
HVOUT 1
OUT 3
OUT 4
OUT 5
Device #1
Device #2
Device #1 Sequence
1. 1.2V
2. 1.8V
3. 3.3V
Device #2 Sequence
1. 3.3V
2. 2.5V
3. 1.2V
1.8V
En
2.5V
En
1.2V
En
Shut_Dn
ispPAC-POWR1014A
OUT 6
OUT 7
SCL
SDA
3.3V
ADC
Power Good
Failed
Q1Power 2 You: A Guide to Power Supply Management and Control
4-10 Power Supply Sequencing
Power Sequencing Algorithm
The algorithm implemented in the Power Manager II is shown in Table 4-2 and Table 4-3). This section
uses the actual LogiBuilder code extracted from the PAC-Designer software.
Applicable Power Manager II Devices
Power sequencing using MOSFETs can be implemented in ispPAC-POWR1220AT8, ispPACPOWR1014/A and ispPAC-POWR607 devices.
Table 4-2. State Machine 0
Step Instruction Outputs Interruptible Comment
0 Begin Startup Sequence 0 ispPAC-POWR1014-02 reset
1 Wait for AGOOD 0
2 Wait for INP_3V3_OK 0 Do not proceed with the sequencing until input
supply is within operating range
3 Wait for IO_2V5_OK En_2V5 = 1, 0 3.3V is stable for Device 2. Now enable 2.5V and
wait for it to reach operating range
4 Wait for Core_1V2_OK or
2.56ms using Timer 1 If Timeout Then Go to 13 with {Failed
= 1,}
En_1V2 = 1, 0 1.2V supply should turn on within 2.5ms. If 1.2V
fails to turn on, activate Failed signal
5 Wait for IO_1V8_OK En_1V8 = 0, 0 Turn on 1.8V with active low enable signal and
wait for it to reach the operating level
6 Wait for FET_3V3_OK En_3V3_MOSF
ET = 1,
0 Turn the MOSFET on to begin feed 3.3V to
Device 1 and wait for it to be stable
7 Wait for NOT INP_3V3_OK
OR NOT IO_2V5_OK OR
NOT IO_1V8_OK OR NOT
Core_1V2_OK OR NOT
FET_3V3_OK
Power_Good =
1,
1 Wait for any supply to fail. If any supply fails, turn
all supplies off in reverse order. The power good
signal is activated as soon as the state machine
enters this step
8 Begin Shutdown Sequence 0
9 En_3V3_MOSFET = 0,
Power_Good = 0,
0 Fault condition, turn the MOSFET off first and
deactivate Power_Good Signal
10 Wait for 2.56ms using timer 1 0
11 En_1V8 = 1, 0 Turn-off 1.8V supply
12 Wait for 2.56ms using timer 1 0
13 En_1V2 = 0, 0 1.2V supply off
14 Wait for 2.56ms using timer 1 0
15 En_2V5 = 0, 0
16 Halt (end-of-program) 0
Table 4-3. Exception Table
EID Expression Outputs
Exception
Handler Comment
0 If Shut_Dn {no outputs
specified}
Go to step 8 Begin Shutting down supplies in reverse order
when Shut_dn signal is active CHAPTER
5
5-1
Hot-Swap Controllers
5.1 What is a Hot-Swap Controller?
Hot-swap controllers limit the inrush current when a circuit board is plugged into a live backplane. In addition, these devices offer over-current, over-voltage and under-voltage protection
to the circuit board. Figure 5-1 shows the block diagram of a typical hot-swap controller implementation for a positive backplane power supply rail. RS
is the current sense resistor. The
MOSFET Q1
is used to control the current through the circuit. The resistors R1
, R2 and R3
are
used to monitor the backplane voltage. The hold-off capacitor, Ch
, is used to provide power to
the board when the backplane voltage briefly drops below the low operating voltage (undervoltage) threshold (say, for less than 10ms).
Figure 5-1. Positive Rail Hot-Swap Controller
When the card is plugged into the live backplane, the hold-off capacitor, Ch
, begins to draw a
large amount of current from the backplane. The hot-swap controller limits the current in-rush
by controlling the voltage applied to the MOSFET gate using the voltage across RS
as feedback. The MOSFET will operate in this current limit mode until the capacitor Ch
is fully
charged.
During the brief capacitor charging period, the inrush current drawn from the backplane often
can be significantly higher than the normal board operating current. As a result, the backplane
voltage can dip below the under-voltage threshold momentarily for the other cards attached to
Hot-swap
Controller
OV
UV
Backplane Supply
(Positive)
Hold-Off
Capacitor
Load
Rs
R1
R2
R3
Ch
Q1Power 2 You: A Guide to Power Supply Management and Control
5-2 Hot-Swap Controllers
the backplane. The charge stored in the capacitor, Ch
, keeps the card operating during this brief voltage
dip period.
Hot-swap controllers are also required to isolate the board from the backplane in case it develops a fault
during operation. For this purpose, the hot-swap controller will monitor the current through the sense
resistor RS
. When the voltage across the resistor RS
increases beyond its threshold value, the hot-swap
controller turns the MOSFET off.
If the backplane voltage drops below the under-voltage threshold or goes above the over-voltage threshold, the power supply to the load is shut off by turning the MOSFET off.
Figure 5-2. Negative Supply Hot-Swap Controller
One of the popular backplane voltages in the telecom industry is -48V. Hot-swap controllers for negative
supplies use the current limiting MOSFET on the negative supply limb, as shown in Figure 5-2. Functions of negative rail hot-swap controllers are similar to the positive voltage hot-swap controllers
described above.
Hot-Swap Circuit Design Considerations
In a hot-swap controller circuit the MOSFET will be required to withstand high levels of power dissipation while the hold-off capacitor is being charged. The suitability of the MOSFET for this purpose is
determined by its Safe Operating Area (SOA) curves.
When a circuit board fault occurs, the current through the MOSFET can increase significantly. If the
MOSFET is not quickly turned off, the peak power dissipated on the MOSFET can damage it. hot-swap
controllers are also required to monitor over-current conditions and initiate either a fold-back current limiting mechanism or turn the MOSFETs off. Usually under high current conditions, the MOSFET should
be turned off within approximately 1s. Some hot-swap controllers implement “retry” to turn the board
on if the fault subsequently clears on its own accord. hot-swap controllers are also required to monitor for
low voltage conditions and shut the board off when such a condition occurs.
5.2 Implementing a Positive Supply Hot-Swap Controller
Using Power Manager II Devices
There are many types of hot-swap controllers with different current control and other monitoring mechanisms. Usually, the complexity of a hot-swap controller depends on the power dissipation requirement of
a circuit board. This section shows how Lattice Power Manager II devices can be used to implement hotswap controllers that range from the simple to the sophisticated.
Hot-swap
Controller
OV
UV
Backplane Supply
(Negative)
Hold-off
Capacitor
Load
R1
R2
R3
Rs
Ch
Q1Power 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-3
Hot-Swap Controller Using Soft-start
Figure 5-3 shows the ispPAC-POWR1014A device implementing a simple hot-swap controller. The principle of operation of this circuit is also called a ‘soft-start’ mechanism.
Figure 5-3. Hot-Swap Control Implemented Through MOSFET Ramp Rate Control
Circuit Operation
In this design, the backplane supply is 5V. The card with the ispPAC-POWR1014A device is plugged into
the live 5V backplane. The ispPAC-POWR1014A device first waits for the 5V backplane voltage to stabilize from the initial contact bounce. After the contact bounce period is complete, the ispPACPOWR1014A turns the MOSFET Q1
on through the Soft_start pin (HVOUT pin). The HVOUT pin
source current is set to a minimum (12.5A). This current charges the MOSFET gate capacitance slowly.
As a result, the MOSFET on-resistance also drops slowly to its final RDS-on value (usually in a few tens
to hundreds of mΩ range). This gradual reduction in MOSFET on-resistance reduces the current in-rush.
This circuit can only be used in low power and low voltage boards. It also requires that the instantaneous
power dissipated by the MOSFET does not violate its safe operating area specification.
Soft-start algorithm:
1. Wait for 5V to be continuously on for 100ms and ensure it is within tolerance by monitoring Inp_5V
signal.
2. Turn on Q1
by setting soft-start signal to logic 1.
3. Wait until supply at 5V load is within tolerance by monitoring the Out_5V signal.
4. Enable the 5V load through the Start_5V_Load signal.
Programmable Features
The following parameters can be changed to make this circuit meet a wide range of application needs:
• Comparator thresholds can be changed to suit difference backplane voltages, e.g., 5V or 3.3V. The softstart function for 12V can be implemented using a P-Channel MOSFET and driven by one of the logic
outputs. Negative rail soft-start can be implemented using N-channel MOSFETs.
• Contact de-bounce period can be changed from 50ms to 2 seconds.
Inp_5V
Soft_start
Backplane
Q1 5V Load
Start_5V_Load
Out_5V
VMON1
VMON2
HVOUT1
OUT3
ADC ispPAC-POWR1014A I
2
CPower 2 You: A Guide to Power Supply Management and Control
5-4 Hot-Swap Controllers
• MOSFET turn on ramp rate can be set using the four current settings available for each HVOUT pin.
• Design can be used to implement a dual hot-swap controller for dual supply backplanes using two
MOSFET drivers in the ispPAC-POWR1014 device.
Integrate Other Board Power Management Functions into a ispPAC-POWR1014A Device
This design consumes a very small portion of the ispPAC-POWR1014A device. The remaining resources
can be used to implement board power management functions such as power sequencing, voltage supervision, reset generation and watchdog timer.
In addition, one may also include faulty board identification and protection. If the board is healthy, the
voltage at the hold-off capacitor should stabilize within a short period of time (say, 5ms). If the board is
faulty (drawing more current than expected), the voltage at the capacitor will drop to a value less than the
lower voltage threshold. When such a condition arises, the MOSFET is turned off immediately. This prevents continuous overloading of the backplane.
One can also monitor the backplane voltage to generate early warning to the load circuit for safe turn off.
Backplane voltage and other on board rail voltages can be measured using the ispPAC-POWR1014A
device’s ADC via the integrated I2
C interface.
Applicable Power Manager II Devices
In this example, a ispPAC-POWR1014A device was used to implement the soft-start function. However,
the soft-start control application can also be implemented in ispPAC-POWR1220AT8, ispPACPOWR1014 and ispPAC-POWR607 devices. The ispPAC-POWR607 devices, however, do not support
the programmable ramp-rate control feature.
Hot-Swap Controller with Hysteretic Current Limit Mechanism
When designing hot-swap controllers for boards with higher power dissipation, or when one is not able to
guarantee the MOSFET safe operating area limits are not violated during the hot-swap operation, or when
the backplane inrush current is to be limited to prevent disruption to other boards plugged into the same
backplane, the following circuit (Figure 5-4) should be used. This circuit begins to operate with the
MOSFET Q1
turned on. The current starts to increase to charge the capacitor Ch
. When the current
exceeds the preset value, the logic in the hot-swap controller turns the MOSFET off. At that time, the current starts to decrease. When the current drops below the preset value, the logic turns the MOSFET on
and the current starts to increase again. This method of limiting the current to a preset value by turning
the MOSFET on/off is called hysteretic mode of operation. Power 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-5
Figure 5-4. Hot-Swap Controller with Hysteretic Current Limit
There are two additional blocks in comparison to the soft-start control circuit shown in Figure 5-3: current monitoring and quick shut-off control. The name of ispPAC-POWR1014A device’s high voltage
MOSFET gate drive pin has been changed from Soft_start to Hyst_Ctrl.
Principle of Operation of the Hysteretic Control Mechanism
Figure 5-5 shows plots of the gate drive of the MOSFET Q1
, current through the MOSFET and the voltage across the capacitor Ch
. When Hyst_Ctrl signal is turned on, Q1
’s gate capacitance starts to charge. At
the same time, the current through the MOSFET also begins to increase. The current through the MOSFET passes through the sense resistor RS
. The current sense amplifier (CSA) outputs a current proportional to the voltage dropped across RS
into series resistors R1
and R2
. The voltage drop across R1
and R2
is monitored by the ispPAC-POWR1014A device through the signal I_In (one of the VMON pins). The
comparator output of this VMON pin toggles when the current through RS
exceeds the maximum allowable limit (IH). As a result, the logic equation in the PLD turns the Hyst_Ctrl pin off. When the Hyst_Ctrl
pin is at logic 0, the MOSFET gate starts to discharge, throttling the current through the MOSFET channel, and the current through the MOSFET begins to drop. The voltage at the I_In pin reduces. When the
voltage drops below the I_In pin threshold (IL), the logic equation in the ispPAC-POWR1014A device
turns the MOSFET back on.
This cyclic throttling action maintains the average current to a value determined by the current threshold
settings. This technique provides many of the advantages of linear current control while sidestepping
many of the potential stability issues.
Inp_5V
Hyst_Ctrl
Q1
Out_5V
I_In
Rs
+3.3V
R1
R2
Short_Ckt
IN1
Backplane
5V Load
Start_5V_Load
ADC ispPAC-POWR1014A
SCL
SDA
VMON1
VMON2
VMON3
OUT3
HVOUT1
IN1
CSA
Q2Power 2 You: A Guide to Power Supply Management and Control
5-6 Hot-Swap Controllers
Figure 5-5. Hysteretic Current Control Through the Capacitor
Turning MOSFET Off Under Short Circuit Conditions
To prevent excessive current drain from the backplane and to protect the MOSFET against damage due to
excessive power dissipation during a short circuit event, the MOSFET should be turned off within 1s
from the time the current reaches a dangerous level. In Figure 5-4, the ispPAC-POWR1014A device’s
digital input pin IN1 is driven to Logic 0 by the transistor Q2
when the current through the 5V supply rail
exceeds short circuit current limit. The voltage across R2
is 0.7V when the current through RS
reaches the
short circuit current level. The logic equation in the ispPAC-POWR1014A device turns the MOSFET off
immediately within 200ns.
Hysteretic Hot-Swap Control Algorithm
The algorithm is divided into two sections:
• Logic equations for hysteretic control and fast-acting MOSFET shut down during a short circuit event
• Sequence control for overall hot-swap event control
Equation 1 implements the hysteretic control. The signal En_Hot_Swap turns the hot-swap controller on
or off. This signal is turned on by the sequence control algorithm after the contact-de-bounce period. The
Hyst_Ctrl (D-type flip-flop) is turned off when the I_In signal voltage exceeds the over-current limit level
and turns back on when the I_In signal drops below the threshold. The comparator hysteresis provides the
delay between turn-on and turn-off.
Equation 2 is a combinatorial equation that turns the MOSFET off as soon as the Short_Ckt signal is
equal to logic 0.
Equation 1:
Hyst_Ctrl.D = En_Hot_swap AND NOT I_IN
Equation 2:
Hyst_Ctrl.Reset = NOT Short_Ckt
VGH
VGL
IL
IH
Capacitor
Voltage
Time
Gate Drive
CurrentPower 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-7
Sequence control:
1. Wait for 5V to be continuously on for 100ms and within the tolerance limits (monitoring Inp_5V signal).
2. Turn on the hysteric hot-swap action by turning on En_Hot_swap signal.
3. Wait for supply at 5V load is within tolerance limits by monitoring the Out_5V signal.
4. Enable the 5V load through the Start_5V_Load signal.
5. During normal operation, if an over current or under-/over-voltage supply fault occurs for a period
greater than the hold-off period (5ms to 10ms), then shut the MOSFET off and retry.
Programmable Features
This circuit offers many programmable features that make it suitable for a wide range of applications.
• Comparator thresholds can be changed to suit different backplane voltages, e.g., 5V or 3.3V.
• Contact de-bounce period can be changed from 50ms to 2 seconds.
• Over-current and short circuit current levels can be set independently.
• The design can be used to implement dual hot-swap controllers for dual supply rail backplanes.
• Hold-off time is programmable from 2 to 100ms (time during which the MOSFET should be left on
under supply fault). After this period expires, the MOSFET is turned off.
The ispPAC-POWR1014A Device Can Integrate Other Board Power Management
Functions
The difference between the soft-start method and hysteretic control in the algorithm is the addition of two
logic equations. As a result, the remaining resources can be used to implement power sequencing, voltage
supervision, reset generation and watchdog timer functions for the board.
For faulty board identification and protection, add a watchdog timer when monitoring the load voltage
immediately after the hysteretic control loop is turned on (after step 4). If this timer expires before the 5V
reaches the operating threshold level (implying a fault that is preventing the charge build up in the capacitor Ch
), turn the MOSFET off and turn an LED on, indicating the supply fault.
Add backplane voltage monitoring logic to provide early warning to the load circuit for safe turn off.
Applicable Power Manager II Devices
This example used the ispPAC-POWR1014A device to implement the hysteretic control hot-swap function. However, the hysteretic control can also be implemented in ispPAC-POWR1220AT8, ispPACPOWR1014 and ispPAC-POWR607 devices.
Advantages of Using Power Manager II Devices for Hot-Swap Controller
There are many hot-swap controllers in the market. Designers have to use these hot-swap controller
devices in addition to the board management function. The Power Manager II device reduces the cost of
implementation by integrating the hot-swap controller function along with overall board management
into a single chip.
In addition, the design can be used across a wide range of applications.Power 2 You: A Guide to Power Supply Management and Control
5-8 Hot-Swap Controllers
12V/24V Hot-Swap Controller
The operating principle of this circuit is the same as that of the 5V hot-swap controller with hysteretic
control mechanism. Two additional features are added to make it compatible with the 12V hot-swap function. These features are an external charge pump and limiting operation of the MOSFET within its safe
operating range.
The maximum MOSFET gate drive voltage of ispPAC-POWR1014/A and ispPAC-POWR1220AT8
devices is 12V. However, to turn the N-Channel MOSFET on the 12V or 24V rail, one has to drive its
gate voltage to 22V or 34V, respectively (about 10V above the rail voltage). To achieve this high voltage,
the following circuit (Figure 5-6) implements an external charge pump using diodes, capacitors and a
transistor.
The operating principle of the external charge pump is as follows (Figure 5-6). The C_Pmp signal (ispPAC-POWR1014A HVOUT pin) toggles between 12V (for 32s) and 0V (for 8s) cyclically. When the
C_Pmp signal is at 0V, the capacitor C1
gets charged to backplane voltage of 12V through the diode D1
.
At this time the transistor Q2
is off. When the C-Pmp signal toggles up to 12V, the C1
voltage gets added
to the C_Pmp pin voltage, resulting in the generation of approximately 24V at the junction of C1
and D1
.
This voltage turns Q2
on and charges the capacitor C2
to about 22V through the diode D2
. This voltage is
sufficient to turn the MOSFET Q1
on.
The transistor Q3
, driven by the S_Dn signal, is used to shut the MOSFET Q1
off by discharging the
MOSFET Q1
gate and C2
when there is a fault.
Figure 5-6. 12V/24V Hot-Swap Controller Using an ispPAC-POWR1014A Device
Limiting the Hot-Swap MOSFET Within its Safe Operating Area
The ispPAC-POWR1014A device implements a hysteretic control loop to limit the current through the
MOSFET within safe operating limits when charging the hold-off capacitor Ch
. The HVOUT pin stops
toggling when the current through the resistor RS
exceeds the set threshold. When toggling is stopped, the
Inp_12V
Backplane
Q1
Out_12V
I_In
Rs
+3.3V
R1
R2
Short_Ckt
+3.3V
D1
Q2
D2
C2
C1
12V Load
Start_12V_Load
C_Pmp
S_Dn
Q3
Ch
VMON1
VMON2
VMON3
OUT3
HVOUT1
OUT4
ADC
ispPAC-POWR1014A
SCL
IN1 SDA
CSAPower 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-9
voltage at the MOSFET gate starts to drop down, reducing the current through the MOSFET. When the
current drops below the threshold, the C-Pmp signal starts to toggle, turning the charge pump on again
Figure 5-7. MOSFET Safe Operating Area (IRF7832)
The safe operating area of the chosen MOSFET (IRF7832) is shown in Figure 5-7 as a log-log graph with
the voltage across the MOSFET on the x-axis and the current through the MOSFET on the y-axis. The
dashed lines in the graph show the maximum allowable current at a given voltage across the MOSFET
for a given pulse width. The red line on the graph shows the operating current limit of this circuit.
Throughout the power-on process, the MOSFET never exceeds its safe operating area limits.
Figure 5-8. Inrush Current Through the MOSFET
I
D
, Drain-to-Source Current (A)
100 µs
1 ms
10 ms
Tc = 25° C
Tj = 150° C
Single Pulse
1000
100
10
1
V
DS, Drain-to-Source Voltage (V)
1 10 100Power 2 You: A Guide to Power Supply Management and Control
5-10 Hot-Swap Controllers
In the oscilloscope plot shown in Figure 5-8, the green trace is the current through the MOSFET and the
pink trace is the voltage across the capacitor. As can be seen, the current is limited to 2A until the voltage
across the capacitor reaches 6V, and after that the current is limited to 4A.
Figure 5-9. Circuit Operation During Short Circuit
When the circuit is turned on to a short circuit, the power feed begins as usual. If the capacitor voltage
does not reach 9V within 10ms, the MOSFETs are turned off and the circuit waits for a retry command.
Figure 5-9 shows the oscilloscope plot of the MOSFET turn-on current with the capacitor Ch
replaced
with a short.
12V Hot-Swap Controller Algorithm
The hot-swap controller algorithm is divided into the following sections:
• Logic equations for the external charge pump operation
• Logic equations for hysteretic control and fast-acting MOSFET shut down during a short circuit event
• Sequence control for overall hot-swap event control
Toggle_C_Pump is an internal variable used to generate 8 s wide pulses.
Equation 3 and Equation 4 use an on-chip hardware timer. There are four programmable timers in a ispPAC-POWR1014A device. Each timer delay can be set from 32s to 2 seconds. Timer count-down is iniEquation 3:
Toggle_C_Pump.D = 32 s Timer Terminal Count
Equation 4:
32 s Timer Gate.D = NOT Toggle_C_PumpPower 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-11
tiated by applying a logic 1 to the gate signal. The timer_TC signal transitions to logic 1 after the timer
count-down is complete. When the timer gate signal is connected to the inverted Timer_TC (Figure 5-
10), the timer generates a 4s pulse every time the timer expires.
Figure 5-10. Timer Configuration to Implement Programmable Frequency Clock
If the timer delay is set to, say, 32s, the timer TC and the timer gate outputs will be:
Figure 5-11. Generating 4µs Wide Pulses with Programmable Interval Using Timer
Equation 3 latches the timer TC into a variable Toggle_C_Pump. This stretches the timer gate by another
4s. The waveform of Toggle_C_Pump is shown in Figure 5-12.
Figure 5-12. Generating 8µs Wide Pulses with 32µs Interval Using Toggle_C_Pump
Programmable
Timer
Timer Gate Timer TC 32µs to 2 seconds
4µs
32µs
Timer Gate
Timer TC
8µs
32µs
Toggle_C_Pump
Toggle_C_Pump
Programmable
Timer
Timer Gate 32µs to 2 seconds
Timer TC
D Q
D-FFPower 2 You: A Guide to Power Supply Management and Control
5-12 Hot-Swap Controllers
Equation 5 controls the MOSFET drive circuit. The Toggle_C_Pump signal is used to drive the external
charge pump circuit. This pulse train is modulated by:
• En_Hot_Swap – Controlled by the sequence control
• (NOT I_IN_2_A AND NOT OUT_12V_GT_6V) – Hysteretic control that limits the current to less
than 2A when the voltage at Ch
is less than 6V
• (NOT I_IN_4_A AND NOT OUT_12V_GT_9V) – Hysteretic control that limits the current to 4A
when the voltage at Ch
is less than 9V
• MOSFET_FULLY_ON – Term that turns the MOSFET fully on when the voltage at Ch
is greater than
9V. This term is controlled by the sequence controller
Equation 6 is a combinatorial equation that turns the MOSFET off as soon as the Short_Ckt signal is
equal to logic 0 or when the operating current is greater than 4A.
Sequence control:
1. Wait for 12V to be continuously on for 100ms and within tolerance by monitoring the Inp_12V signal.
2. Turn on the hysteric hot-swap action by turning on the En_Hot_swap signal.
3. Wait for the supply at 12V load to be within tolerance by monitoring the Out_12V signal within 10ms.
If 10ms timer expires, set En_Hot_Swap signal to 0.
4. Set the TURN_MOSFET_ON_FULLY signal on.
5. Enable the 12V load through the Start_12V_Load signal.
Programmable Features
This circuit offers many programmable features that make it suitable for a wide range of applications.
• Comparator thresholds can be changed to suit different backplane voltages, e.g., 12V or 24V.
• Contact de-bounce period can be changed from 50ms to 2 seconds.
• Over-current, and short circuit current levels can be set independently.
Equation 5:
C_Pmp.D = NOT Toggle_C_Pump AND En_Hot_swap AND
((NOT I_IN_2_A AND NOT OUT_12V_GT_6V)
OR (NOT I_IN_4_A AND NOT OUT_12V_GT_9V)
OR MOSFET_FULLY_ON)
Equation 6:
Shut_Dn = NOT Short_Ckt or (MOSFET_FULLY_ON AND I_IN_4_A)Power 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-13
• Design can be used to implement dual hot-swap controller for dual supply backplanes using two MOSFET drivers of the ispPAC-POWR1014 device.
• Hold-off time programmable from 2 to 100ms (time during which the MOSFET should be left on under
supply fault). After this period expires, the MOSFET is turned off.
The ispPAC-POWR1014A Can Integrate Other Board Power Management Functions
The hot-swap controller uses only about 25% of the ispPAC-POWR1014A device resources. The remaining resources can be used to implement power sequencing, voltage supervision, reset generation and
watchdog timer functions for the board.
Applicable Power Manager II Devices
This example used the ispPAC-POWR1014A device to implement the hysteretic control hot-swap function. However, the hysteretic control can also be implemented in ispPAC-POWR1220AT8, ispPACPOWR1014, and ispPAC-POWR607 devices.
5.3 Implementing a Negative Supply Hot-Swap Controller
Figure 5-13 shows the circuit diagram of a -48V hot-swap controller using the ispPAC-POWR607
device.
Figure 5-13. Hot-Swap Controller Circuit Using an ispPAC-POWR607 Device
The ispPAC-POWR607 controls the MOSFET (STB120NF) shown at the bottom right of the circuit diagram, for inrush current control while operating the MOSFET in its SOA. The controller monitors the circuit current using the current sense resistor shown to the left of the MOSFET. The backplane voltage and
-48V
43k
3.3k
6V
3.3k
6V
.01µF
.05(RS)
Voltage
Regulator
ispPAC-POWR607
100k
100
HVOUT2
HVOUT1
VMON6
VMON5
VMON4
VMON3
VMON2
VMON1
GND
VCC
Vin_High
Vin_OK
VDS_2
VDS_1
Isense_2
Isense_1
Gate_Drive_2
Gate_Drive_1
Ch
IN/OUT3
Enable_Load
43k
IN2
Q2 Q3
VCC_607
GND_607
VCC_607
VCC_607
GND_607
IN/OUT4
Shut_Dn
R2 R1
-48V
Return
Load
STB120NFPower 2 You: A Guide to Power Supply Management and Control
5-14 Hot-Swap Controllers
the voltage across the MOSFET are monitored using two potential dividers of 43K and 3.3K. The 6V
zener diode is used to protect the ispPAC-POWR607’s input section.
When the blade is plugged into the backplane, the ispPAC-POWR607 waits for the contact bounce to settle and then begins to charge the hold-off capacitor, using current pulses instead of a continuous current
feed. The rate of current pulses is programmable to meet the MOSFET's power dissipation characteristics. Once the voltage reaches a preset threshold, the rate of current pulses is increased to hasten the
charging of the hold- off capacitor. After the hold-off capacitor is completely charged, the MOSFET is
fully turned on and the Power_Good Signal is activated. This signal is used to enable the DC-DC converter. The voltage across the MOSFET is monitored by the two voltage monitoring inputs of the ispPAC-POWR607. The programmable threshold set for the first voltage monitoring (Fast Charge Duty
Cycle Threshold) input determines the changeover from slow charging to faster charging of the hold-off
capacitor. The second threshold (End of Soft Start) indicates the completion of the charging of the holdoff capacitor and to fully turn on the MOSFET.
The ispPAC-POWR607 waits for a preset period (determined by the short circuit watchdog timer) for the
voltage across the MOSFET to drop below the fast charge threshold. If the voltage across the MOSFET
does not drop below the fast charge threshold, the MOSFET is turned off, indicating a fault such as a
short circuit. With this implementation, the MOSFET continues to operate within its Safe Operating
Area, even if a short circuit is present.
During normal operation, the ispPAC-POWR607 senses the beginning of a brownout period when the
backplane voltage drops below a preset threshold and initiates an internal programmable timer of 10ms.
If the power supply recovers within that time, the circuit continues to function normally. If the 10ms
timer expires, the hot-swap controller classifies it as an under-voltage event and jumps to the power recycle routine, waiting for the supply to stabilize before initiating a recharge of the hold-off capacitor.
During normal operation, when a card is plugged into the backplane, the backplane supply dips momentarily. During the voltage dip period, all cards use the hold-off capacitor to remain functional. Consequently, the hold-off capacitor loses some charge. When the backplane recovers, the charge in these
capacitors is replenished. This results in a brief current spike, usually less than 100s. This should be
ignored by the hot-swap controller. However, if there is a catastrophic current fault on the board, the hotswap controller should respond to this high current and shut the MOSFET down in less than 1s to prevent fault propagation and to prevent damages to the MOSFET. The transistor Q2
is used to protect the
card when the current fault results in very high current. When the voltage across the current sense resistor
exceeds 0.7V, the transistor Q2
turns on and applies a logical 0 to the digital input of the ispPACPOWR607. The logic equation within the ispPAC-POWR607 then turns on the transistor Q3
. Q3
discharges the MOSFET gate charge, resulting in turning the MOSFET off within 1s.
Controlling Current Inrush While Operating the MOSFET in its Safe Operating Area
The top trace of the oscilloscope in Figure 5-14 shows 10ms wide, 1.5A current pulses charging the holdoff capacitor. The bottom trace is the voltage across the MOSFET while charging a 4700F hold-off
capacitor.Power 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-15
Figure 5-14. Hold-off Capacitor Charging Current and Voltage Across the MOSFET
Two of the ispPAC-POWR607’s MOSFET drivers drive the MOSFET gate. One MOSFET driver maintains the current amplitude at 1.5A, and the second MOSFET driver controls the modulation rate. In this
circuit, the duty cycle was limited deliberately to one 10ms pulse every 260ms. This limits the worst-case
(during short circuit) average power dissipated by the MOSFET to 1.5A * 48V * 5ms / 260ms = 1.4W.
Hot-Swap Controller Algorithm
• The hot-swap controller algorithm is mainly implemented in an ispPAC-POWR607 device using
sequence control. However, the short circuit over current is monitored using a combinatorial logic
equation because of speed.
Sequence control:
1. Turn-off MOSFET and wait for contact bounce to settle.
2. Until the voltage across the MOSFET drops below 25V, charge the capacitor using 10ms wide 1.5A
pulses repeated once every 260ms. If the voltage does not drop below 25V within 512ms, stop hotswap.
3. After the voltage across the MOSFET drops below 25V, increase the duty cycle to 10ms wide 1.5A
pulses repeated at a rate of 65ms.
4. Wait for the voltage across the MOSFET to drop below 1V and turn the MOSFET on fully.
5. If an over-current condition occurs, turn the MOSFET off and retry once in two seconds.
Customizing the -48V Hot-Swap Controller
The entire hot-swap algorithm can be implemented within the 16-macrocell PLD of the programmable
hot-swap controller. Designers can customize this algorithm to suit their blade requirements. The following parameters of the programmable hot-swap controller can be customized:
• Short circuit watchdog duration: If the hold-off capacitor does not charge in the specified time
period, the MOSFET is shut off.
If Short_ckt_Det (output of Q2
) = 0 then turn on Q3
(Q3
discharges the MOSFET gate)
INPUT CURRENT
1A/div
FET VDS
20V/div
48V
1.5APower 2 You: A Guide to Power Supply Management and Control
5-16 Hot-Swap Controllers
• Charging Current Pulse Duration: The pulse width is set to guarantee that the MOSFET operates
within its SOA.
• Charging Current Pulse Frequency: This parameter, along with the charging current pulse duration,
determines the power dissipation for a given MOSFET.
• Minimum Hold-off Time Before Recycling: This determines the blade’s immunity to brownouts.
• Current Sense Scaling: This is set by the selection of the Rsense (RS
) resistor, R1
and R2.
• Height of Charging Current Pulse: Determined by the RS
resistor value, sets the amplitude of the
charging current pulses.
• Circuit Breaker Current: Maximum current value to initiate shut off and re-start.
• End of Soft-start Operation: Sets the voltage at which the MOSFET is fully turned on and the
Power_Good Signal is generated.
• Transition to Fast Charge Duty Cycle: Determines the voltage at which the charge pulse frequency is
increased to safely reduce the hold-off capacitor charging time.
• Minimum Operating Voltage: Determines the backplane voltage below which the brownout process
begins.
• Over-Voltage Protection: Above this voltage, the MOSFET is shut off to protect the blade circuitry.
Applicable Power Manager II Devices
This design is implemented using an ispPAC-POWR607 device. However, the ispPAC-POWR1014A
device can also be used to implement the hot-swap controller if the design requires voltage measurement
through the I2
C interface.
5.4 CompactPCI Board Management
Applications such as CompactPCI or CompactPCI Express use a backplane with multiple power supply
rails.
Figure 5-15 shows the requirements of the hot-swap controller for CompactPCI standard backplane with
voltages of +12V, +5V, +3.3V & -12V. In this design, the +5V and +3.3V rails carry the bulk of the
power.Power 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-17
Figure 5-15. CompactPCI Board Power Management Including Hot-Swap
The Power Manager II ispPAC-POWR1220AT8 device has been used to implement not only the hotswap controller but also the entire circuit board’s power management, as shown in Figure 5-15. In this
design, the 5V and 3.3V hot-swap controllers use the hysteretic current control mechanism (as described
in the section “Hot-Swap Controller with Hysteretic Current Limit Mechanism” on page 5-4) and the +12
and -12V use the soft-start control mechanism (described under “Hot-Swap Controller Using Soft-start”
on page 5-3). The +12V rail uses a P-Channel MOSFET.
CompactPCI Board Management Algorithm
The hot-swap controller, after initiating the hysteretic and soft-start functions, waits for the board supplies to reach normal operating levels within the watchdog time period and then activates the Healthy#
signal.
/BD_SEL
+12V
/PCI_RST
/HEALTHY
Board-level
Power Management
+12V Board
+5V Board
+3.3V Board
-12V Board
/Local_PCI_RST
CPCI
Bus
Board-side
Power
POL
1.8V
POL
1.2V
1.8V Board
1.2V Board
/en
/en
+5V
+3.3V
-12VPower 2 You: A Guide to Power Supply Management and Control
5-18 Hot-Swap Controllers
Figure 5-16. ispPAC-POWR1220AT8 Device – Complete CompactPCI Board Management
If the hot-swap function fails, the Healthy# signal is not activated and the main system does not activate
the PCI card. One can then re-initiate the hot-swap function by extracting and re-inserting the board into
the backplane. After all hot-swapped rails reach normal operating value, the ispPAC-POWR1220AT8
device initiates the sequencing of 2.5V and 1.8V supplies. After all supplies are stable (including the onboard sequenced supplies), the CPU reset signal (CPU_RSTb) is activated. If any supply fails, the
brown_out signal is activated.
Programmable Features
The circuit shown in Figure 5-16 can be customized for the following:
• Over-current for 5V and 3.3V
• Sequencing of board mounted voltage
• Protecting against board faults – Turn off all hot-swap MOSFETs
• Generating other board specific power management signals
• Measuring voltage and current
• Trimming and margining of supplies
Applicable Power Manager II Devices
This example shows CompactPCI Express board power management functions implemented using an
ispPAC-POWR1220AT8 device. If the CompactPCI Express board required the hot-swap function and
minimal board management, then a ispPAC-POWR1014A device would be sufficient.
+12V
+5V
Q1
Q2
Ch
1.8V
POL
2.5V
POL
BRD_SEL#
PCI_RST_b
Brown_Out
CPU_RSTb
12V
1.8V
2.5V
5V
3.3V
I_Sens3V3
FETDRV3V3
V_Sens3V3
I_Sens5V
FETDRV5V
V_Sens5V
V_In_12V
FETDRV12V
V_Sens12V
En_1V8
En_2V5
SCL
SDA
ispPAC-POWR1220AT8
-12V
+3.3V
En_Neg12
Healthy#
-12V
+3.3V
CSA
CSA
Q3Power 2 You: A Guide to Power Supply Management and Control
Hot Swap Controllers
Hot-Swap Controllers 5-19
CompactPCI Express Board Management
CompactPCI Express backplanes are similar to CompactPCI backplanes. However, the 12V supply is
also required to carry the bulk of the power in addition to +5V and 3.3V rails.
Figure 5-17. Complete CompactPCI Express Board Power Management
The difference between the CompactPCI and CompactPCI Express board power management implementation (Figure 5-17) is that in this circuit the 12V hot-swap uses a hysteretic current control mechanism.
The +5V and +3.3V hot-swap implementation is the same as the one described in “Hot-Swap Controller
with Hysteretic Current Limit Mechanism” on page 5-4. The 12V hot-swap mechanism is described in
“12V/24V Hot-Swap Controller” on page 5-8.
Programmable Features
• The secondary board power management section can be completely customized to meet board management needs.
• Power rail voltage and current can be measured through I2
C.
• 12V hot-swap behavior can be adjusted to meet the characteristics of any MOSFET.
Applicable Power Manager II Devices
This example shows CompactPCI Express board power management functions implemented using an
ispPAC-POWR1220AT8 device. If the CompactPCI Express board required the hot-swap function and
minimal board management, then a ispPAC-POWR1014A device would be sufficient.
+12V
+5V
+3.3V
Q5
Q1
Q2
D2
C2
C_Pmp
S_Dn
Q3
Ch
3.3V
ATNSW#
PRSNT#
PWREN#
PERST#
MPWRGD
12V
1.8V
2.5V
5V
3.3V
I_Sens3V3
FETDRV3V3
V_Sens3V3
I_Sens5V
FETDRV5V
V_Sens5V
V_In_12V
I_Sens12V
FETDRV12V
Sh
V_Sens12V
ut_Dn
En_1V8
En_2V5
SCL
SDA
CSA
CSA
1.8V
POL
2.5V
POL
Q4
CSA
ispPAC-POWR1220AT8Power 2 You: A Guide to Power Supply Management and Control
5-20 Hot-Swap Controllers
This page intentionally left blank.CHAPTER
6
6-1
Power Supply OR’ing Controllers
6.1 What is Power Rail OR'ing?
One method used to increase the reliability of high availability systems is through the use of
systems that are powered by two or more (redundant) power supplies. These supplies are generated either by multiple sources or the system is connected to the main supply by the use of
multiple paths. Boards connected to these redundant supplies derive a single high availability
rail through the use of diodes, as shown in Figure 6-1. This arrangement is called a power rail
OR’ing.
Figure 6-1. N-supply OR’ing Control Using Diodes
This is a simple arrangement. Only the supply that has the highest voltage drives the main
board voltage. Also, if the supply voltages are roughly equal, the load power is shared between
each source. If a supply fails, the load is transferred to other supplies automatically without any
interruption.
Although this is the simplest and most reliable way of OR’ing supplies, this circuit has a disadvantage: it wastes power. Diodes usually drop about 700mV. If the load current is, say, 2A, the
power dissipated by the diode is 1.4W. If there are ten boards in a shelf, the power dissipated is
14W, which stresses the cooling system. In addition, diodes that can dissipate more than 2W
must be used. These diodes are not only expensive but also are large, requiring more circuit
board area.
Vin A
Vin B
Vin N
I = 2A
Vdiode = 700mV
Vin to
Board
Power Dissipated = 1.4WPower 2 You: A Guide to Power Supply Management and Control
6-2 Power Supply OR’ing Controllers
To minimize the power dissipation, some designs use Schottky diodes. These diodes drop about 400mV,
resulting in approximately half the power dissipation. Nonetheless, the dissipated power is still too high,
and Schottky diodes are usually more expensive.
Modern power OR’ing circuits use MOSFETS (Figure 6-2) to reduce the power dissipation significantly.
Typical turn-on resistance of an N-channel MOSFET is about 25mΩ, so the power dissipated by this
MOSFET at 2A is 100mW (2*2*25 E-3). In other words, the power dissipation is reduced by 93%.
Figure 6-2. Power Supply OR’ing Control Using MOSFETs to Reduce Power Dissipation
6.2 Challenges of Designing a MOSFET OR’ing Circuit
When turned on, MOSFETs allow current to flow in both directions. Consequently, a voltage difference
between any two rails results in a reverse current flow into the lower voltage supply rail. For example, a
1V difference between VinA and VinB can result in 20A (1V / (0.025 +0.025)) flowing from the higher
voltage supply into a lower supply rail. This causes overloading of supplies and, in some cases, damage
to the supplies.
To prevent reverse currents, a power supply OR’ing control circuit is required. There are two methods
used for preventing the reverse current:
• Monitor current through the MOSFET and turn off the MOSFET, which has less current than the
threshold. Current dropping below the threshold can indicate reverse current build up in that limb. If the
current in all the limbs is greater than the minimum threshold, all the MOSFETs are left turned on in
order to enable load current sharing.
• Monitor the voltage difference between the rails of the input supplies and turn off the MOSFET that is
connected to the lower voltage rail. When the voltage difference between the two rails is less than a
diode voltage drop, then both MOSFETs are left on, the current to be shared.
The following section discusses positive voltage and negative voltage OR’ing circuits implemented using
Lattice Power Manager II devices.
Vin A
Vin B
Vin N
Vin to
Board
V
mosfet = 50mV
Power Dissipated = 100mW
I = 2APower 2 You: A Guide to Power Supply Management and Control
Power Supply OR’ing Controllers
Power Supply OR’ing Controllers 6-3
6.3 +5v Power Supply OR’ing (Using MOSFETs) Circuit
The circuit in Figure 6-3 shows OR’ing of two 5V supply rails, 5V_a and 5V_b. The OR’ing control
algorithm is implemented in a ispPAC-POWR1014A device. The current through each limb is monitored
by the ispPAC-POWR1014A device through current sense amplifiers CSA_a and CSA_b. MOSFETs Q1
and Q2
implement the OR’ing function. The common 5V supply rail is derived by combining the drain
terminals of Q1
and Q2
. When both MOSFETs are off, their body diodes provide an inefficient OR’ing
mechanism. In Figure 6-3 the OR’d supply feeds a hot-swap controller.
Figure 6-3. An ispPAC-POWR1014A Device Implementing Two-Rail 5V OR’ing Control
The circuit starts with both MOSFETs turned off. The load is turned on by enabling the hot-swap controller. When the load starts drawing power, it automatically draws power from one of the MOSFET body
diodes. If both voltages are very close, the load pulls current from both the MOSFET body diodes, and
both are sensed by the respective current sense amplifiers.
The ispPAC-POWR1014A device turns on the MOSFET on a limb only if the current through that limb is
above a threshold value. If the current in both rails is above their thresholds, then both MOSFETs are
turned on.
The ispPAC-POWR1014A device continues to monitor the current level in both limbs. During operation,
if the current through one of the MOSFETs drops below its low current threshold (due to a sudden drop of
Inp_5Vb
Hyst_Ctrl
Q2
5V_Hot-swap
Inp_5Va
I_Inb
Rs
R2
Q1
Rs
R1
5V_a
Start 5V_Hot-swap
CSA
A
VMON1
VMON2
VMON3
VMON4
HVOUT1
OUT3
SCL
SDA
ispPAC-POWR1014A
5V_b
I_Ina
ADC
CSA
B
HVOUT2Power 2 You: A Guide to Power Supply Management and Control
6-4 Power Supply OR’ing Controllers
that power rail’s voltage), then that MOSFET is instantly turned off. When the MOSFET is turned off its
body diode blocks the reverse current. Because the MOSFET is turned off when the current drops below
the positive threshold, the reverse current that would be driven back into the power supply is avoided. In
effect, this circuit implements OR’ing of supply rails through a proactive reverse current avoidance
method.
Algorithm for Implementing OR’ing through MOSFETs
Step 1 – Wait for at least one of the rails to reach operating voltage value.
Step 2 – Enable the load or the hot-swap controller.
Step 3 – Wait for the load to turn on.
Step 4 – If the current in Limb A is greater than its turn-off threshold, turn on the MOSFET.
Step 5 – If the current in Limb B is greater than its turn-off threshold, turn on the MOSFET.
Step 6 – Wait for either of the currents in the MOSFETS that are turned on in a limb to drop below its
turn-off threshold. If the current drops below the turn-off threshold, turn it off and wait for the current to
increase above the turn-off threshold, then turn the MOSFET back on. Continue executing step 6.
Programmable Features
The following programmable features enable the design described above to meet the needs of a wide
variety of OR’ing circuits.
• Individually program thresholds of two comparators to implement hysteresis using a logic equation for
MOSFET turn on current and MOSFET turn-off current levels.
• Programmable thresholds for determining the valid input operating voltage range.
Additional Functions That Can be Integrated into the ispPAC-POWR1014A Device
• Hot-swap controller – Either soft start or hysteretic current controller.
– One of the MOSFET drivers can be freed to implement the hot-swap controller by using the transistor circuit shown in Figure 6-4 on page 6-6.
• Integrate sequencing.
• Integrate voltage supervision, reset generation and watchdog timer functions.
Applicable Power Manager II Devices
Driving a 5V rail requires a MOSFET drive of 12V. This feature is supported in the ispPACPOWR1220AT8, ispPAC-POWR1014 and ispPAC-POWR1014A devices.Power 2 You: A Guide to Power Supply Management and Control
Power Supply OR’ing Controllers
Power Supply OR’ing Controllers 6-5
6.4 Power Supply OR’ing of Three or More 5V Supply Rails
Using MOSFETS
A ispPAC-POWR1014 device supports two MOSFET drive circuits; however, each MOSFET drive can
drive gates of multiple MOSFETs simultaneously. The circuit in Figure 6-4 makes use of this feature to
implement N-supply rail OR’ing through a MOSFET using one HVOUT signal from the Power Manager
II device.
The operating principle of this circuit is the same as above. The only difference here is that a four-transistor circuit is used to drive the MOSFET gate, as shown in the inset block as OR MOSFET Control.
The P1
PNP transistor is turned on to enable the voltage and current from HVOUT to the gate of the
MOSFET. P1
is turned on when N2
turns on, which is when the OUT pin of the ispPAC-POWR1014 is at
Logic 0 (N1
is off). At that time N3
is also off. To turn the OR MOSFET off, digital output is set to Logic
0. At that time N2
turns off and N3
turns on, draining the charge stored in the MOSFET gate, which turns
it off immediately.
The diode D1 is introduced in the base circuit of the N3
to delay turning on N3
compared to N1
, and to
turn the N3
off before N1
. This avoids the condition where P1
and N3
are both on at the same time, preventing turning off the other MOSFETS in the OR circuit.Power 2 You: A Guide to Power Supply Management and Control
6-6 Power Supply OR’ing Controllers
Figure 6-4. N-Channel OR’ing through MOSFETS
Algorithm Implementing N-channel OR’ing through MOSFETs
Step 1 – Wait for at least one of the rails to reach operating voltage value.
Step 2 – Enable the load or the hot-swap controller.
Step 3 – Wait for the load to turn on.
Step 4 – If the current in Limb A is greater than the minimum threshold, turn on the MOSFET through the
corresponding digital control.
Step N – If the current in Limb N is greater than its minimum threshold, turn the MOSFET on.
Step N+1 – Wait for either the current through the limb whose MOSFET is turned on to drop below the
threshold and then turn it off, or wait for the current in the limb whose MOSFET is turned off to go above
threshold and then turn that MOSFET on. Continue executing step N+1.
3.3V
HVOUT1
Gate
OUT
OR MOSFET Control
P1
N1 N2
N3
D1
Inp_5Vb
Qn
5V_Hot-swap
Inp_5Va
I_Inn
Rs
Rn
Q1
Rs
R1
5V_a
Start 5V_Hot-swap
CSA
a
VMON1
VMON2
VMON3
VMON4
HVOUT1
OUT3
SCL
SDA
ispPAC-POWR1014A
5V_n
I_Ina
ADC
CSA
n
OUT8
OUT9Power 2 You: A Guide to Power Supply Management and Control
Power Supply OR’ing Controllers
Power Supply OR’ing Controllers 6-7
(Steps N+1 is implemented using logic equations for all N-MOSFETs such that the circuit monitors and
controls all MOSFETs in parallel.)
Programmable Features
The following programmable features enable the design described above to meet the needs of a wide
variety of OR’ing circuits.
• Individually program the thresholds of two comparators to implement hysteresis (using logic equations) for MOSFET turn-on current and MOSFET turn-off current levels.
• Programmable thresholds for determining the valid input operating voltage range.
Additional Functions That Can be Integrated Into the ispPAC-POWR1014A Device
• Hot-swap controller – Either soft start or hysteretic current controller. The OR’ing circuit uses only one
MOSFET drive output. The second MOSFET drive can then be used to implement the hot-swap controller.
• Integrate sequencing.
• Integrate voltage supervision, reset generation and watchdog timer functions.
Applicable Power Manager II Devices
Driving a 5V rail requires a MOSFET drive of 12V. This feature is supported in the ispPACPOWR1220AT8, ispPAC-POWR1014 and ispPAC-POWR1014A devices.
6.5 N-rail (12V/24V) OR’ing
The operating principle of the N Rail 12V OR’ing with MOSFET is the same as that of the N-Rail 5V
OR’ing with MOSFET. The difference is that the gate of the N-Channel MOSFET on the 12V rail
requires higher voltage than the one supplied by the HVOUT pin of the ispPAC-POWR1014 device.
In addition to the blocks shown in Figure 6-4, Figure 6-5 shows an additional c-pump block at the bottom
right corner that implements an external charge pump to generate 20V at the MOSFET gate.Power 2 You: A Guide to Power Supply Management and Control
6-8 Power Supply OR’ing Controllers
Figure 6-5. N- 12V Rail OR’ing through MOSFET Using an ispPAC-POWR1014A Device
3.3V
CPOUT
Gate
OUT
OR MOSFET Control
P1
N1 N2
N3
D1
Inp_12Vb
Qn
12V_Hot-swap
Inp_12Va
I_Inn
Rs
Rn
Q1
Rs
R1
12V_a
Start 12V_Hot-swap
CSA
a
VMON1
VMON2
VMON3
VMON4
HVOUT1
OUT8
SCL
SDA
ispPAC-POWR1014A
12V_n
I_Ina
ADC
CSA
n
P2
C2
C1
D2
D3
OUT3
OUT9
CPOUT
HVOUT
12V_n
12V_a
C-PumpPower 2 You: A Guide to Power Supply Management and Control
Power Supply OR’ing Controllers
Power Supply OR’ing Controllers 6-9
Operating Principle of the C-Pump Block
The HVOUT pin of the ispPAC-POWR1014A device toggles, outputting 12V for 32s and 0V for 8s.
When the HVOUT pin is at 0V, the capacitor C1
gets charged to a voltage that is highest of all 12V rails
through the diode D2. When the HVOUT pin is at 12V, this voltage is then added to the capacitor (C1
)
voltage and that turns the transistor P2
on and charges C2
through diode D3
to approximately 20V. This
voltage is then routed to the MOSFET gates through the OR MOSFET control block.
The ispPAC-POWR1014 device, like the N-rail (5V) OR’ing circuit operation, then monitors the currents
through the rails and turns on the corresponding MOSFET if its current is higher than the turn-on threshold.
Algorithm Implementing N-Channel OR’ing Through MOSFETS
Step 1 – Wait for at least one of the rails to reach operating voltage value.
Step 2 – Enable the load or the hot-swap controller.
Step 3 – Wait for the load to turn on.
Step 4 – If the current in Limb A is greater than the minimum threshold, turn on the MOSFET through the
corresponding digital control.
Step N – If the current in Limb N is greater than its minimum threshold, turn the MOSFET on.
Step N+1 – Wait for either the current through the limb, whose MOSFET is turned on, to drop below the
threshold and then turn it off, or wait for the current in the limb whose MOSFET is turned off to go above
threshold and then turn that MOSFET on. Continue executing step N+1.
(Steps N+1 is implemented using logic equations for all N-MOSFETs such that the circuit monitors and
controls all MOSFETS in parallel)
Programmable Features
The following programmable features enable the design described above to meet the needs of a wide
variety of OR’ing circuits.
• Individually program the thresholds of two comparators to implement hysteresis through logic equations for MOSFET turn-on current and MOSFET turn-off current levels.
• Programmable thresholds for determining the valid input operating voltage range.
Additional Functions That can be Integrated Into the ispPAC-POWR1014A Device
• Hysteretic current control hot-swap controller. The OR’ing circuit uses only one MOSFET drive output. The Second MOSFET drive then can be used to implement the hot-swap controller.
• Integrate sequencing.
• Integrate voltage supervision, reset generation and watchdog timer functions.Power 2 You: A Guide to Power Supply Management and Control
6-10 Power Supply OR’ing Controllers
Applicable Power Manager II Devices
12V rail OR’ing using MOSFETS can be implemented using ispPAC-POWR607, ispPACPOWR1220AT8, ispPAC-POWR1014 and ispPAC-POWR1014A devices.
6.6 -48V Supply OR’ing Through MOSFETS
The circuit shown in Figure 6-6 monitors the voltage difference between the two -48V voltage rails using
a simple resistive voltage divider. In the following circuit there are two rails, -48VA and -48VB. Initially
the MOSFET is off and the OR’ing function is performed by the body diodes. The voltage difference
between the two rails is monitored by the resistors R1
through R4
. The values are selected such that when
the voltage difference is greater than 0.4V, a Schottky turn-on voltage, the corresponding node A_Hi or
B_Hi goes above 0.75V. The logic equation within the ispPAC-POWR607 device turns the MOSFET on
and the less negative rail is turned off, preventing reverse current. If the voltage difference between the
two rails is less than 0.4V, both MOSFETS will be turned on.
Figure 6-6. Dual -48V MOSFET OR’ing Circuit Using an ispPAC-POWR607 Device
Programmable Features
The values of R1
, R2
, R3
and R4
are selected such that there is a dead band of 0.4V about the common -
48V rail. That is, if the -48VA and -48VB are within 0.4V of each other, both the MOSFETS are turned
on. This dead band voltage value can be changed by selecting a different potential divider setting.
Additional Functions That Can Be Integrated Into the ispPAC-POWR607 Device
One of the useful functions that can be added to the circuit shown in Figure 6-6 is monitoring of -48VA
and -48VB rails, as well as monitoring for fuse failure as shown in Figure 6-7. The voltage monitoring
section generates two fault signals: Battery_Fail_VA and Battery_Fail_VB. These signals also become
active when the corresponding fuse fails. If all the boards in the shelf show a battery failure, then it indiAlgorithm:
If A_Hi is True, Turn on Q1
If B_Hi is True turn on Q2
-48VA
-48VB
10K
10K
A_Hi
B_Hi
A_On
B_On
Start_HS
Q1
Q2
R1
R2
R3
R4
To Hot-swap
Controller
BRD -48V
HVOUT2
GND
HVOUT1
VMON6
VMON5
OUT5
ispPACPOWR607
3K 3KPower 2 You: A Guide to Power Supply Management and Control
Power Supply OR’ing Controllers
Power Supply OR’ing Controllers 6-11
cates the main battery failure. However if one of the cards indicate the battery failure, it indicates a fuse
fault.
Figure 6-7 shows the -48V voltage sensing circuit that uses two 50kΩ resistors (R1
and R2
) to monitor
the voltage. The voltage at the junction of R1
and R2
determines the current through the resistors R2
, R4
and the transistor P1
. The ispPAC-POWR607 monitors the voltage across the resistor R4
, which is proportional to the voltage across the resistors R1
and R2
.
The second ispPAC-POWR607 device performs the hot-swap function in hot-swappable boards. The
voltage monitoring, fuse fault monitoring, MOSFET OR'ing, and hot-swap control functions can be integrated into an ispPAC-POWR1014 device. In addition, if power measurement is required, one can use an
ispPAC-POWR1014A device instead of the ispPAC-POWR1014 device and use a opamp circuit to
amplify the current through the circuit.
Figure 6-7. Voltage Monitoring in Addition to OR’ing Two -48V Rails Using an ispPAC-POWR607 Device
Figure 6-8. -48V Rail Voltage Monitoring Circuit Shown as Vsense A and VSense B Blocks in Figure 6-7.
Applicable Power Manager II Devices
This circuit can be implemented using the ispPAC-POWR607 or ispPAC-POWR1014A devices.
48V
Return
10K
10K
3K
A48_OV
A48_UV
B48_OV
B48_UV
A_Hi
B_Hi
A_On
B_On
Battery_Fail_VA
Battery_Fail_VB
Start_HS
Enable_Load
On_Off HS_Complete
L
O
A
D
Enable_Load
IN1 IN2
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
HVOUT1
GND
HVOUT2
OUT3
OUT4
OUT5
OUT6
ispPAC
POWR607
Hot-Swap
Controller
ispPACPOWR607 #2
Vsense A
Vsense B
-48VA
-48VB
-48V Rtn
-48V A/B
50K
50K
50K
3K
VMON of ispPAC-POWR607
GND of ispPAC-POWR607
R1
R2
R3
R4
P1Power 2 You: A Guide to Power Supply Management and Control
6-12 Power Supply OR’ing Controllers
This page intentionally left blank.CHAPTER
7
7-1
Power Feed Controllers
7.1 What are Power Feed Controllers?
In many systems, including base stations, microwave add-drop multiplexers and MicroTCA
shelves, a circuit board is required to feed power to an external system. In base stations, the
power is for a remote radio head; in the case of a microwave system, an external modem and an
antenna on a tower require power to be sourced from the system on the ground; and in the case
of MicroTCA, the power module is needed to feed power to multiple Advanced Mezzanine
cards plugged into the same shelf.
In most of these cases, the power feed is required to monitor for faults such as over current and
under current, as well as to provide short circuit protection. This chapter discusses -48V and
12V power feed arrangements because they are the most common. These designs can be modified to support other voltages as well.
7.2 Dual Rail -48V Supply Feed
The circuit shown in Figure 7-1 uses MOSFETs to control the power feed to two -48V rails. To
prevent damage to the MOSFETs during the power feed event, the current through the MOSFET is limited using a hysteretic current control mechanism for a fixed period. After that
period, the MOSFET is fully turned on and the circuit goes on to monitor the currents for over
current and under current faults. There are three types of current faults that can occur in power
feed circuits:
1. No current fault – If the external cable is broken
2. Over current fault- External system draws more current than normal (not dangerously high
current)
3. Short circuit current fault – Dangerously high current due to a short circuit in the power feed
cable
If a no-current or over-current fault is detected, the fault flag becomes active for that channel. If
a short circuit is detected, the MOSFET is shut down in less than 500ns. After a fault is Power 2 You: A Guide to Power Supply Management and Control
7-2 Power Feed Controllers
detected, the circuit tries continuously to restart the power feed as long as the enable signal is active for
that channel.
Figure 7-1. The ispPAC-POWR607 Device Implements a Dual-Channel -48V Power Feed Circuit
Circuit Operation
The circuit generates two channels of power, -48V_1 and -48V_2, through the MOSFETs Q1
and Q2
. The
open circuit current limit (the value below which the circuit is assumed to be open) is set by the resistors
RS
1 and RS
2. The monitoring threshold voltage of VMON1, VMON2, VMON3 and VMON4 pins of the
ispPAC-POWR607 device are set to 0.075V. The values of series resistors RS
1 and RS
2 are selected such
that at the lower current limit the voltage dropped across the RS
1 and RS
2 is 0.075V. The over current
limit is set by the resistors R1
and R2
for the power feed 1, and R3
and R4
set the over current limit for
power feed circuit 2. R1
and R2
are selected such that R1
/ (R1
+R2
) = 0.075V when maximum current is
flowing through the RS
1 resistor. In other words, Imax * RS
1 * R1
/ (R1
+R2
) = 0.075V. The values of R4
and R5
are also selected using the same equation.
When the enable signal is activated, the circuit turns on the MOSFET with the current limited to a value
determined by the programmed over current limit for a period determined by the Timer 1 for power feed
1 and Timer 2 for the circuit 2. After Timer 1 or Timer 2 expires, the corresponding MOSFET is fully
turned on and the circuit starts to monitor for over and under current. Note: The selected MOSFET should
be able to handle the maximum current for the duration determined by Timer 1.
After the MOSFET is fully turned on, if an over or under current condition is detected, the MOSFET is
turned off through the transistor N1/ N2, and Timer 3 and Timer 4 (retry timers) are started. When the
retry timer expires, the MOSFET is turned back on with an initial hysteretic control, as before.
If the circuit detects a very high current (as detected by 0.7V across the series resistors RS
1, RS
2) the
transistors N3, N4 pull down signal SC1 and SC2. These signals are connected to the digital inputs of the
ispPAC-POWR607 device. The logic equations within the ispPAC-POWR607 device shut the MOSFET
SC_2
Fault_1
R1 R2
R3
R4
Rs1
Rs2
Q2
N1
N2
100K
100K
VMON 1
VMON 2
HVOUT1
VMON 3
VMON 4
HVOUT2
OUT3
OUT4
-48V_1
-48V_2
Fault_2
OUT6
OUT5
OC_SCb
OUT7
ispPAC-POWR607
-48V_IN
SC_1
GND
-48V_Rtn
3V3 Reg
Vcc
SC_2
SC_1
En_2
En_1
VMON 6
VMON 5
IN1
IN2
N3
N4
Q1Power 2 You: A Guide to Power Supply Management and Control
Power Feed Controllers
Power Feed Controllers 7-3
Q1
, Q2
down immediately through N1
, N2
(in less than 500ns) and the retry timer is started. After the
retry timer expires, the transistor N1
, N2
that shuts down the MOSFET is turned off.
The Fault 1 and Fault 2 signals are controlled by a routine that monitors over and under current conditions in each of the circuits. When an over current fault occurs, the corresponding flag is set to high.
Along with that, the UC_OCb (under current and over current flag) will be set to logic 0. If an under current event is detected, the UC_OCb signal will be set to Logic 1. If the fault exists in both circuits 1 and
2, then the status flag toggles between the conditions once every 8ms.
Algorithm
The design is implemented using logic equations to provide independent operation on each of the channels. The following algorithm makes use of simple logic equations. There are five equations that control
the power feed for one of the circuits. All equations are active in parallel. For example, the short circuit
monitoring section is always active and shuts the MOSFET down if a short circuit occurs when any one
of the other four equations are operational. This algorithm (set of five equations) is repeated for the second channel power feed.
The fault indication flags are controlled by the algorithm implemented in the sequence controller section
of the algorithm.
1. Equation 1 circuit 1 – Waits for the enable signal to become active to begin the hysteretic controlled
power feed. The Power feed is expected to be complete within a preset period set by the hysteretic
control timer. The hysteretic control timer is also started when the enable signal gets activated and
starts the hysteretic control timer. After the initial hysteretic control timer expires, the MOSFET is
turned on fully. If a fault is detected, this equation waits for the retry timer to expire before initiating
the hysteretic power feed.
2. Equation 2 circuit 1 – Waits for a short circuit condition detection. When a short circuit is detected,
this equation turns the MOSFET off through a fast asynchronous reset signal.
3. Equation 3 circuit 1 – Monitors for over or under current conditions. When such a condition is
detected, the MOSFET is turned off and a retry timer (2 seconds) is started.
4. Equation 4 circuit 1 – Monitors for the retry signal and the enable signal to begin the 5ms hysteretic
control timer. This hysteretic control timer is used by equation 1.
5. Equation 5 circuit 1 – The fault flag is cleared to recapture the fault condition when the normal operation begins.
The fault conditions are reported by the sequence controller.
1. When the circuit 1 is operating normally and a fault has not already been reported, check on circuit 1
for over or under current fault on circuit 1 and, if a fault is detected, activate the Fault_1 output.
2. If it is an over current condition or short circuit condition, turn the UC_UCb flag off.
3. When the circuit 2 is operating normally and a fault has not already been reported, check on circuit 2
for over or under current fault on circuit 2 and, if a fault is detected, activate the Fault_2 output.Power 2 You: A Guide to Power Supply Management and Control
7-4 Power Feed Controllers
4. If it is an over current condition or short circuit condition, turn the UC_UCb flag off or else turn it
back on.
Programmable Features of this Circuit
1. The over-current, no-current conditions can be set by selecting the RS
1, R1
and R2
for circuit 1 and
RS
2, R3
and R4
for circuit 2.
2. Program the hysteretic current timer duration to meet the MOSFET’s safe operating area. Note: Both
over current and the duration of hysteretic control duration are determined by the safe operating area
of the MOSFET.
3. Retry duration can be set independently for both circuits.
Applicable devices:
This circuit uses the ispPAC-POWR607 device.
7.3 Three Channels of a +12V Power Feed System
In some applications, two or more channels of 12V power feed are required. For such applications, the
following three-channel power feed circuit is used. More than three channels of power feed requires multiple implementations of the following circuit. This design is modular in order to address implementations requiring less than three channels of power feed so that free resources can be used for other payload
power management functions.Power 2 You: A Guide to Power Supply Management and Control
Power Feed Controllers
Power Feed Controllers 7-5
Figure 7-2. Three-Channel 12V Power Feed Circuit
Figure 7-2 shows a ispPAC-POWR1014A device used to feed 12V to three channels. Each of the channels can be controlled independently. For each channel this circuit offers under current, over current and
short circuit current protection, along with fault indication. After the fault is detected, the circuit retries
continuously with a programmable delay between retries. The power is controlled through a MOSFET
and the circuit ensures operation of the MOSFET in its safe operating area. All voltage and current during
the operation can be measured using the on-chip ADC through I2
C.
Circuit Operation
The ispPAC-POWR1014A device derives its power from the input 12V supply. The operating principle
of the external charge pump is as follows (Figure 7-2):
The ispPAC-POWR1014A HVOUT pin toggles between 12V (for 32s) and 0V (for 8s) cyclically.
When the HVOUT1 pin is at 0V, the capacitor C1
gets charged to backplane voltage of 12V through the
diode D2
. At this time the transistor P2
is off. When the HVOUT1 toggles up to 12V, the C1
voltage is
added to the HVOUT1 pin voltage, resulting in the generation of approximately 24V at the junction of C1
and D2
. This voltage turns P2
on and charges the capacitor C2
to about 22V through the diode D3
. This
voltage is sufficient to turn on the MOSFETs Q1
through Q3
.
Inp_12VIn
Rs3 Q3
Rs2 Q2
12V_In
P2 C2
CPOUT
HVOUT
C-Pump
C1
D2
D3
Rs1 Q1
2
12V#1
12V#2
12V#3
CPOUT
I_12V_1,
Out_12V_1
SC_1
SC_2
SC_3
EN_1
EN_2
EN_3
SC_1,2,3
3.3V
SC
I_12V
Out_12V
CPOUT
Drv
S_Dn
Gate 12V
12V_In
Fault_1, Fault_2, Fault_3
ADC
ispPAC-POWR1014A
VMON1
VMON2,3
VMON4,5
SCL
OUT3,4
HVOUT1
SDA
VMON6,8
OUT5,6
OUT7,8
VMON9
VMON10
IN1
IN2,3,4 OUT9,10,11
2
2
2
2
2
3.3V
CPOUT
Gate
Drv
OR MOSFET Control
P1
N1
N2
N3
D1
3.3V
3.3V
S-Dn
N4
CSAPower 2 You: A Guide to Power Supply Management and Control
7-6 Power Feed Controllers
Once on, the device begins toggling the HVOUT1 pin to generate about 22V at the CPOUT pin and waits
for a high on any of the 3 EN signals. After receiving the En signal, the corresponding MOSFET is turned
on using the dual current level hysteretic control mechanism while monitoring for the output voltage.
When, say, the EN_1 signal is turned on, the OUT3 pin is set to logic 0. This turns off the transistor N1
,
which in turn turns on the transistor N2
. The transistor N2
provides the gate drive for the transistor P1
,
turning it on. The transistor P1
then applies 22V from the CPOUT pin to the gate of the MOSFET Q1
through a resistor, turning it on.
If a supply fault is detected, the OUT3 and the OUT4 pins are set to Logic 1. This turns off the transistor
P2
and turns on the transistor N4
. The N4
then discharges the MOSFET gate to turn it off immediately.
When power feed operation begins the MOSFET Q1
is turned on. As a result, the current through the
MOSFET starts to increase significantly. This results in the MOSFET operating outside its safe operation
area (SOA), resulting in damage to the transistor. To avoid that damage, the MOSFET is turned on with a
hysteretic current control. The following section describes the MOSFET current control operation.
Dual Current Level Hysteretic Control
Figure 7-3 shows the safe operating area for a MOSFET. This is a Log-Log graph with voltage across the
MOSFET (VDS) on the X-axis and current through the MOSFET on the Y-axis. The dotted lines represent the safe operation envelopes for different pulse width durations. When the power is applied to the
MOSFET and begins to turn on, the point of operation is at the right bottom side of the graph. The red
line indicates the current limit controlled by the hysteretic controller implemented in the ispPACPOWR1014A device. The current through the MOSFET is limited initially to the lower level. This current charges the capacitor on the load, reducing the voltage across the MOSFET. When the voltage across
the MOSFET drops to approximately its mid point (for example, 6V), the current is doubled while operating completely within the safe operation area. The first set point current and the second set point values
are determined by the safe operation area of the MOSFET as shown by the red line in Figure 7-3.
Figure 7-3. Safe Operating Area of MOSFET – (IRF7832)
I
D
, Drain-to-Source Current (A)
100 µs
1 ms
10 ms
Tc = 25° C
Tj = 150° C
Single Pulse
1000
100
10
1
V
DS, Drain-to-Source Voltage (V)
1 10 100Power 2 You: A Guide to Power Supply Management and Control
Power Feed Controllers
Power Feed Controllers 7-7
After the voltage at the load reaches the minimum operating value, the MOSFET is turned on fully. The
circuit then begins to monitor for over current and no current faults. When a fault is detected, the corresponding fault output is activated and the circuit waits for the retry delay. During the retry waiting period,
the fault indication is maintained. After the retry period, the circuit begins to restart the MOSFET current.
If the output voltage does not reach its minimum operating value within 10ms, the fault flag is turned on
and the circuit waits for another retry period.
Algorithm for Each Power Feed Channel
1. Wait for enable signal.
2. Start power feed and wait for output voltage to reach its minimum operating level within 10ms. This
step turns on the MOSFET with two current settings.
3. If the output voltage is within its safe operating level, turn the MOSFET on fully and begin monitoring
the output current for over and under current faults. If a fault is observed, flag the fault, then turn the
MOSFET off and jump to retry timer.
4. Wait for the retry timer to expire, then jump to step 1 to begin the power feed process.
5. During the four step sequence above, the following operations are performed in parallel:
– 12V Power feed control with two-step current feed.
– Monitor for short circuit current and turn the MOSFET off within 500ns when a fault is detected.
– Monitor for the enable signal and turn off the MOSFET.
Programmable Features of Power Feed
The following section outlines all the programmable features of this design:
1. Customize the design to meet any MOSFET characteristics: two current levels can be programmed. If
the design requires only one current level, the corresponding equation can be changed easily.
2. If faster turn-on times are required, the circuit can be modified to pump larger currents during start up.
These new currents can be independent of the min and max operating current limits.
3. The timer used to monitor the initial supply turn-on period is programmable. This design used 10ms. It
can be increased or decreased, depending on the design’s requirement.
4. Retry period – this design used a two second timer. It can be programmed from 32s to two seconds in
122 steps.
5. Over current and under current setting – this can be changed simply by altering the threshold of the
comparator.
Integrating Other Payload Power Management Functions into the ispPACPOWR1014A Device
This circuit uses the ispPAC-POWR1014A device to implement three channel 12V power feed functions.
Each channel uses three VMON signals, one digital input signal and four output signals. If the circuit
requires fewer power feed channels, that portion of the design can be removed and the free resources can
be used to integrate other payload power management functions, such as sequencing, monitoring and Power 2 You: A Guide to Power Supply Management and Control
7-8 Power Feed Controllers
watchdog timers. This design can also be exported to a ispPAC-POWR1220AT8 device to implement the
three channel power feed functions along with other payload power management functions.
Applicable Power Manager II Devices
This design used the ispPAC-POWR1014 device. However, the power feed algorithm can be integrated
into a ispPAC-POWR1220AT8 device, or an ispPAC-POWR607 device can be used to implement the
power feed algorithm for each channel.
7.4 2-Channel +12V & 3.3V Power Feed With MOSFET
OR’ing
In applications such as MicroTCA, the power module is required to implement 16 channels of 12V power
feed circuits. Each channel provides power to an Advanced Mezzanine Card (AMC) slot. When an AMC
is plugged into the back plane, the power module turns on the 3.3V to power the AMC’s management
module. The management module then communicates with a shelf manager, which then orders the power
module to turn-on 12V. In some cases, the 12V supply is turned on along with the 3.3V supply and the
circuit does not wait for an independent payload power enable signal. The power module then begins to
monitor for over current and, if an over current condition is detected, the MOSFET is turned off. During
system operation, if the AMC card is extracted the Power Module is required to turn the power off within
100s.
For reliability purposes, the 12V and 3.3V supplies are sourced from two different power module cards.
Both of these supplies are OR’d on the backplane. At any given time only one of the power modules supplies power to the backplane. The standby power module sets its voltage to a value lower than the online
module. To avoid wasting power, MOSFETs are used to provide OR’ing functionality. A detailed
description of the MicroTCA power feed standard is beyond the scope of this document.
The circuit in Figure 7-4 shows how a ispPAC-POWR1014A device can be used to implement a twochannel power feed.Power 2 You: A Guide to Power Supply Management and Control
Power Feed Controllers
Power Feed Controllers 7-9
Figure 7-4. One-Channel uTCA Power Feed Using Half of an ispPAC-POWR104A Device
Circuit Operation
Figure 7-4 shows the circuit required to implement one channel of 12V and 3.3V power feed. The 12V
power feed is controlled through two MOSFETs, the Pass device (Q1
) and the OR’ing (Q2
) device, shown
at the top right section of the circuit. The 3.3V power feed is controlled through a P-Channel MOSFET
Q3
using the transistor N3
. When the Enable# signal is active, the 3.3V supply is turned on through the
MOSFET Q3
. Subsequently, when the Payload_On signal becomes active, the 12V power is fed to the
circuit through the Pass MOSFET Q1
. The pass MOSFET Q1
is turned on using the two-current hysteretic control mechanism. Because Q1
is on the 12V rail, its gate voltage should be at about 20V when it is
turned on. The 20V gate drive is generated through the external charge pump implemented using C1
, D1
,
P2
, D2
and C2
(the circuit operation described in “Dual Current Level Hysteretic Control” on page 7-6),
to ensure that the MOSFET is operated within its SOA. Once the output power is above its minimum
operating level, Q1
is fully turned on and the OR’ing MOSFET Q2
is turned on or off depending on the
EMMC primary or redundant status. This ensures that only the primary supply wins the OR’ing arbitration. When an over current event is detected, the ispPAC-POWR1014A device shuts Q1
and Q2
down
through the transistor N1
.
EMMC Alert
VMON
Open Drain
Digital Out
HVOUT1
OUT
VMON
OUT
EMMC Primary/
Redundant
Enable#
Payload On
Mgmt Power
Control
Current
Sensing
Pass
Device
OR’ing
Device
Q1 Q2
12V Payload
Power
to Load
100 100
4.7M
P1
4.7M 0.001µF
C2
MMBT
2222A
N1
47
D2 P2
0.01µF
C1
2.2K
Quick Shutoff
Output Monitor
Half of
ispPACPOWR1014A
OR-FET
Control
MMBT
2222A N2 Q3
3.3V Power
to Load
D1
Open Drain
Digital Out
Vcc
12V
3.3V
+
_
47M
3K
N3
6V 1K
MMBT2907
Primary
Power
SourcePower 2 You: A Guide to Power Supply Management and Control
7-10 Power Feed Controllers
During Operation
1. If the output supply drops below the minimum threshold (probably because the on-line supply has
failed), the standby device turns on the OR’ing MOSFET Q2
and the primary device turns the OR’ing
MOSFET off and flags the EMMC Alert signal. This ensures that the AMC does not see its 12V supply voltage dip below its operating level.
2. The current in the 12V supply is also monitored for fault. If the current exceeds the maximum operating level, the Pass MOSFET is turned off, activating the EMMC Alert signal.
3. Before the extraction of the AMC from its slot, the AMC usually sends a signal to the shelf manager.
The shelf manager then deactivates its payload power supply by disabling the Payload_On signal.
When the payload signal is turned off, the user can extract the AMC from its backplane. Subsequently,
when the AMC is extracted, the enable signal gets deactivated and the 3.3V supply feed to the AMC is
turned off within 100s. In some cases, the enable payload voltage signal does not exist. In such cases,
the design can be modified to support only Step 4.
4. In the case of an accidental AMC card extraction process, both 12V and the 3.3V supplies are turned
off at the same time within 100s from the time the enable signal becomes inactive.
ispPAC-POWR1014A (MicroTCA) Power Feed Algorithm
1. Wait for the enable signal, and when it becomes active turn the 3.3V supply on.
2. Wait for the Payload_On signal and turn 12V on. This can be modified easily to turn 12V on when the
enable signal is activated. If the 12V does not turn on within 10ms, turn 12V off and report the fault.
3. Turn OR’MOSFET on if the card is primary; otherwise, turn the OR’ing MOSFET off.
4. Start to monitor the following and take action:
a. Current – Should be lower than the over current limit. If the current is more than the over current limit, shut the Pass MOSFET off and flag the error to EMMC.
b. Output voltage – If the voltage is not higher than the lower threshold for primary, then turn the
OR’ing MOSFET off and report the error. If the payload voltage is higher than the over-voltage
limit, turn the Pass and OR’ing MOSFETs off and report the error to the EMMC.
c. If the card is configured as secondary or redundant, and if the voltage is lower than the minimum primary voltage, turn the OR’ing MOSFET on and report the error back to EMMC.
d. If the enable signal becomes inactive, turn the Pass and OR’ing MOSFETs off immediately.
e. If the primary becomes secondary during operation, turn the OR’ing MOSFET off and monitor
for lower than allowed voltage to turn the MOSFET on.
f. If the secondary becomes primary, turn the OR’ing MOSFET on and start monitoring for a
higher than allowed voltage range.Power 2 You: A Guide to Power Supply Management and Control
Power Feed Controllers
Power Feed Controllers 7-11
Programmable Features
• The power feed turn on monitor duration can be programmed to meet the requirements of different
MOSFETs.
• The maximum value of the output current can be altered by reprogramming the ispPAC-POWR1014A
device’s current monitor thresholds.
Other Functional Enhancements
• The voltage and current values can be measured through I2
C.
• Not all MicroTCA implementations use all of the features specified in the standard. In such cases, one
can keep the OR’ing MOSFET off when the current is below a lower threshold limit. This protects
against reverse current flow from the secondary when its voltage is higher than the primary.
Applicable Power Manager II Devices
While up to four channels of Power Feed can be implemented in a ispPAC-POWR1220AT8 device, an
ispPAC-POWR607 device can be used to power a single channel.Power 2 You: A Guide to Power Supply Management and Control
Power Feed Controllers
Power Feed Controllers 7-12
This page intentionally left blank.CHAPTER
8
8-1
Margining and Trimming
8.1 What is Voltage Margining?
Margining is a test step that ensures a board is operational across the input variable range. A
voltage margining test ensures that the board is functional across the operating range of its
onboard and input supplies. Circuit boards are also subject to other margining tests such as
temperature, timing and noise.
For example, if the allowed tolerance of input supply is ±10%, the voltage margining test
ensures that the board is functional when the input supply is at its margin-high (nominal voltage + 10%) value and when its supply is at margin-low (nominal voltage -10%) value. If the
board has a number of board-mounted supplies, then the margining test should also cover the
variation of individual board-mounted supplies.
Semiconductor devices typically operate slowest when their operating temperature is at its
highest value and applied voltages are at their lowest. Similarly, these devices are fastest when
the operating temperature is at its lowest and the voltages are at their highest. To ensure that the
design is stable across temperature and voltage, designers subject their circuit boards to high
temperature in an environmental chamber with the operating voltages dialed down, and then
check the operation at colder temperatures with their voltages dialed up. This is called 4-corner
testing.
Margining tests typically are conducted during board debug. In some cases, Quality and Reliability departments will require margining before they will approve manufactured boards.
8.2 Voltage Margining Implementation
Figure 8-1 shows a DC-DC converter with a resistor connected to its Trim/ Feedback Node.
The value of this resistor typically determines the nominal output voltage value of the DC-DC
converter.Power 2 You: A Guide to Power Supply Management and Control
8-2 Margining and Trimming
Figure 8-1. Supplies are Margined by Changing the Resistor Connected to the Trim/FB Node
DC-DC converters usually require standard resistor values to set their output voltage to a standard value –
e.g., 3.3V, 2.5V, 1.5V. To change the output voltage by ±5% of their nominal operating voltage, designers
use either a potentiometer for each of the DC-DC converters or a series parallel combination of standard
resistor values. One has to manually implement the resistor change to all the boards that will be subject to
testing in an environmental chamber.
Some disadvantages of manually altering resistor values for margining:
• Increased Delay - finding resistor values that accurately alter the output voltage often require a series
and/or parallel combination of standard resistors that must be manually soldered. Different resistor
combinations for each of the supplies must be found. Sometimes the board failures in the environmental chamber could be due to bad solder joints caused by manual soldering. Even if a potentiometer is
used, the moisture in the environmental chamber creates contact problems that delay the margin test.
• Manually soldering a resistor for margining cannot be used for automated reliability testing.
• Due to accuracy requirements, manual methods cannot be used for margining the low core supply voltages of modern VLSIs and CPUs.
8.3 What is Trimming?
Modern circuit boards require multiple DC-DC converters with low voltages (1.2V or less) with high current capacity. A specification of 10A to 20A at such low voltages is not uncommon. In addition, ICs
require very tight output voltage regulation of approximately 1.5% or less to ensure that there is enough
headroom to meet the dynamic current requirements of the CPU/ASIC without violating the input voltage
specs.
Trimming is the process of accurately setting and maintaining the output voltage of a DC-DC converter
close to a pre-determined value across voltage and temperature. Margining is a special case of trimming.
Trimming also uses the same mechanism shown in Figure 8-1 to set a given voltage. However, to meet
accuracy requirements of 1.5% or better, DC-DC converters use very high accuracy (0.1% or better) trim
resistors to set the output voltage. In some cases, laser trimmed resistors and compensating resistors are
used to allow for converter to converter output voltage accuracy differences.
As can be seen, when the DC-DC converter is required to meet high accuracy demands, cost increases
significantly. In some cases, digital power converters are used to meet these high power and high current
demands. These DC-DC converters are more expensive, as they require ADCs, DACs and accurate voltage references.
DC-DC
Converter
Trim/ FB
V
OUT
R
Margined voltage
Note: Change R to increase or decrease the output nominal
voltage by +/-5%. Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-3
Typical Applications That Require Power Supply Trimming
Trimming is required for circuit boards using ICs that require low supply voltages (1.2V or lower) with
high current ratings (5A or more).
For example, a 1.2V DC-DC converter should guarantee a maximum of ±5% (±60mV) variation under all
of the following conditions:
• No-load to full-load average current variation
• Output voltage ripple
• Dynamic power demands by the IC during different average current levels
• Component tolerances during manufacturing
In general, to meet the voltage device spec under all of the above conditions safely, the DC-DC converter
requires an initial operating voltage accuracy of 2% or better. These high accuracy, low voltage supplies
are usually more expensive and require high precision resistors to set the voltage.
Alternatively, the accuracy of a conventional lower cost DC-DC converter can be improved by using an
external trimming mechanism. The next section describes trimming using the Lattice Power Manager II
IC.
8.4 Trimming and Margining – Principle of Operation
Figure 8-2 below shows a Lattice Power Manager II device implementing trimming and margining functions for an analog DC-DC converter.
Figure 8-2. Supplies are Margined by Changing the Resistor Connected to the Trim/FB Node
On the top portion of Figure 8-2 is a DC-DC converter supplying power to its load. The output voltage is
determined by the components used in its feedback circuitry. The Power Manager II device at the bottom
measures the voltage using the on-chip ADC though differential sense inputs. The Power Manager II can
increase or decrease the output voltage of the DC-DC converter by increasing or decreasing the voltage
or current applied to the DC-DC converter’s feedback node, using its on-chip DAC. For some DC-DC
converters, increasing the feedback node current or voltage reduces its output voltage.
PWM
Controller
Inductor &
Filters Switcher
Feedback
Any DC-DC Converter
ispPAC-POWR1220AT8/
ispPAC-POWR6AT6
Load
Differential Voltage Sense
I
2
C
2
Result: Voltage Error <1% At Load! (-40° to +85° C)
Set Point
+/-1
VIN
DAC
ADCPower 2 You: A Guide to Power Supply Management and Control
8-4 Margining and Trimming
A set point register in the Power Manager II holds the required voltage value at the load. Once every
580s the Power Manager II device measures the voltage at the load using its on-chip ADC. The digital
output of the ADC is compared against the set-point register contents. If the load voltage is higher, the
DAC contents are decremented, which in turn reduces the voltage applied to the feedback node of the
DC-DC converter. If the load voltage is lower, the DAC contents are incremented, applying higher voltage to the node. This is called the closed loop trim mechanism.
It is possible to break the closed loop trim and load the DAC register directly through the I2
C bus. This
method is used to implement margining. An external microprocessor directly loads a pre-selected DAC
value into the Power Manager II, which will result in changing the output voltage by, for example, ±5%.
The microprocessor can also measure the output voltage of the DC-DC converter using the Power Manager II’s ADC, and tweak the output voltage up and down as needed to implement closed loop margining.
In a circuit board, there typically are multiple types of supplies providing different supply voltages. These
individual supplies require different current levels to be injected into their feedback nodes. This in turn
requires a unique resistor network for each type of DC-DC converter to be connected between the Power
Manager II and the DC-DC converter feedback node.
The next section briefly describes the Power Manager II’s architecture blocks and then explains the
details of designing a resistor network connected between the DC-DC converter feedback node and the
Power Manager II DAC output.
Power Manager II TrimCell Architecture
The DAC in Figure 8-2 stores the DAC codes for nominal output voltage, as well as for margining up and
down. For example, to support margining (for example ±5%) and trimming of a low voltage set-point (for
example 1.2V 10mV), the three individual DAC values must be stored in different DAC registers. The
Power Manager II device supports six registers for each DAC. The block that includes the DAC and its
associated registers is called a TrimCell. Figure 8-3 is a TrimCell block diagram.Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-5
Figure 8-3. TrimCell Architecture in a Power Manager II Device
Six DAC registers are divided into four hardware addressable groups called Voltage Profiles. Of these six
DAC codes, four are stored in on-chip EEPROM memory. The two remaining registers are volatile. One
of the volatile registers can be loaded directly via the I2
C interface. The second register is controlled by
the closed loop trim circuit. Voltage Profiles 3, 2 and 1, when selected by either the external hardware
pins or internally by the PLD, load the corresponding codes stored in the EEPROM memory into the
DAC. With this feature one can margin each supply high or low using the on-chip PLD, or through the
hardware pins of the Power Manager II device. While operating in these profiles, the Power Manager II is
said to be operating in an open-loop; that is, the DAC register contents are static and are not adjusted during operation, depending on the actual DC-DC converter output voltage.
To support the controlling of output voltage to a very high degree of accuracy (Set-point voltage ±10mV),
the Profile 0 should be used. There are three modes of operation in Profile 0:
1. Open Loop operation with the DAC code stored in the E2
CMOS®
configuration memory. Operation in
this mode is similar to that of the profiles 1, 2 and 3.
2. Open Loop/ External Closed Loop operation – Load the I2
C DAC register via the I2
C bus. This mode
of operation is used by an external microcontroller to fine tune the output voltage, depending on the
DC-DC converter’s actual output voltage. This is called an external closed loop mode of operation.
3. Closed Loop Trim – This mode of operation is used to trim a given DC-DC converter output voltage
accurately. Tight control of the output voltage is maintained by the on-chip closed loop control circuitry. Closed loop circuitry gets activated once every 580s. It can also be programmed to be activated at a slower rate: 1.15ms, 9.2ms or 18.5ms. When activated, the on-chip closed loop control
circuitry measures the DC-DC converter output voltage and compares it to the value stored in the set
point register. Depending on the DC-DC converter’s output voltage excursion, the closed loop circuitry increments or decrements the DAC contents in a way that counters the output voltage excursion
Voltage
Profile 2
Voltage
Profile 1
Voltage
Profile 0
From Closed Loop
Trim Circuit
Voltage Profile 0
Mode Select
(E2CMOS)
Common Voltage
Profile Control
DAC Register 3
(E2CMOS)
Voltage
Profile 3
DAC Register 2
(E2CMOS)
DAC Register 1
(E2CMOS)
DAC Register 0
(E2CMOS)
DAC Register
(I2C)
Profile
Mux
11
8
10
01
00
DAC
TRIMx
Closed Loop
Trim Register
Mode
Mux
8
8
8
8 2
8
8
8Power 2 You: A Guide to Power Supply Management and Control
8-6 Margining and Trimming
direction. The ispPAC-POWR1220AT8 device supports eight TrimCells in its TrimBlock, as shown in
Figure 8-4.
Power Manager II Integrates Multiple TrimCells
The ispPAC-POWR1220AT8 device supports eight TrimCells in its TrimBlock, as shown in Figure 8-4.
Each of the TrimCells can be programmed independently to control a DC-DC converter. The Voltage profile selection is common to all TrimCells and is controlled by either the hardware control pins (VPS [0:1])
or through the on-chip PLD.
Figure 8-4. The ispPAC-POWR1220AT8 Device Provides Eight TrimCells in its Trim Block
When the Voltage proPOWR file is set to, for example, 3 in Figure 8-4 shown above, the DC-DC1 converter outputs 0.95V (5% below the normal operating voltage of 1V), while the DC-DC 2 converter outputs 1.14V (5% below the 1.2V nominal), and so on.
When the voltage profile is set to, for example, 1, the DC-DC1 converter outputs 1V+5%. The DC-DC2
converter outputs 1.2V + 5%. This method is used to implement margining.
TrimCell
#1
(Closed Loop)
TrimCell
#2
(I2
C Update)
TrimCell
#3
(I2
C Update)
TrimCell
#8
(Register 0)
DC-DC 1
Trim-in
VIN
0 123
1V (CLT) 1.05V 0.97V 0.95V
DC-DC Output Voltage
Controlled by Profiles
DC-DC 2
DC-DC 3 Digital Closed Loop
and I
2
C Interface Control
ispPAC-POWR1220AT8
Margin/Trim Block
Trim 1
Trim 2
Trim 3
Trim 8
Trim-in
Trim-in
R1*
R2*
R3*
R8*
*Indicates resistor network
PLD Control Signals
PLD_CLT_EN,
PLD_VPS[0:1]
Input From ADC Mux
Read – 10-bit ADC Code
VPS[0:1]
VIN
VIN
DC-DC 8
Trim-in
VIN
1.2V (I2
C) 1.26V 1.16V 1.14V
1.5V (I2
C) 1.57V 1.45V 1.42V
3.3V (EE) 3.46V 3.20V 3.13VPower 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-7
When VPS [0:1] = 0 the DC-DC 1 converter outputs 1V and the DC-DC2 converter outputs 1.2V. However, TrimCell 0 maintains the DC-DC converter output voltage using the on-chip closed loop control
mechanism, while TrimCell1 uses an external microcontroller to maintain the voltage at 1.2V.
Closed Loop Trim - Mode Operation of TrimCell
Figure 8-5 shows the connection between the TrimCell and the DC-DC converter when configured to
operate in closed loop trim mode. The resistor between the Trim pin and the DC-DC converter Trim_in
pin converts the voltage applied by the DAC into a current added to the Trim summing node of the DCDC converter. The ADC is used to measure the DC-DC converter voltage. The three-state comparator
compares the ADC measured value with the set-point and the output increments, decrements or holds the
content of the closed loop trim register as is.
Figure 8-5. The ispPAC-POWR1220AT8 Device Closed Loop Trimming Mechanism
When the Power Manager II device is powered on, the DAC output voltage starts at the bi-polar zero
value. The bipolar zero voltage is determined by its offset voltage setting 0.6V, 0.8V, 1V and 1.25V. This
results in starting the DC-DC converter output voltage very close to its nominal value. Using this value,
all supplies are sequenced. Once the supply sequencing is complete, the closed loop trimming process is
activated.
The closed loop trimming circuitry operates on each of the TrimCells in a cycle. The closed loop trimming cycle can be activated using a programmable timer and can be set to 580s, 1.15ms, 9.2ms or
18.5ms. The closed loop trim circuitry consists of the ADC, three state comparator, set point register,
channel polarity controller, the control loop register increment/ decrement control and the DAC. During a
trim cycle, the closed loop trim circuitry performs the following functions for each of the TrimCells:
1. Measures the voltage of the DC-DC converter differentially through the ADC.
2. Compares the output of the ADC with the set point register. If the polarity is set as positive, the following are the effects of the comparison:
a. If the DC-DC converter voltage is higher than set point, decrement the contents of the closed loop
trim register.
Three-State
Digital
Compare
(+1/0/-1)
Setpoint
(E2
CMOS)
Channel
Polarity
(E2
CMOS)
E
2
CMOS Registers
TRIMx
VMONx
TRIMIN
DC-DC
Converter
VOUT
GND
ispPAC-POWR1220AT8
DAC Register 3
DAC Register 2
Closed Loop
Trim Register
DAC
TrimCell
DAC Register 1
DAC Register 0
DAC Register I2
C
Profile 0 Mode
Control (E2
CMOS)
Profile Control
(Pins/ PLD)
Update
Rate
Control
ADC
+/-1Power 2 You: A Guide to Power Supply Management and Control
8-8 Margining and Trimming
b. If the DC-DC converter voltage value is less than the set point register value, the closed loop trim
register contents are incremented.
c. If the ADC value is the same as that of the set point register, maintain the closed loop trim register
value.
If the polarity set is negative, the incrementing and decrementing register in steps a. and b. above are
reversed.
Closed loop trimming ensures that the voltage at the load is accurate within ±10mV from the set-point
value This error includes the maximum ADC measurement steady state error and the DAC quantization
error. According to the datasheet, the maximum ADC error (including its gain, offset, INL and DNL
across process, voltage and temperature) is 8mV.
The error from the DAC is due to its step size. This error is calculated as follows:
Usually the resistors between the DAC and the DC-DC converters are calculated such that the full scale
(128) swing of DAC results in swinging the output voltage of the DC-DC converter by 5%. This means
that each step of the DAC code results in an output voltage step of 5% / 128 ~ 0.05%. For a 3.3V supply,
the voltage variation due to a single step of DAC code results in changing the output voltage by
3.3*0.05/100*128 = 130V (approximately). In effect the major error component is the ADC error.
Errors due to DC-DC converter components, DC-DC converter accuracy, etc. are compensated for by the
closed loop trim mechanism, which maintains the output voltage accurately.
Closed Loop Trim and Closed Loop Margining Using a Microcontroller
Figure 8-6 shows the configuration used for closed loop trimming with a microcontroller. Here the microcontroller measures the DC-DC converter output voltage periodically, using the on-chip ADC through the
I
2
C bus. The microcontroller then algorithmically calculates the new DAC value depending on the DCDC converter voltage and loads the new DAC code through the I2
C interface.
The microcontroller-based margining is implemented entirely through the I2
C bus and uses profile 0 in
the Power Manager II. To implement closed loop margining, the microcontroller loads the starting DAC
code into the DAC register via I2
C and waits for the ADC voltage to stabilize. Depending on the stabilized voltage value, the microcontroller increments or decrements the DAC code. This method enables
setting and controlling the margined voltage accurately.Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-9
Figure 8-6. Closed Loop Trimming and Margining Using a Microcontroller
Interfacing Power Manager II with a DC-DC converter
Interfacing a DC-DC converter with the DAC requires that the DC-DC converter output voltage is at its
nominal value when the DAC register value is at its bipolar-zero voltage in Profile 0. It also requires that
the DAC maximum or minimum code results in swinging the DC-DC converter voltage to its margin
voltage value through appropriate current injection into the feedback node.
The resistor values also should take into consideration the type of feedback node arrangements used in
DC-DC converters, their internal reference type (current/ voltage), and type of feedback. To map all types
of DC-DC converter variables to the DAC output voltage swing, a number of resistor network topologies,
shown in Figure 8-7 through Figure 8-11 are required.
Figure 8-7 shows a typical resistor network between a Power Manager II device and a DC-DC converter.
As discussed earlier, the ispPAC-POWR1220AT8 device can monitor and trim up to eight DC-DC converters individually. The trim circuit of the Power Manager interfaces to different types of DC-DC converters through a resistor network, as shown in Figure 8-7.
The resistors R1
and , R2
and R3
determine the starting voltage of the DC-DC converter. This is equivalent to connecting a resistor to ground from the trim pin. The values of these resistors are selected such
that the voltage at the node between R1
and R3
, is equal to the DAC voltage at power up.
The values of these three resistors are calculated by the PAC-Designer software using the following
inputs:
1. Type of DC-DC Converter. There are four types of DC-DC converters:
a. Fixed voltage
b. Output voltage programmable through a resistor to ground connected to its trim input
c Output voltage programmable through a resistor to the output voltage terminal
d. Output voltage is determined by two resistors connected from its feedback node output voltage terminal and to ground
Microcontroller
E
2
CMOS Registers
I
2
C Bus
TRIMx
VMONx
TRIMIN
DC-DC
Converter
VOUT
GND
POWR1220AT8/POWR6AT6
DAC Register 3
DAC Register 2
Closed Loop
Trim Register
DAC
Trim Cell
DAC Register 1
DAC Register 0
DAC Register I2
C
Profile 0 Mode
Control (E2
CMOS)
Profile Control
(Pins/ PLD)
ADCPower 2 You: A Guide to Power Supply Management and Control
8-10 Margining and Trimming
2. Nominal operating voltage
3. Margining voltage range in positive and negative directions
Figure 8-7. Resistor Network Topology #1 Connecting a TrimCell to a DC-DC Converter
Not all DC-DC converter types require the same resistor network of R1
, R2
and R3
as that shown in
Figure 8-7. The other possible types of resistor networks generated by the PAC-Designer software are
shown in Figure 8-8, Figure 8-9, Figure 8-10 and Figure 8-11.
Figure 8-8. Resistor Network Topology #2
Figure 8-9. Resistor Network Topology #3
Figure 8-10. Resistor Network Topology #4
ispPAC-POWR1220AT8
DC-DC Converter
Trim
V
OUT
V
OUT
R3
R1
R2
VIN
TrimCell
#N DAC
V= output
voltage of
DAC at
bipolar zero
ispPACPOWR1220AT8
DC-DC Converter
Trim
V
OUT
R3
R1
R2
DAC
ispPACPOWR1220AT8
DC-DC Converter
R1
R3
DAC
R2
ispPACPOWR1220AT8
DC-DC Converter
R1
R3
DAC
R2
Trim
V
OUTPower 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-11
Figure 8-11. Resistor Network Topology #5
Designing Trimming and Margining Networks using PAC-Designer Software
Determining the required resistor topology involves finding a solution for a number of nodal equations
and an understanding of the error amplifier architecture of the DC-DC converter. In addition, the design
can be iterated until the solution yields standard resistor values.
The PAC-Designer software automates the process of determining the resistor topology while using standard resistors in the resistor network. Calculating the resistor values shown in Figure 8-7 through
Figure 8-11 using the PAC-Designer software is a two-step process:
1. Create a DC-DC Converter Library using the DC-DC converter’s feedback and trim section characteristics – This uses a few parameters commonly specified in a DC-DC converter datasheet.
2. Associate a DC-DC converter to a TrimCell and calculate the resistors for a given output trim and
margin voltage specification for that DC-DC converter.
Creating a DC-DC Converter Library Entry
1. To create a DC-DC converter library entry, open the ispPAC-POWR1220AT8 design and click on the
button ‘DC-DC’ as shown in Figure 8-12 to open the DC-DC Model Selection menu. Click the
button, enter the name of the DC-DC module (example - Murata_1V2_POL) and click on
to open “Select the DC-DC Converter Type” dialog box.
ispPACPOWR1220AT8
DC-DC Converter
R1
DACPower 2 You: A Guide to Power Supply Management and Control
8-12 Margining and Trimming
Figure 8-12. Adding a DC-DC Converter into the Library
2. The “Select the DC-DC Converter Type” dialog box shows four types of DC-DC converters:
a. DC-DC Converter with Trim-up & Trim-down – This DC-DC converter usually is available as a
module with a fixed voltage. These supplies can be margined up and down by connecting a resistor
to GND or to VOUT
b. DC-DC Converter with Programmable Output Voltage – The output voltage of these DC-DC
Converters is set by connecting a resistor from trim pin to ground. The value of the resistor determines the output voltage.
c Programmable DC-DC Converter with Rtrim connected to VOUT – The output voltage of
these DC-DC Converters is set by connecting a resistor from its trim pin to its Vout terminal. The
value of the resistor determines the output voltage.
d. The Discrete Implementation – Represents a class of DC-DC converters whose output voltage is
determined by two resistors: one between the Vout terminal to the feedback node and the second
between the feedback node and the ground.Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-13
Figure 8-13. Selecting the Type of DC-DC Converter
Refer to the DC-DC converter datasheet to select the type of DC-DC converter and click on the
button.
3. This section describes configuration for each type of DC-DC converter.
Fixed voltage – DC-DC Converter with Trim Up and Down Supply
This type of DC-DC converter is usually a module and is designed to provide a fixed voltage. The following message box (Figure 8-14) is used to create the library entry.Power 2 You: A Guide to Power Supply Management and Control
8-14 Margining and Trimming
Figure 8-14. Creating the Library Element for a Fixed Voltage DC-DC Converter
These supplies have a trim pin. This pin is used to margin the supply up by 5- 10% or margin the supply
down by 5-10%.
Nominal output voltage – This is the normal operating voltage of the DC-DC converter when its trim pin
is open. This is its normal operating state.
Next, there are two fields under the headings “Example 1 R to GND”, “Example 2 R to GND” and
“Example 3 R to Vout.” Examples 1 and 2 are conditions used to generate a margin voltage that is different than the nominal voltage. Different target voltages will require different resistor values. These values
are provided in the DC-DC converter datasheet, usually in a table format. Some datasheets provide a formula to calculate these resistors. Enter the values of the target output voltage and the values of the target
resistors that are connected between Trim and GND pins into the required fields.Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-15
The third column requires the value of the resistor to be connected between the trim pin and the Vout pin
of the DC-DC to achieve the corresponding output voltage. Input the resistor value and voltage values in
the required fields. Again, these values are found in the DC-DC converter datasheet.
After entering these values, enter the necessary comments that describe the use of the DC-DC converter
and click on the button followed by the key. In this case the software creates a library
element called “Murtata_1V2_POL.
Programmable Voltage with Resistor Connected from Trim pin to Gnd
Figure 8-15 shows the dialog box that appears when the programmable voltage DC-DC converter is
selected.
Figure 8-15. Reference Voltage/ Current for the DC-DC Converter
All DC-DC converters use some type of reference voltage or current to set the output voltage. The value
of the reference voltage ‘Vref’ is shown either in the specifications section of the datasheet or in its output voltage calculation formula. Sometimes, the datasheet shows the architecture of the error amplifier
with the value of Vref. Power 2 You: A Guide to Power Supply Management and Control
8-16 Margining and Trimming
In some cases, the DC-DC converters use current reference instead of a voltage reference. The current
reference value is accompanied by a parallel resistor. Again, some DC-DC converter datasheets show the
equivalent circuit in the error amplifier section. After entering the Vref or Iref & Rref values, click on
to get the dialog box shown in Figure 8-16.
Figure 8-16. Configuring the Programmable Voltage DC-DC Converter Library Entry
The output voltage of these types of DC-DC converters is determined by the resistor connected from their
Trim pin to Gnd.
To complete this dialog box, refer to the DC-DC converter datasheet for a table that maps the resistor values connected between the trim pin and GND to the desired output voltage values. In some cases, the DCDC datasheet provides a formula for calculating the output voltage for a given trim resistor.Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-17
The first field is the output voltage of the DC-DC converter when the trim pin is open. This usually will
be one of the entries in the table, or is calculated using a formula in the datasheet. The two examples columns are also completed using the same table or the formula in the datasheet of the DC-DC converter.
Note: one of the voltage values selected should be the maximum output voltage and the second voltage
value should correspond to the minimum voltage. These voltage values need not be the actual output voltage used in the circuit board.
Finally, enter the DC-DC converter model name (for example, Murata_OKYT3_D12) and save the file.
Programmable Voltage with Resistor Connected from Trim Pin to Vout
Figure 8-17 shows the dialog box that appears when the programmable voltage DC-DC converter is
selected.
Figure 8-17. Reference Voltage/ Current for the DC-DC Converter
All DC-DC converters use some form of reference voltage or current to set the output voltage. The value
of the reference voltage ‘Vref’ is shown either in the specifications section of the datasheet or in its output voltage calculation formula. Sometimes the datasheet shows the architecture of the error amplifier
with the value of Vref.
In some cases, the DC-DC converters use current reference instead of voltage reference. The current reference value is accompanied by a parallel resistor. Again, some DC-DC converter datasheets show the
equivalent circuit in the error amplifier section. After entering the Vref or Iref & Rref values, click on
to get the dialog box shown in Figure 8-18. Power 2 You: A Guide to Power Supply Management and Control
8-18 Margining and Trimming
Figure 8-18. Configuring the Programmable Voltage DC-DC Converter Library Entry
The output voltage of these types of DC-DC converters is determined by the resistor connected from their
Trim pin to Gnd. To complete this dialog box, refer to the DC-DC converter datasheet for a table that
maps the output voltage to the resistor values connected between the trim pin and Vout. In some cases,
the DC-DC datasheet provides a formula for calculating the output voltage for a given trim resistor.
The first field is the output voltage of the DC-DC converter when the trim pin is open. This usually will
be one of the entries in the table, or is calculated using a formula in the datasheet. The two examples columns are also completed using the same table or the formula in the datasheet of the DC-DC converter.
Note: one of the voltage values selected should be the maximum output voltage and the second voltage
value should be minimum voltage. These voltage values need not be the actual output voltage used in the
circuit board.
Finally, enter the DC-DC converter model name (for example, POL_XYZ) and save the file.Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-19
Creating a Library Entry for a Discrete DC-DC Converter
These types of DC-DC converters are common when they are realized using switcher ICs, switching and
filter elements. The output voltage is programmed by connecting two resistors, Rfb and Rin. The output
voltage of the DC-DC converter is calculated using the formula:
When the DC-DC converter used is of this type, the dialog box, shown in Figure 8-19, is used to create
the library entry.
The dialog box is completed by entering the Rfb and Rin values calculated for a given output voltage, and
Vref, which is found in the datasheet.
Note: the number of resistors used for controlling these types of DC-DC converters can be minimized by
using the actual voltage that is used on the board.
Figure 8-19. Creating a Library Entry for a Discrete DC-DC Converter
4. Once the library entry is created, the next step is to associate the DC-DC converter from the library to
the Trim pin. This is done using the following procedure, shown in Figure 8-20.
a. Start with the ispPAC-POWR1220AT8 schematic
b. Double Click on the Margin/ Trim block
Vout = Rfb*Vref / Rin. (Vref is the DC-DC converter reference voltage)Power 2 You: A Guide to Power Supply Management and Control
8-20 Margining and Trimming
c Double Click on the TrimCell of interest (for example, TrimCell 1)
d. The dialog box shown in Figure 8-21 is used to design the resistor network
Figure 8-20. Accessing the Margin and Trim Dialog Box
Designing the resistor network for a DC-DC converter connected to a TrimCell.
The following dialog box opens after double clicking a TrimCell in the bottom schematic in Figure 8-21.Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-21
Figure 8-21. Calculating the Resistor Network for a Given DC-DC Converter
Schematic Net Name – The actual name of the pin in the schematic
DC-DC converter – Select the appropriate DC-DC converter from the library by clicking the import DCDC menu. In this example, Murata_OKY3_D12 is selected.
Profile 0 mode – The pull down menu selects the operating mode of the TrimCell : Closed loop trim,
Trim using I2
C interface with an external microcontroller and E2
CMOS value (open loop trimming), is
selected
Voltage Profile 0 – The nominal operating voltage of the DC-DC converter.
Voltage Profile 1 – One of the margining profiles: it can be margin-up or margin- low value.
Voltage Profile 2 – The other margin profile. Again, this can be margin-down or margin-up voltage
value.
Voltage Profile 3 – An additional profile provided for convenience. In some cases, this can be used for
additional margin testing.
After entering the required voltage values, click on . The software calculates the resistors to
be placed between the TrimCell output and the DC-DC converter trim pin. Calculated DAC code values Power 2 You: A Guide to Power Supply Management and Control
8-22 Margining and Trimming
along with the DAC currents for each of the profiles are also shown. When the OK button is clicked,
these values are stored into the source file.
The button opens the following dialog box (Figure 8-22) that can be used to fine tune the calculated resistor values.
Figure 8-22. Optimizing Resistor Values
EIA resistor standard – limits the resistor selection to EIA 12, EIA24, EIA48, EIA96, EIA192. It also
provides a method to calculate the exact resistor values. The selection of this option depends on design
requirements
Maximum DAC code range – used to provide additional headroom in the DAC code for maximum voltage variation. This is to account for the errors in resistor values and the DC-DC converter inaccuracies.
Maximum supply adjustment range – this is the maximum margin voltage range with respect to the
nominal value that is specified on profile 0. If the design requires margining of 10%, this value is set to
10%.
Attenuation crossover voltage – the maximum input voltage for the ADC is 2.048V. If this ADC is used
for measuring voltage higher than the Attenuation Crossover Voltage, the on-chip 1:3 attenuator should
be turned on. This allows the maximum voltage input to the ADC to increase to 6.144V. This entry sets
the voltage at which the attenuator should be switched on.
Open External Resistor(s) Threshold – the maximum resistor value above which the resistor is treated
as an open circuit - The trim and margin routine calculates up to three resistors and the associated topology as shown in Figure 8-7, Figure 8-8, Figure 8-9, Figure 8-10 and Figure 8-11. This field can be used
to force the algorithm to minimize the number of resistors to the equivalent circuit shown by Figure 8-11.
To do that, first calculate the resistors using the default values. Change the Open External Resistor(s)
Threshold field to a value slightly higher than the series resistor value and click on the button. The
software automatically calculates the new resistors and the associated DAC values.
Vbpz Selection – usually it is best left as auto. In some cases, by forcing the Vbpz values to one of the
other voltages (0.6V, 0.8V, 1V or 1.25V), the number of resistors can be reduced.Power 2 You: A Guide to Power Supply Management and Control
Margining and Trimming
Margining and Trimming 8-23
After calculating the resistor values for all TrimCells, the software automatically saves all the values in to
the “XXX.PAC” file.
To generate a report file of all resistors connected to all TrimCells the following procedure is followed.
Click on Files> Export and the following dialog box (Figure 8-23) opens.
Figure 8-23. Generating a Report File for Margin and Trim
Under “Export What,” select Margin/ Trim to a file selected by using the Browse button, and click OK.
The output text file format is as shown as follows:
MarginTrimCell
Idx0
TrimCellNumber1
TargetVoutSP11.200
TargetVoutSP21.260
TargetVoutSP31.140
TargetVoutSP41.200
RealizedVoutSP11.198
RealizedVoutSP21.256
RealizedVoutSP31.140
RealizedVoutSP41.198
VdacCodeSP12.000
VdacCodeSP2-6.000
VdacCodeSP310.000
VdacCodeSP42.000
Vref0.752
Rbuffer2561546.920
Rfb14467007.127
Rin1000000000.000Power 2 You: A Guide to Power Supply Management and Control
8-24 Margining and Trimming
Invert1
IsProgrammable1
IsModule1
IsRtGnd1
Rseries2400000.000
Rpdn110000000.000
Rpup210000000.000
Rpdn210000000.000
Rpup110000000.000
BPZVoltage0.600
BrickNameMurata_OKYT3-D12.xml
BrickFilename
TargetVdacCodesMax110
EIAStdIdx1
LooseEIAStdIdx1
AttenuationCrossoverVoltage1.900
MaxDeltaVoutPercent5.000000
RpdnOption0
Ropen10000000.000000000000000
BPZSel0.000000000001056
ResistorComputationAlgorithm1
MarginTrimCell_endCHAPTER
9
9-1
Design Tools for Power Manager II
9.1 PAC-Designer: Power Management Design Tool
One major reason for the popularity among system engineers of programmable devices like the
Power Manager II family is the flexibility of the hardware solution. One silicon device can serve
in a variety of applications or integrate multiple board power management functions. While the
term “programmable” usually conjures images of a software engineer writing ‘C’ or assembly
language for an embedded microcontroller, programmable devices like the Power Manager II are
designed using a class of Electronic Design Automation (EDA) software that is easy to learn for
a hardware engineer with expertise in the analog, system or digital electronics disciplines. Rather
than a software engineer writing firmware, the hardware designer will model the design using a
hardware design language (HDL) or graphical tools like a schematic or waveform editor.
To make designing with the Power Manager II device as easy as possible for the engineer with a
power circuit design background, Lattice provides a free EDA tool called PAC-Designer*. In the
PAC-Designer tool, circuit designs are entered graphically and then verified, all within the software environment. In the example below, the PAC-Designer schematic window provides access
to all configurable elements of an ispPAC-POWR1014A device via its graphical user interface.
All analog input and output pins are represented. Static or non-configurable pins such as power,
ground and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, configurations can be saved, simulated and downloaded to devices.
Programmable hardware with a software design tool provides a more flexible solution for engineering and a cost-cutting measure for component procurement departments. Programmability is
attractive from an economic standpoint to component engineers and procurement personnel who
wish to reduce the number of discrete solutions and vendors that they must qualify, inventory,
and manage. It’s for these economic benefits that procurement departments will heavily influence the preferred part inventory of electronic components.
This chapter describes how PAC-Designer software and development kits are applied to solve
the power management and control scenarios described in earlier chapters of Power 2 You.
* This document refers to PAC-Designer version 5.3 or later.Power 2 You: A Guide to Power Supply Management and Control
9-2 Design Tools for Power Manager
Benefits of Software-Driven Programmable Hardware Design
Power management and control solutions traditionally have been implemented with discrete analog and
mixed-signal ICs. Browse the component catalog of any popular vendor of voltage supervisor or watchdog timer ICs and you’ll quickly see the hundreds of variations available to satisfy a range of accuracy,
operating conditions and capacity. Further, depending on the degree of functional integration required,
even more product variations are available. The Power Manager II technology is disruptive due to it’s
versatility, enabled through programmability. In the same way the TTL discrete logic ICs of the 1970s
have been almost entirely integrated by modern CPLDs and FPGAs, Power Manager II integrates multiple discrete analog ICs and is flexible enough to be applied across most power management configurations.
Benefits of software-driven programmable hardware design include:
• Reduce cost by reducing the number of Power Manager II components – Multiple power management
functions can be integrated into a single power management device. The integrated solution can also be
customized to meet board-specific sense and control interface requirements.
• Reduced risk of board re-spins and faster time to market – New designs or changing board requirements can be handled by an updated program for the Power Manager II. HDL-based designs are flexible to meet changing functional requirements.
• Increased likelihood of first-time success and reduced time to market - Functions and performance can
be modeled by a software program and the model can be tested fully using simulation methods
Advantages of Power Manager II over Microcontroller Firmware-Based Solutions
One of the alternative approaches to a flexible power management solution is a microcontroller with
firmware. Some of the major drawbacks of this approach are:
• Reduced reliability due to slow response to power faults: Power monitoring is controlled by hardwaregenerated interrupts, which occur once in 5 to 10ms. This determines the response time of the power
management function, which is too slow to prevent faults such as Flash memory corruption.
• Increased time to market due to limited fault coverage of the power management algorithm: A major
advantage of HDL-based designs over firmware-based designs is that the HDL-based designs can be
simulated fully on a computer rather than a testing circuit board with limited fault coverage. The types
of faults that can be created on a circuit board are limited because of secondary fault conditions due to
other components on the circuit board that can interfere with the power management algorithm.
• As a result, any changes to software require extensive board-level regression tests that are costly and
time consuming. Consequently, changes to firmware are avoided, reducing its flexibility.Power 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-3
9.2 PAC-Designer Overview
Table 9-1 provides an overview of the major features of PAC-Designer software.
Selecting the Power Manager II Device from a Design Specification
The first step in a power management and control design is to determine how many functions can be integrated into a Power Manager II device. Here are some of the key considerations (Refer to Figure 9-
1“PAC-Designer Software - ispPAC-POWR1014A” on page 9-7 for a brief description of these functions):
• Primary Power Management
– Hot-swap, redundant power feed management, external power feed
– Input voltage – Positive/ negative, need for isolation
• Secondary power management functions
– Main secondary rail(s)
– Number of DC/DC converters that will be sequenced, supervised.
– Number of DC/DC converters that will be margined/trimmed
Table 9-1. Design Tools Overview
Design Entry Tools Purpose
Power Manager II Schematic Navigate and access the configuration of Power Manager II functional blocks such as:
• Digital I/O buffer configuration
• Analog input comparators
• High-voltage output drivers
• Timer/oscillator settings
• Margin and trim cell settings
• Sequence control and supervisory logic
LogiBuilder LogiBuilder is used to design the embedded digital functions of the
Power Manager II. Logic can be captured as a sequence of events
described in a high-level state machine like language or as traditional Boolean equations.
LogiBuilder provides a Sequence Controller window that allows
you to create control sequences and define logic functions and a
Supervisory Equation window to enter combinatorial or registered
logic independent of sequence controller logic.
DC-DC Library Builder The Library Builder is used to define the voltage adjustment characteristics of DC-DC converters and voltage regulators. A detailed
description of trimming and margining software GUI is provided in
the ‘Margining and Trimming,’ Chapter 7.
Simulation Tools Purpose
HDL Export The HDL writer included with PAC-Designer exports an industry
standard Verilog HDL or VHDL model of the digital logic and
timer/counter of the Power Manager II design. HDL models can be
executed with any popular third party simulator such as Aldec’s
Active-HDL program.
Waveform Editor The Waveform Editor is a graphical application used to create and
edit waveforms for logic stimulus. Each waveform is given a userdefined name, and then edited to show transitions. The stimulus is
applied to the LogiBuilder - generated model and waveform results
are produced much like those of a traditional logic analyzer.
Lattice Logic Simulator PAC-Designer includes a logic simulator to verify logic produced
by the LogiBuilder tool.Power 2 You: A Guide to Power Supply Management and Control
9-4 Design Tools for Power Manager
– Number of reset signals that will be distributed on the board for microprocessor, DSP, ASIC, FPGA
devices.
– Number of external watchdog timers required for the system
Once the board power management functions are finalized, use Table 9-2 to select potential Power Manager II devices to integrate the power management functions.
Table 9-2. Power Manager II Vs Board Power Management Functions
Managing Supply Rails in a Circuit Board
ProcessorPMPOWR605
ispPACPOWR607
ispPACPOWR1014
ispPACPOWR1014A
ispPACPOWR1220AT8
Board Input (Primary) Supply Management
Hot-swap
-48V Hot-swap Controller (Payload - isolated)
X
+12 / 24V Hot-swap Controller X X X X
Power Feed To External Systems
-48V Supply Feed X
+12/24V Supply Feed X X X X
Redundant Supply Selection
-48V Supply OR'ing using MOSFET (Payload - isolated)
X
+12/24V Supply OR'ing using MOSFET X X X X
Payload (Secondary) Power Management
Supply Sequencing X X X X
Voltage Supervision X X X X X
Reset Generation X X X X X
Watchdog Timer X X X X X
Voltage Measurement Using ADC X X
Power Supply Voltage Trimming X
Power Supply Margining XPower 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-5
The next step is to identify the smallest Power Manager II device using the number of secondary power
supply rails as well as the functions in Table 9-3.
Power Manager II Design Example
The example considered in this section is a PCI-Express add-on card application. This example is used to
describe the procedure for integrating the power management design into a Power Manager II device.
The first step is to collect the power management design specifications for the PCI Express add-on card.
Table 9-4 summarizes the power management functions implemented in a PCI-Express add-on card:
Table 9-2 shows that these functions can be integrated into a ispPAC-POWR1014A or a ispPACPOWR1220AT8 device. However, using Table 9-3, the smallest Power Manager II device that can integrate all these functions is an ispPAC-POWR1014A. The next step is to start designing the Power Management algorithm using the information given in earlier chapters.
Table 9-3. Select the Smallest Power Manager II Device Using the Number of Rails
Number of rails <3 3 to 5 5 to 8 >8 Comments
Reset Generation ProcessorPMPOWR605
ispPACPOWR1014
ispPACPOWR1220AT8
Voltage Supervision ProcessorPMPOWR605
ispPACPOWR1014
ispPACPOWR1220AT8
Watchdog Timer ProcessorPMPOWR605
ispPACPOWR1014
ispPACPOWR1220AT8
Minimal sequencing
< 3 groups
ProcessorPMPOWR605
ispPACPOWR1014
ispPACPOWR1220AT8
Individual Supply
Sequencing Control
ProcessorPMPOWR605
ispPACPOWR607
ispPACPOWR1220AT8
ispPACPOWR1220AT8
Hot-swap controller -
48V
ispPAC-POWR607 ispPACPOWR607
ispPACPOWR607
ispPACPOWR607
Used on -48V
Rail
Hot-swap controller
+5 or 12 or 24V
ispPAC-POWR607 ispPACPOWR1014
ispPACPOWR1220AT8
ispPACPOWR1220AT8
I
2
C, ADC Measurement
ispPACPOWR1014A
ispPACPOWR1014A
ispPACPOWR1220AT8
ispPACPOWR1220AT8
Supply Margining/Trimming
ispPACPOWR6AT6
ispPACPOWR6AT6
ispPACPOWR1220AT8
ispPACPOWR1220AT8
Table 9-4. PCIe Board Power Management Specifications
Backplane voltage 12V
Hot-swap function required? Yes
Redundant supplies used? No
External power feed function required? No
Number of secondary rails 5
Secondary supply sequencing needed? Yes
Reset generation needed? Yes
Number of reset signals 2
Watchdog Timer required? Yes
Voltage and current measurement needed? YesPower 2 You: A Guide to Power Supply Management and Control
9-6 Design Tools for Power Manager
Design Flow
This section describes a typical user scenario using PAC-Designer software to design a power management algorithm.
The typical design flow to design with PAC-Designer software:
1. Create/Open a project.
2. Configure analog input signals.
3. Configure digital inputs.
4. Configure digital output pins.
5. Configure high-voltage output (HVOUT) pins (MOSFET driver outputs).
6. Configure timer values.
7. Configure an I2
C address.
8. Implement the power management algorithm using the LogiBuilder tool.
9. Simulate the design and iterate steps 2 through 6.
10.Download the design into a Power Manager II device and verify design.
9.3 Example Design Resources
The fastest way to a solution for your particular application often is to modify an existing example. Lattice provides three types of example designs:
• Project examples installed with PAC-Designer software -
To open a project example from PAC-Designer, choose File > Design Example. A dialog listing of
each example with a brief description is provided. Details of each example can be found in
\Examples\Design Examples.ppt.
• Power Manager II Reference Designs at the Lattice website -
Each Lattice Reference Design has a web page that provides a brief overview of that function and available options. Complete details can be found in the documentation for that particular design. The documentation, along with the actual source code, can be downloaded from the web pages.
Link to Lattice Reference Designs:
http://www.latticesemi.com/products/intellectualproperty/aboutreferencedesigns.cfm
• Demonstration designs included with Power Manager II Development Kits -
Demo designs are typically preprogrammed into Power Manager II evaluation boards and are designed
to showcase key features and benefits of the hardware. Other demonstrations and interface utilities are
available at the respective Development Kit web page. Link to Lattice Development Kits:
http://www.latticesemi.com/products/developmenthardware/developmentkits/index.cfmPower 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-7
9.4 Designing PCI-Express Add-on Card Power
Management Using an ispPAC-POWR1014A Device
1. Open/Create a New Design
This section uses the design example ispPAC-POWR1014A-3_PCIe_HS_Seq_Rd_Sup.PAC. The feature
list of this design is found on page 40 of the ‘Design Examples.PPT’ file found in the / Examples directory.
The circuit diagram of the implementation is shown on page 41 of the Design Examples.PPT file. Page
42 provides the algorithm for implementing 12V hot-swap, sequencing, supervision and reset generation
for this design. The next step is to implement the design in PAC-Designer software.
The PAC-Designer software provides the complete design source code. Start the PAC-Designer software.
Click on File > Design Examples and select the above mentioned design example file and click on
button.
The software opens the screen shown in Figure 9-1.
Figure 9-1. PAC-Designer Software - ispPAC-POWR1014A
2. Configuring Analog Input Signals
The next step is to configure the monitoring voltage thresholds. To do that, click on the Analog Inputs
block on the top right of the schematic. The software shows two programmable threshold comparators
with the associated window logic for each of the VMON inputs. In the ispPAC-POWR1014A device
there are 20 programmable threshold comparators.Power 2 You: A Guide to Power Supply Management and Control
9-8 Design Tools for Power Manager
Double click on any of the programmable threshold comparators to open the dialog box. This dialog box
shows the names of the voltage monitoring comparator outputs as well as the thresholds for each of the
comparators.
Figure 9-2. Configuring Voltage Monitoring Inputs of the ispPAC-POWR1014A Device
This dialog box is used to specify the current and voltage monitoring thresholds of both the hot-swap section and the secondary power management sections. This enables fault detection anywhere on the circuit
board. The fault threshold level can be changed by using the Trip point selection pull-down menu. For
each VMON input, its window monitoring mode and/or the associated glitch filter can also be enabled.
This dialog box can also be used to change the pin allocation of any of the VMON pins by using the ‘Pin
Name’ pull down menu.
Then, click on button, navigate back to the main screen and double click on any portion outside
the schematic.Power 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-9
3. Configure Digital Inputs
To configure the digital inputs, click on the digital inputs in the schematic shown in Figure 9-1. The software opens a screen with input signals with input buffers.
Click on any of the input buffers to open the dialog box shown in Figure 9-3.
Figure 9-3. Configure Digital Inputs
Enter the names of the digital input pins and also identify the source of the signal (I2
C/JTAG/ device pin)
and click OK.
This section specifies the interfacing of the Power Manager II with the active low signals on the backplane, such as PRST_N or PERST_N, as well as to the onboard active low signal using the
FPGA_Done_N.
This dialog box can also be used to change the pin allocation of any of the IN pins by using the Pin Name
pull down menu.
Navigate back to the main schematic by double clicking anywhere on the blank screen around the input
pin connection schematic.
4. Configure Digital Output Pins
From the main schematic in Figure 9-1, double click on the digital output to navigate to the next screen
with multiple output buffers. Double click on any of the output buffers to open the dialog box shown in
Figure 9-4.Power 2 You: A Guide to Power Supply Management and Control
9-10 Design Tools for Power Manager
Figure 9-4. Output Pin Configuration Dialog Box
This dialog box is used to configure the output pin name that is used in the algorithm. If a pin is used as
an I2
C output port expander, click on the appropriate radio button for that output.
This section identifies the signals that drive the DC-DC converter signals for sequencing on-board control signals such as PERST local, brown_out_N, etc.
This dialog box can also be used to change the pin allocation of the any of the OUT pins by using the ‘Pin
Name’ pull down menu.
Click on the OK button to navigate back to the screen with output buffers. Click anywhere on that screen.
5. Configure HVOUT Pins
These pins are used to drive the 12V hot-swap control MOSFET as well as the 3.3V soft start MOSFET.
To configure these signals, first click on the HVOUT outputs block on the screen. This opens an intermediate dialog box. Click on any of the boxes to open the dialog box shown in Figure 9-5.Power 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-11
Figure 9-5. MOSFET Configuration Dialog Box
This dialog box enables setting the MOSFET drive voltage as well as MOSFET turn-on/ turn-off ramp
rates.
Enter the names of the output signals used in the design to control the external charge pump for the 12V
MOSFET, as well as the MOSFET turn on for 3.3V.
Click OK and navigate back to the main screen using the same methods described previously.
6. Configure Timer Values
This design uses multiple hardware design timers for the external charge pump, for pulse stretching the
reset output, etc.
To configure the timer, double-click on the timer control box between the input and output control signals
to open an intermediate schematic. Click on the timer blocks to open the timer configuration dialog box
as shown in Figure 9-6.Power 2 You: A Guide to Power Supply Management and Control
9-12 Design Tools for Power Manager
Figure 9-6. Timer Configuration Dialog Box
This dialog box enables changing the Master/ Slave mode of operation when more than one Power Manager II device is used on the board. The time delay for each of the timers can also be set from this menu.
For example, the Timer 4 is used for external charge pump implementation that requires the HVOUT2
pin toggle with a cadence of 32s on and 8s off.
Once the timers are configured, click on the button to return to the main schematic.
7. Configure I2
C Addresses
The ispPAC-POWR1014A device can be used to measure the voltages and currents through the I2
C interface. For this, the ispPAC-POWR1014A should be assigned a unique address by clicking on the I2
C box
in the main schematic in Figure 9-1 to open the dialog box shown in Figure 9-7.Power 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-13
Figure 9-7. Setting the I2
C Address for the ispPAC-POWR1014A Device
The address is set by using the pull down menu on top of the dialog box shown in Figure 9-7. The output
control for each of the output pins as well as for the input pins can be set through this dialog box as well.
Click OK to navigate back to the main schematic.
8. Implementing the Power Management Algorithm Using the LogiBuilder Tool
The power management algorithm as described in the ‘Design Examples.PPT’ file is entered into the ispPAC-POWR1014A device in this section using the LogiBuilder utility.
Double click on the sequence control block of the main schematic to open the LogiBuilder screen, as
shown in Figure 9-8.
To facilitate understanding of the PCI-Express add-on card algorithm, the next section explains the LogiBuilder screen sections.
The LogiBuilder screen is divided into three sections:
The sequential execution sections – Enter a list of instructions listed in Table 9-5 to implement the
sequential execution part of the algorithm.
The exception conditions section – Enables a set of Boolean expressions which, when they become true,
interrupt the sequential execution flow. These exception conditions can only interrupt the steps which are
marked as interruptible. All other steps are not affected by the exception conditions.
The supervisory logic section – Enables the Boolean expressions direct control of some of the outputs
that are not controlled by the sequential execution portion of the algorithm.
The Boolean expressions in the exception condition as well as supervisory logic section operate in parallel to the instructions executed in the sequential execution section.Power 2 You: A Guide to Power Supply Management and Control
9-14 Design Tools for Power Manager
In the sequential execution section each step is divided into five columns:
• Step – This indicates the step number of a given instruction. This step number is used to branch to a
given step from a different location.
• Sequencer instruction – This is the instruction that is being executed by that step. Each step can take
one to several clock cycles. For example, a start timer instruction takes one clock cycle. A wait for
timer instruction stays in that step until the timer expires.
• Outputs – This lists all the outputs whose output values are changed at that step. The output state
changes after the first clock pulse while in that step.
• Interruptible – This flag enables the exception condition to interrupt the flow of execution. If the
interruptible flag is set to ‘no,’ the exception condition cannot alter the flow at that step.
• Comment – This column is used to enter the comment for that instruction.
Sequencer Instructions
There are six types of instructions used to implement the sequential execution portion of the power management algorithm. These instructions are listed in Table 9-5.
Table 9-5. Sequencer Instructions and Description
Instruction Type Instruction Sub Type Operands Description
Wait for
Wait for timer Selected Timer Starts a given timer, waits for it to expire and jumps to the next
sequential step. The timer is reset in the prior step.
Wait for Boolean
Expression
Waits for the Boolean expression to become true at that step.
When Boolean is true, it jumps to next sequential step.
Wait for with
Timer
Boolean
Expression &
Selected Timer
Waits for the Boolean expression to become true until the timer
expires at that step. When Boolean is true, it jumps to next
sequential step.
If the timer expired, it branches to a step indicated by the
instruction.
The timer is reset in the prior step.
IF-Then-Else
IF-Then-Else Boolean
Expression
Tests the Boolean expression:
If true the control branches to the location specified by the 'Then'
Branch. It is possible to alter selected outputs only during this
branch.
If false the control branches to the location specified by the 'Else'
Branch. It is possible to alter selected outputs only during this
branch.
IF-Then-Else with Timer
Boolean
Expression &
Selected Timer
Tests the Boolean expression:
If true the control branches to the location specified by the 'Then'
Branch. It is possible to alter selected outputs only during this
branch.
If the condition is not true, if the timer is expired, control
branches to the location specified by the 'On Timeout Go to
Sequencer Step' Branch.
If the condition is not true and the timer has not expired, the control branches to a location specified by the 'Else' branch.
Output
None
Specified outputs
Only the selected output condition is set to the state specified by
this instruction. Writing the same value to the output pin does
not result in glitches.
Go To
Go to Step Number Control Branches to the step indicated
Halt None Jumps to the same step and waits forever.Power 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-15
Exception conditions section
Each of the exception condition is divided into five columns:
Exception ID – The number of the exception condition: used by the compiler to point errors in that line
Boolean expression – this is the Boolean expression which, when it becomes true, will force the
sequence execution to jump to the step indicated by the exception handler step.
Outputs – Forces the outputs to the value set by the exception condition. Setting or resetting an output
results in the Boolean expression always controlling that output, and is independent of the sequence
instruction execution
Exception handler – This is the step number in the sequential execution section to which the control
jumps when the exception condition becomes true and the sequential execution section is executing a step
that has been flagged as an interruptible step.
Comments – This section is used for providing useful comments about that exception condition.
Supervisory equation section
The supervisory equation window is used to control outputs that are not controlled by the sequential execution section. The supervisory equation is divided into four columns.
Equation – This field indicates the supervisory equation number and is used by the compiler to flag
errors.
Supervisory Logic Equation – this column is where the Boolean logic condition and the associated output that is controlled by the equation is specified.
Macrocell Configuration – This column indicates the type of assignment in the supervisory logic equation for that output. It can be combinational, D-type, T-type, Asynchronous Reset or Asynchronous Preset.
Comment – provides additional information about the step for better understanding of that equation.
9. PCI-Express Example LogiBuilder Code
Figure 9-8 shows the implementation of the PCI-Express add-on card algorithm implemented using the
instructions shown above.
Start/ Stop Timer
Start Timer Selected Timer
Starts a given timer, does NOT wait for it to expire but simply
jumps to the next sequential step. The timer is reset in the prior
step. Instruction used along with the if-then-else with Timer
instruction.
Stop Timer Selected Timer Reset the selected timer.
NOP None None
No action taken during that step. Usually used in conjunction
with the wait for timer or start timer instructions. This enables the
code to jump to those instructions.
Table 9-5. Sequencer Instructions and Description (Continued)
Instruction Type Instruction Sub Type Operands DescriptionPower 2 You: A Guide to Power Supply Management and Control
9-16 Design Tools for Power Manager
Figure 9-8. LogiBuilder Screen to Implement the Power Management Algorithm
The algorithm implemented in this LogiBuilder screen is shown below:
Sequential Execution Section
1. Disable hot-swap operation.
2. Wait for 12V and 3.3V rails to stabilize.
3. Enable hot-swap operation on 12V, operate MOSFET in SOA
4. Wait for 12V output from the MOSFET to reach acceptable thresholds.
5. Start sequencing by enabling 3.3V and 1V supplies.
6. Wait for 3.3V and 1V supplies to reach acceptable voltage levels.
7. Enable 1.8V and soft start 3.3V from the connector.
8. Wait for all board supplies to reach acceptable voltage levels & FPGA to configure.
9. Activate early configuration start signal.
10.Release CPU_Reset signal after the stretch period.
11.Wait for voltage or current faults.Power 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-17
12.Activate Brown_Out signal and wait for interrupt process to complete.
13.Activate CPU_Reset signal and disable 1.8V supply & turn off the 3.3V MOSFET.
14.Wait for 2ms and disable 3.3V and 1V supplies.
15.Wait for 2ms and turn off 12V MOSFET.
Exception conditions section
1. If over current condition is detected jump to step 12.
2. Transfer input PERST state to PERST_Local signal.
Supervisory Equations section
1. Operate charge pump to drive the 12V control N-channel MOSFET by toggling the HS-
12V_MOSFET drive pin (8s Off, 32s On).
2. Limit 12V MOSFET operation in SOA until 12V rail reaches acceptable level, after that turn the
MOSFET on fully.
3. Turn-off 12V MOSFET when over current condition is detected.
The programmable features, shown below, of this design can be used to adapt the design across different
PCI-express add-on card configurations.
• SOA and over current levels.
• Customize the design to suit most MOSFETs.
• Initial contact de-bounce period programmable from 32s to 2 seconds.
• Short circuit timeout during start up programmable from 32s to 2 seconds.
• Reset pulse can be stretch duration programmable from 32s to 2 seconds.
• Each of the voltage monitoring thresholds are programmable from 0.67V to 5.8V.
This algorithm can be imported easily into an ispPAC-POWR1220AT8 device if the number of supplies
in the PCI-Express add-on card increases beyond five or other control functions need to be added.
10. Compiling the Design
After the design is entered, the next step is to compile the program. To compile the program click on
Tools> Compile the LogiBuilder Design
The program converts the code into ABEL (Advanced Boolean Expression Language) language and
compiles the ABEL language into a highly optimized equations netlist. These equations are then sent to
the Fitter program that fits the design into the CPLD of the Power Manager II.
11. Simulating Control and Supervisory Logic
When the primary supply rails for a circuit board are energized how will the Power Manager II respond
and sequence the various DC-DC converters and distribute the reset signals? If the firmware of a microcontroller hangs and fails to reset the watchdog timers you have defined, will the WDT assert an interrupt
the way you expect? These are the types of scenarios you’d like to model before you commit your design Power 2 You: A Guide to Power Supply Management and Control
9-18 Design Tools for Power Manager
to hardware. To help, PAC-Designer software can extract a model of your digital and timer logic to any
popular HDL simulator.
From PAC-Designer, the optimized equations produced by LogiBuilder can also be exported into VHDL
or VerilogHDL languages. These files can then be used for simulation. To export an HDL file, choose
File > Export. The Export dialog, shown in Figure 9-9, appears. From the Export What list, choose
VHDL File or Verilog File.
Figure 9-9. Dialog Box to Export the Design in Verilog for Simulation
The exported Verilog source file shown in Figure 9-10 can be tested fully using any of the popular HDL
simulators such as Aldec’s Active-HDL.Power 2 You: A Guide to Power Supply Management and Control
Design Tools for Power Manager
Design Tools for Power Manager 9-19
Figure 9-10. Exported Verilog Source FilePower 2 You: A Guide to Power Supply Management and Control
9-20 Design Tools for Power Manager
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Design Tools for Power Manager
Design Tools for Power Manager 9-21
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Design Tools for Power Manager
Design Tools for Power Manager 9-22
This page intentionally left blank.latticesemi.com/power2you
Order #: B0041
About the Author
Srirama (“Shyam”) Chandra is a widely-published author and
recognized authority on power management. He is the Product
Marketing Manager for programmable mixed signal products at
Lattice Semiconductor Corporation.
Prior to joining Lattice, Shyam worked for Vantis and AMD in sales
and applications and previously was a telecom design engineer with
Indian Telephone Industries. Shyam received his Masters degree
in Electrical Engineering from the Indian Institute of Technology,
Madras.
Shyam can be contacted at: power2you@latticesemi.com
GAL20V8
High Performance E2
CMOS PLD
Generic Array Logic™
1
2 28
I
I/CLK
NC
I
I
I
I
I
I
NC NC
NC
GND
I
I
I/OE
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
Vcc
I
I/O/Q
4
5
7
9
11
12 14 16 18
19
21
23
25
26
PLCC
1
12 13
I/CLK 24
I
I
I
I
I
I
I
I
I
I
GND
Vcc
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
6
18
GAL20V8
Top View
GAL
20V8
DIP
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20v8_07
Features
• HIGH PERFORMANCE E2
CMOS®
TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS®
Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL®
Devices with Full Function/
Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
Description
The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2
) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL20V8 are the PAL architectures listed
in the table of the macrocell description section. GAL20V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
I
CLK
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
I
I
I
I
I
I
I/OE
I/CLK
OE
8
8
8
8
8
8
8
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
IMUX
IMUX
PROGRAMMABLE
AND-ARRAY
(64 X 40)
OLMC
Lead-Free
Package
Options
Available!2
Specifications GAL20V8
T ) pd (ns) T ) su (ns T ) co (ns I # cc (mA O e rdering Packag
1 0 0 17 0 13
G CI AL20V8 -10LJ
28-Lead PLCC
1 I 30 G P AL20V8B-10LP 24-Pin Plastic DI
1 I 30 G C AL20V8B-10LJ 28-Lead PLC
1 2 5 1 01 0 1 I 3 G P AL20V8B-15LP 24-Pin Plastic DI
1 I 30 G C AL20V8B-15LJ 28-Lead PLC
2 3 0 1 11 56 I G P AL20V8B-20QP 24-Pin Plastic DI
6 I 5 G C AL20V8B-20QJ 28-Lead PLC
2 5 5 1 21 56 I G P AL20V8B-25QP 24-Pin Plastic DI
6 I 5 G C AL20V8B-25QJ 28-Lead PLC
1 I 30 G P AL20V8B-25LP 24-Pin Plastic DI
1 I 30 G C AL20V8B-25LJ 28-Lead PLC
Industrial Grade Specifications
T ) pd (ns) T ) su (ns T ) co (ns I # cc (mA O e rdering Packag
534 5 1 J 1 G C AL20V8C-5L 28-Lead PLC
7 75 5 .5 11
G CJ AL20V8 -7L 28-Lead PLCC
1 P 15 G P AL20V8B-7L 24-Pin Plastic DI
1 0 0 17 5 11
G CJ AL20V8 -10L 28-Lead PLCC
1 P 15 G P AL20V8B-10L 24-Pin Plastic DI
1 2 5 1 01 55 P G P AL20V8B-15Q 24-Pin Plastic DI
5 J 5 G C AL20V8B-15Q 28-Lead PLC
9 P 0 G P AL20V8B-15L 24-Pin Plastic DI
9 J 0 G C AL20V8B-15L 28-Lead PLC
2 5 5 1 21 55 P G P AL20V8B-25Q 24-Pin Plastic DI
5 J 5 G C AL20V8B-25Q 28-Lead PLC
9 P 0 G P AL20V8B-25L 24-Pin Plastic DI
9 J 0 G C AL20V8B-25L 28-Lead PLC
GAL20V8 Ordering Information
Conventional Packaging
Commercial Grade SpecificationsSpecifications GAL20V8
3
Part Number Description
Industrial Grade Specifications
Lead-Free Packaging
Commercial Grade Specifications
T ) pd (ns) T ) su (ns T ) co (ns I # cc (mA O e rdering Packag
534 5 1 N 1 G C AL20V8C-5LJ Lead-Free 28-Lead PLC
7 75 5 .5 11
G CN AL20V8 -7LJ
L C ead-Free 28-Lead PLC
1 N 15 G P AL20V8B-7LP Lead-Free 24-Pin Plastic DI
1 0 0 17 5 11
G CN AL20V8 -10LJ
L C ead-Free 28-Lead PLC
1 N 15 G P AL20V8B-10LP Lead-Free 24-Pin Plastic DI
1 2 5 1 01 55 N G C AL20V8B-15QJ Lead-Free 28-Lead PLC
5 N 5 G P AL20V8B-15QP Lead-Free 24-Pin Plastic DI
9 N 0 G C AL20V8B-15LJ Lead-Free 28-Lead PLC
9 N 0 G P AL20V8B-15LP Lead-Free 24-Pin Plastic DI
2 5 5 1 21 55 N G C AL20V8B-25QJ Lead-Free 28-Lead PLC
5 N 5 G P AL20V8B-25QP Lead-Free 24-Pin Plastic DI
9 N 0 G e AL20V8B-25LJ L C ead-Fre 28-Lead PLC
9 N 0 G P AL20V8B-25LP Lead-Free 24-Pin Plastic DI
T ) pd (ns) T ) su (ns T ) co (ns I # cc (mA O e rdering Packag
1 0 0 17 0 13
G CI AL20V8 -10LJN Lead-Free 28-Pin Plastic DIP
1 I 30 G P AL20V8B-10LPN Lead-Free 24-Pin Plastic DI
1 2 5 1 01 0 1 I 3 G C AL20V8B-15LJN Lead-Free 28-Lead PLC
1 I 30 G P AL20V8B-15LPN Lead-Free 24-Pin Plastic DI
2 3 0 1 11 56 I G C AL20V8B-20QJN Lead-Free 28-Lead PLC
6 I 5 G P AL20V8B-20QPN Lead-Free 24-Pin Plastic DI
2 5 5 1 21 56 I G C AL20V8B-25QJN Lead-Free 28-Lead PLC
6 I 5 G P AL20V8B-25QPN Lead-Free 24-Pin Plastic DI
1 I 30 G C AL20V8B-25LJN Lead-Free 28-Lead PLC
1 I 30 G P AL20V8B-25LPN Lead-Free 24-Pin Plastic DI
Blank = Commercial
I = Industrial
Grade
L = Low Power Power Package
Q = Quarter Power
Speed (ns)
XXXXXXXX XX X XX X
Device Name
_
P = Plastic DIP
PN = Lead-free Plastic DIP
J = PLCC
JN = Lead-free PLCC
GAL20V8C
GAL20V8B4
Specifications GAL20V8
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL20V8 . The
information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user
should not need to directly manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL20V8
can emulate. It also shows the OLMC mode under which the
devices emulate the PAL architecture.
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 13 (DIP pinout) are permanently
configured as clock and output enable, respectively. These pins
cannot be configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 13 become dedicated inputs and
use the feedback paths of pin 22 and pin 15 respectively. Because
of this feedback path usage, pin 22 and pin 15 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18 and 19) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
Registered Complex Simple Auto Mode Select
ABEL P20V8R P20V8C P20V8AS P20V8
CUPL G20V8MS G20V8MA G20V8AS G20V8
LOG/iC GAL20V8_R GAL20V8_C7 GAL20V8_C8 GAL20V8
OrCAD-PLD "Registered"1
"Complex"1
"Simple"1
GAL20V8A
PLDesigner P20V8R2
P20V8C2
P20V8C2
P20V8A
TANGO-PLD G20V8R G20V8C G20V8AS3
G20V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
PAL Architectures GAL20V8
Emulated by GAL20V8 Global OLMC Mode
20R8 Registered
20R6 Registered
20R4 Registered
20RP8 Registered
20RP6 Registered
20RP4 Registered
20L8 Complex
20H8 Complex
20P8 Complex
14L8 Simple
16L6 Simple
18L4 Simple
20L2 Simple
14H8 Simple
16H6 Simple
18H4 Simple
20H2 Simple
14P8 Simple
16P6 Simple
18P4 Simple
20P2 Simple
Output Logic Macrocell (OLMC)
Compiler Support for OLMCSpecifications GAL20V8
5
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as subsets of the I/O function.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE for registered output configuration..
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
D Q
Q
CLK
OE
XOR
XOR
Registered Mode6
Specifications GAL20V8
DIP (PLCC) Package Pinouts
OE
0000
PTD
2640
0280
0320
0600
0640
0920
0960
1240
1280
1560
1600
1880
1920
2200
2240
2520
OLMC
OLMC
XOR-2567
AC1-2639
OLMC
XOR-2566
AC1-2638
OLMC
XOR-2565
AC1-2637
OLMC
XOR-2564
AC1-2636
XOR-2563
AC1-2635
OLMC
XOR-2562
AC1-2634
OLMC
OLMC
XOR-2561
AC1-2633
XOR-2560
AC1-2632
11(13)
10(12)
9(11)
8(10)
7(9)
6(7)
5(6)
4(5)
3(4)
2(3)
1(2)
23(27)
22(26)
21(25)
20(24)
19(23)
18(21)
17(20)
16(19)
15(18)
14(17)
13(16)
SYN-2704
AC0-2705
2703
0 4 8 12 16 20 24 28 32 36
Registered Mode Logic DiagramSpecifications GAL20V8
7
In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 15 & 22) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered
mode.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
13 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 16 through Pin 21 are configured to this function.
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 15 and Pin 22 are configured to this function.
XOR
XOR
Complex Mode8
Specifications GAL20V8
DIP (PLCC) Package Pinouts
0000
PTD
2640
0280
0320
0600
0640
0920
0960
1240
1280
1560
1600
1880
1920
2200
2240
2520
SYN-2704
AC0-2705
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
23(27)
22(26)
21(25)
20(24)
19(23)
18(21)
17(20)
16(19)
15(18)
14(17)
13(16)
11(13)
10(12)
9(11)
8(10)
7(9)
6(7)
5(6)
4(5)
3(4)
2(3)
1(2)
2703
XOR-2567
AC1-2639
XOR-2566
AC1-2638
XOR-2565
AC1-2637
XOR-2564
AC1-2636
XOR-2563
AC1-2635
XOR-2562
AC1-2634
XOR-2561
AC1-2633
XOR-2560
AC1-2632
0 4 8 12 16 20 24 28 32 36
Complex Mode Logic DiagramSpecifications GAL20V8
9
Combinatorial Output with Feedback Configuration
for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 18 & 19 can be configured to
this function.
Combinatorial Output Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 18 & 19 are permanently configured to this
function.
Dedicated Input Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 18 & 19 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
In the Simple mode, pins are configured as dedicated inputs or as
dedicated, always active, combinatorial outputs.
Architecture configurations available in this mode are similar to the
common 14L8 and 16P6 devices with many permutations of generic output polarity or input choices.
All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has programmable polarity.
Pins 1 and 13 are always available as data inputs into the AND
array. The “center” two macrocells (pins 18 and 19) cannot be used
in the input configuration.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Vcc
XOR
Vcc
XOR
Simple Mode10
Specifications GAL20V8
DIP (PLCC) Package Pinouts
0000
PTD
2640
0280
0320
0600
0640
0920
0960
1240
1280
1560
1600
1880
1920
2200
2240
2520
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
XOR-2560
AC1-2632
OLMC
XOR-2561
AC1-2633
XOR-2562
AC1-2634
XOR-2563
AC1-2635
XOR-2564
AC1-2636
XOR-2565
AC1-2637
XOR-2566
AC1-2638
XOR-2567
AC1-2639
23(27)
22(26)
21(25)
20(24)
19(23)
18(21)
17(20)
16(19)
15(18)
14(17)
13(16)
SYN-2704
AC0-2705
2703
11(13)
10(12)
9(11)
8(10)
7(9)
6(7)
5(6)
4(5)
3(4)
2(3)
1(2)
0 4 8 12 16 20 24 28 32 36
Simple Mode Logic DiagramSpecifications GAL20V8
11
GAL20V8C
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL1
Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA
IIH Input or I/O High Leakage Current 3.5V≤ VIN ≤ VCC — — 10 μA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOL Low Level Output Current — — 16 mA
IOH High Level Output Current — — –3.2 mA
IOS2
Output Short Circuit Current VCC = 5V VOUT = 0.5V TA
= 25°C –30 — –150 mA
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (TA
) ............................... 0 to 75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (TA
) ........................... –40 to 85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
SYMBOL PARAMETER CONDITION MIN. TYP.3
MAX. UNITS
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -5/-7/-10 — 75 115 mA
Supply Current ftoggle = 15MHz Outputs Open
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-10 — 75 130 mA
Supply Current ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
Absolute Maximum Ratings(1)
Supply voltage VCC ...................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................ –65 to 150°C
Ambient Temperature with
Power Applied ........................................ –55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)12
Specifications GAL20V8C GAL20V8
-7
MIN. MAX.
-10
MIN. MAX.
tpd A Input or I/O to 8 outputs switching 1 5 3 7.5 3 10 ns
Comb. Output 1 output switching — — — 7 — — ns
tco A Clock to Output Delay 1 4 2 5 2 7 ns
tcf2
— Clock to Feedback Delay — 3 — 3 — 6 ns
tsu — Setup Time, Input or Feedback before Clock↑ 3 — 5 — 7.5 — ns
th — Hold Time, Input or Feedback after Clock↑ 0 — 0 — 0 — ns
A Maximum Clock Frequency with 142.8 — 100 — 66.7 — MHz
External Feedback, 1/(tsu + tco)
fmax3
A Maximum Clock Frequency with 166 — 125 — 71.4 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 166 — 125 — 83.3 — MHz
No Feedback
twh — Clock Pulse Duration, High 3 — 4 — 6 — ns
twl — Clock Pulse Duration, Low 3 — 4 — 6 — ns
ten B Input or I/O to Output Enabled 1 6 3 9 3 10 ns
B OE to Output Enabled 1 6 2 6 2 10 ns
tdis C Input or I/O to Output Disabled 1 5 2 9 2 10 ns
C OE to Output Disabled 1 5 1.5 6 1.5 10 ns
PARAMETER UNITS TEST
COND1
.
DESCRIPTION
COM COM COM/IND
-5
MIN. MAX.
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these
parameters.
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CI
Input Capacitance 8 pF VCC = 5.0V, VI
= 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (TA = 25°C, f = 1.0 MHz)Specifications GAL20V8
13
GAL20V8B
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -10/-15/-25 — 75 130 mA
Supply Current ftoggle = 15MHz Outputs Open Q -20/-25 — 45 65 mA
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10 — 75 115 mA
Supply Current ftoggle = 15MHz Outputs Open L -15/-25 — 75 90 mA
Q -15/-25 — 45 55 mA
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (TA
) ............................... 0 to 75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (TA
) ........................... –40 to 85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP.3
MAX. UNITS
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL1
Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 μA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOL Low Level Output Current — — 24 mA
IOH High Level Output Current — — –3.2 mA
IOS2
Output Short Circuit Current VCC = 5V VOUT = 0.5V TA
= 25°C –30 — –150 mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
Absolute Maximum Ratings(1)
Supply voltage VCC ...................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................ –65 to 150°C
Ambient Temperature with
Power Applied ........................................ –55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).14
Specifications GAL20V8B GAL20V8
tpd A Input or I/O to 8 outputs switching 3 7.5 3 10 3 15 3 20 3 25 ns
Comb. Output 1 output switching — 7 — — — — — — — — ns
tco A Clock to Output Delay 2 5 2 7 2 10 2 11 2 12 ns
tcf2
— Clock to Feedback Delay — 3 — 6 — 8 — 9 — 10 ns
tsu — Setup Time, Input or Fdbk before Clk↑ 7 — 10 — 12 — 13 — 15 — ns
th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns
A Maximum Clock Frequency with 83.3 — 58.8 — 45.5 — 41.6 — 37 — MHz
External Feedback, 1/(tsu + tco)
fmax3
A Maximum Clock Frequency with 100 — 62.5 — 50 — 45.4 — 40 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 100 — 62.5 — 62.5 — 50 — 41.7 — MHz
No Feedback
twh — Clock Pulse Duration, High 5 — 8 — 8 — 10 — 12 — ns
twl — Clock Pulse Duration, Low 5 — 8 — 8 — 10 — 12 — ns
ten B Input or I/O to Output Enabled 3 9 3 10 — 15 — 18 — 25 ns
B OE to Output Enabled 2 6 2 10 — 15 — 18 — 20 ns
tdis C Input or I/O to Output Disabled 2 9 2 10 — 15 — 18 — 25 ns
C OE to Output Disabled 1.5 6 1.5 10 — 15 — 18 — 20 ns
UNITS
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
-25
MIN. MAX.
-20
MIN. MAX.
-15
MIN. MAX.
-10
MIN. MAX.
PARAM. DESCRIPTION TEST
COND1
.
-7
MIN. MAX.
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CI
Input Capacitance 8 pF VCC = 5.0V, VI
= 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
COM COM / IND COM / IND IND COM / IND
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (TA = 25°C, f = 1.0 MHz)Specifications GAL20V8
15
Combinatorial Output Registered Output
Input or I/O to Output Enable/Disable OE to Output Enable/Disable
fmax with Feedback
Clock Width
COMBINATIONAL
OUTPUT
VALID INPUT
INPUT or
I/O FEEDBACK
tpd
CLK
(w/o fb)
1/fmax
twh twl
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
(external fdbk)
tsu
tco
th
1/fmax
OE
REGISTERED
OUTPUT
tdis ten
CLK
REGISTERED
FEEDBACK
tcf tsu
1/fmax (internal fdbk)
COMBINATIONAL
OUTPUT
INPUT or
I/O FEEDBACK
tdis ten
Switching Waveforms16
Specifications GAL20V8
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
fmax with No Feedback
Note:fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
GAL20V8C Output Load Conditions (see figure)
Test Condition R1 R2 CL
A 200Ω 200Ω 50pF
B Active High ∞ 200Ω 50pF
Active Low 200Ω 200Ω 50pF
C Active High ∞ 200Ω 5pF
Active Low 200Ω 200Ω 5pF
TEST POINT
C *L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*CL
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R2
R1
GAL20V8B Output Load Conditions (see figure)
Test Condition R1 R2 CL
A 200Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF
Active Low 200Ω 390Ω 50pF
C Active High ∞ 390Ω 5pF
Active Low 200Ω 390Ω 5pF
CLK
REGISTER
LOGIC
ARRAY
tcf
tpd
fmax with External Feedback 1/(tsu+tco)
Note:fmax with external feedback is calculated from measured
tsu and tco.
REGISTER LOGIC
ARRAY
ts u tc o
CLK
Input Pulse Levels GND to 3.0V
Input Rise and GAL20V8B 2 – 3ns 10% – 90%
Fall Times GAL20V8C 1.5ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
level.
REGISTER LOGIC
ARRAY
CLK
tsu + th
fmax Descriptions
Switching Test ConditionsSpecifications GAL20V8
17
1.0 2.0 3.0 4.0 5.0
-60
0
-20
-40
0
Input Voltage (Volts)
Input Current (uA)
Electronic Signature
An electronic signature is provided in every GAL20V8 device. It
contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum.
Security Cell
A security cell is provided in the GAL20V8 devices to prevent unauthorized copying of the array patterns. Once programmed, this
cell prevents further read access to the functional bits in the device.
This cell can only be erased by re-programming the device, so the
original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user,
regardless of the state of this control cell.
Latch-Up Protection
GAL20V8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of
the traditional p-channel pull-ups in order to eliminate latch-up due
to output overshoots.
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.
Typical Input Pull-up Characteristic
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
GAL20V8 devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing text vectors
perform output register preload automatically.
Input Buffers
GAL20V8 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The GAL20V8 input and I/O pins have built-in active pull-ups. As
a result, unused inputs and I/O's will float to a TTL "high" (logical
"1"). Lattice Semiconductor recommends that all unused inputs
and tri-stated I/O pins be connected to another active input, VCC,
or Ground. Doing this will tend to improve noise immunity and reduce ICC for the device.18
Specifications GAL20V8
Typ. Vref = 3.2V
Typical Output
Typ. Vref = 3.2V
Typical Input
Vcc
PIN
Vcc Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc
PIN
Tri-State Vref
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Circuitry within the GAL20V8 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs set
low after a specified time (tpr, 1μs MAX). As a result, the state on
the registered output pins (if they are enabled) will always be high
on power-up, regardless of the programmed polarity of the output
pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous
nature of system power-up, some conditions must be met to provide
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Vcc (min.)
tpr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
twl
tsu
a valid power-up reset of the device. First, the VCC rise must be
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Power-Up Reset
Input/Output Equivalent SchematicsSpecifications GAL20V8
19
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-1
-0.75
-0.5
-0.25
0
12345678
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-1
-0.75
-0.5
-0.25
0
12345678
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
0 50 100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
0 50 100 150 200 250 300
RISE
FALL
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
GAL20V8C: Typical AC and DC Characteristic Diagrams20
Specifications GAL20V8
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
0.00 20.00 40.00 60.00 80.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00 10.00 20.00 30.00 40.00 50.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.25
3.5
3.75
4
4.25
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
4.50 4.75 5.00 5.25 5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
0 25 50 75 100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
5
10
15
20
25
30
35
40
45
-2.00 -1.50 -1.00 -0.50 0.00
GAL20V8C: Typical AC and DC Characteristic DiagramsSpecifications GAL20V8
21
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-2
-1.5
-1
-0.5
0
12345678
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-2
-1.5
-1
-0.5
0
12345678
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
10
0 50 100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
10
0 50 100 150 200 250 300
RISE
FALL
GAL20V8B-7/-10: Typical AC and DC Characteristic Diagrams22
Specifications GAL20V8
Vol vs Iol
Iol (mA)
Vol (V)
0
0.25
0.5
0.75
1
0.00 20.00 40.00 60.00 80.00 100.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00 10.00 20.00 30.00 40.00 50.00 60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.5
3.75
4
4.25
4.5
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
4.50 4.75 5.00 5.25 5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
-55 -25 0 25 50 75 100 125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
1.30
0 25 50 75 100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
70
80
90
100
-2.00 -1.50 -1.00 -0.50 0.00
GAL20V8B-7/-10: Typical AC and DC Characteristic DiagramsSpecifications GAL20V8
23
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-2
-1.5
-1
-0.5
0
12345678
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-2
-1.5
-1
-0.5
0
12345678
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-4
-2
0
2
4
6
8
10
0 50 100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-4
-2
0
2
4
6
8
10
0 50 100 150 200 250 300
RISE
FALL
GAL20V8B-15/-25: Typical AC and DC Characteristic Diagrams24
Specifications GAL20V8
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
0.00 20.00 40.00 60.00 80.00 100.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00 10.00 20.00 30.00 40.00 50.00 60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.25
3.5
3.75
4
4.25
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
4.50 4.75 5.00 5.25 5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
-55 -25 0 25 50 75 100 125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
1.30
1.40
0 25 50 75 100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
12
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
70
80
90
100
-2.00 -1.50 -1.00 -0.50 0.00
GAL20V8B-15/-25: Typical AC and DC Characteristic DiagramsSpecifications GAL20V8
25
Revision History
Date Version Change Summary
- 20v8_06 Previous Lattice release.
August 2006 20v8_07 Updated for lead-free package options.
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT237
3-to-8 line decoder/demultiplexer
with address latches
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package OutlinesDecember 1990 2
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches 74HC/HCT237
FEATURES
• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent
controls
• Active HIGH mutually exclusive outputs
• Output capability: standard
• I
CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT237 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT237 are 3-to-8 line decoder/demultiplexers
with latches at the three address inputs (An). The “237”
essentially combines the 3-to-8 decoder function with a
3-bit storage latch. When the latch is enabled (LE = LOW),
the “237” acts as a 3-to-8 active LOW decoder. When the
latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the
latches. Further address changes are ignored as long as
LE remains HIGH.
The output enable input (E1 and E2) controls the state of
the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E1 is LOW and E2
is HIGH.
The “237” is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobed
(stored address) applications in bus oriented systems.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr
= tf
= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
P
D = CPD × VCC2 × fi
+ ∑ (CL × VCC2 × f
o) where:
fi
= input frequency in MHz
f
o
= output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL
= output load capacitance in pF
V
CC = supply voltage in V
2. For HC the condition is VI
= GND to VCC
For HCT the condition is VI
= GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL / tPLH propagation delay CL
= 15 pF; VCC = 5 V
An to Yn 16 19 ns
LE to Yn 19 21 ns
E1 to Yn 14 17 ns
E2 to Yn 14 17 ns
CI
input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 60 63 pFDecember 1990 3
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches 74HC/HCT237
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3 A0 to A2 data inputs
4 LE latch enable input (active LOW)
5 E1 data enable input (active LOW)
6 E2 data enable input (active HIGH)
8 GND ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7
multiplexer outputs
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.December 1990 4
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches 74HC/HCT237
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUTS
LE E1
E2
A0
A1
A2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H L H X X X stable
XHX XXX L L L L LLL L
XX L XXX L L L L LLL L
L L H L L L H L L L LLL L
L L HHL L L H L L LLL L
L L H LHL L L H L LLL L
L L HHH L L L L HLLL L
L L H L L H L L L LHLL L
L L H H L H L L L L LHL L
L L H L HH L L L L L LH L
L L HHHH L L L L LLL H
Fig.4 Functional diagram.December 1990 5
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches 74HC/HCT237
Fig.5 Logic diagram.December 1990 6
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches 74HC/HCT237
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr
= tf
= 6 ns; CL
= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
An to Yn
52
19
15
160
32
27
200
40
34
240
48
41
ns 2.0
4.5
6.0
Fig.6
t
PHL/ tPLH propagation delay
LE to Yn
61
22
18
190
38
32
240
48
41
285
57
48
ns 2.0
4.5
6.0
Fig.7
t
PHL/ tPLH propagation delay
E1 to Yn
47
17
14
145
29
25
180
36
31
220
44
38
ns 2.0
4.5
6.0
Fig.7
t
PHL/ tPLH propagation delay
E2 to Yn
47
17
14
145
29
25
180
36
31
220
44
38
ns 2.0
4.5
6.0
Fig.6
t
THL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.6
t
W LE pulse width
LOW
50
10
9
11
4
3
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.8
t
su set-up time
An to LE
50
10
9
6
2
2
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.8
t
h hold time
An to LE
30
6
5
3
1
1
40
8
7
45
9
8
ns 2.0
4.5
6.0
Fig.8December 1990 7
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches 74HC/HCT237
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC) for a unit load of 1 is given in the family specifications.
To determine ∆I
CC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr
= tf
= 6 ns; CL
= 50 pF
INPUT UNIT LOAD COEFFICIENT
An 1.50
E1 1.50
E2 1.50
LE 1.50
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
An to Yn
22 38 48 57 ns 4.5 Fig.6
t
PHL/ tPLH propagation delay
LE to Yn
25 42 53 63 ns 4.5 Fig.7
t
PHL/ tPLH propagation delay
E1 to Yn
20 35 44 53 ns 4.5 Fig.7
t
PHL/ tPLH propagation delay
E2 to Yn
20 33 41 50 ns 4.5 Fig.6
t
THL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6
t
W LE pulse width
HIGH
10 5 13 15 ns 4.5 Fig.8
t
su set-up time
An to LE
10 2 13 15 ns 4.5 Fig.8
t
h hold time
An to LE
5 0 5 5 ns 4.5 Fig.8December 1990 8
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches 74HC/HCT237
AC WAVEFORMS
Fig.6 Waveforms showing the address input (An)
and enable inputs (E2, LE) to output (Yn)
propagation delays and the output transition
times.
(1) HC : VM = 50%; VI
= GND to VCC .
HCT: VM = 1.3 V; VI
= GND to 3 V.
Fig.7 Waveforms showing the enable input (E1) to
output (Yn) propagation delays and the
output transition times.
(1) HC : VM = 50%; VI
= GND to VCC .
HCT: VM = 1.3 V; VI
= GND to 3 V.
Fig.8 Waveforms showing the data set-up, hold times for An input to LE input and the latch enable pulse width.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : VM = 50%; VI
= GND to VCC .
HCT: VM = 1.3 V; VI
= GND to 3 V.December 1990 9
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches 74HC/HCT237
APPLICATION INFORMATION
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
Fig.9 6-to-64 line decoder with input address storage.
August 12, 2008
DS10CP154A
1.5 Gbps 4x4 LVDS Crosspoint Switch
General Description
The DS10CP154A is a 1.5 Gbps 4x4 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs. The
switch configuration can be accomplished via external pins or
the System Management Bus (SMBus) interface. In addition,
the SMBus circuitry enables the loss of signal (LOS) monitors
that can inform a system of the presence of an open inputs
condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower return losses, reduce
component count and further minimize board space.
Features
■ DC - 1.5 Gbps low jitter, low skew, low power operation
■ Pin and SMBus configurable, fully differential, nonblocking architecture
■ Wide input common mode range enables DC coupled
interface to CML or LVPECL drivers
■ LOS circuitry detects open inputs fault condition
■ On-chip 100 Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
■ 8 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 6 mm x 6 mm LLP-40 space saving package
Applications
■ High-speed channel select applications
■ Clock and data buffering and muxing
■ SD / HD SDI Routers
Typical Application
30073703
© 2008 National Semiconductor Corporation 300737 www.national.com
DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint SwitchOrdering Code
NSID Function
DS10CP154ATSQ Crosspoint Switch
Block Diagram
30073701
www.national.com 2
DS10CP154AConnection Diagram
30073702
DS10CP154A Pin Diagram
3 www.national.com
DS10CP154APin Descriptions
Pin Name Pin
Number
I/O, Type Pin Description
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS Inverting and non-inverting high speed LVDS output pins.
EN_smb 17 I, LVCMOS System Management Bus (SMBus) mode enable pin. The pin has
an internal 20k pull down. When the pin is set to a [1], the device
is in the SMBus mode. All SMBus registers are reset when the pin
is toggled.
S00/SCL,
S01/SDA
37,
36
I/O, LVCMOS For EN_smb = [1], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are the
SMBus clock input and data I/O pins respectively.
S10/ADDR0,
S11/ADDR1
35,
34
I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S20/ADDR2,
S21/ADDR3
33,
32
I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S30, S31 13, 14 I, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are nonfunctional and should be tied to either logic [0] or [1].
PWDN 38 I, LVCMOS For EN_smb = [0], this is the power down pin. When the PWDN is
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
NC 11, 12,
18, 19,
20, 31,
39, 40
No connect pins. May be left floating.
VDD 3, 8,
15,25, 30
Power Power supply pins.
GND 16, DAP Power Ground pin and pad (DAP - die attach pad).
www.national.com 4
DS10CP154AAbsolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VCC + 0.3V)
LVCMOS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Input Voltage −0.3V to +4V
LVDS Differential Input Voltage 0V to 1.0V
LVDS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage 0V to 1.0V
LVDS Output Short Circuit Current
Duration 5 ms
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
SQA Package 4.65W
Derate SQA Package 37.2 mW/°C above +25°C
Package Thermal Resistance
θJA +26.9°C/W
θJC +3.8°C/W
ESD Susceptibility
HBM (Note 1) ≥8 kV
MM (Note 2) ≥250V
CDM (Note 3) ≥1250V
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Differential Input
Voltage (VID)
0 1.0 V
Operating Free Air
Temperature (TA
)
−40 +25 +85 °C
SMBus (SDA, SCL) 3.6 V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 2.0 VDD V
VIL Low Level Input Voltage GND 0.8 V
I
IH High Level Input Current VIN = 3.6V
VCC = 3.6V
0 ±10 μA
EN_smb pin 40 175 250 μA
I
IL Low Level Input Current VIN = GND
VCC = 3.6V
0 ±10 μA
VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V −0.9 −1.5 V
VOL Low Level Output Voltage IOL= 4 mA SDA pin 0.4 V
LVDS INPUT DC SPECIFICATIONS
VID Input Differential Voltage 0 1 V
VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV
VTL Differential Input Low Threshold −100 0 mV
VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC -
0.05
V
I
IN Input Current
VIN = 3.6V or 0V
VCC = 3.6V or 0V
±1 ±10 μA
CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF
RIN Input Termination Resistor Between IN+ and IN- 100 Ω
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DS10CP154ASymbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT DC SPECIFICATIONS
VOD Differential Output Voltage
RL
= 100Ω
250 350 450 mV
ΔVOD Change in Magnitude of VOD for Complimentary
Output States -35 35 mV
VOS Offset Voltage
RL
= 100Ω
1.05 1.2 1.375 V
ΔVOS Change in Magnitude of VOS for Complimentary
Output States -35 35 mV
IOS Output Short Circuit Current (Note 8) OUT to GND -25 -55 mA
OUT to VCC 7 55 mA
COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF
ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω
SUPPLY CURRENT
ICC1 Supply Current PWDN = 0 40 50 mA
ICC2 Supply Current PWDN = 1
Broadcast Mode (1:4)
103 125 mA
ICC3 Supply Current PWDN = 1
Quad Buffer Mode (4:4)
115 140 mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA
= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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DS10CP154AAC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS (Note 11)
tPLHD Differential Propagation Delay Low to
High
RL
= 100Ω
500 675 ps
tPHLD Differential Propagation Delay High to
Low
460 675 ps
tSKD1 Pulse Skew |tPLHD − tPHLD| , (Note 12) 40 100 ps
tSKD2 Channel to Channel Skew , (Note 13) 40 125 ps
tSKD3 Part to Part Skew , (Note 14) 50 225 ps
tLHT Rise Time
RL
= 100Ω
145 350 ps
tHLT Fall Time 145 350 ps
tON Power Up Time Time from PWDN = LH to OUTn active 7 20 μs
tOFF Power Down Time Time from PWDN = HL to OUTn
inactive
6 25 ns
tSEL Select Time Time from Sn = LH or HL to new signal
at OUTn
8 12 ns
JITTER PERFORMANCE (Note 11)
tRJ1
Random Jitter
(RMS Value)
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
135 MHz 1 2.0 ps
tRJ2 311 MHz 0.5 1.2 ps
tRJ3 503 MHz 0.5 1.0 ps
tRJ4 750 MHz 0.5 1.0 ps
tDJ1
Deterministic Jitter
(Peak to Peak Value)
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
270 Mbps 7 30 ps
tDJ2 622 Mbps 12 26 ps
tDJ3 1.06 Gbps 9 24 ps
tDJ4 1.5 Gbps 12 28 ps
tTJ1
Total Jitter
(Peak to Peak Value)
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
270 mbps 0.008 0.036 UIP-P
tTJ2 622 Mbps 0.007 0.043 UIP-P
tTJ3 1.06Gbps 0.008 0.064 UIP-P
tTJ4 1.5 Gbps 0.007 0.072 UIP-P
7 www.national.com
DS10CP154ASymbol Parameter Conditions Min Typ Max Units
SMBus AC SPECIFICATIONS
fSMB SMBus Operating Frequency 10 100 kHz
tBUF Bus free time between Stop and Start
Conditions 4.7 μs
tHD:SDA Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
4.0 μs
tSU:SDA Repeated Start Condition setup time. 4.7 μs
tSU:SDO Stop Condition setup time 4.0 μs
tHD:DAT Data hold time 300 ns
tSU:DAT Data setup time 250 ns
tTIMEOUT Detect clock low timeout 25 35 ms
tLOW Clock low period 4.7 μs
tHIGH Clock high period 4.0 50 μs
tPOR Time in which a device must be
operational after power-on reset 500 ms
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA
= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 14: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
www.national.com 8
DS10CP154ADC Test Circuits
30073720
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30073721
FIGURE 2. Differential Driver AC Test Circuit
30073722
FIGURE 3. Propagation Delay Timing Diagram
30073723
FIGURE 4. LVDS Output Transition Times
9 www.national.com
DS10CP154AFunctional Description
The DS10CP154A is a 1.5 Gbps 4x4 LVDS digital crosspoint
switch optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and balanced cables. The DS10CP154A operates in two modes: Pin
Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
When in the Pin Mode, the switch is fully configurable with
external pins. This is possible with two input select pins per
output (e.g. S00 and S01 pins for OUT0).
In the Pin Mode, feedback from the LOS (Loss Of Signal)
monitor circuitry is not available (there is not an LOS output
pin).
When in the SMBus Mode, the full switch configuration and
SoftPWDN can be programmed via the SMBus interface. In
addition, by using the SMBus interface, a user can obtain the
feedback from the built-in LOS circuitry which detects an open
inputs fault condition.
In the SMBus Mode, the S00 and S01 pins become SMBus
clock (SCL) input and data (SDA) input pins respectively; the
S10, S11, S21 and S21 pins become the User-Set SMBus
Slave Address input pins (ADDR0, 1, 2 and 3) while the S30
and S31 pins become non-functional (tieing these two pins to
either H or L is recommended if the device will function only
in the SMBus mode).
In the SMBus Mode, the PWDN pin remains functional. How
this pin functions in each mode is detailed in the following
sections.
DS10CP154A OPERATION IN THE PIN MODE
Power Up
In the Pin Mode, when the power is applied to the device
power suppy pins, the DS10CP154A enters the Power Up
mode when the PWDN pin is set to logic H. When in the Power
Down mode (PWDN pin is set to logic L), all circuitry is shut
down except the minimum required circuitry for the LOS and
SMBus Slave operation.
Switch Configuration
In the Pin Mode, the DS10CP154A operates as a fully pinconfigurable crosspoint switch. The following truth tables illustrate how the swich can be configured with external pins.
Switch Configuration Truth Tables
TABLE 1. Input Select Pins Configuration for the Output OUT0
S01 S00 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
TABLE 2. Input Select Pins Configuration for the Output OUT1
S11 S10 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
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DS10CP154ATABLE 3. Input Select Pins Configuration for the Output OUT2
S21 S20 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
TABLE 4. Input Select Pins Configuration for the Output OUT3
S31 S30 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
DS10CP154A OPERATION IN THE SMBUS MODE
The DS10CP154A operates as a slave on the System Management Bus (SMBus) when the EN_smb pin is set to a high
(1). Under these conditions, the SCL pin is a clock input while
the SDA pin is a serial data input pin.
Device Address
Based on the SMBus 2.0 specification, the DS10CP154A has
a 7-bit slave address. The three most significant bits of the
slave address are hard wired inside the DS10CP154A and
are “101”. The four least significant bits of the address are
assigned to pins ADDR3-ADDR0 and are set by connecting
these pins to GND for a low (0) or to VCC for a high (1). The
complete slave address is shown in the following table:
TABLE 5. DS10CP154A Slave Address
1 0 1 ADDR3 ADDR2 ADDR1 ADDR0
MSB LSB
This slave address configuration allows up to sixteen
DS10CP154A devices on a single SMBus bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high
indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high
indicates a message STOP condition.
IDLE: If SCK and SDA are both high for a time exceeding
tBUF from the last detected STOP condition or if they are high
for a total exceeding the maximum specification for tHIGH
then the bus will transfer to the IDLE state.
SMBus Transactions
A transaction begins with the host placing the DS10CP154A
SMBus into the START condition, then a byte (8 bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’
to signify an ACK, or ‘1’ to signify NACK, after this the host
holds the SCL line low, and waits for the receiver to raise the
SDA line as an ACKnowledge that the byte has been received.
Writing to a Register
To write a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
Reading From a Register
To read a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ
transfer.
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
11 www.national.com
DS10CP154AREGISTER DESCRIPTIONS
There are three data registers in the DS10CP154A accessible via the SMBus interface.
TABLE 6. DS10CP154A SMBus Data Registers
Address
(hex) Name Access Description
0 Switch Configuration R/W Switch Configuration Register
3 Control R/W Powerdown, LOS Enable and Pin Control Register
4 LOS RO Loss Of Signal (LOS) Reporting Register
30073710
FIGURE 5. DS10CP154A Registers Block Diagram
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DS10CP154ASwitch Configuration Register
The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch Configuration Register
mapping and associated truth table.
Bit Default Bit Name Access Description
D[1:0] 00 Input Select 0 R/W Selects which input is routed to the OUT0.
D[3:2] 00 Input Select 1 R/W Selects which input is routed to the OUT1.
D[5:4] 00 Input Select 2 R/W Selects which input is routed to the OUT2.
D[7:6] 00 Input Select 3 R/W Selects which input is routed to the OUT3.
TABLE 7. Switch Configuration Register Truth Table
D1 D0 Input Routed to the OUT0
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power consumption based
on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the power down state).
13 www.national.com
DS10CP154AControl Register
The Control register enables SoftPWDN control, individual output power down (PWDNn) control and LOS Circuitry Enable control
via the SMBus. The following table shows the register mapping.
Bit Default Bit Name Access Description
D[3:0] 1111 PWDNn R/W Writing a [0] to the bit D[n] will power down the output OUTn
when either the PWDN pin OR the Control Register bit D[7]
(SoftPWDN) is set to a high [1].
D[4] x n/a R/W Undefined.
D[5] x n/a R/W Undefined.
D[6] 0 EN_LOS R/W Writing a [1] to the bit D[6] will enable the LOS circuitry and
receivers on all four inputs. The SmartPWDN circuitry will not
disable any of the inputs nor any supporting LOS circuitry
depending on the switch configuration.
D[7] 0 SoftPWDN R/W Writing a [0] to the bit D[7] will place the device into the power
down mode. This pin is ORed together with the PWDN pin.
TABLE 8. DS10CP154A Power Modes Truth Table
PWDN SoftPWDN PWDNn DS25CP104 Power Mode
0 0 x Power Down Mode. In this mode, all circuitry is shut down except the
minimum required circuitry for the LOS and SMBus Slave operation. The
SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs
in this mode by setting the EN_LOS bit to a [1].
0
1
1
1
0
1
x
x
x
Power Up Mode. In this mode, the SmartPWDN circuitry will automatically
power down any unused I/O and logic blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the SmartPWDN circuitry indicates that
that particular output is needed for the particular switch configuration and
the respective PWDNn bit has logic high [1].
An input will be enabled when the SmartPWDN circuitry indicates that that
particular input is needed for the particular switch configuration or the
EN_LOS bit is set to a [1].
LOS Register
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping.
Bit Default Bit Name Access Description
D[0] 0 LOS0 RO Reading a [0] from the bit D[0] indicates an open inputs fault condition on
the IN0. A [1] indicates presence of a valid signal.
D[1] 0 LOS1 RO Reading a [0] from the bit D[1] indicates an open inputs fault condition on
the IN1. A [1] indicates presence of a valid signal.
D[2] 0 LOS2 RO Reading a [0] from the bit D[2] indicates an open inputs fault condition on
the IN2. A [1] indicates presence of a valid signal.
D[3] 0 LOS3 RO Reading a [0] from the bit D[3] indicates an open inputs fault condition on
the IN3. A [1] indicates presence of a valid signal.
D[7:4] 0000 Reserved RO Reserved for future use. Returns undefined value when read.
www.national.com 14
DS10CP154AINPUT INTERFACING
The DS10CP154A accepts differential signals and allows
simple AC or DC coupling. With a wide common mode range,
the DS10CP154A can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following
three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10CP154A inputs
are internally terminated with a 100Ω resistor.
30073731
Typical LVDS Driver DC-Coupled Interface to DS10CP154A Input
30073732
Typical CML Driver DC-Coupled Interface to DS10CP154A Input
30073733
Typical LVPECL Driver DC-Coupled Interface to DS10CP154A Input
15 www.national.com
DS10CP154AOUTPUT INTERFACING
The DS10CP154A outputs signals that are compliant to the
LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
30073734
Typical DS10CP154A Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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DS10CP154APhysical Dimensions inches (millimeters) unless otherwise noted
Order Number DS10CP154ATSQ
NS Package Number SQA40A
(See AN-1187 for PCB Design and Assembly Recommendations)
17 www.national.com
DS10CP154ANotes DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint Switch
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http://www.farnell.com/datasheets
August 12, 2008
DS10CP154A
1.5 Gbps 4x4 LVDS Crosspoint Switch
General Description
The DS10CP154A is a 1.5 Gbps 4x4 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs. The
switch configuration can be accomplished via external pins or
the System Management Bus (SMBus) interface. In addition,
the SMBus circuitry enables the loss of signal (LOS) monitors
that can inform a system of the presence of an open inputs
condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower return losses, reduce
component count and further minimize board space.
Features
■ DC - 1.5 Gbps low jitter, low skew, low power operation
■ Pin and SMBus configurable, fully differential, nonblocking architecture
■ Wide input common mode range enables DC coupled
interface to CML or LVPECL drivers
■ LOS circuitry detects open inputs fault condition
■ On-chip 100 Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
■ 8 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 6 mm x 6 mm LLP-40 space saving package
Applications
■ High-speed channel select applications
■ Clock and data buffering and muxing
■ SD / HD SDI Routers
Typical Application
30073703
© 2008 National Semiconductor Corporation 300737 www.national.com
DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint SwitchOrdering Code
NSID Function
DS10CP154ATSQ Crosspoint Switch
Block Diagram
30073701
www.national.com 2
DS10CP154AConnection Diagram
30073702
DS10CP154A Pin Diagram
3 www.national.com
DS10CP154APin Descriptions
Pin Name Pin
Number
I/O, Type Pin Description
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
1, 2,
4, 5,
6, 7,
9, 10
I, LVDS Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS Inverting and non-inverting high speed LVDS output pins.
EN_smb 17 I, LVCMOS System Management Bus (SMBus) mode enable pin. The pin has
an internal 20k pull down. When the pin is set to a [1], the device
is in the SMBus mode. All SMBus registers are reset when the pin
is toggled.
S00/SCL,
S01/SDA
37,
36
I/O, LVCMOS For EN_smb = [1], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are the
SMBus clock input and data I/O pins respectively.
S10/ADDR0,
S11/ADDR1
35,
34
I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S20/ADDR2,
S21/ADDR3
33,
32
I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
S30, S31 13, 14 I, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are nonfunctional and should be tied to either logic [0] or [1].
PWDN 38 I, LVCMOS For EN_smb = [0], this is the power down pin. When the PWDN is
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
NC 11, 12,
18, 19,
20, 31,
39, 40
No connect pins. May be left floating.
VDD 3, 8,
15,25, 30
Power Power supply pins.
GND 16, DAP Power Ground pin and pad (DAP - die attach pad).
www.national.com 4
DS10CP154AAbsolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VCC + 0.3V)
LVCMOS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Input Voltage −0.3V to +4V
LVDS Differential Input Voltage 0V to 1.0V
LVDS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage 0V to 1.0V
LVDS Output Short Circuit Current
Duration 5 ms
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
SQA Package 4.65W
Derate SQA Package 37.2 mW/°C above +25°C
Package Thermal Resistance
θJA +26.9°C/W
θJC +3.8°C/W
ESD Susceptibility
HBM (Note 1) ≥8 kV
MM (Note 2) ≥250V
CDM (Note 3) ≥1250V
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Differential Input
Voltage (VID)
0 1.0 V
Operating Free Air
Temperature (TA
)
−40 +25 +85 °C
SMBus (SDA, SCL) 3.6 V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 2.0 VDD V
VIL Low Level Input Voltage GND 0.8 V
I
IH High Level Input Current VIN = 3.6V
VCC = 3.6V
0 ±10 μA
EN_smb pin 40 175 250 μA
I
IL Low Level Input Current VIN = GND
VCC = 3.6V
0 ±10 μA
VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V −0.9 −1.5 V
VOL Low Level Output Voltage IOL= 4 mA SDA pin 0.4 V
LVDS INPUT DC SPECIFICATIONS
VID Input Differential Voltage 0 1 V
VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV
VTL Differential Input Low Threshold −100 0 mV
VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC -
0.05
V
I
IN Input Current
VIN = 3.6V or 0V
VCC = 3.6V or 0V
±1 ±10 μA
CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF
RIN Input Termination Resistor Between IN+ and IN- 100 Ω
5 www.national.com
DS10CP154ASymbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT DC SPECIFICATIONS
VOD Differential Output Voltage
RL
= 100Ω
250 350 450 mV
ΔVOD Change in Magnitude of VOD for Complimentary
Output States -35 35 mV
VOS Offset Voltage
RL
= 100Ω
1.05 1.2 1.375 V
ΔVOS Change in Magnitude of VOS for Complimentary
Output States -35 35 mV
IOS Output Short Circuit Current (Note 8) OUT to GND -25 -55 mA
OUT to VCC 7 55 mA
COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF
ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω
SUPPLY CURRENT
ICC1 Supply Current PWDN = 0 40 50 mA
ICC2 Supply Current PWDN = 1
Broadcast Mode (1:4)
103 125 mA
ICC3 Supply Current PWDN = 1
Quad Buffer Mode (4:4)
115 140 mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA
= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
www.national.com 6
DS10CP154AAC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS (Note 11)
tPLHD Differential Propagation Delay Low to
High
RL
= 100Ω
500 675 ps
tPHLD Differential Propagation Delay High to
Low
460 675 ps
tSKD1 Pulse Skew |tPLHD − tPHLD| , (Note 12) 40 100 ps
tSKD2 Channel to Channel Skew , (Note 13) 40 125 ps
tSKD3 Part to Part Skew , (Note 14) 50 225 ps
tLHT Rise Time
RL
= 100Ω
145 350 ps
tHLT Fall Time 145 350 ps
tON Power Up Time Time from PWDN = LH to OUTn active 7 20 μs
tOFF Power Down Time Time from PWDN = HL to OUTn
inactive
6 25 ns
tSEL Select Time Time from Sn = LH or HL to new signal
at OUTn
8 12 ns
JITTER PERFORMANCE (Note 11)
tRJ1
Random Jitter
(RMS Value)
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
135 MHz 1 2.0 ps
tRJ2 311 MHz 0.5 1.2 ps
tRJ3 503 MHz 0.5 1.0 ps
tRJ4 750 MHz 0.5 1.0 ps
tDJ1
Deterministic Jitter
(Peak to Peak Value)
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
270 Mbps 7 30 ps
tDJ2 622 Mbps 12 26 ps
tDJ3 1.06 Gbps 9 24 ps
tDJ4 1.5 Gbps 12 28 ps
tTJ1
Total Jitter
(Peak to Peak Value)
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
270 mbps 0.008 0.036 UIP-P
tTJ2 622 Mbps 0.007 0.043 UIP-P
tTJ3 1.06Gbps 0.008 0.064 UIP-P
tTJ4 1.5 Gbps 0.007 0.072 UIP-P
7 www.national.com
DS10CP154ASymbol Parameter Conditions Min Typ Max Units
SMBus AC SPECIFICATIONS
fSMB SMBus Operating Frequency 10 100 kHz
tBUF Bus free time between Stop and Start
Conditions 4.7 μs
tHD:SDA Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
4.0 μs
tSU:SDA Repeated Start Condition setup time. 4.7 μs
tSU:SDO Stop Condition setup time 4.0 μs
tHD:DAT Data hold time 300 ns
tSU:DAT Data setup time 250 ns
tTIMEOUT Detect clock low timeout 25 35 ms
tLOW Clock low period 4.7 μs
tHIGH Clock high period 4.0 50 μs
tPOR Time in which a device must be
operational after power-on reset 500 ms
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA
= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 14: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
www.national.com 8
DS10CP154ADC Test Circuits
30073720
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30073721
FIGURE 2. Differential Driver AC Test Circuit
30073722
FIGURE 3. Propagation Delay Timing Diagram
30073723
FIGURE 4. LVDS Output Transition Times
9 www.national.com
DS10CP154AFunctional Description
The DS10CP154A is a 1.5 Gbps 4x4 LVDS digital crosspoint
switch optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and balanced cables. The DS10CP154A operates in two modes: Pin
Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
When in the Pin Mode, the switch is fully configurable with
external pins. This is possible with two input select pins per
output (e.g. S00 and S01 pins for OUT0).
In the Pin Mode, feedback from the LOS (Loss Of Signal)
monitor circuitry is not available (there is not an LOS output
pin).
When in the SMBus Mode, the full switch configuration and
SoftPWDN can be programmed via the SMBus interface. In
addition, by using the SMBus interface, a user can obtain the
feedback from the built-in LOS circuitry which detects an open
inputs fault condition.
In the SMBus Mode, the S00 and S01 pins become SMBus
clock (SCL) input and data (SDA) input pins respectively; the
S10, S11, S21 and S21 pins become the User-Set SMBus
Slave Address input pins (ADDR0, 1, 2 and 3) while the S30
and S31 pins become non-functional (tieing these two pins to
either H or L is recommended if the device will function only
in the SMBus mode).
In the SMBus Mode, the PWDN pin remains functional. How
this pin functions in each mode is detailed in the following
sections.
DS10CP154A OPERATION IN THE PIN MODE
Power Up
In the Pin Mode, when the power is applied to the device
power suppy pins, the DS10CP154A enters the Power Up
mode when the PWDN pin is set to logic H. When in the Power
Down mode (PWDN pin is set to logic L), all circuitry is shut
down except the minimum required circuitry for the LOS and
SMBus Slave operation.
Switch Configuration
In the Pin Mode, the DS10CP154A operates as a fully pinconfigurable crosspoint switch. The following truth tables illustrate how the swich can be configured with external pins.
Switch Configuration Truth Tables
TABLE 1. Input Select Pins Configuration for the Output OUT0
S01 S00 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
TABLE 2. Input Select Pins Configuration for the Output OUT1
S11 S10 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
www.national.com 10
DS10CP154ATABLE 3. Input Select Pins Configuration for the Output OUT2
S21 S20 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
TABLE 4. Input Select Pins Configuration for the Output OUT3
S31 S30 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
DS10CP154A OPERATION IN THE SMBUS MODE
The DS10CP154A operates as a slave on the System Management Bus (SMBus) when the EN_smb pin is set to a high
(1). Under these conditions, the SCL pin is a clock input while
the SDA pin is a serial data input pin.
Device Address
Based on the SMBus 2.0 specification, the DS10CP154A has
a 7-bit slave address. The three most significant bits of the
slave address are hard wired inside the DS10CP154A and
are “101”. The four least significant bits of the address are
assigned to pins ADDR3-ADDR0 and are set by connecting
these pins to GND for a low (0) or to VCC for a high (1). The
complete slave address is shown in the following table:
TABLE 5. DS10CP154A Slave Address
1 0 1 ADDR3 ADDR2 ADDR1 ADDR0
MSB LSB
This slave address configuration allows up to sixteen
DS10CP154A devices on a single SMBus bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high
indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high
indicates a message STOP condition.
IDLE: If SCK and SDA are both high for a time exceeding
tBUF from the last detected STOP condition or if they are high
for a total exceeding the maximum specification for tHIGH
then the bus will transfer to the IDLE state.
SMBus Transactions
A transaction begins with the host placing the DS10CP154A
SMBus into the START condition, then a byte (8 bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’
to signify an ACK, or ‘1’ to signify NACK, after this the host
holds the SCL line low, and waits for the receiver to raise the
SDA line as an ACKnowledge that the byte has been received.
Writing to a Register
To write a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
Reading From a Register
To read a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ
transfer.
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
11 www.national.com
DS10CP154AREGISTER DESCRIPTIONS
There are three data registers in the DS10CP154A accessible via the SMBus interface.
TABLE 6. DS10CP154A SMBus Data Registers
Address
(hex) Name Access Description
0 Switch Configuration R/W Switch Configuration Register
3 Control R/W Powerdown, LOS Enable and Pin Control Register
4 LOS RO Loss Of Signal (LOS) Reporting Register
30073710
FIGURE 5. DS10CP154A Registers Block Diagram
www.national.com 12
DS10CP154ASwitch Configuration Register
The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch Configuration Register
mapping and associated truth table.
Bit Default Bit Name Access Description
D[1:0] 00 Input Select 0 R/W Selects which input is routed to the OUT0.
D[3:2] 00 Input Select 1 R/W Selects which input is routed to the OUT1.
D[5:4] 00 Input Select 2 R/W Selects which input is routed to the OUT2.
D[7:6] 00 Input Select 3 R/W Selects which input is routed to the OUT3.
TABLE 7. Switch Configuration Register Truth Table
D1 D0 Input Routed to the OUT0
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power consumption based
on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the power down state).
13 www.national.com
DS10CP154AControl Register
The Control register enables SoftPWDN control, individual output power down (PWDNn) control and LOS Circuitry Enable control
via the SMBus. The following table shows the register mapping.
Bit Default Bit Name Access Description
D[3:0] 1111 PWDNn R/W Writing a [0] to the bit D[n] will power down the output OUTn
when either the PWDN pin OR the Control Register bit D[7]
(SoftPWDN) is set to a high [1].
D[4] x n/a R/W Undefined.
D[5] x n/a R/W Undefined.
D[6] 0 EN_LOS R/W Writing a [1] to the bit D[6] will enable the LOS circuitry and
receivers on all four inputs. The SmartPWDN circuitry will not
disable any of the inputs nor any supporting LOS circuitry
depending on the switch configuration.
D[7] 0 SoftPWDN R/W Writing a [0] to the bit D[7] will place the device into the power
down mode. This pin is ORed together with the PWDN pin.
TABLE 8. DS10CP154A Power Modes Truth Table
PWDN SoftPWDN PWDNn DS25CP104 Power Mode
0 0 x Power Down Mode. In this mode, all circuitry is shut down except the
minimum required circuitry for the LOS and SMBus Slave operation. The
SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs
in this mode by setting the EN_LOS bit to a [1].
0
1
1
1
0
1
x
x
x
Power Up Mode. In this mode, the SmartPWDN circuitry will automatically
power down any unused I/O and logic blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the SmartPWDN circuitry indicates that
that particular output is needed for the particular switch configuration and
the respective PWDNn bit has logic high [1].
An input will be enabled when the SmartPWDN circuitry indicates that that
particular input is needed for the particular switch configuration or the
EN_LOS bit is set to a [1].
LOS Register
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping.
Bit Default Bit Name Access Description
D[0] 0 LOS0 RO Reading a [0] from the bit D[0] indicates an open inputs fault condition on
the IN0. A [1] indicates presence of a valid signal.
D[1] 0 LOS1 RO Reading a [0] from the bit D[1] indicates an open inputs fault condition on
the IN1. A [1] indicates presence of a valid signal.
D[2] 0 LOS2 RO Reading a [0] from the bit D[2] indicates an open inputs fault condition on
the IN2. A [1] indicates presence of a valid signal.
D[3] 0 LOS3 RO Reading a [0] from the bit D[3] indicates an open inputs fault condition on
the IN3. A [1] indicates presence of a valid signal.
D[7:4] 0000 Reserved RO Reserved for future use. Returns undefined value when read.
www.national.com 14
DS10CP154AINPUT INTERFACING
The DS10CP154A accepts differential signals and allows
simple AC or DC coupling. With a wide common mode range,
the DS10CP154A can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following
three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10CP154A inputs
are internally terminated with a 100Ω resistor.
30073731
Typical LVDS Driver DC-Coupled Interface to DS10CP154A Input
30073732
Typical CML Driver DC-Coupled Interface to DS10CP154A Input
30073733
Typical LVPECL Driver DC-Coupled Interface to DS10CP154A Input
15 www.national.com
DS10CP154AOUTPUT INTERFACING
The DS10CP154A outputs signals that are compliant to the
LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
30073734
Typical DS10CP154A Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
www.national.com 16
DS10CP154APhysical Dimensions inches (millimeters) unless otherwise noted
Order Number DS10CP154ATSQ
NS Package Number SQA40A
(See AN-1187 for PCB Design and Assembly Recommendations)
17 www.national.com
DS10CP154ANotes DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint Switch
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OXPCIe840, PCI Express to Parallel Port
Highlights
General Features
oSingle IEEE1284 parallel port
oPCIe x1 end-point
-Integrated 2.5 GT/s SerDes
o11 x 11mm2
, 120-pin TFBGA package
oTypical Power: 200 mWatts
Key Features
oStandards Compliant
-PCI Express Base Specification, r1.1 (backwards
compatible with PCIe r1.0a)
-PCI Power Management Spec, r1.2
-ExpressCard, Mini Card & AIC compatible
-MSI/MSI-X compatible
- ASPM (L0S, L1) Link power management
oHigh Performance
-IEEE1284 compliant parallel port:
Supports SPP, EPP, and ECP modes
5V tolerant parallel port IOs
Direction control logic for external parallel port
drivers
oFlexibility
-8 user-configurable GPIOs/PWMs
- Device parameters configurable via EEPROM
-1.8V, 2.5V or 3.3V UART & GPIO I/O voltage
oRobust Operation
- Operation from a single 3.3 V supply
-Industrial temperature range -40°C to 85°C
oBroad Device Driver Support
-Windows Vista/XP/2K
-WinCE 4.2/5.0/6.0
-Linux 2.4/2.6
Part of the Expresso family of high performance PCI
Express devices, the OXPCIe840 is a single chip
parallel port device in a range of 2, 4 & 8 serial port
solutions, that includes the OXPCIe952, OXPCIe954
& OXPCIe958.
Incorporating PLX Technology’s high performance
parallel port technology, it combines outstanding
system performance with unrivaled flexibility for a
class leading connectivity solution.
Complete with the Oxide development tools and
certified device drivers, the OXPCIe840 is easy to
design-in and the ideal connectivity solution for a
diverse range of products including: PC Add-on
Cards, Industrial PC, Point of Sale Terminals,
Industrial Control, and Embedded Systems.
Accelerate your product development and time to
market with Oxide and PLX Technology’s easy to
design-in, high performance serial connectivity
solutions that just work.
© PLX Technology, www.plxtech.com Page 1 of 2 4/29/2009, Version 1.00 OXPCIe840, PCI Express to Parallel Port
Outstanding Performance
The OXPCIe840 offers the flexibility of SPP, EPP,
and ECP modes of parallel port operation, with
advanced MSI interrupt handling for optimum system
performance.
Its 5V tolerant IOs can be connected directly to a
parallel port device or for true 5V signalling
environments the OXPCIe840 includes the direction
control logic required for an external parallel port
driver. Additionally the device provides 8
GPIO/PWM lines for further flexibility and product
customization.
With comprehensive power management and
industrial temperature range as standard, the
OXPCIe840 is perfect for power and temperature
sensitive ExpressCard and MiniCarddesigns and is
the choice for high performance systems.
To support these advanced features the OXPCIe840 is
backed by a dedicated PLX device driver that is
quality assured, exhaustively tested and WHQL
approved; saving development time and providing
peace of mind.
OXPCIe840
Development Support
Design and evaluation of the OXPCIe840 couldn’t be
easier with this comprehensive reference design kit
(RDK). The RDK includes everything you need for
PC installation and evaluation including Hardware,
Oxide Development Tools and software device
drivers. Simply plug the half length PCI Express
evaluation board into any PCI Express slot, install the
software and its ready to go.
Changing the dynamics of device customization,
Oxide development tools enable customization of the
OXPCIe840 in minutes. No more complex, time
consuming, error prone manual editing of
programming files and driver source code; Oxide’s
intuitive graphical user interface provides simple
‘point and click’ feature selection and text box entry
for fast, error free customization with minimal
software expertise as well as instant access to up to
date documentation, software and reference designs.
Check the PLX website for details.
Ordering Information
Part Number Description
OXPCIe840-FBAG Parallel Port to PCIe Bridge
EK-OXPCIe840 Reference Design Kit
© PLX Technology, www.plxtech.com Page 2 of 2 4/29/2009, Version 1.00
BALADEUSE ETANCHE HLWC 111; Tension, alimentation:230V; Puissance:11W; Light Source:Fluorescente; Longueur:265mm; Couleur, lentilles:Clear; IP / NEMA Rating:IP67; Largeur (externe):50mm; Longueur/hauteur:265mm; Matière:Plastic; Poids:1kg; Tension d'alimentation Vac:230V
MAGNIFIER, LUMINAIRE, SNL319 - UK; Tension, alimentation:230V; Lamp Base Type:3 x fluocompact 9W; Puissance:9W; Light Source:Fluorescente; Longueur:830mm; Diamètre, lentille:162.11mm; Couleur:Light grey RAL7035; Tension d'alimentation Vac:230V
LUMINAIRE, 3-ARM, IP64, ES, 60W; Tension, alimentation:240V; Puissance:60W; Light Source:Å” incandescence; Longueur:750mm; Diamètre, lentille:127mm; Diamètre, extérieur:127mm; IP / NEMA Rating:IP64; Longueur (max..):750mm
TUBULAR LIGHT, CFL, 110V EXT, 18W; Tension, alimentation:110V; Lamp Base Type:Bi-broche; Puissance:18W; Light Source:Fluorescente compacte; Longueur:478mm; Diamètre, lentille:60mm; Diamètre, extérieur:60mm; IP / NEMA Rating:IP67; Longueur (max..):478mm; Longueur cordon:2.75m; Longueur/hauteur:478mm; Tension, alimentation c.c.:110V
FLUORESCENT FITTING, T5 LINK, 570MM; Tension, alimentation:230V; Lamp Base Type:T5; Puissance:13W; Longueur:570mm; SVHC:No SVHC (19-Dec-2011); Couleur:White; Hauteur:43mm; IP / NEMA Rating:IP20; Largeur (externe):21mm; Light Source:Fluorescente; Longueur/hauteur:570mm; Matière:Polycarbonate; Profondeur:55mm; Tension d'alimentation Vac:230V
TUBULAR LIGHT, T8, IP67, 240V, 36W; Tension, alimentation:240V; Lamp Base Type:T8; Puissance:36W; Light Source:Fluorescente; Longueur:1.35m; Diamètre, lentille:80mm; Diamètre, extérieur:80mm; IP / NEMA Rating:IP67; Longueur (max..):1350mm; Longueur cordon:2.75m; Longueur/hauteur:1350mm; Tension d'alimentation Vac:240V
TUBULAR LIGHT, CFL, 110V INT, 24W; Tension, alimentation:110V; Lamp Base Type:Bi-broche; Puissance:24W; Light Source:Fluorescente compacte; Longueur:579mm; Diamètre, lentille:60mm; Diamètre, extérieur:60mm; IP / NEMA Rating:IP67; Longueur (max..):579mm; Longueur cordon:2.75m; Longueur/hauteur:579mm; Tension, alimentation c.c.:110V
ECLAIRAGE MURAL BLANC; Light Source:BC GLS 100W; Longueur:220mm; Largeur:230mm; Profondeur:230mm; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Hauteur:220mm; IP / NEMA Rating:IP65; Lamp Base Type:BC 100W; Matière:Cast Aluminium; Puissance:100W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
LIGHT FITTING, CEILING BRASS; SVHC:No SVHC (19-Dec-2011); Couleur:Brass; Diamètre, extérieur:305mm; IP / NEMA Rating:IP20; Lamp Base Type:BC 60W; Light Source:1 x lampe GLS 60W BC; Longueur/hauteur:90mm; Matière:Pressed Steel; Profondeur:90mm; Puissance:60W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
LIGHT FITTING, CEILING, SLIM, 16W; Largeur:295mm; Profondeur:45mm; SVHC:No SVHC (19-Dec-2011); Couleur:White; Diamètre, extérieur:295mm; IP / NEMA Rating:IP20; Lamp Base Type:4 broches double-D; Largeur (externe):295mm; Light Source:1 x 4 broches 2D 16W; Longueur/hauteur:45mm; Matière:Steel/Acrylic; Profondeur:45mm; Puissance:16W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
ECLAIRAGE SIMPLE SPOT BLANC; Longueur:145mm; Largeur:90mm; Profondeur:160mm; SVHC:No SVHC (19-Dec-2011); Couleur:White; Diamètre, extérieur:90mm; Hauteur:160mm; IP / NEMA Rating:IP20; Lamp Base Type:ES R80; Largeur (externe):90mm; Light Source:1 x ES R80 100W; Longueur/hauteur:145mm; Matière:Pressed Steel; Profondeur:160mm; Puissance:100W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
TRACKLIGHT, COUPLER; SVHC:No SVHC (19-Dec-2011); Couleur:White; IP / NEMA Rating:IP20
TRACKLIGHT, FLEXIBLE TRACK COUPLER; SVHC:No SVHC (19-Dec-2011); Couleur:White; IP / NEMA Rating:IP20
TRACKLIGHT, LIVE END; SVHC:No SVHC (19-Dec-2011); Couleur:White; IP / NEMA Rating:IP20
TRACKLIGHT, TRACK 1200MM; Longueur:1.2m; SVHC:No SVHC (19-Dec-2011); Couleur:White; IP / NEMA Rating:IP20; Longueur/hauteur:1200mm
ECLAIRAGE TRIPLE SPOT GZ10 BLANC; Longueur:257mm; Profondeur:120mm; SVHC:No SVHC (19-Dec-2011); Couleur:White; Diamètre, extérieur:257mm; Hauteur:120mm; IP / NEMA Rating:IP21; Lamp Base Type:GZ10, 50W; Largeur (externe):55mm; Light Source:Halogène; Longueur/hauteur:257mm; Matière:Pressed Steel/Cast Aluminium; Puissance:50W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
ECLAIRAGE DOUBLE SPOTS BLANC; Longueur:370mm; Largeur:90mm; Profondeur:170mm; SVHC:No SVHC (19-Dec-2011); Couleur:White; Diamètre, extérieur:90mm; Hauteur:170mm; IP / NEMA Rating:IP20; Lamp Base Type:ES R80; Largeur (externe):90mm; Light Source:2 x ES R80 100W; Longueur/hauteur:370mm; Matière:Pressed Steel; Puissance:100W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
VOYANT NEON; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Vert; Couleur:vert; Diamètre de découpe panneau:9.5mm; Diamètre, lentille:12mm; Dimension de la lentille:12mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:31mm; Profondeur, derrière panneau:9mm; Taille de lampe:12mm; Tension d'alimentation Vac:250V
INDICATOR NEON 110V BLEU; Tension, alimentation:110V; Lamp Base Type:Fil; Intensité lumineuse:7.5mcd; Couleur:Bleu; Diamètre trou de fixation:14mm; Courant:6mA; SVHC:No SVHC (19-Dec-2011); Approval Bodies:CE; Base Type:Fil; Couleur:Bleu; Courant, fonctionnement c.a.:6mA; Diamètre de découpe panneau:14.5mm; Diamètre, encadrement:16mm; Dimension de la lentille:10mm; Durée de vie:25000h; Durée de vie moyenne de la lampe:25000h; Intensité lumineuse typique:7.5mcd; Longueur, derrière panneau:67mm; Ma
VOYANT NEON; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Ambre; Couleur:Ambre; Diamètre de découpe panneau:9.5mm; Diamètre, lentille:12mm; Dimension de la lentille:12mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:31mm; Profondeur, derrière panneau:9mm; Taille de lampe:12mm; Tension d'alimentation Vac:250V
PLUNGER, RACON, DIA 11.5MM, L 4.8MM; Couleur:White; Diamètre, extérieur:11.5mm; Hauteur:9.7mm; Longueur:4.8mm; Longueur/hauteur:4.8mm
CHASSIS D'INSOLATION A PRESSION 1 FACE; Longueur:625mm; Largeur:305mm; Profondeur:104mm; Working Area:254mm x 405mm; SVHC:No SVHC (19-Dec-2011); Poids:9.5kg; Puissance:60W; Temps de fonctionnement max.:7min; Tension, alimentation:220V; Tension d'alimentation Vac:220V; Tubes, nombre:4
CHASSIS D'INSOLATION A PRESSION CIP 1840; Largeur:290mm; Profondeur:135mm; Working Area:180mm x 400mm; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:30W; Courant:30mA; Hauteur:135mm; Largeur (externe):290mm; Longueur/hauteur:480mm; Poids:5.5kg; Puissance:30W; Tension, alimentation:230V
LAMP, E/SAVING, BC, 9W; Tension, alimentation:240V; Puissance:9W; Flux lumineux:45lm; Longueur:145mm; Diamètre de l'ampoule:41mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:41mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:145mm; Puissance GLS équivalente:40W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, CANDLE, BC, 3W; Tension, alimentation:240V; Puissance:3W; Longueur:120mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:120mm; Puissance GLS équivalente:20W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, CANDLE, ES, 3W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:3W; Longueur:120mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:120mm; Puissance GLS équivalente:20W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, MINI, BC, 14W; Tension, alimentation:240V; Puissance:14W; Longueur:132mm; Diamètre de l'ampoule:40mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:40mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:132mm; Puissance GLS équivalente:75W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, GLOBE, BC, 178MM, B22, 24W; Tension, alimentation:240V; Puissance:24W; Longueur:178mm; Diamètre de l'ampoule:110mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:110mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:178mm; Puissance GLS équivalente:120W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, GLOBE, ES, 168MM, E27, 20W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:20W; Longueur:168mm; Diamètre de l'ampoule:110mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:110mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:168mm; Puissance GLS équivalente:100W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, GLOBE, ES, 178MM, E27, 24W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:24W; Longueur:178mm; Diamètre de l'ampoule:110mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:110mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:178mm; Puissance GLS équivalente:120W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, MINI, SPIRAL, FLUO, BC, 7W; Tension, alimentation:240V; Puissance:7W; Flux lumineux:420lm; Longueur:87mm; Diamètre de l'ampoule:32mm; Température, couleur:2700K; Diamètre, extérieur:32mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:87mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
ENCASTRE GU10 MOULE ORIENTABLE CHROME; Profondeur:116mm; Diamètre, extérieur:80mm; Largeur (externe):80mm; Light Source:Halogène; Longueur/hauteur:116mm; Puissance:50W; Tension, alimentation:240V
LAMP, LOW ENERGY, CANDLE, BC, 5W; Tension, alimentation:240V; Puissance:5W; Longueur:120mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:120mm; Puissance GLS équivalente:30W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, MINI, ES, 8W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:8W; Longueur:112mm; Diamètre de l'ampoule:40mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:40mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:112mm; Puissance GLS équivalente:40W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
FLUORESCENT LAMP, SPIRAL, BC, 20W; Tension, alimentation:240V; Puissance:20W; Longueur:138mm; Diamètre de l'ampoule:52mm; Température, couleur:2700K; Diamètre, extérieur:52mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:138mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
FLUORESCENT LAMP, SPIRAL, BC, 25W; Tension, alimentation:240V; Puissance:25W; Longueur:155mm; Diamètre de l'ampoule:53mm; Température, couleur:2700K; Diamètre, extérieur:53mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:155mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
FLUORESCENT LAMP, SPIRAL, ES, 25W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:25W; Longueur:155mm; Diamètre de l'ampoule:53mm; Température, couleur:2700K; Diamètre, extérieur:53mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:155mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
VOYANT NEON; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Clair; Diamètre trou de fixation:6.3mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Clair; Diamètre de découpe panneau:6.35mm; Epaisseur, panneau max..:6.35mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:250V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:13.5mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:13.5mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:250V
LAMP, E/SAVING, ES, 9W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:9W; Flux lumineux:45lm; Longueur:145mm; Diamètre de l'ampoule:41mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:41mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:145mm; Puissance GLS équivalente:40W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, CANDLE, SES, 5W; Tension, alimentation:240V; Puissance:5W; Longueur:120mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:120mm; Puissance GLS équivalente:30W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, CANDLE, ES, 7W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:7W; Longueur:130mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:130mm; Puissance GLS équivalente:40W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, CANDLE, ES, 11W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:11W; Longueur:130mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:130mm; Puissance GLS équivalente:60W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
FLUORESCENT LAMP, SPIRAL, ES, 11W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:11W; Longueur:113mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:113mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
VOYANT NEON; Tension, alimentation:130V; Lamp Base Type:Fil; Couleur:Clair; Diamètre trou de fixation:6.3mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Clair; Diamètre de découpe panneau:6.35mm; Epaisseur, panneau max..:6.35mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:130V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:13.5mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Diamètre de découpe panneau:13.5mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:250V
VOYANT NEON; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Clair; Diamètre trou de fixation:13.5mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Clair; Diamètre de découpe panneau:13.5mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:250V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:9mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:9mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:50mm; Tension d'alimentation Vac:250V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:40mm; Tension d'alimentation Vac:250V
LAMP, 2D, 38W, 4PIN, 3500K; Tension, alimentation:110V; Lamp Base Type:GR10q; Puissance:38W; Flux lumineux:2700lm; Longueur:207mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011); Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Flux lumineux typique:2700lm; Intensité lumineuse, max..:2700lm; Largeur (externe):205mm; Longueur/hauteur:207mm; Nombre de broches:4; Tension d'alimentation Vac:230V
LAMP, 2D, 16W, 2PIN, 2700K; Tension, alimentation:103V; Lamp Base Type:GR8; Puissance:16W; Flux lumineux:1050lm; Longueur:141mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Flux lumineux typique:1050lm; Intensité lumineuse, max..:1050lm; Largeur (externe):138mm; Longueur/hauteur:141mm; Nombre de broches:2; Tension d'alimentation Vac:230V
LAMP, 2D, 28W, 4PIN, 3500K; Tension, alimentation:108V; Lamp Base Type:GR10q; Puissance:28W; Flux lumineux:2050lm; Longueur:207mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011); Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Flux lumineux typique:2050lm; Intensité lumineuse, max..:2050lm; Largeur (externe):205mm; Longueur/hauteur:207mm; Nombre de broches:4; Tension d'alimentation Vac:230V
VOYANT; Taille de lampe:7.6mm; Tension, alimentation:14V; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Diamètre de découpe panneau:6.3mm; Dimension de la lentille:7.6mm; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:14V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:12mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Ambre; Diamètre de découpe panneau:12mm; Diamètre, lentille:13.6mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:40mm; Tension d'alimentation Vac:250V
LAMP, LOW ENERGY, CANDLE, SES, 3W; Tension, alimentation:240V; Puissance:3W; Longueur:120mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:120mm; Puissance GLS équivalente:20W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, CANDLE, BC, 7W; Tension, alimentation:240V; Puissance:7W; Longueur:130mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:130mm; Puissance GLS équivalente:40W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, CANDLE, SES, 7W; Tension, alimentation:240V; Puissance:7W; Longueur:130mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:130mm; Puissance GLS équivalente:40W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, CANDLE, BC, 11W; Tension, alimentation:240V; Puissance:11W; Longueur:130mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:130mm; Puissance GLS équivalente:60W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, MINI, SES, 5W; Tension, alimentation:240V; Puissance:5W; Longueur:124mm; Diamètre de l'ampoule:40mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:40mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:124mm; Puissance GLS équivalente:25W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, LOW ENERGY, MINI, ES, 14W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:14W; Longueur:132mm; Diamètre de l'ampoule:40mm; Température, couleur:2700K; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:40mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:132mm; Puissance GLS équivalente:75W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP, GLOBE, BC, 168MM, B22, 20W; Tension, alimentation:240V; Puissance:20W; Longueur:168mm; Diamètre de l'ampoule:110mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:110mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:168mm; Puissance GLS équivalente:100W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
FLUORESCENT LAMP, SPIRAL, BC, 15W; Tension, alimentation:240V; Puissance:15W; Longueur:128mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:128mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
FLUORESCENT LAMP, SPIRAL, ES, 15W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:15W; Longueur:128mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:128mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
FLUORESCENT LAMP, SPIRAL, ES, 20W; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:20W; Longueur:138mm; Diamètre de l'ampoule:52mm; Température, couleur:2700K; Diamètre, extérieur:52mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:138mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:6.3mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Ambre; Diamètre de découpe panneau:6.35mm; Epaisseur, panneau max..:6.35mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:250V
VOYANT NEON AMBRE; Taille de lampe:7.6mm; Tension, alimentation:130V; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:Ambre; Diamètre de découpe panneau:6.35mm; Epaisseur, panneau max..:6.35mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:130V
VOYANT NEON AMBRE; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:19mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:130V
VOYANT NEON TRANSPARENT; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Clair; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Clair; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:19mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:130V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:12mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Diamètre de découpe panneau:12mm; Diamètre, lentille:13.6mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:38.2mm; Tension d'alimentation Vac:250V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:12mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:12mm; Diamètre, lentille:13.6mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:38.2mm; Tension d'alimentation Vac:250V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:12mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:12mm; Diamètre, lentille:13.6mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:40mm; Tension d'alimentation Vac:250V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:6.3mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:6.35mm; Epaisseur, panneau max..:6.35mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:250V
VOYANT NEON VERT; Tension, alimentation:130V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:6.3mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:6.35mm; Epaisseur, panneau max..:6.35mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:130V
BATTEN, TWIN, 36W, 4FT, S/S; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:36W; Longueur:1.24m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; Couleur:White; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP20; Largeur (externe):89mm; Light Source:Fluorescente; Longueur/hauteur:1238mm; Profondeur:92mm; Profondeur:92mm
EXIT SIGN, MAINTAINED, 8W; Longueur:360mm; Largeur:184mm; Profondeur:70mm; Température de fonctionnement max..:+25°C; IP / NEMA Rating:IP20; Durée de vie (fonctionnement):3 Hours; Lamp Base Type:G5; Largeur (externe):360mm; Longueur/hauteur:184mm; Poids:2.10kg; Profondeur:70mm; Puissance:8W; Tension, alimentation:230V
BULKHEAD, SQUARE, IP65, OPAL, 28W; Longueur:254mm; Largeur:254mm; Profondeur:95mm; Couleur:Blanc; IP / NEMA Rating:IP65; Lamp Base Type:GR10q; Poids:1.4kg; Puissance:28W; Tension, alimentation:230V
VOYANT NEON AMBRE; Tension, alimentation:130V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Ambre; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:40mm; Tension d'alimentation Vac:130V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:8mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:8mm; Epaisseur, panneau max..:1.6mm; Epaisseur, panneau min.:0.8mm; Longueur/hauteur:41mm; Tension d'alimentation Vac:250V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:8mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Ambre; Diamètre de découpe panneau:8mm; Epaisseur, panneau max..:1.6mm; Epaisseur, panneau min.:0.8mm; Longueur/hauteur:41mm; Tension d'alimentation Vac:250V
VOYANT; Taille de lampe:7.6mm; Tension, alimentation:28V; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; Diamètre de découpe panneau:6.3mm; Dimension de la lentille:7.6mm; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:28V
BATTEN, TWIN, 70W, 6FT, S/S; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:70W; Longueur:1.8m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; Couleur:White; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP20; Largeur (externe):89mm; Light Source:Fluorescente; Longueur/hauteur:1802mm; Profondeur:92mm; Profondeur:92mm
BULKHEAD, 8W, NON-MAINTAINED, IP65; Longueur:390mm; Largeur:110mm; Profondeur:90mm; Température de fonctionnement max..:+25°C; IP / NEMA Rating:IP65; Couleur, base:White; Durée de vie (fonctionnement):3 Hours; Lamp Base Type:G5; Largeur (externe):110mm; Longueur/hauteur:390mm; Poids:1.80kg; Profondeur:90mm; Puissance:8W; Tension, alimentation:230V
FLUORESCENT FITTING, IP65, 1X58W; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:58W; Longueur:1.57m; Diamètre de l'ampoule:26mm; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP65; Largeur (externe):100mm; Light Source:Fluorescente; Longueur/hauteur:1570mm; Profondeur:101mm; Profondeur:101mm
FLUORESCENT FITTING, IP65, 2X58W; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:58W; Longueur:1.57m; Diamètre de l'ampoule:26mm; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP65; Largeur (externe):160mm; Light Source:Fluorescente; Longueur/hauteur:1570mm; Profondeur:101mm; Profondeur:101mm
FLOODLIGHT, GALAXY, SON-E/I, 70W; Longueur:375mm; Largeur:300mm; Profondeur:190mm; IP / NEMA Rating:IP65; Couleur, base:Black; Largeur (externe):300mm; Longueur/hauteur:322mm; Matière:Polycarbonate; Poids:3.5kg; Profondeur:190mm; Puissance:70W; Tension, alimentation:230V
LAMP, 2D, 38W, 4PIN, 2700K; Puissance:38W; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011)
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:2 broches; Couleur:Vert; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:Vert / Noir; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.75mm; Tension d'alimentation Vac:250V; Type de terminaison:Faston Tab
VOYANT; Taille de lampe:7.6mm; Tension, alimentation:28V; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:Ambre; Diamètre de découpe panneau:6.3mm; Dimension de la lentille:7.6mm; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:28V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Ambre; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Epaisseur, panneau max..:3mm; Epaisseur, panneau min.:0.75mm; Tension d'alimentation Vac:250V
BATTEN, SINGLE, 58W, 5FT, S/S; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:58W; Longueur:1.54m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; Couleur:White; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP20; Largeur (externe):58mm; Light Source:Fluorescente; Longueur/hauteur:1538mm; Profondeur:92mm; Profondeur:92mm
BULKHEAD, 8W, NON-MAINTAINED, IP65; Longueur:351mm; Largeur:95mm; Profondeur:75mm; Température de fonctionnement max..:+25°C; IP / NEMA Rating:IP65; Couleur, base:White; Durée de vie (fonctionnement):3 Hours; Lamp Base Type:G5; Largeur (externe):95mm; Longueur/hauteur:351mm; Poids:1.20kg; Profondeur:75mm; Puissance:8W; Tension, alimentation:230V
LIGHT, LOWBAY, SON-E, 250W; Longueur:600mm; Largeur:318mm; Profondeur:184mm; IP / NEMA Rating:IP20; Lamp Base Type:E40; Largeur (externe):318mm; Longueur/hauteur:600mm; Matière:Aluminium; Poids:12kg; Profondeur:184mm; Puissance:250W; Tension, alimentation:230V
VOYANT NEON VERT; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:19mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:130V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Vert; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Epaisseur, panneau max..:3mm; Epaisseur, panneau min.:0.75mm; Tension d'alimentation Vac:250V
BATTEN, SINGLE, 36W, 4FT, S/S; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:36W; Longueur:1.24m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; Couleur:White; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP20; Largeur (externe):58mm; Light Source:Fluorescente; Longueur/hauteur:1238mm; Profondeur:92mm; Profondeur:92mm
BATTEN, SINGLE, 70W, 6FT, S/S; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:70W; Longueur:1.8m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; Couleur:White; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP20; Largeur (externe):58mm; Light Source:Fluorescente; Longueur/hauteur:1802mm; Profondeur:92mm; Profondeur:92mm
BATTEN, TWIN, 58W, 5FT, S/S; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:58W; Longueur:1.54m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; Couleur:White; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP20; Largeur (externe):89mm; Light Source:Fluorescente; Longueur/hauteur:1538mm; Profondeur:92mm; Profondeur:92mm
BATTEN, SINGLE, 58W, 5FT, HF; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:58W; Longueur:1.54m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; Couleur:White; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP20; Largeur (externe):58mm; Light Source:Fluorescente; Longueur/hauteur:1538mm; Profondeur:92mm; Profondeur:92mm
BATTEN, TWIN, 70W, 6FT, HF; Tension, alimentation:230V; Lamp Base Type:G13; Puissance:70W; Longueur:1.8m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; Couleur:White; Diamètre, tube fluorescent:26mm; IP / NEMA Rating:IP20; Largeur (externe):89mm; Light Source:Fluorescente; Longueur/hauteur:1802mm; Profondeur:92mm; Profondeur:92mm
SPOT LIGHT, TWIN, EMERGENCY, 2X18W; Longueur:355mm; Largeur:360mm; Profondeur:80mm; Température de fonctionnement max..:+25°C; IP / NEMA Rating:IP20; Durée de vie (fonctionnement):3 Hours; Lamp Base Type:Culot Wedge; Largeur (externe):360mm; Longueur/hauteur:355mm; Poids:7.0kg; Profondeur:80mm; Puissance:18W; Tension, alimentation:230V
VOYANT NEON VERT; Tension, alimentation:130V; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:40mm; Tension d'alimentation Vac:130V
FLOODLGHT, PRTBL, 38A/H, WITH TRIPOD; Couleur:Black; Durée de vie (fonctionnement):3h high 6h low; Intensité lumineuse, max..:11600lm; Light Source:Fluorescente; Matière:ABS; Tension, alimentation:12V
HCI-TT POWERBALL 150W WDL; Longueur:210mm; Diamètre de l'ampoule:46mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Couleur:Warm White; Lamp Base Type:E40; Puissance:148W
DETECTEUR PRSCE IR FLUSH 2000W 2 CANAUX; Angle de faisceau:360°; Longueur:52mm; Largeur:80mm; Profondeur:80mm; Distance de détection max..:7m; IP / NEMA Rating:IP40; Lamp Base Type:Incandescent / Halogène; Largeur (externe):80mm; Longueur/hauteur:52mm; Profondeur:80mm; Puissance:2kW; Tension, alimentation:230V
DETECTEUR DE PRESENCE IR 2000W 2 CANAUX; Angle de faisceau:360°; Largeur:121.5mm; Distance de détection max..:7m; IP / NEMA Rating:IP40; Lamp Base Type:Incandescent / Halogène; Largeur (externe):121.5mm; Longueur/hauteur:42.5mm; Profondeur:121.5mm; Puissance:2kW; Tension, alimentation:230V
DETECTEUR DE PRESENCE IR FLUSH 2000W; Angle de faisceau:360°; Longueur:52mm; Largeur:80mm; Profondeur:80mm; Distance de détection max..:7m; IP / NEMA Rating:IP40; Lamp Base Type:Incandescent / Halogène; Largeur (externe):80mm; Longueur/hauteur:52mm; Profondeur:80mm; Puissance:2kW; Tension, alimentation:230V
INCANDESCENT LAMP 21VDC; Tension, alimentation:21V; Lamp Base Type:GX5,3; Puissance:150W; Durée de vie moyenne de la lampe:200h; Durée de vie:200h; Longueur/hauteur:44.5mm
TUNGSTEN HALOGEN, 150 WATT; Tension, alimentation:15V; Lamp Base Type:GZ6,35; Puissance:150W; Diamètre, réflecteur:51mm
HCI-TT POWERBALL 70W WDL; Longueur:155mm; Diamètre de l'ampoule:30mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Couleur:Warm White; Lamp Base Type:E27; Puissance:74W
CAPTEUR IR 360° MONTAGE MURAL; Angle de faisceau:360°; Longueur:53mm; Largeur:103mm; Profondeur:103mm; Couleur:White; Fréquence:50Hz; Gamme:6m; Largeur (externe):103mm; Tension, contact c.a. max..:230V; Type de montage:Montage en surface
LAMP, MASCHINE 10-40 V DC; Tension, alimentation:40V; Puissance:12W; Light Source:LED; Longueur:284mm; Couleur:White; Couleur:Blanc; IP / NEMA Rating:IP67; Poids:1kg; Safety Category:III
LAMP MOBILE POWER JET-LIGHT 3X36W ; Tension, alimentation:230V; Lamp Base Type:R7s; Puissance:108W; Longueur:42mm; SVHC:No SVHC (19-Dec-2011); Hauteur:19cm; IP / NEMA Rating:IP44; Intensité lumineuse:2770mcd; Largeur (externe):32cm; Longueur cordon:1.5m; Poids:2kg; Profondeur:23cm; Tension d'alimentation Vac:230V
PLAFONNIER FLUORESCENT T4 16W; Tension, alimentation:230V; Lamp Base Type:T4; Puissance:16W; Longueur:520mm; Température, couleur:3400K; SVHC:No SVHC (19-Dec-2011); Couleur:White; Hauteur:43mm; IP / NEMA Rating:IP20; Largeur (externe):19mm; Longueur cordon:2m; Longueur/hauteur:520mm; Matière:Plastic; Tension d'alimentation Vac:230V
SPOT LV; Profondeur:117mm; SVHC:No SVHC (19-Dec-2011); Couleur:Nickel brossé; Diamètre de découpe panneau:73mm; Diamètre, extérieur:83mm; IP / NEMA Rating:IP65; Lamp Base Type:GU5,3; Light Source:Halogène; Matière:Acier; Puissance:50W; Tension, alimentation:12V
PLAFONNIER FLUORESCENT T4 10W; Tension, alimentation:230V; Lamp Base Type:T4; Puissance:10W; Longueur:390mm; Température, couleur:3400K; SVHC:No SVHC (19-Dec-2011); Couleur:White; Hauteur:43mm; IP / NEMA Rating:IP20; Largeur (externe):19mm; Longueur cordon:2m; Longueur/hauteur:390mm; Matière:Plastic; Tension d'alimentation Vac:230V
PROJECTEUR 2X26W; Longueur:275mm; Largeur:215mm; Profondeur:112mm; IP / NEMA Rating:IP44; SVHC:No SVHC (19-Dec-2011); Light Source:Fluorescente compacte; Matière:ABS
PROJECTEUR 2X26W; Longueur:275mm; Largeur:215mm; Profondeur:112mm; IP / NEMA Rating:IP44; SVHC:No SVHC (19-Dec-2011); Light Source:Fluorescente compacte; Matière:ABS
RBK EMERY CLOTH SHEETS FF; Longueur:380mm; Hauteur:280mm; Largeur (externe):230mm; Longueur/hauteur:380mm; Normes:Flexible; Profondeur:14mm; Taille du grain:F2
FLOODLIGHT, SAFELUX, 38W; Longueur:280mm; Largeur:280mm; Profondeur:80mm; IP / NEMA Rating:IP54; Light Source:Fluorescente compacte; Matière:Polycarbonate
PROJECTEUR 57W AVEC CELLULE PHOTO; Longueur:160mm; Largeur:285mm; Profondeur:145mm; IP / NEMA Rating:IP65; SVHC:No SVHC (19-Dec-2011); Light Source:Fluorescente; Matière:Polycarbonate
PROJECTEUR 24W BASSE ENERGIE; Longueur:135mm; Largeur:210mm; Profondeur:100mm; IP / NEMA Rating:IP44; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:Black; Light Source:Fluorescente; Matière:Polycarbonate
PROJECTEUR PIR 23W BASSE ENERGIE; Longueur:135mm; Largeur:210mm; Profondeur:100mm; IP / NEMA Rating:IP44; SVHC:No SVHC (19-Dec-2011); Light Source:Fluorescente; Matière:Polycarbonate
LAMPS, INCANDESCENT 6.5V; Tension, alimentation:6.5V; Lamp Base Type:S8; Taille de lampe:26mm; Puissance:17.9W; MSCP:23; Durée de vie moyenne de la lampe:100h; Courant:2.75A; Dimension de la lentille:S-8; Durée de vie:100h; Longueur/hauteur:51mm
HALOGEN LAMPS 24VDC; Tension, alimentation:24V; Lamp Base Type:G 6,35; Puissance:150W; SVHC:No SVHC (20-Jun-2011)
PACK LEGENDE; Longueur:220mm; Largeur:108mm; SVHC:No SVHC (19-Dec-2011)
PLAFONNIER FLUORESCENT T4 20W; Tension, alimentation:230V; Lamp Base Type:T4; Puissance:20W; Longueur:620mm; Température, couleur:3400K; SVHC:No SVHC (19-Dec-2011); Couleur:White; Hauteur:43mm; IP / NEMA Rating:IP20; Largeur (externe):19mm; Longueur cordon:2m; Longueur/hauteur:620mm; Matière:Plastic; Tension d'alimentation Vac:230V
PROJECTEUR PORTABLE. UK
SPOT LV. BLANC; Profondeur:117mm; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Diamètre de découpe panneau:73mm; Diamètre, extérieur:83mm; IP / NEMA Rating:IP65; Lamp Base Type:GU5,3; Light Source:Halogène; Matière:Acier; Puissance:50W; Tension, alimentation:12V
BATTEN, FLUORESCENT, T5, 35W; Tension, alimentation:230V; Lamp Base Type:G5; Puissance:35W; Flux lumineux:3300lm; Longueur:1.48m; Diamètre de l'ampoule:38mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:38mm
FLUORESCENT LAMP, TRIPLE, 42W, UK PLG; Lamp Base Type:Pince; Puissance:250W; Light Source:3 x tube économie d'énergie 14W; SVHC:No SVHC (19-Dec-2011)
T6.8 SLIDE BASE VERT 28VDC; Couleur de LED:Vert; Longueur d'onde typ.:527nm; Intensité lumineuse:23cd; Puissance:625mW; Taille de lampe:T-6 4/5; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:28V
T6.8 SLIDE BASE WHITE 28VDC; Couleur de LED:Blanc froid; Température de couleur proximale:8000K; Intensité lumineuse:14cd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:28V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:10mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Diamètre de découpe panneau:10mm; Diamètre, lentille:13.2mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:57.8mm; Tension d'alimentation Vac:250V
VOYANT NEON VERT; Tension, alimentation:130V; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Diamètre de découpe panneau:10mm; Diamètre, lentille:13.2mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:57.8mm; Tension d'alimentation Vac:130V
TETE DE VOYANT BA 9S; Lamp Base Type:BA9s; SVHC:Bis (2-ethylhexyl)phthalate (DEHP) (19-Dec-2011); Couleur:Red; Diamètre de découpe panneau:22mm
T6.8 SLIDE BASE BLEU 24VDC; Couleur de LED:Bleu; Longueur d'onde typ.:470nm; Intensité lumineuse:7000mcd; Puissance:625mW; Taille de lampe:T-6 4/5; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Tension, direct If:24V
LAMP, IR, 10M; Longueur:60mm; Largeur:49mm; Courant:450mA; Courant, fonctionnement c.c.:450mA; Light Source:LED; Longueur/hauteur:60mm; Tension, alimentation:12VDC; Tension, alimentation c.c.:12V
LUMINAIRE, 3-ARM, ES, 60W, IP20; Tension, alimentation:240V; Puissance:60W; Light Source:Å” incandescence; Longueur:1.05m; Diamètre, lentille:127mm; Longueur (max..):1050mm
ACCESSORIES FOR 3SB3; Lamp Base Type:BA9s; Couleur de LED:Blanc; Tension, alimentation:24V; Courant:15mA; Série:3SB3; Tension, résistance d'isolation:400V; Tension, vérification:5V
BASE, WHT, SCREW; Couleur:White
LENS
NIGHT LIGHT, DUSK/DAWN; Longueur:120mm; Largeur:50mm; Profondeur:70mm; Température de fonctionnement max..:+40°C; Puissance:7W; Tension, alimentation:240VAC
SPARE LAMPS FOR NIGHT LIGHT; Tension, alimentation:230V; Lamp Base Type:E14; Puissance:7W; Couleur:Clear; Tension:240VAC
INSPECTION LIGHT, ARM, 700MM; Tension, alimentation:12V; Puissance:50W; Light Source:Halogène; Longueur:700mm; Diamètre, lentille:95mm; Couleur, base:Noir; IP / NEMA Rating:IP65; Longueur (max..):700mm; Longueur cordon:2m; Matière:Polycarbonate
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:10mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:10mm; Diamètre, lentille:13.2mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:57.8mm; Tension d'alimentation Vac:250V
CORPS COMPLET; Lamp Base Type:BA9s; Tension, alimentation:250V; Puissance:2.4W; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge; Diamètre de découpe panneau:22mm; Largeur, découpe panneau:30mm; Longueur, découpe panneau:46.5mm; Profondeur, derrière panneau:43mm; Tension, alimentation max..:250V
VOYANT NEON; Tension, alimentation:130V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:8mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:8mm; Epaisseur, panneau max..:1.6mm; Epaisseur, panneau min.:0.8mm; Longueur/hauteur:41mm; Tension d'alimentation Vac:130V
VOYANT NEON VERT; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:12mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:12mm; Diamètre, lentille:13.6mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:38.2mm; Tension d'alimentation Vac:130V
VOYANT NEON AMBRE; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:12mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Diamètre de découpe panneau:12mm; Diamètre, lentille:13.6mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:38.2mm; Tension d'alimentation Vac:130V
LAMP, 6V, 15W; Tension, alimentation:6V; Puissance:15W; Tension:6V; Tension c.a.:6V
HALOGEN LAMP, 24V, 20W; Tension, alimentation:24V; Puissance:20W; Tension, alimentation c.c. max..:24V
PROJECTEUR AVEC DETECTEUR DE MOUV.; Angle de faisceau:110°; Longueur:255mm; Largeur:110mm; Profondeur:110mm; Couleur:Blanc; Distance de détection max..:8m; IP / NEMA Rating:IP44; Lamp Base Type:BC (capuchon baèonnette); Largeur (externe):110mm; Longueur/hauteur:275mm; Profondeur:100mm; Puissance:60W; Tension, alimentation:240V; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:8mm; Courant:40mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:8mm; Longueur/hauteur:37.9mm; Tension d'alimentation Vac:250V
LAMP, 2W, 24V; Tension, alimentation:30V; Lamp Base Type:BA9s; Taille de lampe:28mm; Puissance:2W; Dimension de la lentille:28mm; Longueur/hauteur:28mm; Tension c.a.:30V; Tension, résistance d'isolation:400V; Tension, vérification:5V
LAMP, BA, 9S, 110-130V; Tension, alimentation:130V; Lamp Base Type:BA9s; Puissance:2.5W; Longueur/hauteur:28mm; Tension c.a.:130V; Tension, résistance d'isolation:400V; Tension, vérification:5V
ACCESSORIES FOR 3SB3; Lamp Base Type:BA9s; Couleur de LED:Rouge; Tension, alimentation:24V; Courant:15mA; Série:3SB3; Tension, résistance d'isolation:400V; Tension, vérification:5V
INSPECTION LAMP, SW., 8W, EURO; Tension, alimentation:230V; Lamp Base Type:G5; Puissance:8W; Light Source:Fluorescente; Longueur:500mm; SVHC:No SVHC (19-Dec-2011); Longueur (max..):50cm; Longueur cordon:5m; Longueur/hauteur:50cm; Poids:0.480kg; Tension d'alimentation Vac:230V
ECLAIRAGE EXTERIEUR FLUORESCENT; Longueur:247mm; Largeur:126mm; Profondeur:110mm; Couleur:Noir; Couleur, base:Noir; Couleur, lentilles:Clair; IP / NEMA Rating:IP65; Lamp Base Type:Baèonnette; Matière:Polycarbonate; Normes:BS4533 Pt102.1; Puissance:18W; Tension, alimentation:240V; Tension d'alimentation Vac:240V
PROJECTEUR. 26W NOIR; Longueur:232mm; Largeur:278mm; Profondeur:122mm; IP / NEMA Rating:IP65; Couleur:Black; Lamp Base Type:2 broches; Largeur (externe):278mm; Light Source:Fluorescente; Longueur/hauteur:232mm; Matière:Polycarbonate; Profondeur:122mm; Puissance:26W; Tension, alimentation:230V
PROJECTEUR. 26W NOIR + PHOTOELECTRIQUE; Longueur:232mm; Largeur:278mm; Profondeur:122mm; IP / NEMA Rating:IP65; Couleur:Black; Lamp Base Type:2 broches; Largeur (externe):278mm; Light Source:Fluorescente; Longueur/hauteur:232mm; Matière:Polycarbonate; Profondeur:122mm; Puissance:26W; Tension, alimentation:230V
LAMP, SPARE, RECHARGEABLE; Puissance:11W; Couleur:Clear
VOYANT NEON VERT; Tension, alimentation:125V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:6.4mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Fil; Couleur:Green; Diamètre de découpe panneau:6.4mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:125V
VOYANT NEON VERT; Tension, alimentation:240V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:6.4mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Fil; Couleur:Green; Diamètre de découpe panneau:6.4mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:240V
VOYANT NEON AMBRE; Tension, alimentation:240V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:6.4mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Fil; Couleur:Ambre; Diamètre de découpe panneau:6.4mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:240V
T6.8 SLIDE BASE BLEU 28VDC; Couleur de LED:Bleu; Longueur d'onde typ.:470nm; Intensité lumineuse:7cd; Puissance:625mW; Taille de lampe:T-6 4/5; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:28V
T6.8 SLIDE BASE WARM WHITE 28VDC; Couleur de LED:Blanc chaud; Intensité lumineuse:9.2cd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:28V
LAMP HOLDER, DIRECT, 130V, 22MM; Lamp Base Type:BA9s; Tension, alimentation:130V; Diamètre de découpe panneau:22.5mm
O/D LIGHTS - 40 CLEAR CHAS.
LAMP, PAR36; Tension, alimentation:6.4V; Puissance:30W; Durée de vie moyenne de la lampe:100h; Angle:5°; Diamètre, extérieur:115mm; Dimension de la lentille:115mm; Durée de vie:100h; Longueur/hauteur:70mm; Tension:6.4V; Tension c.a.:6.4V
PROJECTEUR. 42W NOIR + PHOTOELECTRIQUE; Longueur:232mm; Largeur:278mm; Profondeur:122mm; IP / NEMA Rating:IP65; Couleur:Black; Lamp Base Type:4 broches; Largeur (externe):278mm; Light Source:Fluorescente; Longueur/hauteur:232mm; Matière:Polycarbonate; Profondeur:122mm; Puissance:42W; Tension, alimentation:230V
VOYANT NEON AMBRE; Tension, alimentation:240V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:10mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Fil; Couleur:Ambre; Diamètre de découpe panneau:10mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:31mm; Température de fonctionnement max..:180°C
VOYANT NEON AMBRE; Taille de lampe:15.6mm; Tension, alimentation:130V; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:Ambre; Diamètre de découpe panneau:10mm; Diamètre, lentille:13.2mm; Dimension de la lentille:15.6mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:57.8mm; Tension d'alimentation Vac:130V
TETE VERTE; Lamp Base Type:BA9s; SVHC:Bis (2-ethylhexyl)phthalate (DEHP) (19-Dec-2011); Couleur:Vert; Diamètre:22mm; Diamètre de découpe panneau:28.5mm; Profondeur, derrière panneau:11.5mm
LAMP, IR MEDIUM 20W
WORK LIGHT, 24V, 700MM; Tension, alimentation:24V; Puissance:20W; Light Source:Halogène; Longueur:700mm; Couleur:Noir; Diamètre, base:60mm; IP / NEMA Rating:IP20; Longueur (max..):960mm; Longueur/hauteur:960mm; Matière:Polycarbonate; Tension, alimentation c.c. max..:24V
PROJECTEUR AVEC DETECTEUR DE MOUV.; Angle de faisceau:110°; Longueur:255mm; Largeur:110mm; Profondeur:110mm; Couleur:Noir; Distance de détection max..:8m; IP / NEMA Rating:IP44; Lamp Base Type:BC (capuchon baèonnette); Largeur (externe):110mm; Longueur/hauteur:275mm; Profondeur:100mm; Puissance:60W; Tension, alimentation:240V; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
LAMP HOLDER, BA9S, BASE; Lamp Base Type:BA9s; Série:3SB3; Tension, résistance d'isolation:400V; Tension, vérification:5V
ACCESSORIES FOR 3SB3; Lamp Base Type:BA9s; Couleur de LED:Vert; Tension, alimentation:24V; Courant:15mA; Série:3SB3; Tension, résistance d'isolation:400V; Tension, vérification:5V
BENCH LIGHT, 2X24W; Type de fiche d'alimentation:UK; Lamp Base Type:G13; Puissance:24W
LAMP, IR MEDIUM 50W
HALOGEN LAMP, 24V, 50W; Tension, alimentation:24V; Lamp Base Type:Bi-broche; Puissance:50W; Tension, alimentation c.c.:24V
LAMP HOLDER, BA9S; Lamp Base Type:BA9s; Série:3SB3; Tension, résistance d'isolation:400V; Tension, vérification:5V
LAMP HOLDER, 230/240V; Série:3SB3; Tension, résistance d'isolation:400V; Tension, vérification:5V
ACCESSORIES FOR 3SB3; Lamp Base Type:BA9s; Couleur de LED:Jaune; Tension, alimentation:24V; Courant:15mA; Série:3SB3; Tension, résistance d'isolation:400V; Tension, vérification:5V
SIGNAL LAMP, TRANSPARENT, CLEAR; Taille de lampe:12.5mm; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / clear; Diamètre de découpe panneau:10mm; Dimension de la lentille:12.5mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, GREEN; Tension, alimentation:230V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:10mm; Base Type:Borne souder; Couleur:Transparent / Vert; Diamètre de découpe panneau:10mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, RED; Taille de lampe:12.5mm x 12.5mm; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / Rouge; Diamètre de découpe panneau:10mm; Dimension de la lentille:12.5mm x 12.5mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, CLEAR; Tension, alimentation:24V; Puissance:450mW; Diamètre de découpe panneau:5mm; Hauteur, dessus du panneau:1mm
SIGNAL LAMP; Tension, alimentation:230V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:14mm; Puissance:1.2W; Base Type:Borne souder; Couleur:Transparent / Rouge; Diamètre de découpe panneau:14mm; Hauteur, dessus du panneau:4mm
SIGNAL LAMP; Tension, alimentation:230V; Lamp Base Type:Borne souder; Couleur:Jaune; Diamètre trou de fixation:14mm; Puissance:1.2W; Base Type:Borne souder; Couleur:Transparent / Jaune; Diamètre de découpe panneau:14mm; Hauteur, dessus du panneau:4mm
SIGNAL LAMP, TRANSPARENT, RED; Tension, alimentation:230V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:10mm; Base Type:Borne souder; Couleur:Transparent / Rouge; Diamètre de découpe panneau:10mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, GREEN; Taille de lampe:16mm x 18.2mm; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / Vert; Diamètre de découpe panneau:10mm; Dimension de la lentille:18.2mm x 16mm; Hauteur, dessus du panneau:3mm
ECLAIRAGE EXTERIEUR; Light Source:BC GLS 100W; Longueur:247mm; Largeur:126mm; Profondeur:110mm; Couleur:Noir; Couleur, base:Noir; Couleur, lentilles:Clair; IP / NEMA Rating:IP65; Lamp Base Type:BC (capuchon baèonnette); Matière:Polycarbonate; Normes:BS4533 Pt102.1; Puissance:100W; Tension, alimentation:240V; Tension d'alimentation Vac:240V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:9.5mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Diamètre de découpe panneau:9.5mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:2.8mm; Longueur/hauteur:59.2mm; Tension d'alimentation Vac:250V
LUMINAIRE, 2-ARMS, ES, 60W, IP20; Puissance:60W; Light Source:Å” incandescence; Longueur:650mm; Diamètre, lentille:127mm; Diamètre, extérieur:127mm; Longueur (max..):650mm; Longueur/hauteur:650mm
LUMINAIRE, BENCH MOUNTED; Tension, alimentation:12V; Puissance:20W; Light Source:Halogène; Longueur:700mm; Consommation de puissance:20W; Couleur:Noir; Longueur (max..):600mm; Longueur/hauteur:600mm; Tension d'alimentation Vac:12V
VOYANT NEON AMBRE; Tension, alimentation:125V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:8mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Borne souder; Couleur:Ambre; Diamètre de découpe panneau:8mm; Longueur/hauteur:37.9mm; Tension d'alimentation Vac:125V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:8mm; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Diamètre de découpe panneau:8mm; Longueur/hauteur:37.9mm; Tension d'alimentation Vac:250V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:13mm; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Diamètre, extérieur:13mm; Diamètre, lentille:11.5mm; Epaisseur, panneau max..:4mm; Epaisseur, panneau min.:1.5mm; Longueur/hauteur:28.5mm; Tension d'alimentation Vac:250V
VOYANT NEON AMBRE; Tension, alimentation:125V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:6.4mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Fil; Couleur:Amber; Diamètre de découpe panneau:6.4mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:125V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:13mm; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre, extérieur:13mm; Diamètre, lentille:11.5mm; Epaisseur, panneau max..:4mm; Epaisseur, panneau min.:1.5mm; Longueur/hauteur:28.5mm; Tension d'alimentation Vac:250V
PROJECTEUR. 42W NOIR; Longueur:232mm; Largeur:278mm; Profondeur:122mm; IP / NEMA Rating:IP65; Couleur:Black; Lamp Base Type:4 broches; Largeur (externe):278mm; Light Source:Fluorescente; Longueur/hauteur:232mm; Matière:Polycarbonate; Profondeur:122mm; Puissance:42W; Tension, alimentation:230V
INSPECTION LAMP, 100W, 240V, ES; Tension, alimentation:240V; Puissance:100W; Light Source:Å” incandescence; Type de fiche d'alimentation:UK; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:110mm; IP / NEMA Rating:IP20; Longueur (max..):260mm; Longueur cordon:5m; Longueur/hauteur:260mm; Poids:840g; Tension d'alimentation Vac:240V
SIGNAL LAMP; Taille de lampe:15mm; Tension, alimentation:42V; Puissance:1.2W; Couleur:Noir; Diamètre de découpe panneau:16.2mm; Dimension de la lentille:15mm; Hauteur, dessus du panneau:7.5mm
SIGNAL LAMP, TRANSPARENT, RED; Taille de lampe:12.5mm; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / Rouge; Diamètre de découpe panneau:10mm; Dimension de la lentille:12.5mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, CLEAR; Tension, alimentation:230V; Lamp Base Type:Borne souder; Couleur:Clair; Diamètre trou de fixation:10mm; Base Type:Borne souder; Couleur:Transparent / clear; Diamètre de découpe panneau:10mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, YELLOW; Tension, alimentation:230V; Lamp Base Type:Borne souder; Couleur:Jaune; Diamètre trou de fixation:10mm; Base Type:Borne souder; Couleur:Transparent / Jaune; Diamètre de découpe panneau:10mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, YELLOW; Taille de lampe:16mm x 18.2mm; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / Jaune; Diamètre de découpe panneau:10mm; Dimension de la lentille:18.2mm x 16mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, YELLOW; Tension, alimentation:24V; Puissance:450mW; Couleur:Jaune; Diamètre de découpe panneau:5mm; Hauteur, dessus du panneau:1mm
SIGNAL LAMP, TRANSPARENT, RED; Taille de lampe:8.5mm; Tension, alimentation:24V; Puissance:840mW; Couleur:Transparent / Rouge; Diamètre de découpe panneau:7mm; Dimension de la lentille:8.5mm; Hauteur, dessus du panneau:5mm
SIGNAL LAMP, TRANSPARENT, GREEN; Taille de lampe:8.5mm; Tension, alimentation:24V; Puissance:840mW; Couleur:Transparent / Vert; Diamètre de découpe panneau:7mm; Dimension de la lentille:8.5mm; Hauteur, dessus du panneau:5mm
SIGNAL LAMP, TRANSPARENT, COLOURL; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / clear; Diamètre de découpe panneau:14mm; Hauteur, dessus du panneau:4mm
SIGNAL LAMP, TRANSPARENT, RED; Taille de lampe:18mm; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / Rouge; Diamètre de découpe panneau:14mm; Dimension de la lentille:18mm; Hauteur, dessus du panneau:4mm
NEON BULB; Tension, alimentation:220V; Lamp Base Type:BA9s; Courant:1.8mA; Couleur:Clear; Longueur/hauteur:24mm
SIGNAL LAMP, TRANSPARENT, GREEN; Taille de lampe:12.5mm; Lamp Base Type:Borne souder; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / Vert; Diamètre de découpe panneau:10mm; Dimension de la lentille:12.5mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, GREEN; Taille de lampe:12.5mm x 12.5mm; Lamp Base Type:Borne souder; Tension, alimentation:28V; Puissance:1.2W; Couleur:Transparent / Vert; Diamètre de découpe panneau:10mm; Dimension de la lentille:12.5mm x 12.5mm; Hauteur, dessus du panneau:3mm
SIGNAL LAMP, TRANSPARENT, GREEN; Tension, alimentation:24V; Puissance:450mW; Couleur:Vert; Diamètre de découpe panneau:5mm; Hauteur, dessus du panneau:1mm
NEON BULB; Tension, alimentation:220V; Lamp Base Type:E10; Courant:1.8mA; Couleur:Clear; Longueur/hauteur:28mm
CORPS DE VOYANT; Taille de lampe:T-5 1/2; Tension, alimentation:250V; Courant:6A; SVHC:No SVHC (19-Dec-2011); Contact Material:Argent, Plaqué or; Diamètre de découpe panneau:16.2mm; Dimension de la lentille:T5.5; Largeur (externe):24mm; Longueur/hauteur:18mm; Profondeur, derrière panneau:45mm
CORPS DE VOYANT; Taille de lampe:T-1 3/4; Tension, alimentation:250V; Courant:6A; SVHC:No SVHC (19-Dec-2011); Contact Material:Argent, Plaqué or; Diamètre de découpe panneau:16.2mm; Dimension de la lentille:T-1 3/4; Largeur (externe):24mm; Longueur/hauteur:18mm; Profondeur, derrière panneau:30mm
INDICATOR T1 ROUND; Taille de lampe:T-1; Lamp Base Type:Bi-broche; SVHC:No SVHC (19-Dec-2011); Diamètre de découpe panneau:8mm; Dimension de la lentille:T1; Largeur (externe):9mm; Longueur/hauteur:9mm; Profondeur:25mm; Température de fonctionnement max..:45°C; Température d'utilisation min:-25°C
INDICATOR T1 SQUARE; Taille de lampe:T-1; Lamp Base Type:Bi-broche; Tension, alimentation:72V; Courant:1A; SVHC:No SVHC (19-Dec-2011); Diamètre de découpe panneau:8mm; Dimension de la lentille:T1; Largeur (externe):9mm; Longueur/hauteur:9mm; Profondeur:25mm; Température de fonctionnement max..:45°C; Température d'utilisation min:-25°C; Tension, contact c.a. max..:42VAC; Tension, fonctionnement:42VDC
CORPS DE VOYANT; Taille de lampe:T-5 1/2; Tension, alimentation:250V; Courant:6A; SVHC:No SVHC (19-Dec-2011); Contact Material:Argent, Plaqué or; Diamètre de découpe panneau:16.2mm; Dimension de la lentille:T5.5; Largeur (externe):18mm; Longueur/hauteur:18mm; Profondeur, derrière panneau:45mm
BULB T1 3/4 28V; Tension, alimentation:28V; Lamp Base Type:Midget Groove; Taille de lampe:T-3 1/4; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:40mA; Dimension de la lentille:T-1 3/4; Durée de vie:10000h
400 W LAMP ENCLOSURE; SVHC:No SVHC (19-Dec-2011)
REPLACEMENT BULB 3W CREE FUTURE 3D+; SVHC:No SVHC (19-Dec-2011); Tailles de batterie acceptées:AAA, AA
PROJECTEUR 57W BASSE ENERGIE; Longueur:160mm; Largeur:285mm; Profondeur:145mm; IP / NEMA Rating:IP65; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:Black; Light Source:Fluorescente; Matière:Aluminium
SPOT GU10. BLANC; Profondeur:117mm; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Diamètre de découpe panneau:73mm; Diamètre, extérieur:83mm; IP / NEMA Rating:IP65; Lamp Base Type:GU10; Light Source:Halogène; Matière:Steel; Puissance:50W; Tension, alimentation:240V
SPOT GU10. CHROME; Profondeur:117mm; SVHC:No SVHC (19-Dec-2011); Couleur:Chrome poli; Diamètre de découpe panneau:73mm; Diamètre, extérieur:83mm; IP / NEMA Rating:IP65; Lamp Base Type:GU10; Light Source:Halogène; Matière:Steel; Puissance:50W; Tension, alimentation:240V
VOYANT; Taille de lampe:T-1 3/4; SVHC:No SVHC (19-Dec-2011); Diamètre de découpe panneau:18mm; Dimension de la lentille:T-1 3/4; Largeur (externe):18mm; Longueur/hauteur:18mm; Profondeur, derrière panneau:36mm
VOYANT; Taille de lampe:T-1 3/4; SVHC:No SVHC (19-Dec-2011); Diamètre de découpe panneau:18mm; Dimension de la lentille:T-1 3/4; Largeur (externe):24mm; Longueur/hauteur:18mm; Profondeur, derrière panneau:36mm
SENSOR, DULUX EL, 240V, E27, 15W; Tension, alimentation:240V; Lamp Base Type:E27; Puissance:15W; Flux lumineux:900lm; Longueur:140mm; Diamètre de l'ampoule:52mm; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:52mm; Durée de vie:15000h; Durée de vie moyenne de la lampe:15000h
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:15.9mm; Epaisseur, panneau max..:1.5mm; Epaisseur, panneau min.:0.8mm; Longueur/hauteur:35mm; Tension d'alimentation Vac:250V
VOYANT NEON AMBRE; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Ambre; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:15.9mm; Epaisseur, panneau max..:1.5mm; Epaisseur, panneau min.:0.8mm; Longueur/hauteur:35mm; Tension d'alimentation Vac:250V
VOYANT NEON VERT; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:9.5mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:9.5mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:2.8mm; Longueur/hauteur:59.2mm; Tension d'alimentation Vac:250V
RACCORD FLUORESCENT T5. 8W; Tension, alimentation:230V; Lamp Base Type:Fluorescent T5 300 mm; Puissance:8W; Longueur:345mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011)
VOYANT NEON VERT; Tension, alimentation:240V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:10mm; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:10mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:31mm; Température de fonctionnement max..:180°C
LAMP, 23W, E27; Tension, alimentation:240V; Puissance:23W; Flux lumineux:3000lm; SVHC:No SVHC (19-Dec-2011); Flux lumineux typique:3000lm; Tension d'alimentation Vac:240V
VOYANT NEON VERT; Tension, alimentation:125V; Lamp Base Type:Borne souder; Couleur:Vert; Diamètre trou de fixation:8mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Borne souder; Couleur:vert; Diamètre de découpe panneau:8mm; Longueur/hauteur:37.9mm; Tension d'alimentation Vac:125V
ULTRA SLIM ESD MAGNIFIER EU PLUG; Puissance:28W; Light Source:Fluorescente; Longueur:950mm; Diamètre, lentille:175mm; SVHC:No SVHC (19-Dec-2011)
INSPECTION LIGHT, EURO PLUG; Tension, alimentation:240V; Lamp Base Type:2 broches euro; Puissance:8W; Light Source:Fluorescente; Longueur:55mm; SVHC:Bis (2-ethylhexyl)phthalate (DEHP) (20-Jun-2011)
VOYANT A FILAMENT VERTICALE; Taille de lampe:6.7mm; Tension, alimentation:6V; Courant:40mA; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:vert; Diamètre de découpe panneau:6.4mm; Dimension de la lentille:6.7mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:6V
VOYANT A FILAMENT; Taille de lampe:6.7mm; Tension, alimentation:14V; Courant:40mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Diamètre de découpe panneau:6.4mm; Dimension de la lentille:6.7mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:14V
VOYANT A FILAMENT; Taille de lampe:6.7mm; Tension, alimentation:28V; SVHC:No SVHC (19-Dec-2011); Couleur:Ambre; Diamètre de découpe panneau:6.4mm; Dimension de la lentille:6.7mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:28V
VOYANT A FILAMENT; Taille de lampe:6.7mm; Tension, alimentation:14V; Courant:40mA; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:rouge; Diamètre de découpe panneau:6.4mm; Dimension de la lentille:6.7mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:14V
VOYANT A FILAMENT; Taille de lampe:6.7mm; Tension, alimentation:28V; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:rouge; Diamètre de découpe panneau:6.4mm; Dimension de la lentille:6.7mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:28V
DESK LIGHT, WHITE, UK PLUG; Lamp Base Type:G23; Puissance:11W; Light Source:Fluorescente compacte; Longueur:830mm; Type de fiche d'alimentation:UK; Longueur (max..):1155mm
DESK LIGHT, BLACK, UK PLUG; Lamp Base Type:G24; Puissance:11W; Light Source:Fluorescente compacte; Longueur:830mm; Type de fiche d'alimentation:UK; Longueur (max..):1155mm
FILAMENT BULB; Tension, alimentation:30V; Lamp Base Type:BA9s; Puissance:2W; Durée de vie moyenne de la lampe:10000h; Couleur:Clear; Courant:0.083A; Dimension de la lentille:11mm; Durée de vie:10000h; Longueur/hauteur:29mm; Tension:30V; Tension c.a.:30V
FILAMENT BULB; Tension, alimentation:24V; Lamp Base Type:S8,5; Puissance:3W; Durée de vie moyenne de la lampe:200h; Couleur:Clear; Dimension de la lentille:11.5mm; Durée de vie:200h; Longueur/hauteur:39mm; Tension:24V; Tension c.a.:24V
FILAMENT BULB; Tension, alimentation:28V; Lamp Base Type:T1/4; Taille de lampe:T-1/4; Puissance:840mW; Durée de vie moyenne de la lampe:5000h; Couleur:Clear; Courant:0.03A; Dimension de la lentille:4.3mm; Durée de vie:5000h; Longueur/hauteur:10.5mm; Tension:28V; Tension c.a.:28V
VOYANT A FILAMENT; Taille de lampe:6.7mm; Tension, alimentation:14V; Courant:40mA; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:Ambre; Diamètre de découpe panneau:6.4mm; Dimension de la lentille:6.7mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:14V
VOYANT A FILAMENT; Taille de lampe:6.7mm; Tension, alimentation:28V; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:vert; Diamètre de découpe panneau:6.4mm; Dimension de la lentille:6.7mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:28V
DESK LIGHT, WHITE, UK PLUG; Puissance:11W; Light Source:Fluorescente; Longueur:765mm; Type de fiche d'alimentation:UK; SVHC:No SVHC (19-Dec-2011); Couleur:White; Hauteur:765mm; Largeur (externe):290mm; Longueur cordon:1380mm; Longueur/hauteur:55cm; Poids:362g; Profondeur:240mm
DESK LIGHT, BLACK, UK PLUG; Puissance:11W; Light Source:Fluorescente; Longueur:765mm; Type de fiche d'alimentation:UK; SVHC:No SVHC (19-Dec-2011); Couleur:Black; Hauteur:765mm; Largeur (externe):290mm; Longueur cordon:1380mm; Longueur/hauteur:55cm; Poids:362g; Profondeur:240mm
FILAMENT BULB; Tension, alimentation:30V; Lamp Base Type:E14; Taille de lampe:BA15d; Puissance:4W; Durée de vie moyenne de la lampe:1000h; Couleur:Clear; Courant:0.165A; Dimension de la lentille:17mm; Durée de vie:1000h; Longueur/hauteur:57mm; Tension:30V; Tension c.a.:30V
FILAMENT BULB; Tension, alimentation:24V; Lamp Base Type:T4,5; Puissance:480mW; Durée de vie moyenne de la lampe:8000h; Couleur:Clear; Courant:0.02A; Dimension de la lentille:4.2mm; Durée de vie:8000h; Longueur/hauteur:16.5mm; Tension:24V; Tension c.a.:24V
FILAMENT BULB; Tension, alimentation:30V; Lamp Base Type:W2 x 4,6D; Puissance:1W; Durée de vie moyenne de la lampe:1000h; Couleur:Clear; Courant:0.04A; Dimension de la lentille:5mm; Durée de vie:1000h; Longueur/hauteur:20mm; Tension:30V; Tension c.a.:30V
LAMPE UNIVERSELLE POUR MACHINE WD211; Tension, alimentation:230V; Puissance:11W; Light Source:Fluorescente; Longueur:810mm; Couleur:Light grey RAL7035; IP / NEMA Rating:IP54; Tension d'alimentation Vac:230V
LAMPE UNIVERSELLE 36W SN136; Tension, alimentation:230V; Puissance:36W; Light Source:Fluorescente; Longueur:830mm; Couleur:Light grey RAL7035; IP / NEMA Rating:IP20; Tension d'alimentation Vac:230V
LAMPE TUBE ETANCHE RL70CE-124 24V; Tension, alimentation:24V; Puissance:24W; Light Source:Fluorescente; Longueur:639mm; IP / NEMA Rating:IP67; Tension, alimentation c.c.:24V
LAMPE LOUPE 22W RLL122; Tension, alimentation:230V; Puissance:22W; Light Source:Fluorescente; Longueur:873mm; Diamètre, lentille:120mm; Couleur:Light grey RAL7035; Tension d'alimentation Vac:230V
LAMPE LOUPE 9W ESD SNL319 A; Tension, alimentation:230V; Lamp Base Type:3 x fluocompact 9W; Puissance:9W; Light Source:Fluorescente; Longueur:830mm; Diamètre, lentille:162.11mm; Couleur:Mat black; Tension d'alimentation Vac:230V
AMPOULE 50W 12V CAPSULE GY6.35; Tension, alimentation:12V; Lamp Base Type:GY6,35; Puissance:50W; Longueur:44mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Intensité lumineuse, max..:910lm; Tension, alimentation c.c.:12V
INDICATEUR CORPS CARREE; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Courant:6A; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BEAB / CSA / UL / VDE; Contact Material:Argent; Courant de contact max.:6A; Dimension de la lentille:T-1 3/4; Durée de vie, mécanique:1000000; IP / NEMA Rating:IP65; Largeur (externe):18mm; Longueur/hauteur:18mm; Profondeur:42mm; Résistance d'isolement:50Mohm; Résistance, contact:10mohm; Température de fonctionnement max..:55°C; Température d'utilisation min:-20°C
INDICATEUR CORPS ROND; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Courant:6A; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BEAB / CSA / UL / VDE; Contact Material:Argent; Courant de contact max.:6A; Diamètre, encadrement:18mm; Dimension de la lentille:T-1 3/4; Durée de vie, mécanique:1000000; IP / NEMA Rating:IP65; Profondeur:42mm; Résistance d'isolement:50Mohm; Résistance, contact:10mohm; Température de fonctionnement max..:55°C; Température d'utilisation min:-20°C
LAMPE TUBE ETANCHE RL70 136H; Tension, alimentation:230V; Puissance:36W; Light Source:Fluorescente; Longueur:585mm; Tension, alimentation c.a. max..:230V; Tension, alimentation c.a. min:110V
LAMPE LOUPE + LENTILLE RLL122; Tension, alimentation:230V; Lamp Base Type:T-R29; Puissance:22W; Light Source:Fluorescente; Longueur:873mm; Diamètre, lentille:120mm
AMPOULE 50W 24V CAPSULE GY6.35; Tension, alimentation:24V; Lamp Base Type:GY6,35; Puissance:50W; Longueur:44mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Tension, alimentation c.c.:24V
BLOC D'ANGLE NOIR; Light Source:ES GLS 60W; Longueur:265mm; Largeur:95mm; Profondeur:95mm; SVHC:No SVHC (19-Dec-2011); Couleur:Noir; Hauteur:265mm; IP / NEMA Rating:IP44; Lamp Base Type:ES 60W; Matière:Cast Aluminium; Puissance:60W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
INDICATEUR CORPS RECTANGULAIRE; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Courant:6A; SVHC:No SVHC (19-Dec-2011); Contact Material:Argent; Courant de contact max.:6A; Dimension de la lentille:T-1 3/4; Durée de vie, mécanique:1000000; IP / NEMA Rating:IP65; Largeur (externe):24mm; Longueur/hauteur:18mm; Profondeur:42mm; Résistance d'isolement:50Mohm; Résistance, contact:10mohm; Température de fonctionnement max..:55°C; Température d'utilisation min:-20°C
SUPPORT POUR TUBE FLUO + DIFFUSEUR 36W; Tension, alimentation:230V; Lamp Base Type:T8; Puissance:36W; Longueur:1.23m; SVHC:No SVHC (19-Dec-2011); Couleur:White; Hauteur:95mm; IP / NEMA Rating:IP20; Largeur (externe):55mm; Light Source:Fluorescente; Longueur/hauteur:1235mm; Matière:Pressed Steel/Polycarbonate; Tension d'alimentation Vac:230V
LAMPE SPOT FLEXIBLE 20W 12V IP21; Tension, alimentation:12V; Lamp Base Type:Vis; Puissance:20W; Light Source:Halogène; Longueur:700mm; Diamètre, lentille:70mm; Couleur:Black; Diamètre, extérieur:70mm; IP / NEMA Rating:IP21; Longueur (max..):700mm; Longueur/hauteur:700mm; Tension, alimentation c.c.:12V
INDICATEUR METAL DIA. 29; Courant:16A; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BEAB / CSA / UL / VDE; Diamètre, extérieur:29mm; IP / NEMA Rating:IP65; Longueur/hauteur:60mm; Profondeur, derrière panneau:38mm; Température de fonctionnement max..:85°C; Température d'utilisation min:-20°C; Tension c.a.:250V; Type de borne:vis; peur, découpe panneau:22.5mm
BLOC AVEC VENTILATION; Light Source:BC 40W; Longueur:100mm; Largeur:231mm; Profondeur:72mm; SVHC:No SVHC (19-Dec-2011); Couleur:Noir; Hauteur:100mm; IP / NEMA Rating:IP44; Lamp Base Type:BC rond max. 45 mm 40W; Matière:Cast Aluminium; Puissance:40W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
BLOC DE SECURITE NOIR; Light Source:BC GLS 100W; Longueur:240mm; Largeur:133mm; Profondeur:102mm; SVHC:No SVHC (19-Dec-2011); Couleur:Noir; Hauteur:240mm; IP / NEMA Rating:IP65; Lamp Base Type:BC; Matière:Polycarbonate; Puissance:100W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
ENCASTRE BASSE TENSION CHROME POLI; Largeur:70mm; Profondeur:27mm; SVHC:No SVHC (19-Dec-2011); Couleur:Polished Chrome; Diamètre de découpe panneau:61mm; Diamètre, extérieur:70mm; IP / NEMA Rating:IP20; Lamp Base Type:G4 (M47) 20W; Largeur (externe):70mm; Light Source:Tungstène halogène; Longueur cordon:2.4m; Longueur/hauteur:27mm; Matière:Pressed Steel; Profondeur, derrière panneau:27mm; Puissance:20W; Tension, alimentation:12V; Tension, alimentation c.c.:12V
ENCASTRE BASSE TENSION NICKEL; Largeur:70mm; Profondeur:27mm; SVHC:No SVHC (19-Dec-2011); Couleur:Brushed Nickel; Diamètre de découpe panneau:61mm; Diamètre, extérieur:70mm; IP / NEMA Rating:IP20; Lamp Base Type:G4 (M47) 20W; Largeur (externe):70mm; Light Source:Tungstène halogène; Longueur cordon:2.4m; Longueur/hauteur:27mm; Matière:Pressed Steel; Profondeur, derrière panneau:27mm; Puissance:20W; Tension, alimentation:12V; Tension, alimentation c.c.:12V
ENCASTRE BASSE TENSION BLANC; Largeur:70mm; Profondeur:27mm; SVHC:No SVHC (19-Dec-2011); Couleur:White; Diamètre de découpe panneau:61mm; Diamètre, extérieur:70mm; IP / NEMA Rating:IP20; Lamp Base Type:G4 (M47) 20W; Largeur (externe):70mm; Light Source:Tungstène halogène; Longueur cordon:2.4m; Longueur/hauteur:27mm; Matière:Pressed Steel; Profondeur, derrière panneau:27mm; Puissance:20W; Tension, alimentation:12V; Tension, alimentation c.c.:12V
LAMPE; Largeur (externe):160mm; Longueur d'onde, crête:360nm; Longueur/hauteur:24mm; Profondeur:53mm; Puissance lumineuse:O.3W/cmË› 50mm; Tailles de batterie acceptées:4 x AA (not supplied)
SUPPORT POUR TUBE FLUO + DIFFUSEUR 58W; Tension, alimentation:230V; Lamp Base Type:T8; Puissance:58W; Longueur:1.53m; SVHC:No SVHC (19-Dec-2011); Couleur:White; Hauteur:95mm; IP / NEMA Rating:IP20; Largeur (externe):55mm; Light Source:Fluorescente; Longueur/hauteur:1535mm; Matière:Pressed Steel/Polycarbonate; Tension d'alimentation Vac:230V
LED GU10 240V T/C BLANC; Lamp Base Type:GU10; Couleur de LED:Blanc; Puissance:1.8W; Tension, alimentation:240V; Angle du faisceau:15°; Durée de vie moyenne de la lampe:30000h; Couleur:White; Couleur:Blanc; Couleur, LED:Blanc; Tension, Vf max..:240V; Tension d'alimentation Vac:240V
AMPOULE FLUO POUR RETROECLAIRAGE B22 25W; Tension, alimentation:230V; Puissance:25W; Longueur:140mm; Longueur/hauteur:140mm
LED MIN GROOVE 12V JAUNE; Lamp Base Type:Midget Groove; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:63mcd; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:30mA; Courant, fonctionnement c.a.:30mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lumineuse typique
LED MID GROOVE 24VAC/DC VERT; Lamp Base Type:Midget Groove; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:910mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Green; Couleur, LED:Vert; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumin
LED BA9S 28VAC/DC ROUGE; Lamp Base Type:BA9s; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:350mcd; Taille de lampe:10mm; Tension, alimentation:28V; Courant:13mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:350mcd;
LED BA9S 130VAC BLANC CLAIR; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:250mcd; Taille de lampe:10mm; Tension, alimentation:130V; Courant:5mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:5mA; Courant, fonctionnement c.a.:5mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:250mcd; Température de fonctionnement:-20°C +60°C; Température d
LED BA9S 230VAC VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:200mcd; Taille de lampe:10mm; Tension, alimentation:230V; Courant:3mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Green; Couleur, LED:Vert; Courant, direct, If:3mA; Courant, fonctionnement c.a.:3mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:200mcd; Longueur d'onde, crête:525nm; Températu
LED BA9S 230VAC BLANC CLAIR; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:150mcd; Taille de lampe:10mm; Tension, alimentation:230V; Courant:3mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:3mA; Courant, fonctionnement c.a.:3mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:150mcd; Température de fonctionnement:-20°C +60°C; Température d
LAMPE BA9S HALOGENE 12V; Tension, alimentation:12V; Lamp Base Type:BA9s; Puissance:10W; Longueur:33mm; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:BA9s; Durée de vie:240h; Durée de vie moyenne de la lampe:240h; Emission lumineuse, totale:200lm; Intensité lumineuse, max..:200lm; MSCP:15.9; Taille de lampe:BA9s; Tension c.a.:12V
LAMPE P13.5S 3.6V 0.3A; Tension, alimentation:3.6V; Lamp Base Type:P13,5s; Taille de lampe:11.5mm; MSCP:0.79; Durée de vie moyenne de la lampe:30h; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Courant:0.3A; Dimension de la lentille:P13.5S; Durée de vie:30h; Emission lumineuse, totale:10lm; Longueur/hauteur:32mm; Tension:3.6V; Tension c.a.:3.6V
LAMPE E10 2.4V 300MA; Tension, alimentation:2.4V; Lamp Base Type:E10; Taille de lampe:11.5mm; Durée de vie moyenne de la lampe:4h; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Courant:0.3A; Dimension de la lentille:11mm; Durée de vie:4h; Emission lumineuse, totale:6lm; Longueur/hauteur:24mm; Tension:2.4V; Tension c.a.:2.4V
LED MBC 24VAC/DC VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:567nm; Intensité lumineuse:170mcd; Taille de lampe:T-10; Tension, alimentation:24V; Courant:19mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Vert; Couleur, LED:Vert; Courant, direct, If:15mA; Courant, fonctionnement c.a.:19mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:T10; Durée de vie:60000h; In
LED MIN GROOVE 12V ROUGE; Lamp Base Type:Midget Groove; Couleur de LED:Rouge; Longueur d'onde typ.:635nm; Intensité lumineuse:36mcd; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:30mA; Courant, fonctionnement c.a.:30mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lumineuse typique:36
LED MID GROOVE 24VAC/DC BLANC DF; Lamp Base Type:Midget Groove; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumineuse typique:700mcd; L
LED MID GROOVE 28VAC/DC VERT; Lamp Base Type:Midget Groove; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:910mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Green; Couleur, LED:Vert; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumin
LED BA9S 24VAC/DC VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:1000mcd; Taille de lampe:10mm; Tension, alimentation:24V; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Green; Couleur, LED:Vert; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:1000mcd
LED BA9S 24VAC/DC BLANC CLAIR; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:750mcd; Taille de lampe:10mm; Tension, alimentation:24V; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:750mcd; Température de fonc
LED BA9S 28VAC/DC BLANC CLAIR; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:750mcd; Taille de lampe:10mm; Tension, alimentation:28V; Courant:13mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:750mcd; Température de fonc
LED BA9S 230VAC BLANC DIFF; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:75mcd; Taille de lampe:10mm; Tension, alimentation:230V; Courant:3mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:3mA; Courant, fonctionnement c.a.:3mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:75mcd; Température de fonctionnement:-20°C +60°C; Température de f
LED MBC 24VAC/DC ROUGE; Lamp Base Type:BA9s; Couleur de LED:Rouge; Longueur d'onde typ.:620nm; Intensité lumineuse:110mcd; Taille de lampe:T-10; Tension, alimentation:24V; Courant:19mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Rouge; Couleur, LED:Rouge; Courant, direct, If:15mA; Courant, fonctionnement c.a.:19mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:T10; Durée de vie:60000h
LED MBC 24VAC/DC JAUNE; Lamp Base Type:BA9s; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:120mcd; Taille de lampe:T-10; Tension, alimentation:24V; Courant:19mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Jaune; Couleur, LED:Jaune; Courant, direct, If:15mA; Courant, fonctionnement c.a.:19mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:T10; Durée de vie:60000h
LED MIN GROOVE 24V ROUGE; Lamp Base Type:Midget Groove; Couleur de LED:Rouge; Longueur d'onde typ.:620nm; Intensité lumineuse:36mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:14mA; Courant, fonctionnement c.a.:14mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lumine
LED MIN GROOVE 24V VERT; Lamp Base Type:Midget Groove; Couleur de LED:Vert; Longueur d'onde typ.:567nm; Intensité lumineuse:90mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:14mA; Courant, fonctionnement c.a.:14mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lumineu
LED MIN GROOVE 28V JAUNE; Lamp Base Type:Midget Groove; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:63mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:14mA; Courant, fonctionnement c.a.:14mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lum
LED MID GROOVE 12VAC/DC BLANC DF; Lamp Base Type:Midget Groove; Couleur de LED:Blanc; Intensité lumineuse:350mcd; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumineuse typique:350mcd; T
LED MID GROOVE 24VAC/DC BLEU; Lamp Base Type:Midget Groove; Couleur de LED:Bleu; Longueur d'onde typ.:470nm; Intensité lumineuse:350mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Blue; Couleur, LED:Bleu; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumine
LED MID GROOVE 24VAC/DC BLANC CL; Lamp Base Type:Midget Groove; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumineuse typique:700mcd; T
LED MID GROOVE 28VAC/DC ROUGE; Lamp Base Type:Midget Groove; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:330mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumi
LED MID GROOVE 28VAC/DC JAUNE; Lamp Base Type:Midget Groove; Couleur de LED:Jaune; Longueur d'onde typ.:587nm; Intensité lumineuse:280mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité l
LED MID GROOVE 28VAC/DC BLANC CL; Lamp Base Type:Midget Groove; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumineuse typique:700mcd; T
LED BA9S 28VAC/DC VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:1000mcd; Taille de lampe:10mm; Tension, alimentation:28V; Courant:13mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Green; Couleur, LED:Vert; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:1000mcd
LED BA9S 130VAC JAUNE; Lamp Base Type:BA9s; Couleur de LED:Jaune; Longueur d'onde typ.:587nm; Intensité lumineuse:100mcd; Taille de lampe:10mm; Tension, alimentation:130V; Courant:5mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:5mA; Courant, fonctionnement c.a.:5mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:100mcd; Longueur d'onde, crête:587nm; Tempé
LED BA9S 230VAC ROUGE; Lamp Base Type:BA9s; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:70mcd; Taille de lampe:10mm; Tension, alimentation:230V; Courant:3mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:3mA; Courant, fonctionnement c.a.:3mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:70mcd; Longueur d'onde, crête:630nm; Températur
LAMPE P13.5S HALOGENE 6.0V; Tension, alimentation:6V; Lamp Base Type:P13,5s; Longueur:32mm; SVHC:No SVHC (19-Dec-2011); Courant:1A; Dimension de la lentille:P13.5S; Durée de vie:100h; Durée de vie moyenne de la lampe:100h; Emission lumineuse, totale:100lm; Intensité lumineuse, max..:100lm; MSCP:7.95; Taille de lampe:P13.5S; Tension c.a.:6V
LAMPE P13.5S 3.6V 0.5A; Tension, alimentation:3.6V; Lamp Base Type:P13,5s; Taille de lampe:11.5mm; MSCP:1.59; Durée de vie moyenne de la lampe:30h; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Courant:0.5A; Dimension de la lentille:11.5mm; Durée de vie:30h; Emission lumineuse, totale:17lm; Longueur/hauteur:32mm; Tension:3.6V; Tension c.a.:3.6V
LAMPE E10 HALOGENE 5.2V; Tension, alimentation:5.2V; Lamp Base Type:E10; Longueur:32mm; SVHC:No SVHC (19-Dec-2011); Courant:0.85A; Dimension de la lentille:T9; Durée de vie:25h; Durée de vie moyenne de la lampe:25h; Emission lumineuse, totale:90lm; Intensité lumineuse, max..:90lm; MSCP:7.15; Taille de lampe:T-9; Tension c.a.:5.2V
LAMPE BA9S HALOGENE 12V; Tension, alimentation:12V; Lamp Base Type:BA9s; Puissance:20W; Longueur:33mm; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:BA9s; Durée de vie:240h; Durée de vie moyenne de la lampe:240h; Emission lumineuse, totale:200lm; Intensité lumineuse, max..:200lm; MSCP:15.9; Taille de lampe:BA9s; Tension c.a.:12V
LAMPE P13.5S 5.5V 0.3A; Tension, alimentation:5.4V; Lamp Base Type:P13,5s; Taille de lampe:11.5mm; MSCP:3; Durée de vie moyenne de la lampe:15h; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Courant:0.54A; Dimension de la lentille:P13.5S; Durée de vie:15h; Emission lumineuse, totale:38lm; Longueur/hauteur:32mm; Tension:5.4V; Tension c.a.:5.4V
LAMPE E10 2.2V 250MA; Tension, alimentation:2.2V; Lamp Base Type:E10; Taille de lampe:9mm; Durée de vie moyenne de la lampe:10h; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Courant:0.25A; Dimension de la lentille:9mm; Durée de vie:10h; Emission lumineuse, totale:4lm; Longueur/hauteur:24mm; Tension:2.2V; Tension c.a.:2.2V
LAMPE T3.1/4 12V 5W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:5W; MSCP:4.77; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.37A; Dimension de la lentille:T-1 3/4; Durée de vie:1000h; Emission lumineuse, totale:50lm; Longueur/hauteur:26.8mm; Tension:12V; Tension c.a.:12V
INDICATEUR NEON ROUGE; Tension, alimentation:230V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:12.7mm; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:rouge; Diamètre de découpe panneau:12.7mm; Longueur/hauteur:31.5mm; Tension d'alimentation Vac:230V
INDICATEUR NEON VERT; Tension, alimentation:230V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:12.7mm; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:vert; Diamètre de découpe panneau:12.7mm; Longueur/hauteur:31.5mm; Tension d'alimentation Vac:230V
LED E10 - ROUGE 12VDC; Lamp Base Type:E10; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:1050mcd; Taille de lampe:T-3 1/4; Tension, alimentation:14V; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Catégorie de tension:12V dc; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:15mA; Diamètre, extérieur:9.25mm; Dimension de la lentille:T-3 1/4; Intensité lumineuse typique:1050mcd; Longueur d'onde, crête:630nm; Longueur, lentille:15.65m
LED BA9S 24VDC ROUGE; Lamp Base Type:BA9s; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:1050mcd; Taille de lampe:T-3 1/4; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Catégorie de tension:24V dc; Couleur:Rouge; Couleur, LED:Rouge; Courant, direct, If:15mA; Diamètre, extérieur:9mm; Dimension de la lentille:T-3 1/4; Intensité lumineuse typique:1050mcd; Longueur d'onde, crête:630nm; Longueur, lentille:15.65mm; Longueur/hauteur:28.75mm;
LAMPE BA9S 12V 4W; Tension, alimentation:12V; Lamp Base Type:BA9s; Puissance:4W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:8.8mm; Longueur/hauteur:28mm; Normes:BS233; Style de code:BA9s; Tension:12V; Tension c.a.:12V
LAMPE BA9S 24V 4W; Tension, alimentation:24V; Lamp Base Type:BA9s; Puissance:4W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:8.8mm; Longueur/hauteur:21.5mm; Normes:BS249; Style de code:BA9s; Tension:24V; Tension c.a.:24V
LAMPE BA9S 6.5V 2W; Tension, alimentation:6.5V; Lamp Base Type:BA9s; Taille de lampe:T-2; Puissance:2W; MSCP:0.95; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.3A; Dimension de la lentille:T-3 1/4; Durée de vie:4000h; Emission lumineuse, totale:12lm; Longueur/hauteur:28mm; Style de code:BA9s; Tension:6.5V; Tension c.a.:6.5V
LAMPE FESTOON 12V 10W; Tension, alimentation:12V; Lamp Base Type:Festoon; Taille de lampe:11mm x 38mm; Puissance:10W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:11 x 38mm; Normes:BS272; Style de code:Navette; Tension:12V; Tension c.a.:12V
LAMPE G3.1/2 MBC/MCC 12V 2.2W; Tension, alimentation:12V; Lamp Base Type:BA9s; Taille de lampe:G-3 1/2; Puissance:2.2W; MSCP:1.52; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.183A; Dimension de la lentille:G3 1/2; Durée de vie:3000h; Emission lumineuse, totale:11lm; Longueur/hauteur:25mm; Tension:12V; Tension c.a.:12V
LAMPE G3.1/2 MES 6.5V 0.975W; Tension, alimentation:6.5V; Lamp Base Type:E10; Taille de lampe:G-3 1/2; Puissance:975mW; MSCP:0.57; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.15A; Dimension de la lentille:G3 1/2; Durée de vie:3000h; Emission lumineuse, totale:6lm; Longueur/hauteur:24mm; Tension:6.5V; Tension c.a.:6.5V
LAMPE H3 HALOGENE 12V 55W; Tension, alimentation:12V; Puissance:55W; Longueur:42mm; SVHC:No SVHC (19-Dec-2011); Normes:BS453; Style de code:H3; Tension c.a.:12V
LAMPE H4 XENON 12V 60/55W; Tension, alimentation:12V; Puissance:60W; Taille de lampe:17mm; Longueur:92mm; Lamp Base Type:P43t; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:17mm; Longueur/hauteur:92mm; Normes:BS472X; Style de code:H4; Tension c.a.:12V
LAMPE NEON DEUX BROCHES 4MM; Tension, alimentation:65V; Lamp Base Type:Bi-broche; Courant:300è¾A; SVHC:No SVHC (19-Dec-2011); Courant max.:0.25mA; Dimension de la lentille:T-1 1/4; Longueur cordon:6.85mm; Longueur/hauteur:14mm; Résistance, série, 100V:220K 1/10W; Résistance, série, 240V:560K 1/10W; Taille de lampe:T-1 1/4; Tension, attaque c.a.:65V; Tension, attaque c.c.:90V
LAMPE NEON MCC; Tension, alimentation:120V; Lamp Base Type:BA9s; Courant:2.5mA; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge - Ambre; Dimension de la lentille:T-3 1/4; Longueur/hauteur:28mm; Taille de lampe:10mm / T-3 1/4; Tension, alimentation c.a. max..:120V; Tension, alimentation c.a. min:100V; Tension, attaque c.a.:90V; Tension, attaque c.c.:90V
LAMPE NEON MCC; Tension, alimentation:250V; Lamp Base Type:BA9s; Courant:1.2mA; SVHC:No SVHC (19-Dec-2011); Couleur:Vert; Dimension de la lentille:T-3 1/4; Longueur/hauteur:28mm; Taille de lampe:10mm / T-3 1/4; Tension, alimentation c.a. max..:250V; Tension, alimentation c.a. min:220V; Tension, attaque c.a.:85V; Tension, attaque c.c.:85V
LAMPE NEON T1.1/4 W/E; Tension, alimentation:250V; Lamp Base Type:A fil; Courant:300è¾A; SVHC:No SVHC (19-Dec-2011); Courant max.:0.27mA; Courant min.:0.22mA; Dimension de la lentille:T-1 1/4; Longueur cordon:25mm; Longueur/hauteur:10mm; Résistance, série, 100V:220K 1/4W; Résistance, série, 240V:750K 1/4W; Taille de lampe:T-1 1/4; Tension, attaque c.a.:65V; Tension, attaque c.c.:90V
LAMPE NEON T2 W/E; Tension, alimentation:250V; Lamp Base Type:A fil; Courant:1.8mA; SVHC:No SVHC (19-Dec-2011); Courant max.:2.5mA; Courant min.:1.8mA; Dimension de la lentille:T2; Longueur cordon:30mm; Longueur/hauteur:16mm; Résistance, série, 100V:33K 1/4W; Résistance, série, 240V:100K 1/4W; Taille de lampe:6mm / T-2; Tension, attaque c.a.:95V; Tension, attaque c.c.:35V
LED MIN GROOVE 24V JAUNE; Lamp Base Type:Midget Groove; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:63mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:14mA; Courant, fonctionnement c.a.:14mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lum
LED MIN GROOVE 28V VERT; Lamp Base Type:Midget Groove; Couleur de LED:Vert; Longueur d'onde typ.:567nm; Intensité lumineuse:90mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:14mA; Courant, fonctionnement c.a.:14mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lumineu
LED 24V JAUNE; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:63mcd; Taille de lampe:T-5 1/2; Tension, alimentation:24V; Courant:15mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Diamètre, extérieur:5.8mm; Dimension de la lentille:T5.5; Durée de vie:60000h; Intensité lumi
LED MID GROOVE 24VAC/DC ROUGE; Lamp Base Type:Midget Groove; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:330mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:3.8mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumi
LED MID GROOVE 12VAC/DC ROUGE; Lamp Base Type:Midget Groove; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:330mcd; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumi
LED MID GROOVE 12VAC/DC JAUNE; Lamp Base Type:Midget Groove; Couleur de LED:Jaune; Longueur d'onde typ.:587nm; Intensité lumineuse:280mcd; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité l
LED MID GROOVE 24VAC/DC JAUNE; Lamp Base Type:Midget Groove; Couleur de LED:Jaune; Longueur d'onde typ.:587nm; Intensité lumineuse:280mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité l
LED MID GROOVE 28VAC/DC BLANC DF; Lamp Base Type:Midget Groove; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumineuse typique:700mcd; L
LED BA9S 24VAC/DC ROUGE; Lamp Base Type:BA9s; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:350mcd; Taille de lampe:10mm; Tension, alimentation:24V; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:350mcd;
LED BA9S 24VAC/DC BLANC DIFF; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:750mcd; Taille de lampe:10mm; Tension, alimentation:24V; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:750mcd; Longueur/hauteur:25m
LED BA9S 28VAC/DC JAUNE; Lamp Base Type:BA9s; Couleur de LED:Jaune; Longueur d'onde typ.:587nm; Intensité lumineuse:300mcd; Taille de lampe:10mm; Tension, alimentation:28V; Courant:13mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Courant, fonctionnement c.c.:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:300m
LAMPE NEON T2 W/E; Tension, alimentation:250V; Lamp Base Type:A fil; Courant:1.8mA; SVHC:No SVHC (19-Dec-2011); Courant max.:2.5mA; Courant min.:1.8mA; Dimension de la lentille:T2; Longueur cordon:50mm; Longueur/hauteur:16mm; Résistance, série, 100V:33K 1/4W; Résistance, série, 240V:100K 1/4W; Taille de lampe:6mm / T-2; Tension, attaque c.a.:95V; Tension, attaque c.c.:135V
LAMPE S5.7S 6MM 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:Midget Groove, S5,7s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.3; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-1 3/4; Durée de vie:10000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:15.9mm; Tension:28V; Tension c.a.:28V
LAMPE SBC BA15D 12V 21W; Tension, alimentation:12V; Lamp Base Type:BA15d; Taille de lampe:25mm; Puissance:21W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:25mm; Normes:BS335; Style de code:BA15d; Tension:28V; Tension c.a.:12V
LAMPE SBC BA15D 12V 5W; Tension, alimentation:12V; Lamp Base Type:BA15d; Taille de lampe:18mm; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:18mm; Longueur/hauteur:30mm; Normes:BS209; Style de code:BA15d; Tension c.a.:12V
LAMPE SBC BA15D 24V 5W HD; Tension, alimentation:24V; Lamp Base Type:BA15d; Taille de lampe:18mm; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:18mm; Longueur/hauteur:30mm; Normes:BS247; Style de code:BA15d; Tension:24V; Tension c.a.:24V
LAMPE SCC BA15S 24V 21W; Tension, alimentation:24V; Lamp Base Type:BA15s; Taille de lampe:25mm; Puissance:21W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:25mm; Normes:BS241; Style de code:BA15s; Tension:24V; Tension c.a.:24V
LAMPE SX6S 6MM 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:SX6s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.38; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-1 3/4; Durée de vie:4000h; Emission lumineuse, totale:4.5lm; Longueur/hauteur:16.1mm; Tension:28V; Tension c.a.:28V
LAMPE T1 DEUX BROCHES 12V 0.72W; Tension, alimentation:12V; Taille de lampe:T-1; Puissance:720mW; MSCP:0.15; Durée de vie moyenne de la lampe:16000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:T1; Durée de vie:16000h; Emission lumineuse, totale:1.9lm; Longueur cordon:6.4mm; Longueur/hauteur:9.65mm; Pas:2.54mm; Tension:12V; Tension c.a.:12V
LAMPE T1 W/E 12V 0.72W; Tension, alimentation:12V; Taille de lampe:T-1; Puissance:720mW; MSCP:0.15; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:0.72W; Courant:0.06A; Courant max.:0.06A; Dimension de la lentille:T1; Durée de vie:5000h; Emission lumineuse, totale:1.9lm; Longueur:6.35mm; Longueur cordon:25mm; Longueur/hauteur:6.35mm; Quantité par paquet:10; Tension:12V; Tension c.a.:12V
LAMPE T1 W/E 28V 0.672W; Tension, alimentation:28V; Taille de lampe:T-1; Puissance:670mW; MSCP:0.15; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:0.67W; Courant:0.024A; Courant max.:0.03A; Dimension de la lentille:T1; Durée de vie:1000h; Emission lumineuse, totale:1.9lm; Longueur:6.35mm; Longueur cordon:25mm; Longueur/hauteur:6.35mm; Quantité par paquet:10; Tension:28V; Tension c.a.:28V
LAMPE T1.1/2 LES 6V 0.36W; Tension, alimentation:6V; Lamp Base Type:LES (E5); Taille de lampe:T-1 1/2; Puissance:360mW; MSCP:0.07; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:T-1 1/2; Durée de vie:10000h; Emission lumineuse, totale:1lm; Longueur/hauteur:16mm; Tension:6V; Tension c.a.:6V
LAMPE T1.1/2 W/E 24V 0.96W; Tension, alimentation:24V; Taille de lampe:T-1 1/2; Puissance:960mW; MSCP:0.22; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:0.96W; Courant:0.05A; Courant max.:0.04A; Dimension de la lentille:T-1 1/2; Durée de vie:10000h; Emission lumineuse, totale:2.8lm; Longueur:13.2mm; Longueur cordon:25mm; Longueur/hauteur:13.5mm; Quantité par paquet:10; Tension:24V; Tension c.a.:24V
LAMPE T1.1/2 12V 1.2W ROUGE; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:1.2W; MSCP:0.55; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge; Couleur:Red; Courant:0.1A; Dimension de la lentille:T-1 1/2; Durée de vie:3000h; Emission lumineuse, totale:7lm; Longueur/hauteur:18mm; Tension:12V; Tension c.a.:12V
LAMPE T1.1/2 24V 0.72W; Tension, alimentation:24V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:720mW; MSCP:0.1; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.03A; Dimension de la lentille:T-1 1/2; Durée de vie:5000h; Emission lumineuse, totale:1.25lm; Longueur/hauteur:18mm; Tension:24V; Tension c.a.:24V
LAMPE T1.3/4 DEUX BROCHES 28V 1.12W; Tension, alimentation:28V; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.42; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-1 3/4; Durée de vie:4000h; Emission lumineuse, totale:4.3lm; Longueur cordon:6.85mm; Longueur/hauteur:15.8mm; Pas:3.17mm; Tension:28V; Tension c.a.:28V
LAMPE T1.3/4 MID.FLANGE 28V 1.1W; Tension, alimentation:28V; Lamp Base Type:Midget Flange, SX6s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.35; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Courant, fonctionnement c.c.:0.40A; Diamètre, extérieur:7.37mm; Dimension de la lentille:T-1 3/4; Durée de vie:10000h; Emission lumineuse, totale:4.02lm; Longueur/hauteur:13.3mm; Tension:28V; Tension c.a.:28V; Tension, alimentation c.c.:28V
LAMPE T1.3/4 MID.GROOVE 14V 1.12W; Tension, alimentation:14V; Lamp Base Type:Midget Groove, S5,7s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.38; Durée de vie moyenne de la lampe:15000h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Courant, fonctionnement c.c.:0.08A; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:15000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:15.9mm; Tension:14V; Tension c.a.:14V; Tension, alimentation c.c.:14V
LAMPE T1.3/4 MID.GROOVE 48V 1.2W; Tension, alimentation:48V; Lamp Base Type:Midget Groove, S5,7s; Taille de lampe:T-1 3/4; Puissance:1.2W; MSCP:0.26; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.025A; Courant, fonctionnement c.c.:0.03A; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:5000h; Emission lumineuse, totale:4.3lm; Longueur/hauteur:15.9mm; Tension:48V; Tension c.a.:48V; Tension, alimentation c.c.:48V
LAMPE T1.3/4 14V 1.12W; Tension, alimentation:14V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:1.12W; MSCP:0.3; Durée de vie moyenne de la lampe:15000h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Dimension de la lentille:T-1 3/4; Durée de vie:15000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:20.3mm; Tension:14V; Tension c.a.:14V
LAMPE T3.1/4 MBC/MCC 12V 2.2W; Tension, alimentation:12V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:2W; MSCP:1.07; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.17A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:9.4lm; Longueur/hauteur:30mm; Tension:12V; Tension c.a.:12V
LAMPE T3.1/4 MBC/MCC 130V 2.6W; Tension, alimentation:130V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:3.2W; MSCP:0.31; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.02A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:4.5lm; Longueur/hauteur:30mm; Tension c.a.:130V
LAMPE T3.1/4 MBC/MCC 28V 2.24W; Tension, alimentation:28V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:2.24W; MSCP:0.62; Durée de vie moyenne de la lampe:7500h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Dimension de la lentille:T-3 1/4; Durée de vie:7500h; Emission lumineuse, totale:7.8lm; Longueur/hauteur:30mm; Tension c.a.:28V
LAMPE T3.1/4 MBC/MCC 6.3V 1.575W; Tension, alimentation:6.3V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:1.57W; MSCP:0.9; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.25A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:11.3lm; Longueur/hauteur:30mm; Tension c.a.:6.3V
LAMPE T3.1/4 24V 5W; Tension, alimentation:24V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:5W; MSCP:2.4; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.21A; Dimension de la lentille:T-1 3/4; Durée de vie:1000h; Emission lumineuse, totale:50lm; Longueur/hauteur:26.8mm; Tension:24V; Tension c.a.:24V
LAMPE T6.8 EMISSION LATERALE 30V 1.2W; Tension, alimentation:30V; Taille de lampe:T-6 4/5; Puissance:1.2W; MSCP:0.3; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T6.8; Durée de vie:5000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:46.5mm; Tension c.a.:30V
LAMPE WE 3MM 5V 0.3W; Tension, alimentation:5V; Taille de lampe:T-1; Puissance:300mW; MSCP:0.04; Durée de vie moyenne de la lampe:40000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:T1; Durée de vie:40000h; Emission lumineuse, totale:0.6lm; Longueur/hauteur:6.35mm; Tension:5VDC; Tension c.a.:5V
LED T10 BLANC 24V AC/DC; Lamp Base Type:Culot Wedge; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:T-10; Tension, alimentation:24V; Courant:14mA; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:14mA; Diamètre, extérieur:10mm; Dimension de la lentille:T10; Intensité lumineuse typique:700mcd; Température de fonctionnement:-20°C +60°C; Température de fonctionnement max..:60°C; Température d'utilisation min:-20°C; Tension VDC:24V; Tension, Vf
LED MBC 130VAC VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:565nm; Intensité lumineuse:130mcd; Puissance:490mW; Taille de lampe:T-10; Tension, alimentation:130V; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Vert; Couleur, LED:Vert; Diamètre, extérieur:10mm; Dimension de la lentille:T10; Durée de vie:60000h; Intensité lumineuse typique:130mcd; Longueur d'onde, crête:565nm; Nombre de LED:8; Puissance, Pt
LED MIN GROOVE 12V VERT; Lamp Base Type:Midget Groove; Couleur de LED:Vert; Longueur d'onde typ.:567nm; Intensité lumineuse:90mcd; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:30mA; Courant, fonctionnement c.a.:30mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lumineuse typique:90m
LED T1 DEUX BROCHES 24V ROUGE; Lamp Base Type:Bi-broche; Couleur de LED:Rouge; Longueur d'onde typ.:635nm; Intensité lumineuse:19mcd; Taille de lampe:T-1; Tension, alimentation:24V; Courant:12mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:12mA; Courant, fonctionnement c.a.:12mA; Diamètre, extérieur:4.5mm; Dimension de la lentille:T1; Durée de vie:60000h; Intensité lumineuse typiq
LED T5 BLANC 24V AC/DC; Lamp Base Type:Culot Wedge; Couleur de LED:Blanc; Intensité lumineuse:600mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:12mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:600mcd; Température de fonctionnement:-20°C +60°C; Température de fonctionnement max..:60°C; Température d'uti
LAMPE P13.5S HALOGENE 5.2V; Tension, alimentation:5.2V; Lamp Base Type:P13,5s; Longueur:32mm; SVHC:No SVHC (19-Dec-2011); Courant:0.85A; Dimension de la lentille:P13.5S; Durée de vie:25h; Durée de vie moyenne de la lampe:25h; Emission lumineuse, totale:85lm; Intensité lumineuse, max..:85lm; MSCP:6.76; Taille de lampe:P13.5S; Tension c.a.:5.2V
LAMPE P13.5S 4.75V 0.5A; Tension, alimentation:4.75V; Lamp Base Type:P13,5s; Taille de lampe:11.5mm; MSCP:2.54; Durée de vie moyenne de la lampe:20h; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Courant:0.5A; Dimension de la lentille:11.5mm; Durée de vie:20h; Emission lumineuse, totale:32lm; Longueur/hauteur:32mm; Tension:4.8V; Tension c.a.:4.75V
LAMPE P13.5S 7.5V 0.5A; Tension, alimentation:4.8V; Lamp Base Type:P13,5s; Taille de lampe:11.5mm; MSCP:1.98; Durée de vie moyenne de la lampe:15h; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Courant:0.5A; Dimension de la lentille:11.5mm; Durée de vie:15h; Emission lumineuse, totale:25lm; Longueur/hauteur:32mm; Tension:4.8V; Tension c.a.:4.8V
LED MES 230VAC BLANC DIFF; Lamp Base Type:E10; Couleur de LED:Blanc; Intensité lumineuse:75mcd; Taille de lampe:10mm; Tension, alimentation:230V; Courant:3mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:3mA; Courant, fonctionnement c.a.:3mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:75mcd; Température de fonctionnement:-20°C +60°C; Température de fon
LED BA9S - BLANC 12VDC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:825mcd; Taille de lampe:T-3 1/4; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Catégorie de tension:12V dc; Couleur:White; Couleur, LED:Blanc; Courant, direct, If:15mA; Diamètre, extérieur:9mm; Dimension de la lentille:T-3 1/4; Intensité lumineuse typique:825mcd; Longueur, lentille:15.65mm; Longueur/hauteur:28.75mm; Température de fonctionnement:-30°C +85°C; Température
LAMPE BA9S 12V 2.2W; Tension, alimentation:12V; Lamp Base Type:BA9s; Taille de lampe:T-2; Puissance:2.2W; MSCP:0.87; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.183A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:11lm; Longueur/hauteur:28mm; Style de code:BA9s; Tension:12V; Tension c.a.:12V
LAMPE BA9S 24V 2.9W; Tension, alimentation:24V; Lamp Base Type:BA9s; Taille de lampe:T-2; Puissance:2.8W; MSCP:0.95; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.12A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:12lm; Longueur/hauteur:28mm; Style de code:BA9s; Tension:24V; Tension c.a.:24V
LAMPE G3.1/2 MES 12V 1.2W; Tension, alimentation:12V; Lamp Base Type:E10; Taille de lampe:G-3 1/2; Puissance:1.2W; MSCP:0.47; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.1A; Dimension de la lentille:G3 1/2; Durée de vie:5000h; Emission lumineuse, totale:5lm; Longueur/hauteur:24mm; Tension:12V; Tension c.a.:12V
LAMPE G3.1/2 MES 12V 2.19W; Tension, alimentation:12V; Lamp Base Type:E10; Taille de lampe:G-3 1/2; Puissance:2.2W; MSCP:1.52; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.18A; Dimension de la lentille:G3 1/2; Durée de vie:3000h; Emission lumineuse, totale:9.4lm; Longueur/hauteur:24mm; Tension:12V; Tension c.a.:12V
LAMPE G3.1/2 MES 24V 2.8W; Tension, alimentation:24V; Lamp Base Type:E10; Taille de lampe:G-3 1/2; Puissance:2.8W; MSCP:1.35; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.12A; Dimension de la lentille:G3 1/2; Durée de vie:3000h; Emission lumineuse, totale:10.7lm; Longueur/hauteur:24mm; Tension:24V; Tension c.a.:24V
LAMPE H1 HALOGENE 24V 70W; Tension, alimentation:24V; Lamp Base Type:P14,5s; Puissance:70W; Longueur:67.5mm; SVHC:No SVHC (19-Dec-2011); Normes:BS466; Style de code:H1; Tension c.a.:24V
LAMPE LES 5MM 24V 0.96W; Tension, alimentation:24V; Taille de lampe:T-1 3/4; Puissance:960mW; MSCP:0.24; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-1 1/2; Durée de vie:10000h; Emission lumineuse, totale:3lm; Longueur/hauteur:16mm; Tension:24V; Tension c.a.:24V
LAMPE MES 6.5V 2W; Tension, alimentation:6.5V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:2W; MSCP:0.95; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.3A; Dimension de la lentille:T-3 1/4 MES; Durée de vie:4000h; Emission lumineuse, totale:12lm; Longueur/hauteur:28mm; Tension:6.5V
LAMPE NEON T1.1/4 W/E; Tension, alimentation:240V; Lamp Base Type:A fil; Courant:550è¾A; SVHC:No SVHC (19-Dec-2011); Couleur:Green; Courant max.:0.55mA; Dimension de la lentille:T-1 1/4; Longueur cordon:23mm; Longueur/hauteur:10.5mm; Résistance, série, 100V:100K 1/4W; Résistance, série, 240V:330K 1/4W; Taille de lampe:T-1 1/4; Tension, attaque c.a.:65V; Tension, attaque c.c.:90V
LAMPE NEON T2 W/E; Lamp Base Type:A fil; Courant:500è¾A; SVHC:No SVHC (19-Dec-2011); Courant max.:0.55mA; Courant min.:0.35mA; Dimension de la lentille:T2; Longueur cordon:30mm; Longueur/hauteur:16mm; Résistance, série, 100V:100K 1/4W; Résistance, série, 240V:330K 1/4W; Taille de lampe:6mm / T-2; Tension, attaque c.a.:65V; Tension, attaque c.c.:90V
LAMPE NEON T2 W/E; Tension, alimentation:240V; Lamp Base Type:A fil; Courant:4.5mA; SVHC:No SVHC (19-Dec-2011); Courant max.:4.5mA; Dimension de la lentille:T2; Longueur cordon:30mm; Longueur/hauteur:16mm; Résistance, série, 100V:12K 1/4W; Résistance, série, 240V:39K 1/4W; Taille de lampe:6mm / T-2; Tension, attaque c.a.:95V; Tension, attaque c.c.:135V
LAMPE P13.5S XENON; Tension, alimentation:2.4V; Taille de lampe:11.5mm; Courant:500mA; Longueur:32mm; Lamp Base Type:P13,5s; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:11.5mm; Durée de vie:10h; Durée de vie moyenne de la lampe:10h; Emission lumineuse, totale:10lm; Intensité lumineuse, max..:16.5lm; Longueur/hauteur:32mm; MSCP:1.31; Tension c.a.:2.4V
LAMPE PCB 24V 1.2W GREY; Tension, alimentation:24V; Taille de lampe:5mm; Puissance:1.2W; SVHC:No SVHC (19-Dec-2011); Couleur:Grey; Dimension de la lentille:5mm; Longueur/hauteur:22mm; Normes:BS508T; Style de code:Sur CI; Tension:24V; Tension c.a.:24V
LAMPE SBC BA15D 24V 5W; Tension, alimentation:24V; Lamp Base Type:BA15d; Taille de lampe:18mm; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:18mm; Longueur/hauteur:30mm; Normes:BS150; Style de code:BA15d; Tension:24V; Tension c.a.:24V
LAMPE SCC BA15S 12V 21W; Tension, alimentation:12V; Lamp Base Type:BA15s; Taille de lampe:25mm; Puissance:21W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:25mm; Normes:BS382; Style de code:BA15s; Tension:12V; Tension c.a.:12V
LAMPE SCC BA15S 12V 5W; Tension, alimentation:12V; Lamp Base Type:BA15s; Taille de lampe:18mm; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:18mm; Longueur/hauteur:30mm; Normes:BS207; Style de code:BA15s; Tension:12V; Tension c.a.:12V
LAMPE SCC BA15S 24V 5W HD; Tension, alimentation:24V; Lamp Base Type:BA15s; Taille de lampe:18mm; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:18mm; Longueur/hauteur:30mm; Normes:BS248; Style de code:BA15s; Tension:24V; Tension c.a.:24V
LAMPE T1 DEUX BROCHES 18V 0.47W; Tension, alimentation:18V; Taille de lampe:T-1; Puissance:470mW; MSCP:0.01; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.026A; Dimension de la lentille:T1; Durée de vie:5000h; Emission lumineuse, totale:1.9lm; Longueur cordon:6.4mm; Longueur/hauteur:9.65mm; Pas:2.54mm; Tension:18V; Tension c.a.:18V
LAMPE T1 DEUX BROCHES 28V 0.67W; Tension, alimentation:28V; Taille de lampe:T-1; Puissance:670mW; MSCP:0.15; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.024A; Dimension de la lentille:T1; Durée de vie:4000h; Emission lumineuse, totale:1.9lm; Longueur cordon:6.4mm; Longueur/hauteur:9.65mm; Pas:2.54mm; Tension:28V; Tension c.a.:28V
LAMPE T1 DEUX BROCHES 5V 0.3W; Tension, alimentation:5V; Taille de lampe:T-1; Puissance:300mW; MSCP:0.03; Durée de vie moyenne de la lampe:40000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Diamètre, extérieur:3.3mm; Dimension de la lentille:T1; Durée de vie:40000h; Emission lumineuse, totale:0.38lm; Longueur cordon:6.85mm; Longueur/hauteur:9.65mm; Pas:1.27mm; Tension:5V; Tension c.a.:5V
LAMPE T1.1/2 LES 24V 0.96W; Tension, alimentation:24V; Lamp Base Type:LES (E5); Taille de lampe:T-1 1/2; Puissance:960mW; MSCP:0.23; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:0.96W; Courant:0.04A; Courant max.:0.04A; Dimension de la lentille:T-1 1/2; Durée de vie:10000h; Emission lumineuse, totale:3lm; Longueur/hauteur:16mm; Tension:24V; Tension c.a.:24V
LAMPE T1.1/2 12V 0.36W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:360mW; MSCP:0.08; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.03A; Dimension de la lentille:T-1 1/2; Durée de vie:3000h; Emission lumineuse, totale:0.7lm; Longueur/hauteur:18mm; Tension:12V; Tension c.a.:12V
LAMPE T1.1/2 12V 1.2W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:1.2W; MSCP:0.56; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.1A; Dimension de la lentille:T-1 1/2; Durée de vie:1000h; Emission lumineuse, totale:7.2lm; Longueur/hauteur:18mm; Tension:12V; Tension c.a.:12V
LAMPE T1.1/2 24V 0.96W; Tension, alimentation:24V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:960mW; MSCP:0.24; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-1 1/2; Durée de vie:10000h; Emission lumineuse, totale:3lm; Longueur/hauteur:18mm; Tension c.a.:24V
LAMPE T1.1/2 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:1.12W; MSCP:0.3; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-1 1/2; Durée de vie:10000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:18mm; Tension c.a.:28V
LAMPE T1.3/4 MID.GROOVE 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:Midget Groove, S5,7s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.42; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Courant, fonctionnement c.c.:0.04A; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:4000h; Emission lumineuse, totale:4.3lm; Longueur/hauteur:15.9mm; Tension:28V; Tension c.a.:28V; Tension, alimentation c.c.:28V
LAMPE T1.3/4 MID.GROOVE 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:Midget Groove, S5,7s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.38; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Courant, fonctionnement c.c.:0.04A; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:10000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:15.9mm; Tension:28V; Tension c.a.:28V; Tension, alimentation c.c.:28V
LAMPE T3.1/4 MBC/MCC 24V 2.88W; Tension, alimentation:24V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:2.88W; MSCP:1.24; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.12A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:12lm; Longueur/hauteur:28mm; Tension:24V; Tension c.a.:24V
LAMPE T3.1/4 MBC/MCC 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:1.1W; MSCP:0.34; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:4.3lm; Longueur/hauteur:30mm; Tension c.a.:28V
LAMPE T3.1/4 MES 12V 0.25W; Tension, alimentation:12V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:3W; MSCP:1.19; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.25A; Dimension de la lentille:T-3 1/4; Durée de vie:4000h; Emission lumineuse, totale:12.5lm; Longueur/hauteur:30mm; Tension c.a.:12V
LAMPE T3.1/4 MES 12V 2.2W; Tension, alimentation:12V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:2.2W; MSCP:0.9; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.183A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:11lm; Longueur/hauteur:3mm; Tension c.a.:12V
LAMPE T3.1/4 12V 2.16W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:2.16W; MSCP:2.1; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.18A; Dimension de la lentille:T-1 3/4; Durée de vie:3000h; Emission lumineuse, totale:12.6lm; Longueur/hauteur:26.8mm; Tension:12V; Tension c.a.:12V
LAMPE T3.1/4 24V 3W; Tension, alimentation:24V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:3W; MSCP:1; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.13A; Dimension de la lentille:T-1 3/4; Durée de vie:1000h; Emission lumineuse, totale:22lm; Longueur/hauteur:26.8mm; Tension:24V; Tension c.a.:24V
LAMPE T3.8 AXIAL W/E 15V 0.6W; Tension, alimentation:15V; Lamp Base Type:A fil axial; Taille de lampe:T-1 1/5; Puissance:600mW; MSCP:0.19; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.055A; Dimension de la lentille:T3.8; Durée de vie:5000h; Emission lumineuse, totale:2.3lm; Longueur cordon:15mm; Longueur/hauteur:20mm; Tension:15V; Tension c.a.:15V; Tension, alimentation max..:15V; Tension, alimentation min.:10V
LAMPE T6.2 AXIAL W/E 15V 1.3W; Tension, alimentation:15V; Lamp Base Type:A fil axial; Taille de lampe:T-6 1/2; Puissance:1.3W; MSCP:0.69; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.11A; Dimension de la lentille:T6.2; Durée de vie:5000h; Emission lumineuse, totale:7lm; Longueur cordon:15mm; Longueur/hauteur:28mm; Tension:15V; Tension c.a.:15V; Tension, alimentation max..:15V; Tension, alimentation min.:10V
LAMPE T6.8 EMISSION LATERALE 24V 1.2W; Tension, alimentation:24V; Taille de lampe:T-6 4/5; Puissance:1.2W; MSCP:0.27; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.05A; Dimension de la lentille:T6.8; Durée de vie:5000h; Emission lumineuse, totale:3.5lm; Longueur/hauteur:46.5mm; Tension:24V; Tension c.a.:24V
LAMPE T6.8 EMISSION LATERALE 60V 1.2W; Tension, alimentation:60V; Taille de lampe:T-6 4/5; Puissance:1.2W; MSCP:0.17; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.02A; Dimension de la lentille:T6.8; Durée de vie:5000h; Emission lumineuse, totale:2.2lm; Longueur/hauteur:46.5mm; Tension c.a.:60V
LED EMISSION LATERALE 24V VERT; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Vert; Longueur d'onde typ.:567nm; Intensité lumineuse:90mcd; Taille de lampe:T-5 1/2; Tension, alimentation:24V; Courant:15mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:15mA; Courant, fonctionnement c.a.:15mA; Diamètre, extérieur:5.8mm; Dimension de la lentille:T5.5; Durée de vie:60000h;
LED T1 DEUX BROCHES 24V JAUNE; Lamp Base Type:Bi-broche; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:32mcd; Taille de lampe:T-1; Tension, alimentation:24V; Courant:12mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:12mA; Courant, fonctionnement c.a.:12mA; Diamètre, extérieur:4.5mm; Dimension de la lentille:T1; Durée de vie:60000h; Intensité lumineuse ty
LED T1 DEUX BROCHES 28V ROUGE; Lamp Base Type:Bi-broche; Couleur de LED:Rouge; Longueur d'onde typ.:635nm; Intensité lumineuse:19mcd; Taille de lampe:T-1; Tension, alimentation:28V; Courant:12mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:12mA; Courant, fonctionnement c.a.:12mA; Diamètre, extérieur:4.5mm; Dimension de la lentille:T1; Durée de vie:60000h; Intensité lumineuse typiq
LED T10 BLANC 12V AC/DC; Lamp Base Type:Culot Wedge; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:10mm; Tension, alimentation:12V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:14mA; Diamètre, extérieur:10mm; Dimension de la lentille:T10; Intensité lumineuse typique:700mcd; Température de fonctionnement:-20°C +60°C; Température de fonctionnement max..:60°C; Température d'utilisatio
LED T5 BLANC 28V AC/DC; Lamp Base Type:Culot Wedge; Couleur de LED:Blanc; Intensité lumineuse:600mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:12mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:600mcd; Température de fonctionnement:-20°C +60°C; Température de fonctionnement max..:60°C; Température d'uti
LED BA9S - AMBRE 24VDC; Lamp Base Type:BA9s; Couleur de LED:Jaune; Longueur d'onde typ.:592nm; Intensité lumineuse:1275mcd; Taille de lampe:T-3 1/4; Tension, alimentation:28V; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Catégorie de tension:24V dc; Couleur:Amber; Couleur, LED:Ambre; Courant, direct, If:15mA; Diamètre, extérieur:9mm; Dimension de la lentille:T-3 1/4; Intensité lumineuse typique:1275mcd; Longueur d'onde, crête:592nm; Longueur, lentille:15.65
LAMPE FESTOON 24V 5W; Tension, alimentation:24V; Lamp Base Type:Festoon; Taille de lampe:11mm x 38mm; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:11 x 38mm; Normes:BS242; Style de code:Navette; Tension c.a.:24V
LAMPE G3.1/2 MES 6V 0.36W; Tension, alimentation:6V; Lamp Base Type:E10; Taille de lampe:G-3 1/2; Puissance:360mW; MSCP:0.09; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:G3 1/2; Durée de vie:10000h; Emission lumineuse, totale:1lm; Longueur/hauteur:24mm; Tension:6V; Tension c.a.:6V
LAMPE H4 HALOGENE 12V 60/55W; Tension, alimentation:12V; Puissance:60W; Longueur:92mm; SVHC:No SVHC (19-Dec-2011); Normes:BS472; Style de code:H4; Tension c.a.:12V
LAMPE MES 24V 2.9W; Tension, alimentation:24V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:2.9W; MSCP:0.95; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.12A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:12lm; Longueur/hauteur:28mm; Tension:24V; Tension c.a.:24V
LAMPE NEON MES; Tension, alimentation:250V; Lamp Base Type:E10; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge - Ambre; Diamètre, extérieur:10.3mm; Dimension de la lentille:T-3 1/4; Longueur/hauteur:30mm; Résistance, série, 240V:68Kohm; Taille de lampe:10mm / T-3 1/4; Tension, alimentation c.a. max..:250V; Tension, alimentation c.a. min:220V; Tension, attaque c.a.:230V
LAMPE NEON T1.1/4 W/E; Tension, alimentation:250V; Lamp Base Type:A fil; Courant:1.2mA; SVHC:No SVHC (19-Dec-2011); Courant max.:0.7mA; Courant min.:0.5mA; Dimension de la lentille:T-1 1/4; Longueur cordon:25mm; Longueur/hauteur:10mm; Résistance, série, 100V:ne convient pas; Résistance, série, 240V:220K 1/4W; Taille de lampe:T-1 1/4; Tension, attaque c.a.:95V; Tension, attaque c.c.:135V
LAMPE NEON T1.1/4 W/E; Tension, alimentation:240V; Lamp Base Type:A fil; Courant:1.8mA; SVHC:No SVHC (19-Dec-2011); Courant max.:1.8mA; Dimension de la lentille:T-1 1/4; Longueur cordon:23mm; Longueur/hauteur:10.5mm; Résistance, série, 100V:33K 1/4W; Résistance, série, 240V:100K 1/4W; Taille de lampe:T-1 1/4; Tension, attaque c.a.:95V; Tension, attaque c.c.:135V
LAMPE NEON T2 W/E; Tension, alimentation:250V; Lamp Base Type:A fil; Courant:500è¾A; SVHC:No SVHC (19-Dec-2011); Courant max.:0.55mA; Courant min.:0.35mA; Dimension de la lentille:T2; Longueur cordon:50mm; Longueur/hauteur:16mm; Résistance, série, 100V:100K 1/4W; Résistance, série, 240V:330K 1/4W; Taille de lampe:6mm / T-2; Tension, attaque c.a.:65V; Tension, attaque c.c.:90V
LAMPE NEON T2 W/E; Tension, alimentation:240V; Lamp Base Type:A fil; Courant:800è¾A; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Courant max.:0.8mA; Dimension de la lentille:T2; Longueur cordon:30mm; Longueur/hauteur:12.5mm; Résistance, série, 100V:68K 1/4W; Résistance, série, 240V:220K 1/4W; Taille de lampe:6mm / T-2; Tension, attaque c.a.:65V; Tension, attaque c.c.:90V
LAMPE NEON T2 W/E; Tension, alimentation:240V; Lamp Base Type:A fil; Courant:550è¾A; SVHC:No SVHC (19-Dec-2011); Courant max.:0.55mA; Dimension de la lentille:T2; Longueur cordon:30mm; Longueur/hauteur:16mm; Résistance, série, 100V:100K 1/4W; Résistance, série, 240V:330K 1/4W; Taille de lampe:6mm / T-2; Tension, attaque c.a.:65V; Tension, attaque c.c.:90V
LAMPE NEON T5.5 230V ROUGE; Tension, alimentation:230V; Lamp Base Type:Ampoule de téléphonie; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge - Ambre; Courant max.:2.6mA; Dimension de la lentille:T5.5; Longueur/hauteur:31mm; Taille de lampe:T-5.5; Tension, attaque c.a.:95V
LAMPE SCC BA15S 24V 5W; Tension, alimentation:24V; Lamp Base Type:BA15s; Taille de lampe:18mm; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:18mm; Longueur/hauteur:30mm; Normes:BS149; Style de code:BA15s; Tension c.a.:24V
LAMPE T1 DEUX BROCHES 6V 0.69W; Tension, alimentation:6V; Taille de lampe:T-1; Puissance:690mW; MSCP:0.01; Durée de vie moyenne de la lampe:25000h; SVHC:No SVHC (19-Dec-2011); Courant:0.115A; Dimension de la lentille:T1; Durée de vie:25000h; Emission lumineuse, totale:1.9lm; Longueur cordon:6.4mm; Longueur/hauteur:9.65mm; Pas:2.54mm; Tension:6V; Tension c.a.:6V
LAMPE T1 W/E 5V 0.3W; Tension, alimentation:5V; Taille de lampe:T-1; Puissance:300mW; MSCP:0.04; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:0.3W; Courant:0.06A; Courant max.:0.06A; Dimension de la lentille:T1; Durée de vie:20000h; Emission lumineuse, totale:0.6lm; Longueur:6.35mm; Longueur cordon:25mm; Longueur/hauteur:6.35mm; Quantité par paquet:10; Tension:5V; Tension c.a.:5V
LAMPE T1.1/2 LES 12V 0.96W; Tension, alimentation:12V; Lamp Base Type:LES (E5); Taille de lampe:T-1 1/2; Puissance:960mW; MSCP:0.15; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Dimension de la lentille:T-1 1/2; Durée de vie:10000h; Emission lumineuse, totale:2lm; Longueur/hauteur:16mm; Tension:12V; Tension c.a.:12V
LAMPE T1.1/2 W/E 14V 0.7W; Tension, alimentation:14V; Taille de lampe:T-1 1/2; Puissance:700mW; MSCP:0.03; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.05A; Dimension de la lentille:T-1 1/2; Durée de vie:1000h; Emission lumineuse, totale:3lm; Longueur cordon:19mm; Longueur/hauteur:13.5mm; Tension:14V; Tension c.a.:14V
LAMPE T1.1/4 DEUX BROCHES 12V 0.36W; Tension, alimentation:12V; Taille de lampe:T-1 1/4; Puissance:360mW; MSCP:0.07; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.03A; Diamètre, extérieur:4.75mm; Dimension de la lentille:T-1 1/4; Durée de vie:3000h; Emission lumineuse, totale:0.7lm; Longueur cordon:6.85mm; Longueur/hauteur:14mm; Pas:2.54mm; Tension c.a.:12V
LAMPE T1.1/4 DEUX BROCHES 28V 1.12W; Tension, alimentation:28V; Taille de lampe:T-1 1/4; Puissance:1.12W; MSCP:0.39; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Diamètre, extérieur:4.75mm; Dimension de la lentille:T-1 1/4; Durée de vie:1000h; Emission lumineuse, totale:4lm; Longueur cordon:6.85mm; Longueur/hauteur:14mm; Pas:2.54mm; Tension:28V; Tension c.a.:28V
LAMPE T1.3/4 MID.FLANGE 12V 1.2W; Tension, alimentation:12V; Lamp Base Type:Midget Flange, SX6s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.47; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.09A; Courant, fonctionnement c.c.:0.10A; Diamètre, extérieur:7.37mm; Dimension de la lentille:T-1 3/4; Durée de vie:5000h; Emission lumineuse, totale:4.4lm; Longueur/hauteur:16mm; Tension:12V; Tension c.a.:12V; Tension, alimentation c.c.:12V
LAMPE T1.3/4 MID.FLANGE 14V 1.1W; Tension, alimentation:14V; Lamp Base Type:Midget Flange, SX6s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.62; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Courant, fonctionnement c.c.:0.08A; Diamètre, extérieur:7.37mm; Dimension de la lentille:T-1 3/4; Durée de vie:1000h; Emission lumineuse, totale:6.28lm; Longueur/hauteur:13.3mm; Tension:14V; Tension c.a.:14V; Tension, alimentation c.c.:14V
LAMPE T1.3/4 MID.FLANGE 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:Midget Flange, SX6s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.24; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Courant, fonctionnement c.c.:0.04A; Diamètre, extérieur:7.37mm; Dimension de la lentille:T-1 3/4; Durée de vie:20000h; Emission lumineuse, totale:2.5lm; Longueur/hauteur:16mm; Tension:28V; Tension c.a.:28V; Tension, alimentation c.c.:28V
LAMPE T1.3/4 MID.FLANGE 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:Midget Flange, SX6s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.38; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Courant, fonctionnement c.c.:0.04A; Diamètre, extérieur:7.37mm; Dimension de la lentille:T-1 3/4; Durée de vie:10000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:16mm; Tension c.a.:28V; Tension, alimentation c.c.:28V
LAMPE T1.3/4 MID.FLANGE 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:Midget Flange, SX6s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.42; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Courant, fonctionnement c.c.:0.04A; Diamètre, extérieur:7.37mm; Dimension de la lentille:T-1 3/4; Durée de vie:4000h; Emission lumineuse, totale:4.3lm; Longueur/hauteur:16mm; Tension:28V; Tension c.a.:28V; Tension, alimentation c.c.:28V
LAMPE T1.3/4 MID.GROOVE 14V 1.12W; Tension, alimentation:14V; Lamp Base Type:Midget Groove, S5,7s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.62; Durée de vie moyenne de la lampe:750h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Courant, fonctionnement c.c.:0.08A; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:750h; Emission lumineuse, totale:6.3lm; Longueur/hauteur:15.9mm; Tension:14V; Tension c.a.:14V; Tension, alimentation c.c.:14V
LAMPE T1.3/4 MID.GROOVE 6.3V 1.26W; Tension, alimentation:6.3V; Lamp Base Type:Midget Groove, S5,7s; Taille de lampe:T-1 3/4; Puissance:1.26W; MSCP:0.49; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011); Courant:0.2A; Courant, fonctionnement c.c.:0.20A; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:20000h; Emission lumineuse, totale:5lm; Longueur/hauteur:15.9mm; Tension:6.3V; Tension c.a.:6.3V; Tension, alimentation c.c.:6.3V
LAMPE T2 BAYONET 24V 1W; Tension, alimentation:24V; Lamp Base Type:BA7s; Taille de lampe:T-2; Puissance:1W; MSCP:0.25; Durée de vie moyenne de la lampe:7000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T2; Durée de vie:7000h; Emission lumineuse, totale:3lm; Longueur/hauteur:20.7mm; Tension:5V; Tension c.a.:24V
LAMPE T3.1/4 MBC/MCC 28V 1.96W; Tension, alimentation:28V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:1.96W; MSCP:1; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.07A; Dimension de la lentille:T-3 1/4; Durée de vie:1000h; Emission lumineuse, totale:12.6lm; Longueur/hauteur:30mm; Tension:28V; Tension c.a.:28V
LAMPE T3.1/4 MBC/MCC 6.3V 0.945W; Tension, alimentation:6.3V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:945mW; MSCP:0.33; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011); Courant:0.15A; Dimension de la lentille:T-3 1/4; Durée de vie:20000h; Emission lumineuse, totale:4.1lm; Longueur/hauteur:30mm; Tension c.a.:6.3V
LAMPE T3.1/4 MBC/MCC 6V 1.2W; Tension, alimentation:6V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:1.2W; MSCP:0.38; Durée de vie moyenne de la lampe:15000h; SVHC:No SVHC (19-Dec-2011); Courant:0.2A; Dimension de la lentille:T-3 1/4; Durée de vie:15000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:28mm; Tension c.a.:6V
LAMPE T3.1/4 MES 24V 2.8W; Tension, alimentation:24V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:2.8W; MSCP:1.24; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.12A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:10.7lm; Longueur/hauteur:28mm; Tension c.a.:24V
LAMPE T3.1/4 MES 6.5V 1.95W; Tension, alimentation:6.5V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:1.95W; MSCP:1.11; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.3A; Dimension de la lentille:T-3 1/4; Durée de vie:4000h; Emission lumineuse, totale:12lm; Longueur/hauteur:30mm; Tension:6.5V; Tension c.a.:6.5V
LAMPE T3.1/4 24V 1.92W; Tension, alimentation:24V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:1.92W; MSCP:0.63; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Dimension de la lentille:T-1 3/4; Durée de vie:5000h; Emission lumineuse, totale:8lm; Longueur/hauteur:26.8mm; Tension:24V; Tension c.a.:24V
LAMPE T6.8 EMISSION LATERALE 28V 1.12W; Tension, alimentation:28V; Taille de lampe:T-6 4/5; Puissance:1.12W; MSCP:0.27; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T6.8; Durée de vie:5000h; Emission lumineuse, totale:4.5lm; Longueur/hauteur:46.5mm; Tension:28V; Tension c.a.:28V
LAMPE WE 3MM 28V 0.672W; Tension, alimentation:28V; Taille de lampe:T-1; Puissance:672mW; MSCP:0.15; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.024A; Dimension de la lentille:T1; Durée de vie:4000h; Emission lumineuse, totale:1.9lm; Longueur/hauteur:6.35mm; Tension:28V; Tension c.a.:28V
LED BA9S 48VAC/DC BLANC CLAIR; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:400mcd; Taille de lampe:10mm; Tension, alimentation:48V; Courant:8mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:8mA; Courant, fonctionnement c.a.:8mA; Courant, fonctionnement c.c.:8mA; Diamètre, extérieur:10mm; Dimension de la lentille:10mm; Durée de vie:100000h; Intensité lumineuse typique:400mcd; Température de fonction
LED MBC 230VAC VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:565nm; Intensité lumineuse:130mcd; Puissance:490mW; Taille de lampe:T-10; Tension, alimentation:230V; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Vert; Couleur, LED:Vert; Diamètre, extérieur:10mm; Dimension de la lentille:T10; Durée de vie:60000h; Intensité lumineuse typique:130mcd; Longueur d'onde, crête:565nm; Nombre de LED:8; Puissance, Pt
LED MID GROOVE 12VAC/DC BLANC CL; Lamp Base Type:Midget Groove; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:T-1 3/4; Tension, alimentation:12V; Courant:14mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:14mA; Courant, fonctionnement c.a.:7mA; Courant, fonctionnement c.c.:14mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:100000h; Intensité lumineuse typique:700mcd; T
LED MIN FLANGE 24V ROUGE; Lamp Base Type:Midget Flange; Couleur de LED:Rouge; Longueur d'onde typ.:620nm; Intensité lumineuse:1000mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:14mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:14mA; Courant, fonctionnement c.c.:14mA; Diamètre, tête:6.1mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lumineuse
LED T1 DEUX BROCHES 24V VERT; Lamp Base Type:Bi-broche; Couleur de LED:Vert; Longueur d'onde typ.:567nm; Intensité lumineuse:44mcd; Taille de lampe:T-1; Tension, alimentation:24V; Courant:12mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:12mA; Courant, fonctionnement c.a.:12mA; Diamètre, extérieur:4.5mm; Dimension de la lentille:T1; Durée de vie:60000h; Intensité lumineuse typiqu
LED BA9S - BLANC 24VDC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:825mcd; Taille de lampe:T-3 1/4; Courant:15mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Catégorie de tension:28V dc; Couleur:White; Couleur, LED:Blanc; Courant, direct, If:15mA; Diamètre, extérieur:9mm; Dimension de la lentille:T-3 1/4; Intensité lumineuse typique:825mcd; Longueur, lentille:15.65mm; Longueur/hauteur:28.75mm; Température de fonctionnement:-30°C +85°C; Température
LAMPE FESTOON 12V 5W; Tension, alimentation:12V; Lamp Base Type:Festoon; Taille de lampe:11mm x 38mm; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:11 x 38mm; Normes:BS239; Style de code:Navette; Tension:12V; Tension c.a.:12V
LAMPE G3.1/2 MBC/MCC 6.5V 1.95W; Tension, alimentation:6.5V; Lamp Base Type:BA9s; Taille de lampe:G-3 1/2; Puissance:1.95W; MSCP:1.11; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.3A; Dimension de la lentille:G3 1/2; Durée de vie:4000h; Emission lumineuse, totale:12lm; Longueur/hauteur:25mm; Tension:6.5V; Tension c.a.:6.5V
LAMPE H1 HALOGENE 12V 55W; Tension, alimentation:12V; Lamp Base Type:P14,5s; Puissance:55W; Longueur:67.5mm; SVHC:No SVHC (19-Dec-2011); Normes:BS448; Style de code:H1; Tension c.a.:12V
LAMPE H3 HALOGENE 24V 70W; Tension, alimentation:24V; Lamp Base Type:PK22s; Puissance:70W; Longueur:42mm; SVHC:No SVHC (19-Dec-2011); Normes:BS460; Style de code:H3; Tension c.a.:24V
LAMPE LES 5MM 14V 0.7W; Tension, alimentation:14V; Taille de lampe:T-1 1/2; Puissance:700mW; MSCP:0.23; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.05A; Dimension de la lentille:T-1 1/2; Durée de vie:1000h; Emission lumineuse, totale:3lm; Longueur/hauteur:16mm; Tension:14V; Tension c.a.:14V
LAMPE MES 12V 2.2W; Tension, alimentation:12V; Lamp Base Type:E10; Puissance:2.2W; MSCP:0.87; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Courant:0.183A; Dimension de la lentille:G3 1/2; Durée de vie:4000h; Emission lumineuse, totale:11lm; Longueur/hauteur:11mm; Tension:12V; Tension c.a.:12V
LAMPE MES 24V 1.2W; Tension, alimentation:24V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:1.2W; MSCP:0.31; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.05A; Dimension de la lentille:T-3 1/4; Durée de vie:5000h; Emission lumineuse, totale:4lm; Longueur/hauteur:28mm; Tension:24V; Tension c.a.:24V
LAMPE NEON MCC; Tension, alimentation:250V; Lamp Base Type:BA9s; Courant:2.5mA; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge - Ambre; Dimension de la lentille:T-3 1/4; Longueur/hauteur:28mm; Taille de lampe:10mm / T-3 1/4; Tension, alimentation c.a. max..:250V; Tension, alimentation c.a. min:220V; Tension, attaque c.a.:85V; Tension, attaque c.c.:90V
LAMPE NEON T1.1/4 W/E; Tension, alimentation:240V; Lamp Base Type:A fil; Courant:550è¾A; SVHC:No SVHC (19-Dec-2011); Courant max.:0.55mA; Dimension de la lentille:T-1 1/4; Longueur cordon:23mm; Longueur/hauteur:10.5mm; Résistance, série, 100V:100K 1/4W; Résistance, série, 240V:330K 1/4W; Taille de lampe:T-1 1/4; Tension, attaque c.a.:65V; Tension, attaque c.c.:90V
LAMPE NEON T2 W/E; Tension, alimentation:95V; Lamp Base Type:A fil; Courant:1.8mA; SVHC:No SVHC (19-Dec-2011); Courant max.:1.2mA; Courant min.:0.85mA; Dimension de la lentille:T2; Longueur cordon:25mm; Longueur/hauteur:12.5mm; Résistance, série, 100V:56K 1/4W; Résistance, série, 240V:180K 1/4W; Taille de lampe:6mm / T-2; Tension, attaque c.a.:95V; Tension, attaque c.c.:135V
LAMPE SCC BA15S 12V 10W; Tension, alimentation:12V; Lamp Base Type:BA15s; Taille de lampe:18mm; Puissance:10W; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:18mm; Longueur/hauteur:30mm; Normes:BS245; Style de code:BA15s; Tension:12V; Tension c.a.:12V
LAMPE SMF 3MM 28V 0.672W; Tension, alimentation:28V; Taille de lampe:T-1; Puissance:672mW; MSCP:0.12; Durée de vie moyenne de la lampe:4000h; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Courant:0.024A; Dimension de la lentille:T1; Durée de vie:4000h; Emission lumineuse, totale:1.6lm; Longueur/hauteur:9.53mm; Tension:28V; Tension c.a.:28V
LAMPE SX6S 6MM 28V 1.12W; Tension, alimentation:28V; Lamp Base Type:SX6s; Taille de lampe:T-3 1/4; Puissance:1.12W; MSCP:0.31; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-1 3/4; Durée de vie:10000h; Emission lumineuse, totale:4lm; Longueur/hauteur:16.1mm; Tension:28V; Tension c.a.:28V
LAMPE T1 DEUX BROCHES 12V 0.72W; Tension, alimentation:12V; Taille de lampe:T-1; Puissance:720mW; MSCP:0.01; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:T1; Durée de vie:10000h; Emission lumineuse, totale:1.9lm; Longueur cordon:6.4mm; Longueur/hauteur:9.65mm; Pas:2.54mm; Tension:12V; Tension c.a.:12V
LAMPE T1 DEUX BROCHES 24V 0.58W; Tension, alimentation:24V; Taille de lampe:T-1; Puissance:580mW; MSCP:0.01; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.024A; Dimension de la lentille:T1; Durée de vie:5000h; Emission lumineuse, totale:1.9lm; Longueur cordon:6.4mm; Longueur/hauteur:9.65mm; Pas:2.54mm; Tension:24V; Tension c.a.:24V
LAMPE T1 W/E 5V 0.3W; Tension, alimentation:5V; Taille de lampe:T-1; Puissance:300mW; MSCP:0.03; Durée de vie moyenne de la lampe:25000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:T1; Durée de vie:25000h; Emission lumineuse, totale:0.4lm; Longueur cordon:35mm; Longueur/hauteur:6.35mm; Tension:5V; Tension c.a.:5V
LAMPE T1 W/E 5V 0.575W; Tension, alimentation:5V; Taille de lampe:T-1; Puissance:560mW; MSCP:0.12; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:0.56W; Courant:0.115A; Courant max.:0.12A; Dimension de la lentille:T1; Durée de vie:20000h; Emission lumineuse, totale:1.5lm; Longueur:6.35mm; Longueur cordon:25mm; Longueur/hauteur:6.35mm; Quantité par paquet:10; Tension:5V; Tension c.a.:5V
LAMPE T1.1/2 W/E 14V 0.56W; Tension, alimentation:14V; Taille de lampe:T-1 1/2; Puissance:560mW; MSCP:0.15; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-1 1/2; Durée de vie:5000h; Emission lumineuse, totale:2lm; Longueur cordon:19mm; Longueur/hauteur:13.5mm; Tension:14V; Tension c.a.:14V
LAMPE T1.1/2 W/E 6V0.36W; Tension, alimentation:6V; Taille de lampe:T-1 1/2; Puissance:360mW; MSCP:0.07; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:T-1 1/2; Durée de vie:10000h; Emission lumineuse, totale:1lm; Longueur cordon:19mm; Longueur/hauteur:13.5mm; Tension:6V; Tension c.a.:6V
LAMPE T1.1/2 12V 1W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:1W; MSCP:0.24; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Dimension de la lentille:T-1 1/2; Durée de vie:5000h; Emission lumineuse, totale:3lm; Longueur/hauteur:18mm; Tension:12V; Tension c.a.:12V
LAMPE T1.1/2 12V 2W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:2W; MSCP:0.59; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.166A; Dimension de la lentille:T-1 1/2; Durée de vie:1000h; Emission lumineuse, totale:7.5lm; Longueur/hauteur:18mm; Tension:12V; Tension c.a.:12V
LAMPE T1.1/2 24V 1.2W; Tension, alimentation:24V; Lamp Base Type:Culot Wedge; Taille de lampe:T-1 1/2; Puissance:1.2W; MSCP:0.5; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.05A; Dimension de la lentille:T-1 1/2; Durée de vie:1000h; Emission lumineuse, totale:6.3lm; Longueur/hauteur:18mm; Tension:24V; Tension c.a.:24V
LAMPE T1.1/4 DEUX BROCHES 24V 1.12W; Tension, alimentation:24V; Taille de lampe:T-1 1/4; Puissance:840mW; MSCP:0.19; Durée de vie moyenne de la lampe:7500h; SVHC:No SVHC (19-Dec-2011); Courant:0.035A; Dimension de la lentille:T-1 1/4; Durée de vie:7500h; Emission lumineuse, totale:1.9lm; Longueur cordon:6.85mm; Longueur/hauteur:14mm; Pas:2.54mm; Tension:24V; Tension c.a.:24V
LAMPE T1.1/4 DEUX BROCHES 6V 0.36W; Tension, alimentation:6V; Taille de lampe:T-1 1/4; Puissance:360mW; MSCP:0.15; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:T-1 1/4; Durée de vie:3000h; Emission lumineuse, totale:1.6lm; Longueur cordon:6.85mm; Longueur/hauteur:14mm; Pas:2.54mm; Tension:6V; Tension c.a.:6V
LAMPE T1.3/4 DEUX BROCHES 14V 1.12W; Tension, alimentation:14V; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.38; Durée de vie moyenne de la lampe:15000h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Diamètre, extérieur:6.0mm; Dimension de la lentille:T-1 3/4; Durée de vie:15000h; Emission lumineuse, totale:3.8lm; Longueur cordon:6.85mm; Longueur/hauteur:15.8mm; Pas:3.17mm; Tension:14V; Tension c.a.:14V
LAMPE T1.3/4 MID.FLANGE 14V 1.12W; Tension, alimentation:14V; Lamp Base Type:Midget Flange, SX6s; Taille de lampe:T-1 3/4; Puissance:1.12W; MSCP:0.38; Durée de vie moyenne de la lampe:15000h; SVHC:No SVHC (19-Dec-2011); Courant:0.08A; Courant, fonctionnement c.c.:0.08A; Diamètre, extérieur:7.37mm; Dimension de la lentille:T-1 3/4; Durée de vie:15000h; Emission lumineuse, totale:3.77lm; Longueur/hauteur:13.3mm; Tension:14V; Tension c.a.:14V; Tension, alimentation c.c.:14V
LAMPE T3.1/4 MBC/MCC 24V 1.2W; Tension, alimentation:24V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:1.2W; MSCP:0.39; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.05A; Dimension de la lentille:T-3 1/4; Durée de vie:5000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:30mm; Tension:24V; Tension c.a.:24V
LAMPE T3.1/4 MBC/MCC 24V 1.96W; Tension, alimentation:24V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:2W; MSCP:0.46; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.07A; Dimension de la lentille:T-3 1/4; Durée de vie:10000h; Emission lumineuse, totale:6.3lm; Longueur/hauteur:30mm; Tension:24V; Tension c.a.:24V
LAMPE T3.1/4 MBC/MCC 24V 2W; Tension, alimentation:24V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:2W; MSCP:0.62; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.083A; Dimension de la lentille:T-3 1/4; Durée de vie:10000h; Emission lumineuse, totale:6.3lm; Longueur/hauteur:28mm; Tension c.a.:24V
LAMPE T3.1/4 MBC/MCC 30V 2W; Tension, alimentation:30V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:2W; MSCP:0.65; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.07A; Dimension de la lentille:T-3 1/4; Durée de vie:5000h; Emission lumineuse, totale:6.3lm; Longueur/hauteur:30mm; Tension c.a.:30V
LAMPE T3.1/4 MBC/MCC 48V 1.92W; Tension, alimentation:48V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:1.92W; MSCP:0.65; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.04A; Dimension de la lentille:T-3 1/4; Durée de vie:5000h; Emission lumineuse, totale:6.3lm; Longueur/hauteur:28mm; Tension:48V; Tension c.a.:48V
LAMPE T3.1/4 MBC/MCC 6.5V 0.97W; Tension, alimentation:6.5V; Lamp Base Type:BA9s; Taille de lampe:T-3 1/4; Puissance:970mW; MSCP:0.59; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:0.15A; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Emission lumineuse, totale:6lm; Longueur/hauteur:28mm; Tension:6.5V; Tension c.a.:6.5V
LAMPE T3.1/4 MES 24V 1.2W; Tension, alimentation:24V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:1.2W; MSCP:0.39; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.05A; Dimension de la lentille:T-3 1/4; Durée de vie:5000h; Emission lumineuse, totale:3.8lm; Longueur/hauteur:28mm; Tension c.a.:24V
LAMPE T3.1/4 MES 24V 1.96W; Tension, alimentation:24V; Lamp Base Type:E10; Taille de lampe:T-3 1/4; Puissance:1.96W; MSCP:0.46; Durée de vie moyenne de la lampe:25000h; SVHC:No SVHC (19-Dec-2011); Courant:0.07A; Dimension de la lentille:T-3 1/4; Durée de vie:25000h; Emission lumineuse, totale:4.5lm; Longueur/hauteur:30mm; Tension:24V; Tension c.a.:24V
LAMPE T3.1/4 12V 1.2W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:1.2W; MSCP:0.4; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.1A; Dimension de la lentille:T-1 3/4; Durée de vie:5000h; Emission lumineuse, totale:5lm; Longueur/hauteur:26.8mm; Tension c.a.:12V
LAMPE T3.1/4 12V 2W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:2W; MSCP:0.8; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.166A; Dimension de la lentille:T-1 3/4; Durée de vie:1000h; Emission lumineuse, totale:13lm; Longueur/hauteur:26.8mm; Tension:12V; Tension c.a.:12V
LAMPE T3.1/4 12V 3W; Tension, alimentation:12V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:3W; MSCP:1.11; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.22A; Dimension de la lentille:T-1 3/4; Durée de vie:1000h; Emission lumineuse, totale:22lm; Longueur/hauteur:26.8mm; Tension:12V; Tension c.a.:12V
LAMPE T3.8 AXIAL W/E 8V 0.6W; Tension, alimentation:8V; Lamp Base Type:A fil axial; Taille de lampe:T-3 4/5; Puissance:600mW; MSCP:0.23; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (19-Dec-2011); Courant:0.1A; Dimension de la lentille:T3.8; Durée de vie:5000h; Emission lumineuse, totale:1.9lm; Longueur cordon:15mm; Longueur/hauteur:20mm; Tension c.a.:8V; Tension, alimentation max..:8V; Tension, alimentation min.:5V
LAMPE WE 3MM 12V 0.72W; Tension, alimentation:12V; Taille de lampe:T-1; Puissance:720mW; MSCP:0.15; Durée de vie moyenne de la lampe:16000h; SVHC:No SVHC (19-Dec-2011); Courant:0.06A; Dimension de la lentille:T1; Durée de vie:16000h; Emission lumineuse, totale:1.9lm; Longueur/hauteur:6.35mm; Tension c.a.:12V
LED T1 DEUX BROCHES 12VAC/DC BLANC CL; Lamp Base Type:Bi-broche; Couleur de LED:Blanc; Intensité lumineuse:600mcd; Taille de lampe:T-1; Tension, alimentation:12V; Courant:12mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:12mA; Courant, fonctionnement c.a.:6mA; Courant, fonctionnement c.c.:12mA; Diamètre, extérieur:3.8mm; Dimension de la lentille:T1; Durée de vie:100000h; Intensité lumineuse typique:600mcd; Températu
LED T1 DEUX BROCHES 28VAC/DC BLANC CL; Lamp Base Type:Bi-broche; Couleur de LED:Blanc; Intensité lumineuse:500mcd; Taille de lampe:T-1; Tension, alimentation:28V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:10mA; Courant, fonctionnement c.a.:5mA; Courant, fonctionnement c.c.:10mA; Diamètre, extérieur:3.8mm; Dimension de la lentille:T1; Durée de vie:100000h; Intensité lumineuse typique:500mcd; Températu
LAMPE DEUX BROCHES 28V; Tension, alimentation:28V; Durée de vie moyenne de la lampe:16000h; SVHC:No SVHC (19-Dec-2011); Courant:24mA; Durée de vie:16000h; Tension:28V; Tension c.a.:28V; Tension, fonctionnement nom.:28V
NEON LAMPE VERT 110V; Tension, alimentation:110V; Lamp Base Type:Bi-broche; Courant:1.5mA; SVHC:No SVHC (19-Dec-2011); Couleur:Green; Couleur:Vert; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Tension c.a.:110V
AMPOULES 2.4V 0.7A PQT DE 2; Tension, alimentation:2.4V; MSCP:1.3; Durée de vie moyenne de la lampe:15h; SVHC:No SVHC (19-Dec-2011); Courant:0.7A; Durée de vie:15h; Longueur/hauteur:165mm; Tension:2.4V
TUBE INCASSABLE T8; Tension, alimentation:230V; Puissance:18W; Longueur:600mm; Diamètre de l'ampoule:26mm; SVHC:No SVHC (19-Dec-2011); Couleur:CW; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:20000h; Durée de vie moyenne de la lampe:20000h; Longueur/hauteur:600mm; Tension d'alimentation Vac:230V
NEON LAMPE VERT 250V; Tension, alimentation:220V; Lamp Base Type:Bi-broche; Courant:1.5mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Couleur:Vert; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Tension c.a.:220V
TUBE INCASSABLE T8; Tension, alimentation:230V; Puissance:36W; Longueur:1.2m; Diamètre de l'ampoule:26mm; SVHC:No SVHC (19-Dec-2011); Couleur:CW; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:20000h; Durée de vie moyenne de la lampe:20000h; Longueur/hauteur:1200mm; Tension d'alimentation Vac:230V
KIT DE DEMARRAGE TUBE 8W; Longueur:420mm; Largeur:175mm; Profondeur:90mm; Working Area:159mm x 229mm; SVHC:No SVHC (20-Jun-2011)
LAMPE DEUX BROCHES 5V; Tension, alimentation:5V; Durée de vie moyenne de la lampe:3000h; SVHC:No SVHC (19-Dec-2011); Courant:60mA; Durée de vie:3000h; Tension:5V; Tension c.a.:5V; Tension, fonctionnement nom.:5V
LAMPE DEUX BROCHES 14V; Tension, alimentation:14V; Durée de vie moyenne de la lampe:16000h; SVHC:No SVHC (19-Dec-2011); Courant:40mA; Durée de vie:16000h; Tension:14V; Tension c.a.:14V; Tension, fonctionnement nom.:14V
NEON LAMPE ROUGE 110V; Tension, alimentation:110V; Lamp Base Type:Bi-broche; Courant:1.5mA; SVHC:No SVHC (19-Dec-2011); Couleur:Red; Couleur:Rouge; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Tension c.a.:110V
NEON LAMPE ROUGE 220V; Tension, alimentation:220V; Lamp Base Type:Bi-broche; Courant:1.5mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Couleur:Rouge; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Tension c.a.:220V
AMPOULES 2.2V 0.47A PQT DE 2; Tension, alimentation:2.2V; Durée de vie moyenne de la lampe:15h; SVHC:No SVHC (19-Dec-2011); Courant:0.47A; Durée de vie:15h; Longueur/hauteur:31mm; Tension:2.2V
LAMPE XENON CULOT T10 12V 6W; Tension, alimentation:12V; Puissance:3W; Taille de lampe:T-3 1/4; Courant:444mA; Longueur:26.8mm; Lamp Base Type:Wedge; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:10.3mm; Dimension de la lentille:T-3 1/4; Durée de vie:1000h; Durée de vie moyenne de la lampe:1000h; Intensité lumineuse, max..:102lm; Longueur/hauteur:20.7mm; Normes:T10; Tension, alimentation c.c. max..:12V; Type de boîtier:10.3 x 26.8mm
LED. BA9S 130V BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:500mcd; Tension, alimentation:130V; Courant:5mA; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:5mA; Courant, fonctionnement c.a.:5mA; Dimension de la lentille:BA9s; Intensité lumineuse typique:500mcd; Nombre de LED:3; Température de fonctionnement:-20°C +60°C; Tension, Vf max..:130V; Tension, alimentation c.a. max..:130V; Tension, direct If:130VAC; Tension d'alimentation
LED. BA9S 230V BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:300mcd; Tension, alimentation:230V; Courant:3mA; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:3mA; Courant, fonctionnement c.a.:3mA; Dimension de la lentille:BA9s; Intensité lumineuse typique:300mcd; Nombre de LED:3; Température de fonctionnement:-20°C +60°C; Tension, Vf max..:230V; Tension, alimentation c.a. max..:230V; Tension, direct If:230VAC; Tension d'alimentation
INDICATEUR MININEUX CARRE; SVHC:No SVHC (19-Dec-2011); Couleur:Noir; Epaisseur, panneau max..:4.75mm; Epaisseur, panneau min.:1.52mm; Largeur (externe):18.92mm; Largeur, biseau:20.3mm; Largeur, corps:18.92mm; Longueur/hauteur:36mm; Profondeur:18.92mm; Profondeur, biseau:20.3mm; Température de fonctionnement max..:55°C; Température d'utilisation min:0°C; Type de borne:Solder or Quick Connect
LAMPE XENON CULOT T10 12V 5W; Tension, alimentation:12V; Puissance:5W; Taille de lampe:T-3 1/4; Courant:370mA; Longueur:26.8mm; Lamp Base Type:Wedge; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:10.3mm; Dimension de la lentille:T-3 1/4; Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:60lm; Longueur/hauteur:26.8mm; Normes:T10; Tension, alimentation c.c. max..:12V; Type de boîtier:10.3 x 26.8mm
KIT DE DEMARRAGE TUBE 15W; Longueur:515mm; Largeur:400mm; Profondeur:120mm; Working Area:260mm x 330mm; SVHC:No SVHC (20-Jun-2011)
LAMPE NEON 110V; Tension, alimentation:110V; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Diamètre, extérieur:4.5mm; Dimension de la lentille:T-1 3/4; Longueur:14mm; Longueur/hauteur:14mm; Taille de lampe:5mm / T-1 3/4; Tension d'alimentation Vac:110V
AMPOULE GU10 XENON 20W; Tension, alimentation:240V; Puissance:20W; Longueur:50mm; Lamp Base Type:GU10; Couleur:Clear; Couleur:Clair; Diamètre, extérieur:50mm; Dimension de la lentille:GU10; Durée de vie:5000h; Durée de vie moyenne de la lampe:5000h; Longueur/hauteur:50mm; Tension d'alimentation Vac:240V
AMPOULE DOUBLE D. 16W. 4PIN. 3500K; Tension, alimentation:230V; Lamp Base Type:GR10q; Puissance:16W; Flux lumineux:1050lm; Longueur:132mm; Température, couleur:3500K; Couleur:White; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Flux lumineux typique:1050lm; Intensité lumineuse, max..:1050lm; Largeur (externe):132mm; Longueur/hauteur:132mm; Nombre de broches:4
AMPOULE CAPSULE 240V G9 25W; Tension, alimentation:240V; Lamp Base Type:G9; Puissance:25W; Longueur:40mm; Base Type:G9; Couleur:Clear; Dimension de la lentille:G9; Durée de vie:4000h; Durée de vie moyenne de la lampe:4000h; Taille de lampe:G9; Tension d'alimentation Vac:240V
AMPOULE VERTE REFLECTRICE 60W 240V; Tension, alimentation:240V; Taille de lampe:80mm; Puissance:60W; Angle:80°; Couleur:Vert; Diamètre, extérieur:80mm; Dimension de la lentille:80mm; Longueur/hauteur:109mm; Tension c.a.:240V; Tension d'alimentation Vac:240V
AMPOULE BASSE ENERGIE GU10. 11W. 2700K; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:11W; Flux lumineux:360lm; Longueur:75mm; Diamètre de l'ampoule:50mm; Température, couleur:2700K; Diamètre, extérieur:50mm; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Emission lumineuse, totale:360lm; Flux lumineux typique:360lm; Longueur/hauteur:75mm; Tension d'alimentation Vac:240V
AMPOULE LED. GU10. 3W. BLANCHE; Lamp Base Type:GU10; Couleur de LED:Blanc; Puissance:3W; Tension, alimentation:240V; Durée de vie moyenne de la lampe:50000h; Couleur:Blanc; Couleur:White; Diamètre, extérieur:51mm; Diamètre, réflecteur:51mm; Durée de vie:50000h; Longueur:58mm; Longueur/hauteur:58mm; Tension, direct If:240V; Tension d'alimentation Vac:240V
AMPOULE DOUBLE CULOTS 110V. 500W. 118MM; Tension, alimentation:110V; Lamp Base Type:R7s; Puissance:500W; Longueur:118mm; Couleur:Clear; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:110V
AMPOULE DOUBLE D. 28W. 4PIN. 3500K; Tension, alimentation:230V; Lamp Base Type:GR10q; Puissance:28W; Flux lumineux:2250lm; Longueur:196mm; Température, couleur:3500K; Couleur:White; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Flux lumineux typique:2250lm; Intensité lumineuse, max..:2250lm; Largeur (externe):196mm; Longueur/hauteur:196mm; Nombre de broches:4
AMPOULE DOUBLE D. 38W. 4PIN. 3500K; Tension, alimentation:230V; Lamp Base Type:GR10q; Puissance:38W; Flux lumineux:3000lm; Longueur:198mm; Température, couleur:3500K; Couleur:White; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Flux lumineux typique:3000lm; Intensité lumineuse, max..:3000lm; Largeur (externe):198mm; Longueur/hauteur:198mm; Nombre de broches:4
AMPOULE CAPSULE 12V 20W G4; Tension, alimentation:12V; Lamp Base Type:G4; Puissance:20W; Longueur:33mm; Base Type:G4; Couleur:Clear; Dimension de la lentille:G4; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Taille de lampe:G4; Tension, alimentation c.c.:12V
AMPOULE CAPSULE 240V G9 40W FROST; Tension, alimentation:240V; Lamp Base Type:G9; Puissance:40W; Longueur:40mm; Base Type:G9; Couleur:Frosted; Dimension de la lentille:G9; Durée de vie:4000h; Durée de vie moyenne de la lampe:4000h; Taille de lampe:G9; Tension d'alimentation Vac:240V
AMPOULE LUMIERE DU JOUR 6400K. 18W. E27; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:18W; Flux lumineux:875lm; Longueur:113mm; Diamètre de l'ampoule:45mm; Température, couleur:6400K; Diamètre, extérieur:45mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:113mm; Puissance GLS équivalente:100W; Tension d'alimentation Vac:240V
AMPOULE LED. GU10. 3W. W-BLANCHE; Lamp Base Type:GU10; Couleur de LED:Blanc chaud; Puissance:3W; Tension, alimentation:240V; Durée de vie moyenne de la lampe:50000h; Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:51mm; Diamètre, réflecteur:51mm; Durée de vie:50000h; Longueur:58mm; Longueur/hauteur:58mm; Tension, direct If:240V; Tension d'alimentation Vac:240V
BLOC IP65 POLYCARBONATE BLANC PRIS. 28W; Largeur:286mm; Profondeur:81mm; Couleur:Blanc; Puissance:28W; Tension, alimentation:230V
BLOC IP65 POLYCARBONATE PRIS. 28W; Largeur:286mm; Profondeur:81mm; Couleur:Noir; Puissance:28W; Tension, alimentation:230V
AMPOULE LUMIERE DU JOUR 6400K. 18W. B22; Tension, alimentation:240V; Puissance:18W; Flux lumineux:875lm; Longueur:113mm; Diamètre de l'ampoule:45mm; Température, couleur:6400K; Diamètre, extérieur:45mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:113mm; Puissance GLS équivalente:100W; Tension d'alimentation Vac:240V
AMPOULE BASSE ENERGIE GU10. 11W. 4000K; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:11W; Flux lumineux:360lm; Longueur:75mm; Diamètre de l'ampoule:50mm; Température, couleur:4000K; Diamètre, extérieur:50mm; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Emission lumineuse, totale:360lm; Flux lumineux typique:360lm; Longueur/hauteur:75mm; Tension d'alimentation Vac:240V
AMPOULE ECONOMIQUE R63. 7W. E27; Tension, alimentation:240V; Lamp Base Type:ES; Puissance:7W; Longueur:125mm; Diamètre de l'ampoule:63mm; Température, couleur:2700K; Diamètre, extérieur:63mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:125mm; Tension d'alimentation Vac:240V
AMPOULE DOUBLE CULOTS 240V. 150W. 80MM; Tension, alimentation:240V; Lamp Base Type:R7s; Puissance:150W; Longueur:80mm; Couleur:Clear; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:240V
AMPOULE DOUBLE CULOTS 240V. 200W. 80MM; Tension, alimentation:240V; Lamp Base Type:R7s; Puissance:200W; Longueur:80mm; Couleur:Clear; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:240V
LAMPE 40W SE27 TRANSPARENT; Tension, alimentation:240V; Puissance:40W; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (20-Jun-2011); Couleur:Clear; Diamètre, extérieur:25mm; Durée de vie:1000h; Longueur/hauteur:82mm; Tension:230V; Tension c.a.:240V
LAMPE GU10 50W 30DEG ALU; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:50W; Diamètre, réflecteur:50mm; SVHC:No SVHC (20-Jun-2011); Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension c.a.:240V
LAMPE CAPSULE 12V 20W G5; Tension, alimentation:12V; Lamp Base Type:G4; Puissance:20W; Longueur:31mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:320lm; Tension, alimentation c.c.:12V
LAMPE CAPSULE 12V 20W GY6.36; Tension, alimentation:12V; Lamp Base Type:GY6,35; Puissance:20W; Longueur:44mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:300lm; Tension, alimentation c.c.:12V
LAMPE CAPSULE 24V 100W GY6.36; Tension, alimentation:24V; Lamp Base Type:GY6,35; Puissance:100W; Longueur:44mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:2200lm; Tension, alimentation c.c.:24V
LAMPE 13.8V 25W GZ5; Tension, alimentation:13.8V; Lamp Base Type:GZ4; Puissance:25W; Diamètre, réflecteur:35mm; SVHC:No SVHC (20-Jun-2011); Diamètre, extérieur:35mm; Tension, alimentation c.c.:13.8V
LAMPE 12V 100W GZ6.36; Tension, alimentation:12V; Lamp Base Type:GZ6,35; Puissance:100W; Longueur:42mm; Diamètre, réflecteur:50mm; SVHC:No SVHC (20-Jun-2011); Diamètre, extérieur:50mm; Tension, alimentation c.c.:12V
LAMPE 12V 100W G6.36; Tension, alimentation:12V; Lamp Base Type:G 6,35; Puissance:100W; Longueur:44mm; SVHC:No SVHC (20-Jun-2011); Tension, alimentation c.c.:12V
LAMPE 15V 150W GY6.36; Tension, alimentation:15V; Lamp Base Type:GY6,35; Puissance:150W; Longueur:44mm; SVHC:No SVHC (20-Jun-2011); Tension, alimentation c.c.:15V
LAMPE T8 18W 600MM 3500K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:18W; Flux lumineux:1350lm; Longueur:600mm; Diamètre de l'ampoule:26mm; Température, couleur:3500K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc; Couleur:White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:1350lm; Intensité lumineuse, max..:1350lm; Longueur/hauteur:600mm; Tension d'alimentation Vac:240V
LAMPE T8 30W 900MM 4000K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:30W; Flux lumineux:2400lm; Longueur:900mm; Diamètre de l'ampoule:26mm; Température, couleur:4000K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:2400lm; Intensité lumineuse, max..:2400lm; Longueur/hauteur:900mm; Tension d'alimentation Vac:240V
LAMPE T8 36W 1200MM 6500K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:36W; Flux lumineux:3250lm; Longueur:1.2m; Diamètre de l'ampoule:26mm; Température, couleur:6500K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:3250lm; Intensité lumineuse, max..:3250lm; Longueur/hauteur:1200mm; Tension d'alimentation Vac:240V
LED BA15D 24V BLANC; Lamp Base Type:BA15d; Couleur de LED:Blanc; Intensité lumineuse:1500mcd; Tension, alimentation:24V; Courant:45mA; SVHC:No SVHC (19-Dec-2011); Couleur:White; Couleur, LED:Blanc; Courant, direct, If:45mA; Courant, fonctionnement c.a.:45mA; Courant, fonctionnement c.c.:45mA; Dimension de la lentille:BA15d; Intensité lumineuse typique:1500mcd; Nombre de LED:9; Température de fonctionnement:-20°C +60°C; Température de fonctionnement max..:60°C; Température, stockage max..:80°C;
LED. BA9S 6V BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:245mcd; Tension, alimentation:6V; Courant:75mA; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:470mW; Couleur:White; Couleur, LED:Blanc; Courant, direct, If:75mA; Courant, fonctionnement c.c.:75mA; Dimension de la lentille:BA9s; Intensité lumineuse typique:245mcd; Nombre de LED:1; Température de fonctionnement:-20°C +65°C; Température de fonctionnement max..:65°C; Température, couleur:6500K; Température,
LAMPE 15W SE27 TRANSPARENT; Tension, alimentation:240V; Puissance:15W; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (20-Jun-2011); Couleur:Clear; Diamètre, extérieur:22mm; Durée de vie:1000h; Longueur/hauteur:50mm; Température de fonctionnement max..:300°C; Tension:240V; Tension c.a.:240V
LAMPE CAPSULE 12V 10W G5; Tension, alimentation:12V; Lamp Base Type:G4; Puissance:10W; Longueur:31mm; Température, couleur:2850K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:140lm; Tension, alimentation c.c.:12V
LAMPE CAPSULE 24V 20W G5; Tension, alimentation:24V; Lamp Base Type:G4; Puissance:20W; Longueur:32mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:300lm; Tension, alimentation c.c.:24V
LAMPE CAPSULE 12V 75W GY6.36; Tension, alimentation:12V; Lamp Base Type:GY6,35; Puissance:75W; Longueur:44mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:1595lm; Tension, alimentation c.c.:12V
LAMPE 24V 150W GY6.36; Tension, alimentation:24V; Lamp Base Type:GY6,35; Puissance:150W; SVHC:No SVHC (20-Jun-2011); Intensité lumineuse, max..:5200lm; Tension, alimentation c.c.:24V
LAMPE 36V 400W GY6.36; Tension, alimentation:36V; Lamp Base Type:GY6,35; Puissance:400W; Longueur:60mm; SVHC:No SVHC (20-Jun-2011); Tension, alimentation c.c.:36V
LAMPE T8 18W 600MM 4000K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:18W; Flux lumineux:1350lm; Longueur:600mm; Diamètre de l'ampoule:26mm; Température, couleur:4000K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:1350lm; Intensité lumineuse, max..:1350lm; Longueur/hauteur:600mm; Tension d'alimentation Vac:240V
LAMPE T8 36W 1200MM 3000K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:36W; Flux lumineux:3350lm; Longueur:1.2m; Diamètre de l'ampoule:26mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:3350lm; Intensité lumineuse, max..:3350lm; Longueur/hauteur:1200mm; Tension d'alimentation Vac:240V
LAMPE T8 36W 1200MM 4000K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:36W; Flux lumineux:3350lm; Longueur:1.2m; Diamètre de l'ampoule:26mm; Température, couleur:4000K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:3350lm; Intensité lumineuse, max..:3350lm; Longueur/hauteur:1200mm; Tension d'alimentation Vac:240V
LAMPE T8 58W 1500MM 2700K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:58W; Flux lumineux:5200lm; Longueur:1.5m; Diamètre de l'ampoule:26mm; Température, couleur:2700K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc; Couleur:White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:5200lm; Intensité lumineuse, max..:5200lm; Longueur/hauteur:1500mm; Tension d'alimentation Vac:240V
LAMPE T8 58W 1500MM 3000K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:58W; Flux lumineux:5200lm; Longueur:1.5m; Diamètre de l'ampoule:26mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:5200lm; Intensité lumineuse, max..:5200lm; Longueur/hauteur:1500mm; Tension d'alimentation Vac:240V
LAMPE T8 58W 1500MM 6500K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:58W; Flux lumineux:5000lm; Longueur:1.5m; Diamètre de l'ampoule:26mm; Température, couleur:6500K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:5000lm; Intensité lumineuse, max..:5000lm; Longueur/hauteur:1500mm; Tension d'alimentation Vac:240V
LAMPE 25W SE27 TRANSPARENT; Tension, alimentation:240V; Puissance:25W; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (20-Jun-2011); Couleur:Clear; Diamètre, extérieur:25mm; Durée de vie:1000h; Longueur/hauteur:55mm; Température de fonctionnement max..:300°C; Tension:240V; Tension c.a.:240V
LAMPE IR 250W E27; Tension, alimentation:240V; Lamp Base Type:E27; Taille de lampe:R-125; Puissance:250W; Durée de vie moyenne de la lampe:5000h; SVHC:No SVHC (20-Jun-2011); Diamètre, extérieur:125mm; Durée de vie:5000h; Tension:250V; Tension c.a.:240V; Tension, alimentation c.a. max..:250V
LAMPE 12V 75W GZ6.36; Tension, alimentation:12V; Lamp Base Type:GZ6,35; Puissance:75W; Longueur:42mm; Diamètre, réflecteur:50mm; SVHC:No SVHC (20-Jun-2011); Diamètre, extérieur:50mm; Tension, alimentation c.c.:12V
LAMPE 12V 50W G6.36; Tension, alimentation:12V; Lamp Base Type:G 6,35; Puissance:50W; Longueur:44mm; SVHC:No SVHC (20-Jun-2011); Tension, alimentation c.c.:12V
LAMPE T8 18W 600MM 2700K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:18W; Flux lumineux:1350lm; Longueur:600mm; Diamètre de l'ampoule:26mm; Température, couleur:2700K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc; Couleur:White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:1350lm; Intensité lumineuse, max..:1350lm; Longueur/hauteur:600mm; Tension d'alimentation Vac:240V
LAMPE T8 30W 900MM 3000K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:30W; Flux lumineux:2400lm; Longueur:900mm; Diamètre de l'ampoule:26mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc chaud; Couleur:Warm White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:2400lm; Intensité lumineuse, max..:2400lm; Longueur/hauteur:900mm; Tension d'alimentation Vac:240V
LAMPE NEON 220V; Tension, alimentation:220V; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Diamètre, extérieur:4.5mm; Dimension de la lentille:T-1 3/4; Longueur:14mm; Longueur/hauteur:14mm; Taille de lampe:5mm / T-1 3/4; Tension d'alimentation Vac:220V
LAMPE NEON BA9S 230V ROUGE; Tension, alimentation:230V; Lamp Base Type:BA9s; Courant:2.4mA; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge; Diamètre, extérieur:10mm; Dimension de la lentille:BA9s; Longueur/hauteur:28.3mm; Taille de lampe:BA9s; Température de fonctionnement max..:60°C; Température d'utilisation min:-20°C; Tension c.a.:230V; Tension, alimentation c.a. min:95V; Tension, attaque c.a.:95V
LAMPE T3.1/4 MES 3.7V 1.11W; Tension, alimentation:3.7V; Lamp Base Type:MES (E10 / 13); Taille de lampe:T-3 1/4; Puissance:1.11W; SVHC:No SVHC (19-Dec-2011); Courant:0.3A; Dimension de la lentille:T-3 1/4 MES; Longueur/hauteur:24mm; Tension:3.7V
LAMPE P13.5S 6V 4.5W; Tension, alimentation:6V; Lamp Base Type:B-3 1/2; Taille de lampe:B-3 1/2; Puissance:4.5W; MSCP:5.96; SVHC:No SVHC (19-Dec-2011); Courant:0.75A; Diamètre, extérieur:13.5mm; Dimension de la lentille:B-3 1/2; Emission lumineuse, totale:75lm; Longueur/hauteur:31.8mm; Tension:6V
LAMPE HALOGENE P13.5S 6V 4.2W; Tension, alimentation:6V; Lamp Base Type:MES (E10 / 13); Puissance:4.2W; Longueur:30mm; SVHC:No SVHC (19-Dec-2011); Courant:0.7A; Tension, alimentation c.c.:6V
LAMPE HALOGENE MES 6V 4.2W; Tension, alimentation:6V; Lamp Base Type:MES (E10 / 13); Puissance:4.2W; Longueur:30mm; SVHC:No SVHC (19-Dec-2011); Courant:0.7A; Tension, alimentation c.c.:6V
LED MF T1 3/4 24VDC JAUNE; Lamp Base Type:Midget Flange; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:59mcd; Taille de lampe:6mm; Tension, alimentation:24V; Courant:14mA; SVHC:No SVHC (19-Dec-2011); Couleur:Jaune; Couleur, LED:Jaune; Courant, direct, If:14mA; Diamètre, extérieur:6.35mm; Dimension de la lentille:6mm; Intensité lumineuse typique:59mcd; Longueur d'onde dominante typ.:585nm; Température de fonctionnement:-20°C +60°C; Température de fonctionnement max..:60°
INDICATEUR A NEON M14 230V VERT; Tension, alimentation:230V; Lamp Base Type:Fil; Intensité lumineuse:26mcd; Couleur:Vert; Diamètre trou de fixation:14mm; Courant:1.5mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Vert; Diamètre, extérieur:16mm; IP / NEMA Rating:IP67; Intensité lumineuse typique:26mcd; Matière:Satin Chrome Bezel; Taille du filetage:M14 thread; Température de fonctionnement max..:60°C; Température d'utilisation min:-20°C; Tension c.a.:230V
LED T5.5K 24VAC/DC BLANC; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:T-5 1/2; Tension, alimentation:24V; Courant:14mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Couleur, LED:Blanc; Courant, direct, If:14mA; Dimension de la lentille:3; Intensité lumineuse typique:700mcd; Température de fonctionnement:-20°C +60°C; Tension, Vf max..:24V; Tension, direct If:24V
LED T10X25 BA9S BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:750mcd; Taille de lampe:T-3 1/4; Tension, alimentation:12V; Courant:16mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc diffus; Couleur, LED:Blanc; Courant, direct, If:16mA; Diamètre, extérieur:10mm; Dimension de la lentille:T-3 1/4; Durée de vie:100000h; Intensité lumineuse, max..:750mcd; Longueur/hauteur:25mm; Température de fonctionnement max..:+60°C; Température d'utili
AMPOULE DOUBLE D. 16W. 2PIN. 3500K; Tension, alimentation:230V; Lamp Base Type:GR8; Puissance:16W; Flux lumineux:1050lm; Longueur:132mm; Température, couleur:3500K; Couleur:White; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Flux lumineux typique:1050lm; Intensité lumineuse, max..:1050lm; Largeur (externe):132mm; Longueur/hauteur:132mm; Nombre de broches:2
AMPOULE GU10 XENON 50W; Tension, alimentation:240V; Puissance:50W; Longueur:50mm; Lamp Base Type:GU10; Couleur:Clear; Couleur:Clair; Diamètre, extérieur:50mm; Dimension de la lentille:GU10; Durée de vie:5000h; Durée de vie moyenne de la lampe:5000h; Longueur/hauteur:50mm; Tension d'alimentation Vac:240V
AMPOULE CAPSULE 12V 10W G4; Tension, alimentation:12V; Lamp Base Type:G4; Puissance:10W; Longueur:33mm; Base Type:G4; Couleur:Clear; Dimension de la lentille:G4; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Taille de lampe:G4; Tension, alimentation c.c.:12V
AMPOULE CAPSULE 240V G9 40W; Tension, alimentation:240V; Lamp Base Type:G9; Puissance:40W; Longueur:40mm; Base Type:G9; Couleur:Clear; Dimension de la lentille:G9; Durée de vie:4000h; Durée de vie moyenne de la lampe:4000h; Taille de lampe:G9; Tension d'alimentation Vac:240V
SPOT A LED AVEC FLEXIBLE EURO; Tension, alimentation:240V; Puissance:10W; Light Source:LED; Longueur:655mm; Diamètre, lentille:45mm; Fréquence, alimentation max..:60Hz; IP / NEMA Rating:IP67; Longueur (max..):600mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:100V; Tension d'alimentation Vac:240V
LAMPE T3.1/4 MES 2.5V 0.75W; Tension, alimentation:2.5V; Lamp Base Type:MES (E10 / 13); Taille de lampe:T-3 1/4; Puissance:750mW; SVHC:No SVHC (19-Dec-2011); Courant:0.3A; Dimension de la lentille:T-3 1/4 MES; Longueur/hauteur:21mm; Tension:2.5V
LAMPE P13.5S 12V 3W; Tension, alimentation:12V; Lamp Base Type:B-3 1/2; Taille de lampe:B-3 1/2; Puissance:3W; MSCP:2.7; SVHC:No SVHC (19-Dec-2011); Courant:0.25A; Diamètre, extérieur:13.5mm; Dimension de la lentille:B-3 1/2; Emission lumineuse, totale:34lm; Longueur/hauteur:31.8mm; Tension:12V
LAMPE HALOGENE MES 4V 3.4W; Tension, alimentation:4V; Lamp Base Type:MES (E10 / 13); Puissance:3.4W; Longueur:30mm; SVHC:No SVHC (19-Dec-2011); Courant:0.85A; Tension, alimentation c.c.:4V
INDICATEUR A NEON M14 230V ROUGE; Tension, alimentation:230V; Lamp Base Type:Fil; Intensité lumineuse:33mcd; Couleur:Rouge; Diamètre trou de fixation:14mm; Courant:2.3mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Rouge; Diamètre, extérieur:16mm; IP / NEMA Rating:IP67; Intensité lumineuse typique:33mcd; Matière:Satin Chrome Bezel; Taille du filetage:M14 thread; Température de fonctionnement max..:60°C; Température d'utilisation min:-20°C; Tension c.a.:230V
INDICATEUR A NEON M14 240V AMB; Tension, alimentation:230V; Lamp Base Type:Fil; Intensité lumineuse:61mcd; Couleur:Ambre; Diamètre trou de fixation:14mm; Courant:2.2mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Ambre; Diamètre, extérieur:16mm; IP / NEMA Rating:IP67; Intensité lumineuse typique:61mcd; Matière:Black Chrome Bezel; Taille du filetage:M14 thread; Température de fonctionnement max..:60°C; Température d'utilisation min:-20°C; Tension c.a.:240V
LED T5.5K 24VDC U/VERT; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:2100mcd; Taille de lampe:T-5 1/2; Tension, alimentation:24V; Courant:14mA; SVHC:No SVHC (19-Dec-2011); Couleur:Vert; Couleur, LED:Vert; Courant, direct, If:14mA; Dimension de la lentille:3; Intensité lumineuse typique:2100mcd; Température de fonctionnement:-20°C +60°C; Tension, Vf max..:24V; Tension, direct If:24V
LED E10 T10X25 12V BLANC; Lamp Base Type:E10; Couleur de LED:Blanc; Intensité lumineuse:800mcd; Taille de lampe:T-3 1/4; Tension, alimentation:12V; Courant:16mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc diffus; Couleur, LED:Blanc; Courant, direct, If:16mA; Diamètre, extérieur:10mm; Dimension de la lentille:T-3 1/4; Intensité lumineuse, max..:800mcd; Longueur/hauteur:25mm; Température de fonctionnement max..:-20°C; Température d'utilisation min:+60°C; Tension, direct If:12V; Tolérance, tensio
AMPOULE BASSE ENERGIE FLAMME B15 3W; Tension, alimentation:240V; Puissance:3W; Longueur:120mm; Diamètre de l'ampoule:42mm; Température, couleur:2700K; Couleur:Warm White; Couleur:Blanc chaud; Diamètre, extérieur:42mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:120mm; Puissance GLS équivalente:20W; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:19mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:250V
SUPPORT DE LAMPE; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Diamètre de découpe panneau:19mm; Diamètre, lentille:17mm; Dimension de la lentille:E10; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:54.8mm; Matière:Corps en plastique avec lunette d'encadrement chromée; Profondeur, lentille:16mm; Tension c.a.:50V; Type de borne:Cosses 6.35mm
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Rouge; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Rouge / Noir; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.75mm; Tension d'alimentation Vac:250V
LAMPE T3.1/4 MES 2.2V 0.55W; Tension, alimentation:2.2V; Lamp Base Type:MES (E10 / 13); Taille de lampe:T-3 1/4; Puissance:550mW; SVHC:No SVHC (19-Dec-2011); Courant:0.25A; Dimension de la lentille:T-3 1/4 MES; Longueur/hauteur:21mm; Tension:2.2V
LED T6.8 24VAC/DC; Lamp Base Type:Ampoule de téléphonie, T6,8; Couleur de LED:Blanc; Intensité lumineuse:850mcd; Taille de lampe:7.1mm; Tension, alimentation:24V; Courant:17mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Couleur, LED:Blanc; Courant, direct, If:17mA; Dimension de la lentille:7.1mm; Intensité lumineuse typique:850mcd; Température de fonctionnement:-20°C +60°C; Tension, Vf max..:24V; Tension, direct If:24V
LED T6.8 28VAC/DC BLANC; Lamp Base Type:Ampoule de téléphonie, T6,8; Couleur de LED:Blanc; Intensité lumineuse:850mcd; Taille de lampe:7.1mm; Tension, alimentation:28V; Courant:17mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Couleur, LED:Blanc; Courant, direct, If:17mA; Dimension de la lentille:7.1mm; Intensité lumineuse typique:850mcd; Température de fonctionnement:-20°C +60°C; Tension, Vf max..:28V; Tension, direct If:28V
LED T10X28 BA9S LED 24V BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:1400mcd; Taille de lampe:10mm; Tension, alimentation:24V; Courant:14mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Couleur, LED:Blanc; Courant, direct, If:14mA; Dimension de la lentille:10; Intensité lumineuse typique:1400mcd; Température de fonctionnement:-20°C +60°C; Tension, Vf max..:24V; Tension, direct If:24V
LAMPE XENON 2.3V 0.3A; Tension, alimentation:2.3V; Courant:300mA; SVHC:No SVHC (19-Dec-2011); Consommation de courant:0.3A; Durée de vie:30h; Durée de vie moyenne de la lampe:30h; Emission lumineuse, totale:15lm; Intensité lumineuse, max..:15lm; Tension, alimentation c.c.:2.3V
AMPOULE LUMIERE DU JOUR 6400K. 30W. B22; Tension, alimentation:240V; Puissance:30W; Flux lumineux:1535lm; Longueur:170mm; Diamètre de l'ampoule:55mm; Température, couleur:6400K; Diamètre, extérieur:55mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:170mm; Puissance GLS équivalente:150W; Tension d'alimentation Vac:240V
AMPOULE ECONOMIQUE GLS 15W B22; Tension, alimentation:240V; Puissance:15W; Flux lumineux:610lm; Longueur:135mm; Diamètre de l'ampoule:60mm; Température, couleur:2700K; Diamètre, extérieur:60mm; Longueur/hauteur:135mm; Puissance GLS équivalente:75W; Tension d'alimentation Vac:240V
AMPOULE BASSE ENERGIE GU10. 7W. 2700K; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:7W; Flux lumineux:200lm; Longueur:55mm; Diamètre de l'ampoule:50mm; Température, couleur:2700K; Diamètre, extérieur:50mm; Durée de vie:10000h; Durée de vie moyenne de la lampe:10000h; Emission lumineuse, totale:200lm; Flux lumineux typique:200lm; Longueur/hauteur:55mm; Tension d'alimentation Vac:240V
AMPOULE DOUBLE CULOTS 240V. 100W. 80MM; Tension, alimentation:240V; Lamp Base Type:R7s; Puissance:100W; Longueur:80mm; Couleur:Clear; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:240V
AMPOULE DOUBLE CULOTS 240V. 200W. 118MM; Tension, alimentation:240V; Lamp Base Type:R7s; Puissance:200W; Longueur:118mm; Couleur:Clear; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:240V
AMPOULE DOUBLE CULOTS 240V. 500W. 118MM; Tension, alimentation:240V; Lamp Base Type:R7s; Puissance:500W; Longueur:118mm; Couleur:Clear; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:240V
BLOC GU10 240V 20W PROLITE TRANSPARENT; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:20W; Longueur:56mm; Diamètre, réflecteur:50mm; Angle:36°; Diamètre, extérieur:50mm; Intensité lumineuse, max..:400cd; Tension d'alimentation Vac:240V
BLOC GU10 240V 50W PROLITE TRANSPARENT; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:50W; Longueur:56mm; Diamètre, réflecteur:50mm; Angle:36°; Diamètre, extérieur:50mm; Intensité lumineuse, max..:1000cd; Tension d'alimentation Vac:240V
BLOC IP65 POLYCARBONATE BLANC OPAQUE; Largeur:286mm; Profondeur:81mm; Couleur:Blanc; Puissance:28W; Tension, alimentation:230V
ENCASTRE BASSE TENSION MOULE FIXE CHROME; Profondeur:116mm; Diamètre, extérieur:80mm; Largeur (externe):80mm; Light Source:Halogène; Longueur/hauteur:116mm; Puissance:50W; Tension, alimentation:12V
LAMPE 11W; Tension, alimentation:230V; Lamp Base Type:G23; Puissance:11W; Light Source:Strip; Longueur:480mm; SVHC:No SVHC (19-Dec-2011); Couleur, base:Black; IP / NEMA Rating:IP44; Longueur (max..):480mm; Longueur cordon:5m; Poids:0.7kg; Tension d'alimentation Vac:230V
LAMPE 40W SE27 TRANSPARENT; Tension, alimentation:240V; Puissance:40W; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (20-Jun-2011); Couleur:Clear; Diamètre, extérieur:45mm; Durée de vie:1000h; Longueur/hauteur:75mm; Température de fonctionnement max..:300°C; Tension:240V; Tension c.a.:240V
LAMPE CAPSULE 12V 35W GY6.36; Tension, alimentation:12V; Lamp Base Type:GY6,35; Puissance:35W; Longueur:44mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:600lm; Tension, alimentation c.c.:12V
LAMPE CAPSULE 12V 50W GY6.36; Tension, alimentation:12V; Lamp Base Type:GY6,35; Puissance:50W; Longueur:44mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:905lm; Tension, alimentation c.c.:12V
LAMPE CAPSULE 12V 100W GY6.36; Tension, alimentation:12V; Lamp Base Type:GY6,35; Puissance:100W; Longueur:44mm; Température, couleur:3000K; SVHC:No SVHC (20-Jun-2011); Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:2200lm; Tension, alimentation c.c.:12V
LAMPE 24V 250W GX5.4; Tension, alimentation:24V; Lamp Base Type:GX5,3; Puissance:250W; Longueur:45mm; Diamètre, réflecteur:50mm; SVHC:No SVHC (20-Jun-2011); Diamètre, extérieur:50mm; Tension, alimentation c.c.:24V
LAMPE 230V 500W GY9.6; Tension, alimentation:230V; Lamp Base Type:GY9,5; Puissance:500W; Température, couleur:3200K; SVHC:No SVHC (20-Jun-2011); Tension c.a.:230V
LAMPE T8 70W 1800MM 4000K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:70W; Flux lumineux:6200lm; Longueur:1.8m; Diamètre de l'ampoule:26mm; Température, couleur:4000K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:6200lm; Intensité lumineuse, max..:6200lm; Longueur/hauteur:1800mm; Tension d'alimentation Vac:240V
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:6.3mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:rouge; Diamètre de découpe panneau:6.35mm; Epaisseur, panneau max..:6.35mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:250V
VOYANT NEON ROUGE; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:19mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:130V
SUPPORT DE LAMPE; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Diamètre de découpe panneau:19mm; Diamètre, lentille:17mm; Dimension de la lentille:E10; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:51mm; Matière:Corps en plastique avec lunette d'encadrement chromée; Profondeur, lentille:12mm; Tension c.a.:50V; Type de borne:Cosses 6.35mm
LAMPE DE SIGNALISATION; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:rouge; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:40mm; Tension d'alimentation Vac:250V
SUPPORT DE LAMPE; Taille de lampe:E5/8 or S6/8; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:Bleu; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Dimension de la lentille:E5/8 or S6/8; Epaisseur, panneau max..:9.6mm; Longueur/hauteur:30.5mm; Matière, lentille:Polycarbonate; Profondeur, lentille:9.5mm; Tension c.a.:50V
SUPPORT DE LAMPE; Taille de lampe:E5/8 or S6/8; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:Clair; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Dimension de la lentille:E5/8 or S6/8; Epaisseur, panneau max..:9.6mm; Longueur/hauteur:30.5mm; Matière, lentille:Polycarbonate; Profondeur, lentille:9.5mm; Tension c.a.:50V
VOYANT NEON ROUGE; Taille de lampe:7.6mm; Tension, alimentation:130V; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; Diamètre de découpe panneau:6.35mm; Dimension de la lentille:7.6mm; Epaisseur, panneau max..:6.35mm; Longueur/hauteur:14.5mm; Tension d'alimentation Vac:130V
SUPPORT DE LAMPE; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:Ambre; Diamètre de découpe panneau:19mm; Diamètre, lentille:17mm; Dimension de la lentille:E10; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:54.8mm; Matière:Corps en plastique avec lunette d'encadrement chromé; Profondeur, lentille:16mm; Tension c.a.:50V; Type de borne:Cosses 6.35mm
SUPPORT DE LAMPE; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; Diamètre de découpe panneau:19mm; Diamètre, lentille:17mm; Dimension de la lentille:E10; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:54.8mm; Matière:Corps en plastique avec lunette d'encadrement chromée; Profondeur, lentille:16mm; Tension c.a.:50V; Type de borne:Cosses 6.35mm
SUPPORT DE LAMPE; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:Ambre; Diamètre de découpe panneau:19mm; Diamètre, lentille:17mm; Dimension de la lentille:E10; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:51mm; Matière:Corps en plastique avec lunette d'encadrement chromée; Profondeur, lentille:12mm; Tension c.a.:50V; Type de borne:Cosses 6.35mm
SUPPORT DE LAMPE; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; Diamètre de découpe panneau:19mm; Diamètre, lentille:17mm; Dimension de la lentille:E10; Epaisseur, panneau max..:6.3mm; Longueur/hauteur:51mm; Matière:Corps en plastique avec lunette d'encadrement chromé; Profondeur, lentille:12mm; Tension c.a.:50V; Type de borne:Cosses 6.35mm
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:2 broches; Couleur:Rouge; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge / Noir; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.75mm; Tension d'alimentation Vac:250V; Type de terminaison:Faston Tab
SUPPORT MAGNETIQUE POUR PROJECTEUR
AMPOULE ECONOMIE D'ENERGIE 11W ES; Tension, alimentation:230V; Lamp Base Type:ES; Puissance:11W; Flux lumineux:600lm; Diamètre de l'ampoule:48mm; Température, couleur:6400K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:48mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h
AMPOULE ECONOMIE D'ENERGIE 13W GX23; Tension, alimentation:230V; Lamp Base Type:GX23; Puissance:13W; Flux lumineux:600lm; Température, couleur:6400K; SVHC:No SVHC (19-Dec-2011); Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h
PORTE LAMPE BLEU IP67; Taille de lampe:14.7mm; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Coating:Lunette de chrome; Couleur:Bleu; Diamètre de découpe panneau:12.7mm; Dimension de la lentille:14.7mm; IP / NEMA Rating:IP67
TUBE CIRCULAIRE DAYLIGHT T5 22W; Tension, alimentation:230V; Lamp Base Type:G10q; Puissance:22W; Flux lumineux:1350lm; Diamètre de l'ampoule:16mm; Température, couleur:6400K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h
LED LAMP, 12V, MR16, WHITE, 20 LED; Lamp Base Type:GX5.3 / GU5.3; Couleur de LED:Blanc; Puissance:1.5W; Taille de lampe:50mm; Tension, alimentation:12V; Durée de vie moyenne de la lampe:50000h; Consommation de puissance:1.5W; Couleur:Blanc; Couleur, LED:Blanc; Diamètre, extérieur:50mm; Dimension de la lentille:50mm; Durée de vie:50000h; Longueur/hauteur:40mm; Nombre de LED:20; Tension, Vf max..:12V; Tension, alimentation c.c.:12V; Tension, direct If:12V
LED LAMP, 12V, MR16, WHITE, 20 LED; Lamp Base Type:GX5.3 / GU5.3; Couleur de LED:Blanc; Puissance:1.5W; Taille de lampe:50mm; Tension, alimentation:12V; Durée de vie moyenne de la lampe:50000h; Consommation de puissance:1.5W; Couleur:Blanc; Couleur, LED:Blanc; Diamètre, extérieur:50mm; Dimension de la lentille:50mm; Durée de vie:50000h; Longueur/hauteur:40mm; Nombre de LED:20; Tension, Vf max..:12V; Tension, alimentation c.c.:12V; Tension, direct If:12V
LED LAMP, GU10, WHITE, 18 LED; Lamp Base Type:GU10; Couleur de LED:Blanc; Puissance:1.5W; Taille de lampe:50mm; Tension, alimentation:230V; Durée de vie moyenne de la lampe:50000h; Consommation de puissance:1.5W; Couleur:Blanc; Couleur, LED:Blanc; Diamètre, extérieur:50mm; Dimension de la lentille:50mm; Durée de vie:50000h; Longueur/hauteur:48mm; Nombre de LED:18; Tension, Vf max..:230V; Tension, direct If:230V; Tension d'alimentation Vac:230V
LAMPE P13.5S 7.2V 5.4W; Tension, alimentation:7.2V; Lamp Base Type:B-3 1/2; Taille de lampe:B-3 1/2; Puissance:5.4W; MSCP:7.95; SVHC:No SVHC (19-Dec-2011); Courant:0.75A; Diamètre, extérieur:13.5mm; Dimension de la lentille:B-3 1/2; Emission lumineuse, totale:100lm; Longueur/hauteur:31.8mm; Tension:7.2V
LED T5 WB 24VAC/DC JAUNE; Lamp Base Type:Wedge; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:42mcd; Taille de lampe:5mm; Tension, alimentation:24V; Courant:10mA; SVHC:No SVHC (19-Dec-2011); Couleur:Jaune; Couleur, LED:Jaune; Courant, direct, If:10mA; Diamètre, extérieur:6.1mm; Dimension de la lentille:5mm; Intensité lumineuse typique:42mcd; Longueur d'onde dominante typ.:585nm; Température de fonctionnement:-20°C +60°C; Température de fonctionnement max..:60°C; Tempéra
LAMPE HALOGENE BA9S T10 12V; Tension, alimentation:12V; Puissance:5W; Longueur:30mm; SVHC:No SVHC (19-Dec-2011); Courant:0.417A; Tension, alimentation c.c.:12V
LED T1 3/4 MG 48V BLANC; Lamp Base Type:Midget Groove; Couleur de LED:Blanc; Intensité lumineuse:700mcd; Taille de lampe:T-1 3/4; Tension, alimentation:48V; Courant:8mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Couleur, LED:Blanc; Courant, direct, If:8mA; Dimension de la lentille:5; Intensité lumineuse typique:700mcd; Température de fonctionnement:-20°C +60°C; Tension, Vf max..:48V; Tension, direct If:48V
LED E10 T10X25 24V BLANC; Lamp Base Type:E10; Couleur de LED:Blanc; Intensité lumineuse:750mcd; Taille de lampe:T-3 1/4; Tension, alimentation:24V; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc diffus; Couleur, LED:Blanc; Courant, direct, If:15mA; Diamètre, extérieur:10mm; Dimension de la lentille:T-3 1/4; Intensité lumineuse, max..:750mcd; Longueur/hauteur:25mm; Température de fonctionnement max..:-20°C; Température d'utilisation min:+60°C; Tension, direct If:24V; Tolérance, tensio
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:12mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:rouge; Diamètre de découpe panneau:12mm; Diamètre, lentille:13.6mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:40mm; Tension d'alimentation Vac:250V
VOYANT NEON ROUGE; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:13.5mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Diamètre de découpe panneau:13.5mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:37.5mm; Tension d'alimentation Vac:130V
SUPPORT DE LAMPE; Taille de lampe:E5/8 or S6/8; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:Ambre; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Dimension de la lentille:E5/8 or S6/8; Epaisseur, panneau max..:9.6mm; Longueur/hauteur:30.5mm; Matière, lentille:Polycarbonate; Profondeur, lentille:9.5mm; Tension c.a.:50V
SUPPORT DE LAMPE; Taille de lampe:E5/8 or S6/8; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:vert; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Dimension de la lentille:E5/8 or S6/8; Epaisseur, panneau max..:9.6mm; Longueur/hauteur:30.5mm; Matière, lentille:Polycarbonate; Profondeur, lentille:9.1mm; Tension c.a.:50V
SUPPORT DE LAMPE; Taille de lampe:E5/8 or S6/8; Tension, alimentation:50V; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Dimension de la lentille:E5/8 or S6/8; Epaisseur, panneau max..:9.6mm; Longueur/hauteur:30.5mm; Matière, lentille:Polycarbonate; Profondeur, lentille:9.5mm; Tension c.a.:50V
LED MID-GRV 24V BLANC CHAUD; Lamp Base Type:Midget Groove, S5,7s; Couleur de LED:Blanc chaud; Intensité lumineuse:9200mcd; Puissance:500mW; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc ton chaud; Couleur, lentilles:Water Clear; Courant, fonctionnement c.c.:20mA; Diamètre, extérieur:5.6mm; Diamètre, lentille:4.9mm; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:9200mcd; Largeur (externe):25mm
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:rouge; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:15.9mm; Epaisseur, panneau max..:1.5mm; Epaisseur, panneau min.:0.8mm; Longueur/hauteur:35mm; Tension d'alimentation Vac:250V
AMPOULE DICHROIQUE 35W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:35W; Longueur:29mm; Diamètre, réflecteur:34.7mm; Température, couleur:3100K; SVHC:No SVHC (19-Dec-2011); Angle:38°; Couleur:Cool White; Diamètre, extérieur:51mm; Intensité lumineuse, max..:1100cd
AMPOULE DICHROIQUE 50W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:50W; Longueur:44.5mm; Diamètre, réflecteur:51mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Angle:38°; Couleur:Cool White; Diamètre, extérieur:51mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension c.a.:12V; Tension d'alimentation Vac:12V
LAMPE DULUX S 7W FROIDE; Tension, alimentation:47V; Lamp Base Type:2 broches; Puissance:7W; Flux lumineux:400lm; Longueur:137mm; Diamètre de l'ampoule:19.5mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:19.5mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Emission lumineuse, totale:400lm; Flux lumineux typique:400lm; Largeur (externe):34mm; Longueur/hauteur:138mm; Profondeur:19.5mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. m
LAMPE DULUX D 10W CHAUD; Tension, alimentation:64V; Lamp Base Type:2 broches; Puissance:10W; Flux lumineux:600lm; Longueur:110mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Emission lumineuse, totale:600lm; Flux lumineux typique:600lm; Largeur (externe):34mm; Longueur/hauteur:118mm; Profondeur:34mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
TUBE FLUO 600MM BLANC CHAUD T8; Lamp Base Type:T8; Puissance:18W; Flux lumineux:1350lm; Longueur:600mm; Diamètre de l'ampoule:26mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc chaud; Diamètre, extérieur:26mm; Longueur/hauteur:600mm; Profondeur:26mm
AMPOULE DULUX EL7W B22; Tension, alimentation:240V; Lamp Base Type:B22; Puissance:7W; Flux lumineux:400lm; Longueur:129mm; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:45mm; Durée de vie:15000h; Durée de vie moyenne de la lampe:15000h; Flux lumineux typique:400lm; Intensité lumineuse, max..:400cd; Longueur/hauteur:129mm; Puissance GLS équivalente:35W; Tension d'alimentation Vac:240V
LAMPE DULUX L 18W INTERNA; Tension, alimentation:58V; Puissance:18W; Flux lumineux:1150lm; Longueur:217mm; Diamètre de l'ampoule:17.5mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Couleur:Interna; Diamètre, extérieur:17.5mm; Flux lumineux typique:1200lm; Longueur/hauteur:217mm; Nombre de broches:4
LAMPE DULUX L 24W INTERNA; Tension, alimentation:87V; Puissance:24W; Flux lumineux:1750lm; Longueur:317mm; Diamètre de l'ampoule:17.5mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Couleur:Interna; Diamètre, extérieur:17.5mm; Flux lumineux typique:1800lm; Longueur/hauteur:317mm; Nombre de broches:4
LAMPE DULUX L 55W BLANC FROID; Tension, alimentation:101V; Puissance:55W; Flux lumineux:4800lm; Longueur:533mm; Diamètre de l'ampoule:17.5mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:17.5mm; Flux lumineux typique:4800lm; Longueur/hauteur:533mm; Nombre de broches:4
LAMPE DULUX DE HF 18W BLANC FROID; Tension, alimentation:80V; Lamp Base Type:G24q; Puissance:18W; Flux lumineux:1150lm; Longueur:146mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:1200lm; Longueur/hauteur:146mm; Nombre de broches:4
LAMPE DULUX S/E 7W INTERNA; Tension, alimentation:230V; Lamp Base Type:2G7; Puissance:6.5W; Flux lumineux:400lm; Longueur:114mm; Diamètre de l'ampoule:21mm; Température, couleur:5000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:21mm
AMPOULE DECOSTAR 10W LARGE FAISCEAU; Tension, alimentation:12V; Lamp Base Type:GU4; Puissance:10W; Longueur:37mm; Diamètre, réflecteur:35mm; Température, couleur:3100K; SVHC:No SVHC (19-Dec-2011); Angle:38°; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Intensité lumineuse, max..:300cd; Tension, alimentation c.c.:12V; Type de faisceau:Wide Flood
LAMPE SODIUM TUBULAIRE 250W; Longueur:257mm; Température, couleur:21000K; Courant:3A; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:46mm; Intensité lumineuse, max..:27000lm; Lamp Base Type:E40; Longueur/hauteur:257mm; Puissance:250W; Tension, alimentation:240V
LAMPE SODIUM SON+ TUBULAIRE 70W; Longueur:156mm; Température, couleur:2000K; Courant:980mA; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:37mm; Intensité lumineuse, max..:6500lm
LAMPE A DECHARGE NEUTRE 70W; Longueur:114.2mm; Diamètre de l'ampoule:20mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Neutre; Intensité lumineuse:5.5cd; Lamp Base Type:RX7; Puissance:70W; Tension, alimentation:85V
AMPOULE POUR SPOT 51S 35W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:35W; Longueur:45mm; Diamètre, réflecteur:50mm; SVHC:No SVHC (19-Dec-2011); Divergence du faisceau:10°
AMPOULE POUR SPOT 51S 50W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:50W; Longueur:45mm; Diamètre, réflecteur:51mm; SVHC:No SVHC (19-Dec-2011); Divergence du faisceau:38°; Intensité lumineuse, max..:1450cd
VOYANT NEON ROUGE; Tension, alimentation:230V; Lamp Base Type:2 broches; Couleur:Rouge; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge / Noir; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.75mm; Type de terminaison:Faston Tab
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Rouge; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Epaisseur, panneau max..:3mm; Epaisseur, panneau min.:0.75mm; Tension d'alimentation Vac:250V
LAMPE DULUX S 11W FROIDE; Tension, alimentation:91V; Lamp Base Type:2 broches; Puissance:11W; Flux lumineux:900lm; Longueur:237mm; Diamètre de l'ampoule:19.5mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:19.5mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Emission lumineuse, totale:900lm; Flux lumineux typique:900lm; Largeur (externe):34mm; Longueur/hauteur:238mm; Profondeur:19.5mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a.
TUBE FLUO 600MM BLANC FROID T8; Lamp Base Type:T8; Puissance:18W; Flux lumineux:1350lm; Longueur:600mm; Diamètre de l'ampoule:26mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Diamètre, extérieur:26mm; Longueur/hauteur:600mm; Profondeur:26mm
TUBE FLUO 1800MM BLANC STANDARD T8; Lamp Base Type:T8; Puissance:70W; Flux lumineux:6550lm; Longueur:1.8m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Diamètre, extérieur:26mm; Longueur/hauteur:1800mm; Profondeur:26mm
LAMPE DULUX L 24W BLANC FROID; Tension, alimentation:87V; Puissance:24W; Flux lumineux:1750lm; Longueur:317mm; Diamètre de l'ampoule:17.5mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:17.5mm; Flux lumineux typique:1800lm; Longueur/hauteur:317mm; Nombre de broches:4
LAMPE DULUX L 40W BLANC FROID; Tension, alimentation:126V; Puissance:40W; Flux lumineux:3500lm; Longueur:533mm; Diamètre de l'ampoule:17.5mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:17.5mm; Flux lumineux typique:3500lm; Longueur/hauteur:533mm; Nombre de broches:4
LAMPE DULUX DE HF 10W BLANC FROID; Tension, alimentation:51V; Lamp Base Type:G24q; Puissance:10W; Flux lumineux:600lm; Longueur:103mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:600lm; Longueur/hauteur:103mm; Nombre de broches:4
LAMPE DULUX DE HF 13W BLANC FROID; Tension, alimentation:77V; Lamp Base Type:G24q; Puissance:13W; Flux lumineux:850lm; Longueur:131mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:900lm; Longueur/hauteur:131mm; Nombre de broches:4
LAMPE DULUX DE HF 26W BLANC FROID; Tension, alimentation:80V; Lamp Base Type:G24q; Puissance:26W; Flux lumineux:1750lm; Longueur:165mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:1800lm; Longueur/hauteur:165mm; Nombre de broches:4
LAMPE DULUX T/E 26W CW; Tension, alimentation:80V; Puissance:26W; Flux lumineux:1750lm; Longueur:131mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:1800lm; Longueur/hauteur:131mm
LAMPE DULUX T/E 42W CW; Tension, alimentation:230V; Puissance:42W; Flux lumineux:3200lm; Longueur:168mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:3200lm; Longueur/hauteur:168mm
AMPOULE DECOSTAR 20W SPOT; Tension, alimentation:12V; Lamp Base Type:GU4; Puissance:20W; Longueur:37mm; Diamètre, réflecteur:35mm; Température, couleur:3100K; SVHC:No SVHC (19-Dec-2011); Angle:10°; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Intensité lumineuse, max..:5000cd; Tension, alimentation c.c.:12V; Type de faisceau:Spot
AMPOULE DECOSTAR 20W LARGE FAISCEAU; Tension, alimentation:12V; Lamp Base Type:GU4; Puissance:20W; Longueur:37mm; Diamètre, réflecteur:35mm; Température, couleur:3100K; SVHC:No SVHC (19-Dec-2011); Angle:38°; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Intensité lumineuse, max..:680cd; Tension, alimentation c.c.:12V; Type de faisceau:Wide Flood
AMPOULE DECOSTAR 35W SPOT; Tension, alimentation:12V; Lamp Base Type:GU4; Puissance:35W; Longueur:37mm; Diamètre, réflecteur:35mm; Température, couleur:3100K; SVHC:No SVHC (19-Dec-2011); Angle:10°; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Intensité lumineuse, max..:6500cd; Tension, alimentation c.c.:12V; Type de faisceau:Spot
AMPOULE DECOSTAR 35W LARGE FAISCEAU; Tension, alimentation:12V; Lamp Base Type:GU4; Puissance:35W; Longueur:37mm; Diamètre, réflecteur:35mm; Température, couleur:3100K; SVHC:No SVHC (19-Dec-2011); Angle:38°; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Intensité lumineuse, max..:1100cd; Tension, alimentation c.c.:12V; Type de faisceau:Wide Flood
LAMPE SODIUM ELLIPSOIDALE 70W; Longueur:156mm; Température, couleur:2000K; Courant:980mA; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:70mm; Intensité lumineuse, max..:5600lm; Lamp Base Type:E27; Longueur/hauteur:156mm; Puissance:70W; Tension, alimentation:240V
LAMPE DULUX EL ECO 16W BC; Tension, alimentation:240V; Puissance:16W; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:52mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Flux lumineux typique:600lm; Longueur/hauteur:140mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
AMPOULE POUR SPOT 51S 20W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:20W; Longueur:45mm; Diamètre, réflecteur:51mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Divergence du faisceau:10°; Intensité lumineuse, max..:3000cd
AMPOULE POUR SPOT 51S 35W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:35W; Longueur:45mm; Diamètre, réflecteur:51mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Divergence du faisceau:36°; Intensité lumineuse, max..:6000cd
AMPOULE POUR SPOT 51S 50W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:50W; Longueur:45mm; Diamètre, réflecteur:51mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Divergence du faisceau:10°; Intensité lumineuse, max..:7800cd
LAMPE LED 28V JAUNE; Lamp Base Type:Midget Flange; Couleur de LED:Jaune; Longueur d'onde typ.:592nm; Intensité lumineuse:775mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Jaune; Couleur, LED:Jaune; Courant, direct, If:10mA; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:775mcd; Température de fonctionnement:-40°C +80°C; Tension, Vf max..:28VDC; Tension, direct If:28V
LAMPE FLUO 16W 2D; Tension, alimentation:240V; Lamp Base Type:2 broches 2D; Puissance:16W; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011)
AMPOULE DICHROIQUE 50W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:50W; Longueur:44.5mm; Diamètre, réflecteur:51mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Angle:24°; Couleur:Cool White; Diamètre, extérieur:51mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension c.a.:12V; Tension d'alimentation Vac:12V
AMPOULE HALOPIN TRANSPRTE 25W 240V HP25C; Tension, alimentation:240V; Lamp Base Type:G9; Puissance:25W; Longueur:43mm; Température, couleur:2800K; SVHC:No SVHC (19-Dec-2011); Intensité lumineuse, max..:260lm
AMPOULE HALOPIN TRANSPRTE 40W 240V HP40C; Tension, alimentation:240V; Lamp Base Type:G9; Puissance:40W; Longueur:43mm; Température, couleur:2800K; SVHC:No SVHC (19-Dec-2011); Intensité lumineuse, max..:490lm
TUBE FLUO 1200MM BLANC STANDARD T8; Lamp Base Type:T8; Puissance:36W; Flux lumineux:3350lm; Longueur:1.2m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Flux lumineux typique:3350lm; Longueur/hauteur:1200mm; Profondeur:26mm
TUBE FLUO 1500MM BLANC STANDARD T8; Lamp Base Type:T8; Puissance:58W; Flux lumineux:5200lm; Longueur:1.5m; Diamètre de l'ampoule:26mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Flux lumineux typique:5200lm; Longueur/hauteur:1500mm; Profondeur:26mm
LAMPE SODIUM TUBULAIRE 150W; Longueur:211mm; Température, couleur:2000K; Courant:1.8A; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:46mm; Intensité lumineuse, max..:14500lm
LAMPE SODIUM TUBULAIRE 400W; Longueur:285mm; Température, couleur:2000K; Courant:4.4A; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:46mm; Intensité lumineuse, max..:48000lm; Lamp Base Type:E40; Longueur/hauteur:285mm; Puissance:400W; Tension, alimentation:240V
AMPOULE POUR SPOT 51S 50W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:50W; Longueur:45mm; Diamètre, réflecteur:51mm; SVHC:No SVHC (19-Dec-2011); Divergence du faisceau:24°; Intensité lumineuse, max..:4000cd
LED BA9 28V BLANC CHAUD; Lamp Base Type:BA9; Couleur de LED:Blanc chaud; Intensité lumineuse:9200mcd; Taille de lampe:T-3 1/4; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc ton chaud; Couleur, lentilles:Water Clear; Courant, fonctionnement c.c.:20mA; Diamètre, lentille:4.9mm; Dimension de la lentille:T-3 1/4; Intensité lumineuse typique:9200mcd; Largeur (externe):26mm; Longueur/hauteur:9.2mm; Température de fonctionne
VOYANT NEON ROUGE; Tension, alimentation:130V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:12.7mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:rouge; Diamètre de découpe panneau:12.7mm; Diamètre, lentille:14mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:40mm; Tension d'alimentation Vac:130V
LAMPE LED 14V ROUGE; Lamp Base Type:Midget Flange; Couleur de LED:Rouge; Longueur d'onde typ.:639nm; Intensité lumineuse:775mcd; Taille de lampe:T-1 3/4; Tension, alimentation:14V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Rouge; Couleur, LED:Rouge; Courant, direct, If:10mA; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:775mcd; Température de fonctionnement:-40°C +80°C; Tension, Vf max..:14VDC; Tension, direct If:14V
LAMPE LED 28V VERT; Lamp Base Type:Midget Groove; Couleur de LED:Vert; Longueur d'onde typ.:520nm; Intensité lumineuse:600mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Couleur:Vert; Couleur, LED:Vert; Courant, direct, If:10mA; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:600mcd; Température de fonctionnement:-40°C +80°C; Tension, Vf max..:28VDC; Tension, direct If:28V
STRIPLIGHT, LED, 300MM COLD CLEAR; Light Source:LED; Longueur:320mm; Largeur:47mm; Profondeur:22mm; Couleur:Transparent; Couleur:Blanc froid; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):47mm; Longueur/hauteur:300mm; Profondeur:22mm; Puissance:3.5VA; Taille de lampe:T-4; Température de couleur proximale:7500K; Tension, alimentation:230V
STRIPLIGHT, LED, 400MM PURE PEARL; Light Source:40 x LED; Longueur:420mm; Largeur:20mm; Profondeur:44mm; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:420mm; Profondeur:44mm; Puissance:6VA; Taille de lampe:T-4; Température de couleur proximale:5000K; Tension, alimentation:230V
STRIPLIGHT, LED, 500MM PURE PEARL; Light Source:52 x LED; Longueur:520mm; Largeur:20mm; Profondeur:44mm; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:520mm; Profondeur:44mm; Puissance:12VA; Taille de lampe:T-4; Température de couleur proximale:5000K; Tension, alimentation:230V
STRIPLIGHT, LED, 700MM COLD CLEAR; Light Source:76 x LED; Longueur:720mm; Largeur:20mm; Profondeur:44mm; Couleur:Transparent; Couleur:Blanc froid; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:720mm; Profondeur:44mm; Puissance:12VA; Taille de lampe:T-4; Température de couleur proximale:7500K; Tension, alimentation:230V
STRIPLIGHT, LED, 800MM COLD PEARL; Light Source:88 x LED; Longueur:820mm; Largeur:20mm; Profondeur:44mm; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:820mm; Profondeur:44mm; Puissance:12VA; Taille de lampe:T-4; Température de couleur proximale:7500K; Tension, alimentation:230V
STRIPLIGHT, LED, ULP 400MM PUR PRL; Light Source:44 x LED; Longueur:420mm; Largeur:16mm; Profondeur:16mm; Couleur de LED:Blanc; Courant:400mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:420mm; Profondeur:16mm; Puissance:4.8VA; Température de couleur proximale:5000K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 600MM CLD CLR; Light Source:68 x LED; Longueur:620mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc froid; Couleur de LED:Blanc; Courant:610mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:620mm; Profondeur:16mm; Puissance:7.3VA; Température de couleur proximale:7500K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 800MM PUR CLR; Light Source:92 x LED; Longueur:820mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc pur; Couleur de LED:Blanc; Courant:830mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:820mm; Profondeur:16mm; Puissance:9.9VA; Température de couleur proximale:5000K; Tension, alimentation:12V
LED T5.5 48V BLANC; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Blanc; Intensité lumineuse:850mcd; Taille de lampe:6mm; Tension, alimentation:48V; Courant:7mA; Angle du faisceau:110°; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Courant, direct, If:7mA; Dimension de la lentille:6mm; Tension, direct If:48V
AMPOULE DICHROIQUE 20W; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:20W; Longueur:44.5mm; Diamètre, réflecteur:51mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Angle:38°; Couleur:Cool White; Diamètre, extérieur:51mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension c.a.:12V; Tension d'alimentation Vac:12V
LAMPE DULUX S 5W FROIDE; Tension, alimentation:35V; Lamp Base Type:2 broches; Puissance:5W; Flux lumineux:250lm; Longueur:108mm; Diamètre de l'ampoule:19.5mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:19.5mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Emission lumineuse, totale:250lm; Flux lumineux typique:250lm; Largeur (externe):34mm; Longueur/hauteur:108mm; Profondeur:19.5mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. m
LAMPE DULUX S 9W FROIDE; Tension, alimentation:60V; Lamp Base Type:2 broches; Puissance:9W; Flux lumineux:600lm; Longueur:167mm; Diamètre de l'ampoule:19.5mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:19.5mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Emission lumineuse, totale:600lm; Flux lumineux typique:600lm; Largeur (externe):34mm; Longueur/hauteur:168mm; Profondeur:19.5mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. m
LAMPE DULUX D 13W INTERNA; Tension, alimentation:220V; Lamp Base Type:G24d-1; Puissance:13W; Flux lumineux:900lm; Longueur:138mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Emission lumineuse, totale:900lm; Largeur (externe):34mm; Longueur/hauteur:153mm; Profondeur:34mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
TUBE FLUO 600MM BLANC STANDARD T8; Lamp Base Type:T8; Puissance:18W; Flux lumineux:1350lm; Longueur:600mm; Diamètre de l'ampoule:26mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Flux lumineux typique:1350lm; Longueur/hauteur:600mm; Profondeur:26mm
TUBE FLUO 1200MM BLANC CHAUD T8; Lamp Base Type:T8; Puissance:36W; Flux lumineux:3350lm; Longueur:1.2m; Diamètre de l'ampoule:26mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc chaud; Diamètre, extérieur:26mm; Longueur/hauteur:1200mm; Profondeur:26mm
TUBE FLUO 1500MM BLANC CHAUD T8; Lamp Base Type:T8; Puissance:58W; Flux lumineux:5200lm; Longueur:1.5m; Diamètre de l'ampoule:26mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc chaud; Diamètre, extérieur:26mm; Longueur/hauteur:1500mm; Profondeur:26mm
TUBE FLUO 1500MM BLANC FROID T8; Lamp Base Type:T8; Puissance:58W; Flux lumineux:5200lm; Longueur:1.5m; Diamètre de l'ampoule:26mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Diamètre, extérieur:26mm; Longueur/hauteur:1500mm; Profondeur:26mm
LAMPE DULUX F 24W; Tension, alimentation:87V; Lamp Base Type:2G10; Puissance:24W; Flux lumineux:1650lm; Longueur:165mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:1700lm; Longueur/hauteur:165mm; Nombre de broches:4
LAMPE DULUX F 36W; Tension, alimentation:106V; Lamp Base Type:2G10; Puissance:36W; Flux lumineux:2800lm; Longueur:217mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Flux lumineux typique:2800lm; Longueur/hauteur:217mm
LAMPE DULUX L 36W CW; Tension, alimentation:106V; Puissance:36W; Flux lumineux:2900lm; Longueur:411mm; Diamètre de l'ampoule:17.5mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:17.5mm; Flux lumineux typique:2900lm; Longueur/hauteur:411mm; Nombre de broches:4
LAMPE DULUX L 36W INTERNA; Tension, alimentation:106V; Puissance:36W; Flux lumineux:2900lm; Longueur:411mm; Diamètre de l'ampoule:17.5mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Couleur:Interna; Diamètre, extérieur:17.5mm; Flux lumineux typique:2900lm; Longueur/hauteur:411mm; Nombre de broches:4
LAMPE DULUX S/E 7W BLANC FROID; Tension, alimentation:37V; Lamp Base Type:2G7; Puissance:7W; Flux lumineux:400lm; Longueur:114mm; Diamètre de l'ampoule:21mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:21mm; Flux lumineux typique:400lm; Longueur/hauteur:114mm
LAMPE DULUX S/E 9W BLANC FROID; Tension, alimentation:230V; Lamp Base Type:2G7; Puissance:8W; Flux lumineux:600lm; Longueur:144mm; Diamètre de l'ampoule:21mm; Température, couleur:5000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:21mm
LAMPE DULUX S/E 11W BLANC FROID; Tension, alimentation:75V; Lamp Base Type:2G7; Puissance:11W; Flux lumineux:850lm; Longueur:214mm; Diamètre de l'ampoule:21mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:21mm; Flux lumineux typique:900lm; Longueur/hauteur:214mm
LAMPE DULUX S/E 11W INTERNA; Tension, alimentation:75V; Lamp Base Type:2G7; Puissance:11W; Flux lumineux:850lm; Longueur:214mm; Diamètre de l'ampoule:21mm; Température, couleur:5000K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:21mm; Flux lumineux typique:900lm; Longueur/hauteur:214mm
LAMPE DULUX T 13W BLANC FROID; Tension, alimentation:230V; Lamp Base Type:2 broches; Puissance:13W; Flux lumineux:900lm; Longueur:113mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Longueur/hauteur:113mm
LAMPE DULUX T 18W BLANC FROID; Tension, alimentation:230V; Lamp Base Type:2 broches; Puissance:18W; Flux lumineux:1200lm; Longueur:123mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Longueur/hauteur:123mm
LAMPE DULUX T 26W BLANC FROID; Tension, alimentation:80V; Lamp Base Type:2 broches; Puissance:26W; Flux lumineux:1800lm; Longueur:138mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:1800lm; Longueur/hauteur:138mm
LAMPE DULUX T/E 26W I; Tension, alimentation:80V; Puissance:26W; Flux lumineux:1750lm; Longueur:131mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Couleur:Interna; Flux lumineux typique:1800lm; Longueur/hauteur:131mm
AMPOULE HALOPAR16 240V 50W ALUMINISE; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:50W; Longueur:55mm; Diamètre, réflecteur:50.7mm; Température, couleur:2800K; SVHC:No SVHC (19-Dec-2011); Intensité lumineuse, max..:900cd
LAMPE SODIUM ELLIPSOIDALE 400W; Longueur:290mm; Température, couleur:2000K; Courant:4.45A; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:120mm; Intensité lumineuse, max..:47000lm
LAMPE SODIUM ELLIPSOIDALE 400W; Température, couleur:2000K; Courant:4.45A; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:120mm; Intensité lumineuse, max..:47000lm; Lamp Base Type:E40; Longueur/hauteur:290mm; Puissance:400W; Tension, alimentation:240V
LAMPE A DECHARGE BLANC SOLEIL 250W; Longueur:225mm; Diamètre de l'ampoule:46mm; Température, couleur:5300K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc soleil; Intensité lumineuse:20cd; Lamp Base Type:ES(E40); Puissance:250W; Tension, alimentation:100V
LAMPE A DECHARGE BLANC SOLEIL 400W; Longueur:275mm; Diamètre de l'ampoule:46mm; Température, couleur:3700K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc soleil; Lamp Base Type:ES(E40); Puissance:400W; Tension, alimentation:125V
LAMPE DULUX EL ECO 12W BC; Tension, alimentation:240V; Puissance:12W; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:45mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Flux lumineux typique:400lm; Longueur/hauteur:138mm; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
AMPOULE POUR SPOT 51S 20W SPOT; Tension, alimentation:12V; Lamp Base Type:GU5,3; Puissance:20W; Longueur:45mm; Diamètre, réflecteur:51mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Divergence du faisceau:10°; Intensité lumineuse, max..:3000cd
AMPOULE HQI-T NSI POWERSTAR 400W N; Longueur:248mm; Diamètre de l'ampoule:57mm; Température, couleur:3700K; SVHC:No SVHC (19-Dec-2011); Couleur:Transparent; Lamp Base Type:E40; Puissance:400W
AMPOULE SON-T PLUS 4Y 250W E27/E27; Longueur:257mm; Diamètre de l'ampoule:46mm; Température, couleur:2000K; SVHC:No SVHC (19-Dec-2011); Couleur:Transparent; Lamp Base Type:E40; Puissance:250W
AMPOULE. GU10. HALOGENEE. 20W 230V; Tension, alimentation:230V; Lamp Base Type:GU10; Puissance:20W; Longueur:50mm; Diamètre, réflecteur:50mm; Température, couleur:2800K; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:230V
AMPOULE. GU10. HALOGENEE. 50W 230V; Tension, alimentation:230V; Lamp Base Type:GU10; Puissance:50W; Longueur:50mm; Diamètre, réflecteur:50mm; Température, couleur:2800K; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:230V
AMPOULE MR16 HALOGENE BASSE TENSION 35W; Tension, alimentation:12V; Lamp Base Type:GX5,3 / GU5,3; Puissance:35W; Diamètre, réflecteur:50mm; Température, couleur:2800K; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension, alimentation c.c.:12V
AMPOULE. GU10. ECONOMIQUE 9W; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:9W; Flux lumineux:432lm; Longueur:73mm; Diamètre de l'ampoule:50mm; Température, couleur:2700K; Diamètre, extérieur:50mm; Durée de vie:8000h; Puissance GLS équivalente:45W
TUBE DE LED BLANC CHAUD 61CM; Couleur de LED:Blanc chaud; Température de couleur proximale:3500K; Puissance:5.76W; Tension, alimentation:24V; Courant:240mA; Angle du faisceau:80°; Durée de vie moyenne de la lampe:50000h; Angle:80°; Consommation de puissance:2.76W; Couleur:Chaud; Courant, direct, If:240mA; Largeur (externe):33mm; Longueur:2ft; Longueur/hauteur:27mm; Tension, direct If:24V
LAMPE HALOGENE; Tension, alimentation:21V; Lamp Base Type:GX5,3; Puissance:150W; Longueur:44.5mm; Diamètre, réflecteur:51mm; Intensité lumineuse, max..:80mcd
STRIPLIGHT, LED, 300MM PURE CLEAR; Light Source:LED; Longueur:320mm; Largeur:47mm; Profondeur:22mm; Couleur:Transparent; Couleur:Blanc pur; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):47mm; Longueur/hauteur:320mm; Profondeur:22mm; Puissance:3.5VA; Taille de lampe:T-4; Température de couleur proximale:5000K; Tension, alimentation:230V
STRIPLIGHT, LED, 300MM PURE PEARL; Light Source:LED; Longueur:320mm; Largeur:47mm; Profondeur:22mm; Couleur:Perle; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):47mm; Longueur/hauteur:300mm; Profondeur:22mm; Puissance:3.5VA; Taille de lampe:T-4; Température de couleur proximale:5000K; Tension, alimentation:220V
STRIPLIGHT, LED, 500MM COLD CLEAR; Light Source:52 x LED; Longueur:520mm; Largeur:20mm; Profondeur:44mm; Couleur:Transparent; Couleur:Blanc froid; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:520mm; Profondeur:44mm; Puissance:12VA; Taille de lampe:T-4; Température de couleur proximale:7500K; Tension, alimentation:230V
STRIPLIGHT, LED, 600MM PURE PEARL; Light Source:64 x LED; Longueur:620mm; Largeur:20mm; Profondeur:44mm; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:620mm; Profondeur:44mm; Puissance:12VA; Taille de lampe:T-4; Température de couleur proximale:5000K; Tension, alimentation:230V
STRIPLIGHT, LED, 800MM COLD CLEAR; Light Source:88 x LED; Longueur:820mm; Largeur:20mm; Profondeur:44mm; Couleur:Transparent; Couleur:Blanc froid; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:820mm; Profondeur:44mm; Puissance:12VA; Taille de lampe:T-4; Température de couleur proximale:7500K; Tension, alimentation:230V
STRIPLIGHT, LED, ULP 300MM CLD PRL; Light Source:32 x LED; Longueur:320mm; Largeur:16mm; Profondeur:16mm; Couleur de LED:Blanc; Courant:290mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:320mm; Profondeur:16mm; Puissance:3.5VA; Température de couleur proximale:7500K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 300MM PUR CLR; Light Source:32 x LED; Longueur:320mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc pur; Couleur de LED:Blanc; Courant:290mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:320mm; Profondeur:16mm; Puissance:3.5VA; Température de couleur proximale:5000K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 800MM CLD CLR; Light Source:92 x LED; Longueur:820mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc froid; Couleur de LED:Blanc; Courant:830mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:820mm; Profondeur:16mm; Puissance:9.9VA; Température de couleur proximale:7500K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 800MM PUR PRL; Light Source:92 x LED; Longueur:820mm; Largeur:16mm; Profondeur:16mm; Couleur de LED:Blanc; Courant:830mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:820mm; Profondeur:16mm; Puissance:9.9VA; Température de couleur proximale:5000K; Tension, alimentation:12V
AMPOULE SON-T PLUS 4Y 100W E27/E27; Longueur:210mm; Diamètre de l'ampoule:46mm; Température, couleur:2000K; SVHC:No SVHC (19-Dec-2011); Couleur:Transparent; Lamp Base Type:E40; Puissance:100W
AMPOULE. REFLECTEUR R63. 5W. B22; Tension, alimentation:240V; Lamp Base Type:B22; Puissance:5W; Longueur:131mm; Diamètre de l'ampoule:65mm; Diamètre, extérieur:65mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:131mm
TUBE DE LED BLANC CHAUD 30.5CM; Couleur de LED:Blanc chaud; Température de couleur proximale:3500K; Puissance:2.88W; Tension, alimentation:24V; Courant:120mA; Angle du faisceau:80°; Durée de vie moyenne de la lampe:50000h; Angle:80°; Consommation de puissance:2.88W; Couleur:Chaud; Courant, direct, If:120mA; Largeur (externe):33mm; Longueur:1ft; Longueur/hauteur:27mm; Tension, direct If:24V
STRIPLIGHT, LED, 400MM PURE CLEAR; Light Source:40 x LED; Longueur:420mm; Largeur:20mm; Profondeur:44mm; Couleur:Transparent; Couleur:Blanc pur; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:420mm; Profondeur:44mm; Puissance:6VA; Taille de lampe:T-4; Température de couleur proximale:5000K; Tension, alimentation:230V
STRIPLIGHT, LED, ULP 300MM CLD CLR; Light Source:32 x LED; Longueur:320mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc froid; Couleur de LED:Blanc; Courant:290mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:320mm; Profondeur:16mm; Puissance:3.5VA; Température de couleur proximale:7500K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 300MM PUR PRL; Light Source:32 x LED; Longueur:320mm; Largeur:16mm; Profondeur:16mm; Couleur de LED:Blanc; Courant:290mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:320mm; Profondeur:16mm; Puissance:3.5VA; Température de couleur proximale:5000K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 400MM CLD CLR; Light Source:44 x LED; Longueur:420mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc froid; Couleur de LED:Blanc; Courant:400mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:420mm; Profondeur:16mm; Puissance:4.8VA; Température de couleur proximale:7500K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 400MM PUR CLR; Light Source:44 x LED; Longueur:420mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc pur; Couleur de LED:Blanc; Courant:400mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:420mm; Profondeur:16mm; Puissance:4.8VA; Température de couleur proximale:5000K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 700MM PUR CLR; Light Source:80 x LED; Longueur:720mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc pur; Couleur de LED:Blanc; Courant:720mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:720mm; Profondeur:16mm; Puissance:8.6VA; Température de couleur proximale:5000K; Tension, alimentation:12V
AMPOULE HCI-T POWERBALL 70W WDL; Longueur:100mm; Diamètre de l'ampoule:19mm; Température, couleur:3000K; SVHC:No SVHC (19-Dec-2011); Couleur:Warm White; Lamp Base Type:G12; Puissance:72W
AMPOULE. GU10. HALOGENEE. 35W 230V; Tension, alimentation:230V; Lamp Base Type:GU10; Puissance:35W; Longueur:50mm; Diamètre, réflecteur:50mm; Température, couleur:2800K; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:230V
AMPOULE MR16 HALOGENE BASSE TENSION 50W; Tension, alimentation:12V; Lamp Base Type:GX5,3 / GU5,3; Puissance:50W; Diamètre, réflecteur:50mm; Température, couleur:2800K; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension, alimentation c.c.:12V
AMPOULE MR16 HALOGENE BASSE TENSION 50W; Tension, alimentation:12V; Lamp Base Type:GX5,3 / GU5,3; Puissance:50W; Diamètre, réflecteur:50mm; Température, couleur:2800K; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension, alimentation c.c.:12V
AMPOULE. PAR16 E14 JAUNE; Tension, alimentation:240V; Lamp Base Type:E14; Puissance:40W; Diamètre de l'ampoule:50mm; Couleur:Yellow; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Longueur/hauteur:85mm; Taille de lampe:Parabolique, PAR16, 50 mm; Tension:240VAC
AMPOULE. GU10. ECONOMIQUE 11W; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:11W; Flux lumineux:528lm; Longueur:73mm; Diamètre de l'ampoule:50mm; Température, couleur:2700K; Diamètre, extérieur:50mm; Durée de vie:8000h; Puissance GLS équivalente:55W
AMPOULE. BUG. 9W B22; Tension, alimentation:240V; Lamp Base Type:E27; Puissance:9W; Longueur:142mm; Diamètre de l'ampoule:64mm; Diamètre, extérieur:64mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur/hauteur:142mm
LAMPE MES G3.1/2 11MM; Tension, alimentation:3.5V; Lamp Base Type:E10; Puissance:1W; MSCP:0.59; Durée de vie moyenne de la lampe:1000h; SVHC:No SVHC (19-Dec-2011); Courant:0.3A; Diamètre, extérieur:9.5mm; Dimension de la lentille:G3 1/2; Durée de vie:1000h; Emission lumineuse, totale:6lm; Longueur/hauteur:24mm; Tension:3.5V; Tension c.a.:3.5V
TUBE DE LED LUM. DU JOUR 30.5CM; Couleur de LED:Blanc; Température de couleur proximale:6500K; Puissance:2.88W; Tension, alimentation:24V; Courant:120mA; Angle du faisceau:80°; Durée de vie moyenne de la lampe:50000h; Angle:80°; Consommation de puissance:2.88W; Couleur:Lumière du jour; Courant, direct, If:120mA; Largeur (externe):33mm; Longueur:1ft; Longueur/hauteur:27mm; Tension, direct If:24V
TUBE DE LED LUM. DU JOUR 61CM; Couleur de LED:Blanc; Température de couleur proximale:6500K; Puissance:5.76W; Tension, alimentation:24V; Courant:240mA; Angle du faisceau:80°; Durée de vie moyenne de la lampe:50000h; Angle:80°; Consommation de puissance:5.76W; Couleur:Lumière du jour; Courant, direct, If:240mA; Largeur (externe):33mm; Longueur:2ft; Longueur/hauteur:27mm; Tension, direct If:24V
TUBE DE LED LUM. DU JOUR 91.5CM; Couleur de LED:Blanc; Température de couleur proximale:6500K; Puissance:8.64W; Tension, alimentation:24V; Courant:360mA; Angle du faisceau:80°; Durée de vie moyenne de la lampe:50000h; Angle:80°; Consommation de puissance:8.64W; Couleur:Lumière du jour; Courant, direct, If:360mA; Longueur:3ft; Tension, direct If:24V
TUBE DE LED T5 LUM. DU JOUR 61CM; Couleur de LED:Blanc; Température de couleur proximale:6500K; Puissance:5.76W; Taille de lampe:T-5; Tension, alimentation:24V; Courant:240mA; Angle du faisceau:60°; Angle:60°; Consommation de puissance:5.76W; Couleur:Lumière du jour; Courant, direct, If:240mA; Diamètre, extérieur:16mm; Dimension de la lentille:T5; Longueur:2ft; Température de fonctionnement max..:+40°C; Température d'utilisation min:-20°C; Tension, direct If:24V
LAMP, LED 6 W 100-240 V; Puissance:4W; Light Source:LED; Longueur:633mm; Diamètre, lentille:72mm; Safety Category:II
BLOC DE SECURITE 2 PROJECTEURS 2X20W; Longueur:310mm; Largeur:310mm; Profondeur:70mm; IP / NEMA Rating:IP20; SVHC:No SVHC (19-Dec-2011); Hauteur:310mm; Lamp Base Type:BA 15S 12V 20W ; Largeur (externe):310mm; Longueur/hauteur:310mm; Matière:Steel Box; Profondeur:70mm; Puissance:40W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
TUBE FLUORESCENT T4 6W; Lamp Base Type:T4; Puissance:6W; Longueur:220mm; Température, couleur:3400K; SVHC:No SVHC (19-Dec-2011); Emission lumineuse, totale:550lm; Flux lumineux typique:300lm; Longueur/hauteur:220mm; Matière:Opal Glass
LED SX6S MIDGET FLA.28VA/DC CWHT; Lamp Base Type:Midget Flange; Couleur de LED:Blanc froid; Température de couleur proximale:7000K; Intensité lumineuse:480mcd; Puissance:336mW; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:12mA; Angle du faisceau:160°; Durée de vie moyenne de la lampe:50000h; SVHC:No SVHC (19-Dec-2011); Angle, vision:160°; Couleur, LED:Blanc froid; Courant, direct, If:12mA; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:480mcd; Nombre de LED:1; Tempé
LAMPE U.V; Puissance:4.6W; Courant, alimentation:162mA; Longueur:134.5mm; Diamètre de l'ampoule:15.5mm; Lamp Base Type:G5; SVHC:No SVHC (19-Dec-2011); Base Type:G5; Courant:0.162A; Diamètre, extérieur:15mm; Durée de vie:6000h; Durée de vie moyenne de la lampe:6000h; Longueur d'onde, crête:253.7nm; Longueur/hauteur:134mm; Tension, alimentation:30V
BLOC DE SECURITE 8W; Longueur:345mm; Largeur:120mm; Profondeur:75mm; IP / NEMA Rating:IP65; SVHC:No SVHC (19-Dec-2011); Lamp Base Type:Fluorescent T5 300 mm; Largeur (externe):120mm; Longueur/hauteur:345mm; Matière:Polycarbonate; Profondeur:75mm; Puissance:8W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
TUBE FLUORESCENT T4 10W; Lamp Base Type:T4; Puissance:10W; Longueur:341mm; Température, couleur:3400K; SVHC:No SVHC (19-Dec-2011); Emission lumineuse, totale:550lm; Flux lumineux typique:500lm; Longueur/hauteur:341mm; Matière:Opal Glass
BLOC DE SECURITE 8W; Longueur:345mm; Largeur:120mm; Profondeur:75mm; IP / NEMA Rating:IP65; SVHC:No SVHC (19-Dec-2011); Lamp Base Type:Fluorescent T5 300 mm; Largeur (externe):120mm; Longueur/hauteur:345mm; Matière:Polycarbonate; Profondeur:75mm; Puissance:8W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
TUBE FLUORESCENT T4 16W; Lamp Base Type:T4; Puissance:16W; Longueur:468mm; Température, couleur:3400K; SVHC:No SVHC (19-Dec-2011); Emission lumineuse, totale:550lm; Flux lumineux typique:880lm; Longueur/hauteur:479mm; Matière:Opal Glass
TUBE FLUORESCENT T4 20W; Lamp Base Type:T4; Puissance:20W; Longueur:567mm; Température, couleur:3400K; SVHC:No SVHC (19-Dec-2011); Emission lumineuse, totale:550lm; Flux lumineux typique:1200lm; Longueur/hauteur:567mm; Matière:Opal Glass
DOWNLIGHT KIT, 35W, GU5.3, NICKEL, SQR; Longueur:91mm; Largeur:91mm; Profondeur:150mm; SVHC:No SVHC (19-Dec-2011); Largeur (externe):91mm; Light Source:Halogène
DOWNLIGHT KIT, 35W, GU5.3, WHITE, IP24; Profondeur:150mm; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:91mm; Light Source:Halogène
DOWNLIGHT KIT,35W,GU5.3,NICKEL,IP24; Profondeur:150mm; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:91mm; Light Source:Halogène
DOWNLIGHT KIT, 35W, GU5.3, WHITE, IP24; Longueur:91mm; Largeur:91mm; Profondeur:150mm; SVHC:No SVHC (19-Dec-2011); Largeur (externe):91mm; Light Source:Halogène
LED BA9 BAYN 24V AC/DC WARM WHITE; Lamp Base Type:BA9s; Couleur de LED:Blanc chaud; Intensité lumineuse:1180mcd; Taille de lampe:10mm; Tension, alimentation:24V; Courant:18mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc chaud; Courant, direct, If:18mA; Dimension de la lentille:10mm; Intensité lumineuse typique:1180mcd; Nombre de LED:1; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:24V
LED BA9 BAYN 28V AC/DC WARM WHITE; Lamp Base Type:BA9s; Couleur de LED:Blanc chaud; Intensité lumineuse:1180mcd; Taille de lampe:10mm; Tension, alimentation:28V; Courant:18mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc chaud; Courant, direct, If:18mA; Dimension de la lentille:10mm; Intensité lumineuse typique:1180mcd; Nombre de LED:1; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:28V
LED BA9 BAYN 28V AC/DC 3 CHIP WHITE; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:3500mcd; Taille de lampe:10mm; Tension, alimentation:28V; Courant:19mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc; Courant, direct, If:19mA; Dimension de la lentille:10mm; Intensité lumineuse typique:3500mcd; Nombre de LED:3; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:28V
LED BA9 BAYN 28V AC/DC WRM WHT; Lamp Base Type:BA9s; Couleur de LED:Blanc chaud; Intensité lumineuse:3500mcd; Taille de lampe:10mm; Tension, alimentation:28V; Courant:19mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc chaud; Courant, direct, If:19mA; Dimension de la lentille:10mm; Intensité lumineuse typique:3500mcd; Nombre de LED:3; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:28V
TUBE ULTRA VIOLET; Puissance:14.7W; Courant, alimentation:300mA; Longueur:436mm; Diamètre de l'ampoule:25.5mm; Lamp Base Type:G13; SVHC:No SVHC (19-Dec-2011); Base Type:G13; Courant:0.3A; Diamètre, extérieur:25mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Longueur d'onde, crête:253.7nm; Longueur/hauteur:436mm; Tension, alimentation:55V
LAMPE U.V; Puissance:7.9W; Courant, alimentation:170mA; Longueur:287mm; Diamètre de l'ampoule:15.5mm; Lamp Base Type:G5; SVHC:No SVHC (19-Dec-2011); Base Type:G5; Courant:0.17A; Diamètre, extérieur:15mm; Durée de vie:6000h; Durée de vie moyenne de la lampe:6000h; Longueur d'onde, crête:253.7nm; Longueur/hauteur:287mm; Tension, alimentation:56V
LED JAUNE POUR SERIE AML; Couleur de LED:Jaune; Courant:50mA; SVHC:No SVHC (19-Dec-2011); Couleur:Jaune; Courant, direct, If:50mA; Tension, direct If:4V
BLOC DE SECURITE A LED. ARGENT; Longueur:545mm; Profondeur:370mm; IP / NEMA Rating:IP20; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:Argent; Distance, visible max..:30m; Durée de vie (fonctionnement):3 Heures; Matière:Aluminium; Tension, batterie:3.6V
LAMPE; Tension, alimentation:20V; Lamp Base Type:GX5,3; Puissance:150W; Durée de vie moyenne de la lampe:500h; Durée de vie:500h; Longueur/hauteur:44.5mm; Tension:20V
STRIPLIGHT, LED, 600MM PURE CLEAR; Light Source:64 x LED; Longueur:620mm; Largeur:20mm; Profondeur:44mm; Couleur:Transparent; Couleur:Blanc pur; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:620mm; Profondeur:44mm; Puissance:12VA; Taille de lampe:T-4; Température de couleur proximale:5000K; Tension, alimentation:230V
STRIPLIGHT, LED, 800MM PURE PEARL; Light Source:88 x LED; Longueur:820mm; Largeur:20mm; Profondeur:44mm; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:820mm; Profondeur:44mm; Puissance:12VA; Taille de lampe:T-4; Température de couleur proximale:5000K; Tension, alimentation:230V
STRIPLIGHT, LED, ULP 500MM PUR CLR; Light Source:56 x LED; Longueur:520mm; Largeur:16mm; Profondeur:16mm; Couleur:Blanc pur; Couleur de LED:Blanc; Courant:500mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:520mm; Profondeur:16mm; Puissance:6VA; Température de couleur proximale:5000K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 500MM PUR PRL; Light Source:56 x LED; Longueur:520mm; Largeur:16mm; Profondeur:16mm; Couleur de LED:Blanc; Courant:500mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:520mm; Profondeur:16mm; Puissance:6VA; Température de couleur proximale:5000K; Tension, alimentation:12V
STRIPLIGHT, LED, ULP 800MM CLD PRL; Light Source:92 x LED; Longueur:820mm; Largeur:16mm; Profondeur:16mm; Couleur de LED:Blanc; Courant:830mA; Durée de vie moyenne de la lampe:50000h; Largeur (externe):16mm; Longueur/hauteur:820mm; Profondeur:16mm; Puissance:9.9VA; Température de couleur proximale:7500K; Tension, alimentation:12V
LED E14 24V BLANC; Lamp Base Type:Vis miniature, E14; Couleur de LED:Blanc; Intensité lumineuse:2500mcd; Taille de lampe:T-5; Tension, alimentation:24V; Courant:17mA; Angle du faisceau:110°; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Courant, direct, If:17mA; Dimension de la lentille:T5; Intensité lumineuse, max..:2500mcd; Tension, direct If:24V; Tolérance, tension d'alimentation c.a.+:10%; Tolérance, tension d'alimentation, c.c. +:10%
ULTRA SLIM ESD MAGNIFIER PRISE UK; Puissance:28W; Light Source:Fluorescente; Longueur:950mm; Diamètre, lentille:175mm; SVHC:No SVHC (19-Dec-2011)
TUBE ECONOMIE ENERGIE. 9W; Tension, alimentation:230V; Puissance:9W; Température, couleur:6400K
TUBE CIRCULAIRE ES. 12W; Tension, alimentation:230V; Puissance:12W; Température, couleur:6400K
AMPOULE. 2D - 2 BROCHE 16W; Tension, alimentation:240V; Lamp Base Type:2 broches 2D; Puissance:16W; Flux lumineux:960lm; Longueur:138mm; Diamètre de l'ampoule:135mm; Température, couleur:6400K; Diamètre, extérieur:135mm; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Flux lumineux typique:960lm; Intensité lumineuse, max..:960lm; Largeur (externe):135mm; Longueur/hauteur:138mm
AMPOULE. MR11 HALOGENEE 20W 30 DEGREE27; Tension, alimentation:12V; Lamp Base Type:GZ4; Puissance:20W; Diamètre, réflecteur:37mm; Divergence du faisceau:30°
AMPOULE. PAR16 E14 VERT; Tension, alimentation:240V; Lamp Base Type:E14; Puissance:40W; Diamètre de l'ampoule:50mm; Couleur:Green; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Longueur/hauteur:85mm; Taille de lampe:Parabolique, PAR16, 50 mm; Tension:240VAC
AMPOULE. PAR16 E14 BLEU; Tension, alimentation:240V; Lamp Base Type:E14; Puissance:40W; Diamètre de l'ampoule:50mm; Couleur:Blue; Diamètre, extérieur:50mm; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Longueur/hauteur:85mm; Taille de lampe:Parabolique, PAR16, 50 mm; Tension:240VAC
TUBE DE LED T5 LUM. DU JOUR 30.5CM; Couleur de LED:Blanc; Température de couleur proximale:6500K; Puissance:2.88W; Taille de lampe:T-5; Tension, alimentation:24V; Courant:120mA; Angle du faisceau:60°; Angle:60°; Consommation de puissance:2.88W; Couleur:Lumière du jour; Courant, direct, If:120mA; Diamètre, extérieur:16mm; Dimension de la lentille:T5; Longueur:1ft; Température de fonctionnement max..:+40°C; Température d'utilisation min:-20°C; Tension, direct If:24V
DOWNLIGHT, LED, 12DEG, WHITE; Couleur de LED:Blanc; SVHC:No SVHC (19-Dec-2011); Couleur:Warm White; Diamètre, extérieur:80mm; Light Source:LED; Profondeur:103mm
DOWNLIGHT KIT, LED, 4.5W, ROUND; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:91mm; Light Source:LED; Profondeur:90mm
DOWNLIGHT KIT, LED, 4.5W, SQUARE; SVHC:No SVHC (19-Dec-2011); Largeur (externe):91mm; Light Source:LED; Longueur:91mm; Profondeur:90mm
DOWNLIGHT KIT, 35W, GU5.3, WHITE, RND; Profondeur:150mm; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:91mm; Light Source:Halogène
LAMPE TORCHE RECHARGEABLE. LED. JAUNE; Longueur:189mm; Largeur:112mm; Profondeur:128.5mm; Largeur (externe):112mm; Light Source:LED
DETECTEUR INFRA ROUGE 360° FM BLANC; Angle de faisceau:360°; Longueur:71mm; Largeur:84mm; Profondeur:84mm; Couleur:Blanc; Distance de détection max..:6m; IP / NEMA Rating:IP44; Lamp Base Type:Incandescent / Halogène; Largeur (externe):84mm; Longueur/hauteur:71mm; Profondeur:84mm; Puissance:2kW; Tension, alimentation:230V
DOWNLIGHT, LED, 36DEG, WHITE; Couleur de LED:Blanc; SVHC:No SVHC (19-Dec-2011); Couleur:Cool White; Diamètre, extérieur:80mm; Light Source:LED; Profondeur:99mm
DOWNLIGHT KIT, 35W, GU5.3, NICKEL, RND; Largeur:91mm; Profondeur:150mm; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:91mm; Light Source:Halogène
DOWNLIGHT KIT, 35W, GU5.3, WHITE, SQR; Longueur:91mm; Largeur:91mm; Profondeur:150mm; SVHC:No SVHC (19-Dec-2011); Largeur (externe):91mm; Light Source:Halogène
BANDE LUMINEUSE A LED 24-48VDC. VIS; Puissance:5W; Light Source:LED; Longueur:351mm; Diamètre, lentille:32mm; SVHC:No SVHC (20-Jun-2011)
LED FESTOON 0.5W WARM BLANC 12X42; Lamp Base Type:T-3 3/4; Couleur de LED:Blanc chaud; Température de couleur proximale:3000K; Puissance:500mW; Tension, alimentation:12VDC; Courant:40mA; Angle du faisceau:110°; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011)
BANDE LUMINEUSE A LED 100-240VAC. AIMANT; Lamp Base Type:Vis; Puissance:5W; Light Source:LED; Longueur:351mm; Diamètre, lentille:32mm; SVHC:No SVHC (20-Jun-2011)
STATION DE TRAVAIL ESD LAMPE - UK; Puissance:18W; Light Source:Fluorescente; Longueur:900mm; SVHC:No SVHC (19-Dec-2011)
LED FESTOON 0.5W WARM BLANC 12X42; Lamp Base Type:T-3 3/4; Couleur de LED:Blanc chaud; Température de couleur proximale:3000K; Puissance:500mW; Tension, alimentation:24VDC; Courant:20mA; Angle du faisceau:110°; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011)
LED FESTOON 1W WARM BLANC 12X42; Lamp Base Type:T-3 3/4; Couleur de LED:Blanc chaud; Température de couleur proximale:3200K; Puissance:1W; Tension, alimentation:12VDC; Courant:80mA; Angle du faisceau:120°; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011)
LED FESTOON 1W WARM BLANC 12X42; Lamp Base Type:T-3 3/4; Couleur de LED:Blanc chaud; Température de couleur proximale:3200K; Puissance:1W; Tension, alimentation:24VDC; Courant:40mA; Angle du faisceau:120°; Durée de vie moyenne de la lampe:20000h; SVHC:No SVHC (19-Dec-2011)
LED S5.7S MIDG-GRO 24V AC/DC WHT; Lamp Base Type:S5,7s; Couleur de LED:Blanc; Intensité lumineuse:1100mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:17mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc; Courant, direct, If:17mA; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:1100mcd; Nombre de LED:1; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:24V
LED S5.7S MIDG-GRO 28V AC/DC WHT; Lamp Base Type:S5,7s; Couleur de LED:Blanc; Intensité lumineuse:900mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc; Courant, direct, If:14mA; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:900mcd; Nombre de LED:1; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:28V
LED S5.7S MIDG-GRO 24V AC/DC WM WHT; Lamp Base Type:S5,7s; Couleur de LED:Blanc chaud; Intensité lumineuse:1100mcd; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:17mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc chaud; Courant, direct, If:17mA; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:1100mcd; Nombre de LED:1; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:24V
LED BA9 BAYN 28V AC/DC WHITE; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:1180mcd; Taille de lampe:10mm; Tension, alimentation:28V; Courant:18mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc; Courant, direct, If:18mA; Dimension de la lentille:10mm; Intensité lumineuse typique:1180mcd; Nombre de LED:1; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:28V
LED BA9 BAYN 24V AC/DC 3 CHIP WHITE; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:3700mcd; Taille de lampe:10mm; Tension, alimentation:24V; Courant:20mA; Angle du faisceau:115°; SVHC:No SVHC (19-Dec-2011); Couleur, LED:Blanc; Courant, direct, If:20mA; Dimension de la lentille:10mm; Intensité lumineuse typique:3700mcd; Nombre de LED:3; Température de fonctionnement:-25°C +60°C; Tension, Vf max..:24V
LED SX6S MIDGET FLA.28VA/DC WWHT; Lamp Base Type:Midget Flange; Couleur de LED:Blanc chaud; Température de couleur proximale:3300K; Intensité lumineuse:525mcd; Puissance:360mW; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:13mA; Angle du faisceau:160°; Durée de vie moyenne de la lampe:50000h; SVHC:No SVHC (19-Dec-2011); Angle, vision:160°; Couleur, LED:Blanc chaud; Courant, direct, If:13mA; Dimension de la lentille:T-1 3/4; Intensité lumineuse typique:525mcd; Nombre de LED:1; Tempé
AMPOULE 57W. GX24Q-5; Lamp Base Type:GX24q-5; Puissance:57W; Longueur:188mm; Température, couleur:6400K; SVHC:No SVHC (19-Dec-2011); Couleur:White; Largeur (externe):44mm; Light Source:CFL
LAMPE T-1 3/4 28V POUR AML SERIES; Tension, alimentation:28V; Lamp Base Type:Wedge; Taille de lampe:T-3 1/4; Puissance:1.12W; MSCP:0.3; Durée de vie moyenne de la lampe:7000h; SVHC:No SVHC (19-Dec-2011)
DOWNLIGHT, LED, 12DEG, WHITE; Couleur de LED:Blanc; SVHC:No SVHC (19-Dec-2011); Couleur:Cool White; Diamètre, extérieur:80mm; Light Source:LED; Profondeur:103mm
DOWNLIGHT KIT,35W,GU5.3,NICKEL,IP24; Longueur:91mm; Largeur:91mm; Profondeur:150mm; SVHC:No SVHC (19-Dec-2011); Largeur (externe):91mm; Light Source:Halogène
LED LIGHT, DOT-IT, BLACK; SVHC:No SVHC (19-Dec-2011); Largeur (externe):67mm; Light Source:LED; Longueur:67mm; Profondeur:22mm
LED LIGHT, DOT-IT, PLATINUM; SVHC:No SVHC (19-Dec-2011); Largeur (externe):67mm; Light Source:LED; Longueur:67mm; Profondeur:22mm
LAMPE DE BUREAU 30W 230V; Lamp Base Type:Pince; Puissance:250W; Light Source:3 x tube économie d'énergie 14W; SVHC:No SVHC (19-Dec-2011)
LAMPE HALOGENE 6V 300MA; Tension, alimentation:6V; Lamp Base Type:B-3 1/2 bride; Puissance:1.44W; Température, couleur:3000K; Courant:0.3A; Durée de vie:500h; Durée de vie moyenne de la lampe:500h; Intensité lumineuse, max..:50000cd; Tension c.a.:6V
T1 MF SX3S BASE ROUGE LED 28VDC; Couleur de LED:Rouge; Intensité lumineuse:39mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:11mA; Tension, direct If:28V
T1 MF SX3S BASE BLEU LED 28VDC; Couleur de LED:Bleu; Intensité lumineuse:128mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:11mA; Tension, direct If:28V
T1 MF SX3S BASE WHITE LED 12VDC; Couleur de LED:Blanc froid; Intensité lumineuse:414mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:12mA; Tension, direct If:12V
T1 MF SX3S BASE WHITE LED 28VDC; Couleur de LED:Blanc froid; Intensité lumineuse:414mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:11mA; Tension, direct If:28V
T6.8 SLIDE BASE BLEU 12VDC; Couleur de LED:Bleu; Longueur d'onde typ.:470nm; Intensité lumineuse:7cd; Puissance:625mW; Taille de lampe:T-6 4/5; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
LAMP, 12V, 10W; Tension, alimentation:12V; Puissance:10W; Tension c.a.:12V
T1 MF SX3S BASE JAUNE LED 12VDC; Couleur de LED:Jaune; Intensité lumineuse:87mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
T6.8 SLIDE BASE WARM WHITE 12VDC; Couleur de LED:Blanc chaud; Intensité lumineuse:9.2cd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
WORK LIGHT, 230/12V, 700MM; Tension, alimentation:230V; Puissance:20W; Light Source:Halogène; Longueur:700mm; Couleur:Noir; Diamètre, base:60mm; IP / NEMA Rating:IP20; Longueur (max..):960mm; Longueur/hauteur:960mm; Matière:Polycarbonate; Tension, alimentation c.a. max..:230V; Tension, alimentation c.c. max..:12V
LED ROUGE 24V; Lamp Base Type:BA15d; Couleur de LED:Rouge; Tension, alimentation:24V; SVHC:No SVHC (19-Dec-2011); Couleur:Red; Couleur, LED:Rouge; Température de fonctionnement:-25°C +50°C; Tension VDC:24V; Tension, Vf max..:24V; Tension, Vf typ.:24V; Tension, direct If:24V; Type de boîtier:Zamak; Type de boîtier opto:Zamak
LAMPE BA15D 12V; Tension, alimentation:12V; Lamp Base Type:BA15d; Puissance:10W; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Tension:12V; Tension c.a.:12V
LED MONTAGE AVANT 18-30VAC/DC. BLANC; Lamp Base Type:BA9s; Tension, alimentation:30V; Puissance:260mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:55°C; Température d'utilisation min:-25°C
LED MONTAGE ARRIERE 18-30VAC/DC. ROUGE; Tension, alimentation:30V; Puissance:260mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:55°C; Température d'utilisation min:-25°C
LED MONTAGE ARRIERE 85-264VAC. BLANC; Tension, alimentation:264V; Puissance:330mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:70°C; Température d'utilisation min:-25°C
LAMPE UVA 609MM 20W; Puissance:20W; Longueur:610mm; Lamp Base Type:Bi-broche; SVHC:No SVHC (19-Dec-2011); Base Type:Bi-broche; Longueur/hauteur:610mm; Température de fonctionnement max..:50°C; Température d'utilisation min:-25°C
LAMPE POUR MAGLITE AA ET AAA; Taille de lampe:8mm; Puissance:900mW; Dimension de la lentille:8mm; Quantité par paquet:2
LAMPE ES50 50W 240V GU10 25; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:50W; Longueur:55mm; Diamètre, réflecteur:51mm; Température, couleur:2750K; Diamètre, extérieur:51mm; Durée de vie:2500h; Durée de vie moyenne de la lampe:2500h; Intensité lumineuse, max..:1150cd; Tension c.a.:240V
LAMPE 63 50W 240V E27 25; Tension, alimentation:240V; Lamp Base Type:E27; Puissance:50W; Longueur:88mm; Diamètre, réflecteur:65mm; Température, couleur:2900K; Diamètre, extérieur:63mm; Divergence du faisceau:25°; Durée de vie:2500h; Durée de vie moyenne de la lampe:2500h; Intensité lumineuse, max..:1000cd; Tension c.a.:240V; Tension d'alimentation Vac:240V
LAMPE 80 50W 240V E27 10; Tension, alimentation:240V; Lamp Base Type:E27; Puissance:50W; Longueur:108mm; Diamètre, réflecteur:81mm; Température, couleur:2900K; Diamètre, extérieur:80mm; Divergence du faisceau:10°; Durée de vie:2500h; Durée de vie moyenne de la lampe:2500h; Intensité lumineuse, max..:4000cd; Tension c.a.:240V; Tension d'alimentation Vac:240V
LAMPE 80 75W 240VE27 25; Tension, alimentation:240V; Lamp Base Type:E27; Puissance:75W; Longueur:108mm; Diamètre, réflecteur:81mm; Température, couleur:2900K; Diamètre, extérieur:80mm; Divergence du faisceau:25°; Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:1300cd; Tension c.a.:240V; Tension d'alimentation Vac:240V
LAMPE 95 75W 240V E27 30; Tension, alimentation:240V; Lamp Base Type:E27; Puissance:75W; Longueur:91mm; Diamètre, réflecteur:97mm; Température, couleur:2900K; Diamètre, extérieur:95mm; Divergence du faisceau:30°; Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:2200cd; Tension c.a.:240V; Tension d'alimentation Vac:240V
LAMPE 95 100W 240V E27 30; Tension, alimentation:240V; Lamp Base Type:E27; Puissance:100W; Longueur:91mm; Diamètre, réflecteur:97mm; Température, couleur:2900K; Diamètre, extérieur:95mm; Divergence du faisceau:30°; Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:3500cd; Tension c.a.:240V; Tension d'alimentation Vac:240V
TUBE FLUO MINIATURE T5 4W; Tension, alimentation:29V; Lamp Base Type:G5; Puissance:4W; Flux lumineux:140lm; Longueur:136mm; Diamètre de l'ampoule:16mm; Température, couleur:3500K; Couleur:White; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Flux lumineux typique:145lm; Intensité lumineuse, max..:145lm; Longueur/hauteur:150mm
TUBE FLUO T5 FHE 21W BLANC CHAUD; Tension, alimentation:123V; Lamp Base Type:G5; Puissance:21W; Flux lumineux:1910lm; Longueur:849mm; Diamètre de l'ampoule:16mm; Température, couleur:3000K; Couleur:Blanc chaud; Couleur:Warm White; Courant:170mA; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Durée de vie:16000h; Durée de vie moyenne de la lampe:16000h; Flux lumineux typique:2100lm; Intensité lumineuse, max..:2100lm; Longueur/hauteur:850mm
TUBE FLUO T5 FHE 28W BLANC CHAUD; Tension, alimentation:167V; Lamp Base Type:G5; Puissance:28W; Flux lumineux:2640lm; Longueur:1.15m; Diamètre de l'ampoule:16mm; Température, couleur:3000K; Couleur:Blanc chaud; Couleur:Warm White; Courant:170mA; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Durée de vie:16000h; Durée de vie moyenne de la lampe:16000h; Flux lumineux typique:2900lm; Intensité lumineuse, max..:2900lm; Longueur/hauteur:1150mm
TUBE FLUO T5 FHE 35W BLANC CHAUD; Tension, alimentation:209V; Lamp Base Type:G5; Puissance:35W; Flux lumineux:3320lm; Longueur:1.45m; Diamètre de l'ampoule:16mm; Température, couleur:3000K; Couleur:Blanc chaud; Couleur:Warm White; Courant:170mA; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Durée de vie:16000h; Durée de vie moyenne de la lampe:16000h; Flux lumineux typique:3650lm; Intensité lumineuse, max..:3650lm; Longueur/hauteur:1450mm
AMPOULE POUR LAMPE TORCHE T4 (PQ2); Tension, alimentation:2.4V; Taille de lampe:T-4; Courant:700mA; SVHC:No SVHC (19-Dec-2011); Dimension de la lentille:T-4; Durée de vie:50h; Durée de vie moyenne de la lampe:50h; Intensité lumineuse, max..:15lm
LAMPE TORCHE (PQ2); Tension, alimentation:4.8V; Lamp Base Type:B-3 1/2; Taille de lampe:11mm; Couleur:Clear; Courant:0.75A; Diamètre, extérieur:11mm; Dimension de la lentille:11mm; Longueur/hauteur:29mm; Quantité par paquet:2; Tension:4.8V; Tension c.a.:4.8V
AMPOULE POUR TORCHE PQ2; Couleur:Clear; Quantité par paquet:2
AMPOULE POUR MAG-LITE 2 PILES PQ2; Tension, alimentation:2.4V; Durée de vie moyenne de la lampe:36h; Courant:0.67A; Durée de vie:36h; Quantité par paquet:2; Tension:2.4V
WORK LAMP, MAGNETIC MOUNT; Tension, alimentation:12V; Lamp Base Type:H3; Puissance:55W; Light Source:H3 55W; Longueur:240mm; Diamètre, lentille:162mm; SVHC:No SVHC (19-Dec-2011); Calibre du Fusible:8A; Courant:4.6A; Courant, fonctionnement c.c.:4.6A; Diamètre, câble min.:1mm; Largeur (externe):162mm; Longueur (max..):240mm; Longueur/hauteur:239mm; Matière:Polypropylène et polycarbonate; Matière, lentille:Polycarbonate; Profondeur:92mm; Taille de fil, mm2 min.:1mmË›; Tension, alimentation c.c.:12V
LAMPE DULUX DE HF 10W INTERNA; Tension, alimentation:51V; Lamp Base Type:G24q; Puissance:10W; Flux lumineux:600lm; Longueur:103mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Couleur:Interna; Flux lumineux typique:600lm; Intensité lumineuse, max..:600lm; Longueur/hauteur:103mm; Nombre de broches:4
AMPOULE DE RECHANGE; SVHC:No SVHC (19-Dec-2011)
LAMPE SODIUM SON+ TUBULAIRE 150W; Température, couleur:2000K; Courant:1.8A; SVHC:No SVHC (19-Dec-2011); Diamètre, extérieur:46mm; Intensité lumineuse, max..:17500lm; Lamp Base Type:ES(E40); Longueur/hauteur:211mm; Puissance:150W; Tension, alimentation:240V
LAMP, DICHRORIC, 12V, 10W; Tension, alimentation:12V; Puissance:10W
LED VERTE 24V; Lamp Base Type:BA15d; Couleur de LED:Vert; Tension, alimentation:24V; SVHC:No SVHC (19-Dec-2011); Couleur:Green; Couleur, LED:Vert; Température de fonctionnement:-25°C +50°C; Tension VDC:24V; Tension, Vf max..:24V; Tension, Vf typ.:24V; Tension, direct If:24V; Type de boîtier:Zamak; Type de boîtier opto:Zamak
LED MONTAGE AVANT 12-30VAC/DC. VERT; Puissance:260mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:70°C; Température d'utilisation min:-25°C; Tension, alimentation c.a. max..:30V; Tension, alimentation c.a. min:12V; Tension, alimentation c.c. max..:30V; Tension, alimentation c.c. min.:12V; Type de terminaison: visser
LED MONTAGE AVANT 18-30VAC/DC. BLEU; Tension, alimentation:30V; Puissance:260mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:Bleu; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:55°C; Température d'utilisation min:-25°C
LED MONTAGE AVANT 85-264VAC. ROUGE; Tension, alimentation:264V; Puissance:330mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:70°C; Température d'utilisation min:-25°C
LED. F/FXG. 85V-264VAC. VERT; Tension, alimentation:264V; Puissance:330mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:70°C; Température d'utilisation min:-25°C
AMPOULE 12V; Tension, alimentation:12V; Lamp Base Type:BA15d; Puissance:4.8W; Durée de vie moyenne de la lampe:2000h; SVHC:No SVHC (20-Jun-2011); Couleur:Clear; Courant:0.43A; Dimension de la lentille:BA15d; Durée de vie:2000h; Tension:12V; Tension c.a.:12V
AMPOULE 24V; Tension, alimentation:24V; Lamp Base Type:BA15d; Taille de lampe:BA15d; Puissance:4.8W; Durée de vie moyenne de la lampe:2000h; SVHC:No SVHC (20-Jun-2011); Courant:0.21A; Dimension de la lentille:BA15d; Durée de vie:2000h; Tension c.a.:24V
LAMPE LOUPE MAGNIFIQUE BLANCHE; Puissance:18W; Longueur:1.05m; Longueur (max..):1050mm; Longueur/hauteur:1050mm
LAMPE UVA 304MM 8W; Puissance:8W; Longueur:305mm; Lamp Base Type:Bi-broche; SVHC:No SVHC (19-Dec-2011); Base Type:Bi-broche; Longueur/hauteur:305mm; Température de fonctionnement max..:50°C; Température d'utilisation min:-25°C
LAMPE UVA 457MM 15W; Puissance:15W; Longueur:457mm; Lamp Base Type:Bi-broche; SVHC:No SVHC (19-Dec-2011); Base Type:Bi-broche; Longueur/hauteur:457mm; Température de fonctionnement max..:50°C; Température d'utilisation min:-25°C
BLOC D'ECLAIRAGE B22 100W TRANSP; Light Source:BC GLS 100W; Longueur:240mm; Largeur:117mm; Profondeur:140mm; Couleur:Clear; Puissance:100W; Tension, alimentation:230V
BLOC D'ECLAIRAGE GLS 100W VERRE TRANSP; Light Source:BC GLS 100W; Longueur:240mm; Largeur:117mm; Profondeur:140mm; Couleur:Clear; Puissance:100W; Tension, alimentation:230V
INDICATEUR NEON ROUGE; Tension, alimentation:230V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:8mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Rouge; Couleur, lentilles:Rouge; Diamètre de découpe panneau:8mm; Diamètre de découpe panneau:8.0mm; Diamètre, extérieur:9.5mm; Durée de vie:25000h; Durée de vie moyenne de la lampe:25000h; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.8mm; Longueur:37mm; Longueur/hauteur:37mm; Tensi
LAMPE BA5D 230V 7W; Tension, alimentation:230V; Lamp Base Type:BA15d; Puissance:7W; SVHC:No SVHC (19-Dec-2011); IP / NEMA Rating:IP65; Light Source:Å” incandescence; Longueur:52mm; Matière:Polycarbonate
LAMPE 50 40W 240V E14 25; Tension, alimentation:240V; Lamp Base Type:E14; Puissance:40W; Longueur:79mm; Diamètre, réflecteur:50mm; Température, couleur:2700K; Diamètre, extérieur:50mm; Divergence du faisceau:25°; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Intensité lumineuse, max..:950cd; Tension c.a.:240V; Tension d'alimentation Vac:240V
TUBE FLUO MINIATURE T5 8W; Tension, alimentation:56V; Lamp Base Type:G5; Puissance:8W; Flux lumineux:400lm; Longueur:288mm; Diamètre de l'ampoule:16mm; Température, couleur:3500K; Couleur:White; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Flux lumineux typique:400lm; Longueur/hauteur:300mm
FLEXIBLE LAMP, HM, 12V, 700MM, 35W; Tension, alimentation:12V; Puissance:35W; Longueur:910mm; Longueur (max..):700mm
AMPOULE POUR H-4DCA; Tension, alimentation:4.8V; Puissance:2.4W; Diamètre, réflecteur:100mm; SVHC:No SVHC (19-Dec-2011); Courant:0.5A; Divergence du faisceau:3.5°; Durée de vie:20h; Durée de vie moyenne de la lampe:20h; Intensité lumineuse, max..:37lm; MSCP:2.94; Tension c.a.:4.8V
LAMPE BA15D 7W 120V PAQUET DE 10; Tension, alimentation:120V; Lamp Base Type:BA15d; Puissance:7W; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Quantité par paquet:10; Taille:BA15d; Tension:120V; Tension c.a.:120V
AMPOULE POUR MAG-LITE 3 PILES PQ2; Tension, alimentation:3.8V; Durée de vie moyenne de la lampe:38h; Courant:0.6A; Durée de vie:38h; Quantité par paquet:2; Tension:3.8V
AMPOULE DE REMPLACEMENT POUR 3535678; Puissance:15W; Flux lumineux:900lm; Longueur:760mm; Température, couleur:6500K; SVHC:No SVHC (19-Dec-2011); Longueur/hauteur:76cm
T6.8 SLIDE BASE JAUNE 12VDC; Couleur de LED:Jaune; Longueur d'onde typ.:591nm; Intensité lumineuse:16cd; Puissance:625mW; Taille de lampe:T-6 4/5; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
T6.8 SLIDE BASE WHITE 12VDC; Couleur de LED:Blanc froid; Température de couleur proximale:8000K; Intensité lumineuse:14cd; Puissance:625mW; Taille de lampe:T-6 4/5; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
LAMPE HALOGENE 2.5V 0.5A; Tension, alimentation:4V; Courant:0.5A
VOYANT NEON ROUGE; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:10mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Diamètre de découpe panneau:10mm; Diamètre, lentille:13.2mm; Epaisseur, panneau max..:12mm; Longueur/hauteur:57.8mm; Tension d'alimentation Vac:130V
AMPOULE POUR PENLIGHT 742 PQ2; Lamp Base Type:Vis; SVHC:No SVHC (20-Jun-2011); Couleur:Clear; Tension:2.25V; Tension c.a.:2.25V; Tension, alimentation:2.25V
SUPPORT FLUORESCENT T5. 13W; Tension, alimentation:230V; Lamp Base Type:Fluorescent T5 525 mm 13W; Puissance:13W; Longueur:570mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011)
T1 MF SX3S BASE ROUGE LED 12VDC; Couleur de LED:Rouge; Intensité lumineuse:39mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
T1 MF SX3S BASE VERT LED 12VDC; Couleur de LED:Vert; Intensité lumineuse:576mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
T1 MF SX3S BASE JAUNE LED 28VDC; Couleur de LED:Jaune; Intensité lumineuse:87mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:11mA; Tension, direct If:28V
T1 MF SX3S BASE BLEU LED 12VDC; Couleur de LED:Bleu; Intensité lumineuse:128mcd; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
T6.8 SLIDE BASE ROUGE12VDC; Couleur de LED:Rouge; Longueur d'onde typ.:643nm; Intensité lumineuse:11cd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:12V
T6.8 SLIDE BASE ROUGE28VDC; Couleur de LED:Rouge; Longueur d'onde typ.:643nm; Intensité lumineuse:11cd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Courant, direct, If:20mA; Tension, direct If:28V
AMPOULE 12V SX3S S6/8 3MM; Tension, alimentation:12V; Lamp Base Type:Sub-Midget Flange SX4s; Taille de lampe:T-1; Puissance:700mW; Durée de vie moyenne de la lampe:16000h; Courant:0.06A; Dimension de la lentille:T1; Durée de vie:16000h; Emission lumineuse, totale:1.9lm; Longueur/hauteur:14mm; Tension c.a.:12V
LAMPE DULUX DE HF 18W INTERNA; Tension, alimentation:80V; Lamp Base Type:G24q; Puissance:18W; Flux lumineux:1200lm; Longueur:130mm; Température, couleur:2700K; SVHC:No SVHC (19-Dec-2011); Couleur:Interna; Flux lumineux typique:1200lm; Intensité lumineuse, max..:1200lm; Longueur/hauteur:146mm; Nombre de broches:4
LED MIDGET 28V BLANC; Lamp Base Type:Midget Groove, S5,7s; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Puissance:500mW; Taille de lampe:4.8mm; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:17mA; Courant, direct, If:17mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fonc
LED MIDGET 12V BLANC; Lamp Base Type:Midget Flange; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Taille de lampe:4.8mm; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fonctionnement:-40°C +80°C
LED BA9 12V BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Puissance:625mW; Taille de lampe:4.8mm; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fonctionnement:-40°C
LED BA9 24V BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Température de couleur proximale:8000K; Intensité lumineuse:3000mcd; Puissance:625mW; Taille de lampe:4.8mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Temp
LED A BAYONNETTE BA9 VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:6000mcd; Taille de lampe:4.8mm; Tension, alimentation:50V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:Green; Couleur, LED:Vert; Courant, If moy.:10mA; Courant, If, intensité lumineuse:20mA; Courant, direct, If:10mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typiq
LED A BAYONNETTE BA9 BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Taille de lampe:4.8mm; Tension, alimentation:50V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:10mA; Courant, If, intensité lumineuse:20mA; Courant, direct, If:10mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Tempéra
LED MIDGET ROUGE; Lamp Base Type:Midget Groove; Couleur de LED:Rouge; Longueur d'onde typ.:660nm; Intensité lumineuse:2750mcd; Taille de lampe:4.8mm; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Rouge; Couleur, LED:Rouge; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:5.6mm; Dimension de la lentille:4.8mm; Intensité lumineuse typique:2750mcd; Longueur d'onde, cr
HALOGEN LAMP, 12V, 50W; Tension, alimentation:12V; Lamp Base Type:Bi-broche; Puissance:50W; Tension, alimentation c.c.:12V
LED MIDGET VERT; Lamp Base Type:Midget Groove; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:6000mcd; Taille de lampe:4.8mm; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Vert; Couleur, LED:Vert; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:5.6mm; Dimension de la lentille:4.8mm; Intensité lumineuse typique:6000mcd; Longueur d'onde, crête:
LED MIDGET VERT; Lamp Base Type:Midget Groove; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:6000mcd; Taille de lampe:4.8mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Vert; Couleur, LED:Vert; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:5.6mm; Dimension de la lentille:4.8mm; Intensité lumineuse typique:6000mcd; Longueur d'onde, crête:
LED A BAYONNETTE BA9 VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:6000mcd; Puissance:625mW; Taille de lampe:4.6mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Green; Couleur, LED:Vert; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:9.2mm; Dimension de la lentille:4.6mm; Intensité lumineuse typique:6000mcd; Long
LED T5.5 12V VERT; Lamp Base Type:Ampoule de téléphonie; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:6000mcd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Green; Couleur, LED:Vert; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:4.8mm; Dimension de la lentille:T5.5; Intensité lumineuse typique:600
LED T5.5 28V JAUNE; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Jaune; Longueur d'onde typ.:590nm; Intensité lumineuse:4500mcd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Yellow; Couleur, LED:Jaune; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:4.8mm; Dimension de la lentille:T5.5; Intensité lumineuse t
LAMPE BA15D 230V; Tension, alimentation:230V; Lamp Base Type:BA15d; Puissance:25W; SVHC:No SVHC (19-Dec-2011); Tension:230VAC; Tension c.a.:230V
LAMPE BA15D 24V; Tension, alimentation:24V; Lamp Base Type:BA15d; Puissance:4W; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Tension:24V; Tension c.a.:24V
LED MONTAGE AVANT 85-264VAC. BLANC; Tension, alimentation:264V; Puissance:330mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:70°C; Température d'utilisation min:-25°C
LED MONTAGE AVANT 85-264VAC. BLEU; Tension, alimentation:264V; Puissance:330mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:Bleu; Courant, direct, If:15mA; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement:-25°C +70°C; Température de fonctionnement max..:70°C; Température d'utilisation min:-25°C; Tension, Vf max..:264VAC
LED MONTAGE ARRIERE 85-264VAC. ROUGE; Tension, alimentation:264V; Puissance:330mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:70°C; Température d'utilisation min:-25°C
TETE DE LAMPE TEMOIN JAUNE BA9S; Lamp Base Type:BA9s; SVHC:No SVHC (19-Dec-2011); Couleur:Jaune; Diamètre de découpe panneau:22mm
TETE DE LAMPE TEMOIN BLEU BA9S; Lamp Base Type:BA9s; SVHC:No SVHC (19-Dec-2011); Couleur:Bleu; Diamètre de découpe panneau:22mm
LAMPE BA15D 24V 7W; Tension, alimentation:24V; Lamp Base Type:BA15d; Puissance:7W; SVHC:No SVHC (19-Dec-2011); IP / NEMA Rating:IP65; Light Source:Å” incandescence; Longueur:52mm; Matière:Polycarbonate
LAMPE ES50 50W 240V GU10 50; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:50W; Longueur:55mm; Diamètre, réflecteur:51mm; Température, couleur:2750K; Diamètre, extérieur:51mm; Durée de vie:2500h; Durée de vie moyenne de la lampe:2500h; Intensité lumineuse, max..:500cd; Tension c.a.:240V
LAMPE 120 100W 240V E27 30; Tension, alimentation:240V; Lamp Base Type:E27; Puissance:100W; Longueur:136mm; Diamètre, réflecteur:124mm; Température, couleur:2900K; Diamètre, extérieur:120mm; Divergence du faisceau:30°; Durée de vie:3000h; Durée de vie moyenne de la lampe:3000h; Intensité lumineuse, max..:3500cd; Tension c.a.:240V; Tension d'alimentation Vac:240V
TUBE FLUO MINIATURE T5 6W; Tension, alimentation:42V; Lamp Base Type:G5; Puissance:6W; Flux lumineux:280lm; Longueur:212mm; Diamètre de l'ampoule:16mm; Température, couleur:3500K; Couleur:White; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Flux lumineux typique:280lm; Longueur/hauteur:225mm
TUBE FLUO T5 FHE 35W BLANC FROID; Tension, alimentation:209V; Lamp Base Type:G5; Puissance:35W; Flux lumineux:3320lm; Longueur:1.45m; Diamètre de l'ampoule:16mm; Température, couleur:4000K; Couleur:Blanc froid; Couleur:Cool White; Courant:170mA; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Durée de vie:16000h; Durée de vie moyenne de la lampe:16000h; Flux lumineux typique:3650lm; Intensité lumineuse, max..:3650lm; Longueur/hauteur:1450mm
TUBE FLUO T5 FHO 24W BLANC FROID; Tension, alimentation:75V; Lamp Base Type:G5; Puissance:24W; Flux lumineux:1700lm; Longueur:549mm; Diamètre de l'ampoule:16mm; Température, couleur:4000K; Couleur:Blanc froid; Couleur:Cool White; Courant:300mA; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Durée de vie:16000h; Durée de vie moyenne de la lampe:16000h; Flux lumineux typique:2000lm; Intensité lumineuse, max..:2000lm; Longueur/hauteur:550mm
AMPOULE DE REMPLACEMENT H1 70W; Tension, alimentation:24V; Puissance:70W; Tension, alimentation c.c.:24V
LAMPE DULUX L 18W BLANC FROID; Tension, alimentation:58V; Puissance:18W; Flux lumineux:1200lm; Longueur:217mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Couleur:Cool White; Flux lumineux typique:1200lm; Intensité lumineuse, max..:1200lm; Longueur/hauteur:217mm; Nombre de broches:4
AMPOULE FLUO T5 14W BLANC FROID; Tension, alimentation:230V; Lamp Base Type:T5; Puissance:14W; Flux lumineux:1350lm; Longueur:550mm; Diamètre de l'ampoule:16mm; Température, couleur:4000K; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc froid; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Durée de vie:20000h; Durée de vie moyenne de la lampe:20000h; Flux lumineux typique:1350lm; Intensité lumineuse, max..:1350lm; Longueur/hauteur:550mm
LAMP, 12V, 2W; Tension, alimentation:12V; Puissance:2W; Tension:12V; Tension c.a.:12V
HALOGEN LAMP, 12V, 20W; Tension, alimentation:12V; Lamp Base Type:Bi-broche; Puissance:20W; Tension, alimentation c.c. max..:12V
LAMPE BA15D 230V; Tension, alimentation:230V; Lamp Base Type:BA15d; Puissance:5W; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Tension:230V; Tension c.a.:230V
LED MONTAGE AVANT 18-30VAC/DC. ROUGE; Tension, alimentation:30V; Puissance:260mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:55°C; Température d'utilisation min:-25°C
LED MONTAGE ARRIERE 18-30VAC/DC. BLANC; Tension, alimentation:30V; Puissance:260mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:55°C; Température d'utilisation min:-25°C
LED MONTAGE ARRIERE 18-30VAC/DC. VERT; Tension, alimentation:30V; Puissance:260mW; Courant:15mA; SVHC:No SVHC (19-Dec-2011); Couleur:vert; IP / NEMA Rating:IP20; Résistance de choc:>30; Taille en mm2 max.. du fil rigide:2.5mmË›; Taille en mm2 max.. du fil tressé:1.5mmË›; Température de fonctionnement max..:55°C; Température d'utilisation min:-25°C
TETE DE LAMPE TEMOIN BLANC BA9S; Lamp Base Type:BA9s; SVHC:No SVHC (19-Dec-2011); Couleur:Blanc; Diamètre de découpe panneau:22mm
LED T5.5 12V BLANC; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:T5.5; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température d
LED T6.8 24V BLANC; Lamp Base Type:Ampoule de téléphonie; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Taille de lampe:T-6 4/5; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:T6.8; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fonctionnement:-40°C +80°C; Tempé
LED A BAYONNETTE BA9 ROUGE; Lamp Base Type:BA9s; Couleur de LED:Rouge; Longueur d'onde typ.:660nm; Intensité lumineuse:2750mcd; Taille de lampe:4.8mm; Tension, alimentation:50V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:Rouge; Couleur, LED:Rouge; Courant, If moy.:10mA; Courant, If, intensité lumineuse:20mA; Courant, direct, If:10mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse ty
LED T5.5 24V VERT; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:6000mcd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Green; Couleur, LED:Vert; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:4.8mm; Dimension de la lentille:T5.5; Intensité lumineuse typique:6000mcd; Lo
PROJECTEUR PAR INFRAROUGE 150W; Angle de faisceau:140°; Longueur:180mm; Largeur:130mm; Profondeur:170mm; Couleur:Noir; Distance de détection max..:12m; IP / NEMA Rating:IP44; Largeur (externe):130mm; Longueur/hauteur:170mm; Profondeur:140mm; Puissance:150W; Tension, alimentation:230V; Tension, alimentation c.a. max..:240V; Tension, alimentation c.a. min:220V
AMPOULE POUR LAMPE TORCHE ANTIDEFLAGRANT; SVHC:No SVHC (19-Dec-2011); Tension:4.5V
LED BLEU; Longueur d'onde typ.:470nm; Intensité lumineuse:450mcd; Couleur:Blue; Couleur, LED:Bleu; Courant, direct, If:15mA; Intensité lumineuse typique:450mcd; Tension, Vf typ.:24V
LED VERT; Lamp Base Type:Bi-broche; Couleur de LED:Vert; Longueur d'onde typ.:560nm; Intensité lumineuse:33mcd; Taille de lampe:T-1; Tension, alimentation:2V; Courant:10mA; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:10mA; Dimension de la lentille:T-1; Intensité lumineuse typique:33mcd; Tension, Vf max..:2V; Tension, Vf typ.:2V; Tension, direct If:2V; Type de boîtier:Radial; Type de boîtier opto:Radial
LED JAUNE; Lamp Base Type:Bi-broche; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:52mcd; Taille de lampe:T-1; Tension, alimentation:2V; Courant:10mA; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:10mA; Dimension de la lentille:T-1; Intensité lumineuse typique:52mcd; Tension, Vf max..:2V; Tension, Vf typ.:2V; Tension, direct If:2V; Type de boîtier:Radial; Type de boîtier opto:Radial
AMPOULE POUR MAG-LITE 4 PILES PQ2; Tension, alimentation:4.8V; Durée de vie moyenne de la lampe:38h; Courant:0.6A; Durée de vie:38h; Quantité par paquet:2; Tension:4.8V
LED VERT; Lamp Base Type:BA9s; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:1000mcd; Tension, alimentation:24V; Courant:15mA; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:15mA; Intensité lumineuse typique:1000mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V; Tension, direct If:24V
LED JAUNE; Longueur d'onde typ.:592nm; Intensité lumineuse:250mcd; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:15mA; Intensité lumineuse typique:250mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V
LED BLANC; Lamp Base Type:Wedge, W2x4.6d; Couleur de LED:Blanc; Intensité lumineuse:400mcd; Tension, alimentation:24V; Courant:12mA; Couleur:White; Couleur, LED:Blanc; Courant, direct, If:12mA; Intensité lumineuse typique:400mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V; Tension, direct If:24V
LED ROUGE BASE T 4.5; Lamp Base Type:Ampoule de téléphonie, T4.5; Couleur de LED:Rouge; Longueur d'onde typ.:635nm; Intensité lumineuse:52mcd; Tension, alimentation:3V; Courant:10mA; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:10mA; Dimension de la lentille:T 4.5; Intensité lumineuse typique:52mcd; Tension, Vf max..:3V; Tension, Vf typ.:3V; Tension, direct If:3V
LED VERT BASE T 4.5; Lamp Base Type:Ampoule de téléphonie, T4.5; Couleur de LED:Vert; Longueur d'onde typ.:560nm; Intensité lumineuse:33mcd; Tension, alimentation:3V; Courant:10mA; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:10mA; Dimension de la lentille:T 4.5; Intensité lumineuse typique:33mcd; Tension, Vf max..:3V; Tension, Vf typ.:3V; Tension, direct If:3V
LAMPE ES63 75W 240V GU10 50; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:75W; Longueur:62mm; Diamètre, réflecteur:64mm; Température, couleur:2800K; Diamètre, extérieur:64mm; Durée de vie:2500h; Durée de vie moyenne de la lampe:2500h; Intensité lumineuse, max..:1000cd; Tension d'alimentation Vac:240V
TUBE FLUO MINIATURE T5 13W; Tension, alimentation:95V; Lamp Base Type:G5; Puissance:13W; Flux lumineux:880lm; Longueur:517mm; Diamètre de l'ampoule:16mm; Température, couleur:3500K; Couleur:White; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Flux lumineux typique:880lm; Intensité lumineuse, max..:880lm; Longueur/hauteur:525mm
TUBE FLUO T5 FHE 14W BLANC CHAUD; Tension, alimentation:82V; Lamp Base Type:T5; Puissance:14W; Longueur:550mm; Diamètre de l'ampoule:16mm; Température, couleur:3000K; Couleur:Blanc chaud; Couleur:Warm White; Courant:170mA; Diamètre, extérieur:16mm; Diamètre, tube fluorescent:16mm; Durée de vie:16000h; Durée de vie moyenne de la lampe:16000h; Longueur/hauteur:550mm
CAPSULE BULB FOR HM, 12V, 35W; Tension, alimentation:12V; Puissance:35W
AMPOULE POUR LAMPE TORCHE STYLO; Tension, alimentation:2.25V; Puissance:1.2W; MSCP:0.39; Durée de vie moyenne de la lampe:5h; SVHC:No SVHC (19-Dec-2011); Courant:0.25A; Durée de vie:5h; Tension:2.25V
TUBE A INCANDESCENCE 250W SON +LAMPE; Longueur:460mm; Largeur:360mm; Profondeur:132mm; IP / NEMA Rating:IP65; SVHC:No SVHC (19-Dec-2011); Couleur:Black; Lamp Base Type:GES / E40; Largeur (externe):360mm; Light Source:HPS 250W; Longueur/hauteur:460mm; Matière:Aluminium; Poids:9kg; Profondeur:132mm; Puissance:250W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
TUBE A INCANDESCENCE 400W MH +LAMPE; Longueur:460mm; Largeur:360mm; Profondeur:132mm; IP / NEMA Rating:IP65; SVHC:No SVHC (19-Dec-2011); Couleur:Black; Lamp Base Type:GES / E40; Largeur (externe):360mm; Light Source:Halogénures métalliques; Longueur/hauteur:460mm; Matière:Aluminium; Poids:9kg; Profondeur:132mm; Puissance:400W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
HALOGEN LAMP, 12V, 50W; Tension, alimentation:12V; Lamp Base Type:Bi-broche; Puissance:50W; Tension c.a.:12V
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:9.5mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Diamètre de découpe panneau:9.5mm; Diamètre, lentille:12mm; Epaisseur, panneau max..:2.8mm; Longueur/hauteur:59.2mm; Tension d'alimentation Vac:250V
AMPOULE 130V; Tension, alimentation:130V; Lamp Base Type:BA15d; Puissance:4.8W; Durée de vie moyenne de la lampe:2000h; SVHC:No SVHC (20-Jun-2011); Couleur:Clear; Dimension de la lentille:BA15d; Durée de vie:2000h; Tension:130V; Tension c.a.:130V
VOYANT NEON ROUGE; Tension, alimentation:130V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:12mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Diamètre de découpe panneau:12mm; Diamètre, lentille:13.6mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:38.2mm; Tension d'alimentation Vac:130V
VOYANT NEON ROUGE; Tension, alimentation:125V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:8mm; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Diamètre de découpe panneau:8mm; Longueur/hauteur:37.9mm; Tension d'alimentation Vac:125V
VOYANT NEON ROUGE; Tension, alimentation:125V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:6.4mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Fil; Couleur:Red; Diamètre de découpe panneau:6.4mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:125V
VOYANT NEON ROUGE; Tension, alimentation:240V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:6.4mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Fil; Couleur:Red; Diamètre de découpe panneau:6.4mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:240V
AMPOULE DE RECHANGE; Tension, alimentation:3V; Puissance:1.8W; Courant:600mA; SVHC:No SVHC (19-Dec-2011); Durée de vie:20h; Durée de vie moyenne de la lampe:20h; Intensité lumineuse, max..:8.8lm
LAMPE TORCHE STABEX MINI; SVHC:No SVHC (19-Dec-2011); Normes:EEx ia e IIC T4
LAMPE HALOGENE POUR 4715731; Tension, alimentation:4.5V; Puissance:2.4W; Intensité lumineuse, max..:35lm
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:8mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Borne souder; Couleur:rouge; Diamètre de découpe panneau:8mm; Longueur/hauteur:37.9mm; Tension d'alimentation Vac:250V
VOYANT NEON ROUGE; Tension, alimentation:250V; Lamp Base Type:Borne souder; Couleur:Rouge; Diamètre trou de fixation:13mm; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:rouge; Diamètre, extérieur:13mm; Diamètre, lentille:11.5mm; Epaisseur, panneau max..:4mm; Epaisseur, panneau min.:1.5mm; Longueur/hauteur:28.5mm; Tension d'alimentation Vac:250V
VOYANT A FILAMENT ROUGE; Taille de lampe:6.7mm; Tension, alimentation:6V; Courant:40mA; SVHC:No SVHC (19-Dec-2011); Couleur:rouge; Diamètre de découpe panneau:6.4mm; Dimension de la lentille:6.7mm; Epaisseur, panneau max..:3.5mm; Epaisseur, panneau min.:0.5mm; Longueur/hauteur:30mm; Température de fonctionnement max..:70°C; Tension d'alimentation Vac:6V
BLOC D'ECLAIRAGE DOUBLE PL9 TRANSP; Longueur:240mm; Largeur:117mm; Profondeur:140mm; Couleur:Clear; Tension, alimentation:230V
INDICATEUR NEON AMBRE; Tension, alimentation:230V; Lamp Base Type:Borne souder; Couleur:Ambre; Diamètre trou de fixation:8mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Borne souder; Couleur:Ambre; Couleur, lentilles:Ambre; Diamètre de découpe panneau:8mm; Diamètre de découpe panneau:8.0mm; Diamètre, extérieur:9.5mm; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.8mm; Longueur:37mm; Longueur/hauteur:37mm; Tension, alimentation c.a. max..:250V; Tension, alimentation c.a. m
INDICATEUR NEON ROUGE; Tension, alimentation:230V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:9mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Rouge; Couleur, lentilles:Rouge; Diamètre de découpe panneau:9mm; Diamètre de découpe panneau:9.0mm; Diamètre, extérieur:10.0mm; Durée de vie:25000h; Durée de vie moyenne de la lampe:25000h; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.8mm; Longueur:26mm; Longueur cordon:200mm; Longueur/hauteur:26mm; Ten
INDICATEUR NEON AMBRE; Tension, alimentation:230V; Lamp Base Type:Fil; Couleur:Ambre; Diamètre trou de fixation:9mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Ambre; Couleur, lentilles:Ambre; Diamètre de découpe panneau:9mm; Diamètre de découpe panneau:9.0mm; Diamètre, extérieur:10.0mm; Durée de vie:25000h; Durée de vie moyenne de la lampe:25000h; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.8mm; Longueur:26mm; Longueur cordon:200mm; Longueur/hauteur:26mm; Ten
LAMPE D'INSPECTION 11W/110V; Tension, alimentation:110V; Lamp Base Type:G23; Puissance:11W; Longueur:480mm; Type de fiche d'alimentation:UK; SVHC:No SVHC (19-Dec-2011); Longueur (max..):48cm; Longueur/hauteur:48cm; Tension d'alimentation Vac:110V
BLOC D'ECLAIRAGE B22 100W ROUGE; Light Source:BC GLS 100W; Longueur:240mm; Largeur:117mm; Profondeur:140mm; Couleur:Red; Puissance:100W; Tension, alimentation:230V
VOYANT NEON ROUGE; Tension, alimentation:240V; Lamp Base Type:Fil; Couleur:Rouge; Diamètre trou de fixation:10mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Base Type:Fil; Couleur:rouge; Diamètre de découpe panneau:10mm; Epaisseur, panneau max..:2mm; Longueur/hauteur:31mm; Température de fonctionnement max..:180°C
INDICATEUR NEON VERT; Tension, alimentation:230V; Lamp Base Type:Fil; Couleur:Vert; Diamètre trou de fixation:9mm; Courant:20mA; SVHC:No SVHC (19-Dec-2011); Base Type:Fil; Couleur:Vert; Couleur, lentilles:Vert; Diamètre de découpe panneau:9mm; Diamètre de découpe panneau:9.0mm; Diamètre, extérieur:10.0mm; Durée de vie:25000h; Durée de vie moyenne de la lampe:25000h; Epaisseur, panneau max..:2.5mm; Epaisseur, panneau min.:0.8mm; Longueur:26mm; Longueur cordon:200mm; Longueur/hauteur:26mm; Tension
TUBE FLUORESCENT; Tension, alimentation:230V; Puissance:28W; SVHC:No SVHC (19-Dec-2011); Light Source:Fluorescente
LAMPE BA15D 7W 230V PAQUET DE 10; Tension, alimentation:230V; Lamp Base Type:BA15d; Puissance:7W; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Quantité par paquet:10; Taille:BA15d; Tension:230V; Tension c.a.:230V
LED T5.5 24V BLANC; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:T5.5; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fonctionneme
LED 24V BLANC; Lamp Base Type:E10; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Puissance:625mW; Taille de lampe:4.8mm; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fonctionnement:-40°C +80°C; Température
LED BA15D 24V BLANC; Lamp Base Type:BA15d; Couleur de LED:Blanc; Température de couleur proximale:8000K; Intensité lumineuse:3000mcd; Taille de lampe:16mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:15°; Angle, vision:30°; Couleur, LED:Blanc; Courant, If moy.:25mA; Courant, direct, If:25mA; Dimension de la lentille:16mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Nombre de LED:6; Température de fonc
LED BA15D 28V BLANC; Lamp Base Type:BA15d; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Puissance:225mW; Taille de lampe:16mm; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:15°; Angle, vision:30°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:17mA; Courant, direct, If:17mA; Dimension de la lentille:16mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Nombre de LED:6; Température de foncti
LED A BAYONNETTE BA9 BLEU; Lamp Base Type:BA9s; Couleur de LED:Bleu; Longueur d'onde typ.:470nm; Intensité lumineuse:2000mcd; Puissance:625mW; Taille de lampe:4.8mm; Tension, alimentation:48V; Courant:10mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:Bleu; Couleur, LED:Bleu; Courant, If moy.:10mA; Courant, If, intensité lumineuse:20mA; Courant, direct, If:10mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité
LED MIDGET ROUGE; Lamp Base Type:Midget Groove; Couleur de LED:Rouge; Longueur d'onde typ.:660nm; Intensité lumineuse:2750mcd; Taille de lampe:4.8mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Rouge; Couleur, LED:Rouge; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:5.6mm; Dimension de la lentille:4.8mm; Intensité lumineuse typique:2750mcd; Longueur d'onde, cr
LED T6.8 24V ROUGE; Lamp Base Type:Ampoule de téléphonie; Couleur de LED:Rouge; Longueur d'onde typ.:660nm; Intensité lumineuse:2750mcd; Taille de lampe:T-6 4/5; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Red; Couleur, LED:Rouge; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:7.0mm; Dimension de la lentille:T6.8; Intensité lumineuse typique:2750mcd; Longueur d'onde, crête:6
LED T6.8 24V JAUNE; Lamp Base Type:Ampoule de téléphonie; Couleur de LED:Jaune; Longueur d'onde typ.:590nm; Intensité lumineuse:4500mcd; Taille de lampe:T-6 4/5; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Yellow; Couleur, LED:Jaune; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:7.0mm; Dimension de la lentille:T6.8; Intensité lumineuse typique:4500mcd; Longueur d'onde, crêt
LED ROUGE; Longueur d'onde typ.:630nm; Intensité lumineuse:70mcd; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:12mA; Intensité lumineuse typique:70mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V
LED VERT; Lamp Base Type:Wedge, W2x4.6d; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:600mcd; Tension, alimentation:24V; Courant:12mA; Couleur:Green; Couleur, LED:Vert; Courant, direct, If:12mA; Intensité lumineuse typique:600mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V; Tension, direct If:24V
LED BLEU; Longueur d'onde typ.:470nm; Intensité lumineuse:300mcd; Couleur:Blue; Couleur, LED:Bleu; Courant, direct, If:12mA; Intensité lumineuse typique:300mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V
LED ROUGE; Lamp Base Type:Bi-broche; Couleur de LED:Rouge; Longueur d'onde typ.:635nm; Intensité lumineuse:52mcd; Taille de lampe:T-1; Tension, alimentation:2V; Courant:10mA; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:10mA; Dimension de la lentille:T-1; Intensité lumineuse typique:52mcd; Tension, Vf max..:2V; Tension, Vf typ.:2V; Tension, direct If:2V; Type de boîtier:Radial; Type de boîtier opto:Radial
LED JAUNE BASE T 4.5; Lamp Base Type:Ampoule de téléphonie, T4.5; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:52mcd; Tension, alimentation:3V; Courant:10mA; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:10mA; Dimension de la lentille:T 4.5; Intensité lumineuse typique:52mcd; Tension, Vf max..:3V; Tension, Vf typ.:3V; Tension, direct If:3V
LED MIDGET 12V BLANC; Lamp Base Type:Midget Groove; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Taille de lampe:4.8mm; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fonctionnement:-40°C +80°C
LED MIDGET 24V BLANC; Lamp Base Type:Midget Groove; Couleur de LED:Blanc; Température de couleur proximale:8000K; Intensité lumineuse:3000mcd; Taille de lampe:4.8mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Températu
LED MIDGET 24V BLANC; Lamp Base Type:Midget Flange; Couleur de LED:Blanc; Température de couleur proximale:8000K; Intensité lumineuse:3000mcd; Taille de lampe:4.8mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Températu
LED BA9 28V BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc froid; Intensité lumineuse:14000mcd; Puissance:625mW; Taille de lampe:4.8mm; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:14000mcd; Température de fonctionnement:-40°C
LED BA9 48V BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Température de couleur proximale:8000K; Intensité lumineuse:3000mcd; Puissance:625mW; Taille de lampe:4.8mm; Tension, alimentation:48V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:12mA; Courant, direct, If:12mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fon
LED 12V BLANC; Lamp Base Type:E10; Couleur de LED:Blanc froid; Intensité lumineuse:3000mcd; Puissance:625mW; Taille de lampe:4.8mm; Tension, alimentation:12V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:60°; Angle, vision:120°; Couleur:White; Couleur, LED:Blanc; Courant, If moy.:20mA; Courant, direct, If:20mA; Dimension de la lentille:4.8mm; Durée de vie:100000h; Intensité lumineuse typique:3000mcd; Température de fonctionnement:-40°C +80°C
LED T1 BI-PIN 28V ROUGE; Lamp Base Type:Bi-broche; Couleur de LED:Rouge; Longueur d'onde typ.:630nm; Intensité lumineuse:14mcd; Puissance:500mW; Taille de lampe:T-1; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:12mA; Courant, fonctionnement c.a.:12mA; Diamètre, extérieur:4.2mm; Dimension de la lentille:T1; Durée de vie:60000h; Intensité lumi
LED T1 BI-PIN 28V JAUNE; Lamp Base Type:Bi-broche; Couleur de LED:Jaune; Longueur d'onde typ.:585nm; Intensité lumineuse:18mcd; Puissance:500mW; Taille de lampe:T-1; Tension, alimentation:28V; Courant:20mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Yellow; Couleur, LED:Jaune; Courant, direct, If:12mA; Courant, fonctionnement c.a.:12mA; Diamètre, extérieur:4.2mm; Dimension de la lentille:T1; Durée de vie:60000h; Intensité l
LED A BAYONNETTE BA9 ROUGE; Lamp Base Type:BA9s; Couleur de LED:Rouge; Longueur d'onde typ.:660nm; Intensité lumineuse:3000mcd; Puissance:625mW; Taille de lampe:4.6mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Red; Couleur, LED:Rouge; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:9.2mm; Dimension de la lentille:4.6mm; Intensité lumineuse typique:3000mcd; Lon
LED A BAYONNETTE BA9 JAUNE; Lamp Base Type:BA9; Couleur de LED:Jaune; Longueur d'onde typ.:590nm; Intensité lumineuse:2500mcd; Puissance:625mW; Taille de lampe:4.6mm; Tension, alimentation:24V; Courant:20mA; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Yellow; Couleur, LED:Jaune; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:9.2mm; Dimension de la lentille:4.6mm; Intensité lumineuse typique:2500mcd; L
LED T5.5 24V ROUGE; Lamp Base Type:Ampoule de téléphonie, T5,5; Couleur de LED:Rouge; Longueur d'onde typ.:660nm; Intensité lumineuse:2750mcd; Puissance:500mW; Taille de lampe:T-5 1/2; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Red; Couleur, LED:Rouge; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:4.8mm; Dimension de la lentille:T5.5; Intensité lumineuse typique:2750mcd; L
LED ROUGE; Longueur d'onde typ.:621nm; Intensité lumineuse:250mcd; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:15mA; Intensité lumineuse typique:250mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V
LED BLEU; Longueur d'onde typ.:470nm; Intensité lumineuse:450mcd; Couleur:Blue; Couleur, LED:Bleu; Courant, direct, If:15mA; Intensité lumineuse typique:450mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V
LED BLANC; Lamp Base Type:BA9s; Couleur de LED:Blanc; Intensité lumineuse:600mcd; Tension, alimentation:24V; Courant:15mA; Couleur:White; Couleur, LED:Blanc; Courant, direct, If:15mA; Intensité lumineuse typique:600mcd; Tension, Vf max..:24V; Tension, Vf typ.:24V; Tension, direct If:24V
BLOC DE SECURITE GRIS; Light Source:BC GLS 100W; Longueur:235mm; Largeur:117mm; Profondeur:102mm; SVHC:No SVHC (19-Dec-2011); Couleur:Gris; Hauteur:235mm; IP / NEMA Rating:IP65; Lamp Base Type:BC 100W; Matière:Metal Base/Polycarbonate Diffuser; Puissance:100W; Tension, alimentation:230V; Tension d'alimentation Vac:230V
AMPOULE POUR MC 1 RECHARGEABLE METAL D; Puissance:5.5W; SVHC:No SVHC (19-Dec-2011); Courant, sortie:1A; Tension c.a.:5.5V
AMPOULE CAPSULE 12V 50W GY6.35; Tension, alimentation:12V; Lamp Base Type:GY6,35; Puissance:50W; Longueur:44mm; Base Type:GY6,35; Couleur:Clear; Dimension de la lentille:GY6.35; Durée de vie:8000h; Durée de vie moyenne de la lampe:8000h; Taille de lampe:GY6.35; Tension, alimentation c.c.:12V
BLOC DE SECURITE CHROME; Longueur:410mm; Largeur:125mm; Profondeur:90mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:Polished Chrome; Lamp Base Type:Fluorescent T5 8W; Matière:Steel; Tension, alimentation:240V
BLOC DE SECURITE BLANC; Longueur:410mm; Largeur:125mm; Profondeur:90mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:White; Lamp Base Type:Fluorescent T5 8W; Matière:Steel; Tension, alimentation:240V
MODULE 0.72W. 9 LED; Largeur:35mm; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:0.72W; Largeur (externe):35mm; Longueur/hauteur:270mm; Puissance:720mW
BLOC DE SECURITE A LED. BLANC; Longueur:545mm; Profondeur:370mm; IP / NEMA Rating:IP20; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Couleur:Blanc; Distance, visible max..:30m; Durée de vie (fonctionnement):3 Heures; Matière:Aluminium; Tension, batterie:3.6V
BLOC INDICATEUR; SVHC:No SVHC (19-Dec-2011); Diamètre de découpe panneau:16mm; Profondeur:35mm
INDICATEUR CORPS 18X24; Taille de lampe:T-1 3/4; Lamp Base Type:Midget Groove; SVHC:No SVHC (19-Dec-2011); Approval Bodies:CSA / SEV / UL / VDE; Diamètre de découpe panneau:16mm; Dimension de la lentille:T-1 3/4; Largeur (externe):24mm; Longueur/hauteur:18mm; Profondeur, derrière panneau:23.5mm
AMPOULE DE REMPLACEMENT TUBE XENON; Tension, alimentation:230V; Puissance:15W
CORPS POUR INDICATEUR; Taille de lampe:T-1 3/4; Tension, alimentation:24V; Courant:6A; SVHC:No SVHC (19-Dec-2011); Approval Bodies:CSA / SEV / UL / VDE; Diamètre de découpe panneau:22.5mm; Dimension de la lentille:T-1 3/4; IP / NEMA Rating:IP65; Longueur, axe:50mm; Profondeur, derrière panneau:48mm
LED T6.8 24V VERT; Lamp Base Type:Ampoule de téléphonie; Couleur de LED:Vert; Longueur d'onde typ.:525nm; Intensité lumineuse:6000mcd; Taille de lampe:T-6 4/5; Tension, alimentation:24V; Durée de vie moyenne de la lampe:100000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:42.5°; Angle, vision:85°; Couleur:Green; Couleur, LED:Vert; Courant, If moy.:20mA; Courant, direct, If:20mA; Diamètre, extérieur:7.0mm; Dimension de la lentille:T6.8; Intensité lumineuse typique:6000mcd; Longueur d'onde, crête:52
INDICATEUR CORPS 18X18; Taille de lampe:T-1 3/4; Lamp Base Type:Midget Groove; SVHC:No SVHC (19-Dec-2011); Diamètre de découpe panneau:16mm; Dimension de la lentille:T-1 3/4; Largeur (externe):18mm; Longueur/hauteur:18mm; Profondeur, derrière panneau:23.5mm
BLOC D'ECLAIRAGE POLY. GLS 100W; Light Source:BC GLS 100W; Longueur:240mm; Largeur:117mm; Profondeur:140mm; Couleur:Clear; Puissance:100W; Tension, alimentation:230V
LED MIN GROOVE 28V ROUGE; Lamp Base Type:Midget Groove; Couleur de LED:Rouge; Longueur d'onde typ.:620nm; Intensité lumineuse:36mcd; Taille de lampe:T-1 3/4; Tension, alimentation:28V; Courant:14mA; Durée de vie moyenne de la lampe:60000h; SVHC:No SVHC (19-Dec-2011); Angle, moitié:70°; Angle, vision:140°; Couleur:Red; Couleur, LED:Rouge; Courant, direct, If:14mA; Courant, fonctionnement c.a.:14mA; Diamètre, extérieur:5.85mm; Dimension de la lentille:T-1 3/4; Durée de vie:60000h; Intensité lumine
LAMPE T3.1/4 6.3V 1.575W; Tension, alimentation:6.3V; Lamp Base Type:Culot Wedge; Taille de lampe:T-3 1/4; Puissance:1.57W; MSCP:0.65; Durée de vie moyenne de la lampe:10000h; SVHC:No SVHC (19-Dec-2011); Courant:0.25A; Dimension de la lentille:T-1 3/4; Durée de vie:10000h; Emission lumineuse, totale:8.2lm; Longueur/hauteur:26.8mm; Tension:6.3V; Tension c.a.:6.3V
AMPOULE GU10 XENON 35W; Tension, alimentation:240V; Puissance:35W; Longueur:50mm; Lamp Base Type:GU10; Couleur:Clear; Couleur:Clair; Diamètre, extérieur:50mm; Dimension de la lentille:GU10; Durée de vie:5000h; Durée de vie moyenne de la lampe:5000h; Longueur/hauteur:50mm; Tension d'alimentation Vac:240V
BLOC GU10 240V 35W PROLITE TRANSPARENT; Tension, alimentation:240V; Lamp Base Type:GU10; Puissance:35W; Longueur:56mm; Diamètre, réflecteur:50mm; Diamètre, extérieur:50mm; Intensité lumineuse, max..:600cd; Tension d'alimentation Vac:240V
LAMPE T8 18W 600MM 6500K; Tension, alimentation:240V; Lamp Base Type:G13; Puissance:18W; Flux lumineux:1300lm; Longueur:600mm; Diamètre de l'ampoule:26mm; Température, couleur:6500K; SVHC:No SVHC (20-Jun-2011); Couleur:Blanc froid; Couleur:Cool White; Diamètre, extérieur:26mm; Diamètre, tube fluorescent:26mm; Durée de vie:17500h; Durée de vie moyenne de la lampe:17500h; Flux lumineux typique:1300lm; Intensité lumineuse, max..:1300lm; Longueur/hauteur:600mm; Tension d'alimentation Vac:240V
AMPOULE DOUBLE CULOTS 240V. 300W. 118MM; Tension, alimentation:240V; Lamp Base Type:R7s; Puissance:300W; Longueur:118mm; Température, couleur:2900K; Couleur:Clear; Durée de vie:2000h; Durée de vie moyenne de la lampe:2000h; Tension d'alimentation Vac:240V
MODULE 1.2W. 15 LED; Largeur:35mm; SVHC:No SVHC (19-Dec-2011); Consommation de puissance:1.2W; Largeur (externe):35mm; Longueur/hauteur:395mm; Puissance:1.2W
MODULE 2.15W. 27 LED; Largeur:35mm; SVHC:No SVHC (19-Dec-2011); Approval Bodies:BS / EN; Consommation de puissance:2.15W; Couleur:Blanc; IP / NEMA Rating:IP20; Largeur (externe):35mm; Longueur/hauteur:620mm; Matière:Polycarbonate; Puissance:2.15W
STRIPLIGHT, LED, 400MM COLD CLEAR; Light Source:40 x LED; Longueur:420mm; Largeur:20mm; Profondeur:44mm; Couleur:Transparent; Couleur:Blanc froid; Couleur de LED:Blanc; Durée de vie moyenne de la lampe:50000h; Largeur (externe):20mm; Longueur/hauteur:420mm; Profondeur:44mm; Puissance:6VA; Taille de lampe:T-4; Température de couleur proximale:7500K; Tension, alimentation:230V
PROJECTEUR LED; Longueur:306mm; Largeur:2583mm; Profondeur:457mm; Largeur (externe):258mm; Light Source:LED
BANDE LUMINEUSE A LED 24-48VDC. AIMANT; Lamp Base Type:Vis; Puissance:5W; Light Source:LED; Longueur:351mm; Diamètre, lentille:32mm; SVHC:No SVHC (20-Jun-2011)
SUPPORT FLUORESCENT T5. 28W; Tension, alimentation:230V; Lamp Base Type:Fluorescent T5 1 150 mm 28W; Puissance:28W; Longueur:1.2m; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011)
LAMPE BA15D 230V; Tension, alimentation:230V; Lamp Base Type:BA15d; Puissance:10W; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Tension:230V; Tension c.a.:230V
SUPPORT FLUORESCENT T5. 21W; Tension, alimentation:230V; Lamp Base Type:T5 Fluorescent 850 mm 21W; Puissance:21W; Longueur:900mm; Température, couleur:3500K; SVHC:No SVHC (19-Dec-2011)
LAMPE BA15D 7W 12V PAQUET DE 10; Tension, alimentation:12V; Lamp Base Type:BA15d; Puissance:7W; SVHC:No SVHC (19-Dec-2011); Couleur:Clear; Quantité par paquet:10; Taille:BA15d; Tension:12V; Tension c.a.:12V
