MICROCHIP 51295f_cn.pdf - PDF - Farnell Element 14

MICROCHIP 51295f_cn.pdf - PDF - Farnell Element 14 - Revenir à l'accueil

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Documents PDF :

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[TXT] Analog-Devices-Basic..> 08-Sep-2014 17:49  1.9M  
[TXT] Analog-Devices-Compl..> 08-Sep-2014 17:38  2.0M  
[TXT] Analog-Devices-Convo..> 09-Sep-2014 08:26  2.1M  
[TXT] Analog-Devices-Convo..> 09-Sep-2014 08:25  2.2M  
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[TXT] Farnell-CIRRUS-LOGIC..> 10-Mar-2014 17:20  2.1M  
[TXT] Farnell-CLASS 1-or-2..> 22-Jul-2014 12:30  4.7M  
[TXT] Farnell-CLRC632-NXP-..> 20-Dec-2014 10:22  2.6M  
[TXT] Farnell-CRC-HANDCLEA..> 07-Jul-2014 19:46  1.2M  
[TXT] Farnell-CS5532-34-BS..> 01-Apr-2014 07:39  3.5M  
[TXT] Farnell-Cannon-ZD-PD..> 11-Mar-2014 08:13  2.8M  
[TXT] Farnell-Ceramic-tran..> 14-Jun-2014 18:19  3.4M  
[TXT] Farnell-Circuit-Impr..> 25-Jul-2014 12:22  3.1M  
[TXT] Farnell-Circuit-Note..> 26-Mar-2014 18:00  2.8M  
[TXT] Farnell-Circuit-Note..> 26-Mar-2014 18:00  2.8M  
[TXT] Farnell-Cles-electro..> 21-Mar-2014 08:13  3.9M  
[TXT] Farnell-Clipper-Seri..> 08-Jul-2014 18:48  2.8M  
[TXT] Farnell-Compensating..> 09-Sep-2014 08:16  2.6M  
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[TXT] Farnell-Conception-d..> 11-Mar-2014 07:49  2.4M  
[TXT] Farnell-Connectors-N..> 14-Jun-2014 18:12  2.1M  
[TXT] Farnell-Construction..> 14-Jun-2014 18:25  2.5M  
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[TXT] Farnell-Crucial-Ball..> 20-Dec-2014 16:48  8.0M  
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[TXT] Farnell-Cube-3D-Prin..> 18-Jul-2014 17:02  2.5M  
[TXT] Farnell-Current-Tran..> 26-Mar-2014 17:58  2.7M  
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[TXT] Farnell-DAC8143-Data..> 18-Jul-2014 16:59  1.5M  
[TXT] Farnell-DC-DC-Conver..> 15-Jul-2014 16:48  781K  
[TXT] Farnell-DC-Fan-type-..> 14-Jun-2014 09:48  2.5M  
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[TXT] Farnell-DG411-DG412-..> 07-Jul-2014 19:47  1.0M  
[TXT] Farnell-DP83846A-DsP..> 18-Jul-2014 16:55  1.5M  
[TXT] Farnell-DS3231-DS-PD..> 18-Jul-2014 16:57  2.5M  
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[TXT] Farnell-Davum-TMC-PD..> 14-Jun-2014 18:27  2.4M  
[TXT] Farnell-De-la-puissa..> 29-Mar-2014 11:10  3.3M  
[TXT] Farnell-Decapant-KF-..> 07-Jul-2014 19:45  1.2M  
[TXT] Farnell-Directive-re..> 25-Mar-2014 08:16  3.0M  
[TXT] Farnell-Documentatio..> 14-Jun-2014 18:26  2.5M  
[TXT] Farnell-Download-dat..> 16-Jul-2014 09:02  2.2M  
[TXT] Farnell-Download-dat..> 13-Jun-2014 18:40  1.8M  
[TXT] Farnell-Drawing-Octo..> 09-Jul-2015 11:13  2.4M  
[TXT] Farnell-Dremel-Exper..> 22-Jul-2014 12:34  1.6M  
[TXT] Farnell-Dual-MOSFET-..> 28-Jul-2014 17:41  2.8M  
[TXT] Farnell-ECO-Series-T..> 20-Mar-2014 08:14  2.5M  
[TXT] Farnell-EE-SPX303N-4..> 15-Jul-2014 17:06  969K  
[TXT] Farnell-ELMA-PDF.htm    29-Mar-2014 11:13  3.3M  
[TXT] Farnell-EMC1182-PDF.htm 25-Mar-2014 08:17  3.0M  
[TXT] Farnell-EPCOS-173438..> 04-Jul-2014 10:43  3.3M  
[TXT] Farnell-EPCOS-Sample..> 11-Mar-2014 07:53  2.2M  
[TXT] Farnell-ES1F-ES1J-fi..> 06-Jul-2014 10:04  867K  
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[TXT] Farnell-ESM6045DV-ST..> 13-Oct-2014 07:06  850K  
[TXT] Farnell-ESMT-M52D323..> 20-Dec-2014 16:50  7.6M  
[TXT] Farnell-Ed.081002-DA..> 19-Mar-2014 18:02  2.5M  
[TXT] Farnell-Encodeur-USB..> 08-Jul-2014 18:56  2.0M  
[TXT] Farnell-Evaluating-t..> 22-Jul-2014 12:28  4.9M  
[TXT] Farnell-Everything-Y..> 11-Oct-2014 12:05  1.5M  
[TXT] Farnell-Excalibur-Hi..> 28-Jul-2014 17:10  2.4M  
[TXT] Farnell-Excalibur-Hi..> 28-Jul-2014 17:10  2.4M  
[TXT] Farnell-Explorer-16-..> 29-Jul-2014 10:31  1.3M  
[TXT] Farnell-F28069-Picco..> 14-Jun-2014 18:14  2.0M  
[TXT] Farnell-F42202-PDF.htm  19-Mar-2014 18:00  2.5M  
[TXT] Farnell-FAN6756-Fair..> 06-Jul-2014 10:04  850K  
[TXT] Farnell-FDC2512-Fair..> 06-Jul-2014 10:03  886K  
[TXT] Farnell-FDS-ITW-Spra..> 14-Jun-2014 18:22  3.3M  
[TXT] Farnell-FDV301N-Digi..> 06-Jul-2014 10:03  886K  
[TXT] Farnell-FICHE-DE-DON..> 10-Mar-2014 16:17  1.6M  
[TXT] Farnell-FSDM0565RB-F..> 09-Jul-2015 11:23  1.2M  
[TXT] Farnell-Fairchild-2N..> 09-Jul-2015 11:20  1.8M  
[TXT] Farnell-Fairchild-FD..> 09-Jul-2015 11:21  1.7M  
[TXT] Farnell-Fast-Charge-..> 28-Jul-2014 17:12  6.4M  
[TXT] Farnell-Fastrack-Sup..> 23-Jun-2014 10:25  3.3M  
[TXT] Farnell-Ferric-Chlor..> 29-Mar-2014 11:14  2.8M  
[TXT] Farnell-Fiche-de-don..> 14-Jun-2014 09:47  2.5M  
[TXT] Farnell-Fiche-de-don..> 14-Jun-2014 18:26  2.5M  
[TXT] Farnell-Fluke-1730-E..> 14-Jun-2014 18:23  2.5M  
[TXT] Farnell-Fluke-Ti400-..> 20-Dec-2014 16:48  8.0M  
[TXT] Farnell-Full-Datashe..> 15-Jul-2014 17:08  951K  
[TXT] Farnell-Full-Datashe..> 15-Jul-2014 16:47  803K  
[TXT] Farnell-GALVA-A-FROI..> 26-Mar-2014 17:56  2.7M  
[TXT] Farnell-GALVA-MAT-Re..> 26-Mar-2014 17:57  2.7M  
[TXT] Farnell-GN-RELAYS-AG..> 20-Mar-2014 08:11  2.6M  
[TXT] Farnell-Gertboard-Us..> 29-Jul-2014 10:30  1.4M  
[TXT] Farnell-HC49-4H-Crys..> 14-Jun-2014 18:20  3.3M  
[TXT] Farnell-HEF4052B-NXP..> 09-Jul-2015 11:18  2.0M  
[TXT] Farnell-HFE1600-Data..> 14-Jun-2014 18:22  3.3M  
[TXT] Farnell-HI-70300-Sol..> 14-Jun-2014 18:27  2.4M  
[TXT] Farnell-HIP4081A-Int..> 07-Jul-2014 19:47  1.0M  
[TXT] Farnell-HUNTSMAN-Adv..> 10-Mar-2014 16:17  1.7M  
[TXT] Farnell-Haute-vitess..> 20-Dec-2014 18:50  2.4M  
[TXT] Farnell-Hex-Inverter..> 29-Jul-2014 10:31  875K  
[TXT] Farnell-High-precisi..> 08-Jul-2014 18:51  2.3M  
[TXT] Farnell-ICM7228-Inte..> 07-Jul-2014 19:46  1.1M  
[TXT] Farnell-IP4251_52_53..> 20-Dec-2014 09:51  1.6M  
[TXT] Farnell-IP4252CZ16-8..> 13-Jun-2014 18:41  1.7M  
[TXT] Farnell-ISL6251-ISL6..> 07-Jul-2014 19:47  1.1M  
[TXT] Farnell-Instructions..> 19-Mar-2014 18:01  2.5M  
[TXT] Farnell-Jeu-multi-la..> 25-Jul-2014 12:23  3.0M  
[TXT] Farnell-KA3525A-SMPS..> 09-Jul-2015 11:23  1.2M  
[TXT] Farnell-KSZ8851SNL-S..> 23-Jun-2014 10:28  2.1M  
[TXT] Farnell-Keyboard-Mou..> 22-Jul-2014 12:27  5.9M  
[TXT] Farnell-L-efficacite..> 11-Mar-2014 07:52  2.3M  
[TXT] Farnell-L78-Positive..> 13-Oct-2014 07:04  1.8M  
[TXT] Farnell-L78-STMicroe..> 11-Oct-2014 15:49  1.6M  
[TXT] Farnell-L78S-STMicro..> 22-Jul-2014 12:32  1.6M  
[TXT] Farnell-L293B-STMicr..> 11-Oct-2014 15:49  1.7M  
[TXT] Farnell-L293d-Texas-..> 08-Jul-2014 18:53  2.2M  
[TXT] Farnell-L4978-STMicr..> 13-Oct-2014 07:07  783K  
[TXT] Farnell-L6384E-STMic..> 13-Oct-2014 07:02  1.9M  
[TXT] Farnell-L6562-STMicr..> 13-Oct-2014 07:07  754K  
[TXT] Farnell-LCW-CQ7P.CC-..> 25-Mar-2014 08:19  3.2M  
[TXT] Farnell-LD-WSECO16-P..> 25-Jul-2014 12:22  3.1M  
[TXT] Farnell-LF351-STMicr..> 11-Oct-2014 15:49  1.7M  
[TXT] Farnell-LM3S6952-Mic..> 22-Jul-2014 12:27  5.9M  
[TXT] Farnell-LM19-Texas-I..> 18-Jul-2014 17:00  1.2M  
[TXT] Farnell-LM139-LM239-..> 13-Oct-2014 07:07  771K  
[TXT] Farnell-LM158-LM258-..> 11-Oct-2014 15:49  1.6M  
[TXT] Farnell-LM217-LM317-..> 13-Oct-2014 07:04  1.7M  
[TXT] Farnell-LM324-Texas-..> 29-Jul-2014 10:32  1.5M  
[TXT] Farnell-LM350-STMicr..> 13-Oct-2014 07:03  1.8M  
[TXT] Farnell-LM386-Low-Vo..> 29-Jul-2014 10:32  1.5M  
[TXT] Farnell-LM555-Timer-..> 08-Jul-2014 18:53  2.2M  
[TXT] Farnell-LM2904-LM290..> 13-Oct-2014 07:04  1.7M  
[TXT] Farnell-LM7805-Fairc..> 09-Sep-2014 08:13  2.7M  
[TXT] Farnell-LME49725-Pow..> 14-Jun-2014 09:49  2.5M  
[TXT] Farnell-LMH6518-Texa..> 18-Jul-2014 16:59  1.3M  
[TXT] Farnell-LMP91051-Use..> 29-Jul-2014 10:30  1.4M  
[TXT] Farnell-LMT88-2.4V-1..> 28-Jul-2014 17:42  2.8M  
[TXT] Farnell-LOCTITE-542-..> 25-Mar-2014 08:15  3.0M  
[TXT] Farnell-LOCTITE-3463..> 25-Mar-2014 08:19  3.0M  
[TXT] Farnell-LPC11U3x-32-..> 16-Jul-2014 09:01  2.4M  
[TXT] Farnell-LPC81xM-32-b..> 16-Jul-2014 09:02  2.0M  
[TXT] Farnell-LPC81xM-NXP-..> 20-Dec-2014 10:26  1.2M  
[TXT] Farnell-LPC178x-7x-N..> 20-Dec-2014 10:21  1.6M  
[TXT] Farnell-LPC408x-7x 3..> 16-Jul-2014 09:03  1.6M  
[TXT] Farnell-LPC1769-68-6..> 16-Jul-2014 09:02  1.9M  
[TXT] Farnell-LPC1769-68-6..> 20-Dec-2014 10:06  2.2M  
[TXT] Farnell-LPC2141-42-4..> 09-Jul-2015 11:23  1.5M  
[TXT] Farnell-LPC2364-65-6..> 09-Jul-2015 11:23  1.4M  
[TXT] Farnell-LPC2468-NXP-..> 09-Jul-2015 11:23  1.6M  
[TXT] Farnell-LPC3220-30-4..> 16-Jul-2014 09:02  2.2M  
[TXT] Farnell-LPC4350-30-2..> 20-Dec-2014 10:21  1.4M  
[TXT] Farnell-LQ-RELAYS-AL..> 06-Jul-2014 10:02  924K  
[TXT] Farnell-LT1961-Linea..> 18-Jul-2014 16:58  1.6M  
[TXT] Farnell-LT3757-Linea..> 18-Jul-2014 16:58  1.6M  
[TXT] Farnell-LT6233-Linea..> 18-Jul-2014 16:56  1.3M  
[TXT] Farnell-LUMINARY-MIC..> 22-Jul-2014 12:31  3.6M  
[TXT] Farnell-LUXEON-Guide..> 11-Mar-2014 07:52  2.3M  
[TXT] Farnell-Leaded-Trans..> 23-Jun-2014 10:26  3.2M  
[TXT] Farnell-Les-derniers..> 11-Mar-2014 07:50  2.3M  
[TXT] Farnell-Loctite3455-..> 25-Mar-2014 08:16  3.0M  
[TXT] Farnell-Low-Noise-24..> 06-Jul-2014 10:05  1.0M  
[TXT] Farnell-Low-cost-Enc..> 13-Jun-2014 18:42  1.7M  
[TXT] Farnell-Lubrifiant-a..> 26-Mar-2014 18:00  2.7M  
[TXT] Farnell-M68000-PDF.htm  09-Jul-2015 11:22  1.7M  
[TXT] Farnell-MAX200-MAX20..> 09-Jul-2015 11:16  2.2M  
[TXT] Farnell-MAX202E-MAX2..> 09-Jul-2015 11:15  2.2M  
[TXT] Farnell-MAX232-MAX23..> 08-Jul-2014 18:52  2.3M  
[TXT] Farnell-MAX481-MAX48..> 09-Jul-2015 11:16  2.1M  
[TXT] Farnell-MAX756-MAX75..> 09-Jul-2015 11:16  2.2M  
[TXT] Farnell-MAX1365-MAX1..> 18-Jul-2014 16:56  1.4M  
[TXT] Farnell-MAX3221-Rev-..> 08-Sep-2014 07:28  1.8M  
[TXT] Farnell-MAX3222-MAX3..> 09-Jul-2015 11:16  2.1M  
[TXT] Farnell-MAX4661-MAX4..> 09-Sep-2014 08:10  2.8M  
[TXT] Farnell-MB85RS128B-F..> 20-Dec-2014 09:38  1.1M  
[TXT] Farnell-MC3510-PDF.htm  25-Mar-2014 08:17  3.0M  
[TXT] Farnell-MC21605-PDF.htm 15-Jan-2016 11:02  2.8M  
[TXT] Farnell-MC34063ABD-T..> 13-Oct-2014 07:06  844K  
[TXT] Farnell-MCF532x-7x-E..> 29-Mar-2014 11:14  2.8M  
[TXT] Farnell-MCOC1-Farnel..> 16-Jul-2014 09:04  1.0M  
[TXT] Farnell-MCP3421-Micr..> 18-Jul-2014 17:00  1.2M  
[TXT] Farnell-MIC809-MIC81..> 09-Jul-2015 11:13  2.4M  
[TXT] Farnell-MICREL-KSZ88..> 11-Mar-2014 07:54  2.2M  
[TXT] Farnell-MICROCHIP-PI..> 19-Mar-2014 18:02  2.5M  
[TXT] Farnell-MICROCHIP-PI..> 25-Jul-2014 12:34  6.7M  
[TXT] Farnell-MIDAS-un-tra..> 15-Jul-2014 17:05  1.0M  
[TXT] Farnell-MMBZxVCL-MMB..> 20-Dec-2014 09:53  1.6M  
[TXT] Farnell-MOLEX-39-00-..> 10-Mar-2014 17:19  1.9M  
[TXT] Farnell-MOLEX-43020-..> 10-Mar-2014 17:21  1.9M  
[TXT] Farnell-MOLEX-43160-..> 10-Mar-2014 17:21  1.9M  
[TXT] Farnell-MOLEX-87439-..> 10-Mar-2014 17:21  1.9M  
[TXT] Farnell-MPXV7002-Rev..> 20-Mar-2014 17:33  2.8M  
[TXT] Farnell-MSP-EXP430F5..> 29-Jul-2014 10:31  1.2M  
[TXT] Farnell-MSP430-Hardw..> 29-Jul-2014 10:36  1.1M  
[TXT] Farnell-MSP430F15x-M..> 08-Sep-2014 07:32  1.3M  
[TXT] Farnell-MTX-3250-MTX..> 18-Jul-2014 17:01  2.5M  
[TXT] Farnell-MTX-Compact-..> 18-Jul-2014 17:01  2.5M  
[TXT] Farnell-MULTICOMP-Ra..> 22-Jul-2014 12:57  5.9M  
[TXT] Farnell-MX670-MX675-..> 14-Jun-2014 09:46  2.5M  
[TXT] Farnell-Maxim-MAX322..> 09-Jul-2015 11:17  2.1M  
[TXT] Farnell-Microchip-MC..> 13-Jun-2014 18:27  1.8M  
[TXT] Farnell-Microship-PI..> 11-Mar-2014 07:53  2.2M  
[TXT] Farnell-Midas-Active..> 14-Jun-2014 18:17  3.4M  
[TXT] Farnell-Midas-MCCOG4..> 14-Jun-2014 18:11  2.1M  
[TXT] Farnell-Mini-Fit-Jr-..> 18-Jul-2014 17:03  2.5M  
[TXT] Farnell-Miniature-Ci..> 26-Mar-2014 17:55  2.8M  
[TXT] Farnell-Mistral-PDF.htm 14-Jun-2014 18:12  2.1M  
[TXT] Farnell-Molex-83421-..> 14-Jun-2014 18:17  3.4M  
[TXT] Farnell-Molex-COMMER..> 14-Jun-2014 18:16  3.4M  
[TXT] Farnell-Molex-Crimp-..> 10-Mar-2014 16:27  1.7M  
[TXT] Farnell-Multi-Functi..> 20-Mar-2014 17:38  3.0M  
[TXT] Farnell-NA555-NE555-..> 08-Jul-2014 18:53  2.2M  
[TXT] Farnell-NA555-NE555-..> 08-Sep-2014 07:51  1.5M  
[TXT] Farnell-NE556-SA556-..> 11-Oct-2014 15:48  1.7M  
[TXT] Farnell-NE5532-Texas..> 29-Jul-2014 10:32  1.5M  
[TXT] Farnell-NT3H1101-NT3..> 20-Dec-2014 10:06  2.3M  
[TXT] Farnell-NTE_SEMICOND..> 11-Mar-2014 07:52  2.3M  
[TXT] Farnell-NVE-datashee..> 28-Jul-2014 17:12  6.5M  
[TXT] Farnell-NXP-74VHC126..> 10-Mar-2014 16:17  1.6M  
[TXT] Farnell-NXP-BT136-60..> 11-Mar-2014 07:52  2.3M  
[TXT] Farnell-NXP-PBSS9110..> 10-Mar-2014 17:21  1.9M  
[TXT] Farnell-NXP-PCA9555 ..> 11-Mar-2014 07:54  2.2M  
[TXT] Farnell-NXP-PMBFJ620..> 10-Mar-2014 16:16  1.7M  
[TXT] Farnell-NXP-PSMN1R7-..> 10-Mar-2014 16:17  1.6M  
[TXT] Farnell-NXP-PSMN7R0-..> 10-Mar-2014 17:19  2.1M  
[TXT] Farnell-NXP-TEA1703T..> 11-Mar-2014 08:15  2.8M  
[TXT] Farnell-NaPiOn-Panas..> 06-Jul-2014 10:02  911K  
[TXT] Farnell-Nilfi-sk-E-..> 14-Jun-2014 09:47  2.5M  
[TXT] Farnell-Novembre-201..> 20-Mar-2014 17:38  3.3M  
[TXT] Farnell-OMRON-INDUST..> 25-Jul-2014 12:31  6.9M  
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[TXT] Farnell-OMRON-Master..> 10-Mar-2014 16:26  1.8M  
[TXT] Farnell-OPA627-Texas..> 09-Sep-2014 08:08  2.8M  
[TXT] Farnell-OSLON-SSL-Ce..> 19-Mar-2014 18:03  2.1M  
[TXT] Farnell-OXPCIE958-FB..> 13-Jun-2014 18:40  1.8M  
[TXT] Farnell-Octal-D-type..> 03-Jun-2015 18:10  2.5M  
[TXT] Farnell-Octal-Genera..> 28-Jul-2014 17:42  2.8M  
[TXT] Farnell-PADO-semi-au..> 04-Jul-2014 10:41  3.7M  
[TXT] Farnell-PBSS5160T-60..> 19-Mar-2014 18:03  2.1M  
[TXT] Farnell-PBSS5320X-NX..> 20-Dec-2014 09:47  1.6M  
[TXT] Farnell-PCF8574-PCF8..> 16-Jul-2014 09:03  1.7M  
[TXT] Farnell-PDTA143X-ser..> 20-Mar-2014 08:12  2.6M  
[TXT] Farnell-PDTB123TT-NX..> 20-Dec-2014 09:39  1.0M  
[TXT] Farnell-PESD5V0F1BL-..> 20-Dec-2014 09:39  1.1M  
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[TXT] Farnell-PESD9X5.0L-P..> 13-Jun-2014 18:43  1.6M  
[TXT] Farnell-PIC12F529T39..> 20-Dec-2014 09:39  1.0M  
[TXT] Farnell-PIC12F609-61..> 04-Jul-2014 10:41  3.7M  
[TXT] Farnell-PIC18F1220-1..> 20-Dec-2014 16:53  7.5M  
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[TXT] Farnell-TMP006EVM-Us..> 29-Jul-2014 10:30  1.3M  
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[TXT] Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46  464K 
 2006 Microchip Technology Inc. DS51295F_CN MPLAB® C18 C 编译器 入门 DS51295F_CN 第 ii 页  2006 Microchip Technology Inc. 提供本文档的中文版本仅为了便于理解。请勿忽视文档中包含 的英文部分,因为其中提供了有关 Microchip 产品性能和使用 情况的有用信息。Microchip Technology Inc. 及其分公司和相 关公司、各级主管与员工及事务代理机构对译文中可能存在的 任何差错不承担任何责任。建议参考 Microchip Technology Inc. 的英文原版文档。 本出版物中所述的器件应用信息及其他类似内容仅为您提供便 利,它们可能由更新之信息所替代。确保应用符合技术规范, 是您自身应负的责任。Microchip 对这些信息不作任何明示或 暗示、书面或口头、法定或其他形式的声明或担保,包括但不 限于针对其使用情况、质量、性能、适销性或特定用途的适用 性的声明或担保。 Microchip 对因这些信息及使用这些信息而 引起的后果不承担任何责任。如果将 Microchip 器件用于生命 维持和 / 或生命安全应用,一切风险由买方自负。买方同意在 由此引发任何一切伤害、索赔、诉讼或费用时,会维护和保障 Microchip 免于承担法律责任,并加以赔偿。在 Microchip 知识 产权保护下,不得暗中或以其他方式转让任何许可证。 商标 Microchip 的名称和徽标组合、 Microchip 徽标、 Accuron、 dsPIC、 KEELOQ、 microID、 MPLAB、 PIC、 PICmicro、 PICSTART、 PRO MATE、 PowerSmart、 rfPIC 和 SmartShunt 均为 Microchip Technology Inc. 在美国和其他国 家或地区的注册商标。 AmpLab、 FilterLab、 Migratable Memory、 MXDEV、 MXLAB、SEEVAL、SmartSensor 和 The Embedded Control Solutions Company 均为 Microchip Technology Inc. 在美国的 注册商标。 Analog-for-the-Digital Age、 Application Maestro、 CodeGuard、 dsPICDEM、 dsPICDEM.net、 dsPICworks、 ECAN、 ECONOMONITOR、 FanSense、 FlexROM、 fuzzyLAB、In-Circuit Serial Programming、ICSP、ICEPIC、 Linear Active Thermistor、 Mindi、 MiWi、 MPASM、 MPLIB、 MPLINK、 PICkit、 PICDEM、 PICDEM.net、 PICLAB、 PICtail、 PowerCal、 PowerInfo、 PowerMate、 PowerTool、REAL ICE、rfLAB、rfPICDEM、Select Mode、 Smart Serial、 SmartTel、 Total Endurance、 UNI/O、 WiperLock和ZENA均为Microchip Technology Inc.在美国和其 他国家或地区的商标。 SQTP 是 Microchip Technology Inc. 在美国的服务标记。 在此提及的所有其他商标均为各持有公司所有。 © 2006, Microchip Technology Inc. 版权所有。 请注意以下有关 Microchip 器件代码保护功能的要点: • Microchip 的产品均达到 Microchip 数据手册中所述的技术指标。 • Microchip 确信:在正常使用的情况下, Microchip 系列产品是当今市场上同类产品中最安全的产品之一。 • 目前,仍存在着恶意、甚至是非法破坏代码保护功能的行为。就我们所知,所有这些行为都不是以 Microchip 数据手册中规定的 操作规范来使用 Microchip 产品的。这样做的人极可能侵犯了知识产权。 • Microchip 愿与那些注重代码完整性的客户合作。 • Microchip 或任何其他半导体厂商均无法保证其代码的安全性。代码保护并不意味着我们保证产品是 “牢不可破”的。 代码保护功能处于持续发展中。 Microchip 承诺将不断改进产品的代码保护功能。任何试图破坏 Microchip 代码保护功能的行为均可视 为违反了 《数字器件千年版权法案 (Digital Millennium Copyright Act)》。如果这种行为导致他人在未经授权的情况下,能访问您的 软件或其他受版权保护的成果,您有权依据该法案提起诉讼,从而制止这种行为。 Microchip 位于美国亚利桑那州 Chandler 和 Tempe、位于俄勒冈州 Gresham 及位于加利福尼亚州 Mountain View 的全球总部、设计中心和 晶圆生产厂均通过了 ISO/TS-16949:2002 认证。公司在 PICmicro® 8 位单片机、 KEELOQ® 跳码器件、串行 EEPROM、单片机外设、非易失 性存储器和模拟产品方面的质量体系流程均符合 ISO/TS- 16949:2002。此外,Microchip 在开发系统的设计和生产方面的质量体 系也已通过了 ISO 9001:2000 认证。 MPLAB® C18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 iii 页 目录 前言 ................................................................................................................................. 1 第 1 章 概述 1.1 简介 ................................................................................................................ 9 1.2 嵌入式系统编程工具 ....................................................................................... 9 1.3 系统要求 ....................................................................................................... 11 1.4 目录 .............................................................................................................. 12 1.5 关于语言工具 ................................................................................................ 13 1.6 执行流程 ....................................................................................................... 14 第 2 章 安装 2.1 简介 .............................................................................................................. 15 2.2 安装 MPLAB C18 .......................................................................................... 15 2.3 卸载 MPLAB C18 .......................................................................................... 24 第 3 章 项目的基本操作及 MPLAB IDE 配置 3.1 简介 .............................................................................................................. 25 3.2 项目概述 ....................................................................................................... 25 3.3 创建文件 ....................................................................................................... 26 3.4 创建项目 ....................................................................................................... 26 3.5 使用项目窗口 ................................................................................................ 30 3.6 配置语言工具路径 ......................................................................................... 30 3.7 检查安装和编译选项 ..................................................................................... 33 3.8 编译和测试 ................................................................................................... 35 第 4 章 简单入门程序 4.1 简介 .............................................................................................................. 39 4.2 程序 1: “Hello, world!” ............................................................................. 39 4.3 程序 2:使用软件模拟器点亮 LED ............................................................... 44 4.4 程序 3:使用软件模拟器使 LED 闪烁 ........................................................... 49 4.5 使用演示板 ................................................................................................... 55 第 5 章 特性 5.1 概述 .............................................................................................................. 59 5.2 MPLAB 项目编译选项 ................................................................................... 59 5.3 演示:代码优化 ............................................................................................ 64 5.4 演示:在 Watch 窗口中显示数据 .................................................................. 76 MPLAB® C18 C 编译器入门 DS51295F_CN 第 iv 页  2006 Microchip Technology Inc. 第 6 章 架构 6.1 简介 .............................................................................................................. 89 6.2 PIC18XXXX 架构 .......................................................................................... 90 6.3 MPLAB C18 启动代码 .................................................................................. 94 6.4 #pragma 伪指令 ........................................................................................... 94 6.5 段 ................................................................................................................. 96 6.6 SFR 和软件 / 硬件定时器 .............................................................................. 97 6.7 中断 .............................................................................................................. 98 6.8 数学函数库和 I/O 函数库 .............................................................................. 98 第 7 章 疑难解答 7.1 简介 .............................................................................................................. 99 7.2 错误消息 ..................................................................................................... 100 7.3 常见问题 (FAQ) ...................................................................................... 101 术语表 ..........................................................................................................................107 索引 .............................................................................................................................121 全球销售及服务网点 ....................................................................................................123 MPLAB® C18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 1 页 前言 简介 本文档旨在帮助嵌入式系统工程师快速学会使用 Microchip 的 MPLAB® C18 C 编译 器。通过配合使用 MPLAB C18 C 编译器、 MPLINK™ 链接器、 MPLAB IDE 和 PIC18 PICmicro MCU,可快速开发出 PICmicro® 单片机应用。关于本文所讲述编译器 特征的详细介绍,请参阅 《MPLAB® C18 C 编译器用户指南》(DS51288J_CN)。 本文所提供信息适用于有单片机使用背景、理解 8 位单片机基本概念且熟悉 C 编程语 言的工程师或学生。 本章内容包括: • 文档编排 • 本指南使用的约定 • 推荐读物 • Microchip 网站 • 开发系统变更通知客户服务 • 客户支持 客户须知 所有文档均会过时,本文档也不例外。 Microchip 的工具和文档将不断演变以满足客户的需求,因此 实际使用中有些对话框和 / 或工具说明可能与本文档所述之内容有所不同。请访问我们的网站 (www.microchip.com)获取最新文档。 文档均标记有 “DS”编号。该编号出现在每页底部的页码之前。 DS 编号的命名约定为 “DSXXXXXA”,其中 “XXXXX”为文档编号,“A”为文档版本。 欲了解开发工具的最新信息,请参考 MPLAB® IDE 在线帮助。从 Help (帮助)菜单选择 Topics (主题),打开现有在线帮助文件列表。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 2 页  2006 Microchip Technology Inc. 文档编排 • 第1章 概述——对MPLAB C18 C编译器及其组件,以及它与MPLAB集成开发环境 (IDE)的集成方面的概述。 • 第 2 章 安装——一步步地指导 MPLAB C18 C 编译器的安装过程。 • 第3章 项目的基本操作及MPLAB IDE配置——通过MPLAB项目和MPLAB SIM软 件模拟器介绍了使用 MPLAB C18 时的 MPLAB IDE 设置,并提供了运行本指南中 示例和应用程序所需 MPLAB IDE 设置方面基本知识的参考信息。 • 第 4 章 简单入门程序——提供了简单的示例,从最简单的“Hello, world!”入门程 序开始,接着提供了点亮连接到 PIC18 单片机的 LED 的程序。 • 第 5 章 特性——概括介绍了 MPLAB C18 编译器的总体功能,提供了关于优化的代 码演示,并举例说明了如何使用 MPLAB Watch (观察)窗口来查看数据元素和结 构。 • 第6章 架构——讲述了PIC18架构,以及MPLAB C18编译器有别于其他C编译器的 特殊功能。 • 第7章 疑难解答——列出了常见的错误消息和技术问题,并提供了处理这些问题的 答案和指导。 前言  2006 Microchip Technology Inc. DS51295F_CN 第 3 页 本指南使用的约定 本手册采用以下文档约定: 文档约定 说明 表示 示例 Arial 字体: 斜体字符 参考书目 MPLAB® IDE User's Guide 需强调的文字 ... 仅有的编译器 ... 首字母大写 窗口 Output 窗口 对话框 Settings 对话框 菜单选项 选择 Enable Programmer 引用 窗口或对话框中的域名 “Save project before build” 带右尖括号且有下划线的斜体 文字 菜单路径 File>Save 粗体字 对话框按钮 单击 OK 选项卡 单击 Power 选项卡 尖括号 < > 括起的文字 键盘上的按键 按 Courier 字体: 常规 Courier 源代码示例 #define START 文件名 main.c 文件路径 c:\mcc18\h 关键字 _asm, _endasm, static 命令行选项 -Opa+, -Opa- 位值 0, 1 常数 0xFF, ‘A’ 斜体 Courier 可变参数 file.o,其中file 可以是任 一有效文件名 0bnnnn 二进制数, n 是其中一位 0b00100, 0b10 0xnnnn 十六进制数, n 是其中一位 0xFFFF, 0x007A 方括号 [ ] 可选参数 mcc18 [options] file [options] 花括号和竖线: { | } 选择互斥参数; “或”选择 errorlevel {0|1} 省略号 ... 代替重复文字 var_name [, var_name...] 表示由用户提供的代码 void main (void) { ... } MPLAB® C18 C 编译器入门 DS51295F_CN 第 4 页  2006 Microchip Technology Inc. 推荐读物 PIC18 开发参考读物 要了解更多关于编译器的函数库和预编译目标文件、 MPLAB IDE 及其他工具使用方面 的信息,请阅读以下推荐读物。 MPLAB-C18-README.txt 关于使用 MPLAB C18 C 编译器的最新信息,请阅读本软件自带的 MPLAB-C18-README.txt 文件(ASCII 文本)。此 readme 文件包含了本文档可能未提 供的更新信息。 Readme for XXX.txt 需要其他 Microchip 工具的最新信息 (MPLAB IDE 和 MPLINK 链接器等),请阅读软 件自带的相关 readme 文件 (ASCII 文本文件)。 MPLAB® C18 C 编译器用户指南 (DS51288J_CN) 一个综合指南,讲述了针对 PIC18 器件设计的 Microchip MPLAB C18 C 编译器的使用 及特征。 PIC18 Configuration Settings Addendum (DS51537) 给出了 MPLAB C18 C 编译器 #pragma config 伪指令和 MPASM CONFIG 伪指令支 持的 Microchip PIC18 器件的配置位设置。 MPLAB C18 C 编译器函数库 (DS51297F_CN) 关于 MPLAB C18 函数库和预编译目标文件的参考指南。列出了随 MPLAB C18 C 编译 器提供的所有库函数,并详细描述了这些库函数的使用。 MPLAB® IDE 用户指南 (DS51519A_CN) 介绍如何安装 MPLAB IDE 软件及如何使用 IDE 创建项目并烧写器件。 MPASM™ 汇编器、 MPLINK™ 目标链接器和 MPLIB™ 目标库管理器用户指南 (DS33014J_CN) 这个用户指南描述了如何使用 Microchip 的 PICmicro 单片机汇编器 (MPASM )、链 接器 (MPLINK)和库管理器 (MPLIB)。 PICmicro® 18C 单片机系列参考手册 (DS39500A_CN) 重点介绍 PIC18 系列器件。说明了 PIC18 系列的架构和外设模块的工作原理,但没有 涉及到每个器件的具体细节。 PIC18 器件数据手册 讲述 PIC18 器件工作和电气特性的数据手册。 要获得上述任何文档,请访问 Microchip 的网站(www.microchip.com),获得 Adobe Acrobat (.pdf)格式的文档。 前言  2006 Microchip Technology Inc. DS51295F_CN 第 5 页 C 语言及其他参考书 有许多有关 C 语言一般知识的参考书和教材,其中一些资料还涉及到使用 Microchip 单片机开发嵌入式应用。 American National Standard for Information Systems – Programming Language – C. American National Standards Institute (ANSI), 11 West 42nd. Street, New York, New York, 10036. 此标准规定了用 C 语言编写程序的格式,并对 C 程序进行了解释。其目的是提高 C 程序在多种计算机系统上的可移植性、可靠性、可维护性及执行效率。 Harbison, Samuel P. and Steele, Guy L., C: A Reference Manual, Fourth Edition. Prentice-Hall, Englewood Cliffs, New Jersey 07632. 详细地讲述了 C 编程语言。这本书是一本权威性的参考手册,它对 C 语言、运行时 库以及 C 编程的风格都进行了完整的描述,C 编程强调正确性、可移植性和可维护 性。 Huang, Han-Way. PIC® Microcontroller: An Introduction to Software & Hardware Interfacing. Thomson Delmar Learning, Clifton Park, New York 12065. 对 Microchip PIC18 单片机系列进行了全面介绍,包括 PIC 单片机外设功能的编 程和接口。这本书可用作大学教科书,其中使用了 PIC 单片机汇编语言和 MPLAB C18 C 编译器。 Kernighan, Brian W. and Ritchie, Dennis M. The C Programming Language, Second Edition. Prentice Hall, Englewood Cliffs, New Jersey 07632. 对由 ANSI 标准定义的 C 语言进行了简明阐述。对于 C 程序员来说是一本出色的参 考书。 Kochan, Steven G. Programming In ANSI C, Revised Edition. Hayden Books, Indianapolis, Indiana 46268. 学习 ANSI C 的另一本出色的参考书,用作大学教材。 Peatman, John B. Embedded Design with the PIC18F452 Microcontroller, First Edition. Pearson Education, Inc., Upper Saddle River, New Jersey 07458. 重点介绍Microchip公司的PIC18FXXX系列单片机以及如何编写优化的应用代码。 Van Sickle, Ted. Programming Microcontrollers in C, First Edition. LLH Technology Publishing, Eagle Rock, Virginia 24085. 讲述单片机 C 语言编程的基本原理。 Standards Committee of the IEEE Computer Society – IEEE Standard for Binary Floating-Point Arithmetic. The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, New York 10017. 这个标准描述了 MPLAB C18 采用的浮点数格式。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 6 页  2006 Microchip Technology Inc. 应用笔记 Microchip 提供了丰富的应用笔记,许多应用笔记都与 MPLAB C18 C 编译器兼容。下 面列出了其中的部分应用笔记。请查看 Microchip 网站中最新发布的应用笔记。 • AN953 Data Encryption Routines for the PIC18 • AN851 A FLASH Bootloader for PIC16 and PIC18 Devices • AN937 Implementing a PID Controller Using a PIC18 MCU • AN914 Dynamic Memory Allocation for the MPLAB C18 C Compiler • AN991 Using the C18 Compiler and the MSSP to Interface I2C™ EEPROMs with PIC18 Devices • AN878 PIC18C ECAN C Routines • AN738 PIC18C CAN Routines in ‘C’ • AN930 J1939 C LIbrary for CAN-Enabled PICmicro® MCUs 设计中心 Microchip 网站 www.microchip.com 中包含许多设计中心,提供针对某个具体行业的 指导信息。这些设计中心中包含源代码、应用笔记、网络资源和针对具体应用推荐的 Microchip MCU。 下面是所提供的部分设计中心: • Microchip 产品入门 • 汽车电子解决方案 • 高引脚数 / 高存储容量单片机 • KEELOQ® 鉴定解决方案 • 电池管理解决方案 • LCD 解决方案 • 网络连接解决方案 - 物理协议:CAN、 LIN 和 USB - 无线协议:ZigBee™、红外和 rfPIC® - 互联网协议:TCP/IP • 低功耗解决方案 • 机电一体化设计 • 电机控制解决方案 • 家电解决方案 • 全球最小的单片机 • 公用仪表解决方案 • EMC 设计 • 3V 系统设计 • 16 位单片机解决方案 前言  2006 Microchip Technology Inc. DS51295F_CN 第 7 页 MICROCHIP 网站 Microchip 在全球网站 www.microchip.com 上提供在线支持。用户可以在网站上很方 便地获得文件和信息。用户可以使用互联网浏览器访问网站。该网站包含以下信息: • 产品支持——数据手册和勘误表、应用笔记和示例程序、设计资源、用户指南和硬 件支持文档、最新的软件版本和归档软件 • 一般技术支持——常见问题 (FAQ)解答、技术支持请求、在线讨论组以及 Microchip 顾问计划成员名单 • Microchip 业务——产品选型和订购指南、最新的 Microchip 新闻、研讨会与活动安 排表、 Microchip 销售办事处、代理商及工厂代表列表 开发系统变更通知客户服务 Microchip 的客户通知服务有助于客户了解 Microchip 产品的最新信息。注册客户可在 他们感兴趣的某个产品系列或开发工具发生变更、更新、发布新版本或勘误表时,收 到电子邮件通知。 欲注册,请登录 Microchip 网站 www.microchip.com,点击 “变更通知客户 (Customer Change Notification)”服务并按照注册说明完成注册。 开发系统产品的分类如下: • 编译器——Microchip C 编译器及其他语言工具的最新信息,包括 MPLAB C18 和 MPLAB C30 C 编译器、MPASM 和 MPLAB ASM30 汇编器、MPLINK 和 MPLAB LINK30 目标链接器,以及 MPLIB 和 MPLAB LIB30 目标库管理器。 • 仿真器——Microchip 在线仿真器的最新信息,包括 MPLAB ICE 2000 和 MPLAB ICE 4000。 • 在线调试器——Microchip 在线调试器 MPLAB ICD 2 的最新信息。 • MPLAB® IDE——关于支持开发系统工具的 Windows® 集成开发环境 Microchip MPLAB IDE 的最新信息,主要针对 MPLAB IDE、 MPLAB SIM 软件模拟器、 MPLAB 项目管理器以及一般编辑和调试功能。 • 编程器——Microchip 编程器的最新信息,包括 MPLAB PM3 器件编程器和 PICSTART® Plus 开发编程器。 客户支持 Microchip 产品的用户可通过以下渠道获得帮助: • 代理商或代表 • 当地销售办事处 • 应用工程师 (FAE) • 技术支持 客户应联系其代理商、代表或应用工程师 (FAE)寻求支持。当地销售办事处也可为 客户提供帮助。本文档后附有销售办事处的联系方式。 也可通过 http://support.microchip.com 获得网上技术支持。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 8 页  2006 Microchip Technology Inc. 注: MPLAB® C18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 9 页 第 1 章 概述 1.1 简介 本章介绍用于嵌入式系统编程的软件工具。讲述了编译器和汇编器的功能及区别,以 及 C 语言的优势。还介绍了 MPLAB C18 的目录结构、各种语言工具可执行文件和执 行流程。 本章内容包括: • 嵌入式系统编程工具 • 系统要求 • 目录 • 关于语言工具 • 执行流程 1.2 嵌入式系统编程工具 1.2.1 MPLAB C18 C 编译器 MPLAB C18 C编译器是在PC机上运行的交叉编译器,生成可由Microchip PIC18XXXX 系列单片机执行的代码。与汇编器一样, MPLAB C18 编译器将人可理解的语句翻译 为单片机可执行的 “1”和 “0”。而与汇编器不同的是,编译器不将机器助记符一对 一地翻译为机器码。 MPLAB C18 接受标准 C 语句,如 if(x==y) 和 temp=0x27,并将其转换为 PIC18XXXX 机器码。编译器在这个过程中融合了很多 “智能”功能。当代码中一个 C 函数采用的子程序也被其他 C 函数使用时,编译器将优化这段代码。编译器能重新排 列代码,删除不会执行到的代码,在多个函数间共用公共代码段,且可识别到使用效 率低的数据和寄存器并优化对它们的访问。 代码采用标准的 ANSI C 符号编写。源代码被编译为程序代码块和数据块,然后 “链 接”到其他的代码和数据块,再存放到 PIC18XXXX 单片机的各存储区中。这个过程 称为 “build”,且在编写、测试和调试代码的程序开发过程中经常会进行多次 build。 通过使用 “make”程序可使这个过程更为 “智能化”,它仅对上次编译后项目中更改 过的 C 源文件调用编译器,因此可缩短项目编译的时间。 可通过命令行调用 MPLAB C18 编译器及其相关工具 (如链接器和汇编器)来生成 .HEX 文件,可将这种文件烧写到 PIC18XXXX 器件中。也可从 MPLAB IDE 中调用 MPLAB C18 及其他工具 。 MPLAB 图形用户界面作为一个单一的环境,可在其中为嵌 入式应用编写、编译和调试代码。 MPLAB 对话框和项目管理器完成编译器、汇编器和链接器的大部分具体工作,因而用 户可将主要精力集中在编写和调试应用程序的任务上。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 10 页  2006 Microchip Technology Inc. 由于 MPLAB C18 编译器使用标准 C 语言,因而使得嵌入式系统应用的开发更为容 易。有许多教授 C 语言的参考书,本文档的前言 “推荐读物”中列出了一些这样的参 考书。本指南假定读者已经了解关于 C 编程的基本知识。 C 语言的优势在于,它使用 广泛,可在不同的架构之间移植,有许多相关的参考书和教材,且比汇编语言更易于 维护和扩展。另外, MPLAB C18 可为 PIC18XXXX 单片机编译出极为高效率的代码。 1.2.2 MPASM 交叉汇编器和 MPLINK 链接器 通常情况下,可使用交叉汇编器和交叉编译器来为项目编写代码。MPASM 是 MPLAB IDE 的一个组件,它与 MPLINK配合工作,MPLINK将汇编语言代码段与 MPLAB C18 C 编译器生成的代码链接起来。 汇编语言程序适用于要求非常快运行速度或要求在严格定义的时间内运行的小代码段。 1.2.3 其他工具 本指南中,利用 MPLAB IDE 的图形化用户界面和开发环境,通过 MPLAB C18 编译器 来编写和编译代码示例。《MPLAB® IDE v6.xx 快速入门指南》中提供了教程并一步步 指导和帮助您了解和学习使用 MPLAB IDE。其他有关汇编语言和链接器的信息,请参 阅 《MPASM™ 汇编器、 MPLINK™ 目标链接器和 MPLIB™ 目标库管理器用户指 南 》。 Microchip 的 PICDEM™ 2 Plus 开发板可使用 PIC18F452 作为主单片机,且本文档提供 的示例可在此开发板上运行,使板上的 LED 闪烁。 也可使用 MPLAB ICD 2 来对 PICDEM 2 Plus 开发板上的 PIC18F452 编程及调试程 序。但运行本指南中的示例可不需要这些硬件工具。可在免费的 MPLAB IDE 中,使用 的 MPLAB SIM 的 PIC18XXXX 模拟器来进行调试。 注: 尽管编译器生成代码的执行时间可能与使用汇编语言生成的代码几乎相 同,但由于编译是一个翻译转换过程,经过这一翻译转换过程后才能生成 可直接从汇编语言生成的机器码,因此编译器生成的代码不可能比汇编语 言代码执行速度快。 概述  2006 Microchip Technology Inc. DS51295F_CN 第 11 页 1.3 系统要求 使用 MPLAB C18 和 MPLAB IDE 的建议系统要求为: • Intel® Pentium® PC,安装 Microsoft® 32 位 Windows 操作系统(Windows 2000、 Windows XP 家庭版或 Windows XP 专业版) • 大约 250 MB 硬盘空间 • 针对本指南中某些示例的可选硬件工具: - PICDEM 2 Plus 开发板和电源 - MPLAB ICD 2 在线调试器 (需要串行或 USB 连接) 尽管 MPLAB C18 可独立于 MPLAB IDE 单独使用,但本指南举例说明了 MPLAB C18 在 MPLAB 集成开发环境中的使用。应该在安装 MPLAB C18 之前安装 MPLAB IDE。 MPLAB IDE 的默认安装可能有预先设定的选择。当为使用 MPLAB C18 而安装 MPLAB IDE 时,至少要选择如下组件 (参见图 1-1): • MPLAB IDE 器件支持 - 8 位 MCU • Microchip 应用程序 - MPLAB IDE - MPLAB SIM - MPASM 工具包(这个工具包也可随 MPLAB C18 安装,因此安装 MPLAB IDE 时不必安装它) 图 1-1: MPLAB® IDE 安装菜单 * 可选的组件。如果要使用 MPLAB ICD 2 来进行编程和调试,要选择这个组件。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 12 页  2006 Microchip Technology Inc. 1.4 目录 可将 MPLAB C18 安装到 PC 的任何目录下。默认安装目录为 C:\mcc18。 图 1-2 示出了 MPLAB C18 典型安装的目录结构: 图 1-2: MPLAB® C18 目录结构 MPLAB C18安装目录包含编译器、汇编器和链接器的readme文件。表 1-1对其子目录 的内容进行了描述。 表 1-1: MPLAB C18 子目录描述 目录 描述 bin 包含编译器和链接器的可执行文件。将在第 1.5 节 “关于语言工具”中 对这些可执行文件进行更详细的描述。 doc 包含 C18 C 编译器的文档。仅当选择安装文档时,才会安装文档 (参 见第 2.2.5 节 “选择组件”和图 2-5)。 example 包含范例应用程序,帮助用户开始学习使用 MPLAB C18,其中包括本 文档中使用的示例。这些代码示例可能和第 4 章 “简单入门程序”中使 用的代码略微不同。 h 包含标准 C 函数库的头文件和所支持 PICmicro® 单片机的特定处理器 函数库的头文件。 lib 包含标准 C 函数库 (clib.lib 或 clib_e.lib)、特定处理器的函 数库 (p18xxxx.lib 或 p18xxxx_e.lib,其中 xxxx 是具体的器 件型号)和启动模块 (c018.o、 c018_e.o、c018i.o、 c018i_e.o、 c018iz.o 和 c018iz_e.o)。 lkr 包含供 MPLAB C18 使用的链接描述文件。 mpasm 包含 MPASM 汇编器以及 MPLAB C18 所支持器件的汇编头文件 (p18xxxx.inc)。 src 包含标准 C 函数库、特定处理器函数库和启动模块的 C 和汇编源代码 文件。其中包含针对扩展模式和传统 (非扩展)模式的子文件夹。 概述  2006 Microchip Technology Inc. DS51295F_CN 第 13 页 1.5 关于语言工具 MPLAB C18 编译器安装目录下的 bin 和 mpasm 子目录包含 MPLAB C18 、MPASM 汇 编器和 MPLINK 链接器的可执行文件。一般情况下,这些可执行文件中的大多数在编 译过程中自动运行。 MPLAB IDE 项目管理器需要知道主编译器、汇编器、链接器和库 可执行文件的安装位置 (由 Project>LanguageToolLocations 设置)。其中某些工具的 简要描述参见表 1-2。 关于语言工具的更详细信息,包括其命令行用法,请参考 《MPLAB® C18 C 编译器用 户指南》(DS51288J_CN)和 《MPASM™ 汇编器、 MPLINK™ 目标链接器和 MPLIB™ 目标库管理器用户指南 》(DS33014J_CN)。 表 1-2: MPLAB® C18、 MPASM™ 汇编器和 MPLINK™ 链接器可执行文件 可执行文件 描述 mcc18.exe 编译器 shell。它以 C 文件 (如 file.c)作为输入,调用扩展 模式和非扩展模式编译器可执行文件。 mplink.exe 链接器的驱动程序。它以链接描述文件 (如 18F452.lkr)、 目标文件和库文件作为输入,并把这些文件传递给 _mplink.exe。然后它会把_mplink.exe输出的COFF文件传 递给 mp2hex.exe。 _mplink.exe 链接器。它输入链接描述文件、目标文件和库文件,输出公共 目标文件格式 (Common Object File Format, COFF)可执行 文件 (如 file.out 或 file.cof)。 COFF 文件是对输入目 标文件及从函数库引用的目标文件的数据和代码进行地址分配 的结果。 _mplink.exe 也可以选择生成一个映射文件 (如 file.map),这种映射文件包含关于数据和代码分配的详细信 息。 mp2hex.exe 把 COFF 文件转化为 hex 文件的文件转换器。 hex 文件是 PICmicro® 单片机编程器(如 PICSTART® Plus 或 PRO MATE® II)可读的文件格式。mp2hex.exe 输入由 _mplink.exe 生成 的 COFF 文件,输出 hex 文件 (如 file.hex)。 mplib.exe 库管理器。它允许创建和管理库文件 (如 file.lib),而库 文件则充当目标文件的存档文件。库文件用于将目标文件组织 成可重用的代码库。 mpasmwin.exe Windows® 汇编器可执行文件,它以汇编源文件 (如 file.asm)作为输入,输出 COFF 文件(如 file.o)或 hex 文件和 COD 文件 (如 file.hex 和 file.cod)。汇编源文 件可能包含汇编头文件 (如 p18f452.inc),汇编头文件也包 含汇编源代码。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 14 页  2006 Microchip Technology Inc. 1.6 执行流程 图 1-3 举例说明了语言工具的执行流程。 图 1-3: 语言工具执行流程 在上面的示例中,由 MPLAB C18 编译两个 C 文件 file2.c 和 file3.c,由 MPASM 汇编汇编文件 file1.asm,生成了目标文件 file1.o、 file2.o 和 file3.o。 预编译的目标文件 file4.o 和 file3.o 形成名为 lib1.lib 的库文件。最后,链接 器将其余的目标文件与库文件组合在一起。 MPLINK 还输入链接描述文件 script.lkr。 MPLINK 生成输出文件 output.cof、 output.map 和 HEX 文件 output.hex。 03$60:,1 03/,% 03/,1. 0&& 0&& 䕧ܹ ⑤᭛ӊ Ⳃᷛ ᭛ӊ ᑧ᭛ӊ੠ 䫒᥹ᦣ䗄᭛ӊ ߎ䕧 ᭛ӊ RXWSXWFRI RXWSXWPDS RXWSXWKH[ OLEOLE VFULSWONU ILOHR ILOHR ILOHR ILOHR ILOHDVP ILOHF ILOHF Œ Œ MPLAB® C18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 15 页 第 2 章 安装 2.1 简介 在安装 MPLAB C18 之前,应该先在 PC 上安装 MPLAB IDE。 MPLAB IDE 的安装文 件可从 CD-ROM 上获得或从 www.microchip.com 免费下载。 MPLAB IDE 的项目管理 器和 MPLAB SIM 软件模拟器都是 MPLAB IDE 的组件,本指南中广泛使用了这两个组 件和内置的调试器 (参见第 1.3 节 “系统要求”)。 本章详细讲述如何安装 MPLAB C18。有些情况下需要卸载软件,为此也提供了如何卸 载软件的指示说明。 2.2 安装 MPLAB C18 要安装 MPLAB C18,请运行 CD-ROM 中的安装程序。如果要升级 MPLAB C18,请 运行从 Microchip 网站上下载的升级安装程序。在整个安装过程中,一系列的对话框将 一步步地指导您如何进行安装。 2.2.1 欢迎 首先会出现一个欢迎屏幕 (图 2-1),告知安装程序要安装的 MPLAB C18 的版本号。 图 2-1: 安装:欢迎屏幕 点击 Next 继续安装。 Needs Updating MPLAB® C18 C 编译器入门 DS51295F_CN 第 16 页  2006 Microchip Technology Inc. 2.2.2 许可协议 接着出现 MPLAB C18 许可协议。阅读协议,然后点击 “I Accept”。 图 2-2: 安装:许可协议 接受许可协议后,点击 Next> 继续。 安装  2006 Microchip Technology Inc. DS51295F_CN 第 17 页 2.2.3 Readme 文件 随后将显示 MPLAB C18 的 readme 文件 (图 2-3)。这个文件包含关于此版本 MPLAB C18 的重要信息,如支持的器件、新特性、已知问题及变通解决方案。每个版 本的 readme 文件有所不同,看起来与下图中类似,但内容不同。 图 2-3: 安装:README 文件 看完 readme 文件后,点击 Next 继续安装。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 18 页  2006 Microchip Technology Inc. 2.2.4 选择安装目录 选择要将 MPLAB C18 安装到哪个目录中。 当第一次安装 MPLAB C18 时,默认的安装目录是 C:\mcc18,如图 2-4 所示。如果 要安装到其他目录中,请点击 Browse。 如果是安装升级版本,安装程序则会将默认安装目录设置为上次安装时的目录。在升 级时,所选的安装目录必须是上次安装或升级时的安装目录。 图 2-4: 安装:选择安装目录 点击 Next。 注: 在安装过程中,安装目录和其子目录中的文件可能会被覆盖或删除。若要 保存任何文件,例如要保存上次安装修改过的链接描述文件或库源代码, 则可在继续进行安装前将这些文件复制到安装目录外的目录中去。 注: 安装升级版本时,如果不安装到原有版本所在的目录中,将显示错误消息 “No previous installation”。 安装  2006 Microchip Technology Inc. DS51295F_CN 第 19 页 2.2.5 选择组件 选中相应的复选框,选择需要安装的组件 (图 2-5)。表 2-1 详细描述了可选择组件。 也会随 MPLAB IDE 提供 MPASM 的链接描述文件。当使用 MPLAB C18 编译器时, 要确保使用随 MPLAB C18 安装的链接描述文件,而不是随 MPLAB IDE 安装的链接 描述文件。随 MPLAB C18 提供的链接描述文件具有某些特殊编译器伪指令。 图 2-5: 安装:选择组件 点击 Next> 继续。 注: MPASM 和 MPLINK 随 MPLAB IDE 免费提供。这两个工具也可随 MPLAB C18 编译器安装。为确保所有这些工具互相兼容,应该使用 MPASM 和 MPLINK 随 MPLAB C18 编译器提供的版本。 注: 并非所有的安装都包含文档。对于升级程序和某些从网上下载的安装程 序,文档是单独发布的。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 20 页  2006 Microchip Technology Inc. 表 2-1: MPLAB C18 软件组件 组件 描述 程序文件 编译器和链接器的可执行文件。用户应该选择安装这个组件,除非是仅 升级辅助文件 (不升级可执行文件)。 汇编器文件 MPASM™ 汇编器以及 MPLAB C18 所支持器件的汇编头文件 (p18xxxx.inc)。 链接描述文件 MPLINK™ 链接器需要的文件。每个支持的 PICmicro 单片机都有一个这 样的文件。每个文件为处理器提供了一个默认的存储配置,并指引链接 器在处理器的存储器中分配代码和数据。 注:这些链接描述文件有别于随 MPLAB IDE 提供的链接描述文件,是 专门为 MPLAB C18 设计的。建议安装这个组件。 标准头文件 这些是标准 C 函数库和特定处理器函数库的头文件。建议安装这个组 件。 标准函数库 这个组件包含标准 C 函数库、特定处理器函数库和启动模块。请参阅 《MPLAB® C18 C 编译器函数库》(DS51297F_CN)和 《MPLAB® C18 C 编译器用户指南》(DS51288J_CN),以获取更多关于函数库和 启动模块的信息。由于大多数典型的程序都使用函数库和一个启动模 块,推荐用户安装这个组件。 示例 这些是范例应用程序,其中包括本文档中讲述的示例,用来帮助用户学 习使用 MPLAB C18。 库源代码 标准 C 函数库和特定处理器函数库的源代码。可安装这个组件来查看源 代码,以及修改或重建函数库。 预处理器源代码 这是预处理器的源代码,供有兴趣的用户参考。 安装  2006 Microchip Technology Inc. DS51295F_CN 第 21 页 2.2.6 配置选项 在接下来的 Configuration Options (配置选项)对话框 (图 2-6)中,选择所需要的 MPLAB C18 配置选项。 图 2-6: 安装:配置选项 表 2-2 对各配置选项进行了详细描述。点击 Next。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 22 页  2006 Microchip Technology Inc. 表 2-2: MPLAB C18 配置选项 配置 描述 Add MPLAB C18 to PATH environment variable 将 MPLAB C18 可执行文件 (mcc18.exe)和 MPLINK 链接 器可执行文件 (mplink.exe)的路径添加到 PATH 环境变 量的开头。这样用户就能从任何目录、在命令 shell 提示符下 启动 MPLAB C18 编译器和 MPLINK 链接器。不管是否已经 包含了目录,都要将这个选项放在路径的最前面。 Add MPASM to PATH environment variable 将 MPASM 可执行文件 (mpasmwin.exe)的路径添加到 PATH 环境变量的开头。这样用户就能从任何目录、在命令 shell 提示符下启动 MPASM 汇编器。不管是否已经包含了目 录,都要将这个选项放在路径的最前面。 Add header file path to MCC_INCLUDE environment variable 将 MPLAB C18 头文件目录的路径添加到 MCC_INCLUDE 环 境变量的开头。 MCC_INCLUDE 是一个由分号隔开的目录列表。如果 MPLAB C18 在由 -I 命令行选项指定的目录列表中找不到头文件,那 么它将在 MCC_INCLUDE 目录列表中搜索头文件。选择该配 置选项表明在包含标准头文件时,用户不必使用 -I 命令行选 项。如果该变量不存在,就创建它。 Modify PATH and MCC_INCLUDE variables for all users 此选项只在当前用户以管理员身份登录 Windows NT 或 Windows 2000 计算机时出现。如果选择这个配置,则对前三 个选项中指定的变量所做的修改会影响到所有的用户,否则 只有当前用户的变量会受影响。 Update MPLAB IDE to use this MPLAB C18 只有当系统安装有 MPLAB IDE 时才会出现此选项。选择此选 项将把 MPLAB IDE 配置为使用新安装的 MPLAB C18。这包 括在 MPLAB IDE 中,使用 MPLAB C18 库目录作为 MPLAB C18 项目的默认库路径。 Update MPLAB IDE to use this MPLINK linker 只有当系统安装有 MPLAB IDE 时才会出现此选项。选择此选 项将 MPLAB IDE 配置为使用新安装的 MPLINK™ 链接器。 安装  2006 Microchip Technology Inc. DS51295F_CN 第 23 页 2.2.7 文档通知 如果可执行文件不安装文档,将出现与图 2-7 类似的通知。可从 MPLAB C18 安装 CD-ROM 和 Microchip 网站上获得文档。 图 2-7: 安装:更新文档提示 2.2.8 开始安装 在 Start Installation (开始安装)屏幕 (图 2-8)中点击 Next> 安装文件。 注: 要通过 MPLAB C18 CD-ROM 或从网站上下载的带文档的升级版本自动安 装文档,请在 Select Components (选择组件)对话框中选择 Documentation (文档)选项 (见图 2-5)。 注: 安装目录及其子目录中的所有文件都会被覆盖或删除。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 24 页  2006 Microchip Technology Inc. 图 2-8: 安装:开始安装 2.2.9 完成安装 在 Installation Complete (安装完成)屏幕中,点击 Finish。此时 MPLAB C18 已安 装成功。 为使 MPLAB C18 能正常运行,可能需要重新启动计算机。如果出现了 “Restart Computer” (“重启计算机”)对话框,可选择 Yes 立即重新启动计算机,或选择 No,以后再重新启动计算机。 2.3 卸载 MPLAB C18 要卸载 MPLAB C18,请打开 Windows 控制面板并运行 “Add/Remove Programs” (“添加 / 删除程序”)。在程序列表中选择安装的 MPLAB C18 程序,并按照指示来 删除程序。这样就会从计算机中删除 MPLAB C18 目录及其中的内容。 注: 如果卸载 MPLAB C18 的升级版本,则全部安装内容都会被删除; MPLAB C18 不能恢复到升级前安装的版本。在卸载升级版本前,要确保 有原先的安装盘,以便以后可重新安装 MPLAB C18。 MPLAB® C18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 25 页 第 3 章 项目的基本操作及 MPLAB IDE 配置 3.1 简介 本章讲述项目的基本操作以及通过 MPLAB SIM 测试本指南中示例和应用程序的配置 选项。本章仅对此做了概括性介绍,并以一个普通的应用作为示例。关于器件选择和 链接描述文件的详细信息随具体应用而有所不同。如果读者对于这些基本操作已较为 熟悉,则可忽略本章内容。 本章内容包括: • 项目概述 • 创建文件 • 创建项目 • 使用项目窗口 • 配置语言工具路径 • 检查安装和编译选项 • 编译和测试 3.2 项目概述 项目由 MPLAB IDE 中与语言工具 (如 MPLAB C18)相关的文件组成。项目由源文 件、头文件、目标文件库文件和链接描述文件组成。每个项目都应该有一个或多个源 文件及一个链接描述文件。 一般来说,至少需要一个头文件来标识目标单片机的寄存器名。头文件一般被源文件 包含进来而不用明确地添加到项目中。 项目的输出文件包括将作为固件装载到目标单片机中的可执行代码。生成的调试文件 有助于 MPLAB IDE 将源文件中的符号和函数名与可执行代码和用于存储变量的存储区 关联起来。 本指南中的大部分示例和应用程序都只包含一个由一个源文件和一个链接描述文件组 成的项目。 更多信息,请参阅 《MPLAB® IDE v6.xx 快速入门指南》(DS51281C_CN)。 注: 这里未一步步讲述创建和编译项目所需的详细步骤,而仅概述了如何确保 正确设置 MPLAB IDE 的关键操作。《MPLAB® IDE 用户指南》中提供了如 何创建项目的教程。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 26 页  2006 Microchip Technology Inc. 3.3 创建文件 启动 MPLAB IDE 并选择 File>New 打开一个新的空白源文件。本指南中的示例和应用 程序列出了源代码,可通过 MPLAB 编辑器键入或拷贝并粘贴这些源代码到文本文件 中。示例源代码在 mcc18\example\getting started 中。 键入或拷贝源代码 (在本指南的每个示例中列出)到这个新文件中。(从本文档的示 例中拷贝的源代码可能不保留空白。)选择 File>Save As 来保存这个文件。浏览至一 个文件夹或新建一个文件夹来保存文件。点击 Save (保存)。 3.4 创建项目 1. 选择Project>Project Wizard来创建新项目。当显示Welcome屏幕时,点击Next> 继续。 2. 在 “Step One: Select a device”对话框中,用下拉菜单来选择器件。 图 3-1: 项目向导——选择器件 点击 Next> 继续。 注: 可在创建新项目之前或之后创建新源文件,这个顺序并不重要。创建新文 件并不会自动将该文件添加到当前打开的项目中。 项目的基本操作及 MPLAB IDE 配置  2006 Microchip Technology Inc. DS51295F_CN 第 27 页 3. 在 “Step Two: Select a language toolsuite”对话框中选择 “Microchip C18 Toolsuite”作为 “Active Toolsuite”。然后点击工具包中 (在 “Toolsuite Contents”下)的每个语言工具并检查或设置与相关可执行文件的路径 (图 3-2)。 图 3-2: 项目向导——选择语言工具包 MPASM 汇编器应指向 “Location”下的汇编器可执行文件 MPASMWIN.exe。 如果没有,应键入或浏览到可执行文件的路径,默认为: C:\mcc18\mpasm\MPASMWIN.exe MPLAB C18 C 编译器应指向 “Location”下的编译器可执行文件 mcc18.exe。 如果没有,应键入或浏览到可执行文件的路径,默认为: C:\mcc18\bin\mcc18.exe MPLINK 目标链接器应指向 “Location”下的链接器可执行文件 MPLink.exe。 如果没有,应键入或浏览到可执行文件的路径,默认为: C:\mcc18\bin\MPLink.exe MPLIB 库管理器应指向 “Location”下的库可执行文件 MPLib.exe。如果没 有,应键入或浏览到可执行文件的路径,默认为: C:\mcc18\bin\MPLib.exe 点击 Next> 继续。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 28 页  2006 Microchip Technology Inc. 4. 在 “Step Three: Name your project”(图 3-3)对话框中,键入项目名并点击 Browse 选择保存项目的文件夹。然后点击 Next> 继续。 图 3-3: 项目向导——项目名和目录 5. 在 “Step Four: Add any existing files to your project”对话框中,浏览至要添加 到项目中的源文件。 首先,选择原先创建好的源文件。如果还未创建源文件,可以以后后再添加 (见图 3-4)。点击 ADD>> 将它添加到项目要使用的文件列表中 (在右侧)。 图 3-4: 项目向导——添加 C 源文件 项目的基本操作及 MPLAB IDE 配置  2006 Microchip Technology Inc. DS51295F_CN 第 29 页 然后,必须添加链接描述文件,告知链接器所选择器件的存储器构成。链接描述 文件位于 MPLAB C18 安装目录下的 lkr 子文件夹中。向下滚动滚动条找到所 选择器件的 .lkr 文件,选中它并点击 ADD>> 将该文件添加到项目中。请参见 图 3-5 中的示例。选择 Next> 继续。 图 3-5: 项目向导——添加链接描述文件 6. 在 Summary (摘要)屏幕中,重新检查 “Project Parameters”(项目参数), 验证器件、工具包以及项目文件的路径是否正确。如果想修改某一项,可以点击 Set Language Tool Locations 打开 Set Language Tool Locations (设置 语言工具路径)对话框。点击 Microchip C18 Toolsuite 旁边的加号来展开它,然后 选中并展开 Executables 文件夹。在展开的列表中点击每个可执行文件来检查其安装 路径是否与 Location 中所示一致。 注: 如果发生错误,可选中文件名并按删除键或通过鼠标右键菜单来删除文 件。将光标移动到 “Source Files”或 “Linker Scripts”上并通过鼠标右 键来向项目添加正确的文件。 项目的基本操作及 MPLAB IDE 配置  2006 Microchip Technology Inc. DS51295F_CN 第 31 页 对于 MPASM 汇编器,要检查其路径是否如图 3-7 所示,为 C:\mcc18\mpasm\MPASMWIN.exe。 图 3-7: 设置语言工具路径:MPASM™ 汇编器 对于 MPLAB C18 编译器可执行文件,要检查其路径是否如图 3-8 所示,为 C:\mcc18\bin\mcc18.exe。 图 3-8: 设置语言工具路径:MPLAB® C18 MPLAB® C18 C 编译器入门 DS51295F_CN 第 32 页  2006 Microchip Technology Inc. 对于 MPLIB 库管理器 (编译器包可执行文件的一部分),要检查其路径是否如图 3-9 所示,为 C:\mcc18\bin\MPLib.exe。 图 3-9: 设置语言工具路径:MPLIB™ 库管理器 对于 MPLINK 链接器,要确保其路径如图 3-10 所示,为 C:\mcc18\bin\MPLink.exe。 图 3-10: 设置语言工具路径:MPLINK™ 链接器 点击 OK 保存这些设置并关闭这个对话框。 项目的基本操作及 MPLAB IDE 配置  2006 Microchip Technology Inc. DS51295F_CN 第 33 页 3.7 检查安装和编译选项 在编译和测试程序之前,还应该检查安装和项目设置。 语言工具应该安装正确,且设置对于这些第一批代码示例要正确,否则将发生错误。 按照如下所述进行这些检查: 1. 选择 Project>Build Options...>Project,并点击 General (常规)选项卡。如果 Include Path和Library Path未如图 3-11中所示设置,则使用Browse按钮来在 MPLAB C18 安装目录中找到这些文件夹。 图 3-11: 编译选项:GENERAL 注: 可为一个包含路径或一个库搜索路径输入多个路径,方法是将路径之间用 分号分隔开: c:\myprojects\h;c:\mcc18\h。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 34 页  2006 Microchip Technology Inc. 2. 有一个选项要更改为与默认设置不同。点击 MPLINK Linker 选项卡。如果 Suppress COD-file generation 复选框没有选中,则选中它: 图 3-12: 编译选项:MPLINK™ LINKER 点击 OK 关闭这个对话框。 注: 如果不选中这个复选框,链接器会生成 MPLAB IDE 不再使用的老 .cod 文 件类型。这个文件格式具有 62 个字符的文件 / 路径长度限制,将导致错误 “name exceeds file format maximum of 62 characters”。 项目的基本操作及 MPLAB IDE 配置  2006 Microchip Technology Inc. DS51295F_CN 第 35 页 3.8 编译和测试 3.8.1 编译项目 如果按照指示完成了安装,就可以选择菜单 Project>Build All 或 Project>Make 来编译 项目了。 可不通过菜单选择,而使用快捷键 Ctrl+F10 和 F10 来进行编译。工具栏中也包含这些 功能的图标,因此按一下功能键或点击一次鼠标即可编译项目: 图 3-13: BUILD ALL 和 MAKE 的图标 项目应正确编译,如 Output (输出)窗口中所示: 图 3-14: 编译成功后的 OUTPUT 窗口 如果来自 MPLINK (链接器)和 MP2HEX (.hex 文件转换器)的消息未显示 “Errors : 0”,则可能有输入错误。在 Output 窗口中找到第一个错误。如果是输 入错误,则在 Output 窗口中的该错误行上双击来在文件 main.c 中编辑错误。如果存 在其他错误,请参阅第 7 章 “疑难解答”。 注: 编译并链接项目中的所有文件称为 “make”或 “build”。 Build All 将重 新编译项目中的所有源文件,而 Make 将仅重新编译自上次编译后更改过 的源文件,因此 Make 编译速度较快,尤其是项目中包含许多源文件时。 注: 将光标放在这些图标上,即可弹出文本标识图标的功能。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 36 页  2006 Microchip Technology Inc. 3.8.2 通过 MPLAB® SIM 测试程序 要在 MPLAB IDE 中测试这些程序,可使用内置的软件模拟器 MPLAB SIM。 1. 选择 Debugger>Select Tool>MPLAB SIM 来启用模拟器。 更改调试工具后要重新编译项目,因为程序存储区可能被清除了。 2. 选择 Debugger>Settings 并点击 Uart1 IO 选项卡。应该选中 Enable Uart1 IO(使 能 Uart1 IO)复选框,且 Output (输出)应该设置为 Window (窗口),如 图 3-15 所示: 图 3-15: 软件模拟器设置:UART1 注: 这个对话框可使来自 printf() 函数的文本传输到软件模拟器的 UART (串行 I/O 外设),然后传输到 MPLAB IDE 的 Output 窗口。 项目的基本操作及 MPLAB IDE 配置  2006 Microchip Technology Inc. DS51295F_CN 第 37 页 选择了软件模拟器后,将在 MPLAB 菜单下出现 Debug Toolbar (调试工具栏, 图 3-16)。 图 3-16: 调试工具栏 欲获得关于项目、 MPLAB 配置和调试技巧的更多信息,请参阅 《MPLAB® IDE 用户 指南》。 图标 功能 Run 运行程序 Halt 暂停程序执行 Animate 连续单步执行指令。使用 Debugger>Halt 或按 Halt 图标来 暂停。 Step Into 单步执行下一条指令 Step Over 单步跳过下一条指令 Step Out 单步跳出子程序 Reset 执行 MCLR 复位 MPLAB® C18 C 编译器入门 DS51295F_CN 第 38 页  2006 Microchip Technology Inc. 注: MPLAB® C 18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 39 页 第 4 章 简单入门程序 4.1 简介 假设读者已熟悉 MPLAB 项目。第 3 章 “项目的基本操作及 MPLAB IDE 配置”给出 了有关 MPLAB 项目的简要概述。更多深入描述,请参见 《MPLAB® IDE 用户指南》。 下面的章节给出了三个简单的入门程序,目的在于使工程师或学生通过使用 MPLAB 集成开发环境熟悉 MPLAB C18 C 编译器。 • 程序 1: “Hello, world!”—— 输出文本 “Hello, world!” • 程序 2:使用软件模拟器点亮 LED ——写入模拟的 PIC 18 器件的 I/O 引脚以点亮 一个指示灯。 • 程序 3:使用软件模拟器使 LED 闪烁 ——扩展第二个程序,使指示灯闪烁。 • 使用演示板 ——演示了如何使用演示板测试程序。 如果有 MPLAB ICD 2 和开发硬件,就能在编译程序 3 后使用 MPLAB ICD 2 在开 发板上调式程序,从而使开发板上的 LED 闪烁。 4.2 程序 1: “HELLO, WORLD!” 4.2.1 写源代码 典型的 “Hello, world!”函数包含以下 C 语句来输出一条消息: printf ("Hello, world!\n"); 函数 main() 如例 4-1 那样编写: 例 4-1: HELLO, WORLD! main() 代码 void main (void) { printf ("Hello, world!\n"); while (1) ; } 注: 由于通常情况下 “Hello, world!”程序是在 PC 上编译、执行,然后返回操 作系统和其他任务的,因此不使用最后的 “while (1)”语句。但是在嵌 入式控制器中,目标单片机是持续运行的,必须做一些事情,因此在此例 中,采用了一个无限循环来使单片机在完成输出 “Hello, world!”这一任务 后保持忙碌。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 40 页  2006 Microchip Technology Inc. 要使用 MPLAB C18 进行编译,代码必须如例 4-2 那样编写。 例 4-2: 程序 1 代码 第一行包含头文件 stdio.h,此文件含有 printf() 函数的原型。#pragma 语句是 MPLAB C18 特有的。 #pragma 语句控制目标单片机的看门狗定时器 , 将看门狗定时 器禁止以防止其干扰程序的执行。 4.2.2 创建程序 1 在名为 first project 的新文件夹下创建一个名为 gs1 的新项目。创建一个新文 件,将例 4-2 中的代码键入或复制、粘贴到此文件中,将该文件保存为 main.c。然 后,将该文件夹中的 main.c 作为源文件添加到项目中,并在项目中添加 18F452.lkr 链接描述文件。 最终的项目应如图 4-1 所示: 图 4-1: 最终项目窗口 #include #pragma config WDT = OFF void main (void) { printf ("Hello, world!\n"); while (1) ; } 注: 看门狗定时器是 PIC18 MCU 的外设,它在默认情况下是使能的。使能看 门狗定时器时,程序最终会因该定时器超时而复位。在最终应用中,可以 使能看门狗定时器来用它检验固件是否正确运行。 注: 切记通过 Configure>Select Device (配置 > 选择器件)选择 PIC18F452 作为当前器件。 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 41 页 4.2.3 设置存储模型 当通过包含 stdio.h 使用标准库时,应为项目选择大代码模型。 转到 Project>Build Options>Project 对话框,并选择 MPLAB C18 选项卡,然后选择 Categories: Memory Model (类别:存储模型)并选中 Large code model (> 64K bytes) (大代码模型 (> 64 KB))。 图 4-2: 选择大代码模型 注: 标准库是按大代码模型构建的,如果没有选中大代码模型,就会发出类型 限定符不匹配的警告。请参见第 7 章 “疑难解答”中的 FAQ-4“为什么会 出现 “Warning [2066] type qualifier mismatch in assignment”(警告 [2066] 指定的类型限定符不匹配)?”。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 42 页  2006 Microchip Technology Inc. 4.2.4 测试程序 1 使用 Project>Build All (项目 > 编译所有)或等效的图标来编译项目。 编译成功后, Run (运行)图标会变为蓝色,表明程序暂停并准备运行。选择 Run 图 标后该图标变为灰色,表明程序正在运行。Halt (暂停)图标变为蓝色,表明程序正 在运行并可被暂停。此外,会在底部的状态栏显示 “Running...”。选择 Halt 图标, 若此时 Output 窗口未打开,就会将其打开 (见图 4-3)。 图 4-3: OUTPUT 窗口:“HELLO, WORLD!” “Hello, world!”文本应该会出现在 Output 窗口的 SIM Uart1 选项卡中。 选择 Reset (复位)图标复位程序 , 然后再次选择 Run 图标将这条消息再次输出到 Output 窗口中。 注: 输出 “Hello, world!”之后,程序继续执行,运行无限循环 while (1) 直 到被暂停。如果程序暂停后立即执行 Run,那么将继续运行无限循环。为 了使程序从头开始重新执行,可在程序暂停后选择 Reset 图标。 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 43 页 4.2.5 解决问题 如果由于输入错误导致编译项目时出错, Output 窗口的最后几行可能会如图 4-4 所 示: 图 4-4: OUTPUT 窗口语法错误 用鼠标双击包含 “syntax error”的行 (见图 4-4),就会打开 MPLAB 编辑器窗 口,光标停留在该窗口中出现该语法错误的行上。 “could not find stdio.h”错误通常意味着没有设置包含路径。请参见第 3.7 节 “检查安装和编译选项”了解有关设置包含路径的信息。 “type qualifier mismatch in assignment”警告可能意味着在使用标准 I/O 时未选择大存储模型。请参见第 4.2.3 节 “设置存储模型”。 “c018i.o is not found”错误可能意味着没有正确设置库路径。请参见第 3.7 节 “检查安装和编译选项”了解有关设置库路径的信息。 如果有消息显示在 c018i.o 中无法找到 “main”的定义,请检查确保 “main”中 的所有字母都是小写的,因为 C 语言是区分大小写的。 “could not find definition of symbol...”错误通常是由于使用了错误的 链接描述文件引起的: 确保使用的是 mcc18\lkr 目录下的 18F452.lkr 文件。在 MPLAB IDE 的某个子目 录中也含有一个供仅使用汇编器的项目使用的链接描述文件。请始终将 mcc18\lkr 链接描述文件用于所有使用 MPLAB C18 编译器的项目。 如果 “Hello, world!”未出现在 Output 窗口中,请尝试下列步骤: 1. 确保选择了软件模拟器 (Debugger>Select Tool>MPLAB SIM)(调试器 > 选择 工具 >MPLAB SIM)。 2. 确保使能了 Uart1 以发送 printf() 文本到 MPLAB IDE 的 Output 窗口,如图 3-15 所示。 3. 选择 Halt 图标 (图 3-16)。 4. 再次执行 Build All。 Output 窗口中应该不会有错误消息,并且在该窗口的最后 一行会显示 “Build Succeeded”(编译成功)消息 (图 3-13)。 5. 选择调试工具栏上的 Reset 图标 (图 3-16)。 6. 选择调试工具栏上的 Run 图标 (图 3-16)。 注: 右击鼠标并选择 Clear Page (清空页面)选项可将 Output 窗口清空。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 44 页  2006 Microchip Technology Inc. 4.2.6 程序 1 “Hello, world!”总结 第一个程序示例到此结束,本示例涉及以下主题: • 编写 MPLAB C18 代码 • 编译 (编译和链接)项目 • 用 MPLAB SIM 测试项目 • 解决初学者易犯的错误 4.3 程序 2:使用软件模拟器点亮 LED 第一个示例演示了在 MPLAB IDE 中使用 MPLAB C18 创建、编译和测试项目的基本步 骤。它尚未涉及目标处理器将利用该代码完成什么任务的细节。在下一程序中,将生 成代码来模拟点亮与 PIC18F452 的某一引脚相连的发光二极管 (Light Emitting Diode,LED)。 4.3.1 创建新项目 在名为 “Second Project”的新文件夹下创建名为 “GS2”的新项目。 确保设置了语言工具并且正确配置了 Build Options,如第 3.7 节 “检查安装和编译选 项”所示。 4.3.2 编写源代码 创建一个新文件并键入例 4-3 中的代码。将其以 main.c 文件名保存在 “Second Project”文件夹中。 例 4-3: 程序 2 代码:main.c 本代码第一行包含了适用于所有 PIC18XXXX 器件的名为 p18cxxx.h 的通用处理器 头文件。此文件会选择与在 MPLAB IDE 中选择的器件相适应的头文件;在本例中为文 件名为 p18f542.h 的头文件 (也可以明确地包含该文件)。此文件包含了这些器件 中特殊功能寄存器的定义。 “#pragma config WDT = OFF”与第一个程序中相同。 #include #pragma config WDT = OFF void main (void) { TRISB = 0; /* Reset the LEDs */ PORTB = 0; /* Light the LEDs */ PORTB = 0x5A; while (1) ; } 注: 在 MPLAB C18 中, main 函数的返回值声明为 void,因为嵌入式应用程 序不会返回到另一个操作系统或函数。 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 45 页 本例将使用 PORTB 寄存器 8 位 I/O 端口的 4 个引脚。 “TRISB = 0”将 PIC18F452 器件的 TRISB 寄存器清零。 TRIS 寄存器控制端口上 I/O 引脚的方向。端口引脚可以是输入引脚,也可以是输出引脚。将该寄存器的所有位 清零将使 8 个引脚都成为输出引脚。 “PORTB = 0”将 PORTB 寄存器的 8 个引脚都设置为 0 或低电压。 “PORTB = 0x5A”将 PORTB 的 4 个引脚设置为 1 或高电压。 (0x5A = 0b01011010)。 当在 PIC18F452 中执行此程序时,与其中一个引脚正确连接的 LED 的电平将会升高, 点亮 LED。 将 main.c 作为源文件添加到项目中。选择 18F452.lkr 文件作为项目的链接描述文 件。项目窗口应如图 4-5 所示。 图 4-5: GS2 项目 4.3.3 编译程序 2 通过 Project>Build All 编译项目。如有错误,请检查语言工具的路径以及编译选项是否 正确,或者请参见第 4.2.5 节 “解决问题”或 第 7 章 “疑难解答”。 注: 一个便于记忆如何配置 TRIS 寄存器的方法是:将位设置为 0 表示输出, 因为零 (0)像字母 O (Output,输出)(O = 0)。将位设置为 1 表示输 入,因为数字一 (1)像字母 I (Input,输入)(I = 1)。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 46 页  2006 Microchip Technology Inc. 4.3.4 测试程序 2 如同第一个程序,将使用 MPLAB IDE 中的软件模拟器测试此代码。确保使能了软件模 拟器。如果没有预先选择软件模拟器,就需要重新编译项目。 要测试代码,必须监视 PORTB 上的引脚状态。 MPLAB IDE 中有两种方法可以完成此 任务。 4.3.4.1 将光标置于变量之上 成功编译项目后,使用鼠标将光标置于编辑器窗口中的变量名之上,以显示变量的当 前值。在运行程序之前,将光标放在 PORTB 上应该显示其值为零 (见图 4-6): 图 4-6: 执行程序前将光标置于 PORTB 上 单击 Run 图标 (或选择 Debug>Run (调试 > 运行)),然后单击 Halt 图标并再次将 光标置于该变量上。此时其值应为 0x5A (见图 4-7): 图 4-7: 执行程序后将光标置于 PORTB 上 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 47 页 4.3.4.2 使用 WATCH (观察)窗口 检查变量值的第二种方法是将其拖放到 Watch 窗口中。选择 View>Watch (视图 > 观 察)打开一个新的 Watch 窗口 (见图 4-8)。 图 4-8: 新 Watch 窗口 现在将 Watch 窗口拖离源文件窗口直到两窗口无任何重叠。选中 main.c 中的单词 PORTB。当该单词处于高亮状态时,将其拖动到 Watch 窗口的空白区域。 Watch 窗 口现在与图 4-9 相似。 图 4-9: WATCH 窗口中的 PORTB 变量 注: 如果 PORTB 的值为 0x5A,则表明此前已执行了程序。双击 Watch 窗口中 的值,键入零使之清零。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 48 页  2006 Microchip Technology Inc. 选择 Run 图标,数秒后再选择 Halt 图标。 Watch 窗口中应该显示 PORTB 的值为 0x5A (见图 4-10)。 图 4-10: 程序执行后的 WATCH 窗口 双击 Watch 窗口中 PORTB 的值 0x5A 使之高亮,然后键入任意其他 8 位值。依次选 择 Reset 和 Run,等待数秒后按下 Halt,将会看到该值返回到 0x5A。 4.3.5 程序 2 总结 第二个程序示例到此结束。该示例演示了以下主题: • 使用带有特定处理器的寄存器定义的包含文件 • 编写代码设置 PIC18F452 中 PORTB 寄存器的位 • 使用鼠标查看寄存器的值 • 通过拖放向 Watch 窗口添加变量或寄存器 • 使用 Watch 窗口查看变量或寄存器的内容 • 在 Watch 窗口中改变变量或寄存器的值 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 49 页 4.4 程序 3:使用软件模拟器使 LED 闪烁 4.4.1 修改源代码 本程序将在上一程序的基础上使 PORTB 上的 LED 闪烁。修改上一程序使之循环运 行,以交替地将引脚设置为高电平或低电平。将程序 2 的代码修改为例 4-4 所示: 例 4-4: 程序 3 代码 现在 while() 无限循环中的代码会不断地将 PORTB 的 4 个引脚置 1 和清零。 这样会产生使 LED 闪烁的效果吗? PIC18F452 指令的执行速度非常快,通常小于一微秒,具体取决于时钟速度。 LED 可 能在不断地点亮-熄灭,但是非常快,以至于肉眼无法察觉它们是在闪烁的。处理器 的时钟频率可由软件模拟器控制。选择 Debugger>Settings (调试器 > 设置)显示 Simulator Settings (软件模拟器设置)对话框 (见图 4-11): 图 4-11: 软件模拟器设置 #include #pragma config WDT = OFF void main (void) { TRISB = 0; while (1) { /* Reset the LEDs */ PORTB = 0; /* Light the LEDs */ PORTB = 0x5A; } MPLAB® C 18 C 编译器入门 DS51295F_CN 第 50 页  2006 Microchip Technology Inc. 4.4.2 选择跑表 (Stopwatch) 在 Osc/Trace (振荡器 / 跟踪)选项卡上,处理器频率的默认设置为 20 MHz。如果显 示的不是 20 MHz,请将其修改到与图 4-11 中的设置相匹配。然后单击 OK。 引脚电平变高和变低之间的时间间隔可用 MPLAB 跑表测定。选择 Debugger>Stopwatch (调试器 > 跑表)显示 MPLAB 跑表 (见图 4-12)。 图 4-12: 跑表 Stopwatch 窗口也显示当前的处理器频率设置为 20 MHz。为了测定 LED 点亮和熄灭 之间的时间间隔,要在代码的恰当位置设置断点。使用鼠标右键来设置断点。 将光标放在包含 PORTB 的第 12 行上并右击鼠标,将显示如图 4-13 所示的调式菜单。 图 4-13: 鼠标右键菜单 注: 如果无法从下拉菜单中选择 Stopwatch,可能是由于没有设置软件模拟器 (Debugger>Select Tool>MPLAB SIM)。 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 51 页 4.4.3 设置断点 从右键弹出菜单中选择 “Set Breakpoint”(设置断点),应该在屏幕的当前行显示一 个断点,由左侧空白区域中的红色 “B”图标表示 (见图 4-14)。 图 4-14: 断点 在第 15 行 (此行将值 0x5A 发送到 PORTB)设置第二个断点。此时编辑器窗口中应 该有两个断点,与图 4-15 相似: 图 4-15: 第二个断点 注: 如果无法设置断点,可能是因为尚未编译项目。选择 Project>Build All 并在 随后尝试重新设置断点。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 52 页  2006 Microchip Technology Inc. 4.4.4 运行程序 3 选择 Run 图标,程序应被执行,并随后在第一个断点处停止,由绿色的箭头指示。注 意跑表已经测量了到达第一个断点所花的时间 (见图 4-16)。 图 4-16: 运行到第一个断点 跑表读数为 7.000000 微秒,表示程序从复位到运行至该断点用了 7 微秒。 再次选择 Run 使程序运行至第二个断点 (见图 4-17): 图 4-17: 运行到第二个断点 此时跑表读数为 7.200000 微秒,表明从上一断点运行到此处用了 0.2 微秒。再次选择 Run 循环返回至第一个断点 (见图 4-18): 图 4-18: 循环返回至第一个断点 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 53 页 4.4.5 分析程序 3 我们可以回答前面提出的问题了。跑表读数为 8.000000 微秒,因此执行一次循环的用 时为 8.0 –7.2 = 0.8 微秒。如果 LED 每微秒点亮并熄灭的次数多于一次,对于肉眼来 说太快而无法分辨。要使 LED 以可被感知的速率闪烁,就必须降低处理器频率,或者 必须添加一些延时。 如果应用程序所需要做的只是使这些 LED 闪烁的话,就可以降低处理器频率。因为这 样做会使所有的代码都运行得非常慢,完成其他任务而不是使 LED 闪烁的代码也会运 行得很慢。更好的解决方案是添加一段延时。 4.4.6 添加一段延时 延时可以是一个使某个变量递减很多次的简单子程序。对本程序而言,延时子程序 可按例 4-5 编写: 例 4-5: 延时程序 将其添加到 main.c 的代码中,并在 LED 熄灭和点亮后分别插入对该延时函数的调用 (见例 4-6)。 例 4-6: 加入了延时的程序 3 代码 void delay (void) { int i; for (i = 0; i < 10000; i++) ; } #include #pragma config WDT = OFF void delay (void) { unsigned int i; for (i = 0; i < 10000; i++) ; } void main (void) { TRISB = 0; while (1) { /* Reset the LEDs */ PORTB = 0; /* Delay so human eye can see change */ delay (); /* Light the LEDs */ PORTB = 0x5A; /* Delay so human eye can see change */ delay (); MPLAB® C 18 C 编译器入门 DS51295F_CN 第 54 页  2006 Microchip Technology Inc. 4.4.7 编译程序 3 在将源代码作了如上修改后再次选择 Project>Build All 来重新编译项目,并向写有 PORTB 的第 18 行和第 23 行添加断点。使用跑表测试代码。 代码中其他位置可能还会显示前面设置的断点。使用鼠标右键菜单 Remove Breakpoint (移除断点),只留下需要的第 18 行和第 23 行的断点。 再次测定断点间的时间间隔。停止在第一个断点后,按下跑表上的 Zero (清零)按钮 来从此断点开始测量。 如果变量 i 从 10000 开始向下计数,当其为零时测得的时间间隔约为 36 毫秒。记住 当变量 i 被定义为 int 时,其范围为 -32768 至 32767 (见 《MPLAB® C18 C 编译器 用户指南》)。 其最大值 (32767)将使延时增长约 3 倍。如果 i 被声明为 unsigned int,其范围可扩展至 65535,如图 4-19 所示。当设置为此值时,测得的延 时将约为 301 毫秒,这意味着执行一次循环 (有两段延时)需用约 602 毫秒。刚超过 半秒,因此 LED 每秒约闪烁两次。请参见图 4-19。 图 4-19: LED 每 0.6 秒闪烁一次的最终代码 4.4.8 程序 3 总结 第三个程序示例到此结束。该示例涉及以下主题: • 使用特定处理器的包含文件 • 设置软件模拟器处理器频率 • 设置断点 • 使用 MPLAB 跑表测量时间 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 55 页 4.5 使用演示板 本节使用硬件来演示前面的程序,而并非模拟。如果没有适合硬件,可跳过本节。本 节所要求的硬件如下: • MPLAB ICD 2 在线调试器 • J6 上安装有跳线的 PICDEM 2 Plus 演示板 4.5.1 选择 MPLAB ICD 2 按照 MPLAB IDE 安装向导上的指导安装 MPLAB ICD 2。将 PICDEM 2 Plus 板与电源 相连,将 MPLAB ICD 2 上的 ICD 电缆与演示板相连。 使用 Debugger>Select Tool>MPLAB ICD 2 (调试器 > 选择工具 >MPLAB ICD 2)选 择 MPLAB ICD 2 作为硬件调试器。选择 Debugger>Connect (调试器 > 连接)确保 MPLAB ICD 2 已经与 MPLAB IDE 建立了通信。 如果一切均已安装并正确连接, Output 窗口应与图 4-20 相似: 图 4-20: MPLAB® ICD 2 OUTPUT 窗口 4.5.2 烧写代码以便用 MPLAB ICD 2 进行测试 当改变调试器时,必须重新编译项目。点击 Build All 图标。 选择 Debugger>Program (调试器 > 编程)将程序下载到 PICDEM 2 Plus 演示板。 注: 如果因为未找到 MPLAB ICD 2 或者 USB 端口无法打开而导致操作失败, 请检查 MPLAB IDE 文档查看器 (MPDocViewer.exe,在 MPLAB 安装目 录下的 Utilities 文件夹里),其中包含有安装 MPLAB ICD 2 的 USB 驱动程 序的相关信息。 注: 当使用 MPLAB ICD 2 时,会提供特殊的链接描述文件,这样应用代码就不 会使用供 MPLAB ICD 2 调试用的小存储区。这些链接描述文件的名称都以 字符“i”结尾。对当前项目,使用名为 18f452i.lkr 的链接描述文件。 在使用 MPLAB ICD 2 调试时总是使用名称含有 “i”的链接描述文件。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 56 页  2006 Microchip Technology Inc. Output 窗口应该显示与图 4-21 相似的文本: 图 4-21: 编程后 MPLAB® ICD 2 的输出 4.5.3 在演示板上测试程序 3 选择 Run 图标。标识为 RB3 和 RB1 的 LED 应该会开始闪烁 (见图 4-22)。 图 4-22: PICDEM™ 2 PLUS 演示板的顶部 由于 PORTB 的值在 0x5A 与 0x00 之间交替变换以控制 4 个 LED, RB1 和 RB3 应该 闪烁,以表示 0x5A 的低半字节或值 0xA (二进制数 1010)。 注: 这些 LED 被标识为 RB0、 RB1、 RB2 及 RB3 是因为当 J6 上安装了跳线 时它们与 PORTB 的引脚相连。 PORTB 的 8 个端口引脚被称为 RBn,其 中 n 的范围为 0 到 7。这些引脚中只有 4 个连接了 LED。 确保安装 了 J6 跳线 简单入门程序  2006 Microchip Technology Inc. DS51295F_CN 第 57 页 LED 很可能闪烁得比前面在程序 3 中使用软件模拟器中的跑表时慢。这是因为 PICDEM 2 Plus 演示板带有的振荡器是 4 MHz 的,而使用软件模拟器时时钟频率为 20 MHz。延时 循环的值可以减小到 10000 以加快闪烁。 4.5.4 对演示板上的处理器编程 当 MPLAB ICD 2 作为调试器工作时,可以单步执行程序,可将变量输入到 Watch 窗 口,可以像在软件模拟器中一样运行和暂停程序。 当程序运行完全正常后,就可以将它烧写到目标器件中,从而无需连接 MPLAB ICD 2 和 PC 即可运行。 4.5.5 取消选定 MPLAB ICD 2 作为调试器 要取消 MPLAB ICD 2 作为调试器,请选择 Debugger>Select Tool>None (调试器 > 选择工具 > 无)。 4.5.6 设置 MPLAB ICD 2 作为编程器 选择 Programmer>Select Programmer>MPLAB ICD 2 (编程器 > 选择编程器 >MPLAB ICD2)将 MPLAB ICD 2 使能为编程器。 注: 跑表是软件模拟器的一种调试功能。 MPLAB ICD 2 不具备等效的功能。 注: 当使用 MPLAB ICD 2 作为调试器时,会将特殊的代码下载到目标器件中, 器件进入在线调试模式。对于最终应用,应关闭 MPLAB ICD 2 功能。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 58 页  2006 Microchip Technology Inc. 4.5.7 烧写器件 要将我们的代码下载并烧写到 PIC18F452 中,请选择 Programmer>Program (编程 器 > 烧写)。 Output 窗口应该会显示结果 (见图 4-23): 图 4-23: 烧写后 MPLAB® ICD 2 的输出 现在可以将 MPLAB ICD 2 与 PICDEM 2 Plus 断开。如果按下 PICDEM Plus 板上的 RESET (复位)按钮 (S1), LED 就会像之前一样开始闪烁,表明固件已被成功地 烧写到了最终应用中。 4.5.8 演示板使用总结 在演示板上实现较短的 C 程序的说明到此结束。本程序示例涉及以下主题: • 选择 MPLAB ICD 2 作为调试器 • 使用 MPLAB ICD 2 调试演示板 • 选择 MPLAB ICD 2 作为编程器 • 使用 MPLAB ICD 2 将最终固件烧写到应用中。 注: 现在调试已完成,可使用原来的链接描述文件 18f452.lkr 来代替在使用 MPLAB ICD 2 进行调试时的 18f452i.lkr。 MPLAB® C 18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 59 页 第 5 章 特性 5.1 概述 本章将讲述可通过 MPLAB 用户界面控制的 MPLAB C18 的很多特性。范例项目将展示 MPLAB C18 和 MPLAB 调试器的一些特性。可通过将范例中的源代码复制并粘贴到 MPLAB 编辑器中创建所有这些项目。 本章涉及以下主题: • MPLAB 项目编译选项 - General 选项 - Memory Model 选项 - Optimization 选项 • 演示:代码优化 • 演示:在 Watch 窗口中显示数据 - 基本数据类型 - 数组 - 结构 - 指针 - 映射文件 5.2 MPLAB 项目编译选项 MPLAB 项目管理器中含有控制 MPLAB C18 编译器、MPASM 汇编器及 MPLINK 链接 器的设置。可为整个项目设置项目选项,也可为每个源文件分别调整项目选项。 项目编译选项具有如下选项卡来控制项目的语言工具选项。 • General (常规)——为项目设置路径。 • MPASM/C17/C18 Suite (MPASM/C17/C18 工具包)——将编译目标设置为标 准或库。 • MPASM Assembler (MPASM 汇编器)——控制 MPASM 开关选项,如是否区 分大小写、是否启用 PIC18XXXX 扩展模式、十六进制文件格式、警告及错误消 息。 • MPLINK Linker (MPLINK 链接器)——确定 HEX 文件的格式,以及映射文件和 调试输出文件的生成。 • MPLAB C18 —— 设置 general、 memory model 及 optimization 选项。 注: 可为每个文件分别定制编译设置。选择 Project>Build Options...> (项目 > 编译选项 > 文件名)显示项目中各文件的选项。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 60 页  2006 Microchip Technology Inc. MPLAB C18 对话框具有 3 个分类,可从 Categories (分类)下拉菜单中选择。 • General 选项 • Memory Model 选项 • Optimization 选项 5.2.1 General 选项 选择 Project>Build Options...>Project 显示控制整个项目选项的对话框。MPLAB C18 选项卡具有以下设置 (见图 5-1): 图 5-1: 项目的 General 选项对话框 Diagnostic level (诊断级别)——通过以下三个设置控制诊断输出: - 仅输出错误 - 输出错误及警告 - 输出错误、警告及消息 Default storage class (默认存储类别)——设置局部变量的默认存储类别。可通过 在定义各局部变量时将其声明为所希望的类别改写。 - Auto (自动)——这是默认设置,允许可重入的代码。这是在扩展模式中允 许使用的惟一存储类别。 - Static (静态)——局部变量和参数将被静态分配,因而存取这些变量和参数 所需代码量较小。仅在非扩展模式中才允许使用。 - Overlay (重叠)——局部变量及参数将被静态分配。此外,可能的话,局部 变量将会与其他函数的局部变量重叠。仅在非扩展模式中才允许使用。 特性  2006 Microchip Technology Inc. DS51295F_CN 第 61 页 Enable integer promotions (启用整型提升)—— ANSI C 标准要求算术运算以 int 精度 (16 位)或更高精度执行。禁用此选项有利于缩短应用程序的代码长度。若要求 与 ANSI C 兼容,应选中此复选框。 Treat ‘char’ as unsigned (将 char 视为无符号型)—— 因为 PIC18XXXX 器件的数据 总线是 8 位的,因而计算时通常使用 0 至 255 (0xFF)之间的值。正常情况下, char 定义一个值在 -128 至 127 之间的变量。将普通的 char 视为无符号型 (unsigned)将 只允许在 0 至 255 之间的正值,在一些用 8 位单片机处理长度较短变量的应用中,这样 做可能更适合于计算。 Extended mode (扩展模式)——允许使用 PIC18XXXX 扩展模式进行编译。当使用 支持扩展模式的 PIC18XXXX 器件时,必须使用恰当的链接描述文件。扩展模式链接 描述文件的名称以 “_e”结尾,如 18f2520_e.lkr。 Macro Definitions (宏定义)——可通过 Add (添加)按钮向宏定义段添加宏。这 与 《MPLAB® C18 C 编译器用户指南》中 “简介”部分描述的 -D 命令行选项是等效 的。 Inherit global settings (继承全局设置)——当选中此复选框时,文件会继承项目的 所有设置。 Use Alternate Settings (使用其他设置)——当选中此复选框时,设置仅适用于当前 文件。允许设置当前 MPLAB 对话框不支持的其他编译器命令行选项。更多有关编译 器开关选项的信息请参见 《MPLAB® C18 C 编译器用户指南》。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 62 页  2006 Microchip Technology Inc. 5.2.2 Memory Model 选项 该对话框可单独控制编译器的存储模型 (见图 5-2)。 图 5-2: MEMORY MODEL 选项对话框 Code Model (代码模型)—— 将程序存储器指针的默认长度设置为 16 位或 24 位。 可通过声明该指针为 near (16 位)或 far (24 位)改写默认设置。使用 16 位指针 (小代码模型)可提高代码效率,但如果指针指向的是程序存储器大于 64 KB 的器件 中的程序存储数据 (romdata),就应该使用 24 位指针 (大代码模型)。 Data Model (数据模型)—— 默认数据段 (idata 和 udata)位于快速操作 RAM (Access RAM )中 (小代码模型)或分区 RAM (大代码模型)中。可通过将各变量 声明为 near 或 far 并在正确的存储区中创建段来改写特定变量的位置。 Stack Model (堆栈模型)——设置数据堆栈是否能延伸到一个存储区之外。堆栈的 大小和位置在链接描述文件中设置。如果链接描述文件将堆栈定义为延伸到单个存储 区外,此堆栈应该被设置为 “Multi-bank model”(多存储区模型)。如果使用的堆栈 较大,由于数据堆栈指针需要按 16 位而不是 8 位进行算术运算,因而会使性能略微下 降。 注: 小代码模型只能用于非扩展模式。 特性  2006 Microchip Technology Inc. DS51295F_CN 第 63 页 5.2.3 Optimization 选项 该对话框可单独控制编译器的各种优化 (见图 5-3)。有关每种优化的详细信息,请参 见 《MPLAB® C18 C 编译器用户指南》中的 “优化”一章。 通常来说,在调试代码时,推荐使用 Debug (调试)设置。 图 5-3: OPTIMIZATION 选项对话框 可通过 Generate Command Line (生成命令行)下的单选按钮控制优化。有关各种 优化的详细信息,请参见 《MPLAB® C18 C 编译器用户指南》中的 “优化”一章。 有四种设置: Disable (禁止)——禁止所有优化 Debug —— 启用大多数优化,但禁止一些不利于调试的优化,特别是合并相同字符 串、代码排序及 WREG 跟踪。 Enable all (启用所有)——启用所有优化。 Custom (定制)—— 启用选中的优化。 Procedural-abstraction passes ( 过程抽象次数)——可多次执行过程抽象优化。 默认情况下运行 4 次过程抽象。也可尝试运行更多次过程抽象以进一步缩短代码,但 这样做可能会产生太多同时被抽象的函数,导致运行时返回堆栈溢出。可设置过程抽 象次数少于 4 次以使对返回堆栈的影响最小。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 64 页  2006 Microchip Technology Inc. 5.3 演示:代码优化 本节将通过一个示例讲述代码优化如何影响项目调试。在无优化的情况下创建并编译 代码。单步执行代码演示代码的预期行为。 之后,代码将被优化并会看到单步执行仍能产生正确的操作,但是代码的执行流程发 生了改变 (被优化),使得调试更加困难。 5.3.1 创建优化项目 要进行演示,通过 Project>New... (项目 > 新建)在 MPLAB IDE 中创建一个新项目 (见图 5-4)。将其命名为 “Optimizations”并创建一个名为 “More Projects” 的新项目目录。 图 5-4: 创建优化项目 特性  2006 Microchip Technology Inc. DS51295F_CN 第 65 页 使用 File>New (文件 > 新建)创建一个新文件并复制或键入以下代码 (例 5-1)。使 用 File>Save (文件 > 保存)将其以文件名 optimizations.c 保存在 More Projects 目录中。 例 5-1: 优化代码 #include void main (void) { int j = 0; int i; for (i = 0; i < 10; i++) { printf ("%d:\t", i); if (i % 2) { printf ("ODD"); j += i; } else { printf ("EVEN"); j += i; } printf ("\tj = %d\n", j); } while (1) ; } MPLAB® C 18 C 编译器入门 DS51295F_CN 第 66 页  2006 Microchip Technology Inc. 右击项目窗口中的 Source Files 并将源文件 optimizations.c 添加到项目中。右击 项目窗口中的 Linker Scripts,添加链接描述文件 18F452.lkr (见图 5-5)。 图 5-5: 优化项目 5.3.2 启用软件模拟器 按如下方法设置软件模拟器: • 通过 Debugger>Select Tool>MPLAB SIM 将软件模拟器设置为当前调试器。 特性  2006 Microchip Technology Inc. DS51295F_CN 第 67 页 5.3.3 关闭优化 按以下步骤设置调试所需的编译选项: • 选择 Project>Build Options>Project 弹出编译对话框。 • 选择 MPLAB C18 选项卡并选择 Categories: Optimizations 显示如下所示的对话 框。 • 像图 5-6 所示选中 Debug 以禁止不利于调试的优化。 图 5-6: 编译选项:调试时的优化设置 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 68 页  2006 Microchip Technology Inc. 5.3.4 检查设置 • 双击 General 选项卡并查看包含路径及库路径是否如第 3.7 节 “检查安装和编译 选项”那样正确设置。 • 还要检查 Debugger>Settings (调试器 > 设置)并单击 Uart1 IO 选项卡。确保选 中了 Enable Uart1 IO (使能 Uart1 IO)复选框并且 Output (输出)被设置为 Window (窗口)。 5.3.5 编译并测试项目 使用 Project>Build All 或工具栏中的 Build All 图标来编译项目。 单击 Run 图标并检查 Output 窗口以查看代码是否正确执行。 Output 窗口应该显示: 0: EVEN j = 0 1: ODD j = 1 2: EVEN j = 3 3: ODD j = 6 4: EVEN j = 10 5: ODD j = 15 6: EVEN j = 21 7: ODD j = 28 8: EVEN j = 36 9: ODD j = 45 5.3.6 单步执行代码 先后单击 Halt 图标和 Reset 图标以确保准备从头开始执行代码。 在 “for”循环处设置断点并单击 Run 图标使程序在主循环开始处暂停,如图 5-7 所 示: 图 5-7: 优化示例——优化关闭第 1 步 单击 Step Over 按钮开始单步执行代码。再次单击 Step Over 使代码执行到 “if”语 句 (见图 5-8)。 图 5-8: 优化示例——优化关闭第 2 步 特性  2006 Microchip Technology Inc. DS51295F_CN 第 69 页 再次单击 Step Over 使代码执行到该语句的 “else”部分。模运算(%)的结果在第一次循 环时为假,如 Output 窗口所示, Output 窗口的第一行显示为 “Even”(见图 5-9)。 图 5-9: 优化示例——优化关闭第 3 步 继续单击 Step Over 使代码再次执行到 “if”语句 (见图 5-10、图 5-12、图 5-13 和 图 5-14)。 图 5-10: 优化示例——优化关闭第 4 步 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 70 页  2006 Microchip Technology Inc. 图 5-11: 优化示例——优化关闭第 5 步 图 5-12: 优化示例——优化关闭第 6 步 图 5-13: 优化示例——优化关闭第 7 步 图 5-14: 优化示例-优化关闭第 8 步 特性  2006 Microchip Technology Inc. DS51295F_CN 第 71 页 继续单击 Step Over 使代码执行到第 15 行,即函数 “if”部分的 “j += i”语句 (见图 5-15 和图 5-14)。 图 5-15: 优化示例——优化关闭第 9 步 图 5-16: 优化示例——优化关闭第 10 步 这一节演示了无优化情况下的代码运行。如同预期的那样,单步代码执行符合逻辑地 进行着。下一节将展示优化后的代码行为。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 72 页  2006 Microchip Technology Inc. 5.3.7 启用优化 选择 Project>Build Options>Project 对话框,然后选择 MPLAB C18 选项卡 (见 图 5-17)。选择 Categories: Optimization 下拉菜单,然后选中 Enable all 单选按 钮。 图 5-17: MPLAB® C18 编译选项:优化开启 特性  2006 Microchip Technology Inc. DS51295F_CN 第 73 页 使用 Build All 图标重新编译项目。如果还没有设置断点的话,在第 8 行的 “for”语 句处设置断点,然后使用 Step Over 图标单步执行代码 (见图 5-18 到图 5-26)。 图 5-18: 优化示例——优化开启第 1 步 和以前一样,使用 Step Over 图标单步执行代码。 图 5-19: 优化示例——优化开启第 2 步 图 5-20: 优化示例——优化开启第 3 步 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 74 页  2006 Microchip Technology Inc. 图 5-21: 优化示例——优化开启第 4 步 图 5-22: 优化示例——优化开启第 5 步 图 5-23: 优化示例——优化开启第 6 步 图 5-24: 优化示例——优化开启第 7 步 特性  2006 Microchip Technology Inc. DS51295F_CN 第 75 页 图 5-25: 优化示例——优化开启第 8 步 图 5-26: 优化示例——优化开启第 9 步 再一次 Step Over 会产生令人吃惊的结果。上图中,程序计数器箭头在函数的 “if” 部分,而现在程序计数器却跳到了函数的 “else”部分 (见图 5-27)。 图 5-27: 优化示例——优化开启第 10 步 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 76 页  2006 Microchip Technology Inc. 再次单击 Step Over 会看到将要执行代码中 “else”部分的 “j += i”语句 (见图 5-28)。 图 5-28: 优化示例——优化开启第 11 步 这一节演示了代码已经使用 “尾部合并 (tail merging)”技术进行了优化。代码 “if”与 “else”部分的 “j += i”语句由原来分离的两组代码优化为了一组代 码。 单步执行代码时,代码跳到了 “else”子句部分,但实际执行的仍是代码的 “if” 部分。上图中第 15 行的第一个 “j += i”语句已被删除。这一优化在调试时会导致 令人困惑的结果。代码仍按照设计的那样执行,但是编译器将其重新组织了以产生更 少的指令。 5.4 演示:在 WATCH 窗口中显示数据 5.4.1 基本数据类型 MPLAB C18 中的变量可以被添加到 Watch 窗口中。 MPLAB IDE 可用适合每种数据类 型的格式正确显示它们的值。 可以使用一个新的项目完成此演示。选择 Project>New Project,将项目名称设置为 “Data Types”并将项目目录设置为在上一演示中使用的同一目录 (见图 5-29)。 图 5-29: 演示:数据类型 特性  2006 Microchip Technology Inc. DS51295F_CN 第 77 页 该示例代码 (例 5-2)使用 MPLAB C18 的基本数据类型。使用 File>New 创建新文 件,将其保存为 “basic_types.c”,并将这个文件和 18F452.lkr 链接描述文件 添加到项目中。 例 5-2: 数据类型代码 char gC; unsigned char guC; signed char gsC; int gI; unsigned int guI; short int gSI; unsigned short int guSI; short long int gSLI; unsigned short long int guSLI; long int gLI; unsigned long int guLI; float gF; unsigned float guF; void main (void) { gC = 'a'; guC = 'b'; gsC = 'c'; gI = 10; guI = 0xA; gSI = 0b1010; guSI = 10u; gLI = 0x1234; guLI = 0xFA5A; gF = -1.395; guF = 3.14; while (1) ; } MPLAB® C 18 C 编译器入门 DS51295F_CN 第 78 页  2006 Microchip Technology Inc. 选择 View>Watch 显示 Watch 窗口,并通过选中源代码中的变量并将其拖放到 Watch 窗口来添加变量 (见图 5-30)。 图 5-30: 数据类型 WATCH 窗口 编译项目;先后单击 Run 和 Halt。将会按照 basic_types.c 中的设置显示变量的 值。那些发生变化的变量将以红色显示,如图 5-31 所示。 图 5-31: 运行后的数据类型 WATCH 窗口 特性  2006 Microchip Technology Inc. DS51295F_CN 第 79 页 5.4.2 数组 数组在 MPLAB C18 Watch 窗口中以可折叠的项显示,允许其在需要被查看时展开,而在 观察其他变量时折叠起来,以提供更多的空间。为了演示,使用下列代码 (例 5-3)创建 一个新的名为 arrays.c 的源文件和一个名为 “Arrays”的新项目。 例 5-3: 数组代码 将名为 array.c 的文件和链接描述文件 18F452.lkr 添加到这个项目中 (见图 5-32)。 图 5-32: 数组项目 选择 View>Watch 打开一个 Watch 窗口并将名为 “x”和 “i”的数组拖放到 Watch 窗口中 (见图 5-33)。 图 5-33: 数组 Watch 窗口 char x[] = "abc"; int i[] = { 1, 2, 3, 4, 5}; void main (void) { while (1); ; } MPLAB® C 18 C 编译器入门 DS51295F_CN 第 80 页  2006 Microchip Technology Inc. 确保选择了软件模拟器作为调试器,编译项目并运行程序。随后,单击 Halt 可查看数 组。在图 5-34 中,每个数组旁的 “+”号被展开了。注意程序执行后数组中值。 图 5-34: 展开的数组 5.4.3 结构 和数组一样,MPLAB C18 中的结构在 Watch 窗口中也显示为可展开 / 可折叠的成员。 例 5-4 中的演示代码将用来演示结构在 MPLAB C18 Watch 窗口中的显示方式。 例 5-4: 结构代码 struct { int x; char y[4]; } s1 = { 0x5A, “abc” }; struct { int x[5]; int y; } s2 = { { 10, 22, 30, 40, 50 }, 0xA5 }; void main (void) { while (1) ; } 特性  2006 Microchip Technology Inc. DS51295F_CN 第 81 页 用该源文件创建一个项目 (见图 5-35),向其中添加 18F452.lkr 链接描述文件,然 后将软件模拟器设置为调试器并编译项目。 图 5-35: 结构:项目 程序运行之前, Watch 窗口应如图 5-36 所示,此时所有的成员都是展开的: 图 5-36: 结构:WATCH 窗口 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 82 页  2006 Microchip Technology Inc. 在单击 Run 之后单击 Halt, Watch 窗口应该显示储存在结构中的值 (见图 5-37): 图 5-37: 结构:代码执行后的 WATCH 窗口 5.4.4 指针 MPLAB C18 中的指针可用来指向 ROM 或 RAM 中的数据。本演示使用 3 个指针,说 明了它们在 PIC 18 架构中的使用方法。 源代码如例 5-5 所示。将其输入到 MPLAB IDE 中的新文件中,并以文件名 “pointers.c”保存在 “More Projects”文件夹中。 例 5-5: 指针代码 ram char * ram_ptr; near rom char * near_rom_ptr; far rom char * far_rom_ptr; char ram_array[] = "this is RAM"; rom char rom_array[] = "this is ROM"; void main (void) { ram_ptr = &ram_array[0]; near_rom_ptr = &rom_array[0]; far_rom_ptr = (far rom char *)&rom_array[0]; while (1) ; } 特性  2006 Microchip Technology Inc. DS51295F_CN 第 83 页 创建一个名为 “Pointers”的新项目,将 pointers.c 文件作为源文件添加到项目 中,并在项目中添加 18F452.lkr 链接描述文件。项目应如图 5-38 所示: 图 5-38: 指针:项目 选择 Project>Build All 编译项目。先不要运行项目。 选择 View>Watch 打开一个空的 Watch 窗口,然后选中源代码窗口中的 3 个指针和 2 个数组并将它们拖放到 Watch 窗口中,如图 5-39 所示。 图 5-39: 指针:程序运行前的 WATCH 窗口 在执行此演示程序之前,不妨看看程序存储器。注意 Watch 窗口显示名为 “rom_array” 的数组位于程序存储器地址 0x010E 处。选择 View>Program Memory (视图 > 程序存储 器)打开 Program Memory 窗口,向下滚动以查看 0x010E 附近的地址 (见图 5-40)。 图 5-40: 指针:程序存储器 注: 确保选择了窗口底部的 Opcode Hex (十六进制操作码)选项卡。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 84 页  2006 Microchip Technology Inc. 在位于地址 0x010E 处的名为 “rom_array”的 ROM 数组中设置的文本明确地将 “this is ROM”文本存储到程序存储器中。 单击 Run 图标执行程序,然后单击 Halt 图标。 Watch 窗口 (见图 5-41)现在将显示 3 个指针的值,并且文件寄存器 (RAM)区域包含 “this is RAM”字符串。 图 5-41: 指针:程序运行后的 WATCH 窗口 注: 在图 5-40 中,RAM 数组中的文本“this is RAM”也紧随其后显示了出 来。这是为什么呢?这是一个已初始化数据的示例。 RAM 数组是在源代码 中定义的,但当 PIC18 器件最初上电时,并没有设置 RAM 的内容,其中 存储的是随机值。为了在程序运行时初始化 RAM,会执行 MPLAB C18 初 始化代码 (c018i.o 作为预编译的库包含在链接描述文件中),从而将程 序存储器中的这一文本传送到 RAM。 特性  2006 Microchip Technology Inc. DS51295F_CN 第 85 页 可展开数组,以显示其中每个元素的地址 (见图 5-42): 图 5-42: 指针:数组展开后的 WATCH 窗口 选择 View>File Registers (视图 > 文件寄存器)并向下滚动到地址 0x0080 以查看 RAM 数组的内容 (见图 5-43)。 图 5-43: 指针:程序运行后的文件寄存器 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 86 页  2006 Microchip Technology Inc. 5.4.5 映射文件 可由链接器生成映射文件,以提供一个文挡来定义由链接器确定的变量和代码的地址。 要生成映射文件,请选择 Project>Build Project>Project 并选择 MPLINK Linker (MPLINK 链接器)选项卡 (见图 5-44)。选中标有 Generate Map File (生成映射 文件)的复选框。 图 5-44: 生成映射文件 特性  2006 Microchip Technology Inc. DS51295F_CN 第 87 页 用 Project>Build All 重新编译项目,然后使用 File>Open,使用标有 Files of Type (文件类型)的底部下拉菜单将文件分类,使只显示 Map Files (*.map) (映射文 件)。请参见图 5-45。应该已生成了一个名为 pointers.map 的映射文件。 图 5-45: 打开映射文件 选中这个文件并单击 Open (打开)在 MPLAB 编辑器中查看文件。这个文件相当长, 其顶部应该如图 5-46 所示: 图 5-46: pointers.c 映射文件 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 88 页  2006 Microchip Technology Inc. 下向滚动文件,将会看到在 pointers.c 程序中定义的变量 (见图 5-47)。映射文件 显示了这些变量在存储器中的地址以及定义它们的源文件。 图 5-47: pointers.c 中定义的变量 MPLAB® C 18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 89 页 第 6 章 架构 6.1 简介 C 编译器的每个实现都必须支持目标处理器的特定功能。在 MPLAB C18 中, PIC18XXXX 的独特特性要求必须对存储器结构、中断、特殊功能寄存器以及单片机内 核中与标准 C 语言无关的其他方面的细节加以考虑。本章提供了对 PIC18XXXX 某些 方面的概述,数据手册中包含对这些方面的详尽叙述。 • PIC18XXXX 架构 • MPLAB C18 启动代码 • #pragma 伪指令 • 段 • SFR 和软件 / 硬件定时器 • 中断 • 数学函数库和 I/O 函数库 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 90 页  2006 Microchip Technology Inc. 6.2 PIC18XXXX 架构 PIC18XXXX MCU 是 “哈佛架构”的单片机,即程序存储空间和数据存储空间是相互 分离的。返回堆栈有其自身专用的存储区,并且如果特定器件具有片上数据 EEPROM 存储器的话,还会有一个非易失性存储空间。 6.2.1 程序存储器 使用 21 位的程序计数器来寻址程序存储空间,因此可允许 2 MB 的程序存储空间 (见 图 6-1)。通常,PIC18XXXX MCU 拥有 16 KB 至 128 KB 范围的片上程序存储器。有 些器件还允许扩展外部存储器。 复位时,程序计数器被设置为 0,取出第一条指令。中断向量位于地址为 0x000008 和 0x000018 的存储单元中,因此通常会在地址为 0 的存储单元中放置一条 GOTO 指令以 使程序跳过中断向量。 图 6-1: PIC18F452 程序存储器 程序存储器包含 16 位字。大多数指令是 16 位的,但有些是双字的 32 位指令。不能按 奇数字节边界访问指令。 PIC18F 器件带有闪存程序存储器, PIC18C 器件带有一次性可编程 (One-Time-Programmable, OTP)存储器(或在某些情况下,为紫外线(UV)可擦 除窗口器件)。通常,只有将固件烧写到器件中时才会写 OTP 存储器。而可以通过运 行程序来擦除和重写闪存存储器。只需对器件进行少许连接,就可以对 OTP 和闪存器 件编程了,从而能在器件被焊接到目标电路板上后对它们进行编程。 PC<20:0> 1 级堆栈• 31 级堆栈 复位向量 低优先级中断向量 • • CALL、RCALL、RETURN RETFIE 和 RETLW 21 0000h 0018h 8000h 7FFFh 片上 程序存储器 高优先级中断向量 0008h 用户存储空间 读为 0 1FFFFFh 200000h 架构  2006 Microchip Technology Inc. DS51295F_CN 第 91 页 以下是 PIC18 架构的一些重要特性以及 MPLAB C18 与程序存储器有关的功能: MPLAB C18 实现 请参见 《MPLAB® C18 C 编译器用户指南》了解更多关于这些特性的信息。 • 通常通过段属性 code 将指令存储到程序存储器中。 • 可通过段属性 romdata 和 rom 关键字将数据存储到程序存储器中。 • 可对 MPLAB C18 进行配置,为两种存储模型 (小存储模型和大存储模型)生成 代码。在使用小存储模型时,指向程序存储器的指针使用 16 位。大存储模型时使 用 24 位指针。 PIC18 架构 • GOTO 指令和 CALL 指令都是双字 (32 位)指令,可以跳转到程序存储器中的任 何位置。 • 如果执行双字指令的第二个字 (使用 GOTO 指令转移或跳转到指令的中间),它将 始终被执行为一条 NOP 指令。 • 所有指令都按偶数字节边界对齐。 • 在某些 PIC18XXXX 器件中,可以将整个程序存储器或程序存储器的部分空间代码 保护。代码会正确执行但不能被读出或复制。 • 可使用表读指令读取程序存储器,并使用表写指令以特定的代码顺序写程序存储 器。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 92 页  2006 Microchip Technology Inc. 6.2.2 数据存储器 数据存储器在 PIC18XXXX 系列中被称为 “文件寄存器”。它由一个多达 4096 个字节 的 8 位 RAM 组成。在上电时,数据存储器中的值是随机的。数据由 256 字节的存储 区为单位构成。在用存储区选择寄存器 (Bank Select Register, BSR)(寄存器地址 的高 4 位)选定了某个存储区后, PIC18 指令才能只使用寄存器地址的低 8 位来读写 文件寄存器。 12 位指针允许在不指定存储区的情况下间接访问整个 RAM 空间。此外, 可以直接访问 Bank 0 和 Bank 15 中的特殊存储区,而无需考虑分区和 BSR 寄存器的 内容。这些特殊数据存储区被称为快速操作 RAM。大部分特殊功能寄存器位于快速操 作 RAM 的高地址区域中 (见图 6-2)。以上说明只适用于非扩展模式。 图 6-2: PIC18F452 数据存储器 未初始化的数据存储器变量、数组和结构通常用段属性 udata 存储在数据存储器中。 可在 MPLAB C18 中定义已初始化数据,以确保在编译器执行初始化时变量的值正确。 这意味着启动时,存储在程序存储器中的值会被传送到数据存储器中。根据应用程序 需要多大初始化存储区,使用已初始化数据 (而不是在运行时设置数据值)可能会对 程序存储器的使用效率产生不良影响。 因为文件寄存器是 8 位的,所以在使用变量时,应该考虑是将其定义为 int 还是 char。当预计变量的值不会超过255时,将其定义为unsigned char会产生更小更快 的代码。 Bank 0 Bank 1 Bank 14 Bank 15 数据存储器映射 080h 07Fh F80h FFFh 00h 7Fh 80h FFh Bank 4 Bank 3 Bank 2 F7Fh F00h EFFh 3FFh 300h 2FFh 200h 1FFh 100h 0FFh 000h 快速操作 RAM FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h GPR GPR GPR GPR SFR 未用 快速操作 RAM 高 快速操作 RAM 低 Bank 5 GPR GPR Bank 6 至 4FFh 400h 5FFh 500h 600h 未用 读为 00h (SFR) 快速操作存储区 架构  2006 Microchip Technology Inc. DS51295F_CN 第 93 页 6.2.3 特殊功能寄存器 特殊功能寄存器 (SFR)包括 CPU 内核寄存器 (如堆栈指针、 STATUS 寄存器和程 序计数器)和用于单片机外设模块的寄存器 (见图 6-3)。大多数 SFR 位于 Bank 15 中,并可以被直接访问而不需要使用 BSR,除非器件具有更多外设寄存器, 超过了 Bank 15 的 128 字节存储区。那样的话,必须使用 BSR 来读写那些特殊功能 寄存器。 图 6-3: PIC18F452 特殊功能寄存器 6.2.4 返回地址堆栈 CALL 和 RETURN 指令将程序计数器的值压入和弹出返回地址堆栈。返回堆栈是存储器中 一块独立的区域,允许 31 级子程序嵌套。 注: 如果有超过 128 字节的特殊功能寄存器,某些 PIC18 器件会减少 Bank 0 中快速操作 RAM 的数量,并增加 Bank 15 中的快速操作 RAM 的数量。 地址 名称 地址 名称 地址 名称 地址 名称 FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch - FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh - FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah - FF9h PCL FD9h FSR2L FB9h - F99h - FF8h TBLPTRU FD8h STATUS FB8h - F98h - FF7h TBLPTRH FD7h TMR0H FB7h - F97h - FF6h TBLPTRL FD6h TMR0L FB6h - F96h TRISE(2) FF5h TABLAT FD5h T0CON FB5h - F95h TRISD(2) FF4h PRODH FD4h - FB4h - F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h - FF0h INTCON3 FD0h RCON FB0h - F90h - FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh - FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh - FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE(2) FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD(2) FEBh PLUSW0(3) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh - F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h - FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2 F87h - FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h - FE5h POSTDEC1(3) FC5h SSPCON2 FA5h - F85h - FE4h PREINC1(3) FC4h ADRESH FA4h - F84h PORTE(2) FE3h PLUSW1(3) FC3h ADRESL FA3h - F83h PORTD(2) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h - FA0h PIE2 F80h PORTA 注 1: 未用的寄存器,读为 0。 2: 该寄存器在 PIC18F2X2 器件上不存在。 3: 这不是一个物理寄存器。 注: 在使用 MPLAB C18 时,分区通常是透明的,但可使用 #pragma varlocate 伪指令告知编译器变量存储的位置,从而产生更高效的代码。 注: CALL/RETURN 堆栈与由 MPLAB C18 维护的软件堆栈不同。软件堆栈用于 存储自动参数和局部变量,并按照链接描述文件中的定义将它们分配到文件 寄存器存储区中。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 94 页  2006 Microchip Technology Inc. 6.2.5 EEPROM 数据存储器 数据 EEPROM 是独立的非易失性存储器。它可用来在芯片断电时存储数据。它可通过 4 个特殊功能寄存器进行访问,对其进行写操作需要特殊的写顺序。在许多 PIC18XXXX 器件中,该存储区也可被保护,使得数据不能被读出或复制。请参见 《MPLAB® C18 C 编译器用户指南》获取读写数据 EEPROM 存储器的代码示例。 6.2.6 配置存储区 配置位控制 PIC18XXXX 器件的各种模式,包括振荡器类型、看门狗定时器、代码保 护和其他特性。该存储区超过了程序存储器的 21 位地址范围,但可使用表读和表写指 令进行访问。大多数配置位已在编程器件时 (使用 MPLAB PM3、 PICSTART Plus、 MPLAB ICD 2 或其他编程硬件)被设置为了所需的状态。最初编程时,可通过 MPLAB C18 #pragma config 伪指令将这些位置 1,通常应用程序不需要访问存储 器的这一区域。 6.2.7 扩展模式 某些 PIC18XXXX 器件有一种为提高可重入代码效率而设计的备用工作模式。当这些 器件被编程为使用扩展模式时,寻址快速操作 RAM 的方式会受到影响,一些指令的执 行会有所不同,并且可使用某些新的指令和寻址模式。此外,使用扩展模式的应用程 序还需要随 MPLAB C18 安装、名称以 _e 结尾的特殊链接描述文件。 请参见相关的 PIC18XXXX 数据手册了解该模式的有关信息,尤其是在应用程序中使 用了汇编语言代码的情况。 6.3 MPLAB C18 启动代码 预编译代码块必须链接到每个 MPLAB C18 程序中,来初始化寄存器并为编译器设置 数据堆栈。该代码在应用程序启动时执行,然后跳转到应用程序中的 main()。有不同 的启动代码组可供选择,这取决于是否要求在启动时将变量初始化为 0 以及扩展模式 是否使能。请参见 《MPLAB® C18 C 编译器用户指南》了解有关启动代码的信息。 6.4 #pragma 伪指令 按照目标处理器架构的要求,ANSI C 标准为每个 C 实现提供了定义独特语法结构的方 法。这是通过使用 #pragma 伪指令完成的。 MPLAB C18 编译器中最常见的 #pragma 伪指令可标识 PIC18XXXX 中使用的存储器段。例如, #pragma code 告知 MPLAB 18 将该伪指令后的 C 语言代码编译到程序存储器的 “code”段中。对 于每个 PIC18XXXX 器件 ,在每个 PIC18XXXX 器件的相应链接描述文件中定义 code 段,指定执行指令的程序存储区。可以如给出的示例那样插入该伪指令,也可以在该 伪指令后直接跟目标处理器 code 区中的某个地址,从而可以完全控制代码在存储器 中的位置。这通常无关紧要,但在某些应用程序中,如引导加载程序,对应用程序中 某些代码块的执行位置进行严格控制就非常重要。 架构  2006 Microchip Technology Inc. DS51295F_CN 第 95 页 将代码从另一种编译器移植到 MPLAB C18 时,原编译器的 #pragma 伪指令的操作必 须被识别并转换成 MPLAB C18 的类似伪指令。无法被 MPLAB C18 识别的 #pragma 伪指令将被忽略,从而允许将代码从一种架构移植到另一种架构,并且不会出现编译 错误。理解原编译器中 #pragma 伪指令的功能以及新的目标架构是工程师的职责所 在,以在不同的单片机之间有效移植代码。 在为变量分配存储空间时,另一种最常见的 #pragma 伪指令是 #pragma udata 在此声明之后定义的未初始化变量将使用通用寄存器进行存储。 这与为变量和指令位于相同存储空间内的器件编写 C 程序不同。在 PIC18XXXX 上, 程序存储器和文件寄存器存储器有很大不同,因此,必须明确地区分数据存储器和程 序存储器中的存储区。 MPLAB C18 中的 #pragma 伪指令如表 6-1 所示: 表 6-1: MPLAB® C18 #pragma 伪指令 关于这些 #pragma 伪指令及其他伪指令的完整信息,请参见 《MPLAB® C18 C 编译 器用户指南》。 伪指令 用途 code 程序存储器指令。将所有后续指令编译到目标 PIC18XXXX 的程序存储 器段中。 romdata 存储在程序存储器中的数据。将后续静态数据编译到目标 PIC18XXXX 的程序存储器段中。 udata 未初始化的数据。使用 PIC18XXXX 的文件寄存器 (数据)空间存储将 要在后面的源代码中使用的未初始化的静态变量。这些存储单元的值未 被初始化。更多信息,请参见 《MPLAB® C18 C 编译器用户指南》中 的 “启动代码”章节。 idata 已初始化数据。使用 PIC18XXXX 的文件寄存器 (数据)空间存储将要 在后面的源代码中使用的未初始化的变量。 但是,与 udata 不同,这 些单元将被设置为在源代码中定义的值。注意,这意味着这些值将被放 在程序存储器中的某个位置,然后在应用程序开始执行前被编译器初始 化代码传送到文件寄存器中。 config 定义 PIC18XXXX 配置位的状态。这些状态会生成到由链接器输出的 .HEX 文件中,并将与应用固件一同被编程到器件中。 interrupt 将指定 C 函数中的代码编译为高优先级中断服务程序。请参见 《MPLAB® C18 C 编译器用户指南》中的 “中断服务程序”章节。 interruptlow 将指定 C 函数中的代码编译为低优先级中断服务程序。请参见 《MPLAB® C18 C 编译器用户指南》中的 “中断服务程序”章节。 varlocate 指定变量的存放位置,使得编译器不会生成在访问变量时设置存储区的 额外指令。请参见 《MPLAB® C18 C 编译器用户指南》中的 “#pragma varlocate”章节。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 96 页  2006 Microchip Technology Inc. 6.5 段 如上所述,段是 PIC18XXXX 存储器中的各种区域,包括程序存储器、文件寄存器 (数据)存储器、 EEDATA 非易失性存储器和数据堆栈存储区以及其他一些存储区。 通常,程序存储器和数据存储器需要段。随着设计日益复杂,还可能需要其他类型的 段。 段是在链接描述文件中定义的。以下是 PIC18F452 的链接描述文件: 例 6-1: PIC18F452 的链接描述文件示例 该链接描述文件定义名为 page 的主程序存储区,地址从 0x002A 延伸到 0x7FFF。 当遇到 #pragma code 伪指令时,编译器将生成存放到该区域的机器码指令。 为 PIC18F452 的 6 个文件寄存器存储区 (gpr = 通用寄存器存储区)定义了数据存储 器段。由于在 PIC18XXXX 上存储器是分区的,这 6 个区域被各自定义为独立的段。 在遇到 #pragma udata 和 #pragma idata 时,编译器将在这些文件寄存器存储区 中保留区域,来存储随后定义的变量。 accessram 和 accesssfr 段用于定义数据存储器中的快速操作 RAM 区域。 注意,某些区域被标记为 “PROTECTED”。这意味着链接器不会将代码或数据放入那 些区域,除非特别指定。要将代码或数据放入受保护的区域,请使用如下所示的 #pragma 伪指令: #pragma code page 这将导致其后的指令被编译到 page 段中,通常是在链接描述文件中定义的主程序存 储区。 // Sample linker script for the PIC18F452 processor LIBPATH . FILES c018i.o FILES clib.lib FILES p18f452.lib CODEPAGE NAME=vectors START=0x0 END=0x29 PROTECTED CODEPAGE NAME=page START=0x2A END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED SECTION NAME=CONFIG ROM=config STACK SIZE=0x100 RAM=gpr5 架构  2006 Microchip Technology Inc. DS51295F_CN 第 97 页 6.6 SFR 和软件 / 硬件定时器 PIC18XXXX 特殊功能寄存器 (SFR)是单片机文件寄存器区域中的特殊寄存器。包 括控制单片机内核的寄存器,如堆栈指针、 STATUS 寄存器和程序计数器,以及控制 各种外设的寄存器。外设包括输入和输出引脚、定时器、USART 和读写器件 EEDATA 区域的寄存器等。 MPLAB C18 可以通过名称访问这些寄存器,并且可像读写应用程序 中定义的变量那样对它们进行读写。但是使用时仍要小心,因为一些特殊功能寄存器 的特性与变量有所不同。有些特殊功能寄存器只有某些位可用,有些是只读的,还有 些可能会在被访问时影响其他寄存器或器件的操作。 6.6.1 I/O 寄存器 通过读写与器件上的端口引脚相关的寄存器来完成 PIC18XXXX 引脚的输入和输出。 请查看数据手册了解器件的可用端口。每个端口都有 3 个与之相关的特殊功能寄存器。 其中一个称为 TRIS 寄存器,它定义端口引脚的方向:输入或输出。第二个称为 PORT 寄存器,用来读写端口引脚的值;第三个称为 LAT 寄存器,它是一个锁存器,可允许 读写端口上的值,而实际上并不读端口上引脚的当前状态。这在 PIC18XXXX 架构中 很重要,因为需要考虑读 - 修改 - 写操作。存储 I/O 端口寄存器的内容不能像存储变量 一样处理——两者的操作有很大差异。欲知更多信息请参见数据手册。 有些引脚是复用的,在将它们用作数字 I/O 之前可能需要通过其他特殊功能寄存器进 行配置。特别是很多 PIC18XXXX 器件上的 PORTA 也能用作 A/D 转换器的模拟输入。 要将 PORTB 配置为 4 个输入引脚和 4 个输出引脚,在 MPLAB C 18 中可编写下列代 码: 6.6.2 硬件定时器 PIC18XXXX 定时器也是通过特殊功能寄存器配置并访问的。大多数 PIC18XXXX 器件 至少有 3 个定时器。例如,PIC18F452 中的 Timer0 通过 T0CON 寄存器进行配置,并 且可使用两个 8 位寄存器 TMR0L 和 TMR0H 读取和写入其计数器 / 定时器值。 INTCON 寄存器中的某些位可用来将 Timer0 设置为中断源,并且还控制 Timer0 在用 作计数器时是依靠振荡器的输出还是外部信号计数。 6.6.3 软件定时器 正如在任何 C 程序中那样,可以用软件创建延时和定时循环。设计考虑将影响到如何 采用软件定时器和硬件定时器。典型的软件延时循环包括创建一个计数变量,并将其 递减直至为零。软件定时器的缺点在于,如果发生中断,软件定时器的延时将被延长, 并可能变得无法预测。此外,在处理软件延时循环时,程序除了能对中断作出响应外, 什么也不能做。 TRISB = 0xF0 /* configure PORTB as 4 input pins, bits 4-7 and 4 output pins, bits 0-3 */ PORTB = 0x0C /* set pins 0 and 1 low, pins 2 and 3 high */ MPLAB® C 18 C 编译器入门 DS51295F_CN 第 98 页  2006 Microchip Technology Inc. 6.7 中断 中断是 PIC18XXXX 内核的一个功能。定时器、I/O 引脚、USART、A/D 和其他外设均 能导致中断。当发生中断时,应用程序中的代码被暂停,而执行中断服务程序中的代 码。 当中断服务程序结束时,会执行一条 “从中断返回”指令,程序将从停止的地方 恢复执行。 在 PIC18XXXX 中有低优先级中断和高优先级中断两种。决定使用哪种中断是设计应 用时需要考虑的事项。在 MPLAB C18 中可使用这两种中断类型 ,但设计人员必须注 意特定中断操作的细节以保护一些关键内部寄存器的内容。最重要的是要仔细考虑变 量的使用和库 (尤其是在中断服务程序中使用的变量和库)。 当中断发生时,低优先级中断只保存 PC (程序计数器寄存器)。对于高优先级中断, PIC18XXXX 内核将自动保存 PC、 WREG、 BSR 和 STATUS 寄存器。请参见 《MPLAB® C18 C 编译器用户指南》中的 “ISR 现场保护”章节,了解关于在中断过 程中保存应用程序变量的信息。 6.8 数学函数库和 I/O 函数库 MPLAB C18 有用于外设控制、外设软件实现、通用数据处理和数学函数的库。请参见 《MPLAB® C18 C 编译器函数库》(DS51297F_CN)了解对这些库的完整描述。 为这些库提供了源代码,因此可根据应用的需求修改这些库,从而对它们进行定制并 重建。 对外设库进行使用通常要求理解器件数据手册中所描述的外设操作。使用 C 函数库可 以简化外设的初始化和使用。 MPLAB C18 数学函数库包括浮点运算、三角运算和其他运算。在 8 位嵌入式控制器上 使用浮点和复数数学函数时,应该仔细权衡,评估这些运算对于特定设计是否是高效 率的选择。通常,表、插值表或使用其他方法的近似算法会为任务提供足够的精度。 32 位浮点运算执行起来通常需要几百个周期,可能会占用非常大的程序存储空间。 MPLAB® C 18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 99 页 第 7 章 疑难解答 7.1 简介 本章涉及在初学 MPLAB C18 时可能遇到的常见错误消息。本章还回答了许多常见问题 (Frequently Asked Question, FAQ)。 错误消息 • EM-1 链接器错误:“name exceeds file format maximum of 62 characters”(文件 名超过了文件格式要求的最多 62 个字符的限制) • EM-2 链接器错误:“could not find file ‘c018i.o’”(找不到文件 c018i.o) • EM-3 编译器错误 “Error [1027] unable to locate ‘p18cxxx.h’”(错误 [1027] 不能 定位 p18cxxx.h) • EM-4 编译器错误:“Error [1105]symbol ‘symbol-name’ has not been defined.”(错 误 [1105] 符号 “符号名”未定义。) • EM-5 MPLAB IDE 错误:“Skipping link step. The project contains no linker script.” (跳过链接步骤。项目未包含链接描述文件。) • EM-6 编译器错误:Syntax Error (语法错误) • EM-7 链接器错误:“Could not find definition of symbol...”(找不到符号 ... 的定义) 常见问题 (FAQ) • FAQ-1 是否安装了使用 MPLAB C18 所需的 MPLAB IDE 组件? • FAQ-2 需要设置什么才能在 Output 窗口中显示 printf() 语句? • FAQ-3 如何在某处声明一个全局结构 / 联合,这样就不需要在所有引用该变量的 .c 文件中添加 “extern”声明语句了? • FAQ-4 为什么会出现 “Warning [2066] type qualifier mismatch in assignment”(警 告 [2066] 指定的类型限定符不匹配)? • FAQ-5 当我取字符串指针的内容时,结果不是字符串的第一个字符,为什么? • FAQ-6 使用低优先级中断的代码示例在哪里? • FAQ-7 可以使用 16 位变量访问 16 位定时器的特殊功能寄存器 (如 TMR1L 和 TMR1H)吗? • FAQ-8 我如何修复数据存储器段的 “unable to fit section”(不能分配到段)错误? • FAQ-9 我如何修复程序存储器段的 “unable to fit section”(不能分配到段)错误? • FAQ-10 我如何在数据存储器中创建一个大对象 (> 256 字节)? • FAQ-11 我如何将数据表存入程序存储器? • FAQ-12 我如何将数据从程序存储器复制到数据存储器? • FAQ-13 我如何在 C 程序中设置配置位? • FAQ-14 有哪些有关在 C 程序中设置配置位的参考资料? • FAQ-15 我如何使用 printf 输出字符串常量? • FAQ-16 当我对两个字符执行算术运算,并将运算结果赋值给一个整型变量,但我没 有得到期望的值。为什么? MPLAB® C 18 C 编译器入门 DS51295F_CN 第 100 页  2006 Microchip Technology Inc. 7.2 错误消息 EM-1 链接器错误:“name exceeds file format maximum of 62 characters”(文件名超过了文件格式要求的最多 62 个字符的限制) 选择 Project>Build Options…>Project 的 MPLINK 选项卡,选中复选框 Suppress Cod-file generation (禁止生成 Cod 文件)。 COD 文件是较早的格式,现在已不再 使用。 EM-2 链接器错误:“could not find file ‘c018i.o’”(找不到文件 c018i.o) 在 Project>Build Options…>Project 的 General 选项卡中输入正确的目录路径。将 Library Path (库路径)文本框设置为 “C:\mcc18\lib”。 c018i.o 是 MPLAB C18 的启动库。它设置堆栈,初始化变量,然后跳转到应用程序的 main() 函数。 EM-3 编译器错误 “Error [1027] unable to locate ‘p18cxxx.h’”(错误 [1027] 不能定位 p18cxxx.h) 在 Project>Build Options&…>Project 的 General 选项卡上输入正确的目录路径。将 Include Path (包含路径)文本框设置为 “C:\mcc18\h”。 p18cxxx.h 是一个通 用头文件,包含特定于选定处理器的头文件。 EM-4 编译器错误:“Error [1105]symbol ‘symbol-name’ has not been defined.”(错误 [1105] 符号 “符号名”未定义。) 如果符号名是一个特殊功能寄存器 (如 TRISB),请确认已包含了通用处理器头文件 (#include )或特定于处理器的包含文件 (如 #include )。特殊功能寄存器在特定于处理器的头文件中声明。还要确认特殊功 能寄存器全部为大写字母 (即 TRISB 而非 trisb),因为 C 语言是区分大小写的,特 殊功能寄存器全用大写字母声明。 如果符号名不是特殊功能寄存器,请确认在使用前已定义符号,并且符号名拼写正确。 EM-5 MPLAB IDE 错误:“Skipping link step. The project contains no linker script.”(跳过链接步骤。项目未包含链接描述文件。) 请确认项目包含一个链接描述文件。链接描述文件在 MPLAB C18 安装目录的 lkr 子 目录中。 EM-6 编译器错误:Syntax Error (语法错误) 这通常是源代码中的拼写错误。双击 Output 窗口中的错误行,就能转到 MPLAB 编辑 器窗口,并且光标停留在该窗口中引起错误的行上。通常采用颜色区分代码的语法会 显示错误。 EM-7 链接器错误:“Could not find definition of symbol...”(找不到符号 ... 的定义) 这可能是由于使用了错误的链接描述文件导致的。 MPLAB C18 的链接描述文件包含其 他库文件。请确认使用的是 MPLAB C18 安装目录 lkr 子目录中的链接描述文件。 项目编译通过,但在链接器尝试链接时,显示以下错误: Error - could not find definition of symbol 'putsMYFILE' in file 'C:\My Projects\myfile.o'. Errors : 1 可能是 C 文件同汇编文件同名,尽管扩展名不同。仔细查看 Output 窗口以判断是否链 接器尝试生成两个文件名相同的 .o 文件。这样很有可能会忽略项目中同名的第一个文 件。重命名文件,这样文件就不会同名了。 疑难解答  2006 Microchip Technology Inc. DS51295F_CN 第 101 页 7.3 常见问题 (FAQ) FAQ-1 是否安装了使用 MPLAB C18 所需的 MPLAB IDE 组件? 下面是检查安装的组件的方法: 转到 Windows 的开始菜单,浏览到 Microchip 文件夹,选择 MPLAB>Set Up MPLAB Tools,验证是否安装了正确的组件。请参见图 1-1,了解 MPLAB C18 所需的最小 IDE 安装选择。 FAQ-2 需要设置什么才能在 Output 窗口中显示 printf() 语句? 在 MPLAB IDE 中,选择 Debugger>Select Tool>MPLAB SIM,启用软件模拟器,并访 问 debugger 菜单。然后选择 Debugger>Settings,单击 Uart1 I/O 选项卡。请确认选 中了 “Enable Uart1 I/O”,在 Output 框中选中 Window 选项 (见图 3-15)。 FAQ-3 如何在某处声明一个全局结构 / 联合,这样就不需要在所有引用该变 量的 .c 文件中添加 “extern”声明语句了? 在头文件中创建一个 typedef: typedef union { struct { unsigned char Outstanding_Comms_Req:1; }; unsigned char All_Flags; } RS485_t; 然后在一个 .c 文件中使用: RS485_t RS485_Flags; 要定义联合,可以在其他 .c 文件中使用: extern RS485_t RS485_Flags; 还可以将 extern 写入一个头文件中,然后将该头文件包含在 .c 文件中。 FAQ-4 为什么会出现 “Warning [2066] type qualifier mismatch in assignment”(警告 [2066] 指定的类型限定符不匹配)? MPLAB C18 提供的库是使用大代码模型编译 (-ml 命令行选项)的。默认情况下, MPLAB IDE 和编译器将使用小代码模型编译应用程序。例如,随编译器提供的 printf 函数期望收到 “const far rom char *”,但没有为应用程序选择大代码 模型时,应用程序实际发送 “const near rom char *”到 printf 函数。正是 far 和 near 间的差别引起了“type qualifier mismatch in assignment”警告。要消除这 些警告,应采取以下三种措施中的一种: 1. 使用小代码模型重新编译随 MPLAB C18 提供的库 (仅在所有应用程序均使用 小代码模型时推荐); 2. 在 IDE 中为特定应用程序启用大代码模型 (可能会增加代码尺寸);或 3. 将常量字符强制转换为常量 far rom 字符串指针,如: printf ((const far rom char *)”This is a test\n\r”); MPLAB® C 18 C 编译器入门 DS51295F_CN 第 102 页  2006 Microchip Technology Inc. FAQ-5 当我取字符串指针的内容时,结果不是字符串的第一个字符,为什 么? const char *path = "file.txt"; while(*path) // while end of string not found { path++; length++; } MPLAB C18 将常量字符串存储在程序存储器中。但 path 是一个指向数据存储器的指 针。当取 path 指针的内容时,访问的是数据存储器,而非程序存储器。解决方法是 添加 rom 关键字,使指针指向 ROM 单元,而非 RAM。 const rom char *path = "file.txt"; FAQ-6 使用低优先级中断的代码示例在哪里? 请参见 《MPLAB® C18 C 编译器用户指南》中的 #pragma interruptlow 和 “示例” 一章。 FAQ-7 可以使用 16 位变量访问 16 位定时器的特殊功能寄存器 (如 TMR1L 和 TMR1H)吗? 请不要将 TMR1H 和 TMR1L 组合成一个 16 位变量进行访问。两个特殊功能寄存器的 读写顺序非常关键,因为只有读 / 写完 TMR1L 寄存器才表示读 / 写完了整个 16 位定 时器。如果编译器正好在写 TMR1H 前写了 TMR1L,那么就不会将写入 TMR1H 的数 据装入定时器的高字节。同样,编译器先读哪个字节也是不可控制的。 FAQ-8 我如何修复数据存储器段的 “unable to fit section”(不能分配到 段)错误? MPLAB C18 提供了两种不同的数据存储器段类型: • udata——包含静态分配的未初始化用户变量 • idata——包含静态分配的已初始化用户变量 在 MPLAB C18 中每种段类型都有默认的段 (如 .udata_foobar.o)。 例如,给出以下位于 foobar.c 中的源代码: unsigned char foo[255]; int bar; void main (void) { while (1) ; } 该代码会导致下列错误: Error - section ‘.udata_foobar.o’can not fit the section. Section ‘.udata_foobar.o’ length = 0x00000101. 疑难解答  2006 Microchip Technology Inc. DS51295F_CN 第 103 页 有两种方法可解决这个错误: 1. 将 foobar.c 分成多个文件: foo.c unsigned char foo[255]; void main (void) { while (1) ; } bar.c int bar; 2. 使用 #pragma udata 伪指令创建一个独立的段,包含 foo 和 bar 变量: foobar.c #pragma udata foo unsigned char foo[255]; #pragma udata bar int bar; void main (void) { while (1) ; } FAQ-9 我如何修复程序存储器段的 “unable to fit section”(不能分配到 段)错误? MPLAB C18 提供了两种不同的程序存储器段类型: • code——包含可执行指令 • romdata——包含变量和常量 默认情况下, MPLAB IDE 仅启用不影响调试的优化。要减少代码段所用的程序存储器 空间,请启用所有的优化。要在 MPLAB IDE 中启用优化,请选择 Project>Build options…>Project,单击 MPLAB C18 选项卡,并设置 Categories: Optimization 启 用所有优化。 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 104 页  2006 Microchip Technology Inc. FAQ-10 我如何在数据存储器中创建一个大对象 (> 256 字节)? 默认情况下, MPLAB C18 假设对象不超过存储区边界。要安全使用大于 256 字节的 对象,需要执行下列步骤: 1. 必须使用 #pragma idata 或 #pragma udata 伪指令将对象分配到恰当的段 中: #pragma udata buffer_scn static char buffer[0x180]; #pragma udata 2. 必须通过指针访问对象: char * buf_ptr = &buffer[0]; ... // examples of use buf_ptr[5] = 10; if (buf_ptr[275] > 127) ... 3. 必须在链接描述文件中创建一个跨越多个存储区的区域: - 修改前的链接描述文件: DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF - 修改后的链接描述文件: DATABANK NAME=big START=0x200 END=0x37F PROTECTED DATABANK NAME=gpr3 START=0x380 END=0x3FF 4. 必须通过在链接描述文件中添加 SECTION 伪指令,将对象所在的段 (在第 1 步 中创建)分配到新的区域 (在第 3 步中创建): SECTION NAME=buffer_scn RAM=big FAQ-11 我如何将数据表存入程序存储器? 默认情况下,MPLAB C18 将用户变量存入数据存储器。rom 限定符用于指示将对象分 配到程序存储器中: rom int array_of_ints_in_rom[] = { 0, 1, 2, 3, 4, 5 }; rom int * q = &array_of_ints_in_rom[0]; 在上面的示例中, array_of_ints_in_rom 表示程序存储器中的整型数组。q 是一 个指针,可用于遍历数组中的元素。 疑难解答  2006 Microchip Technology Inc. DS51295F_CN 第 105 页 FAQ-12 我如何将数据从程序存储器复制到数据存储器? 对于指针类型,使用下列某个标准库函数: 对于非指针类型,可以直接分配。 示例: rom int rom_int = 0x1234; ram int ram_int; rom char * rom_ptr = “Hello, world!”; ram char ram_buffer[14]; void main(void) { ram_int = rom_int; strcpypgm2ram (ram_buffer, rom_ptr); } FAQ-13 我如何在 C 程序中设置配置位? MPLAB C18 提供了 #pragma config 伪指令,可以在 C 程序中设置配置位。 使用示例: /* Oscillator Selection: HS */ #pragma config OSC = HS /* Enable watchdog timer and set postscaler to 1:128 */ #pragma config WDT = ON, WDTPS=128 FAQ-14 有哪些有关在 C 程序中设置配置位的参考资料? • 《MPLAB® C18 C 编译器用户指南》包含对 #pragma config 伪指令的一般说 明。 • “PIC18 Configuration Settings Addendum”包含所有 PIC18 器件的可用配置设置 和值。 • MPLAB C18 --help-config 命令行选项列出了特定器件具有的配置设置和标准 输出值。 函数 说明 memcpypgm2ram 将 ROM 中的一段缓冲区复制到 RAM memmovepgm2ram 将 ROM 中的一段缓冲区复制到 RAM strcatpgm2ram 将 ROM 中的源字符串复制添加到 RAM 中目标字符串尾 strcpypgm2ram 将 RAM 中的字符串复制到 ROM strncatpgm2ram 将 ROM 中源字符串中指定数量的字符添加到 RAM 中目标字 符串尾 strncpypgm2ram 将 ROM 中源字符串中的字符复制到 RAM 中的目标字符串中 MPLAB® C 18 C 编译器入门 DS51295F_CN 第 106 页  2006 Microchip Technology Inc. FAQ-15 我如何使用 printf 输出字符串常量? 因为字符串常量存储在程序存储器中,因而需要添加特定于 MPLAB C18 的转换运算 符 (%S)来处理程序存储器数组 (rom char [])中字符的输出: #include rom char * foo = “Hello, world!”; void main (void) { printf (“%S\n”, foo); printf (“%S\n”, “Hello, world!”); } 当输出一个 far 程序存储器数组 (far rom char [])时,请确认使用 H 大小指定符 (即 %HS): #include far rom char * foo = “Hello, world!”; void main (void) { printf (“%HS\n”, foo); } FAQ-16 当我对两个字符执行算术运算,并将运算结果赋值给一个整型变量, 但我没有得到期望的值。为什么? 给定以下示例: unsigned char a, b; unsigned int i; a = b = 0x80; i = a + b; ANSI/ISO 期望 i 的值是 0x100,但 MPLAB C18 将 i 设置为 0x00。 默认情况下,MPLAB C18 以最大操作数的长度执行算术运算,即使两个操作数都小于 int 长度。要启用 ISO 要求的运算方式,即所有算术运算采用的精度均大于或等于 int,使用 -Oi 命令行选项。要在 MPLAB IDE 中启用该功能,请选择 Project>Build options…>Project,单击 MPLAB C18 选项卡,选中 Enable integer promotions。 MPLAB® C18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 107 页 术语表 ANSI 美国国家标准学会,是美国负责制订和批准的组织。 ASCII 美国信息交换标准码是使用 7 个二进制数字来表示每个字符的字符集编码。它包括大写 和小写字母、数字、符号以及控制字符。 Build 编译并链接一个应用的所有源文件。 八进制 (Octal) 使用数字 0-7,以 8 为基数的计数体制。最右边的位表示 1 的倍数,右侧第二位表示 8 的倍数,右侧第三位表示 82 = 64 的倍数,以此类推。 编译器 (Compiler) 将用高级语言编写的源文件翻译成机器码的程序。 C 具有表达式简练、现代控制流程和数据结构,以及运算符丰富等特点的通用编程语言。 COFF 公共目标文件格式。这种格式的目标文件包含机器码、调试及其他信息。 CPU 参见中央处理单元。 场景 (Scenario) 对于 MPLAB SIM 软件模拟器来说,是用于激励控制的一个特定设置。 操作码 (Opcode) 操作码。参见助记符。 程序存储器 (Program Memory) 器件中存储指令的存储器。亦指仿真器或软件模拟器中包含下载的目标应用固件的存 储器。 程序计数器 (Program Counter) 包含正在执行的指令的地址的存储单元。 触发输出 (Trigger Output) 指可在任意地址或地址范围产生的仿真器输出信号,与跟踪和断点的设置无关。可设 置任意个触发输出点。 次数计数器 (Pass Counter) 每次一个事件 (如执行特定地址处的一条指令)发生时都会递减 1 的计数器。当次数 计数器的值为零时,事件满足。可将次数计数器分配给断点和跟踪逻辑,以及在 complex trigger (复杂触发)对话框中的任何连续事件。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 108 页  2006 Microchip Technology Inc. 存储类别 (Storage Class) 决定对象的生存时间。 存储模型 (Memory Models) 指定指向程序存储器的指针长度的描述。 存储限定符 (Storage Qualifier) 表明对象的特殊属性 (如 volatile)。 错误文件 (Error File) 包含由语言工具生成的错误消息和诊断的文件。 DSC 参见数字信号控制器。 单片机 (Microcontroller) 高度集成的芯片,它包括 CPU、 RAM、程序存储器、 I/O 端口和定时器。 单片机模式 (Microcontroller Mode) PIC17 和 PIC18 系列单片机的一种程序存储器配置。在单片机模式下,仅允许内部执 行。因此,在这种模式下仅可使用片内程序存储器。 导出 (Export) 以标准的格式将数据发送出 MPLAB IDE。 导入 (Import) 从外面的源 (如 hex 文件)将数据送入 MPLAB IDE。 递归 (Recursion) 已定义的函数或宏可调用自己的概念。当编写递归宏时要特别小心;当递归没有出口 时容易陷入无限循环。 递归调用 (Recursive Call) 直接或间接调用自己的函数。 地址 (Address) 标识存储器中位置的值。 堆栈,软件 (Stack, Software) 用来存储返回地址、函数参数和局部变量的存储区。当用高级语言开发代码时,该存 储区一般由编译器管理。 堆栈,硬件 (Stack, Hardware) PICmicro 单片机中调用函数时存储返回地址的存储区。 段 (Section) 指定的代码或数据序列。 段属性 (Section Attribute) 段的特性 (如 access 段)。 断点,软件 (Breakpoint, Software) 一个地址,固件会在这个地址处暂停执行。通常由特殊的 break 指令获得。 断点,硬件 (Breakpoint, Hardware) 一种事件,执行这种事件会导致暂停。 术语表  2006 Microchip Technology Inc. DS51295F_CN 第 109 页 EEPROM 电可擦除的可编程只读存储器。一种可电擦除的特殊 PROM。一次写或擦除一个字节。 EEPROM 即使电源关闭时也能保留内容。 EPROM 可擦除的可编程只读存储器。通常通过紫外线照射来擦除的可编程只读存储器。 二进制 (Binary) 使用数字 0 和 1,以 2 为基数的计数体制。最右边的位表示 1 的倍数,右边第二位表 示 2 的倍数,右边第三位表示 22 = 4 的倍数,以此类推。 FNOP 强制空操作。强制 NOP 周期是双周期指令的第二个周期。由于 PICmicro 单片机的架构 是流水线型,在执行当前指令的同时预取物理地址空间中的下一条指令,如果当前指 令改变了程序计数器,那么这条预取的指令就被忽略了,导致一个强制 NOP 周期。 Free-Standing 一种 C 编译器实现,它接受任何不使用复杂类型的严格符合程序,而且在这种实现 中,对 ISO 库条款中规定的属性的使用,仅限于标准头文件 的内容。 仿真 (Emulation) 象执行存储在单片机中的固件一样执行装入仿真存储区中的软件的过程。 仿真存储器 (Emulation Memory) 仿真器内部的程序存储器。 仿真器 (Emulator) 执行仿真的硬件。 仿真器系统 (Emulator System) MPLAB ICE 2000 和 4000 仿真器系统包括仿真器主机、处理器模块、器件适配器、电 缆和 MPLAB IDE 软件。 仿真器主机 (Pod, Emulator) 包含仿真存储区、跟踪存储区、事件和周期定时器,以及跟踪 / 断点逻辑的仿真器盒 子。 非扩展模式 (Non-Extended Mode) 在非扩展模式下,编译器不会使用扩展指令和立即数变址寻址模式;也称为 “传统” 模式。 非实时 (Non Real-Time) 指处理器执行到断点或单步执行指令,或 MPLAB IDE 运行在软件模拟器模式。 非易失性存储器 (Non-Volatile Storage) 电源关闭时保留其内容的存储器件。 符号 (Symbol) 描述组成程序的不同部分的一种通用机制。这些部分包括函数名、变量名、段名、文 件名和结构 / 枚举 / 联合标记名等。 MPLAB IDE 中的符号主要指变量名、函数名和汇 编标号。链接后符号的值就是其在存储器中的值。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 110 页  2006 Microchip Technology Inc. GPR 通用寄存器。器件数据存储器 (RAM)的一部分,作为一般用途。 概要 (Profile) 对于 MPLAB SIM 软件模拟器来说,是对寄存器执行的激励的汇总表。 高级语言 (High-Level Language) 编写程序的语言,它比汇编语言更不依赖于具体的处理器。 跟踪 (Trace) 记录程序执行的仿真器或软件模拟器功能。仿真器将程序执行记录到其跟踪缓冲区内, 并可上载到 MPLAB IDE 的跟踪窗口中。 跟踪存储区 (Trace Memory) 跟踪存储区包含在仿真器内部。跟踪存储区有时称为跟踪缓冲区。 工作簿 (Workbook) 对于 MPLAB SIM 软件模拟器来说,是一种用于产生 SCL 激励的设置。 观察变量 (Watch Variable) 调试会话期间可在 Watch 窗口中监控的变量。 归档 (Archive) 可重定位目标模块的集合。由将多个源文件编译 / 汇编为目标文件,然后使用归档器将 目标文件组合为一个库文件生成。可将库与目标模块和其他库链接,生成可执行代码。 归档器 (Archiver) 生成和操作库的工具。 国际标准化组织 (International Organization for Standardization) 制订许多行业和技术 (包括计算和通讯)方面的标准的一个组织。 过滤器 (Filter) 通过选择确定在跟踪显示或数据文件中包含 / 排除哪些数据。 宏 (Macro) 宏指令。以缩写形式表示指令序列的指令。 宏伪指令 (Macro Directive) 控制宏定义体中执行和数据分配的伪指令。 Hex 代码 (Hex Code) 以十六进制格式代码存储的可执行指令。 hex 代码包含在 hex 文件中。 Hex 文件 (Hex File) 包含适用于对器件编程的十六进制地址和值 (hex 代码)的 ASCII 文件。 环境 — IDE (Environment – IDE) 应用程序开发桌面的特定布局。 环境 — MPLAB PM3 (Environment – MPLAB PM3) 包含关于如何烧写器件的文件的文件夹。可将这个文件传输到 SD™/MMC 卡。 汇编器 (Assembler ) 把汇编源代码翻译成机器码的语言工具。 汇编语言 (Assembly) 以符号形式描述二进制机器码的符号语言。 术语表  2006 Microchip Technology Inc. DS51295F_CN 第 111 页 ICD 在线调试器。 MPLAB ICD 2 是 Microchip 的在线调试器。 ICE 在线仿真器。 MPLAB ICE 2000 和 4000 是 Microchip 的在线仿真器。 IDE 集成开发环境。 MPLAB IDE 是 Microchip 的集成开发环境。 IEEE 电子和电气工程师协会。 IRQ 参见中断请求。 ISO 参见国际标准化组织。 ISR 参见中断服务程序。 激励 (Stimulus) 软件模拟器的输入 (即为模拟对外部信号的响应而生成的数据)。通常数据采用文本 文件中一系列动作的形式。激励可以是异步的,同步的 (引脚),时钟激励和寄存器 激励。 机器码 (Machine Code) 处理器实际读和解释的计算机程序的表示。二进制机器码的程序由一系列机器指令 (可能还包含数据)组成。特定处理器的所有可能指令的集合称为 “指令集”。 机器语言 (Machine Language) 特定中央处理单元的指令集,不需翻译即可用于处理器。 基数 (Radix) 数字基,十六进制或十进制,用于指定一个地址。 交叉引用文件 (Cross Reference File) 引用符号表的一个文件及引用符号的文件列表。如果定义了符号,列出的第一个文件 是定义的位置。其他文件包含对符号的引用。 校准存储区 (Calibration Memory) 用于保存PICmicro单片机片内RC振荡器或其他外设校准值的特殊功能寄存器或通用寄 存器。 节点 (Node) MPLAB IDE 项目的组件。 警告 (Warning) 提醒出现了可能导致器件、软件文件或设备物理损坏的通知。 静态 RAM 或 SRAM (Static RAM or SRAM) 静态随机访问存储器。目标板上可读 / 写且不需要经常刷新的程序存储器。 局部标号 (Local Label) 用LOCAL伪指令在一个宏内部定义的标号。这些标号特定于宏实例化的一个给定示例。 也就是说,声明为 local 的符号和标号在遇到 ENDM 宏后不再可访问。 绝对段 (Absolute Section) 具有链接器不能改变的固定 (绝对)地址的段。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 112 页  2006 Microchip Technology Inc. 看门狗定时器 (Watchdog Timer) PICmicro 单片机中在一段可选择长度的时间后复位处理器的定时器。使用配置位来使 能、禁止和设置 WDT。 可重定位 (Relocatable) 其段没有被分配到固定存储地址的目标文件。 可重入函数 (Reentrant) 可以有多个同时运行的实例的函数。在下面两种情况下可能发生函数重入:直接或间 接递归调用函数;或者在由函数转入的中断处理过程中又执行此函数。 控制伪指令 (Control Directive) 汇编语言代码中根据汇编时指定表达式的值包含或忽略代码的伪指令。 库 (Library) 参见归档。 库管理器 (Librarian) 参见归档器。 快速存取存储区 (Access Memory) PIC18 单片机中的一些特殊寄存器,对这些寄存器的访问与存储区选择寄存器 (BSR)的设置无关。 扩展单片机模式 (Extended Microcontroller Mode) 在扩展单片机模式中,既可使用片内程序存储器,也可使用外部存储器。如果程序存 储器地址大于 PIC17C 或 PIC18C 器件的内部存储空间,执行自动切换到外部存储器。 扩展模式 (Extended Mode) 在扩展模式下,编译器将使用扩展指令 (即 ADDFSR、 ADDULNK、 CALLW、 MOVSF、 MOVSS、 PUSHL、 SUBFSR 和 SUBULNK)和立即数变址寻址模式。 链接描述文件 (Linker Script File) 链接器的命令文件。定义链接选项并描述目标平台上的可用存储器。 链接器 (Linker) 把目标文件和库文件组合起来生成可执行代码并解析一个模块对另外一个模块引用的 语言工具。 列表伪指令 (Listing Directive) 控制汇编器列表文件格式的伪指令。它们允许指定标题、分页及其他列表控制。 列表文件 (Listing File) 列出为每条 C 源语句生成的机器码,源文件中遇到的汇编指令、汇编器伪指令或宏的 ASCII 文本文件。 逻辑探头 (Logic Probe) Microchip 的某些仿真器最多可连接 14 个逻辑探头。逻辑探头提供外部跟踪输入、触发 输出信号、 +5V 和公共接地端。 术语表  2006 Microchip Technology Inc. DS51295F_CN 第 113 页 Make 项目 (Make Project) 重新编译应用程序的命令,仅编译自上次编译完成后更改了的源文件。 MCU 单片机。 microcontroller 的缩写形式;也写作 µC。 MPASM 汇编器 (MPASM Assembler) PICmicro 单片机、 KEELOQ® 器件及 Microchip 存储器件的 Microchip 可重定位宏汇编 器。 MPLAB ICD 2 Microchip 的在线调试器,与 MPLAB IDE 配合工作。 ICD 支持内置调试电路的闪存器 件。每个 ICD 的主要组件是模块。一个完整的系统包括模块、适配头、演示板、电缆 和 MPLAB IDE 软件。 MPLAB ICE 2000/4000 Microchip 的在线仿真器,与 MPLAB IDE 配合工作。MPLAB ICE 2000 支持 PICmicro MCU。MPLAB ICE 4000 支持 PIC18F MCU和 dsPIC30F DSC。每个 ICE 的主要组件是 仿真器主机。一个完整的系统包括仿真器主机、处理器模块、电缆和 MPLAB IDE 软 件。 MPLAB IDE Microchip 的集成开发环境。 MPLAB PM3 Microchip 的器件编程器。用于对 PIC18 单片机和 dsPIC® 数字信号控制器编程。可与 MPLAB IDE 配合使用或独立使用。将取代 PRO MATE® II 而使之废弃。 MPLAB SIM Microchip 的软件模拟器,与 MPLAB IDE 配合工作,支持 PICmicro MCU 和 dsPIC DSC 器件。 MPLIB 目标库管理器 (MPLIB Object Librarian ) MPLIB 库管理器是用于将由 MPASM 汇编器(mpasm 或 mpasmwin v2.0)或 MPLAB C1X C 编译器生成的 COFF 目标模块组合成库文件的目标库管理器。 MPLINK 目标链接器 (MPLINK Object Linker) MPLINK链接器是Microchip MPASM汇编器和Microchip MPLAB C17或C18 C编译器的 目标链接器。也可将 MPLINK 链接器与 Microchip MPLIB 库管理器配合使用。 MPLINK 链接器设计为在 MPLAB IDE 中使用,尽管它也可独立于 MPLAB IDE 使用。 MRU 最近使用的。指可从 MPLAB IDE 主下拉菜单选择的文件和窗口。 命令行接口 (Command Line Interface) 仅基于文本输入和输出,在程序和其用户之间进行通讯的一种方式。 模板 (Template) 为以后插入自己的文件中使用而创建的文本行。 MPLAB 编辑器将模板存储到模板文件 中。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 114 页  2006 Microchip Technology Inc. 目标 (Target) 指用户硬件。 目标板 (Target Board) 构成目标应用的电路和可编程器件。 目标处理器 (Target Processor) 目标应用板上的单片机。 目标代码 (Object Code) 由汇编器或编译器生成的机器码。 目标文件 (Object File) 包含机器码,也可能包含调试信息的文件。它可以直接执行;或为可重定位的,需要 与其他目标文件 (如库文件)链接来生成完全可执行的程序。 目标文件伪指令 (Object File Directives) 仅当生成目标文件时使用的伪指令。 目标应用程序 (Target Application) 目标板上的软件。 NOP 空操作。执行该指令时,除了程序计数器加 1 外没有任何其他影响。 内部链接 (Internal Linkage) 如果不能从定义函数或变量的模块外部访问它们,则这样的函数或变量具有内部链接。 匿名结构 (Anonymous Structure) 为 C 联合的一个成员的未命名结构。对匿名结构的成员的访问与访问包含该匿名结构的 联合的成员的方法相同。例如,在下面的代码中, hi 和 lo 都是联合 caster 中匿名结构 的成员: union castaway int intval; struct { char lo; //accessible as caster.lo char hi; //accessible as caster.hi }; } caster; 术语表  2006 Microchip Technology Inc. DS51295F_CN 第 115 页 OTP 可一次编程。非窗口封装的 EPROM 器件。由于 EPROM 需要紫外线照射来擦除其存储 内容,因此只有窗口片是可擦除的。 PC 个人计算机或程序计数器。 PC 主机 (PC Host) 运行有一个支持的 Windows 操作系统的任何 IBM 或兼容个人计算机。 PICmicro MCU PICmicro 单片机 (MCU)指 Microchip 的所有单片机系列。 PICSTART Plus Microchip 器件的开发编程器。可对 8、14、28 和 40 引脚的 PICmicro 单片机进行编程。 必须与 MPLAB IDE 软件配合使用。 Pragma 一种伪指令,它对于特定的编译器有意义。通常将 pragma 用于向编译器传送实现定 义的信息。 MPLAB C30 使用属性来传送这种信息。 PRO MATE II Microchip 的器件编程器。可对大多数 PICmicro 单片机、大多数存储器和 KEELOQ 器件 进行编程。可与 MPLAB IDE 配合使用或单独使用。 PWM 信号 (PWM Signal) 脉冲宽度调制信号。某些 PICmicro MCU 包含 PWM 外设。 跑表 (Stopwatch) 测量执行周期的计数器。 片外存储器 (Off-Chip Memory) 指 PIC17 或 PIC18 器件的一种存储器选择,这种情况下存储器可位于目标板上,或所有 程序存储器都由仿真器提供。 配置位 (Configuration Bit) 可编程来设置 PICmicro 单片机工作模式的专用位。配置位可或不可再编程。 器件编程器 (Device Programmer) 用于对电可编程半导体器件 (如单片机)进行编程的工具。 嵌套深度 (Nesting Depth) 宏可包含其他宏的最大深度。 RAM 随机访问存储器 (数据存储器)。可以以任意顺序访问这种存储器中的信息。 ROM 只读存储器 (程序存储器)。不能修改的存储器。 Run 将仿真器从暂停状态释放,允许仿真器实时运行应用代码、实时改变 I/O 状态或实时响 应 I/O 的命令。 软件模拟器 (Simulator) 模拟器件操作的软件程序。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 116 页  2006 Microchip Technology Inc. SFR 参见特殊功能寄存器。 Single Step 这一命令单步执行代码,一次执行一条指令。执行每条指令后, MPLAB IDE 更新寄存 器窗口、通过查看变量及状态显示,可分析和调试指令。也可单步执行 C 编译器源代 码,但不是每次执行一条指令,MPLAB IDE 将执行一行高级 C 语句生成的所有汇编指 令。 Skew 不同时间出现在处理器总线上与指令执行有关的信息。例如,执行前一条指令的过程 中取指时,被执行的操作码出现在总线上;当实际执行操作码时,源数据地址及其值 以及目标数据地址出现在总线上。当执行下一条指令时,目标数据值出现在总线上。 跟踪缓冲区一次捕捉总线上的这些信息。因此,跟踪缓冲区的一条记录将包含三条指 令的执行信息。执行一条指令时,从一条信息到另一条信息的捕捉周期数称为 skew。 Skid 当使用硬件断点来暂停处理器时,在处理器暂停前可能再执行一条或多条指令。断点 后执行的指令条数称为 skid。 Step Into 这一命令与 Single Step 相同。Step Into (与 Step Over 相对)在 CALL 指令后,单步执 行子程序。 Step Out Step Out 允许跳出当前正在单步执行的子程序。此命令执行子程序中剩下的代码,然 后在子程序的返回地址处停止执行。 Step Over Step Over 允许单步执行时跳过子程序。这个命令执行子程序中的代码,然后在子程序 的返回地址处停止执行。 当 step over 一条 CALL 指令时,下一个断点将设置在 CALL 指令后的下一条指令处。 如果由于某种原因,子程序陷入无限循环或不正确返回,下一个断点将永远执行不到。 选择 Halt 来重新获得对程序执行的控制。 闪存 (Flash) 按块 (而不是按字节)写或擦除数据的一种 EEPROM。 上电复位仿真 (Power-on-Reset Emulation) 在开始为应用上电时,将随机值写到数据RAM 区中来模拟RAM中的未初始化值的软件 随机过程。 上载 (Upload) 上载功能将数据从一个工具,如仿真器或编程器,传送到主机 PC,或将数据从目标板 传送到仿真器。 事件 (Event) 对可能包含地址、数据、次数计数、外部输入、周期类型 (取指和读 / 写)及时间标记 的总线周期的描述。事件用于描述触发、断点和中断。 十六进制 (Hexadecimal) 使用数字 0-9 以及字母 A-F (或 a-f),以 16 为基数的计数体制。字母 A-F 表示十进 制数 10 到 15。最右边的位表示 1 的倍数,右边第二位表示 16 的倍数,第三位表示 162 = 256 的倍数,以此类推。 术语表  2006 Microchip Technology Inc. DS51295F_CN 第 117 页 实时 (Real-Time) 当从仿真器或 MPLAB ICD 模式中的暂停状态释放时,处理器以实时模式运行且与芯片 的正常操作相同。在实时模式下,使能 MPLAB ICE 的实时跟踪缓冲区,并持续捕捉 所有选择的周期,使能所有 break 逻辑。在仿真器或 MPLAB ICD 模式下,处理器实 时运行,直到有效断点导致暂停,或者直到用户暂停仿真器。在软件模拟器模式下, 实时仅意味着单片机指令的执行速度与主机 CPU 可模拟的指令速度一样快。 数据存储器 (Data Memory) 在 Microchip MCU 和 DSC 器件中,数据存储器 (RAM)由通用寄存器 (GPR)和特 殊功能寄存器 (SFR)组成。某些器件还有 EEPROM 数据存储器。 数据伪指令 (Data Directive) 指控制汇编器的程序和数据存储空间分配,并提供通过符号 (即有意义的名字)引用 数据项的方法的伪指令。 数字信号控制器 (Digital Signal Controller) 具有数字信号处理能力的单片机 (如 Microchip dsPIC® 器件)。 特殊功能寄存器 (Special Function Register) 数据存储器 (RAM)的一部分,专用于控制 I/O 处理函数、 I/O 状态、定时器或其他 模式及外设的寄存器。 条件编译 (Conditional Compilation) 只有当预处理伪指令指定的某个常量表达式为真时才编译程序段的操作。 Watch 窗口 (Watch Window) Watch 窗口包含一系列观察变量,这些变量在每次执行到断点时更新。 WDT 参见看门狗定时器。 外部 RAM (External RAM) 片外的读 / 写存储器。 外部符号 (External Symbol) 具有外部链接的标识符符号。这可能是一个引用或一个定义。 外部符号解析 (External Symbol Resolution) 链接器搜集所有输入模块的外部符号定义来解析所有外部符号引用的过程。没有相应 定义的任何外部符号引用都会导致报告链接器错误。 外部输入线 (External Input Line) 用于根据外部信号设置事件的外部输入信号逻辑探针线 (TRIGIN)。 微处理器模式 (Microprocessor Mode) PIC17 和 PIC18 系列单片机的一种程序存储器配置。在微处理器模式下,不使用片内的 程序存储器。整个程序存储器映射到外部。 伪指令 (Directive) 源代码中控制语言工具操作的语句。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 118 页  2006 Microchip Technology Inc. 未初始化数据 (Uninitialized Data) 定义时未提供初始值的数据。在 C 中, int myVar; 定义了将存放到未初始化数据段的一个变量。 文件寄存器 (File Register) 片内数据存储器,包括通用寄存器 (GPR)和特殊功能寄存器 (SFR) 系统窗口控制 (System Window Control) 系统窗口控制位于窗口或某些对话框的左上角。点击这一控制通常会弹出包含 “Minimize (最小化)”、“Maximize (最大化)”和 “Close (关闭)”等项的菜 单。 下载 (Download) 数据从主机发送到其他设备,如仿真器、编程器或目标板的过程。 限定符 (Qualifier) 次数计数器使用的地址或地址范围,或用作复杂触发中另一个操作之前的事件。 向量 (Vector) 指定事件 (如复位或中断)发生时,应用程序跳转到的存储器地址。 项目 (Project) 为应用构建目标代码和可执行代码的一组源文件及指令。 消息 (Message) 显示出来的文本,警告在语言工具的操作中可能存在的问题。消息不会停止操作。 小尾数法 (Little Endianess) 多字节数据的数据存储顺序机制。在这种机制中,最低有效字节存储到较低的地址。 样机系统 (Prototype System) 指用户目标应用或目标板的一个术语。 已分配段 (Assigned Section) 已在链接器命令文件中分配到目标存储区的段。 异步事件 (Asynchronous Events) 不同时发生的多个事件。通常用来指可能在处理器执行过程中的任意时刻发生的中断。 异步激励 (Asynchronous Stimulus) 使用软件模拟器时,为模拟被模拟器件的外部输入而生成的数据。 应用 (Application) 可由 PICmicro 单片机控制的一组软硬件。 源代码 (Source Code) 编程人员编写计算机程序的形式。采用某种正式的编程语言编写源代码,可翻译为机 器码或被解释程序执行。 源文件 (Source File) 包含源代码的 ASCII 文本文件。 术语表  2006 Microchip Technology Inc. DS51295F_CN 第 119 页 原始数据 (Raw Data) 与一个段有关的代码或数据的二进制表示。 运算符 (Operator) 构成表达式时使用的符号,如加法符号 “+”和减法符号 “-”。每个运算符都有用于 确定求值顺序的指定优先级。 运行时模型 (Runtime Model) 描述目标架构资源的使用。 暂停 (Halt) 停止程序执行。执行 Halt 与在断点处停止相同。 帧指针 (Frame Pointer) 指向堆栈中位置的指针,它将堆栈中的函数参数和局部变量分隔开。提供了一种方便 的方式来访问局部变量和当前函数的其他值。 指令 (Instruction) 告知中央处理单元执行特定操作,并包含操作中要使用的数据的位序列。 指令集 (Instruction Set) 特定处理器理解的机器语言指令的集合。 致命错误 (Fatal Error) 引起编译立即中止的错误。不产生其他消息。 中断 (Interrupt) 传递到 CPU 的信号,它使 CPU 暂停执行正在运行的应用程序,把控制权转交给中断 服务程序 (ISR),以处理事件。 中断处理程序 (Interrupt Handler) 发生中断时处理特殊代码的子程序。 中断服务程序 (Interrupt Service Routine) 当产生中断时进入的用户生成代码。代码在程序存储器中的位置通常取决于所产生中 断的类型。 中断请求 (Interrupt Request) 使处理器暂停正常的指令执行并开始执行中断处理程序的事件。某些处理器有几种中 断请求事件,允许具有不同优先级的中断。 中断响应时间 (Latency) 从事件发生到得到响应的时间。 中央处理单元 (Central Processing Unit) 器件的一部分,负责取出要执行的正确指令,对指令进行译码,然后执行指令。需要 时,它和算术逻辑单元 ( Arithmetic Logic Unit, ALU)配合工作,来完成指令的执 行。它控制程序存储器地址总线、数据存储器地址总线和对堆栈的访问。 助记符 (Mnemonics) 可直接翻译为机器码的文本指令。也称为操作码。 状态条 (Status Bar) 状态条位于 MPLAB IDE 窗口的底部,表明光标位置、开发模式和器件,以及有效工具 条等当前信息。 MPLAB® C18 C 编译器入门 DS51295F_CN 第 120 页  2006 Microchip Technology Inc. 字节存储顺序 (endianness) 描述多字节对象的字节存储顺序。 字母数字字符 (Alphanumeric) 字母数字字符由字母字符和十进制数字 (0, 1, …, 9)组成。 字母字符 (Alphabetic Character) 字母字符指属于阿拉伯字母表 (a, b, …, z, A, B, …, Z)中字母的字符。 MPLAB® C18 C 编译器 入门  2006 Microchip Technology Inc. DS51295F_CN 第 121 页 索引 符号 #pragma 伪指令 ...................................................... 94 HEX............................................................................ 9 _mplink.exe ......................................................... 13 A 安装 MPLAB C18 ..................................................... 15 B build ........................................................................... 9 变更通知客户服务 ..................................................... 7 编译项目 .................................................................. 35 编译选项 .................................................................. 33 不能定位 ‘p18cxxx.h’ ........................................ 100 找不到符号定义 ..................................................... 100 C 参考书 ....................................................................... 5 常见问题 (FAQ) ................................................... 99 程序存储器 .............................................................. 90 错误消息 .................................................................. 99 Could not find definition of symbol.................. 100 name exceeds...62 characters........................ 100 symbol 'symbol-name’ has not been defined.. 100 Syntax Error.................................................... 100 unable to locate 'p18cxxx.h' ........................... 100 语法错误................................................................... 43 could not find file 'c018i.o' .............................. 100 D Default storage class ............................................... 60 Diagnostic level........................................................ 60 低优先级中断................................................................ 102 调试工具栏....................................................................... 37 段....................................................................................... 96 断点................................................................................... 51 E EEPROM 数据存储器 .............................................. 94 Enable integer promotions ....................................... 61 Extended mode........................................................ 61 F 返回地址堆栈................................................................... 93 非扩展模式....................................................................... 13 符号 ‘符号名’尚未定义........................................... 100 复制数据........................................................................ 105 G General .................................................................... 60 General 选项 ........................................................... 60 H hex ........................................................................... 13 函数库 ..........................................................12, 20, 98 汇编 ................................................................... 12, 20 J I/O 寄存器 ................................................................ 97 Inherit global settings ............................................... 61 将光标置于变量之上 ................................................ 46 结构 ......................................................................... 80 解决问题 .................................................................. 43 警告 type qualifier mismatch in assignment ............ 101 K 客户支持 ............................................................................ 7 可执行程序 ......................................................... 12, 13, 20 扩展模式 ................................................................... 13, 94 L 链接描述文件 ........................................................... 12, 20 M Macro Definitions ..................................................... 61 Make .......................................................................... 9 MCC_INCLUDE ......................................................... 22 mcc18.exe.............................................................. 13 Microchip 网站 ........................................................... 7 mp2hex.exe............................................................ 13 MPASM 汇编器 ....................................................... 12 MPASM 交叉汇编器 ................................................ 10 mpasmwin.exe ....................................................... 13 MPLAB C18 编译器安装 .......................................... 13 MPLAB ICD2............................................................ 55 MPLAB IDE 组件 ..................................................... 11 mplib.exe.............................................................. 13 mplink.exe............................................................ 13 MPLINK 链接器 ................................................. 10, 13 目录................................................................................... 18 O Optimization ............................................................. 63 Optimization 选项........................................................... 63 P PATH 环境变量............................................................... 22 PICDEM 2 Plus 演示板 ............................................ 56 printf .................................................................. 106 Procedural-abstraction passes................................. 63 跑表................................................................................... 50 配置存储区 ...................................................................... 94 配置位 ................................................................... 105 索引  2006 Microchip Technology Inc. DS51295F_CN 第 122 页 Q 启动代码........................................................................... 94 R readme 文件 .................................................................... 17 软件定时器....................................................................... 97 软件模拟器设置............................................................... 49 S 设计中心............................................................................. 6 示例................................................................................... 20 鼠标右键菜单................................................................... 50 数据表............................................................................ 104 数据存储器....................................................................... 92 数据类型........................................................................... 76 数组................................................................................... 79 T Treat 'char' as unsigned ......................................... 61 特殊功能寄存器 ....................................................... 93 添加文件到项目中 ................................................... 28 头文件 ................................................................12, 20 标准 C ..........................................................12, 20 推荐读物 .................................................................... 4 W Watch 窗口 .............................................................. 47 Use Alternate Settings ............................................. 61 文档约定 .................................................................... 3 文件名超过文件格式要求的最大 62 字符的限制 .... 100 问题解答 .................................................................... 7 X 系统要求 .......................................................................... 11 项目 .................................................................................. 25 项目编译选项 .......................................................... 59 项目窗口 .......................................................................... 30 项目向导 .......................................................................... 26 小尾数法 ........................................................................ 118 卸载 MPLAB C18 ..................................................... 24 许可协议 .......................................................................... 16 Y 演示板 ..................................................................... 55 因特网地址 ................................................................ 7 硬件定时器 .............................................................. 97 应用笔记 .................................................................... 6 语法错误 ................................................................. 43, 100 语言工具 .......................................................................... 13 流程 .......................................................................... 14 语言工具路径 .......................................................... 30 语言工具设置 .......................................................... 27 源代码 标准 C 函数库 .................................................. 12 特定处理器函数库 ............................................ 12 Z 找不到 ‘c018i.o’ ................................................ 100 指定的类型限定符不匹配 ...................................... 101 指针 .................................................................................. 82 中断 .................................................................................. 98 中断服务程序 ........................................................ 119 字符串 ............................................................................ 102 索引  2006 Microchip Technology Inc. DS51295F_CN 第 123 页 注: DS51295F_CN 第 124 页  2006 Microchip Technology Inc. 美洲 公司总部 Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 1-480-792-7200 Fax: 1-480-792-7277 技术支持: http://support.microchip.com 网址:www.microchip.com 亚特兰大 Atlanta Alpharetta, GA Tel: 1-770-640-0034 Fax: 1-770-640-0307 波士顿 Boston Westborough, MA Tel: 1-774-760-0087 Fax: 1-774-760-0088 芝加哥 Chicago Itasca, IL Tel: 1-630-285-0071 Fax: 1-630-285-0075 达拉斯 Dallas Addison, TX Tel: 1-972-818-7423 Fax: 1-972-818-2924 底特律 Detroit Farmington Hills, MI Tel: 1-248-538-2250 Fax: 1-248-538-2260 科科莫 Kokomo Kokomo, IN Tel: 1-765-864-8360 Fax: 1-765-864-8387 洛杉矶 Los Angeles Mission Viejo, CA Tel: 1-949-462-9523 Fax: 1-949-462-9608 圣克拉拉 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 加拿大多伦多 Toronto Mississauga, Ontario, Canada Tel: 1-905-673-0699 Fax: 1-905-673-6509 亚太地区 亚太总部 Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 中国 - 北京 Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 中国 - 成都 Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 中国 - 福州 Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 中国 - 香港特别行政区 Tel: 852-2401-1200 Fax: 852-2401-3431 中国 - 青岛 Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 中国 - 上海 Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 中国 - 沈阳 Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 中国 - 深圳 Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 中国 - 顺德 Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 中国 - 武汉 Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 中国 - 西安 Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 台湾地区 - 高雄 Tel: 886-7-536-4818 Fax: 886-7-536-4803 台湾地区 - 台北 Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 台湾地区 - 新竹 Tel: 886-3-572-9526 Fax: 886-3-572-6459 亚太地区 澳大利亚 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 印度 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 印度 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 印度 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 日本 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 韩国 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 韩国 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 或 82-2-558-5934 马来西亚 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 菲律宾 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 新加坡 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 泰国 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 欧洲 奥地利 Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 丹麦 Denmark-Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 法国 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 德国 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 意大利 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 荷兰 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 西班牙 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 英国 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 全球销售及服务网点 08/29/06  2015 Microchip Technology Inc. DS00001854B-page 1 Highlights • USB Hub Feature Controller IC with 4 USB 3.0/ 2.0 downstream ports • USB-IF Battery Charger revision 1.2 support on up & downstream ports (DCP, CDP, SDP) • FlexConnect: Downstream port able to swap with upstream port, allowing master capable devices to control other devices on the hub • USB to I2C/UART/SPI/GPIO bridge endpoint support • USB Link Power Management (LPM) support • Enhanced OEM configuration options available through either OTP or SPI ROM • Available in 64-pin (9 x 9 mm) SQFN lead-free, RoHS compliant package • Commercial and industrial grade temperature support • Configuration Straps: Predefined configuration of system level functions including GPIOs Target Applications • Standalone USB Hubs • Laptop Docks • PC Motherboards • PC Monitor Docks • Multi-function USB 3.0 Peripherals Key Benefits • USB 3.0 compliant 5 Gbps, 480 Mbps, 12 Mbps and 1.5 Mbps operation - 5 V tolerant USB 2.0 pins - 1.32 V tolerant USB 3.0 pins - Integrated termination & pull-up/pull-down resistors • Supports per port battery charging of most popular battery powered devices - USB-IF Battery Charging rev. 1.2 support (DCP, CDP, SDP) - Apple portable product charger emulation - Chinese YD/T 1591-2006 charger emulation - Chinese YD/T 1591-2009 charger emulation - European Union universal mobile charger support - Support for Microchip USC100x family of battery charging controllers - Supports additional portable devices • Smart port controller operation - Firmware handling of companion port controllers • On-chip microcontroller - Manages I/Os, VBUS, and other signals • 8 KB RAM, 64 KB ROM • 8 KB One Time Programmable (OTP) ROM - Includes on-chip charge pump • Configuration programming via OTP ROM, SPI ROM, or SMBus • PortSwap - Configurable differential intro-pair signal swapping • PHYBoostTM - Programmable USB transceiver drive strength for recovering signal integrity • VariSenseTM - Programmable USB receiver sensitivity • Compatible with Microsoft Windows 8, 7, XP, Apple OS X 10.4+, and Linux hub drivers • Optimized for low-power operation and low thermal dissipation • Package - 64-pin SQFN (9 x 9 mm) • Environmental - 3 kV HBM JESD22-A114F ESD protection - Commercial temperature range (0°C to +70°C) - Industrial temperature range (-40°C to +85°C) USB5734 4-Port SS/HS USB Controller Hub USB5734 DS00001854B-page 2  2015 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2015 Microchip Technology Inc. DS00001854B-page 3 USB5734 1.0 Preface ............................................................................................................................................................................................ 4 2.0 Introduction ..................................................................................................................................................................................... 6 3.0 Pin Description and Configuration .................................................................................................................................................. 8 4.0 Device Connections ...................................................................................................................................................................... 26 5.0 Modes of Operation ...................................................................................................................................................................... 28 6.0 Device Configuration ..................................................................................................................................................................... 31 7.0 Device Interfaces .......................................................................................................................................................................... 33 8.0 Functional Descriptions ................................................................................................................................................................. 35 9.0 Operational Characteristics ........................................................................................................................................................... 41 10.0 Package Outlines ........................................................................................................................................................................ 50 11.0 Revision History .......................................................................................................................................................................... 52 USB5734 DS00001854B-page 4  2015 Microchip Technology Inc. 1.0 PREFACE 1.1 General Terms TABLE 1-1: GENERAL TERMS Term Description ADC Analog-to-Digital Converter Byte 8 bits CDC Communication Device Class CSR Control and Status Registers DWORD 32 bits EOP End of Packet EP Endpoint FIFO First In First Out buffer FS Full-Speed FSM Finite State Machine GPIO General Purpose I/O HS Hi-Speed HSOS High Speed Over Sampling Hub Feature Controller The Hub Feature Controller, sometimes called a Hub Controller for short is the internal processor used to enable the unique features of the USB Controller Hub. This is not to be confused with the USB Hub Controller that is used to communicate the hub status back to the Host during a USB session. I 2C Inter-Integrated Circuit LS Low-Speed lsb Least Significant Bit LSB Least Significant Byte msb Most Significant Bit MSB Most Significant Byte N/A Not Applicable NC No Connect OTP One Time Programmable PCB Printed Circuit Board PCS Physical Coding Sublayer PHY Physical Layer PLL Phase Lock Loop RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. SDK Software Development Kit SMBus System Management Bus UUID Universally Unique IDentifier WORD 16 bits  2015 Microchip Technology Inc. DS00001854B-page 5 USB5734 1.2 Reference Documents 1. UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http:// www.usb.org 2. Universal Serial Bus Specification, Revision 3.0, http://www.usb.org 3. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org 4. I 2C-Bus Specification, Version 1.1, http://www.nxp.com 5. System Management Bus Specification, Version 1.0, http://smbus.org/specs USB5734 DS00001854B-page 6  2015 Microchip Technology Inc. 2.0 INTRODUCTION 2.1 General Description The Microchip USB5734 hub is low-power, OEM configurable, USB 3.0 hub feature controller with 4 downstream ports and advanced features for embedded USB applications. The USB5734 is fully compliant with the USB 3.0 Specification and USB 2.0 Link Power Management Addendum. The USB5734 supports 5 Gbps SuperSpeed (SS), 480 Mbps HiSpeed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB downstream devices on all enabled downstream ports. The USB5734 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub feature controller that is the culmination of five generations of Microchip hub feature controller design and experience with proven reliability, interoperability, and device compatibility. The SuperSpeed hub feature controller operates in parallel with the USB 2.0 controller, decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic. The USB5734 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the configuration process assigning default values to USB3.0 ports and GPIOs OEMs can disable ports, enable battery charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI ROM. The USB5734 supports both upstream battery charger detection and downstream battery charging. The USB5734 integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5734 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles: • DCP: Dedicated Charging Port (Power brick with no data) • CDP: Charging Downstream Port (1.5A with data) • SDP: Standard Downstream Port (0.5A with data) • Custom profiles loaded via SMBus or OTP The USB5734 provides an additional USB endpoint dedicated for use as a USB to I2C/UART/SPI/GPIO interface, allowing external circuits or devices to be monitored, controlled, or configured via the USB interface. Additionally, the USB5734 includes many powerful and unique features such as: FlexConnect, which provides flexible connectivity options. One of the USB5734’s downstream ports can be reconfigured to become the upstream port, allowing master capable devices to control other devices on the hub. PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the PCB. PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity in a compromised system environment. The graphic on the right shows an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in a compromised system environment VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used. The USB5734 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow for maximum operational flexibility, and are available as GPIOs for customer specific use. The USB5734 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal block diagram of the USB5734 is shown in Figure 2-1.  2015 Microchip Technology Inc. DS00001854B-page 7 USB5734 FIGURE 2-1: INTERNAL BLOCK DIAGRAM USB 3.0 Hub Controller TX SS Flex PHY RX SS Flex PHY USB 2.0 Flex PHY USB 2.0 Hub Controller Buffer HS/FS/LS Routing Logic Common Block & PLL Registers & Hub I/O VBUS Control Buffer TX SS PHY RX SS PHY USB2.0 PHY Buffer Buffer TX SS PHY RX SS PHY USB2.0 PHY Buffer Buffer TX SS PHY RX SS PHY USB2.0 PHY Buffer Buffer TX SS PHY RX SS PHY USB2.0 PHY Buffer Buffer Upstream USB Port 0 (or Downstream Port 1 via FlexConnect) Downstream USB Port 1 (or Upstream Port via FlexConnect) Downstream USB Port 2 Downstream USB Port 3 Downstream USB Port 4 Embedded 8051 µC Registers & Hub I/O 64k ROM 8k RAM APB Bus XData Downstream RX SS bus Downstream TX SS bus Reset & 8051 Boot Seq. Xdata-toAPB Bridge Programmable Functions SPI/ SMBus/ UART 8k OTP PROG_FUNC[7:1] UART SPI/SMBus USB5734 DS00001854B-page 8  2015 Microchip Technology Inc. 3.0 PIN DESCRIPTION AND CONFIGURATION 3.1 Pin Assignments Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Configuration Straps and Programmable Functions" for additional information. FIGURE 3-1: 64-SQFN PIN ASSIGNMENTS Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field. (Connect exposed pad to ground with a via field) VSS USB5734 64-SQFN (Top View) 5 6 7 8 9 10 11 12 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 60 59 58 57 56 55 54 53 USB3DN_RXDM1 USB3DN_RXDP1 USB2DN_DP2/PRT_DIS_P2 USB2DN_DM2/PRT_DIS_M2 USB3DN_TXDP2 USB3DN_TXDM2 VDD12 USB3DN_RXDP2 PROG_FUNC4 SPI_CE_N/GPIO7/CFG_NON_REM SPI_DO/UART_TX/GPIO5/I2C_SLV_CFG1 PRT_CTL1 PRT_CTL3 VDD12 USB3UP_RXDP VDD12 USB3UP_TXDM USB3UP_TXDP VDD12 USB3DN_TXDP4 USB3DN_TXDM3 USB3DN_RXDM3 USB3DN_TXDP3 USB2DN_DM3/PRT_DIS_M3 USB2DN_DP3/PRT_DIS_P3 VDD33 SPI_CLK/UART_RX/GPIO4/I2C_SLV_CFG0 USB2UP_DP USB3DN_TXDM4 USB2UP_DM USB3DN_RXDP3 SPI_DI/GPIO9/CFG_BC_EN 62 61 52 51 3 4 13 14 19 20 29 30 36 35 46 45 VDD12 USB2DN_DP4/PRT_DIS_P4 USB2DN_DM4/PRT_DIS_M4 VDD12 VDD12 USB3DN_TXDM1 USB3DN_TXDP1 USB2DN_DM1/PRT_DIS_M1 XTALI/CLK_IN XTALO ATEST USB3UP_RXDM VBUS_DET/GPIO16 PROG_FUNC3 PROG_FUNC2 PRT_CTL2 1 USB2DN_DP1/PRT_DIS_P1 2 CFG_STRAP 16 15 PROG_FUNC7 USB3DN_RXDM2 17 18 VDD12 VDD33 32 USB3DN_RXDP4 USB3DN_RXDM4 31 34 33 VDD33 PRT_CTL4/GANG_PWR 48 47 PROG_FUNC5 RESET_N 50 49 PROG_FUNC1 PROG_FUNC6 64 RBIAS VDD33 63  2015 Microchip Technology Inc. DS00001854B-page 9 USB5734 Table 3-1 details the package pin assignments in table format. TABLE 3-1: 64-SQFN PIN ASSIGNMENTS Pin Number Pin Name Pin Number Pin Name 1 CFG_STRAP 33 VDD33 2 USB2DN_DP1/PRT_DIS_P1 34 PRT_CTL4/GANG_PWR 3 USB2DN_DM1/PRT_DIS_M1 35 VDD12 4 USB3DN_TXDP1 36 PRT_CTL3 5 USB3DN_TXDM1 37 PRT_CTL2 6 VDD12 38 PRT_CTL1 7 USB3DN_RXDP1 39 PROG_FUNC2 8 USB3DN_RXDM1 40 PROG_FUNC3 9 USB2DN_DP2/PRT_DIS_P2 41 VBUS_DET/GPIO16 10 USB2DN_DM2/PRT_DIS_M2 42 SPI_CLK/UART_RX/GPIO4/I2C_SLV_CFG0 11 USB3DN_TXDP2 43 SPI_DO/UART_TX/GPIO5/I2C_SLV_CFG1 12 USB3DN_TXDM2 44 SPI_DI/GPIO9/CFG_BC_EN 13 VDD12 45 SPI_CE_N/GPIO7/CFG_NON_REM 14 USB3DN_RXDP2 46 PROG_FUNC4 15 USB3DN_RXDM2 47 PROG_FUNC5 16 PROG_FUNC7 48 RESET_N 17 VDD12 49 PROG_FUNC6 18 VDD33 50 PROG_FUNC1 19 USB2DN_DP3/PRT_DIS_P3 51 VDD12 20 USB2DN_DM3/PRT_DIS_M3 52 VDD33 21 USB3DN_TXDP3 53 USB2UP_DP 22 USB3DN_TXDM3 54 USB2UP_DM 23 VDD12 55 USB3UP_TXDP 24 USB3DN_RXDP3 56 USB3UP_TXDM 25 USB3DN_RXDM3 57 VDD12 26 USB2DN_DP4/PRT_DIS_P4 58 USB3UP_RXDP 27 USB2DN_DM4/PRT_DIS_M4 59 USB3UP_RXDM 28 USB3DN_TXDP4 60 ATEST 29 USB3DN_TXDM4 61 XTALO 30 VDD12 62 XTALI/CLK_IN 31 USB3DN_RXDP4 63 VDD13 32 USB3DN_RXDM4 64 RBIAS USB5734 DS00001854B-page 10  2015 Microchip Technology Inc. 3.2 Pin Descriptions This section contains descriptions of the various USB5734 pins. This pin descriptions have been broken into functional groups as follows: • USB 3.0 Pin Descriptions • USB 2.0 Pin Descriptions • USB Port Control Pin Descriptions • SPI/UART Pin Descriptions • Programmable Function Pin Descriptions • Miscellaneous Pin Descriptions • Power and Ground Pin Descriptions The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “Active high” signals. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive. Note: The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables. A description of the buffer types is provided in Section 3.3, "Buffer Types," on page 15. For additional information on configuration straps and configurable pins, refer to Section 3.4, "Configuration Straps and Programmable Functions". TABLE 3-2: USB 3.0 PIN DESCRIPTIONS Num Pins Symbol Buffer Type Description 1 USB3UP_TXDP IO-U USB 3.0 upstream SuperSpeed transmit data plus. 1 USB3UP_TXDM IO-U USB 3.0 upstream SuperSpeed transmit data minus. 1 USB3UP_RXDP IO-U USB 3.0 upstream SuperSpeed receive data plus. 1 USB3UP_RXDM IO-U USB 3.0 upstream SuperSpeed receive data minus. 4 USBDN_TXDP[4:1] IO-U USB 3.0 downstream ports 4-1 SuperSpeed transmit data plus. 4 USBDN_TXDM[4:1] IO-U USB 3.0 downstream ports 4-1 SuperSpeed transmit data minus. 4 USBDN_RXDP[4:1] IO-U USB 3.0 downstream ports 4-1 SuperSpeed receive data plus. 4 USBDN_RXDM[4:1] IO-U USB 3.0 downstream ports 4-1 SuperSpeed receive data minus. TABLE 3-3: USB 2.0 PIN DESCRIPTIONS Num Pins Symbol Buffer Type Description 1 USB2UP_DP IO-U USB 2.0 upstream data plus (D+). 1 USB2UP_DM IO-U USB 2.0 upstream data minus (D-).  2015 Microchip Technology Inc. DS00001854B-page 11 USB5734 Note 2: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Configuration Straps and Programmable Functions" for additional information. 4 USB2DN_DP[4:1] IO-U USB 2.0 downstream ports 4-1 data plus (D+). PRT_DIS_P[4:1] I Port 4-1 D+ Disable Configuration Strap. These configuration straps are used in conjunction with the corresponding PRT_DIS_M[4:1] straps to disable the related port (4-1). Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])" for more information. See Note 2. 4 USB2DN_DM[4:1] IO-U USB 2.0 downstream ports 4-1 data minus (D-). PRT_DIS_M[4:1] I Port 4-1 D- Disable Configuration Strap. These configuration straps are used in conjunction with the corresponding PRT_DIS_P[4:1] straps to disable the related port (4-1). Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])" for more information. See Note 2. 1 VBUS_DET IS This signal detects the state of the upstream bus power. When designing a detachable hub, this pin must be connected to the VBUS power pin of the upstream USB port through a resistor divider (50 k by 100 k) to provide 3.3 V. For self-powered applications with a permanently attached host, this pin must be connected to either 3.3 V or 5.0 V through a resistor divider to provide 3.3 V. In embedded applications, VBUS_DET may be controlled (toggled) when the host desires to renegotiate a connection without requiring a full reset of the device. GPIO16 I/O6 General purpose input/output 16. TABLE 3-4: USB PORT CONTROL PIN DESCRIPTIONS Num Pins Symbol Buffer Type Description 1 PRT_CTL1 I (PU) Port 1 Power Enable / Overcurrent Sense. As an output, this signal is an active high control signal used to enable power to the downstream port 1. As an input, this signal indicates an overcurrent condition from an external current monitor on USB port 1. 1 PRT_CTL2 I (PU) Port 2 Power Enable / Overcurrent Sense. As an output, this signal is an active high control signal used to enable power to the downstream port 2. As an input, this signal indicates an overcurrent condition from an external current monitor on USB port 2. TABLE 3-3: USB 2.0 PIN DESCRIPTIONS (CONTINUED) Num Pins Symbol Buffer Type Description USB5734 DS00001854B-page 12  2015 Microchip Technology Inc. 1 PRT_CTL3 I (PU) Port 3 Power Enable / Overcurrent Sense. As an output, this signal is an active high control signal used to enable power to the downstream port 3. As an input, this signal indicates an overcurrent condition from an external current monitor on USB port 3. 1 PRT_CTL4 I (PU) Port 4 Power Enable / Overcurrent Sense. As an output, this signal is an active high control signal used to enable power to the downstream port 4. As an input, this signal indicates an overcurrent condition from an external current monitor on USB port 4. GANG_PWR I (PU) When pulled high enables gang mode. Gang power pin when used in gang mode. TABLE 3-5: SPI/UART PIN DESCRIPTIONS Num Pins Symbol Buffer Type Description 1 SPI_CE_N O12 Active low SPI chip enable output. GPIO7 I/O12 General purpose input/output 7. CFG_NON_REM I Non-Removable Port Configuration Strap. This configuration strap is used to configure the number of nonremovable ports. Refer to Section 3.4.3, "Non-Removable Port Configuration (CFG_NON_REM)" for more information. See Note 3. 1 SPI_CLK O6 SPI clock output to the serial ROM, when configured for SPI operation. UART_RX I UART receive pin, when configured for UART operation. GPIO4 I/O6 General purpose input/output 4. I2C_SLV_CFG0 I I 2C Slave 0 Configuration Strap. This configuration strap is used to configure I2C controller 0. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])" for additional information. 1 SPI_DO O6 SPI data output, when configured for SPI operation. UART_TX O12 UART transmit pin, when configured for UART operation. GPIO5 I/O6 General purpose input/output 5. I2C_SLV_CFG1 I I 2C Slave 1 Configuration Strap. This configuration strap is used to configure I2C controller 1. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])" for additional information. TABLE 3-4: USB PORT CONTROL PIN DESCRIPTIONS (CONTINUED) Num Pins Symbol Buffer Type Description  2015 Microchip Technology Inc. DS00001854B-page 13 USB5734 Note 3: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Configuration Straps and Programmable Functions" for additional information. Note 4: The PROG_FUNC2 buffer type is I/O6. The PROG_FUNC7 buffer type is I/O10. All other PROG_FUNCx pins have a buffer type of I/O12. Note 5: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Configuration Straps and Programmable Functions" for additional information. 1 SPI_DI IS SPI data input, when configured for SPI operation. GPIO9 I/O12 General purpose input/output 9. CFG_BC_EN I Battery Charging Configuration Strap. This configuration strap is used to enable battery charging. Refer to Section 3.4.4, "Battery Charging Configuration (CFG_BC_EN)" for more information. See Note 3. TABLE 3-6: PROGRAMMABLE FUNCTION PIN DESCRIPTIONS Num Pins Symbol Buffer Type Description 7 PROG_FUNC[7:1] Note 4 Programmable function pins 7-1. The functions of these pins are configured via the CFG_STRAP pin. Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" for additional information. 1 CFG_STRAP I Device Mode Configuration Strap. This configuration strap is used to set the device mode. Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" for more information. See Note 5. TABLE 3-5: SPI/UART PIN DESCRIPTIONS (CONTINUED) Num Pins Symbol Buffer Type Description USB5734 DS00001854B-page 14  2015 Microchip Technology Inc. TABLE 3-7: MISCELLANEOUS PIN DESCRIPTIONS Num Pins Symbol Buffer Type Description 1 RESET_N IS The RESET_N pin puts the device into Reset Mode, as the name of the pin and function then align. 1 XTALI ICLK External 25 MHz crystal input CLK_IN ICLK External reference clock input. The device may alternatively be driven by a single-ended clock oscillator. When this method is used, XTALO should be left unconnected. 1 XTALO OCLK External 25 MHz crystal output 1 RBIAS AI A 12.0 k (+/- 1%) resistor is attached from ground to this pin to set the transceiver’s internal bias settings. 1 ATEST AI Analog test pin. This signal is used for test purposes and must always be connected to ground. TABLE 3-8: POWER AND GROUND PIN DESCRIPTIONS Num Pins Symbol Buffer Type Description 4 VDD33 P +3.3 V power and internal regulator input Refer to Section 4.1, "Power Connections" for power connection information. 8 VDD12 P +1.2 V core power Refer to Section 4.1, "Power Connections" for power connection information. Pad VSS P Common ground. This exposed pad must be connected to the ground plane with a via array.  2015 Microchip Technology Inc. DS00001854B-page 15 USB5734 3.3 Buffer Types TABLE 3-9: BUFFER TYPES Buffer Type Description I Input IS Schmitt-triggered input O6 Output with 6 mA sink and 6 mA source O10 Output with 10 mA sink and 10 mA source O12 Output with 12 mA sink and 12 mA source OD12 Open-drain output with 12 mA sink PU 50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled. Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled high, an external resistor must be added. PD 50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled. Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled low, an external resistor must be added. IO-U Analog input/output as defined in USB specification AI Analog input ICLK Crystal oscillator input pin OCLK Crystal oscillator output pin P Power pin Note: Refer to Section 9.5, "DC Specifications" for individual buffer DC electrical characteristics. USB5734 DS00001854B-page 16  2015 Microchip Technology Inc. 3.4 Configuration Straps and Programmable Functions Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset (RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various device configuration straps and associated programmable pin functions. 3.4.1 SPI/SMBUS/I2C/UART CONFIGURATION (I2C_SLV_CFG[1:0]) The SPI/SMBus/I2C//UART pins can be configured into one of four functional modes: • SPI Mode • SMBus Slave Enable Mode • I2C Bridging Mode • UART Mode If 10 k pull-up resistors are detected on SPI_DO and SPI_CLK, the SPI/SMBus/I2C/UART pins are configured into SMBus Slave Enable Mode. If a 10 k pull-down resistor is detected on SPI_DO, the SPI/SMBus/I2C/UART pins are configured into UART Mode. If no pull-ups or pull-downs are detected on SPI_DO and SPI_CLK, the SPI/SMBus/I2C/ UART pins are first configured into SPI Mode. If no valid SPI ROM is detected, the SPI/SMBus/I2C/UART pins are configured into I2C Bridging Mode. The strap settings for these supported modes are detailed in Table 3-10. The individual pin function assignments for each mode are detailed in Table 3-11. For additional device connection information, refer to Section 4.0, "Device Connections". Note 6: In order to use the SPI interface, an SPI ROM containing a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA must be present. Refer to Section 7.1, "SPI Master Interface" for additional information. Note 7: In order to use the SMBus slave interface, the SPI_DO and SPI_CLK pins must be configured for SMBus Slave Enable Mode and CFG_STRAP must be configured to Configuration 1, 2, 3, or 6, which programs the PROG_FUNC4 and PROG_FUNC5 pins as SMDAT and SMCLK, respectively. When in Configuration 4 or 5, the SMBus slave interface is not usable. Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" for additional information. Note 8: In order to use the I2C Bridging interface, the SPI_DO and SPI_CLK pins must be configured for I2C Bridging Mode and CFG_STRAP must be configured to Configuration 1, 2, 3, or 6, which programs the PROG_- FUNC4 and PROG_FUNC5 pins as SMDAT and SMCLK, respectively. When in Configuration 4 or 5, the I 2C Bridging interface is not usable. Additional hub register configuration is also required. Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" and Section 7.3, "I2C Bridge Interface" for additional information. Note: The system designer must guarantee that configuration straps meet the timing requirements specified in Section 9.6.1, "Power-On and Configuration Strap Timing," on page 45 and Section 9.6.2, "Reset and Configuration Strap Timing," on page 45. If configuration straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. Note: The following interfaces cannot be used simultaneously: • UART and SMBus Slave • UART and SPI • SMBus Slave and I2C Bridging interface TABLE 3-10: SPI/SMBUS/I2C/UART MODE CONFIGURATION SETTINGS Pin SPI Mode (Note 6) SMBus Slave Enable Mode (Note 7) I 2C Bridging Mode (Note 8) UART Mode 43 (SPI_DO) No pull-up/down 10 k pull-up No pull-up/down 10 k pull-down 42 (SPI_CLK) No pull-up/down 10 k pull-up No pull-up/down No pull-up/down  2015 Microchip Technology Inc. DS00001854B-page 17 USB5734 3.4.2 PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1]) The PRT_DIS_P[4:1] and PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1). For PRT_DIS_Px (where x is the corresponding port 4-1): 0 = Port x D+ Enabled 1 = Port x D+ Disabled For PRT_DIS_Mx (where x is the corresponding port 4-1): 0 = Port x D- Enabled 1 = Port x D- Disabled 3.4.3 NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM) The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in Table 3-12. TABLE 3-11: SPI/SMBUS/I2C/UART MODE PIN ASSIGNMENTS Pin SPI Mode SMBus Slave Enable Mode I 2C Bridging Mode UART Mode 45 SPI_CE_N CFG_NON_REM CFG_NON_REM CFG_NON_REM 44 SPI_DI CFG_BC_EN CFG_BC_EN CFG_BC_EN 43 SPI_DO I2C_SLV_CFG0 - UART_TX 42 SPI_CLK I2C_SLV_CFG1 - UART_RX Note: Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0 port. TABLE 3-12: CFG_NON_REM RESISTOR ENCODING CFG_NON_REM Resistor Value Setting 200 kΩ Pull-Down All ports removable 200 kΩ Pull-Up Port 1 non-removable 10 kΩ Pull-Down Port 1, 2 non-removable 10 kΩ Pull-Up Port 1, 2, 3, non-removable 10 Ω Pull-Down Port 1, 2, 3, 4 non-removable USB5734 DS00001854B-page 18  2015 Microchip Technology Inc. 3.4.4 BATTERY CHARGING CONFIGURATION (CFG_BC_EN) The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in Table 3-13. 3.4.5 DEVICE MODE / PROG_FUNC[7:1] CONFIGURATION (CFG_STRAP) The CFG_STRAP is used to configure the programmable function pins (PROG_FUNC[7:1]) into one of six modes. These modes are selected by the configuration of an external resistor on the CFG_STRAP pin. The resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up, as shown in Table 3-14. For details on each device mode, including pin assignments, refer to the following subsections. TABLE 3-13: CFG_BC_EN RESISTOR ENCODING CFG_BC_EN Resistor Value Setting 200 kΩ Pull-Down No battery charging 200 kΩ Pull-Up Port 1 battery charging 10 kΩ Pull-Down Port 1, 2 battery charging 10 kΩ Pull-Up Port 1, 2, 3, battery charging 10 Ω Pull-Down Port 1, 2, 3, 4 battery charging TABLE 3-14: CFG_STRAP RESISTOR ENCODING CFG_STRAP Resistor Value Mode 200 kΩ Pull-Down Configuration 1 - Mixed Mode 200 kΩ Pull-Up Configuration 2 - FlexConnect Mode 10 kΩ Pull-Down Configuration 3 - Speed Indicator Mode 10 kΩ Pull-Up Configuration 4 - GPIO Mode (Reserved) 10 Ω Pull-Down Configuration 5 - Battery Charging / Power Delivery Indicator Mode 10 Ω Pull-Up Configuration 6 - Full UART Mode  2015 Microchip Technology Inc. DS00001854B-page 19 USB5734 3.4.5.1 Configuration 1 - Mixed Mode When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to provide an SMBus/I2C interface, 3 GPIOs, and FlexConnect capabilities. Table 3-15 details the PROG_FUNC[7:1] pin assignments in this mode. TABLE 3-15: CONFIGURATION 1 PROG_FUNC[7:1] FUNCTION ASSIGNMENT Pin Function Buffer Type Description PROG_FUNC1 GPIO1 I/O12 General Purpose Input/Output 1 PROG_FUNC2 GPIO2 I/O6 General Purpose Input/Output 2 PROG_FUNC3 GPIO3 I/O12 General Purpose Input/Output 3 PROG_FUNC4 SMDAT OD12 SMBus/I2C Data The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". PROG_FUNC5 SMCLK OD12 SMBus/I2C Clock The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". PROG_FUNC6 FLEXCMD IS FlexConnect Control 0: Normal Operation (Port 0 upstream, Port 1 downstream) 1: Flex Operation (Port 1 upstream, Port 0 downstream) Note: Refer to Section 8.2, "FlexConnect" for additional information. PROG_FUNC7 USB2_SUSP_IND O10 USB2.0 Suspend Indicator USB2_SUSP_IND can be used as a sideband remote wakeup signal for the host when in USB2.0 suspend. Note: Refer to Section 8.5, "Remote Wakeup Indicator" for additional information. USB5734 DS00001854B-page 20  2015 Microchip Technology Inc. 3.4.5.2 Configuration 2 - FlexConnect Mode When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to provide FlexConnect, an SMBus/I2C interface, and other additional features. Table 3-16 details the PROG_FUNC[7:1] pin assignments in this mode. TABLE 3-16: CONFIGURATION 2 PROG_FUNC[7:1] FUNCTION ASSIGNMENT Pin Function Buffer Type Description PROG_FUNC1 HOST_TYPE0 O12 Port 0 USB Host Type Tri-state: No USB host detected on Port 0 0: USB 3.0 Host detected on Port 0 1: USB 2.0 or USB 1.1 Host detected on Port 0 A USB 2.0 Host is considered detected when the USB 2.0 hub address register holds a non-zero value. A USB 3.0 Host is considered detected when the USB 3.0 hub address register holds a non-zero value. PROG_FUNC2 HOST_TYPE1 O6 Port 1 USB Host Type Tri-state: No USB host detected on Port 1 0: USB 3.0 Host detected on Port 1 1: USB 2.0 or USB 1.1 Host detected on Port 1 A USB 2.0 Host is considered detected when the USB 2.0 hub address register holds a non-zero value. A USB 3.0 Host is considered detected when the USB 3.0 hub address register holds a non-zero value. PROG_FUNC3 FLEX_STATE_N O12 FlexConnect State Compliment Indicator This signal reflects the inverse of the current state of FLEXCMD. 0: Flex Operation (Port 1 upstream, Port 0 downstream) 1: Normal Operation (Port 0 upstream, Port 1 downstream) Note: Refer to Section 8.2, "FlexConnect" for additional information. PROG_FUNC4 SMDAT OD12 SMBus/I2C Data The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". PROG_FUNC5 SMCLK OD12 SMBus/I2C Clock The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". PROG_FUNC6 FLEXCMD IS FlexConnect Control 0: Normal Operation (Port 0 upstream, Port 1 downstream) 1: Flex Operation (Port 1 upstream, Port 0 downstream) Note: Refer to the Section 8.2, "FlexConnect" for additional information. PROG_FUNC7 FLEX_STATE O10 FlexConnect State Indicator This signal reflects the current state of FLEXCMD. 0: Normal Operation (Port 0 upstream, Port 1 downstream) 1: Flex Operation (Port 1 upstream, Port 0 downstream) Note: Refer to Section 8.2, "FlexConnect" for additional information.  2015 Microchip Technology Inc. DS00001854B-page 21 USB5734 3.4.5.3 Configuration 3 - Speed Indicator Mode When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to indicate speed status, host type, and provide an SMBus/I2C interface. Table 3-17 details the PROG_FUNC[7:1] pin assignments in this mode. TABLE 3-17: CONFIGURATION 3 PROG_FUNC[7:1] FUNCTION ASSIGNMENT Pin Function Buffer Type Description PROG_FUNC1 SPEED_IND1 O12 Port 1 Speed Indicator Tri-state: Not connected 0: USB 2.0 / USB 1.1 1: USB 3.0 PROG_FUNC2 SPEED_IND2 O6 Port 2 Speed Indicator Tri-state: Not connected 0: USB 2.0 / USB 1.1 1: USB 3.0 PROG_FUNC3 SPEED_IND3 O12 Port 3 Speed Indicator Tri-state: Not connected 0: USB 2.0 / USB 1.1 1: USB 3.0 PROG_FUNC4 SMDAT OD12 SMBus/I2C Data The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". PROG_FUNC5 SMCLK OD12 SMBus/I2C Clock The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". PROG_FUNC6 SPEED_IND4 O12 Port 4 Speed Indicator Tri-state: Not connected 0: USB 2.0 / USB 1.1 1: USB 3.0 PROG_FUNC7 HOST_TYPE O10 Port 0 USB Host Type Tri-state: No USB host detected on Port 0 0: USB 3.0 Host detected on Port 0 1: USB 2.0 or USB 1.1 Host detected on Port 0 A USB 2.0 Host is considered detected when the USB 2.0 hub address register holds a non-zero value. A USB 3.0 Host is considered detected when the USB 3.0 hub address register holds a non-zero value. USB5734 DS00001854B-page 22  2015 Microchip Technology Inc. FIGURE 3-2: CONFIGURATION 3 PROG_FUNC[7:1] PIN CONNECTIONS PROG_FUNC1 3.3 V Rail SPEED_IND1 330 PROG_FUNC2 PROG_FUNC3 PROG_FUNC4 MMBD914LT1G Speed LED Indication: OFF – Port Not Connected A – USB2.0/1.1 Connection B – USB 3.0 Connection PROG_FUNC5 PROG_FUNC6 PROG_FUNC7 SPEED_IND2 330 SPEED_IND3 330 SPEED_IND4 330 HOST_TYPE 330 SMDAT SMCLK A B A B A B A B A B  2015 Microchip Technology Inc. DS00001854B-page 23 USB5734 3.4.5.4 Configuration 4 - GPIO Mode (Reserved) When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to provide 7 general purpose I/Os that can be used for GPIO bridging. Table 3-18 details the PROG_FUNC[7:1] pin assignments in this mode. 3.4.5.5 Configuration 5 - Battery Charging / Power Delivery Indicator Mode When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to indicate battery charging and 3 general purpose I/Os. Table 3-19 details the PROG_FUNC[7:1] pin assignments in this mode. TABLE 3-18: CONFIGURATION 4 PROG_FUNC[7:1] FUNCTION ASSIGNMENT Pin Function Buffer Type Description PROG_FUNC1 GPIO1 I/O12 General Purpose Input/Output 1 PROG_FUNC2 GPIO2 I/O6 General Purpose Input/Output 2 PROG_FUNC3 GPIO3 I/O12 General Purpose Input/Output 3 PROG_FUNC4 GPIO6 I/O12 General Purpose Input/Output 4 PROG_FUNC5 GPIO8 I/O12 General Purpose Input/Output 5 PROG_FUNC6 GPIO10 I/O12 General Purpose Input/Output 6 PROG_FUNC7 GPIO11 I/O10 General Purpose Input/Output 7 TABLE 3-19: CONFIGURATION 5 PROG_FUNC[7:1] FUNCTION ASSIGNMENT Pin Function Buffer Type Description PROG_FUNC1 BC_IND1 O12 Port 1 Battery Charging Indicator Tri-state: Battery Charging not enabled 0: In BC 1.2 Mode 1: Battery Charging enabled PROG_FUNC2 BC_IND2 O6 Port 2 Battery Charging Indicator Tri-state: Battery Charging not enabled 0: In BC 1.2 Mode 1: Battery Charging enabled PROG_FUNC3 BC_IND3 O12 Port 3 Battery Charging Indicator Tri-state: Battery Charging not enabled 0: In BC 1.2 Mode 1: Battery Charging enabled PROG_FUNC4 BC_IND4 O12 Port 4 Battery Charging Indicator Tri-state: Battery Charging not enabled 0: In BC 1.2 Mode 1: Battery Charging enabled PROG_FUNC5 GPIO8 I/O12 General Purpose Input/Output 8 PROG_FUNC6 GPIO10 I/O12 General Purpose Input/Output 10 PROG_FUNC7 GPIO11 I/O10 General Purpose Input/Output 11 USB5734 DS00001854B-page 24  2015 Microchip Technology Inc. FIGURE 3-3: CONFIGURATION 5 PROG_FUNC[7:1] PIN CONNECTIONS PROG_FUNC1 3.3 V Rail BC_STATUS_1 330 PROG_FUNC2 PROG_FUNC3 PROG_FUNC4 MMBD914LT1G BC LED Indication: OFF – BC In not Enabled A – BC Enabled B – BC in 1.2 Mode PROG_FUNC5 PROG_FUNC6 PROG_FUNC7 BC_STATUS_2 330 BC_STATUS_3 330 BC_STATUS_4 330 GPIO8 GPIO10 GPIO11 A B A B A B A B  2015 Microchip Technology Inc. DS00001854B-page 25 USB5734 3.4.5.6 Configuration 6 - Full UART Mode When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set for full UART configuration and also provide an SMBus/I2C interface. In this mode the PROG_FUNCx pins are used in conjunction with the UART_TX and UART_RX pins for a full UART interface. Table 3-20 details the PROG_FUNC[7:1] pin assignments in this mode. Note: When flow control is disabled, UART_nCTS, UART_nDCD, and UART_nDSR must not be left floating. In this case, these pins should include external pull-downs to maintain UART communication in Full UART Mode with no flow control. TABLE 3-20: CONFIGURATION 6 PROG_FUNC[7:1] FUNCTION ASSIGNMENT Pin Function Buffer Type Description PROG_FUNC1 UART_nRTS I/O12 UART Request To Send PROG_FUNC2 UART_nCTS I/O6 UART Clear To Send PROG_FUNC3 UART_nDCD I/O12 UART Data Carrier Detect PROG_FUNC4 SMDAT OD12 SMBus/I2C Data The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". PROG_FUNC5 SMCLK OD12 SMBus/I2C Clock The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". PROG_FUNC6 UART_nDTR I/O12 UART Data Terminal Ready PROG_FUNC7 UART_nDSR I/O10 UART Data Set Ready USB5734 DS00001854B-page 26  2015 Microchip Technology Inc. 4.0 DEVICE CONNECTIONS 4.1 Power Connections Figure 4-1 illustrates the device power connections. 4.2 SPI ROM Connections Figure 4-2 illustrates the device SPI ROM connections. Refer to Section 7.1, "SPI Master Interface," on page 33 for additional information on this device interface. FIGURE 4-1: POWER CONNECTIONS FIGURE 4-2: SPI ROM CONNECTIONS +3.3V Supply USB5734 3.3V Internal Logic VDD33 (4x) VSS 1.2V Internal Logic +1.2V Supply VDD12 (8x) USB5734 SPI_CE_N SPI_CLK SPI_DO SPI_DI SPI ROM CE# CLK DO DI  2015 Microchip Technology Inc. DS00001854B-page 27 USB5734 4.3 SMBus Slave Connections Figure 4-3 illustrates the device SMBus slave connections. Refer to Section 7.2, "SMBus Slave Interface," on page 33 for additional information on this device interface. 4.4 I2C Bridge Connections Figure 4-4 illustrates the device I2C bridge connections. Refer to Section 7.3, "I2C Bridge Interface," on page 33 for additional information on this device interface. 4.5 UART Bridge Connections Figure 4-5 illustrates the device UART bridge connections. Refer to Section 7.4, "Two Pin Serial Port (UART) Interface," on page 34 for additional information on this device interface. FIGURE 4-3: SMBUS SLAVE CONNECTIONS FIGURE 4-4: I2C BRIDGE CONNECTIONS FIGURE 4-5: UART BRIDGE CONNECTIONS +3.3V USB5734 SMCLK SMDAT SMBus Master Clock Data 10K +3.3V 10K +3.3V 10K +3.3V 10K I2C_SLV_CFG1 I2C_SLV_CFG0 +3.3V USB5734 SMCLK SMDAT I 2 C Slave Clock Data 10K +3.3V 10K I2C_SLV_CFG1 I2C_SLV_CFG0 X X No Connect USB5734 UART_RX UART_TX UART TX RX 10K USB5734 DS00001854B-page 28  2015 Microchip Technology Inc. 5.0 MODES OF OPERATION The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the RESET_N pin, as shown in Table 5-1. The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation. TABLE 5-1: MODES OF OPERATION RESET_N Input Summary 0 Standby Mode: This is the lowest power mode of the device. No functions are active other than monitoring the RESET_N input. All port interfaces are high impedance and the PLL is halted. Refer to Section 8.3.2, "External Chip Reset (RESET_N)" for additional information on RESET_N. 1 Hub (Normal) Mode: The device operates as a configurable USB hub with battery charger detection. This mode has various sub-modes of operation, as detailed in Figure 5-1. Power consumption is based on the number of active ports, their speed, and amount of data received. FIGURE 5-1: HUB MODE FLOWCHART Combine OTP Config Data In SPI Mode & Ext. SPI ROM present? YES NO Run From External SPI ROM Hub Connect (Hub.Connect) (SPI_INIT) Normal operation SMBus Host Present? RESET_N deasserted Modify Config Based on Config Straps (CFG_RD) Load Config from Internal ROM YES NO (STRAP) UART Present? YES NO Perform SMBus/I2 C Initialization SOC Done? NO YES (SOC_CFG) (CDC) Expose CDC Interface (OTP_CFG)  2015 Microchip Technology Inc. DS00001854B-page 29 USB5734 5.1 Boot Sequence 5.1.1 STANDBY MODE If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode and must be re-initialized after RESET_N is negated high. 5.1.2 SPI INITIALIZATION STAGE (SPI_INIT) The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset, the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal ROM (CFG_RD stage). When using an external SPI ROM, a 1 Mbit, 60 MHz or faster ROM must be used. Both 1- and 2-bit SPI operation are supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also supported. If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_RD stage). 5.1.3 CONFIGURATION READ STAGE (CFG_RD) In this stage, the internal firmware loads the default values from the internal ROM and then uses the configuration strapping options to override the default values. Refer to Section 3.4, "Configuration Straps and Programmable Functions" for information on usage of the various device configuration straps. 5.1.4 STRAP READ STAGE (STRAP) In this stage, the firmware registers the configuration strap settings on the SPI_DO and SPI_CLK pins. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])" for information on configuring these straps. If configured for SMBus Slave Mode, the next state will be SOC_CFG. If configured for UART Mode, the device will become a UART bridging combination device and the next state will be CDC. If neither condition is met, the next state is OTP_CFG. 5.1.5 SOC CONFIGURATION STAGE (SOC_CFG) In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB device descriptors and port electrical settings. There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When the SOC has completed configuring the device, it must write to register 0xFF to end the configuration. 5.1.6 CDC CONFIGURATION STAGE (CDC) If the device is configured in UART Mode, (UART Bridge), the hub feature controller will identify itself as a CDC UART device and move to the OTP_CFG. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])" for information on configuring the UART Mode. 5.1.7 OTP CONFIGURATION STAGE (OTP_CFG) Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is programmed. After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present. Once VBUS is present, and battery charging is enabled, the device will transition to the Battery Charger Detection Stage. If VBUS is present, and battery charging is not enabled, the device will transition to the Connect stage. USB5734 DS00001854B-page 30  2015 Microchip Technology Inc. 5.1.8 HUB CONNECT STAGE (HUB.CONNECT) Once the CHGDET stage is completed, the device enters the Hub Connect stage. USB connect can be initiated by asserting the VBUS pin function high. The device will remain in the Hub Connect stage indefinitely until the VBUS pin function is deasserted. 5.1.9 NORMAL MODE Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the system. If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub.Connect stage until the soft disconnect is negated.  2015 Microchip Technology Inc. DS00001854B-page 31 USB5734 6.0 DEVICE CONFIGURATION The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly function when attached to a USB host controller. The hub can be configured either internally or externally depending on the implemented interface. Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5734 functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch programming tool. For additional information on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5734 product page at www.microchip.com/USB5734. 6.1 Customer Accessible Functions The following USB or SMBus accessible functions are available to the customer via the Pro-Touch Programming Tool. 6.1.1 USB ACCESSIBLE FUNCTIONS 6.1.1.1 I2C Bridging Access over USB Access to I2C devices is performed as a pass-through operation from the USB Host. The device firmware has no knowledge of the operation of the attached I2C device. For more information, refer to the Microchip USB5734 product page and SDK at www.microchip.com/USB5734. 6.1.1.2 SPI Access over USB Access to an attached SPI device is performed as a pass-through operation from the USB Host. The device firmware has no knowledge of the operation of the attached SPI device. For more information, refer to the Microchip USB5734 product page and SDK at www.microchip.com/USB5734. 6.1.1.3 UART Access over USB Access to UART devices is performed as a pass-through operation from the USB Host. The device firmware has no knowledge of the operation of the attached UART device. For more information, refer to the Microchip USB5734 product page and SDK at www.microchip.com/USB5734. 6.1.1.4 OTP Access over USB The OTP ROM in the device is accessible via the USB bus. All OTP parameters can be modified to the USB Host. The OTP operates in Single Ended mode. For more information, refer to the Microchip USB5734 product page and SDK at www.microchip.com/USB5734. 6.1.1.5 Battery Charging Access over USB The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than the preprogrammed or OTP programmed behavior is desired. For more information, refer to the Microchip USB5734 product page and SDK at www.microchip.com/USB5734. Note: Device configuration straps and programmable pins are detailed in Section 3.4, "Configuration Straps and Programmable Functions," on page 16. Refer to Section 7.0, "Device Interfaces" for detailed information on each device interface. Note: For additional programming details, refer to the Pro-Touch programming tool. Note: Refer to Section 7.3, "I2C Bridge Interface," on page 33 for additional information on the I2C interface. Note: Refer to Section 7.1, "SPI Master Interface," on page 33 for additional information on the SPI. Note: Refer to Section 7.4, "Two Pin Serial Port (UART) Interface," on page 34 for additional information on the UART interface. USB5734 DS00001854B-page 32  2015 Microchip Technology Inc. 6.1.2 SMBUS ACCESSIBLE FUNCTIONS OTP access and configuration of specific device functions are possible via the USB5734 SMBus. All OTP parameters can be modified via the SMBus Host. The OTP can be programmed to operate in Single-Ended, Differential, Redundant, or Differential Redundant mode, depending on the level of reliability required. For more information, refer to AN1903 - “Configuration Options for the USB5734 and USB5744” application note at www.microchip.com/AN1903.  2015 Microchip Technology Inc. DS00001854B-page 33 USB5734 7.0 DEVICE INTERFACES The USB5734 provides multiple interfaces for configuration and external memory access. This section details the various device interfaces and their usage: • SPI Master Interface • SMBus Slave Interface • I2C Bridge Interface • Two Pin Serial Port (UART) Interface 7.1 SPI Master Interface The device is capable of code execution from an external SPI ROM. When configured for SPI Mode, on power up the firmware looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal ROM. 7.2 SMBus Slave Interface The device includes an integrated SMBus slave interface, which can be used to access internal device run time registers or program the internal OTP memory. SMBus slave detection is accomplished by detection of pull-up resistors on both the SMDAT and SMCLK signals. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])" for additional information. 7.3 I2C Bridge Interface The I2C Bridge interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The I2C Bridge conforms to the Fast-Mode I2C Specification (400 kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility. The device acts as the master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and generates the START and STOP conditions. The I2C Bridge interface frequency is configurable through the I2C Bridging commands. I2C Bridge frequencies are derived from the formula 626KHz/n, where n is any integer from 1 to 256. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])" for additional information. Note: For details on how to enable each interface, refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])". For information on device connections, refer to Section 4.0, "Device Connections". For information on device configuration, refer to Section 6.0, "Device Configuration". Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5734 functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch programming tool. For additional information on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5734 product page at www.microchip.com/USB5734. Note: For SPI timing information, refer to Section 9.6.6, "SPI Timing". Note: All device configuration must be performed via the Pro-Touch Programming Tool. For additional information on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5734 product page at www.microchip.com/USB5734. USB5734 DS00001854B-page 34  2015 Microchip Technology Inc. 7.4 Two Pin Serial Port (UART) Interface The device incorporates a fully programmable, universal asynchronous receiver/transmitter (UART) that is functionally compatible with the NS 16550AF, 16450, 16450 ACE registers and the 16C550A. The UART performs serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. Two sets of baud rates are provided: 24 Mhz and 16 MHz. When the 24 Mhz source clock is selected, standard baud rates from 50 to 115.2 K are available. When the source clock is 16 MHz, baud rates from 125 K to 1,000 K are available. The character options are programmable for the transmission of data in word lengths of from five to eight, 1 start bit; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UART contains a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UART is also capable of supporting the MIDI data rate. 7.4.1 TRANSMIT OPERATION Transmission is initiated by writing the data to be sent to the TX Holding Register or TX FIFO (if enabled). The data is then transferred to the TX Shift Register together with a start bit and parity and stop bits as determined by settings in the Line Control Register. The bits to be transmitted are then shifted out of the TX Shift Register in the order Start bit, Data bits (LSB first), Parity bit, Stop bit, using the output from the Baud Rate Generator (divided by 16) as the clock. If enabled, a TX Holding Register Empty interrupt will be generated when the TX Holding Register or the TX FIFO (if enabled) becomes empty. When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of data for transmission at a time. Transmission will continue until the TX FIFO is empty. The FIFO’s readiness to accept more data is indicated by interrupt. 7.4.2 RECEIVE OPERATION Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided by the Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive clock. When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of this register.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register. If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Register or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors. When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of received data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is available when the RX FIFO contains 1, 4, 8 or 14 bytes of data. Note: Extensions to the I2C Specification are not supported. All device configuration must be performed via the Pro-Touch Programming Tool. For additional information on the Pro-Touch programming tool, contact your local sales representative.  2015 Microchip Technology Inc. DS00001854B-page 35 USB5734 8.0 FUNCTIONAL DESCRIPTIONS This section details various USB5734 functions, including: • Downstream Battery Charging • FlexConnect • Resets • Link Power Management (LPM) • Remote Wakeup Indicator • Port Control Interface 8.1 Downstream Battery Charging The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the device. Those components must be provided externally by the OEM. If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTL[4:1] pins, is on a per port basis. For example, the OEM can configure two ports to support battery charging through high current power FETs and leave the other two ports as standard USB ports. For additional information, refer to the Microchip USB5734 Battery Charging application note on the Microchip.com USB5734 product page at www.microchip.com/USB5734. 8.2 FlexConnect This feature allows the upstream port to be swapped with downstream physical port 1. Only downstream port 1 can be swapped physically. Using port remapping, any logical port (number assignment) can be swapped with the upstream port (non-physical). FlexConnect is enabled/disabled via the FLEXCONNECT control bit in the Connect Configuration register (address 0x318E). The FLEXCONNECT configuration bit switches the port. This bit can be controlled via the I2C interface or via the FLEXCMD pin (PROG_FUNC6 in configurations 1 or 2). Toggling of FLEXCMD will cause an interrupt to the device firmware. The firmware will then change the port direction based on the input value. Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" for additional information. For additional information, refer to the Microchip USB5734 FlexConnect application note on the Microchip.com USB5734 product page. FIGURE 8-1: BATTERY CHARGING EXTERNAL POWER SUPPLY SOC VBUS[n] PRT_CTL[n] INT SCL SDA Microchip Hub DC Power USB5734 DS00001854B-page 36  2015 Microchip Technology Inc. 8.3 Resets The device includes the following chip-level reset sources: • Power-On Reset (POR) • External Chip Reset (RESET_N) • USB Bus Reset 8.3.1 POWER-ON RESET (POR) A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.1, "Power-On and Configuration Strap Timing," on page 45. 8.3.2 EXTERNAL CHIP RESET (RESET_N) A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the specifications in Section 9.6.2, "Reset and Configuration Strap Timing," on page 45. While reset is asserted, the device (and its associated external circuitry) enters Standby Mode and consumes minimal current. Assertion of RESET_N causes the following: 1. The PHY is disabled and the differential pairs will be in a high-impedance state. 2. All transactions immediately terminate; no states are saved. 3. All internal registers return to the default state. 4. The external crystal oscillator is halted. 5. The PLL is halted. 8.3.3 USB BUS RESET In response to the upstream port signaling a reset to the device, the device performs the following: 1. Sets default address to 0. 2. Sets configuration to Unconfigured. 3. Moves device from suspended to active (if suspended). 4. Complies with the USB Specification for behavior after completion of a reset sequence. The host then configures the device in accordance with the USB Specification. 8.4 Link Power Management (LPM) The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1. Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating Conditions**," on page 41, prior to (or coincident with) the assertion of RESET_N. Note: The device does not propagate the upstream USB reset to downstream devices. TABLE 8-1: LPM STATE DEFINITIONS State Description Entry/Exit Time to L0 L2 Suspend Entry: ~3 ms Exit: ~2 ms (from start of RESUME) L1 Sleep Entry: <10 us Exit: <50 us L0 Fully Enabled (On) -  2015 Microchip Technology Inc. DS00001854B-page 37 USB5734 8.5 Remote Wakeup Indicator The remote wakeup indicator feature uses USB2_SUSP_IND as a side band signal to wake up the host when in USB2.0 suspend. This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration bit in the hub configuration space register CFG3. The only way to control the bit is by configuration EEPROM, SMBus or internal ROM default setting. The state is only modified during a power on reset, or hardware reset. No dynamic reconfiguring of this capability is possible. When HUB_RESUME_INHIBIT = ‘0’, Normal Resume Behavior per the USB 2.0 specification When HUB_RESUME_INHIBIT = ‘1’, Modified Resume Behavior is enabled For additional information, refer to the Microchip USB5734 Suspend Indicator application note on the Microchip.com USB5734 product page. 8.6 Port Control Interface Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled directly from the USB hub, or via the processor. Additionally, smart port controllers can be controlled via the I2C interface. The device can be configured into the following port control modes: • Ganged Mode • Combined Mode Port connection in various modes are detailed in the following subsections. 8.6.1 PORT CONNECTION IN GANGED MODE In this mode, one pin (GANG_PWR) is used to control port power and over-current sensing. 8.6.2 PORT CONNECTION IN COMBINED MODE 8.6.2.1 Port Power Control using USB Power Switch When operating in combined mode, the device will have one port power control and over-current sense pin for each downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation, the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not interfere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up. Note: The USB2_SUSP_IND signal only indicates the USB2.0 state. USB5734 DS00001854B-page 38  2015 Microchip Technology Inc. 8.6.2.2 Port Power Control using Poly Fuse When using the device with a poly fuse, there is no need for an output power control. To maintain consistency, the same circuit will be used. A single port power control and over-current sense for each downstream port is still used from the Hub's perspective. When disabling port power, the driver will actively drive a '0'. This will have no effect as the external diode will isolate pin from the load. When port power is enabled, it will disable the output driver and enable the pull-up resistor. This means that the pull-up resistor is providing 3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will be at 0.7 volts, and the Schmidt trigger input will register this as a low resulting in an over-current detection. The open drain output does not interfere. FIGURE 8-2: PORT POWER CONTROL WITH USB POWER SWITCH Note: The USB 2.0 and USB 3.0 bPwrOn2PwrGood descriptors must be set to 0 when using poly-fuse mode. Refer to Microchip application note AN1903 “Configuration Options for the USB5734 and USB5744” for details on how to change these values. USB Power Switch 50k PRTPWR EN OCS OCS Pull-Up Enable 5V USB Device FILTER PRT_CTLx  2015 Microchip Technology Inc. DS00001854B-page 39 USB5734 8.6.2.3 Port Power Control with Single Poly Fuse and Multiple Loads Many customers use a single poly fuse to power all their devices. For the ganged situation, all power control pins must be tied together. FIGURE 8-3: PORT POWER CONTROL USING A POLY FUSE FIGURE 8-4: PORT POWER CONTROL WITH GANGED CONTROL WITH POLY FUSE PRT_CTLx 50k PRTPWR OCS USB Device Pull-Up Enable 5V Poly Fuse FILTER Pull-Up Enable USB Device Poly Fuse 5V Pull-Up Enable Pull-Up Enable 50k 50k 50k PRTPWR OCS USB Device USB Device PRT_CTLx PRT_CTLy PRT_CTLz USB5734 DS00001854B-page 40  2015 Microchip Technology Inc. 8.6.3 PORT CONTROLLER CONNECTION EXAMPLE FIGURE 8-5: USB5734 WITH 4 GENERIC PORT POWER CONTROLLERS (2 BC ENABLED) Note: The CFG_BC_EN configuration strap must be properly configured to enable battery charging on the appropriate ports. For example, in the application shown in Figure 8-5, CFG_BC_EN must be connected to an external 10 kΩ pull-down resistor to enable battery charging on Ports 1 and 2. For more information on the CFG_BC_EN configuration strap, refer to Section 3.4.4, "Battery Charging Configuration (CFG_BC_EN)". USB5734 Port 1 Connector Generic Port Power Controller POWER (High Current) (BC Enabled) OCS D+ D- VBUS D+ D- Port 2 Connector Generic Port Power Controller POWER (High Current) (BC Enabled) OCS D+ D- VBUS D+ D- PRT_CTL2 PRT_CTL1 Port 3 Connector Generic Port Power Controller POWER OCS D+ D- VBUS D+ D- PRT_CTL3 Port 4 Connector Generic Port Power Controller POWER OCS D+ D- VBUS D+ D- PRT_CTL4  2015 Microchip Technology Inc. DS00001854B-page 41 USB5734 9.0 OPERATIONAL CHARACTERISTICS 9.1 Absolute Maximum Ratings* +1.2 V Supply Voltage (VDD12) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +1.32 V +3.3 V Supply Voltage (VDD33) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V Positive voltage on input signal pins, with respect to ground (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 V Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V Positive voltage on XTALI/CLK_IN, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.63 V Positive voltage on USB DP/DM signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6.0 V Positive voltage on USB 3.0 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground . . . . . . . . . .1.32 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125oC Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020 HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit. Note 2: This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLK_IN, and XTALO *Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 9.2, "Operating Conditions**", Section 9.5, "DC Specifications", or any other applicable section of this specification is not implied. 9.2 Operating Conditions** +1.2 V Supply Voltage (VDD12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.08 V to +1.32 V +3.3 V Supply Voltage (VDD33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V Input Signal Pins Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V XTALI/CLK_IN Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V USB 2.0 DP/DM Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V USB 3.0 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +1.32 V Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Note 3 +1.2 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 µs +3.3 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 µs Note 3: 0oC to +70oC for commercial version, -40oC to +85oC for industrial version. **Proper operation of the device is guaranteed only within the ranges specified in this section. Note: Do not drive input signals without power supplied to the device. USB5734 DS00001854B-page 42  2015 Microchip Technology Inc. 9.3 Package Thermal Specifications FIGURE 9-1: SUPPLY RISE TIME MODEL TABLE 9-1: PACKAGE THERMAL PARAMETERS Symbol °C/W Velocity (Meters/s) JA 25 0 22 1 JT 0.2 0 0.3 1 JC 2.5 0 2.5 1 Note: Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51. TABLE 9-2: MAXIMUM POWER DISSIPATION Parameter Value Units PD(max) 1400 mW t10% 10% 90% Voltage TRT t90% Time 3.3 V 100% VSS VDD33 90% 100% 1.2 V VDD12  2015 Microchip Technology Inc. DS00001854B-page 43 USB5734 9.4 Power Consumption This section details the power consumption of the device as measured during various modes of operation. Power dissipation is determined by temperature, supply voltage, and external source/sink requirements. TABLE 9-3: DEVICE POWER CONSUMPTION Typical (mA) Typical Power VDD33 VDD12 (mW) Reset 0.8 1.8 4.8 No VBUS 2.0 5.0 12.6 Global Suspend 2.0 5.2 12.9 4 FS Ports 39 35 170 4 HS Ports 53 42 222 4 SS Ports 55 683 1001 4 SS/HS Ports 93 688 1132 USB5734 DS00001854B-page 44  2015 Microchip Technology Inc. 9.5 DC Specifications Note 4: The PROG_FUNC3 pin has a Schmitt trigger hysteresis minimum of 10 mV and a maximum of 60 mV. Note 5: XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator. Note 6: Refer to the USB 3.0 Specification for USB DC electrical characteristics. TABLE 9-4: I/O DC ELECTRICAL CHARACTERISTICS Parameter Symbol Min Typical Max Units Notes I Type Input Buffer Low Input Level High Input Level VIL VIH 2.1 0.9 V V IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis (VIHT - VILT) VIL VIH VHYS 1.9 9 20 0.9 40 V V mV Note 4 O6 Type Output Buffer Low Output Level High Output Level VOL VOH VDD33-0.4 0.4 V V IOL = 6 mA IOH = -6 mA O10 Type Output Buffer Low Output Level High Output Level VOL VOH VDD33-0.4 0.4 V V IOL = 10 mA IOH = -10 mA O12 Type Output Buffer Low Output Level High Output Level VOL VOH VDD33-0.4 0.4 V V IOL = 12 mA IOH = -12 mA OD12 Type Output Buffer Low Output Level VOL 0.4 V IOL = 12 mA ICLK Type Input Buffer (XTALI Input) Low Input Level High Input Level VIL VIH 0.85 0.50 VDD33 V V Note 5 IO-U Type Buffer (See Note 6) Note 6  2015 Microchip Technology Inc. DS00001854B-page 45 USB5734 9.6 AC Specifications This section details the various AC timing specifications of the device. 9.6.1 POWER-ON AND CONFIGURATION STRAP TIMING Figure 9-2 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in Section 9.2, "Operating Conditions**," on page 41. Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.2, "Reset and Configuration Strap Timing" for additional details. 9.6.2 RESET AND CONFIGURATION STRAP TIMING Figure 9-3 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to Section 8.3, "Resets" for additional information on resets. Refer to Section 3.4, "Configuration Straps and Programmable Functions" for additional information on configuration straps. FIGURE 9-2: POWER-ON CONFIGURATION STRAP VALID TIMING TABLE 9-5: POWER-ON CONFIGURATION STRAP LATCHING TIMING Symbol Description Min Typ Max Units tcsh Configuration strap hold after external power supplies at operational levels 1 ms FIGURE 9-3: RESET_N CONFIGURATION STRAP TIMING TABLE 9-6: RESET_N CONFIGURATION STRAP TIMING Symbol Description Min Typ Max Units trstia RESET_N input assertion time 5 s tcsh Configuration strap pins hold after RESET_N deassertion 1 ms All External Power Supplies Vopp Configuration Straps tcsh RESET_N Configuration Straps trstia tcsh USB5734 DS00001854B-page 46  2015 Microchip Technology Inc. 9.6.3 USB TIMING All device USB signals confirm to the voltage, power, and timing characteristics/specifications as set forth in the Universal Serial Bus Specification. Please refer to the Universal Serial Bus Specification, Revision 3.0, available at http:// www.usb.org/developers/docs. 9.6.4 I2C TIMING All device I2C signals confirm to the 100KHz Standard Mode (Sm) voltage, power, and timing characteristics/specifications as set forth in the I 2C-Bus Specification. Please refer to the I 2C-Bus Specification, available at http://www.nxp.com/ documents/user_manual/UM10204.pdf. 9.6.5 SMBUS TIMING All device SMBus signals confirm to the voltage, power, and timing characteristics/specifications as set forth in the System Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available at http://smbus.org/specs. Note: The clock input must be stable prior to RESET_N deassertion. Configuration strap latching and output drive timings shown assume that the Power-On reset has finished first otherwise the timings in Section 9.6.1, "Power-On and Configuration Strap Timing" apply.  2015 Microchip Technology Inc. DS00001854B-page 47 USB5734 9.6.6 SPI TIMING This section specifies the SPI timing requirements for the device. FIGURE 9-4: SPI TIMING TABLE 9-7: SPI TIMING (30 MHZ OPERATION) Symbol Description Min Typ Max Units tfc Clock frequency 30 MHz tceh Chip enable (SPI_CE_EN) high time 100 ns tclq Clock to input data 13 ns tdh Input data hold time 0 ns tos Output setup time 5 ns toh Output hold time 5 ns tov Clock to output valid 4 ns tcel Chip enable (SPI_CE_EN) low to first clock 12 ns tceh Last clock to chip enable (SPI_CE_EN) high 12 ns TABLE 9-8: SPI TIMING (60 MHZ OPERATION) Symbol Description Min Typ Max Units tfc Clock frequency 60 MHz tceh Chip enable (SPI_CE_EN) high time 50 ns tclq Clock to input data 9 ns tdh Input data hold time 0 ns tos Output setup time 5 ns toh Output hold time 5 ns tov Clock to output valid 4 ns tcel Chip enable (SPI_CE_EN) low to first clock 12 ns tceh Last clock to chip enable (SPI_CE_EN) high 12 ns SPI_CLK SPI_DI SPI_DO SPI_CE_N tcel tfc tclq tceh tdh tos toh tov toh USB5734 DS00001854B-page 48  2015 Microchip Technology Inc. 9.7 Clock Specifications The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input. If the singleended clock oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum. It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XTALI/XTALO). The following circuit design (Figure 9-5) and specifications (Table 9-9) are required to ensure proper operation. 9.7.1 CRYSTAL SPECIFICATIONS It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XTALI/XTALO). Refer to Table 9-9 for the recommended crystal specifications. Note 7: Frequency Deviation Over Time is also referred to as Aging. FIGURE 9-5: 25MHZ CRYSTAL CIRCUIT TABLE 9-9: CRYSTAL SPECIFICATIONS PARAMETER SYMBOL MIN NOM MAX UNITS NOTES Crystal Cut AT, typ Crystal Oscillation Mode Fundamental Mode Crystal Calibration Mode Parallel Resonant Mode Frequency Ffund - 25.000 - MHz Frequency Tolerance @ 25oC Ftol - - ±50 PPM Note 7 Frequency Stability Over Temp Ftemp - - ±50 PPM Note 7 Frequency Deviation Over Time Fage - ±3 to 5 - PPM Total Allowable PPM Budget - - ±100 PPM Note 8 Shunt Capacitance CO - 7 typ - pF Load Capacitance CL - 20 typ - pF Drive Level PW 100 - - uW Equivalent Series Resistance R1 - - 50 Ω Operating Temperature Range Note 8 - Note 9 oC XTALI/CLK_IN Pin Capacitance - 3 typ - pF Note 10 XTALO Pin Capacitance - 3 typ - pF Note 10 USB5734 XTALO XTALI Y1 C1 C2  2015 Microchip Technology Inc. DS00001854B-page 49 USB5734 Note 8: 0 °C for commercial version, -40 °C for industrial version. Note 9: +70 °C for commercial version, +85 °C for industrial version. Note 10: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this value. The XTALI/CLK_IN pin, XTALO pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors. These two external load capacitors determine the accuracy of the 25.000 MHz frequency. 9.7.2 EXTERNAL REFERENCE CLOCK (CLK_IN) When using an external reference clock, the following input clock specifications are suggested: • 25 MHz • 50% duty cycle ±10%, ±100 ppm • Jitter < 100 ps RMS USB5734 DS00001854B-page 50  2015 Microchip Technology Inc. 10.0 PACKAGE OUTLINES Note: For the most current package drawings, see the Microchip Packaging Specification at: http://www.microchip.com/packaging. FIGURE 10-1: 64-SQFN PACKAGE (DRAWING)  2015 Microchip Technology Inc. DS00001854B-page 51 USB5734 FIGURE 10-2: 64-SQFN PACKAGE (DIMENSIONS) USB5734 DS00001854B-page 52  2015 Microchip Technology Inc. 11.0 REVISION HISTORY TABLE 11-1: REVISION HISTORY Revision Level & Date Section/Figure/Entry Correction DS00001854B (04-16-15) Features Changed Environmental feature bullet from “4kV HBM JESD22-A114F ESD protection” to “3kV HBM JESD22-A114F ESD protection” Section 9.2, Operating Conditions** Changed XTALI/CLK_IN Voltage to -0.3V to +3.6V Table 9-9, "Crystal Specifications" Total Allowable PPM budget changed to 100pm, removed notes under table regarding “Frequency Tolerance” and “Frequency and Transmitter Clock Frequency” Section 9.7.2, External Reference Clock (CLK_IN) Changed +-350ppm t +-100 ppm Figure 3-1, "64-SQFN Pin Assignments", Table 3-1, "64-SQFN Pin Assignments" Modified pin 32 from “PRT_CTL4/ GANG_PWR” to “PRT_CTL4/GANG_PWR” Table 3-4, "USB Port Control Pin Descriptions" Revised description of Pin 1, GANG_PWR Table 1-1, "General Terms" and throughout document Replaced the term Hub Controller with Hub Feature Controller, added definition in Table 1- 1, "General Terms". Section 6.1.2, SMBus Accessible Functions Added web link to AN1903 Removed PortMap feature throughout document. Table 3-7, "Miscellaneous Pin Descriptions" Modified RESET_N pin description Section 8.4, Link Power Management (LPM) Removed “per the USB 3.0 Specification” from the first sentence. Removed last sentence “For additional information, refer to the USB 3.0 Specification.” Table 9-2, "MAXIMUM Power Dissipation" Added Table 9-2. Section 9.7, "Clock Specifications",Figure 9-5, Table 9-9, "Crystal Specifications" Updated these sections. Section 9.7.2, External Reference Clock (CLK_IN) Oscillator changed from “35MHz” to “25 MHz” Section 9.6.6, SPI Timing Removed SPI interface configure note Section 9.1, Absolute Maximum Ratings* Added “Positive voltage on USB 3.0 USB3UP- _xxxx and USB3DN_xxxx signal pins, with respect to ground...1.32 V Changed XTALI positive voltage from 2.1V to 3.63V. Changed “USB 3.0 DP/DM Signal Pins Voltage” to “USB 3.0 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage” Section 8.6.2, "Port Connection in Combined Mode," on page 37 Added note under Section 8.6.2  2015 Microchip Technology Inc. DS00001854B-page 53 USB5734 Product Identification System on page 55 Updated ordering information Section 9.1, "Absolute Maximum Ratings*," on page 41 Updated +1.2V supply voltage absolute max value. Added HBM ESD performance specification. Table 9-1, “Package Thermal Parameters,” on page 42 Added package thermal parameters. Worldwide Sales and Service on page 57 Updated Worldwide Sales Listing Table 9-4, “I/O DC Electrical Characteristics,” on page 44 Updated I buffer type high input level max. Added IS buffer type Schmitt trigger hysteresis values and note for PROG_FUNC3 pin. Cover, All Updated document title to “4-Port SS/HS Controller Hub” Removed PortMap references. Removed sentence: ”These circuits are used to detect the attachment and type of a USB charger and provide an interrupt output to indicate charger information is available to be read from the device’s status registers via the serial interface.“ FIGURE 3-1: 64-SQFN Pin Assignments on page 8 Added configuration strap note under figure. Table 3-6, “Programmable Function Pin Descriptions,” on page 13, Table 3-15, Table 3-16, Table 3-17, Table 3-18, Table 3-19, Table 3-20 Added note to PROG_FUNC[7:1] buffer type column, which indicates the following: “The PROG_FUNC2 buffer type is I/O6. The PROG_FUNC7 buffer type is I/O10. All other PROG_FUNCx pins have a buffer type of I/ O12.” Table 3-15, Table 3-16, Table 3-17, Table 3-18, Table 3-19, Table 3-20 Updated PROG_FUNC2 and PROG_FUNC7 buffer type definitions to reflect O6 and O10 outputs, respectively. Table 3-9, “Buffer Types,” on page 15, Table 9-4, “I/O DC Electrical Characteristics,” on page 44 Added O10 buffer type Table 3-15, “Configuration 1 PROG_- FUNC[7:1] Function Assignment,” on page 19 Updated PROG_FUNC7 name in Configuration 1 - Mixed Mode from SUSP_IND to USB2_SUSP_IND and clarified description. Section 3.4.5.6, "Configuration 6 - Full UART Mode," on page 25 Added note: “When flow control is disabled, UART_nCTS, UART_nDCD, and UART_nDSR must not be left floating. In this case, these pins should include external pulldowns to maintain UART communication in Full UART Mode with no flow control.” Section 8.2, "FlexConnect," on page 35 Updated second paragraph to clarify proper FLEXCONNECT operation. Section 8.5, "Remote Wakeup Indicator," on page 37 Updated SUSP_IND to USB2_SUSP_IND and clarified the function is for USB2.0 only. DS00001854A (12-15-14) All Initial Release TABLE 11-1: REVISION HISTORY (CONTINUED) Revision Level & Date Section/Figure/Entry Correction USB5734 DS00001854B-page 54  2015 Microchip Technology Inc. THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support  2015 Microchip Technology Inc. DS00001854B-page 55 USB5734 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: USB5734 Tape and Reel Option: Blank = Standard packaging (tray) T = Tape and Reel( Note 1) Temperature Range: Blank = 0C to +70C (Commercial) I = -40C to +85C (Industrial) Package: MR = 64-pin SQFN Examples: a) USB5734/MR Tray, Commercial temp., 64-pin SQFN b) USB5734-I/MR Tray, Industrial temp., 64-pin SQFN c) USB5734T-I/MR Tape & reel, Industrial temp., 64-pin SQFN d) USB5734T/MR Tape & reel, Commercial temp., 64-pin SQFN Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. PART NO. Device Tape & Reel / Temperature Range [X] [-X] XX Package Option USB5734 DS00001854B-page 56  2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632772190 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS00001854B-page 57  2015 Microchip Technology Inc. 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These statements involve risks and uncertainties that could cause actual results to differ materially from such forward looking statements. Such risks and uncertainties include the actual timing of the closing of the acquisition, the satisfaction of the conditions to closing in the acquisition agreement, any termination of the acquisition agreement, the effect of the acquisition on Microchip’s and Micrel’s existing relationships with customers, employees and vendors and on Microchip’s and Micrel’s respective operating results and businesses; general economic, industry or political conditions in the U.S. or internationally; and the risks described from time to time in SEC reports including filings on Forms 10-K, 10-Q and 8-K. You can obtain copies of applicable Forms 10-K, 10-Q and 8-K and other relevant documents for free at Microchip’s website (www.microchip.com), at Micrel’s website (www.Micrel.com) or the SEC's website (www.sec.gov) or from commercial document retrieval services. You are cautioned not to place undue reliance on these forward-looking statements, which speak only as of the date such statements are made. We do not undertake any obligation to publicly update any forward-looking statements to reflect events, circumstances or new information after the date hereof.  Additional Information and Where to Find It Microchip will file a Registration Statement on Form S-4 that will include a proxy statement of Micrel in connection with the acquisition transaction. Investors and security holders are urged to read such document when it becomes available because it will contain important information about the transaction. Investors and security holders may obtain free copies of such document (when it becomes available) and other documents filed with the SEC at the SEC's web site at www.sec.gov. Microchip, Micrel and their directors and executive officers may be deemed to be participants in the solicitation of proxies from the shareholders of Micrel in connection with the acquisition transaction. Information regarding the special interests of these directors and executive officers in the transaction will be included in the proxy statement/prospectus described above. Additional information regarding the directors and executive officers of Microchip is also included in Microchip's proxy statement for its 2014 Annual Meeting of Stockholders, which was filed with the SEC on July 18, 2014. Additional information regarding the directors and executive officers of Micrel is also included in Micrel’s Annual Report on Form 10-K/A, which was filed with the SEC on April 24, 2015. These documents are available free of charge at the SEC's web site at www.sec.gov and as described above. 3 Micrel Overview  High quality Analog franchise with attractive product portfolio  Linear & Power Management (52%), LAN solutions (21%), Timing & Communications (25%) and Foundry Services (2%)  Diversified end markets  Industrial and Automotive (48%), Communications (36%) and Consumer (16%)  Technology leadership and innovation  Over 230 core new products introduced in the last 4 years  Over 400 patents granted  CY14 revenue of $248M  52.1% non-GAAP gross margin; 9.4% non-GAAP operating margin  Proprietary product line supports consistent profitability  $95M cash and investments on the balance sheet at 3/31/15  No debt  Headquartered in San Jose, CA  698 employees worldwide 4 Diverse Customer Base Of Industry Leaders Industrial & Automotive Communications Consumer No customer > 10% of revenues 5 Linear and Power Solutions 6 LAN Solutions 7 Timing & Communication Solutions Clock & Timing Solutions High Speed Communications MEMS resonator Products Consumer Industrial & Automotive Communication s Markets 8 Compelling Strategic Rationale  Enhances Microchip’s Analog product portfolio through the addition of a rich portfolio of Linear and Power Management products that complement our offerings  Expands Microchip’s portfolio of LAN and connectivity solutions, giving us a richer product offering and additional applications and customers we can serve  Adds Timing and Communication products as a new set of products and business unit to Microchip  Microchip’s manufacturing and sales channel strengths can extend the reach of Micrel’s solutions into new applications and markets  Adds strong patent portfolio of over 400 patents to Microchip IP portfolio 9 Transaction Summary  Transaction value of $839M representing $14/share  $744M net of Micrel’s cash and investments  Micrel shareholders can elect to receive either Microchip shares or cash, but at least 42% of the transaction value must be in shares  Transaction will initially be mildly dilutive on a non GAAP basis  Microchip expects to do a share buy back to emulate a cash transaction  Expect transaction to be accretive on a non-GAAP basis in the first full quarter after the stock buy back  Expect transaction to close in early CQ3 2015  Will provide more guidance on revenue, gross margin, synergy and EPS impact after the transaction closes Thank You! www.microchip.com  2011 - 2014 Microchip Technology Inc. DS00001725B-page 1 Features • High Speed USB Mux for multiplexing the USB lanes between different functions - Switch the USB connector between two different functions - Up to 1GHz Bandwidth • USB Port ESD Protection (DP/DM) - ±15kV (air discharge) - ±15kV (contact discharge) - IEC 61000-4-2 level 4 ESD protection without external devices • flexPWRTM Technology - 30nA Active/Standby Current - Extremely low power design ideal for battery powered applications • Control inputs accommodate 1.8V to 5V inputs • DP/DM tolerate up to 5.5V • Industrial Operating Temperature -40°C to +85°C • 10 pin, QFN, RoHS compliant package; (1.3mm x 1.8mm x 0.55mm height, 0.4mm pitch) • 10 pin, QFN, RoHS compliant package; (1.6mm x 2.1mm x 0.55mm height, 0.5mm pitch) Block Diagram OE_N S DP DM ESD Protection HS USB Switch DM_2 DP_2 USB Connector USB 2.0 PHY, Processor, or Accessory Processor GND DM_1 DP_1 USB 2.0 PHY, Processor, or Accessory DP DM DP DM USB3740B VDD VDD ESD Protection USB3740B High Speed USB 2.0 Switch with ESD Protection and Low Standby Current USB3740B DS00001725B-page 2  2011 - 2014 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011 - 2014 Microchip Technology Inc. DS00001725B-page 3 USB3740B Table of Contents 1.0 General Description ........................................................................................................................................................................ 4 2.0 Pin Layout ....................................................................................................................................................................................... 5 3.0 Electrical Specifications .................................................................................................................................................................. 6 4.0 General Operation .......................................................................................................................................................................... 7 5.0 Application Notes ............................................................................................................................................................................ 8 6.0 Package Outlines ............................................................................................................................................................................ 9 The Microchip Web Site ...................................................................................................................................................................... 12 Customer Change Notification Service ............................................................................................................................................... 12 Customer Support ............................................................................................................................................................................... 12 Product Identification System ............................................................................................................................................................. 13 USB3740B DS00001725B-page 4  2011 - 2014 Microchip Technology Inc. 1.0 GENERAL DESCRIPTION The USB3740B is a USB 2.0 compliant High Speed switch that provides robust ESD protection to the interface in an extremely small package. Outstanding ESD robustness eliminates the need for external ESD protection devices to save eBOM cost and PCB area. The high bandwidth capabilities of the USB3740B enable extremely low high frequency loss and an exceptionally clean USB 2.0 High Speed eye diagram. 1.1 Reference Document Universal Serial Bus Specification, Revision 2.0 FIGURE 1-1: USB3740B USB 2.0 HIGH SPEED EYE DIAGRAM Input to Switch Output of Switch  2011 - 2014 Microchip Technology Inc. DS00001725B-page 5 USB3740B 2.0 PIN LAYOUT 2.1 Pin Diagram The USB3740B is available in both a 0.4mm pitch QFN (1.3mm x 1.8mm) and 0.5mm pitch QFN (1.55mm x 2.05mm) package. 2.2 Ball/Pin Definitions The following table details the ball/pin definitions for the package diagram above. FIGURE 2-1: USB3740B PACKAGE DIAGRAM Pin Name Type/ Direction Description 10 DP Analog USB Mux Output 9 DM Analog 2 DP_1 Analog USB Mux Input 1 1 DM_1 Analog 6 DP_2 Analog USB Mux Input 2 7 DM_2 Analog 8 GND Analog Ground 5 VDD Analog Power 4 S Digital Input Switch control. Refer to Table 4-1. 3 OE_N Digital Input Active low switch Output Enable. Refer to Table 4-1. DP_2 S OE_N DP VDD GND DM_2 3 4 5 6 7 10 9 8 2 1 DM DP_1 DM_1 USB3740B DS00001725B-page 6  2011 - 2014 Microchip Technology Inc. 3.0 ELECTRICAL SPECIFICATIONS 3.1 Absolute Maximum Ratings Stresses beyond the Absolute Maximum Ratings may damage the USB3740B. 3.2 Electrical Specifications TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Description Rating Unit VDD Voltage to GND -0.3 to 6.0 V Any other pin to GND -0.3 to VDD+0.5 V Operating Temperature Range -40 to +85 C Storage Temperature Range -55 to +150 C ESD Rating HBM (JESD 22) 8,000 V HBM (Pin to Ground) 8,000 V IEC-61000-4-2 15,000 (Air) 15,000 (Contact) V TABLE 3-2: ELECTRICAL SPECIFICATIONS Characteristic Symbol MIN TYP MAX Units Conditions VDD = 5.0V, TA = -40C to 85C, all typical values at TA = 25C unless otherwise noted. VDD Recommended Operating Conditions Input Voltage VDD 3.0 5.5 V Active/Standby IDD 30 175 nA USB Mux Characteristics USB Mux On Resistance RON_USB 1 2 5 ohm 0V < Vin < 3.3V 1 2 2.5 0V < Vin < 0.4V USB Mux Off Leakage IOFF_USB 100 200 nA 0V < Vin < 3.3V On Capacitance CON_USB 5 7 pF VDD = 3V Off Capacitance COFF_USB 3 4 pF VDD = 3V Off Isolation -30 -32 -40 dB RL = 50 ohm, F = 250MHz Crosstalk -30 -45 -60 dB RL = 50 ohm, F = 250MHz Bandwidth (-3dB) BW 950 1000 1100 MHz RL = 50 ohm, CL = 0pF 850 950 980 RL = 50 ohm, CL = 5pF 530 560 600 RL = 50 ohm, CL = 10pF Control Signal Characteristics Input Logic High Threshold VIN_H 1.4 V Input Logic Low Threshold VIN_L 0.4 V  2011 - 2014 Microchip Technology Inc. DS00001725B-page 7 USB3740B 4.0 GENERAL OPERATION The USB3740B is a high bandwidth switch suitable for many applications, including High Speed USB. The mux allows high speed signals to pass through and still meet HS USB signaling requirements. The USB3740B will protect the system from ESD stress events on all DP and DM pins. The USB3740B provides ESD protection to the IEC-61000 ESD specification. The USB mux is designed to pass High Speed USB signals to the USB connector, and allows for two USB inputs to be multiplexed into one USB output. The USB Mux is designed to pass USB signals from 0 to VDD. It is not designed to pass signals that go above VDD or below ground. The USB3740B switches are controlled by the digital signals OE_N and S, as shown in Table 4-1. TABLE 4-1: USB3740B SWITCH STATES DEFINITION OE_N S Switch State 1 X STANDBY: • Both switch paths disconnected. • Lowest power state 0 0 DP = DP1, DM = DM1: 0 1 DP = DP2, DM = DM2: USB3740B DS00001725B-page 8  2011 - 2014 Microchip Technology Inc. 5.0 APPLICATION NOTES 5.1 ESD Performance The USB3740B is protected from ESD strikes. By eliminating the requirement for external ESD protection devices, board space is conserved, and the board manufacturer is enabled to reduce cost. The advanced ESD structures integrated into the USB3740B protect the device whether or not it is powered up. 5.1.1 HUMAN BODY MODEL (HBM) PERFORMANCE HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. The USB3740B HBM performance is detailed in Table 3-1. 5.1.2 EN/IEC 61000-4-2 PERFORMANCE The EN/IEC 61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered down. Microchip contracts with Independent laboratories to test the USB3740B to EN/IEC 61000-4-2 in a working system. Reports are available upon request. Please contact your Microchip representative, and request information on 3rd party ESD test results. The reports show that systems designed with the USB3740B can safely provide the ESD performance shown in Table 3-1 without additional board level protection. In addition to defining the ESD tests, EN/IEC 61000-4-2 also categorizes the impact to equipment operation when the strike occurs (ESD Result Classification). The USB3740B maintains an ESD Result Classification 1 or 2 when subjected to an EN/IEC 61000-4-2 (level 4) ESD strike. Both air discharge and contact discharge test techniques for applying stress conditions are defined by the EN/IEC 61000-4-2 ESD document. 5.1.2.1 Air Discharge To perform this test, a charged electrode is moved close to the system being tested until a spark is generated. This test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and construction of the test equipment. 5.1.2.2 Contact Discharge The uncharged electrode first contacts the USB connector to prepare this test, and then the probe tip is energized. This yields more repeatable results, and is the preferred test method. The independent test laboratories contracted by Microchip provide test results for both types of discharge methods.  2011 - 2014 Microchip Technology Inc. DS00001725B-page 9 USB3740B 6.0 PACKAGE OUTLINES Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging. FIGURE 6-1: 10 PIN, 1.3MM X 1.8MM QFN PACKAGE OUTLINE USB3740B DS00001725B-page 10  2011 - 2014 Microchip Technology Inc. FIGURE 6-2: 10 PIN, 1.6MM X 2.1MM QFN PACKAGE OUTLINE  2011 - 2014 Microchip Technology Inc. DS00001725B-page 11 USB3740B APPENDIX A: DATA SHEET REVISION HISTORY TABLE A-1: REVISION HISTORY Revision Section/Figure/Entry Correction DS00001725B (08-21-14) Document is converted to Microchip template; Product Identification System page replaces Ordering Information. DS00001725A replaces the previous SMSC version, Rev. 1.2 Title changed from “High Speed Switch for Mobile and Portable Applications” to “High Speed USB 2.0 Switch with ESD Protection and Low Standby Current” Rev. 1.2 (07-30-12) Table 3-1, “Absolute Maximum Ratings,” on page 6 Corrected “Any other pin to GND” row’s rating to “- 0.3 to VDD+0.5V” Rev. 1.1 (12-15-11) Section 2.2, "Ball/Pin Definitions" In Section 2.2, changed the description of Pin #8 as follows: “Ground” Rev. 1.0 (08-03-11) Data Sheet Release USB3740B DS00001725B-page 12  2011 - 2014 Microchip Technology Inc. THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support  2011 - 2014 Microchip Technology Inc. DS00001725B-page 13 USB3740B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XXX Device Package Device: USB3740B Package: AI2 = 10-pin QFN (1.3mm x 1.8mm) AI9 = 10-pin QFN (1.6mm x 2.1mm) Tape and Reel Option: Blank = Tray packaging TR = Tape and Reel Examples: a) USB3740B-AI2-TR 10-pin QFN RoHS Compliant package (1.3mm x 1.8mm) Tape & Reel b) USB3740B-AI9-TR 10-pin QFN RoHS Compliant package (1.6mm x 2.1mm) Tape & Reel [X](1) Tape and Reel Option - Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Reel size is 4,000. - DS00001725B-page 14  2011 - 2014 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011 - 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632765369 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS00001725B-page 15  2011 - 2014 Microchip Technology Inc. AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Canada - Toronto Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-3019-1500 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 Taiwan - Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Dusseldorf Tel: 49-2129-3766400 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Pforzheim Tel: 49-7231-424750 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Venice Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Poland - Warsaw Tel: 48-22-3325737 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Worldwide Sales and Service 03/25/14 © 2006 Microchip Technology Inc. DS70046E dsPIC30F Family Reference Manual High-Performance Digital Signal Controllers DS70046E-page ii © 2006 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2006 Microchip Technology Inc. 70046E-page iii PAGE M SECTION 1. INTRODUCTION 1-1 Introduction ...................................................................................................................................................... 1-2 Manual Objective ............................................................................................................................................. 1-2 Device Structure ............................................................................................................................................... 1-3 Development Support ...................................................................................................................................... 1-4 Style and Symbol Conventions ........................................................................................................................ 1-4 Related Documents ..........................................................................................................................................1-6 Revision History ............................................................................................................................................... 1-7 SECTION 2. CPU 2-1 Introduction ...................................................................................................................................................... 2-2 Programmer’s Model ........................................................................................................................................ 2-4 Software Stack Pointer .....................................................................................................................................2-8 CPU Register Descriptions ............................................................................................................................. 2-11 Arithmetic Logic Unit (ALU) ............................................................................................................................ 2-17 DSP Engine .................................................................................................................................................... 2-18 Divide Support ................................................................................................................................................ 2-27 Instruction Flow Types ...................................................................................................................................2-27 Loop Constructs ............................................................................................................................................. 2-30 Address Register Dependencies .................................................................................................................... 2-35 Register Maps ................................................................................................................................................ 2-38 Related Application Notes ..............................................................................................................................2-40 Revision History ............................................................................................................................................. 2-41 SECTION 3. DATA MEMORY 3-1 Introduction ...................................................................................................................................................... 3-2 Data Space Address Generator Units (AGUs) ................................................................................................. 3-5 Modulo Addressing ..........................................................................................................................................3-7 Bit-Reversed Addressing ............................................................................................................................... 3-14 Control Register Descriptions ......................................................................................................................... 3-18 Related Application Notes ..............................................................................................................................3-23 Revision History ............................................................................................................................................. 3-24 SECTION 4. PROGRAM MEMORY 4-1 Program Memory Address Map ....................................................................................................................... 4-2 Program Counter .............................................................................................................................................. 4-4 Data Access from Program Memory ................................................................................................................ 4-4 Program Space Visibility from Data Space ...................................................................................................... 4-8 Program Memory Writes ................................................................................................................................ 4-10 PSV Code Examples ...................................................................................................................................... 4-11 Related Application Notes ..............................................................................................................................4-12 Revision History ............................................................................................................................................. 4-13 Table of Contents 70046E-page iv © 2006 Microchip Technology Inc. PAGE M SECTION 5. FLASH AND EEPROM PROGRAMMING 5-1 Introduction ...................................................................................................................................................... 5-2 Table Instruction Operation .............................................................................................................................. 5-2 Control Registers ............................................................................................................................................. 5-5 Run-Time Self-Programming (RTSP) .............................................................................................................5-10 Data EEPROM Programming ........................................................................................................................ 5-15 Design Tips .................................................................................................................................................... 5-21 Related Application Notes ..............................................................................................................................5-22 Revision History ............................................................................................................................................. 5-23 SECTION 6. RESET INTERRUPTS 6-1 Introduction ...................................................................................................................................................... 6-2 Non-Maskable Traps ........................................................................................................................................ 6-6 Interrupt Processing Timing ........................................................................................................................... 6-11 Interrupt Control and Status Registers ........................................................................................................... 6-14 Interrupt Setup Procedures ............................................................................................................................ 6-42 Design Tips .................................................................................................................................................... 6-44 Related Application Notes ..............................................................................................................................6-45 Revision History ............................................................................................................................................. 6-46 SECTION 7. OSCILLATOR 7-1 Introduction ...................................................................................................................................................... 7-2 Device Clocking and MIPS ............................................................................................................................... 7-5 Oscillator Configuration .................................................................................................................................... 7-6 Oscillator Control Registers – OSCCON and OSCTUN .................................................................................7-13 Primary Oscillator ........................................................................................................................................... 7-20 Crystal Oscillators/Ceramic Resonators ......................................................................................................... 7-22 Determining Best Values for Crystals, Clock Mode, C1, C2 and Rs .............................................................. 7-24 External Clock Input ....................................................................................................................................... 7-25 External RC Oscillator .................................................................................................................................... 7-26 Phase Locked Loop (PLL) ..............................................................................................................................7-30 Low-Power 32 kHz Crystal Oscillator .............................................................................................................7-31 Oscillator Start-up Timer (OST) ...................................................................................................................... 7-31 Internal Fast RC Oscillator (FRC) .................................................................................................................. 7-31 Internal Low-Power RC (LPRC) Oscillator ..................................................................................................... 7-32 Fail-Safe Clock Monitor (FSCM) .................................................................................................................... 7-32 Programmable Oscillator Postscaler .............................................................................................................. 7-33 Clock Switching Operation ............................................................................................................................. 7-34 Design Tips .................................................................................................................................................... 7-38 Related Application Notes ..............................................................................................................................7-39 Revision History ............................................................................................................................................. 7-40 Table of Contents © 2006 Microchip Technology Inc. 70046E-page v PAGE M SECTION 8. RESET 8-1 Introduction ...................................................................................................................................................... 8-2 Clock Source Selection at Reset ...................................................................................................................... 8-5 POR: Power-on Reset ...................................................................................................................................... 8-5 External Reset (EXTR) .....................................................................................................................................8-7 Software RESET Instruction (SWR) ................................................................................................................. 8-7 Watchdog Time-out Reset (WDTR) ................................................................................................................. 8-7 Brown-out Reset (BOR) ................................................................................................................................... 8-8 Using the RCON Status Bits .......................................................................................................................... 8-10 Device Reset Times ....................................................................................................................................... 8-11 Device Start-up Time Lines ............................................................................................................................ 8-13 Special Function Register Reset States ......................................................................................................... 8-16 Design Tips .................................................................................................................................................... 8-17 Related Application Notes ..............................................................................................................................8-18 Revision History ............................................................................................................................................. 8-19 SECTION 9. LOW VOLTAGE DETECT (LVD) 9-1 Introduction ...................................................................................................................................................... 9-2 LVD Operation ................................................................................................................................................. 9-5 Design Tips ...................................................................................................................................................... 9-6 Related Application Notes ................................................................................................................................9-7 Revision History ............................................................................................................................................... 9-8 SECTION 10. WATCHDOG TIMER AND POWER SAVING MODES 10-1 Introduction .................................................................................................................................................... 10-2 Power Saving Modes ..................................................................................................................................... 10-2 Sleep Mode .................................................................................................................................................... 10-2 Idle Mode ....................................................................................................................................................... 10-4 Interrupts Coincident with Power Save Instructions .......................................................................................10-5 Watchdog Timer ............................................................................................................................................. 10-6 Peripheral Module Disable (PMD) Registers ..................................................................................................10-9 Design Tips .................................................................................................................................................. 10-10 Related Application Notes ............................................................................................................................ 10-11 Revision History ........................................................................................................................................... 10-12 SECTION 11. I/O PORTS 11-1 Introduction .................................................................................................................................................... 11-2 I/O Port Control Registers ..............................................................................................................................11-3 Peripheral Multiplexing ...................................................................................................................................11-4 Port Descriptions ............................................................................................................................................ 11-6 Change Notification (CN) Pins ....................................................................................................................... 11-7 CN Operation in Sleep and Idle Modes .......................................................................................................... 11-8 Related Application Notes ............................................................................................................................ 11-11 Revision History ........................................................................................................................................... 11-12 Table of Contents 70046E-page vi © 2006 Microchip Technology Inc. PAGE M SECTION 12. TIMERS 12-1 Introduction .................................................................................................................................................... 12-2 Timer Variants ................................................................................................................................................ 12-3 Control Registers ........................................................................................................................................... 12-6 Modes of Operation ........................................................................................................................................12-9 Timer Prescalers .......................................................................................................................................... 12-14 Timer Interrupts ............................................................................................................................................ 12-14 Reading and Writing 16-bit Timer Module Registers .................................................................................... 12-15 Low Power 32 kHz Crystal Oscillator Input .................................................................................................. 12-15 32-bit Timer Configuration ............................................................................................................................ 12-16 32-bit Timer Modes of Operation ................................................................................................................. 12-18 Reading and Writing into 32-bit Timers ........................................................................................................ 12-21 Timer Operation in Power Saving States ..................................................................................................... 12-21 Peripherals Using Timer Modules ................................................................................................................ 12-22 Design Tips .................................................................................................................................................. 12-24 Related Application Notes ............................................................................................................................ 12-25 Revision History ........................................................................................................................................... 12-26 SECTION 13. INPUT CAPTURE 13-1 Introduction .................................................................................................................................................... 13-2 Input Capture Registers ................................................................................................................................. 13-3 Timer Selection ..............................................................................................................................................13-4 Input Capture Event Modes ........................................................................................................................... 13-4 Capture Buffer Operation ............................................................................................................................... 13-8 Input Capture Interrupts ................................................................................................................................. 13-9 UART Autobaud Support ............................................................................................................................... 13-9 Input Capture Operation in Power Saving States ........................................................................................ 13-10 I/O Pin Control .............................................................................................................................................. 13-10 Special Function Registers Associated with the Input Capture Module ....................................................... 13-11 Design Tips .................................................................................................................................................. 13-12 Related Application Notes ............................................................................................................................ 13-13 Revision History ........................................................................................................................................... 13-14 SECTION 14. OUTPUT COMPARE 14-1 Introduction .................................................................................................................................................... 14-2 Output Compare Registers ............................................................................................................................ 14-3 Modes of Operation ........................................................................................................................................14-4 Output Compare Operation in Power Saving States .................................................................................... 14-23 I/O Pin Control .............................................................................................................................................. 14-23 Design Tips .................................................................................................................................................. 14-26 Related Application Notes ............................................................................................................................ 14-27 Revision History ........................................................................................................................................... 14-28 Table of Contents © 2006 Microchip Technology Inc. 70046E-page vii PAGE M SECTION 15. MOTOR CONTROL PWM 15-1 Introduction .................................................................................................................................................... 15-2 Control Registers ........................................................................................................................................... 15-4 PWM Time Base .......................................................................................................................................... 15-16 PWM Duty Cycle Comparison Units ............................................................................................................. 15-20 Complementary PWM Output Mode ............................................................................................................ 15-26 Dead Time Control ....................................................................................................................................... 15-27 Independent PWM Output Mode .................................................................................................................. 15-30 PWM Output Override .................................................................................................................................. 15-31 PWM Output and Polarity Control ................................................................................................................ 15-34 PWM Fault Pins ........................................................................................................................................... 15-34 PWM Update Lockout .................................................................................................................................. 15-37 PWM Special Event Trigger ......................................................................................................................... 15-38 Operation in Device Power Saving Modes ................................................................................................... 15-38 Special Features for Device Emulation ........................................................................................................ 15-39 Related Application Notes ............................................................................................................................ 15-42 Revision History ........................................................................................................................................... 15-43 SECTION 16. QUADRATURE ENCODER INTERFACE (QEI) 16-1 Module Introduction ........................................................................................................................................16-2 Control and Status Registers ......................................................................................................................... 16-4 Programmable Digital Noise Filters ................................................................................................................ 16-9 Quadrature Decoder .................................................................................................................................... 16-10 16-bit Up/Down Position Counter ................................................................................................................. 16-12 Using QEI as an Alternate 16-bit Timer/Counter .......................................................................................... 16-16 Quadrature Encoder Interface Interrupts ..................................................................................................... 16-17 I/O Pin Control .............................................................................................................................................. 16-18 QEI Operation During Power Saving Modes ................................................................................................ 16-19 Effects of a Reset ......................................................................................................................................... 16-19 Design Tips .................................................................................................................................................. 16-21 Related Application Notes ............................................................................................................................ 16-22 Revision History ........................................................................................................................................... 16-23 Table of Contents 70046E-page viii © 2006 Microchip Technology Inc. PAGE M SECTION 17. 10-BIT A/D CONVERTER 17-1 Introduction .................................................................................................................................................... 17-2 Control Registers ........................................................................................................................................... 17-4 A/D Result Buffer ........................................................................................................................................... 17-4 A/D Terminology and Conversion Sequence ............................................................................................... 17-11 A/D Module Configuration ............................................................................................................................ 17-13 Selecting the Voltage Reference Source ..................................................................................................... 17-13 Selecting the A/D Conversion Clock ............................................................................................................ 17-13 Selecting Analog Inputs for Sampling .......................................................................................................... 17-14 Enabling the Module .................................................................................................................................... 17-16 Specifying the Sample/Conversion Sequence ............................................................................................. 17-16 How to Start Sampling ................................................................................................................................. 17-17 How to Stop Sampling and Start Conversions ............................................................................................. 17-18 Controlling Sample/Conversion Operation ................................................................................................... 17-29 Specifying How Conversion Results are Written Into the Buffer .................................................................. 17-30 Conversion Sequence Examples ................................................................................................................. 17-31 A/D Sampling Requirements ........................................................................................................................ 17-45 Reading the A/D Result Buffer ..................................................................................................................... 17-46 Transfer Function ......................................................................................................................................... 17-47 A/D Accuracy/Error ...................................................................................................................................... 17-47 Connection Considerations .......................................................................................................................... 17-47 Initialization .................................................................................................................................................. 17-48 A/D Conversion Speeds ............................................................................................................................... 17-49 Operation During Sleep and Idle Modes ...................................................................................................... 17-55 Effects of a Reset ......................................................................................................................................... 17-55 Special Function Registers Associated with the 10-bit A/D Converter ......................................................... 17-56 Design Tips .................................................................................................................................................. 17-57 Related Application Notes ............................................................................................................................ 17-58 Revision History ........................................................................................................................................... 17-59 Table of Contents © 2006 Microchip Technology Inc. 70046E-page ix PAGE M SECTION 18. 12-BIT A/D CONVERTER 18-1 Introduction .................................................................................................................................................... 18-2 Control Registers ........................................................................................................................................... 18-4 A/D Result Buffer ........................................................................................................................................... 18-4 A/D Terminology and Conversion Sequence ............................................................................................... 18-10 A/D Module Configuration ............................................................................................................................ 18-11 Selecting the Voltage Reference Source ..................................................................................................... 18-11 Selecting the A/D Conversion Clock ............................................................................................................ 18-12 Selecting Analog Inputs for Sampling .......................................................................................................... 18-12 Enabling the Module .................................................................................................................................... 18-14 How to Start Sampling ................................................................................................................................. 18-14 How to Stop Sampling and Start Conversions ............................................................................................. 18-14 Controlling Sample/Conversion Operation ................................................................................................... 18-19 Specifying How Conversion Results are Written into the Buffer .................................................................. 18-19 Conversion Sequence Examples ................................................................................................................. 18-21 A/D Sampling Requirements ........................................................................................................................ 18-26 Reading the A/D Result Buffer ..................................................................................................................... 18-27 Transfer Function ......................................................................................................................................... 18-28 A/D Accuracy/Error ...................................................................................................................................... 18-28 Connection Considerations .......................................................................................................................... 18-28 Initialization .................................................................................................................................................. 18-29 A/D Conversion Speeds ............................................................................................................................... 18-30 Operation During Sleep and Idle Modes ...................................................................................................... 18-33 Effects of a Reset ......................................................................................................................................... 18-33 Special Function Registers Associated with the 12-bit A/D Converter ......................................................... 18-34 Design Tips .................................................................................................................................................. 18-35 Related Application Notes ............................................................................................................................ 18-36 Revision History ........................................................................................................................................... 18-37 SECTION 19. UART 19-1 Introduction .................................................................................................................................................... 19-2 Control Registers ........................................................................................................................................... 19-3 UART Baud Rate Generator (BRG) ............................................................................................................... 19-8 UART Configuration ..................................................................................................................................... 19-10 UART Transmitter ........................................................................................................................................ 19-11 UART Receiver ............................................................................................................................................ 19-14 Using the UART for 9-bit Communication .................................................................................................... 19-18 Receiving Break Characters ........................................................................................................................ 19-19 Initialization .................................................................................................................................................. 19-20 Other Features of the UART ........................................................................................................................ 19-21 UART Operation During CPU Sleep and Idle Modes ................................................................................... 19-21 Registers Associated with UART Module ..................................................................................................... 19-22 Design Tips .................................................................................................................................................. 19-23 Related Application Notes ............................................................................................................................ 19-24 Revision History ........................................................................................................................................... 19-25 Table of Contents 70046E-page x © 2006 Microchip Technology Inc. PAGE M SECTION 20. SERIAL PERIPHERAL INTERFACE (SPI™) 20-1 Introduction .................................................................................................................................................... 20-2 Status and Control Registers ......................................................................................................................... 20-4 Modes of Operation ........................................................................................................................................20-7 SPI Master Mode Clock Frequency .............................................................................................................. 20-19 Operation in Power Save Modes ................................................................................................................. 20-20 Special Function Registers Associated with SPI Modules ........................................................................... 20-22 Related Application Notes ............................................................................................................................ 20-23 Revision History ........................................................................................................................................... 20-24 SECTION 21. INTER-INTEGRATED CIRCUIT™ (I2C™) 21-1 Overview ........................................................................................................................................................ 21-2 I 2C Bus Characteristics .................................................................................................................................. 21-4 Control and Status Registers ......................................................................................................................... 21-7 Enabling I2C Operation ................................................................................................................................ 21-13 Communicating as a Master in a Single Master Environment ...................................................................... 21-15 Communicating as a Master in a Multi-Master Environment ........................................................................ 21-29 Communicating as a Slave .......................................................................................................................... 21-32 Connection Considerations for I2C Bus ....................................................................................................... 21-47 Module Operation During PWRSAV Instruction ........................................................................................... 21-49 Effects of a Reset ......................................................................................................................................... 21-49 Design Tips .................................................................................................................................................. 21-50 Related Application Notes ............................................................................................................................ 21-51 Revision History ........................................................................................................................................... 21-52 SECTION 22. DATA CONVERTER INTERFACE (DCI) 22-1 Introduction .................................................................................................................................................... 22-2 Control Register Descriptions ......................................................................................................................... 22-2 Codec Interface Basics and Terminology ....................................................................................................... 22-8 DCI Operation .............................................................................................................................................. 22-10 Using the DCI Module .................................................................................................................................. 22-17 Operation in Power Saving Modes ............................................................................................................... 22-28 Registers Associated with DCI ..................................................................................................................... 22-28 Design Tips .................................................................................................................................................. 22-30 Related Application Notes ............................................................................................................................ 22-31 Revision History ........................................................................................................................................... 22-32 Table of Contents © 2006 Microchip Technology Inc. 70046E-page xi PAGE M SECTION 23. CAN MODULE 23-1 Introduction .................................................................................................................................................... 23-2 Control Registers for the CAN Module ........................................................................................................... 23-2 CAN Module Features .................................................................................................................................. 23-28 CAN Module Implementation ....................................................................................................................... 23-29 CAN Module Operation Modes .................................................................................................................... 23-36 Message Reception ..................................................................................................................................... 23-39 Transmission ................................................................................................................................................ 23-49 Error Detection ............................................................................................................................................. 23-58 CAN Baud Rate ............................................................................................................................................ 23-60 Interrupts ...................................................................................................................................................... 23-64 CAN Capture ................................................................................................................................................ 23-65 CAN Module I/O ........................................................................................................................................... 23-65 Operation in CPU Power Saving Modes ...................................................................................................... 23-66 CAN Protocol Overview ............................................................................................................................... 23-68 Related Application Notes ............................................................................................................................ 23-72 Revision History ........................................................................................................................................... 23-73 SECTION 24. DEVICE CONFIGURATION 24-1 Introduction .................................................................................................................................................... 24-2 Device Configuration Registers ...................................................................................................................... 24-2 Configuration Bit Descriptions ........................................................................................................................ 24-6 Device Identification Registers ....................................................................................................................... 24-7 Related Application Notes ..............................................................................................................................24-8 Revision History ............................................................................................................................................. 24-9 SECTION 25. DEVELOPMENT TOOL SUPPORT 25-1 Introduction .................................................................................................................................................... 25-2 Microchip Hardware and Language Tools ...................................................................................................... 25-2 Third Party Hardware/Software Tools and Application Libraries ................................................................... 25-6 dsPIC30F Hardware Development Boards .................................................................................................. 25-11 Related Application Notes ............................................................................................................................ 25-15 Revision History ........................................................................................................................................... 25-16 SECTION 26. APPENDIX 26-1 Table of Contents 70046E-page xii © 2006 Microchip Technology Inc. PAGE M NOTES: Table of Contents © 2004 Microchip Technology Inc. DS70048C-page 1-1 Introduction 1 Section 1. Introduction HIGHLIGHTS This section of the manual contains the following topics: 1.1 Introduction .................................................................................................................... 1-2 1.2 Manual Objective ........................................................................................................... 1-2 1.3 Device Structure............................................................................................................. 1-3 1.4 Development Support ....................................................................................................1-4 1.5 Style and Symbol Conventions ...................................................................................... 1-4 1.6 Related Documents ....................................................................................................... 1-6 1.7 Revision History ............................................................................................................. 1-7 dsPIC30F Family Reference Manual DS70048C-page 1-2 © 2004 Microchip Technology Inc. 1.1 Introduction Microchip is a leading provider of microcontrollers and analog semiconductors. The company’s focus is on products that meet the needs of the embedded control market. We are a leading supplier of: • 8-bit general purpose microcontrollers (PICmicro® MCUs) • dsPIC30F 16-bit microcontrollers • Speciality and standard non-volatile memory devices • Security devices (KEELOQ®) • Application specific standard products Please request a Microchip Product Line Card for a listing of all the interesting products that we have to offer. This literature can be obtained from your local sales office, or downloaded from the Microchip web site (www.microchip.com). 1.2 Manual Objective PICmicro and dsPIC30F devices are grouped by the size of their Instruction Word and Data Path. The current device families are: 1. Base-Line: 12-bit Instruction Word length, 8-bit Data Path 2. Mid-Range: 14-bit Instruction Word length, 8-bit Data Path 3. High-End: 16-bit Instruction Word length, 8-bit Data Path 4. Enhanced: 16-bit Instruction Word length, 8-bit Data Path 5. dsPIC30F: 24-bit Instruction Word length, 16-bit Data Path This manual describes the dsPIC30F 16-bit MCU family of devices. This manual explains the operation of the dsPIC30F MCU family architecture and peripheral modules, but does not cover the specifics of each device. The user should refer to the data sheet for device specific information. The information that can be found in the data sheet includes: • Device memory map • Device pinout and packaging details • Device electrical specifications • List of peripherals included on the device Code examples are given throughout this manual. These examples sometimes need to be written as device specific as opposed to family generic, though they are valid for most other devices. Some modifications may be required for devices with variations in register file mappings. © 2004 Microchip Technology Inc. DS70048C-page 1-3 Section 1. Introduction Introduction 1 1.3 Device Structure Each part of the dsPIC30F device can be placed into one of three groups: 1. CPU Core 2. System Integration 3. Peripherals 1.3.1 CPU Core The CPU core pertains to the basic features that are required to make the device operate. The sections of the manual related to the CPU core include: 1. CPU 2. Data Memory 3. Program Memory 4. DSP Engine 5. Interrupts 1.3.2 System Integration System integration functions help to: • Decrease system cost • Increase system reliability • Increase design flexibility The following sections of the manual discuss dsPIC30F system integration functions: 1. Oscillator 2. Reset 3. Low Voltage Detect 4. Watchdog Timer and Power Saving Modes 5. Flash and EEPROM Programming 6. Device Configuration 1.3.3 Peripherals The dsPIC30F has many peripherals that allow the device to be interfaced to the external world. The peripherals discussed in this manual include: 1. I/O Ports 2. Timers 3. Input Capture Module 4. Output Compare Module 5. Quadrature Encoder Interface (QEI) 6. 10-bit A/D Converter 7. 12-bit A/D Converter 8. UART Module 9. SPITM Module 10. I2CTM Module 11. Data Converter Interface (DCI) Module 12. CAN Module 1.3.4 Memory Technology At the time of this writing, all dsPIC30F devices use Flash program memory technology. The Flash program memory can be electrically erased or programmed. dsPIC30F Family Reference Manual DS70048C-page 1-4 © 2004 Microchip Technology Inc. 1.4 Development Support Microchip offers a wide range of development tools that allow users to efficiently develop and debug application code. Microchip’s development tools can be broken down into four categories: 1. Code generation 2. Hardware/Software debug 3. Device programmer 4. Product evaluation boards A full description of each of Microchip’s development tools is discussed in Section 25. “Development Tool Support”. As new tools are developed, the latest product briefs and user guides can be obtained from the Microchip web site (www.microchip.com) or from your local Microchip Sales Office. Microchip offers other reference tools to speed the development cycle. These include: • Application Notes • Reference Designs • Microchip web site • Local Sales Offices with Field Application Support • Corporate Support Line The Microchip web site lists other sites that may be useful references. 1.5 Style and Symbol Conventions Throughout this document, certain style and font format conventions are used. Most format conventions imply a distinction should be made for the emphasized text. The MCU industry has many symbols and non-conventional word definitions/abbreviations. Table 1-1 provides a description for many of the conventions contained in this document. Located at the rear of this document, a glossary provides additional word and abbreviation definitions used throughout this manual. © 2004 Microchip Technology Inc. DS70048C-page 1-5 Section 1. Introduction Introduction 1 1.5.1 Document Conventions Table 1-1 defines some of the symbols and terms used throughout this manual. Table 1-1: Document Conventions Symbol or Term Description set To force a bit/register to a value of logic ‘1’. clear To force a bit/register to a value of logic ‘0’. Reset 1) To force a register/bit to its default state. 2) A condition in which the device places itself after a device Reset occurs. Some bits will be forced to ‘0’ (such as interrupt enable bits), while others will be forced to ‘1’ (such as the I/O data direction bits). 0xnn or nnh Designates the number ‘nn’ in the hexadecimal number system. These conventions are used in the code examples. For example, 0x13F or 13Fh. B‘bbbbbbbb’ Designates the number ‘bbbbbbbb’ in the binary number system. This convention is used in the text and in figures and tables. For example, B‘10100000’. R-M-W Read-Modify-Write. This is when a register or port is read, then the value is modified, and that value is then written back to the register or port. This action can occur from a single instruction (such as bit set, BSET), or a sequence of instructions. : (colon) Used to specify a range or the concatenation of registers/bits/pins. One example is TMR3:TMR2, which is the concatenation of two 16-bit registers to form a 32-bit timer value. Concatenation order (left-right) usually specifies a positional relationship (MSb to LSb, higher to lower). < > Specifies bit(s) locations in a particular register. One example is PTCON (or PTMOD<1:0>), which specifies the register and associated bits or bit positions. MSb, MSbit, LSb, LSbit Indicates the Least Significant or Most Significant bit in a field. MSByte, MSWord, LSByte, LSWord Indicates the Least/Most Significant Byte or Word in a field of bits. Courier Font Used for code examples, binary numbers and for instruction mnemonics in the text. Times Font Used for equations and variables. Times, Bold Font, Italics Used in explanatory text for items called out from a graphic/ equation/example. Note A Note presents information that we wish to re-emphasize, either to help you avoid a common pitfall, or make you aware of operating differences between some device family members. A Note is always in a shaded box (as below), unless used in a table, where it is at the bottom of the table (as in this table). Note: This is a Note in a shaded note box. dsPIC30F Family Reference Manual DS70048C-page 1-6 © 2004 Microchip Technology Inc. 1.5.2 Electrical Specifications Throughout this manual, there will be references to electrical specifications and their parameter numbers. Table 1-2 shows the parameter numbering convention for dsPIC30F devices. A parameter number represents a unique set of characteristics and conditions that is consistent between every data sheet, though the actual parameter value may vary from device to device. This manual describes a family of devices and therefore, does not specify the parameter values. The user should refer to the “Electrical Specifications” section of the device data sheet for the actual parameter values for that device. Table 1-2: Electrical Specification Parameter Numbering Convention 1.6 Related Documents Microchip, as well as other sources, offers additional documentation which can aid in your development with dsPIC30F MCUs. These lists contain the most common documentation, but other documents may also be available. Please check the Microchip web site (www.microchip.com) for the latest published technical documentation. 1.6.1 Microchip Documentation The following dsPIC30F documentation is available from Microchip at the time of this writing. Many of these documents provide application specific information that gives actual examples of using, programming and designing with dsPIC30F MCUs. 1. dsPIC30F Programmer’s Reference Manual (DS70030) The dsPIC30F Programmer’s Reference Manual provides information about the dsPIC30F programmer’s model and instruction set. A description of each instruction and syntax examples are provided in this document. 2. dsPIC30F Family Overview (DS70043) This document provides a summary of the available dsPIC30F family variants, including device pinouts, memory sizes and available peripherals. 3. dsPIC30F Data Sheets (DS70082 and DS70083) The data sheets contain device specific information, such as pinout and packaging details, electrical specifications and memory maps. 1.6.2 Third Party Documentation There are several documents available from third party sources around the world. Microchip does not review these documents for technical accuracy. However, they may be a helpful source for understanding the operation of Microchip dsPIC30F devices. Please refer to the Microchip web site for third party documentation related to the dsPIC30F. Parameter Number Format Comment DXXX DC Specification AXXX DC Specification for Analog Peripherals XXX Timing (AC) Specification PDXXX Device Programming DC Specification PXXX Device Programming Timing (AC) Specification Legend: XXX represents a number. © 2004 Microchip Technology Inc. DS70048C-page 1-7 Section 1. Introduction Introduction 1 1.7 Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual. Revision C There were no technical content revisions to this section of the manual, however, this section was updated to reflect Revision C throughout the manual. dsPIC30F Family Reference Manual DS70048C-page 1-8 © 2004 Microchip Technology Inc. NOTES: © 2004 Microchip Technology Inc. DS70049C-page 2-1 CPU 2 Section 2. CPU HIGHLIGHTS This section of the manual contains the following topics: 2.1 Introduction .................................................................................................................... 2-2 2.2 Programmer’s Model...................................................................................................... 2-4 2.3 Software Stack Pointer................................................................................................... 2-8 2.4 CPU Register Descriptions .......................................................................................... 2-11 2.5 Arithmetic Logic Unit (ALU).......................................................................................... 2-17 2.6 DSP Engine ................................................................................................................. 2-18 2.7 Divide Support .............................................................................................................2-27 2.8 Instruction Flow Types ................................................................................................. 2-27 2.9 Loop Constructs........................................................................................................... 2-30 2.10 Address Register Dependencies .................................................................................2-35 2.11 Register Maps.............................................................................................................. 2-38 2.12 Related Application Notes............................................................................................2-40 2.13 Revision History ...........................................................................................................2-41 dsPIC30F Family Reference Manual DS70049C-page 2-2 © 2004 Microchip Technology Inc. 2.1 Introduction The dsPIC30F CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word, with a variable length opcode field. The program counter (PC) is 24-bits wide and addresses up to 4M x 24 bits of user program memory space. A single cycle instruction pre-fetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The dsPIC30F devices have sixteen 16-bit working registers in the programmer’s model. Each of the working registers can act as a data, address, or address offset register. The 16th working register (W15) operates as a software stack pointer for interrupts and calls. The dsPIC30F instruction set has two classes of instructions: the MCU class of instructions and the DSP class of instructions. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. The instruction set includes many Addressing modes and was designed for optimum C compiler efficiency. The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operate solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device specific. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. Furthermore, RAM may be connected to the program memory bus on devices with an external bus and used to extend the internal data RAM. Overhead free circular buffers (modulo addressing) are supported in both X and Y address spaces. The modulo addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports bit-reverse addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. The CPU supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct and Register Indirect Addressing modes. Each instruction is associated with a predefined Addressing mode group depending upon its functional requirements. As many as 6 Addressing modes are supported for each instruction. For most instructions, the dsPIC30F is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3 operand instructions can be supported, allowing A+B=C operations to be executed in a single cycle. The DSP engine features a high speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bi-directional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 15 bits right, or up to 16 bits left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers. This requires that the data space be split for these instructions and linear for all others. This is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. The dsPIC30F has a vectored exception scheme with up to 8 sources of non-maskable traps and 54 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1. © 2004 Microchip Technology Inc. DS70049C-page 2-3 Section 2. CPU CPU 2 Figure 2-1: dsPIC30F CPU Core Block Diagram Power-up Timer Oscillator Start-up Timer POR/BOR Reset Watchdog Timer Instruction Decode & Control OSC1/CLKI MCLR VDD, VSS Low Voltage Detect UART1, CAN2 Timing Generation CAN1, 16 PCH PCL 16 Program Counter 16-bit ALU 24 24 24 24 X Data Bus IR I 2C™ DCI PCU 10-bit or Timers Input Capture Module Output Compare Module 16 16 16 16 x 16 W Reg Array Divide Support Engine DSP ROM Latch 16 Y Data Bus EA MUX X RAGU X WAGU Y AGU AVDD, AVSS SPI2 UART2 16 16 16 16 16 16 16 16 16 8 Interrupt Controller PSV & Table Data Access Control Block Stack Control Logic Loop Control Logic Data Latch Data Latch Y Data (4 Kbytes) RAM X Data (4 Kbytes) RAM Address Latch Address Latch Control Signals to Various Blocks 16 SPI1, Address Latch Program Memory (144 Kbytes) Data Latch Data EEPROM (4 Kbytes) I/O Ports 16 16 16 X Address Bus Y Address Bus 16 Literal Data 12-bit ADC dsPIC30F Family Reference Manual DS70049C-page 2-4 © 2004 Microchip Technology Inc. 2.2 Programmer’s Model The programmer’s model for the dsPIC30F is shown in Figure 2-2. All registers in the programmer’s model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. In addition to the registers contained in the programmer’s model, the dsPIC30F contains control registers for modulo addressing, bit-reversed addressing and interrupts. These registers are described in subsequent sections of this document. All registers associated with the programmer’s model are memory mapped, as shown in Table 2-8 on page 2-38. Table 2-1: Programmer’s Model Register Descriptions Register(s) Name Description W0 through W15 Working register array ACCA, ACCB 40-bit DSP Accumulators PC 23-bit Program Counter SR ALU and DSP Engine Status register SPLIM Stack Pointer Limit Value register TBLPAG Table Memory Page Address register PSVPAG Program Space Visibility Page Address register RCOUNT REPEAT Loop Count register DCOUNT DO Loop Count register DOSTART DO Loop Start Address register DOEND DO Loop End Address register CORCON Contains DSP Engine and DO Loop control bits © 2004 Microchip Technology Inc. DS70049C-page 2-5 Section 2. CPU CPU 2 Figure 2-2: Programmer’s Model N OV SZ C TBLPAG 22 0 7 0 15 0 Program Counter Data Table Page Address Status Register Working/Address Registers DSP Operand Registers W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 Frame Pointer/W14 Stack Ptr/W15 DSP Address Registers 39 31 0 DSP Accumulators PSVPAG 7 0 Program Space Visibility RA 0 OA OB SA SB RCOUNT 15 0 REPEAT Loop Counter DCOUNT 15 0 DO Loop Counter DOSTART 22 0 DO Loop Start Address DOEND DO Loop End Address IPL<2:0> SPLIM Stack Pointer Limit 15 22 0 SRL PUSH.S and POP.S Shadows 0 0 OAB SAB Page Address DA DC CORCON 15 0 Core Control Register ACCAU ACCAH ACCAL ACCBU ACCBH ACCBL ACCA ACCB SRH 0 0 Note: DCOUNT, DOSTART and DOEND have one level of shadow registers (not shown) for nested DO loops. dsPIC30F Family Reference Manual DS70049C-page 2-6 © 2004 Microchip Technology Inc. 2.2.1 Working Register Array The 16 working (W) registers can function as data, address or address offset registers. The function of a W register is determined by the Addressing mode of the instruction that accesses it. The dsPIC30F instruction set can be divided into two instruction types: register and file register instructions. Register instructions can use each W register as a data value or an address offset value. For example: MOV W0,W1 ; move contents of W0 to W1 MOV W0,[W1] ; move W0 to address contained in W1 ADD W0,[W4],W5 ; add contents of W0 to contents pointed ; to by W4. Place result in W5. 2.2.1.1 W0 and File Register Instructions W0 is a special working register because it is the only working register that can be used in file register instructions. File register instructions operate on a specific memory address contained in the instruction opcode and W0. W1-W15 cannot be specified as a target register in file register instructions. The file register instructions provide backward compatibility with existing PICmicro® devices which have only one W register. The label ‘WREG’ is used in the assembler syntax to denote W0 in a file register instruction. For example: MOV WREG,0x0100 ; move contents of W0 to address 0x0100 ADD 0x0100,WREG ; add W0 to address 0x0100, store in W0 2.2.1.2 W Register Memory Mapping Since the W registers are memory mapped, it is possible to access a W register in a file register instruction as shown below: MOV 0x0004, W10 ; equivalent to MOV W2, W10 where 0x0004 is the address in memory of W2. Further, it is also possible to execute an instruction that will attempt to use a W register as both an address pointer and operand destination. For example: MOV W1,[W2++] where: W1 = 0x1234 W2 = 0x0004 ;[W2] addresses W2 In the example above, the contents of W2 are 0x0004. Since W2 is used as an address pointer, it points to location 0x0004 in memory. W2 is also mapped to this address in memory. Even though this is an unlikely event, it is impossible to detect until run-time. The dsPIC30F ensures that the data write will dominate, resulting in W2 = 0x1234 in the example above. 2.2.1.3 W Registers and Byte Mode Instructions Byte instructions which target the W register array only affect the Least Significant Byte of the target register. Since the working registers are memory mapped, the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses. 2.2.2 Shadow Registers Many of the registers in the programmer’s model have an associated shadow register as shown in Figure 2-2. None of the shadow registers are accessible directly. There are two types of shadow registers: those utilized by the PUSH.S and POP.S instructions and those utilized by the DO instruction. Note: For a complete description of Addressing modes and instruction syntax, please refer to the dsPIC30F Programmer’s Reference Manual (DS70032). © 2004 Microchip Technology Inc. DS70049C-page 2-7 Section 2. CPU CPU 2 2.2.2.1 PUSH.S and POP.S Shadow Registers The PUSH.S and POP.S instructions are useful for fast context save/restore during a function call or Interrupt Service Routine (ISR). The PUSH.S instruction will transfer the following register values into their respective shadow registers: • W0...W3 • SR (N, OV, Z , C, DC bits only) The POP.S instruction will restore the values from the shadow registers into these register locations. A code example using the PUSH.S and POP.S instructions is shown below: MyFunction: PUSH.S ; Save W registers, MCU status MOV #0x03,W0 ; load a literal value into W0 ADD RAM100 ; add W0 to contents of RAM100 BTSC SR,#Z ; is the result 0? BSET Flags,#IsZero ; Yes, set a flag POP.S ; Restore W regs, MCU status RETURN The PUSH.S instruction will overwrite the contents previously saved in the shadow registers. The shadow registers are only one level in depth, so care must be taken if the shadow registers are to be used for multiple software tasks. The user must ensure that any task using the shadow registers will not be interrupted by a higher priority task that also uses the shadow registers. If the higher priority task is allowed to interrupt the lower priority task, the contents of the shadow registers saved in the lower priority task will be overwritten by the higher priority task. 2.2.2.2 DO Loop Shadow Registers The following registers are automatically saved in shadow registers when a DO instruction is executed: • DOSTART • DOEND • DCOUNT The DO shadow registers are one level in depth, permitting two loops to be automatically nested. Refer to Section 2.9.2.2 “DO Loop Nesting” for further details. 2.2.3 Uninitialized W Register Reset The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. An attempt to use an uninitialized register as an address pointer will reset the device. A word write must be performed to initialize a W register. A byte write will not affect the initialization detection logic. dsPIC30F Family Reference Manual DS70049C-page 2-8 © 2004 Microchip Technology Inc. 2.3 Software Stack Pointer W15 serves as a dedicated software stack pointer and is automatically modified by exception processing, subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies reading, writing and manipulating the stack pointer (e.g., creating stack frames). W15 is initialized to 0x0800 during all Resets. This address ensures that the stack pointer (SP) will point to valid RAM in all dsPIC30F devices and permits stack availability for non-maskable trap exceptions, which may occur before the SP is initialized by the user software. The user may reprogram the SP during initialization to any location within data space. The stack pointer always points to the first available free word and fills the software stack working from lower towards higher addresses. It pre-decrements for a stack pop (read) and post-increments for a stack push (writes), as shown in Figure 2-3. When the PC is pushed onto the stack, PC<15:0> is pushed onto the first available stack word, then PC<22:16> is pushed into the second available stack location. For a PC push during any CALL instruction, the MSByte of the PC is zero-extended before the push as shown in Figure 2-3. During exception processing, the MSByte of the PC is concatenated with the lower 8 bits of the CPU status register, SR. This allows the contents of SRL to be preserved automatically during interrupt processing. Figure 2-3: Stack Operation for a CALL Instruction Note: In order to protect against misaligned stack accesses, W15<0> is fixed to ‘0’ by the hardware. PC<15:0> PC<22:16> 15 0 W15 (before CALL) W15 (after CALL) Stack Grows Towards Higher Address B‘000000000’ CALL SUBR © 2004 Microchip Technology Inc. DS70049C-page 2-9 Section 2. CPU CPU 2 2.3.1 Software Stack Examples The software stack is manipulated using the PUSH and POP instructions. The PUSH and POP instructions are the equivalent of a MOV instruction with W15 used as the destination pointer. For example, the contents of W0 can be pushed onto the stack by: PUSH W0 This syntax is equivalent to: MOV W0,[W15++] The contents of the top-of-stack can be returned to W0 by: POP W0 This syntax is equivalent to: MOV [--W15],W0 Figure 2-4 through Figure 2-7 show examples of how the software stack is used. Figure 2-4 shows the software stack at device initialization. W15 has been initialized to 0x0800. Furthermore, this example assumes the values 0x5A5A and 0x3636 have been written to W0 and W1, respectively. The stack is pushed for the first time in Figure 2-5 and the value contained in W0 is copied to the stack. W15 is automatically updated to point to the next available stack location (0x0802). In Figure 2-6, the contents of W1 are pushed onto the stack. In Figure 2-7, the stack is popped and the top-of-stack value (previously pushed from W1) is written to W3. Figure 2-4: Stack Pointer at Device Reset Figure 2-5: Stack Pointer After the First PUSH Instruction Figure 2-6: Stack Pointer After the Second PUSH Instruction 0x0000 0xFFFE W15 0x0800 W15 = 0x0800 W0 = 0x5A5A W1 = 0x3636 0x0000 0xFFFE 0x5A5A W15 = 0x0802 W0 = 0x5A5A W1 = 0x3636 0x0800 PUSH W0 W15 0x0802 0x0000 0xFFFE 0x5A5A 0x3636 W15 = 0x0804 W0 = 0x5A5A W1 = 0x3636 0x0800 PUSH W1 0x0802 W15 0x0804 dsPIC30F Family Reference Manual DS70049C-page 2-10 © 2004 Microchip Technology Inc. Figure 2-7: Stack Pointer After a POP Instruction 2.3.2 W14 Software Stack Frame Pointer A frame is a user defined section of memory in the stack that is used by a single subroutine. W14 is a special working register because it can be used as a stack frame pointer with the LNK (link) and ULNK (unlink) instructions. W14 can be used in a normal working register by instructions when it is not used as a frame pointer. Refer to the “dsPIC30F Programmer’s Reference Manual” (DS70030) for software examples that use W14 as a stack frame pointer. 2.3.3 Stack Pointer Overflow There is a stack limit register (SPLIM) associated with the stack pointer that is reset to 0x0000. SPLIM is a 16-bit register, but SPLIM<0> is fixed to ‘0’ because all stack operations must be word aligned. The stack overflow check will not be enabled until a word write to SPLIM occurs, after which time it can only be disabled by a device Reset. All effective addresses generated using W15 as a source or destination are compared against the value in SPLIM. If the contents of the Stack Pointer (W15) are greater than the contents of the SPLIM register by 2 and a push operation is performed, a Stack Error Trap will not occur. The Stack Error Trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a Stack Error Trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value, 0x1FFE. If stack overflow checking has been enabled, a stack error trap will also occur if the W15 effective address calculation wraps over the end of data space (0xFFFF). Refer to Section 6. “Reset Interrupts” for more information on the stack error trap. 2.3.4 Stack Pointer Underflow The stack is initialized to 0x0800 during Reset. A stack error trap will be initiated should the stack pointer address ever be less than 0x0800. 0x0000 0xFFFE 0x05A5A 0x03636 0x3636 → W3 W15 = 0x0802 POP W3 0x0802 0x0800 W15 Note: A Stack Error Trap may be caused by any instruction that uses the contents of the W15 register to generate an effective address (EA). Thus, if the contents of W15 are greater than the contents of the SPLIM register by 2, and a CALL instruction is executed, or if an interrupt occurs, a Stack Error Trap will be generated. Note: A write to the Stack Pointer Limit register, SPLIM, should not be followed by an indirect read operation using W15. Note: Locations in data space between 0x0000 and 0x07FF are, in general, reserved for core and peripheral special function registers. © 2004 Microchip Technology Inc. DS70049C-page 2-11 Section 2. CPU CPU 2 2.4 CPU Register Descriptions 2.4.1 SR: CPU Status Register The dsPIC30F CPU has a 16-bit status register (SR), the LSByte of which is referred to as the lower status register (SRL). The upper byte of SR is referred to as SRH. A detailed description of SR is shown in Register 2-1. SRL contains all the MCU ALU operation status flags, plus the CPU interrupt priority status bits, IPL<2:0> and the REPEAT loop active status bit, RA (SR<4>). During exception processing, SRL is concatenated with the MSByte of the PC to form a complete word value, which is then stacked. SRH contains the DSP Adder/Subtractor status bits, the DO loop active bit, DA (SR<9>) and the Digit Carry bit, DC (SR<8>). The SR bits are readable/writable with the following exceptions: 1. The DA bit (SR<8>): DA is a read only bit. 2. The RA bit (SR<4>): RA is a read only bit. 3. The OA, OB (SR<15:14>) and OAB (SR<11>) bits: These bits are read only and can only be modified by the DSP engine hardware. 4. The SA, SB (SR<13:12>) and SAB (SR<10>) bits: These are read and clear only and can only be set by the DSP engine hardware. Once set, they remain set until cleared by the user, irrespective of the results from any subsequent DSP operations. 2.4.2 CORCON: Core Control Register The CORCON register contains bits that control the operation of the DSP multiplier and DO loop hardware. The CORCON register also contains the IPL3 status bit, which is concatenated with IPL<2:0> (SR<7:5>), to form the CPU Interrupt Priority Level. Note: Clearing the SAB bit will also clear both the SA and SB bits. Note: A description of the SR bits affected by each instruction is provided in the dsPIC30F Programmer’s Reference Manual (DS70030). dsPIC30F Family Reference Manual DS70049C-page 2-12 © 2004 Microchip Technology Inc. Register 2-1: SR: CPU Status Register Upper Byte: R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 Lower Byte: (SRL) R/W-0(2) R/W-0(2) R/W-0(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0> RA N OV Z C bit 7 bit 0 bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated Note: This bit may be read or cleared (not set). bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated Note: This bit may be read or cleared (not set). bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated Note: This bit may be read or cleared (not set). Clearing this bit will clear SA and SB. bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data) of the result occurred © 2004 Microchip Technology Inc. DS70049C-page 2-13 Section 2. CPU CPU 2 Register 2-1: SR: CPU Status Register (Continued) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1) 111 = CPU Interrupt Priority Level is 7 (15). User interrupts disabled. 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. 2: The IPL<2:0> status bits are read only when NSTDIS = 1 (INTCON1<15>). bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clear only bit S = Set only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70049C-page 2-14 © 2004 Microchip Technology Inc. Register 2-2: CORCON: Core Control Register Upper Byte: U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL<2:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF bit 7 bit 0 bit 15-13 Unimplemented: Read as '0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect Note: This bit will always read as ‘0’. bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active • • 001 = 1 DO loop active 000 = 0 DO loops active bit 7 SATA: AccA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled bit 6 SATB: AccB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Note: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2004 Microchip Technology Inc. DS70049C-page 2-15 Section 2. CPU CPU 2 Register 2-2: CORCON: Core Control Register (Continued) bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Bit can be cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70049C-page 2-16 © 2004 Microchip Technology Inc. 2.4.3 Other dsPIC30F CPU Control Registers The registers listed below are associated with the dsPIC30F CPU core, but are described in further detail in other sections of this manual. 2.4.3.1 TBLPAG: Table Page Register The TBLPAG register is used to hold the upper 8 bits of a program memory address during table read and write operations. Table instructions are used to transfer data between program memory space and data memory space. Refer to Section 4. “Program Memory” for further details. 2.4.3.2 PSVPAG: Program Space Visibility Page Register Program space visibility allows the user to map a 32-Kbyte section of the program memory space into the upper 32 Kbytes of data address space. This feature allows transparent access of constant data through dsPIC30F instructions that operate on data memory. The PSVPAG register selects the 32 Kbyte region of program memory space that is mapped to the data address space. Refer to Section 4. “Program Memory” for more information on the PSVPAG register. 2.4.3.3 MODCON: Modulo Control Register The MODCON register is used to enable and configure modulo addressing (circular buffers). Refer to Section 3. “Data Memory” for further details on modulo addressing. 2.4.3.4 XMODSRT, XMODEND: X Modulo Start and End Address Registers The XMODSRT and XMODEND registers hold the start and end addresses for modulo (circular) buffers implemented in the X data memory address space. Refer to Section 3. “Data Memory” for further details on modulo addressing. 2.4.3.5 YMODSRT, YMODEND: Y Modulo Start and End Address Registers The YMODSRT and YMODEND registers hold the start and end addresses for modulo (circular) buffers implemented in the Y data memory address space. Refer to Section 3. “Data Memory” for further details on modulo addressing. 2.4.3.6 XBREV: X Modulo Bit-Reverse Register The XBREV register is used to set the buffer size used for bit-reversed addressing. Refer to Section 3. “Data Memory” for further details on bit-reversed addressing. 2.4.3.7 DISICNT: Disable Interrupts Count Register The DISICNT register is used by the DISI instruction to disable interrupts of priority 1-6 for a specified number of cycles. See Section 6. “Reset Interrupts” for further information. © 2004 Microchip Technology Inc. DS70049C-page 2-17 Section 2. CPU CPU 2 2.5 Arithmetic Logic Unit (ALU) The dsPIC30F ALU is 16-bits wide and is capable of addition, subtraction, single bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) status bits in the SR register. The C and DC status bits operate as a Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory depending on the Addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the dsPIC30F Programmer’s Reference Manual (DS70030) for information on the SR bits affected by each instruction, Addressing modes and 8-bit/16-bit Instruction modes. 2.5.1 Byte to Word Conversion The dsPIC30F has two instructions that are helpful when mixing 8-bit and 16-bit ALU operations. The sign-extend (SE) instruction takes a byte value in a W register or data memory and creates a sign-extended word value that is stored in a W register. The zero-extend (ZE) instruction clears the 8 MSbs of a word value in a W register or data memory and places the result in a destination W register. Note 1: Byte operations use the 16-bit ALU and can produce results in excess of 8 bits. However, to maintain backward compatibility with PICmicro devices, the ALU result from all byte operations is written back as a byte (i.e., MSByte not modified), and the SR register is updated based only upon the state of the LSByte of the result. 2: All register instructions performed in Byte mode only affect the LSByte of the W registers. The MSByte of any W register can be modified by using file register instructions that access the memory mapped contents of the W registers. dsPIC30F Family Reference Manual DS70049C-page 2-18 © 2004 Microchip Technology Inc. 2.6 DSP Engine The DSP engine is a block of hardware which is fed data from the W register array but contains its own specialized result registers. The DSP engine is driven from the same instruction decoder that directs the MCU ALU. In addition, all operand effective addresses (EAs) are generated in the W register array. Concurrent operation with MCU instruction flow is not possible, though both the MCU ALU and DSP engine resources may be shared by all instructions in the instruction set. The DSP engine consists of the following components: • high speed 17-bit x 17-bit multiplier • barrel shifter • 40-bit adder/subtractor • two target accumulator registers • rounding logic with Selectable modes • saturation logic with Selectable modes Data input to the DSP engine is derived from one of the following sources: 1. Directly from the W array (registers W4, W5, W6 or W7) for dual source operand DSP instructions. Data values for the W4, W5, W6 and W7 registers are pre-fetched via the X and Y memory data buses. 2. From the X memory data bus for all other DSP instructions. Data output from the DSP engine is written to one of the following destinations: 1. The target accumulator, as defined by the DSP instruction being executed. 2. The X memory data bus to any location in the data memory address space. The DSP engine has the capability to perform inherent accumulator to accumulator operations which require no additional data. The MCU shift and multiply instructions use the DSP engine hardware to obtain their results. The X memory data bus is used for data reads and writes in these operations. A block diagram of the DSP engine is shown in Figure 2-8. Note: For detailed code examples and instruction syntax related to this section, refer to the dsPIC30F Programmer’s Reference Manual (DS70030). © 2004 Microchip Technology Inc. DS70049C-page 2-19 Section 2. CPU CPU 2 Figure 2-8: DSP Engine Block Diagram Zero Backfill Sign-Extend Barrel Shifter 40-bit Accumulator A 40-bit Accumulator B Round Logic X Data Bus To/From W Array Adder Saturate Negate 32 32 32 16 16 16 16 40 40 40 40 Y Data Bus 40 16 40 Multiplier/Scaler 17-bit x 17-bit 16-bit to 17-bit Conversion Saturation Logic dsPIC30F Family Reference Manual DS70049C-page 2-20 © 2004 Microchip Technology Inc. 2.6.1 Data Accumulators There are two 40-bit data accumulators, ACCA and ACCB, that are the result registers for the DSP instructions listed in Table 2-3. Each accumulator is memory mapped to three registers, where ‘x’ denotes the particular accumulator: • ACCxL: ACCx<15:0> • ACCxH: ACCx<31:16> • ACCxU: ACCx<39:32> For fractional operations that use the accumulators, the radix point is located to the right of bit 31. The range of fractional values that be stored in each accumulator is -256.0 to (256.0 – 2-31). For integer operations that use the accumulators, the radix point is located to the right of bit 0. The range of integer values that can be stored in each accumulator is -549,755,813,888 to 549,755,813,887. 2.6.2 Multiplier The dsPIC30F features a 17-bit x 17-bit multiplier which is shared by both the MCU ALU and the DSP engine. The multiplier is capable of signed or unsigned operation and can support either 1.31 fractional (Q.31) or 32-bit integer results. The multiplier takes in 16-bit input data and converts the data to 17-bits. Signed operands to the multiplier are sign-extended. Unsigned input operands are zero-extended. The 17-bit conversion logic is transparent to the user and allows the multiplier to support mixed sign and unsigned/unsigned multiplication. The IF control bit (CORCON<0>) determines integer/fractional operation for the instructions listed in Table 2-3. The IF bit does not affect MCU multiply instructions listed in Table 2-4, which are always integer operations. The multiplier scales the result one bit to the left for fractional operation. The LSbit of the result is always cleared. The multiplier defaults to Fractional mode for DSP operations at a device Reset. The representation of data in hardware for each of these modes is as follows: • Integer data is inherently represented as a signed two’s complement value, where the MSbit is defined as a sign bit. Generally speaking, the range of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1. • Fractional data is represented as a two’s complement fraction where the MSbit is defined as a sign bit and the radix point is implied to lie just after the sign bit (Q.X format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 21-N). Figure 2-9 and Figure 2-10 illustrate how the multiplier hardware interprets data in Integer and Fractional modes. The range of data in both Integer and Fractional modes is listed in Table 2-2. © 2004 Microchip Technology Inc. DS70049C-page 2-21 Section 2. CPU CPU 2 Figure 2-9: Integer and Fractional Representation of 0x4001 Figure 2-10: Integer and Fractional Representation of 0xC002 Different Representations of 0x4001 Integer: -215 214 213 212 . . . . 0x4001 = 214 + 20 = 16385 1.15 Fractional: 2-15 0 2-1 2-2 2-3 -2 . . . 0 20 0x4001 = 2-1 + 2-15 = 0.500030518 Implied Radix Point . 1 0000000000000 1 0 1 0000000000000 1 Different Representations of 0xC002 Integer: -215 214 213 212 . . . . 0xC002 = -215 + 214 + 20 = -32768 + 16384 + 2 = -16382 1.15 Fractional: 2-15 . 2-1 2-2 2-3 -2 . . . 0 20 0xC002 = -20 + 2-1 + 2-14 = -1 + 0.5 + 0.000061035 = -0.499938965 Implied Radix Point 1 1 0000000000001 0 1 1 0000000000001 0 dsPIC30F Family Reference Manual DS70049C-page 2-22 © 2004 Microchip Technology Inc. Table 2-2: dsPIC30F Data Ranges 2.6.2.1 DSP Multiply Instructions The DSP instructions that utilize the multiplier are summarized in Table 2-3. Table 2-3: DSP Instructions that Utilize the Multiplier The US control bit (CORCON<12>) determines whether DSP multiply instructions are signed (default) or unsigned. The US bit does not influence the MCU multiply instructions which have specific instructions for signed or unsigned operation. If the US bit is set, the input operands for instructions shown in Table 2-3 are considered as unsigned values which are always zero-extended into the 17th bit of the multiplier value. 2.6.2.2 MCU Multiply Instructions The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiplies as shown in Table 2-4. All multiplications performed by the MUL instruction produce integer results. The MUL instruction may be directed to use byte or word sized operands. Byte input operands will produce a 16-bit result and word input operands will produce a 32-bit result to the specified register(s) in the W array. Table 2-4: MCU Instructions that Utilize the Multiplier Register Size Integer Range Fraction Range Fraction Resolution 16-bit -32768 to 32767 -1.0 to (1.0 – 2-15) (Q.15 Format) 3.052 x 10-5 32-bit -2,147,483,648 to 2,147,483,647 -1.0 to (1.0 – 2-31) (Q.31 Format) 4.657 x 10-10 40-bit -549,755,813,888 to 549,755,813,887 -256.0 to (256.0 – 2-31) (Q.31 Format with 8 Guard bits) 4.657 x 10-10 DSP Instruction Description Algebraic Equivalent MAC Multiply and Add to Accumulator OR Square and Add to Accumulator a = a + b*c a = a + b2 MSC Multiply and Subtract from Accumulator a = a – b*c MPY Multiply a = b*c MPY.N Multiply and Negate Result a = -b*c ED Partial Euclidean Distance a = (b – c)2 EDAC Add Partial Euclidean Distance to the Accumulator a = a + (b – c)2 Note: DSP instructions using the multiplier can operate in Fractional (1.15) or Integer modes. MCU Instruction Description MUL/MUL.UU Multiply two unsigned integers MUL.SS Multiply two signed integers MUL.SU/MUL.US Multiply a signed integer with an unsigned integer Note 1: MCU instructions using the multiplier operate only in Integer mode. 2: Result of an MCU multiply is 32-bits long and is stored in a pair of W registers. © 2004 Microchip Technology Inc. DS70049C-page 2-23 Section 2. CPU CPU 2 2.6.3 Data Accumulator Adder/Subtractor The data accumulators have a 40-bit adder/subtractor with automatic sign extension logic for the multiplier result (if signed). It can select one of two accumulators (A or B) as its pre-accumulation source and post-accumulation destination. For the ADD (accumulator) and LAC instructions, the data to be accumulated or loaded can optionally be scaled via the barrel shifter prior to accumulation. The 40-bit adder/subtractor may optionally negate one of its operand inputs to change the sign of the result (without changing the operands). The negate is used during multiply and subtract (MSC), or multiply and negate (MPY.N) operations. The 40-bit adder/subtractor has an additional saturation block which controls accumulator data saturation, if enabled. 2.6.3.1 Accumulator Status Bits Six Status register bits have been provided to support saturation and overflow. They are located in the CPU Status register, SR, and are listed below: Table 2-5: Accumulator Overflow and Saturation Status Bits The OA and OB bits are read only and are modified each time data passes through the accumulator add/subtract logic. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). This type of overflow is not catastrophic; the guard bits preserve the accumulator data. The OAB status bit is the logically ORed value of OA and OB. The OA and OB bits, when set, can optionally generate an arithmetic error trap. The trap is enabled by setting the corresponding overflow trap flag enable bit OVATE:OVBTE (INTCON1<10:9>). The trap event allows the user to take immediate corrective action, if desired. The SA and SB bits can be set each time data passes through the accumulator saturation logic. Once set, these bits remain set until cleared by the user. The SAB status bit indicates the logically ORed value of SA and SB. The SA and SB bits will be cleared when SAB is cleared. When set, these bits indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, the SA and SB bits indicate that a catastrophic overflow has occurred (the sign of the accumulator has been destroyed). If the COVTE (INTCON1<8>) bit is set, SA and SB bits will generate an arithmetic error trap when saturation is disabled. Status Bit Location Description OA SR<15> Accumulator A overflowed into guard bits (ACCA<39:32>) OB SR<14> Accumulator B overflowed into guard bits(ACCB<39:32>) SA SR<13> ACCA saturated (bit 31 overflow and saturation) or ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation) SB SR<12> ACCB saturated (bit 31 overflow and saturation) or ACCB overflowed into guard bits and saturated (bit 39 overflow and saturation) OAB SR<11> OA logically ORed with OB SAB SR<10> SA logically ORed with SB. Clearing SAB will also clear SA and SB. Note: See Section 6. “Reset Interrupts” for further information on arithmetic warning traps. Note: The user must remember that SA, SB and SAB status bits can have different meanings depending on whether accumulator saturation is enabled. The Accumulator Saturation mode is controlled via the CORCON register. dsPIC30F Family Reference Manual DS70049C-page 2-24 © 2004 Microchip Technology Inc. 2.6.3.2 Saturation and Overflow Modes The device supports three Saturation and Overflow modes. 1. Accumulator 39-bit Saturation: In this mode, the saturation logic loads the maximally positive 9.31 value (0x7FFFFFFFFF), or maximally negative 9.31 value (0x8000000000), into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This Saturation mode is useful for extending the dynamic range of the accumulator. To configure for this mode of saturation, the ACCSAT(CORCON<4>) bit must be set. Additionally, the SATA and/or SATB (CORCON<7 and/or 6>) bits must be set to enable accumulator saturation. 2. Accumulator 31-bit Saturation: In this mode, the saturation logic loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0xFF80000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits 32 through 39 are not used, except for sign-extension of the accumulator value. Consequently, the OA, OB or OAB bits in SR will never be set. To configure for this mode of overflow and saturation, the ACCSAT (CORCON<4>) bit must be cleared. Additionally, the SATA and/or SATB (CORCON<7 and/or 6>) bits must be set to enable accumulator saturation. 3. Accumulator Catastrophic Overflow: If the SATA and/or SATB (CORCON<7 and/or 6>) bits are not set, then no saturation operation is performed on the accumulator and the accumulator is allowed to overflow all the way up to bit 39 (destroying its sign). If the COVTE bit (INTCON1<8>) is set, a catastrophic overflow will initiate an arithmetic error trap. Note that accumulator saturation and overflow detection can only result from the execution of a DSP instruction that modifies one of the two accumulators via the 40-bit DSP ALU. Saturation and overflow detection will not take place when the accumulators are accessed as memory mapped registers via MCU class instructions. Furthermore, the accumulator status bits shown in Table 2-5 will not be modified. However, the MCU status bits (Z, N, C, OV, DC) will be modified depending on the MCU instruction that accesses the accumulator. 2.6.3.3 Data Space Write Saturation In addition to adder/subtractor saturation, writes to data space can be saturated without affecting the contents of the source accumulator. This feature allows data to be limited while not sacrificing the dynamic range of the accumulator during intermediate calculation stages. Data space write saturation is enabled by setting the SATDW control bit (CORCON<5>). Data space write saturation is enabled by default at a device Reset. The data space write saturation feature works with the SAC and SAC.R instructions. The value held in the accumulator is never modified when these instructions are executed. The hardware takes the following steps to obtain the saturated write result: 1. The read data is scaled based upon the arithmetic shift value specified in the instruction. 2. The scaled data is rounded (SAC.R only). 3. The scaled/rounded value is saturated to a 16-bit result based on the value of the guard bits. For data values greater than 0x007FFF, the data written to memory is saturated to the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data written to memory is saturated to the maximum negative 1.15 value, 0x8000. Note: See Section 6. “Reset Interrupts” for further information on arithmetic error traps. © 2004 Microchip Technology Inc. DS70049C-page 2-25 Section 2. CPU CPU 2 2.6.3.4 Accumulator ‘Write Back’ The MAC and MSC instructions can optionally write a rounded version of the accumulator that is not the target of the current operation into data space memory. The write is performed across the X-bus into combined X and Y address space. This accumulator write back feature is beneficial in certain FFT and LMS algorithms. The following Addressing modes are supported by the accumulator write back hardware: 1. W13, register direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fractional result. 2. [W13]+=2, register indirect with post-increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2. 2.6.4 Round Logic The round logic can perform a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND (CORCON<1>) bit. It generates a 16-bit, 1.15 data value, which is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored. The two Rounding modes are shown in Figure 2-11. Conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the MSWord excluding the guard or overflow bits (bits 16 through 31). If the LSWord of the accumulator is between 0x8000 and 0xFFFF (0x8000 included), the MSWord is incremented. If the LSWord of the accumulator is between 0x0000 and 0x7FFF, the MSWord is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value will tend to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding except when the LSWord equals 0x8000. If this is the case, the LSbit of the MSWord (bit 16 of the accumulator) is examined. If it is ‘1’, the MSWord is incremented. If it is ‘0’, the MSWord is not modified. Assuming that bit 16 is effectively random in nature, this scheme will remove any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X-bus (subject to data saturation, see Section 2.6.3.3 “Data Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write back data path is always subject to rounding. Figure 2-11: Conventional and Convergent Rounding Modes 16 15 0 16 15 0 16 15 0 16 15 0 1XXX XXXX XXXX XXXX 1000 0000 0000 0000 0XXX XXXX XXXX XXXX 1000 0000 0000 0000 1 0 Conventional (Biased) Convergent (Unbiased) Round Up (add 1 to MSWord) when: Round Down (add nothing) when: Round Up (add 1 to MSWord) when: 1. LSWord = 0x8000 and bit 16 = 1 2. LSWord > 0x8000 LSWord >= 0x8000 LSWord < 0x8000 Round Down (add nothing) when: 1. LSWord = 0x8000 and bit 16 = 0 2. LSWord < 0x8000 MSWord MSWord MSWord MSWord dsPIC30F Family Reference Manual DS70049C-page 2-26 © 2004 Microchip Technology Inc. 2.6.5 Barrel Shifter The barrel shifter is capable of performing up to a 16-bit arithmetic right shift, or up to a 16-bit left shift, in a single cycle. The barrel shifter can be used by DSP instructions or MCU instructions for multi-bit shifts. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation: • A positive value will shift the operand right • A negative value will shift the operand left • A value of ‘0’ will not modify the operand The barrel shifter is 40-bits wide to accommodate the width of the accumulators. A 40-bit output result is provided for DSP shift operations, and a 16-bit result for MCU shift operations. A summary of instructions that use the barrel shifter is provided below in Table 2-6. Table 2-6: Instructions that Utilize the DSP Engine Barrel Shifter 2.6.6 DSP Engine Mode Selection The various operational characteristics of the DSP engine discussed in previous sub-sections can be selected through the CPU Core Configuration register (CORCON). These are listed below: • Fractional or integer multiply operation. • Conventional or convergent rounding. • Automatic saturation on/off for ACCA. • Automatic saturation on/off for ACCB. • Automatic saturation on/off for writes to data memory. • Accumulator Saturation mode selection. 2.6.7 DSP Engine Trap Events The various arithmetic error traps that can be generated for handling exceptions in the DSP engine are selected through the Interrupt Control register (INTCON1). These are listed below: • Trap on ACCA overflow enable, using OVATE (INTCON1<10>). • Trap on ACCB overflow enable, using OVBTE (INTCON1<9>). • Trap on catastrophic ACCA and/or ACCB overflow enable, using COVTE (INTCON1<8>). An arithmetic error trap will also be generated when the user attempts to shift a value beyond the maximum allowable range (+/- 16 bits) using the SFTAC instruction. This trap source cannot be disabled. The execution of the instruction will complete, but the results of the shift will not be written to the target accumulator. For further information on bits in the INTCON1 register and arithmetic error traps, please refer to Section 6. “Reset Interrupts”. Instruction Description ASR Arithmetic multi-bit right shift of data memory location LSR Logical multi-bit right shift of data memory location SL Multi-bit shift left of data memory location SAC Store DSP accumulator with optional shift SFTAC Shift DSP accumulator © 2004 Microchip Technology Inc. DS70049C-page 2-27 Section 2. CPU CPU 2 2.7 Divide Support The dsPIC30F supports the following types of division operations: • DIVF: 16/16 signed fractional divide • DIV.SD: 32/16 signed divide • DIV.UD: 32/16 unsigned divide • DIV.SW: 16/16 signed divide • DIV.UW: 16/16 unsigned divide The quotient for all divide instructions is placed in W0, and the remainder in W1. The 16-bit divisor can be located in any W register. A 16-bit dividend can be located in any W register and a 32-bit dividend must be located in an adjacent pair of W registers. All divide instructions are iterative operations and must be executed 18 times within a REPEAT loop. The user is responsible for programming the REPEAT instruction. A complete divide operation takes 19 instruction cycles to execute. The divide flow is interruptible, just like any other REPEAT loop. All data is restored into the respective data registers after each iteration of the loop, so the user will be responsible for saving the appropriate W registers in the ISR. Although they are important to the divide hardware, the intermediate values in the W registers have no meaning to the user. The divide instructions must be executed 18 times in a REPEAT loop to produce a meaningful result. Refer to the “dsPIC30F Programmer’s Reference Manual” (DS70030) for more information and programming examples for the divide instructions. 2.8 Instruction Flow Types Most instructions in the dsPIC30F architecture occupy a single word of program memory and execute in a single cycle. An instruction pre-fetch mechanism facilitates single cycle (1 TCY) execution. However, some instructions take 2 or 3 instruction cycles to execute. Consequently, there are seven different types of instruction flow in the dsPIC® architecture. These are described below: 1. 1 Instruction Word, 1 Instruction Cycle: These instructions will take one instruction cycle to execute as shown in Figure 2-12. Most instructions are 1-word, 1-cycle instructions. Figure 2-12: Instruction Flow – 1-Word, 1-Cycle 2. 1 Instruction Word, 2 Instruction Cycles: In these instructions, there is no pre-fetch flush. The only instructions of this type are the MOV.D instructions (load and store double-word). Two cycles are required to complete these instructions, as shown in Figure 2-13. Figure 2-13: Instruction Flow – 1-Word, 2-Cycle (MOV.D Operation) TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOV #0x55AA,W0 Fetch 1 Execute 1 2. MOV W0,PORTA Fetch 2 Execute 2 3. MOV W0,PORTB Fetch 3 Execute 3 TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOV #0x1234,W0 Fetch 1 Execute 1 2. MOV.D [W0++],W1 Fetch 2 Execute 2 R/W Cycle 1 3. MOV #0x00AA,W1 Fetch 3 Execute 2 R/W Cycle2 No Fetch Execute 3 4. MOV #0x00CC,W0 Fetch 4 Execute 4 dsPIC30F Family Reference Manual DS70049C-page 2-28 © 2004 Microchip Technology Inc. 3. 1 Instruction Word, 2 or 3 Instruction Cycle Program Flow Changes: These instructions include relative call and branch instructions, and skip instructions. When an instruction changes the PC (other than to increment it), the program memory pre-fetch data must be discarded. This makes the instruction take two effective cycles to execute, as shown in Figure 2-14. Figure 2-14: Instruction Flow – 1-Word, 2-Cycle (Program Flow Change) Three cycles will be taken when a two-word instruction is skipped. In this case, the program memory pre-fetch data is discarded and the second word of the two-word instruction is fetched. The second word of the instruction will be executed as a NOP, as shown in Figure 2-15. Figure 2-15: Instruction Flow – 1-Word, 3-Cycle (2-Word Instruction Skipped) 4. 1 Instruction Word, 3 Instruction Cycles (RETFIE, RETURN, RETLW): The RETFIE, RETURN and RETLW instructions, that are used to return from a subroutine call or an Interrupt Service Routine, take 3 instruction cycles to execute, as shown in Figure 2-16. Figure 2-16: Instruction Flow – 1-Word, 3-Cycle (RETURN, RETFIE, RETLW) TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOV.B #0x55,W0 Fetch 1 Execute 1 2. BTSC PORTA,#3 Fetch 2 Execute 2 Skip Taken 3. ADD.B PORTA (executed as FNOP) Fetch 3 Forced NOP 4. BRA SUB_1 Fetch 4 Execute 4 5. ADD.B PORTB (executed as FNOP) Fetch 5 Forced NOP 6. SUB_1: Instruction @ address SUB_1 Fetch SUB_1 TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. BTSC SR,#Z Fetch 1 Execute 1, Skip Taken 2. GOTO LABEL Fetch 2 Forced NOP (GOTO 2nd word) Fetch 2nd word of GOTO 2nd word executed as a NOP 3. BCLR PORTB,#3 Fetch 3 Execute 3 4. MOV W0,W1 Fetch 4 Execute 4 TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOV #0x55AA,W0 Fetch 1 Execute 1 2. RETURN Fetch 2 Execute 2 3. (instruction in old program flow) Fetch 3 Execute 2 4. MOV W0, W3 (instruction in new program flow) No Fetch Execute 2 5. MOV W3, W5 Fetch 4 Execute 4 Fetch 5 © 2004 Microchip Technology Inc. DS70049C-page 2-29 Section 2. CPU CPU 2 5. Table Read/Write Instructions: These instructions will suspend fetching to insert a read or write cycle to the program memory. The instruction fetched while executing the table operation is saved for 1 cycle and executed in the cycle immediately after the table operation as shown in Figure 2-17. Figure 2-17: Instruction Pipeline Flow – Table Operations 6. 2 Instruction Words, 2 Instruction Cycles: In these instructions, the fetch after the instruction contains data. This results in a 2-cycle instruction as shown in Figure 2-18. The second word of a two-word instruction is encoded so that it will be executed as a NOP, should it be fetched by the CPU without first fetching the first word of the instruction. This is important when a two-word instruction is skipped by a skip instruction (see Figure 2-15). Figure 2-18: Instruction Pipeline Flow – 2-Word, 2-Cycle 7. Address Register Dependencies: These are instructions that are subjected to a stall due to a data address dependency between the X-data space read and write operations. An additional cycle is inserted to resolve the resource conflict as discussed in Section 2.10 “Address Register Dependencies”. Figure 2-19: Instruction Pipeline Flow – 1-Word, 1-Cycle (With Instruction Stall) TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOV #0x1234,W0 Fetch 1 Execute 1 2. TBLRDL.w [W0++],W1 Fetch 2 Execute 2 3. MOV #0x00AA,W1 Fetch 3 PM Data Read Cycle Bus Read Execute 3 4. MOV #0x00CC,W0 Fetch 4 Execute 4 TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOV #0xAA55,W0 Fetch 1 Execute 1 2. GOTO LABEL Fetch 2L Update PC Fetch 2H Forced NOP 3. LABEL: MOV W0,W2 Fetch 3 Execute 3 4. BSET PORTA, #3 Fetch 4 Execute 4 TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOV W0,W1 Fetch 1 Execute 1 2. MOV [W1],[W4] Fetch 2 Execute 1 Stall Execute 2 3. MOV W2,W1 Fetch 3 Execute 3 dsPIC30F Family Reference Manual DS70049C-page 2-30 © 2004 Microchip Technology Inc. 2.9 Loop Constructs The dsPIC30F supports both REPEAT and DO instruction constructs to provide unconditional automatic program loop control. The REPEAT instruction is used to implement a single instruction program loop. The DO instruction is used to implement a multiple instruction program loop. Both instructions use control bits within the CPU Status register, SR, to temporarily modify CPU operation. 2.9.1 Repeat Loop Construct The REPEAT instruction causes the instruction that follows it to be repeated a number of times. A literal value contained in the instruction or a value in one of the W registers can be used to specify the repeat count value. The W register option enables the loop count to be a software variable. An instruction in a REPEAT loop will be executed at least once. The number of iterations for a repeat loop will be the 14-bit literal value + 1, or Wn + 1. The syntax for the two forms of the REPEAT instruction is given below: REPEAT #lit14 ; RCOUNT <-- lit14 (Valid target Instruction) or REPEAT Wn ; RCOUNT <-- Wn (Valid target Instruction) 2.9.1.1 Repeat Operation The loop count for Repeat operations is held in the 14-bit RCOUNT register, which is memory mapped. RCOUNT is initialized by the REPEAT instruction. The REPEAT instruction sets the Repeat Active, or RA (SR<4>) status bit to ‘1’, if the RCOUNT is a non-zero value. RA is a read only bit and cannot be modified through software. For repeat loop count values greater than ‘0’, the PC is not incremented. Further PC increments are inhibited until RCOUNT = 0. See Figure 2-20 for an instruction flow example of a Repeat loop. For a loop count value equal to ‘0’, REPEAT has the effect of a NOP and the RA (SR<4>) bit is not set. The Repeat loop is essentially disabled before it begins, allowing the target instruction to execute only once while pre-fetching the subsequent instruction (i.e., normal execution flow). Figure 2-20: REPEAT Instruction Pipeline Flow Note: The instruction immediately following the REPEAT instruction (i.e., the target instruction) is always executed at least one time. It is always executed one time more than the value specified in the 14-bit literal or the W register operand. TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1.REPEAT #0x2 Fetch 1 Execute 1 2.MAC W4*W5,A,[W8]+=2,W4 Fetch 2 Execute 2 No Fetch Execute 2 No Fetch Execute 2 3.BSET PORTA,#3 Fetch 3 Execute 3 PC (at end of instruction) PC PC+2 PC+2 PC+2 PC+4 PC+6 RCOUNT (at end of instruction) X210 0 0 RA (at end of instruction) 0110 0 0 © 2004 Microchip Technology Inc. DS70049C-page 2-31 Section 2. CPU CPU 2 2.9.1.2 Interrupting a REPEAT Loop A REPEAT instruction loop may be interrupted at any time. The RA state is preserved on the stack during exception processing to allow the user to execute further REPEAT loops from within (any number) of nested interrupts. After SRL is stacked, the RA status bit is cleared to restore normal execution flow within the ISR. Returning into a Repeat loop from an ISR using RETFIE requires no special handling. Interrupts will pre-fetch the repeated instruction during the third cycle of the RETFIE. The stacked RA bit will be restored when the SRL register is popped and, if set, the interrupted Repeat loop will be resumed. 2.9.1.2.1 Early Termination of a Repeat Loop An interrupted Repeat loop can be terminated earlier than normal in the ISR by clearing the RCOUNT register in software. 2.9.1.3 Restrictions on the REPEAT Instruction Any instruction can immediately follow a REPEAT except for the following: 1. Program Flow Control instructions (any branch, compare and skip, subroutine calls, returns, etc.). 2. Another REPEAT or DO instruction. 3. DISI, ULNK, LNK, PWRSAV, RESET. 4. MOV.D instruction. Note: If a Repeat loop has been interrupted and an ISR is being processed, the user must stack the RCOUNT (Repeat Count register) prior to executing another REPEAT instruction within an ISR. Note: If Repeat was used within an ISR, the user must unstack RCOUNT prior to executing RETFIE. Note: Should the repeated instruction (target instruction in the Repeat loop) be accessing data from PS using PSV, the first time it is executed after a return from an exception will require 2 instruction cycles. Similar to the first iteration of a loop, timing limitations will not allow the first instruction to access data residing in PS in a single instruction cycle. Note: There are some instructions and/or Instruction Addressing modes that can be executed within a Repeat loop, but make little sense when repeated. dsPIC30F Family Reference Manual DS70049C-page 2-32 © 2004 Microchip Technology Inc. 2.9.2 DO Loop Construct The DO instruction can execute a group of instructions that follow it a specified number of times without software overhead. The set of instructions up to and including the end address will be repeated. The repeat count value for the DO instruction can be specified by a 14-bit literal or by the contents of a W register declared within the instruction. The syntax for the two forms of the DO instruction is given below: DO #lit14,LOOP_END ; DCOUNT <-- lit14 Instruction1 Instruction2 : : LOOP_END: Instruction n DO Wn,LOOP_END ; DCOUNT <-- Wn<13:0> Instruction1 Instruction2 : : LOOP_END: Instruction n The following features are provided in the DO loop construct: • A W register can be used to specify the loop count. This allows the loop count to be defined at run-time. • The instruction execution order need not be sequential (i.e., there can be branches, subroutine calls, etc.). • The loop end address does not have to be greater than the start address. 2.9.2.1 DO Loop Registers and Operation The number of iterations executed by a DO loop will be the (14-bit literal value +1) or the (Wn value + 1). If a W register is used to specify the number of iterations, the two MSbits of the W register are not used to specify the loop count. The operation of a DO loop is similar to the ‘do-while’ construct in the C programming language because the instructions in the loop will always be executed at least once. The dsPIC30F has three registers associated with DO loops: DOSTART, DOEND and DCOUNT. These registers are memory mapped and automatically loaded by the hardware when the DO instruction is executed. DOSTART holds the starting address of the DO loop while DOEND holds the end address of the DO loop. The DCOUNT register holds the number of iterations to be executed by the loop. DOSTART and DOEND are 22-bit registers that hold the PC value. The MSbits and LSbits of these registers is fixed to ‘0’. Refer to Figure 2-2 for further details. The LSbit is not stored in these registers because PC<0> is always forced to ‘0’. The DA status bit (SR<9>) indicates that a single DO loop (or nested DO loops) is active. The DA bit is set when a DO instruction is executed and enables a PC address comparison with the DOEND register on each subsequent instruction cycle. When PC matches the value in DOEND, DCOUNT is decremented. If the DCOUNT register is not zero, the PC is loaded with the address contained in the DOSTART register to start another iteration of the DO loop. The DO loop will terminate when DCOUNT = 0. If there are no other nested DO loops in progress, then the DA bit will also be cleared. Note: The group of instructions in a DO loop construct is always executed at least one time. The DO loop is always executed one time more than the value specified in the literal or W register operand. © 2004 Microchip Technology Inc. DS70049C-page 2-33 Section 2. CPU CPU 2 2.9.2.2 DO Loop Nesting The DOSTART, DOEND and DCOUNT registers each have a shadow register associated with them, such that the DO loop hardware supports one level of automatic nesting. The DOSTART, DOEND and DCOUNT registers are user accessible and they may be manually saved to permit additional nesting, where required. The DO Level bits, DL<2:0> (CORCON<10:8>) indicate the nesting level of the DO loop currently being executed. When the first DO instruction is executed, DL<2:0> is set to B‘001’ to indicate that one level of DO loop is underway. The DA (SR<9>) is also set. When another DO instruction is executed within the first DO loop, the DOSTART, DOEND and DCOUNT registers are transferred into the shadow registers, prior to being updated with the new loop values. The DL<2:0> bits are set to B‘010’ indicating that a second, nested DO loop is in progress. The DA (SR<9>) bit also remains set. If no more than one level of DO loop nesting is required in the application, no special attention is required. Should the user require more than one level of DO loop nesting, this may be achieved through manually saving the DOSTART, DOEND and DCOUNT registers prior to executing the next DO instruction. These registers should be saved whenever DL<2:0> is B’010’ or greater. The DOSTART, DOEND and DCOUNT registers will automatically be restored from their shadow registers when a DO loop terminates and DL<2:0> = B’010’. 2.9.2.3 Interrupting a DO Loop DO loops may be interrupted at any time. If another DO loop is to be executed during the ISR, the user must check the DL<2:0> status bits and save the DOSTART, DOEND and DCOUNT registers as required. No special handling is required if the user can ensure that only one level of DO loop will ever be executed in: • both background and any one ISR handler (if interrupt nesting is enabled) or • both background and any ISR (if interrupt nesting is disabled) Alternatively, up to two (nested) DO loops may be executed in either background or within any • one ISR handler (if interrupt nesting is enabled) or • in any ISR (if interrupt nesting is disabled) It is assumed that no DO loops are used within any trap handlers. Returning to a DO loop from an ISR, using the RETFIE instruction, requires no special handling. 2.9.2.4 Early Termination of the DO loop There are two ways to terminate a DO loop, earlier than normal: 1. The EDT (CORCON<11>) bit provides a means for the user to terminate a DO loop before it completes all loops. Writing a ‘1’ to the EDT bit will force the loop to complete the iteration underway and then terminate. If EDT is set during the penultimate or last instruction of the loop, one more iteration of the loop will occur. EDT will always read as a ‘0’; clearing it has no effect. After the EDT bit is set, the user can optionally branch out of the DO loop. 2. Alternatively, the code may branch out of the loop at any point except from the last instruction, which cannot be a flow control instruction. Although the DA bit enables the DO loop hardware, it will have no effect unless the address of the penultimate instruction is encountered during an instruction pre-fetch. This is not a recommended method for terminating a DO loop. Note: The DL<2:0> (CORCON<10:8>) bits are combined (logically OR-ed) to form the DA (SR<9>) bit. If nested DO loops are being executed, the DA bit is cleared only when the loop count associated with the outer most loop expires. Note: Exiting a DO loop without using EDT is not recommended because the hardware will continue to check for DOEND addresses. dsPIC30F Family Reference Manual DS70049C-page 2-34 © 2004 Microchip Technology Inc. 2.9.2.5 DO Loop Restrictions DO loops have the following restrictions imposed: • choice of last instruction in the loop • the loop length (offset from the first instruction) • reading of the DOEND register All DO loops must contain at least 2 instructions because the loop termination tests are performed in the penultimate instruction. REPEAT should be used for single instruction loops. The special function register, DOEND, cannot be read by user software in the instruction that immediately follows either a DO instruction, or a file register write operation to the DOEND SFR. The instruction that is executed two instructions before the last instruction in a DO loop should not modify any of the following: • CPU priority level governed by the IPL (SR<7:5>) bits • Peripheral Interrupt Enable bits governed by the IEC0, IEC1 and IEC2 registers • Peripheral Interrupt Priority bits governed by the IPC0 through IPC11 registers If the restrictions above are not followed, the DO loop may execute incorrectly. 2.9.2.5.1 Last Instruction Restrictions There are restrictions on the last instruction executed in a DO loop. The last instruction in a DO loop should not be: 1. Flow control instruction (for e.g., any branch, compare and skip, GOTO, CALL, RCALL, TRAP). 2. RETURN, RETFIE and RETLW will work correctly as the last instruction of a DO loop, but the user must be responsible for returning into the loop to complete it. 3. Another REPEAT or DO instruction. 4. Target instruction within a REPEAT loop. This restriction implies that the penultimate instruction also cannot be a REPEAT. 5. Any instruction that occupies two words in program space. 6. DISI instruction 2.9.2.5.2 Loop Length Restrictions Loop length is defined as the signed offset of the last instruction from the first instruction in the DO loop. The loop length when added to the address of the first instruction in the loop forms the address of the last instruction of the loop.There are some loop length values that should be avoided. 1. Loop Length = -2 Execution will start at the first instruction in the loop (i.e., at [PC]) and will continue until the loop end address (in this case [PC – 4]) is pre-fetched. As this is the first word of the DO instruction, it will execute the DO instruction again, re-initializing the DCOUNT and pre-fetching [PC]. This will continue forever as long as the loop end address [PC – 4] is pre-fetched. This value of n has the potential of creating an infinite loop (subject to a Watchdog Timer Reset). end_loop: DO #33, end_loop ;DO is a two-word instruction NOP ;2nd word of DO executes as a NOP ADD W2,W3,W4 ;First instruction in DO loop([PC]) © 2004 Microchip Technology Inc. DS70049C-page 2-35 Section 2. CPU CPU 2 2. Loop Length = -1 Execution will start at the first instruction in the loop (i.e., at [PC]) and will continue until the loop end address ([PC – 2]) is pre-fetched. Since the loop end address is the second word of the DO instruction, it will execute as a NOP but will still pre-fetch [PC]. The loop will then execute again. This will continue as long as the loop end address [PC – 2] is pre-fetched and the loop does not terminate. Should the value in the DCOUNT register reach zero and on a subsequent decrement generate a borrow, the loop will terminate. However, in such a case the initial instruction outside the loop will once again be the first loop instruction. DO #33, end_loop ;DO is a two-word instruction end_loop: NOP ;2nd word of DO executes as a NOP ADD W2,W3,W4 ;First instruction in DO loop([PC]) 3. Loop Length = 0 Execution will start at the first instruction in the loop (i.e., at [PC]) and will continue until the loop end address ([PC]) is pre-fetched. If the loop is to continue, this pre-fetch will cause the DO loop hardware to load the DOEND address ([PC]) into the PC for the next fetch (which will be [PC] again). After the first true iteration of the loop, the first instruction in the loop will be executed repeatedly until the loop count underflows and the loop terminates. When this occurs, the initial instruction outside the loop will be the instruction after [PC]. DO #33, end_loop ;DO is a two-word instruction NOP ;2nd word of DO executes as a NOP end_loop: ADD W2,W3,W4 ;First instruction in DO loop([PC]) 2.10 Address Register Dependencies The dsPIC30F architecture supports a data space read (source) and a data space write (destination) for most MCU class instructions. The effective address (EA) calculation by the AGU and subsequent data space read or write, each take a period of 1 instruction cycle to complete. This timing causes the data space read and write operations for each instruction to partially overlap, as shown in Figure 2-21. Because of this overlap, a ‘Read-After-Write’ (RAW) data dependency can occur across instruction boundaries. RAW data dependencies are detected and handled at run-time by the dsPIC30F CPU. Figure 2-21: Data Space Access Timing ADD MOV [W7] [W10] [W9]++ X-Space Address W7 W10 W8 W9 ADD W0, [W7], [W10] MOV [W8], [W9]++ X-Space RAGU [W8] Instruction Register Contents X-Space WAGU 1 Instruction Cycle (TCY) TCY0 TCY1 TCY2 dsPIC30F Family Reference Manual DS70049C-page 2-36 © 2004 Microchip Technology Inc. 2.10.1 Read-After-Write Dependency Rules If the W register is used as a write operation destination in the current instruction and the W register being read in the pre-fetched instruction are the same, the following rules will apply: 1. If the destination write (current instruction) does not modify the contents of Wn, no stalls will occur. or 2. If the source read (pre-fetched instruction) does not calculate an EA using Wn, no stalls will occur. During each instruction cycle, the dsPIC30F hardware automatically checks to see if a RAW data dependency is about to occur. If the conditions specified above are not satisfied, the CPU will automatically add a one instruction cycle delay before executing the pre-fetched instruction. The instruction stall provides enough time for the destination W register write to take place before the next (pre-fetched) instruction has to use the written data. Table 2-7: Read-After-Write Dependency Summary 2.10.2 Instruction Stall Cycles An instruction stall is essentially a one instruction cycle wait period appended in front of the read phase of an instruction, in order to allow the prior write to complete before the next read operation. For the purposes of interrupt latency, it should be noted that the stall cycle is associated with the instruction following the instruction where it was detected (i.e., stall cycles always precede instruction execution cycles). Destination Addressing Mode using Wn Source Addressing Mode using Wn Status Examples (Wn = W2) Direct Direct Allowed ADD.w W0, W1, W2 MOV.w W2, W3 Direct Indirect Stall ADD.w W0, W1, W2 MOV.w [W2], W3 Direct Indirect with modification Stall ADD.w W0, W1, W2 MOV.w [W2++], W3 Indirect Direct Allowed ADD.w W0, W1, [W2] MOV.w W2, W3 Indirect Indirect Allowed ADD.w W0, W1, [W2] MOV.w [W2], W3 Indirect Indirect with modification Allowed ADD.w W0, W1, [W2] MOV.w [W2++], W3 Indirect with modification Direct Allowed ADD.w W0, W1, [W2++] MOV.w W2, W3 Indirect Indirect Stall ADD.w W0, W1, [W2] MOV.w [W2], W3 ; W2=0x0004 (mapped W2) Indirect Indirect with modification Stall ADD.w W0, W1, [W2] MOV.w [W2++], W3 ; W2=0x0004 (mapped W2) Indirect with modification Indirect Stall ADD.w W0, W1, [W2++] MOV.w [W2], W3 Indirect with modification Indirect with modification Stall ADD.w W0, W1, [W2++] MOV.w [W2++], W3 © 2004 Microchip Technology Inc. DS70049C-page 2-37 Section 2. CPU CPU 2 If a RAW data dependency is detected, the dsPIC30F will begin an instruction stall. During an instruction stall, the following events occur: 1. The write operation underway (for the previous instruction) is allowed to complete as normal. 2. Data space is not addressed until after the instruction stall. 3. PC increment is inhibited until after the instruction stall. 4. Further instruction fetches are inhibited until after the instruction stall. 2.10.2.1 Instruction Stall Cycles and Interrupts When an interrupt event coincides with two adjacent instructions that will cause an instruction stall, one of two possible outcomes could occur: 1. The interrupt could be coincident with the first instruction. In this situation, the first instruction will be allowed to complete and the second instruction will be executed after the ISR completes. In this case, the stall cycle is eliminated from the second instruction because the exception process provides time for the first instruction to complete the write phase. 2. The interrupt could be coincident with the second instruction. In this situation, the second instruction and the appended stall cycle will be allowed to execute prior to the ISR. In this case, the stall cycle associated with the second instruction executes normally. However, the stall cycle will be effectively absorbed into the exception process timing. The exception process proceeds as if an ordinary two-cycle instruction was interrupted. 2.10.2.2 Instruction Stall Cycles and Flow Change Instructions The CALL and RCALL instructions write to the stack using W15 and may, therefore, force an instruction stall prior to the next instruction, if the source read of the next instruction uses W15. The RETFIE and RETURN instructions can never force an instruction stall prior to the next instruction because they only perform read operations. However, the user should note that the RETLW instruction could force a stall, because it writes to a W register during the last cycle. The GOTO and branch instructions can never force an instruction stall because they do not perform write operations. 2.10.2.3 Instruction Stalls and DO and REPEAT Loops Other than the addition of instruction stall cycles, RAW data dependencies will not affect the operation of either DO or REPEAT loops. The pre-fetched instruction within a REPEAT loop does not change until the loop is complete or an exception occurs. Although register dependency checks occur across instruction boundaries, the dsPIC30F effectively compares the source and destination of the same instruction during a REPEAT loop. The last instruction of a DO loop either pre-fetches the instruction at the loop start address or the next instruction (outside the loop). The instruction stall decision will be based on the last instruction in the loop and the contents of the pre-fetched instruction. 2.10.2.4 Instruction Stalls and Program Space Visibility (PSV) When program space (PS) is mapped to data space by enabling the PSV (CORCON<2>) bit, and the X space EA falls within the visible program space window, the read or write cycle is redirected to the address in program space. Accessing data from program space takes up to 3 instruction cycles. Instructions operating in PSV address space are subject to RAW data dependencies and consequent instruction stalls, just like any other instruction. Consider the following code segment: ADD W0,[W1],[W2++] ; PSV = 1, W1=0x8000, PSVPAG=0xAA MOV [W2],[W3] This sequence of instructions would take 5 instruction cycles to execute. 2 instruction cycles are added to perform the PSV access via W1. Furthermore, an instruction stall cycle is inserted to resolve the RAW data dependency caused by W2. dsPIC30F Family Reference Manual DS70049C-page 2-38 © 2004 Microchip Technology Inc. 2.11 Register Maps A summary of the registers associated with the dsPIC30F CPU core is provided in Table 2-8. Table 2-8: dsPIC30F Core Register Map Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State W0 0000 W0 (WREG) 0000 0000 0000 0000 W1 0002 W1 0000 0000 0000 0000 W2 0004 W2 0000 0000 0000 0000 W3 0006 W3 0000 0000 0000 0000 W4 0008 W4 0000 0000 0000 0000 W5 000A W5 0000 0000 0000 0000 W6 000C W6 0000 0000 0000 0000 W7 000E W7 0000 0000 0000 0000 W8 0010 W8 0000 0000 0000 0000 W9 0012 W9 0000 0000 0000 0000 W10 0014 W10 0000 0000 0000 0000 W11 0016 W11 0000 0000 0000 0000 W12 0018 W12 0000 0000 0000 0000 W13 001A W13 0000 0000 0000 0000 W14 001C W14 0000 0000 0000 0000 W15 001E W15 0000 0000 0000 0000 SPLIM 0020 SPLIM 0000 0000 0000 0000 ACCAL 0022 ACCAL 0000 0000 0000 0000 ACCAH 0024 ACCAH 0000 0000 0000 0000 ACCAU 0026 Sign-extension of ACCA<39> ACCAU 0000 0000 0000 0000 ACCBL 0028 ACCBL 0000 0000 0000 0000 ACCBH 002A ACCBH 0000 0000 0000 0000 ACCBU 002C Sign-extension of ACCB<39> ACCBU 0000 0000 0000 0000 PCL 002E PCL 0000 0000 0000 0000 PCH 0030 — — — — — — — — — PCH 0 0000 0000 0000 0000 TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000 PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000 RCOUNT 0036 RCOUNT xxxx xxxx xxxx xxxx DCOUNT 0038 DCOUNT xxxx xxxx xxxx xxxx DOSTARTL 003A DOSTARTL 0 xxxx xxxx xxxx xxx0 DOSTARTH 003C — — — — — — — — — — DOSTARTH 0000 0000 00xx xxxx DOENDL 003E DOENDL 0 xxxx xxxx xxxx xxx0 DOENDH 0040 — — — — — — — — — — DOENDH 0000 0000 00xx xxxx SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000 © 2004 Microchip Technology Inc. DS70049C-page 2-39 Section 2. CPU CPU 2 CORCON 0044 — — — US EDT DL2 DL<1:0> SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000 MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000 XMODSRT 0048 XMODSRT<15:0> 0 xxxx xxxx xxxx xxx0 XMODEND 004A XMODEND<15:0> 1 xxxx xxxx xxxx xxx1 YMODSRT 004C YMODSRT<15:0> 0 xxxx xxxx xxxx xxx0 YMODEND 004E YMODEND<15:0> 1 xxxx xxxx xxxx xxx1 XBREV 0050 BREN XBREV<14:0> xxxx xxxx xxxx xxxx DISICNT 0052 — — DISICNT<13:0> 0000 0000 0000 0000 Reserved 0054 - 007E — — — — — — — — — — — — — — — — 0000 0000 0000 0000 Legend: x = uninitiated Note: Refer to the device data sheet for specific Core Register Map details. Table 2-8: dsPIC30F Core Register Map (Continued) Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State dsPIC30F Family Reference Manual DS70049C-page 2-40 © 2004 Microchip Technology Inc. 2.12 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the dsPIC30F CPU module are: Title Application Note # No related application notes at this time. Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. © 2004 Microchip Technology Inc. DS70049C-page 2-41 Section 2. CPU CPU 2 2.13 Revision History Revision A This is the initial released revision of this document. Revision B This revision incorporates additional technical content for the dsPIC30F CPU module. Revision C This revision incorporates all known errata at the time of this document update. dsPIC30F Family Reference Manual DS70049C-page 2-42 © 2004 Microchip Technology Inc. NOTES: © 2004 Microchip Technology Inc. DS70050C-page 3-1 Data Memory 3 Section 3. Data Memory HIGHLIGHTS This section of the manual contains the following topics: 3.1 Introduction .................................................................................................................... 3-2 3.2 Data Space Address Generator Units (AGUs)............................................................... 3-5 3.3 Modulo Addressing ........................................................................................................ 3-7 3.4 Bit-Reversed Addressing ............................................................................................. 3-14 3.5 Control Register Descriptions ...................................................................................... 3-18 3.6 Related Application Notes............................................................................................3-23 3.7 Revision History ........................................................................................................... 3-24 dsPIC30F Family Reference Manual DS70050C-page 3-2 © 2004 Microchip Technology Inc. 3.1 Introduction The dsPIC30F data width is 16-bits. All internal registers and data space memory are organized as 16-bits wide. The dsPIC30F features two data spaces. The data spaces can be accessed separately (for some DSP instructions) or together as one 64-Kbyte linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. An example data space memory map is shown in Figure 3-1. Data memory addresses between 0x0000 and 0x07FF are reserved for the device special function registers (SFRs). The SFRs include control and status bits for the CPU and peripherals on the device. The RAM begins at address 0x0800 and is split into two blocks, X and Y data space. For data writes, the X and Y data spaces are always accessed as a single, linear data space. For data reads, the X and Y memory spaces can be accessed independently or as a single, linear space. Data reads for MCU class instructions always access the the X and Y data spaces as a single combined data space. Dual source operand DSP instructions, such as the MAC instruction, access the X and Y data spaces separately to support simultaneous reads for the two source operands. MCU instructions can use any W register as an address pointer for a data read or write operation. During data reads, the DSP class of instructions isolates the Y address space from the total data space. W10 and W11 are used as address pointers for reads from the Y data space. The remaining data space is referred to as X space, but could more accurately be described as “X minus Y” space. W8 and W9 are used as address pointers for data reads from the X data space in DSP class instructions. Figure 3-2 shows how the data memory map functions for both MCU class and DSP class instructions. Note that it is the W register number and type of instruction that determines how address space is accessed for data reads. In particular, MCU instructions treat the X and Y memory as a single combined data space. The MCU instructions can use any W register as an address pointer for reads and writes. The DSP instructions that can simultaneously pre-fetch two data operands, split the data memory into two spaces. Specific W registers must be used for read address pointers in this case. Some DSP instructions have the ability to store the accumulator that is not targeted by the instruction to data memory. This function is called “accumulator write back”. W13 must be used as an address pointer to the combined data memory space for accumulator write back operations. For DSP class instructions, W8 and W9 should point to implemented X memory space for all memory reads. If W8 or W9 points to Y memory space, zeros will be returned. If W8 or W9 points to an unimplemented memory address, an address error trap will be generated. For DSP class instructions, W10 and W11 should point to implemented Y memory space for all memory reads. If W10 or W11 points to implemented X memory space, all zeros will be returned. If W10 or W11 points to an unimplemented memory address, an address error trap will be generated. For additional information on address error traps, refer to Section 6. “Reset Interrupts”. Note: The data memory map and the partition between the X and Y data spaces is device specific. Refer to the specific dsPIC30F device data sheet for further details. © 2004 Microchip Technology Inc. DS70050C-page 3-3 Section 3. Data Memory Data Memory 3 Figure 3-1: Example Data Memory Map Note 1: The partition between the X and Y data spaces is device specific. Refer to the appropriate device data sheet for further details. The data space boundaries indicated here are used for example purposes only. 2: Near data memory can be accessed directly via file register instructions that encode a 13-bit address into the opcode. At a minimum, the near data memory region overlaps all of the SFR space and a portion of X memory space. All of X memory space and some or all of Y memory space may be included in the near data memory region, depending on the device variant. 3: All data memory can be accessed indirectly via W registers or directly using the MOV instruction. 4: Upper half of data memory map can be mapped into a segment of program memory space for program space visibility. 0x0000 0x07FE 0x17FE LSByte 16-bits Address MSByte LSByte MSByte Address 0x0001 0x07FF 0x17FF 0xFFFF X Data RAM 0x8001 0x8000 Provides Program Space Visibility Unimplemented 0x27FF 0x27FE 0x2801 0x2800 0x0801 0x0800 0x1801 0x1800 Near Data Memory 0x1FFF SFR Space X Data RAM Y Data RAM dsPIC30F Family Reference Manual DS70050C-page 3-4 © 2004 Microchip Technology Inc. Figure 3-2: Data Spaces for MCU and DSP Instructions 3.1.1 Near Data Memory An 8-Kbyte address space, referred to as near data memory, is reserved in the data memory space between 0x0000 and 0x1FFF. Near data memory is directly addressable via a 13-bit absolute address field within all file register instructions. The memory regions included in the near data region will depend on the amount of data memory implemented for each dsPIC30F device variant. At a minimum, the near data region will include all of the SFRs and some of the X data memory. For devices that have smaller amounts of data memory, the near data region may include all of X memory space and possibly some or all of Y memory space. Refer to Figure 3-1 for more details. (Y SPACE) X SPACE UNUSED X SPACE X SPACE UNUSED UNUSED MCU Class Instructions (Read/Write) Dual Source Operand DSP Instructions (Read) Indirect EA from W10, W11 Indirect EA from W8, W9 Note: Data writes for DSP instructions consider the entire data memory as one combined space. DSP instructions that perform an accumulator write back use W13 as an address pointer for writes to the combined data spaces. DSP Instructions (Write) Y SPACE Note: The entire 64K data space can be addressed directly using the MOV instruction. Refer to the dsPIC30F Programmer’s Reference Manual (DS70030) for further details. © 2004 Microchip Technology Inc. DS70050C-page 3-5 Section 3. Data Memory Data Memory 3 3.2 Data Space Address Generator Units (AGUs) The dsPIC30F contains an X AGU and a Y AGU for generating data memory addresses. Both X and Y AGUs can generate any effective address (EA) within a 64-Kbyte range. However, EAs that are outside the physical memory provided will return all zeros for data reads and data writes to those locations will have no effect. Furthermore, an address error trap will be generated. For more information on address error traps, refer to Section 6. “Reset Interrupts”. 3.2.1 X Address Generator Unit The X AGU is used by all instructions and supports all Addressing modes. The X AGU consists of a read AGU (X RAGU) and a write AGU (X WAGU), which operate independently on separate read and write buses during different phases of the instruction cycle. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (DSP instruction class). The X write data bus is the only write path to the combined X and Y data space for all instructions. The X RAGU starts its effective address calculation during the prior instruction cycle, using information derived from the just pre-fetched instruction. The X RAGU EA is presented to the address bus at the beginning of the instruction cycle. The X WAGU starts its effective address calculation at the beginning of the instruction cycle. The EA is presented to the address bus during the write phase of the instruction. Both the X RAGU and the X WAGU support modulo addressing. Bit-reversed addressing is supported by the X WAGU only. 3.2.2 Y Address Generator Unit The Y data memory space has one AGU that supports data reads from the Y data memory space. The Y memory bus is never used for data writes. The function of the Y AGU and Y memory bus is to support concurrent data reads for DSP class instructions. The Y AGU timing is identical to that of the X RAGU, in that its effective address calculation starts prior to the instruction cycle, using information derived from the pre-fetched instruction. The EA is presented to the address bus at the beginning of the instruction cycle. The Y AGU supports Modulo Addressing and Post-modification Addressing modes for the DSP class of instructions that use it. Note: The Y AGU does not support data writes. All data writes occur via the X WAGU to the combined X and Y data spaces. The Y AGU is only used during data reads for dual source operand DSP instructions. dsPIC30F Family Reference Manual DS70050C-page 3-6 © 2004 Microchip Technology Inc. Figure 3-3: Data Space Access Timing 3.2.3 Address Generator Units and DSP Class Instructions The Y AGU and Y memory data path are used in concert with the X RAGU by the DSP class of instructions to provide two concurrent data read paths. For example, the MAC instruction can simultaneously pre-fetch two operands to be used in the next multiplication. The DSP class of instructions dedicates two W register pointers, W8 and W9, to always operate through the X RAGU and address X data space independently from Y data space, plus two W register pointers, W10 and W11, to always operate through the Y AGU and address Y data space independently from X data space. Any data write performed by a DSP class instruction will take place in the combined X and Y data space and the write will occur across the X-bus. Consequently, the write can be to any address irrespective of where the EA is directed. The Y AGU only supports Post-modification Addressing modes associated with the DSP class of instructions. For more information on Addressing modes, please refer to the dsPIC30F Programmer’s Reference Manual. The Y AGU also supports modulo addressing for automated circular buffers. All other (MCU) class instructions can access the Y data address space through the X AGU when it is regarded as part of the composite linear space. IR X RAGU X WAGU X Data Read [W7] ADD MOV Y Address MAC SUB [W7] [W8]+=2 [--W9] ALU OP ALU OP [W10] [W9++] [W13] [W6++] Stall Check [W10]+=2 Stall Check X Address Y AGU [W7] W10 W9 W8 W13 W9-2 W6 [W8] [W9-2] X Data Write [W10] [W9] [W13] W10 Y Data (Read) [W10] ADD.W W0, [W7], [W10] MOV.W W10, [W9++] MAC W4*W5, A, W4, [W8]+=2, W5, [W10]+=2, [W13]+=2 SUB.W W4, [--W9], [W6++] During Stall Check TCY Q3 © 2004 Microchip Technology Inc. DS70050C-page 3-7 Section 3. Data Memory Data Memory 3 3.2.4 Data Alignment The ISA supports both word and byte operations for all MCU instructions that access data through the X memory AGU. The LSb of a 16-bit data address is ignored for word operations. Word data is aligned in the little-endian format with the LSByte at the even address (LSB = 0) and the MSByte at the odd address (LSB = 1). For byte operations, the LSB of the data address is used to select the byte that is accessed. The addressed byte is placed on the lower 8 bits of the internal data bus. All effective address calculations are automatically adjusted depending on whether a byte or a word access is performed. For example, an address will be incremented by 2 for a word operation that post-increments the address pointer. Figure 3-4: Data Alignment 3.3 Modulo Addressing Modulo, or circular addressing provides an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code as is typical in many DSP algorithms. Any W register, except W15, can be selected as the pointer to the modulo buffer. The modulo hardware performs boundary checks on the address held in the selected W register and automatically adjusts the pointer value at the buffer boundaries, when required. dsPIC30F modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into Program space) and Y data spaces. The modulo data buffer length can be any size up to 32K words. The modulo buffer logic supports buffers using word or byte sized data. However, the modulo logic only performs address boundary checks at word address boundaries, so the length of a byte modulo buffer must be even. In addition, byte-sized modulo buffers cannot be implemented using the Y AGU because byte access is not supported via the Y memory data bus. Note: All word accesses must be aligned to an even address (LSB = 0). Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations or translating from existing PICmicro code. Should a misaligned word read or write be attempted, an address error trap will occur. A misaligned read operation will complete, but a misaligned write will not take place. The trap will then be taken, allowing the system to examine the machine state prior to execution of the address Fault. 15 8 7 0 0001 0003 0005 0000 0002 0004 Byte 1 Byte 3 Byte 5 MSByte LSByte Word 0 Word 1 0006 0008 Long Word<15:0> 000A Long Word<31:16> 000C Byte 0 Byte 2 Byte 4 dsPIC30F Family Reference Manual DS70050C-page 3-8 © 2004 Microchip Technology Inc. 3.3.1 Modulo Start and End Address Selection Four address registers are available for specifying the modulo buffer start and end addresses: • XMODSRT: X AGU Modulo Start Address Register • XMODEND: X AGU Modulo End Address Register • YMODSRT: Y AGU Modulo Start Address Register • YMODEND: Y AGU Modulo End Address Register The start address for a modulo buffer must be located at an even byte address boundary. The LSB of the XMODSRT and YMODSRT registers is fixed at ‘0’ to ensure the correct modulo start address. The end address for a modulo buffer must be located at an odd byte address boundary. The LSB of the XMODEND and YMODEND registers is fixed to ‘1’ to ensure the correct modulo end address. The start and end address selected for each modulo buffer have certain restrictions, depending on whether an incrementing or decrementing buffer is to be implemented. For an incrementing buffer, a W register pointer is incremented through the buffer address range. When the end address of the incrementing buffer is reached, the W register pointer is reset to point to the start of the buffer. For a decrementing buffer, a W register pointer is decremented through the buffer address range. When the start address of a decrementing buffer is reached, the W register pointer is reset to point to the end of the buffer. 3.3.1.1 Modulo Start Address The data buffer start address is arbitrary, but must be at a ‘zero’ power of two boundary for incrementing modulo buffers. The modulo start address can be any value for decrementing modulo buffers and is calculated using the chosen buffer end address and buffer length. For example, if the buffer length for an incrementing buffer is chosen to be 50 words (100 bytes), then the buffer start byte address must contain 7 Least Significant zeros. Valid start addresses may, therefore, be 0xNN00 and 0xNN80, where ‘N’ is any hexadecimal value. 3.3.1.2 Modulo End Address The data buffer end address is arbitrary but must be at a ‘ones’ boundary for decrementing buffers. The modulo end address can be any value for an incrementing buffer and is calculated using the chosen buffer start address and buffer length. For example, if the buffer size (modulus value) is chosen to be 50 words (100 bytes), then the buffer end byte address for decrementing modulo buffer must contain 7 Least Significant ones. Valid end addresses may, therefore, be 0xNNFF and 0xNN7F, where ‘x’ is any hexadecimal value. Note: The user must decide whether an incrementing or decrementing modulo buffer is required for the application. There are certain address restrictions that depend on whether an incrementing or decrementing modulo buffer is to be implemented. Note: If the required modulo buffer length is an even power of 2, modulo start and end addresses can be chosen that satisfy the requirements for incrementing and decrementing buffers. © 2004 Microchip Technology Inc. DS70050C-page 3-9 Section 3. Data Memory Data Memory 3 3.3.1.3 Modulo Address Calculation The end address for an incrementing modulo buffer must be calculated from the chosen start address and the chosen buffer length in bytes. Equation 3-1 may be used to calculate the end address. Equation 3-1: Modulo End Address for Incrementing Buffer The start address for a decrementing modulo buffer is calculated from the chosen end address and the buffer length, as shown in Equation 3-2. Equation 3-2: Modulo Start Address for Decrementing Buffer 3.3.1.4 Data Dependencies Associated with Modulo Addressing SFRs A write operation to the Modulo Addressing Control register, MODCON, should not be immediately followed by an indirect read operation using any W register. The code segment shown in Example 3-1 will thus lead to unexpected results. Example 3-1: Incorrect MODCON Initialization To work around this problem of initialization, use any Addressing mode other than indirect reads in the instruction that immediately follows the initialization of MODCON. A simple work around to the problem is achieved by adding a NOP after initializing MODCON, as shown in Example 3-2. Example 3-2: Correct MODCON Initialization End Address = Start Address + Buffer Length – 1 Start Address = End Address – Buffer Length + 1 Note 1: Using a POP instruction to pop the contents of the top-of-stack (TOS) location into MODCON, also constitutes a write to MODCON. The instruction immediately following a write to MODCON cannot be any instruction performing an indirect read operation. 2: The user should note that some instructions perform an indirect read operation, implicitly. These are: POP, RETURN, RETFIE, RETLW and ULNK. MOV #0x8FF4, w0 ;Initialize MODCON MOV w0, MODCON MOV [w1], w2 ;Incorrect EA generated here MOV #0x8FF4, w0 ;Initialize MODCON MOV w0, MODCON NOP ;See Note below MOV [w1], w2 ;Correct EA generated here dsPIC30F Family Reference Manual DS70050C-page 3-10 © 2004 Microchip Technology Inc. An additional condition exists for indirect read operations performed immediately after writing to the modulo address SFRs: • XMODSRT • XMODEND • YMODSRT • YMODEND If modulo addressing has already been enabled in MODCON, then a write to the X (or Y) modulo address SFRs should not be immediately followed by an indirect read, using the W register designated for modulo buffer access from X-data space (or Y-data space). The code segment in Example 3-3 shows how initializing the modulo SFRs associated with the X-data space, could lead to unexpected results. A similar example can be made for initialization in Y-data space. Example 3-3: Incorrect Modulo Addressing Setup To work around this issue, insert a NOP, or perform any operation other than an indirect read that uses the W register designated for modulo buffer access, after initializing the modulo address SFRs. This is demonstrated in Example 3-4. Another alternative would be to enable modulo addressing in MODCON after initializing the modulo start and end address SFRs. Example 3-4: Correct Modulo Addressing Setup MOV #0x8FF4, w0 ;Modulo addressing enabled MOV w0, MODCON ;in X-data space using w4 ;for buffer access MOV #0x1200, w4 ;XMODSRT is initialized MOV w4, XMODSRT MOV #0x12FF, w0 ;XMODEND is initialized MOV w0, XMODEND MOV [w4++], w5 ;Incorrect EA generated MOV #0x8FF4, w0 ;Modulo addressing enabled MOV w0, MODCON ;in X-data space using w4 ;for buffer access MOV #0x1200, w4 ;XMODSRT is initialized MOV w4, XMODSRT MOV #0x12FF, w0 ;XMODEND is initialized MOV w0, XMODEND NOP ;See Note below MOV [w4++], w5 ;Correct EA generated here Note: Alternatively, execute other instructions that do not perform indirect read operations, using the W register designated for modulo buffer access. © 2004 Microchip Technology Inc. DS70050C-page 3-11 Section 3. Data Memory Data Memory 3 3.3.2 W Address Register Selection The X address space pointer W register (XWM) to which modulo addressing is to be applied, is stored in MODCON<3:0> (see Register 3-1). The XMODSRT, XMODEND, and the XWM register selection are shared between the X RAGU and X WAGU. Modulo addressing is enabled for X data space when XWM is set to any value other than 15 and the XMODEN bit is set (MODCON<15>). W15 cannot be used as the pointer for modulo addressing because it is the dedicated software stack pointer. The Y address space pointer W register (YWM) to which modulo addressing is to be applied, is stored in MODCON<7:4> (see Register 3-2). Modulo addressing is enabled for Y data space when YWM is set to any value other than 15 and the YMODEN bit is set (MODCON<14>). 3.3.3 Modulo Addressing Applicability Modulo addressing can be applied to the effective address (EA) calculation associated with the selected W register. It is important to realize that the address boundary tests look for addresses equal to or greater than the upper address boundary for incrementing buffers and equal to or less than the lower address boundary for decrementing buffers. Address changes may, therefore, jump over boundaries and still be adjusted correctly. Remember that the automatic adjustment of the W register pointer by the modulo hardware is uni-directional. That is, the W register pointer may not be adjusted correctly by the modulo hardware when the W register pointer for an incrementing buffer is decremented and vice versa. The exception to this rule is when the buffer length is an even power of 2 and the start and end addresses can be chosen to meet the -boundary requirements for both incrementing and decrementing modulo buffers. A new EA can exceed the modulo buffer boundary by up to the length of the buffer and still be successfully corrected. This is important to remember when the Register Indexed ([Wb + Wn]) and Literal Offset ([Wn + lit10]) Addressing modes are used. The user should remember that the Register Indexed and Literal Offset Addressing modes do not change the value held in the W register. Only the indirect with Pre- and Post-modification Addressing modes ([Wn++], [Wn--], [++Wn], [--Wn]) will modify the W register address value. Note: A write to the MODCON register should not be followed by an instruction that performs an indirect read operation using a W register. Unexpected results may occur. Some instructions perform an implicit indirect read. These are:POP, RETURN, RETFIE, RETLW and ULNK. dsPIC30F Family Reference Manual DS70050C-page 3-12 © 2004 Microchip Technology Inc. 3.3.4 Modulo Addressing Initialization for Incrementing Modulo Buffer The following steps describe the setup procedure for an incrementing circular buffer. The steps are similar whether the X AGU or Y AGU is used. 1. Determine the buffer length in 16-bit data words. Multiply this value by 2 to get the length of the buffer in bytes. 2. Select a buffer starting address that is located at a binary ‘zeros’ boundary based on the desired length of the buffer. Remember that the buffer length in words must be multiplied by 2 to obtain the byte address range. For example, a buffer with a length of 100 words (200 bytes) could use 0xXX00 as the starting address. 3. Calculate the buffer end address using the buffer length chosen in Step 1 and the buffer start address chosen in Step 2. The buffer end address is calculated using Equation 3-1. 4. Load the XMODSRT (YMODSRT) register with the buffer start address chosen in Step 2. 5. Load the XMODEND (YMODEND) register with the buffer end address calculated in Step 3. 6. Write to the XWM<3:0> (YWM<3:0>) bits in the MODCON register to select the W register that will be used to access the circular buffer. 7. Set the XMODEN (YMODEN) bit in the MODCON register to enable the circular buffer. 8. Load the selected W register with address that points to the buffer. 9. The W register address will be adjusted automatically at the end of the buffer when an indirect access with pre/post increment is performed (see Figure 3-5). Figure 3-5: Incrementing Buffer Modulo Addressing Operation Example 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 50 Words Byte Address MOV #0x1100,W0 MOV W0,XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,XMODEND ;set modulo end address MOV #0x8001,W0 MOV W0,MODCON ;enable W1, X AGU for modulo MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x1100,W1 ;point W1 to buffer DO #49,FILL ;fill the 50 buffer locations FILL: MOV W0,[W1++] ;fill the next location ;W1 = 0x1100 when DO loop completes © 2004 Microchip Technology Inc. DS70050C-page 3-13 Section 3. Data Memory Data Memory 3 3.3.5 Modulo Addressing Initialization for Decrementing Modulo Buffer The following steps describe the setup procedure for a decrementing circular buffer. The steps are similar whether the X AGU or Y AGU is used. 1. Determine the buffer length in 16-bit data words. Multiply this value by 2 to get the length of the buffer in bytes. 2. Select a buffer end address that is located at a binary ‘ones’ boundary, based on the desired length of the buffer. Remember that the buffer length in words must be multiplied by 2 to obtain the byte address range. For example, a buffer with a length of 128 words (256 bytes) could use 0xXXFF as the end address. 3. Calculate the buffer start address using the buffer length chosen in Step 1 and the end address chosen in Step 2. The buffer start address is calculated using Equation 3-2. 4. Load the XMODSRT (YMODSRT) register with the buffer start address chosen in Step 3. 5. Load the XMODEND (YMODEND) register with the buffer end address chosen in Step 2. 6. Write to the XWM<3:0> (YWM<3:0>) bits in the MODCON register to select the W register that will be used to access the circular buffer. 7. Set the XMODEN (YMODEN) bit in the MODCON register to enable the circular buffer. 8. Load the selected W register with address that points to the buffer. 9. The W register address will be adjusted automatically at the end of the buffer when an indirect access with pre/post-decrement is performed (see Figure 3-6). Figure 3-6: Decrementing Buffer Modulo Addressing Operation Example 0x11E0 0x11FF Start Addr = 0x11E0 End Addr = 0x11FF Length = 16 Words Byte Address MOV #0x11E0,W0 MOV W0,XMODSRT ;set modulo start address MOV #0x11FF,W0 MOV W0,XMODEND ;set modulo end address MOV #0x8001,W0 MOV W0,MODCON ;enable W1, X AGU for modulo MOV #0x000F,W0 ;W0 holds buffer fill value MOV #0x11FE,W1 ;point W1 to buffer DO #15,FILL ;fill the 16 buffer locations MOV W0,[W1--] ;fill the next location FILL: DEC W0,W0 ;decrement the fill value ; W1 = 0x11FE when DO loop completes dsPIC30F Family Reference Manual DS70050C-page 3-14 © 2004 Microchip Technology Inc. 3.4 Bit-Reversed Addressing 3.4.1 Introduction to Bit-Reversed Addressing Bit-reversed addressing simplifies data re-ordering for radix-2 FFT algorithms. It is supported through the X WAGU only. Bit-reversed addressing is accomplished by effectively creating a ‘mirror image’ of an address pointer by swapping the bit locations around the center point of the binary value, as shown in Figure 3-7. An example bit-reversed sequence for a 4-bit address field is shown in Table 3-1. Figure 3-7: Bit-Reversed Address Example Table 3-1: Bit-Reversed Address Sequence (16-Entry) b3 b2 b1 b0 b0 b1 b2 b3 Bit locations swapped left-to-right around center of binary value. Bit-Reversed Result Normal Address Bit-Reversed Address A3 A2 A1 A0 decimal A3 A2 A1 A0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0 0 1 1 3 1 1 0 0 12 0100 4 0010 2 0 1 0 1 5 1 0 1 0 10 0110 6 0110 6 0 1 1 1 7 1 1 1 0 14 1000 8 0001 1 1001 9 1001 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 © 2004 Microchip Technology Inc. DS70050C-page 3-15 Section 3. Data Memory Data Memory 3 3.4.2 Bit-Reversed Addressing Operation Bit-reversed addressing is only supported by the X WAGU and is controlled by the MODCON and XBREV special function registers. Bit-reversed addressing is invoked as follows: 1. Bit-reversed addressing is assigned to one of the W registers using the BWM control bits (MODCON<11:8>). 2. Bit-reversed addressing is enabled by setting the BREN control bit (XBREV<15>). 3. The X AGU bit-reverse modifier is set via the XB control bits (XBREV<14:0>). When enabled, the bit-reversed addressing hardware will generate bit-reversed addresses, only when the register indirect with Pre- or Post-increment Addressing modes are used ([Wn++], [++Wn]). Furthermore, bit-reverse addresses are only generated for Word mode instructions. It will not function for all other Addressing modes or Byte mode instructions (normal addresses will be generated). 3.4.2.1 Modulo Addressing and Bit-Reversed Addressing Modulo addressing and bit-reversed addressing can be enabled simultaneously using the same W register, but bit-reversed addressing operation will always take precedence for data writes when enabled. As an example, the following setup conditions would assign the same W register to modulo and bit-reversed addressing: • X modulo addressing is enabled (XMODEN = 1) • Bit-reverse addressing is enabled (BREN = 1) • W1 assigned to modulo addressing (XWM<3:0> = 0001) • W1 assigned to bit-reversed addressing (BWM<3:0> = 0001) For data reads that use W1 as the pointer, modulo address boundary checking will occur. For data writes using W1 as the destination pointer, the bit-reverse hardware will correct W1 for data re-ordering. 3.4.2.2 Data Dependencies Associated with XBREV If bit-reversed addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to the XBREV register should not be followed by an indirect read operation using the W register, designated as the bit reversed address pointer. Note: A write to the MODCON register should not be followed by an instruction that performs an indirect read operation using a W register. Unexpected results may occur. Some instructions perform an implicit indirect read. These are: POP, RETURN, RETFIE, RETLW and ULNK. dsPIC30F Family Reference Manual DS70050C-page 3-16 © 2004 Microchip Technology Inc. 3.4.3 Bit-Reverse Modifier Value The value loaded into the XBREV register is a constant that indirectly defines the size of the bit-reversed data buffer. The XB modifier values used with common bit-reversed buffers are summarized in Table 3-2. Table 3-2: Bit-Reversed Address Modifier Values The bit-reverse hardware modifies the W register address by performing a ‘reverse-carry’ addition of the W contents and the XB modifier constant. A reverse-carry addition is performed by adding the bits from left-to-right instead of right-to-left. If a carry-out occurs in a bit location, the carry out bit is added to the next bit location to the right. Example 3-5 demonstrates the reverse-carry addition and subsequent W register values using 0x0008 as the XB modifier value. Note that the XB modifier is shifted one bit location to the left to generate word address values. Buffer Size (Words) XB Bit-Reversed Address Modifier Value 32768 0x4000 16384 0x2000 8192 0x1000 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 Note: Only the the bit-reversed modifier values shown will produce valid bit-reversed address sequences. © 2004 Microchip Technology Inc. DS70050C-page 3-17 Section 3. Data Memory Data Memory 3 Example 3-5: XB Address Calculation When XB<14:0> = 0x0008, the bit-reversed buffer size will be 16 words. Bits 1-4 of the W register will be subject to bit-reversed address correction, but bits 5-15 (outside the pivot point) will not be modified by the bit-reverse hardware. Bit 0 is not modified because the bit-reverse hardware only operates on word addresses. The XB modifier controls the ‘pivot point’ for the bit-reverse address modification. Bits outside of the pivot point will not be subject to bit-reversed address corrections. Figure 3-8: Bit-Reversed Address Modification for 16-Word Buffer 0000 0000 0000 0000 Wn points to word 0 +1 0000 Wn = Wn + XB 0000 0000 0001 0000 Wn points to word 8 +1 0000 Wn = Wn + XB 0000 0000 0000 1000 Wn points to word 4 +1 0000 Wn = Wn + XB 0000 0000 0001 1000 Wn points to word 12 +1 0000 Wn = Wn + XB 0000 0000 0000 0100 Wn points to word 2 +1 0000 Wn = Wn + XB 0000 0000 0001 0100 Wn points to word 10 Bit-Reversed Result 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XB<14:0> = 0x0008 Bits 1-4 of address Pivot Point are modified. dsPIC30F Family Reference Manual DS70050C-page 3-18 © 2004 Microchip Technology Inc. 3.4.4 Bit-Reversed Addressing Code Example The following code example reads a series of 16 data words and writes the data to a new location in bit-reversed order. W0 is the read address pointer and W1 is the write address pointer subject to bit-reverse modification. ; Set XB for 16-word buffer, enable bit reverse addressing MOV #0x8008,W0 MOV W0,XBREV ; Setup MODCON to use W1 for bit reverse addressing MOV #0x01FF,W0 MOV W0,MODCON ; W0 points to input data buffer MOV #Input_Buf,W0 ; W1 points to bit reversed data MOV #Bit_Rev_Buf,W1 ; Re-order the data from Input_Buf into Bit_Rev_Buf REPEAT #15 MOV [W0++],[W1++] 3.5 Control Register Descriptions The following registers are used to control modulo and bit-reversed addressing: • MODCON: Modulo Addressing Control Register • XMODSRT: X AGU Modulo Start Address Register • XMODEND: X AGU Modulo End Address Register • YMODSRT: Y AGU Modulo Start Address Register • YMODEND: Y AGU Modulo End Address Register • XBREV: X AGU Bit-Reverse Addressing Control Register A detailed description of each register is provided on subsequent pages. © 2004 Microchip Technology Inc. DS70050C-page 3-19 Section 3. Data Memory Data Memory 3 Register 3-1: MODCON: Modulo and Bit-Reversed Addressing Control Register Upper Byte: R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 XMODEN YMODEN — — BWM<3:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 YWM<3:0> XWM<3:0> bit 7 bit 0 bit 15 XMODEN: X RAGU and X WAGU Modulus Addressing Enable bit 1 = X AGU modulus addressing enabled 0 = X AGU modulus addressing disabled bit 14 YMODEN: Y AGU Modulus Addressing Enable bit 1 = Y AGU modulus addressing enabled 0 = Y AGU modulus addressing disabled bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 BWM<3:0>: X WAGU Register Select for Bit-Reversed Addressing bits 1111 = Bit-reversed addressing disabled 1110 = W14 selected for bit-reversed addressing 1101 = W13 selected for bit-reversed addressing • • 0000 = W0 selected for bit-reversed addressing bit 7-4 YWM<3:0>: Y AGU W Register Select for Modulo Addressing bits 1111 = Modulo addressing disabled 1010 = W10 selected for modulo addressing 1011 = W11 selected for modulo addressing Note: All other settings of the YWM<3:0> control bits are reserved and should not be used. bit 3-0 XWM<3:0>: X RAGU and X WAGU W Register Select for Modulo Addressing bits 1111 = Modulo addressing disabled 1110 = W14 selected for modulo addressing • • 0000 = W0 selected for modulo addressing Note: A write to the MODCON register should not be followed by an instruction that performs an indirect read operation using a W register. Unexpected results may occur. Some instructions perform an implicit indirect read. These are: POP, RETURN, RETFIE, RETLW and ULNK. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70050C-page 3-20 © 2004 Microchip Technology Inc. Register 3-2: XMODSRT: X AGU Modulo Addressing Start Register Register 3-3: XMODEND: X AGU Modulo Addressing End Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 XS<15:8> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 XS<7:1> 0 bit 7 bit 0 bit 15-1 XS<15:1>: X RAGU and X WAGU Modulo Addressing Start Address bits bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 XE<15:8> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 XE<7:1> 1 bit 7 bit 0 bit 15-1 XE<15:1>: X RAGU and X WAGU Modulo Addressing End Address bits bit 0 Unimplemented: Read as ‘1’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70050C-page 3-21 Section 3. Data Memory Data Memory 3 Register 3-4: YMODSRT: Y AGU Modulo Addressing Start Register Register 3-5: YMODEND: Y AGU Modulo Addressing End Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 YS<15:8> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 YS<7:1> 0 bit 7 bit 0 bit 15-1 YS<15:1>: Y AGU Modulo Addressing Start Address bits bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 YE<15:8> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 YE<7:1> 1 bit 7 bit 0 bit 15-1 YE<15:1>: Y AGU Modulo Addressing End Address bits bit 0 Unimplemented: Read as ‘1’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70050C-page 3-22 © 2004 Microchip Technology Inc. Register 3-6: XBREV: X Write AGU Bit-Reversal Addressing Control Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BREN XB<14:8> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 XB<7:0> bit 7 bit 0 bit 15 BREN: Bit-Reversed Addressing (X AGU) Enable bit 1 = Bit-reversed addressing enabled 0 = Bit-reversed addressing disabled bit 14-0 XB<14:0>: X AGU Bit-Reversed Modifier bits 0x4000 = 32768 word buffer 0x2000 = 16384 word buffer 0x1000 = 8192 word buffer 0x0800 = 4096 word buffer 0x0400 = 2048 word buffer 0x0200 = 1024 word buffer 0x0100 = 512 word buffer 0x0080 = 256 word buffer 0x0040 = 128 word buffer 0x0020 = 64 word buffer 0x0010 = 32 word buffer 0x0008 = 16 word buffer 0x0004 = 8 word buffer 0x0002 = 4 word buffer 0x0001 = 2 word buffer Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70050C-page 3-23 Section 3. Data Memory Data Memory 3 3.6 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Data Memory module are: Title Application Note # No related application notes at this time. Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. dsPIC30F Family Reference Manual DS70050C-page 3-24 © 2004 Microchip Technology Inc. 3.7 Revision History Revision A This is the initial released revision of this document. Revision B This revision incorporates additional technical content for the dsPIC30F Data Memory module. Revision C This revision incorporates all known errata at the time of this document update. © 2005 Microchip Technology Inc. DS70051D-page 4-1 P r o g r a m Memory 4 Section 4. Program Memory HIGHLIGHTS This section of the manual contains the following topics: 4.1 Program Memory Address Map..................................................................................... 4-2 4.2 Program Counter ........................................................................................................... 4-4 4.3 Data Access from Program Memory.............................................................................. 4-4 4.4 Program Space Visibility from Data Space .................................................................... 4-8 4.5 Program Memory Writes .............................................................................................. 4-10 4.6 PSV Code Examples ................................................................................................... 4-11 4.7 Related Application Notes............................................................................................4-12 4.8 Revision History ........................................................................................................... 4-13 dsPIC30F Family Reference Manual DS70051D-page 4-2 © 2005 Microchip Technology Inc. 4.1 Program Memory Address Map The dsPIC30F devices have a 4M x 24-bit program memory address space, shown in Figure 4-1. There are three available methods for accessing program space. 1. Via the 23-bit PC. 2. Via table read (TBLRD) and table write (TBLWT) instructions. 3. By mapping a 32-Kbyte segment of program memory into the data memory address space. The program memory map is divided into the user program space and the user configuration space. The user program space contains the Reset vector, interrupt vector tables, program memory and data EEPROM memory. The user configuration space contains non-volatile configuration bits for setting device options and the device ID locations. © 2005 Microchip Technology Inc. DS70051D-page 4-3 Section 4. Program Memory P r o g r a m Memory 4 Figure 4-1: Example Program Space Memory Map Note: The address boundaries for user Flash program memory and data EEPROM memory will depend on the dsPIC30F device variant that is selected. Refer to the appropriate device data sheet for further details. Reset - Target Address User Memory Space 000000 00007E Level 15 Trap Vector 000002 000080 Device Configuration User Flash Program Memory 018000 017FFE Configuration Memory Space Data EEPROM Level 14 Trap Vector Level 13 Trap Vector Level 12 Trap Vector Level 11 Trap Vector Level 10 Trap Vector Level 9 Trap Vector Level 8 Trap Vector Interrupt 0 Vector Interrupt 1 Vector Interrupt 52 Vector Interrupt 53 Vector (48K Instructions) (4 Kbytes) 800000 F80000 Registers F8000E F80010 DEVID (2) FEFFFE FF0000 FFFFFE Reserved F7FFFE Reserved 7FF000 7FEFFE (Read 0’s) 8005FE 800600 UNITID 000014 Interrupt Vector Table 8005BE 8005C0 Reset - GOTO Instruction 000004 Reserved 7FFFFE Reserved 000100 0000FE 000084 Reserved Level 15 Trap Vector Level 14 Trap Vector Level 13 Trap Vector Level 12 Trap Vector Level 11 Trap Vector Level 10 Trap Vector Level 9 Trap Vector Level 8 Trap Vector Interrupt 0 Vector Interrupt 1 Vector Interrupt 52 Vector Interrupt 53 Vector 000082 Alternate Interrupt Vector Table dsPIC30F Family Reference Manual DS70051D-page 4-4 © 2005 Microchip Technology Inc. 4.2 Program Counter The PC increments by 2 with the LSb set to ‘0’ to provide compatibility with data space addressing. Sequential instruction words are addressed in the 4M program memory space by PC<22:1>. Each instruction word is 24-bits wide. The LSb of the program memory address (PC<0>) is reserved as a byte select bit for program memory accesses from data space that use Program Space Visibility or table instructions. For instruction fetches via the PC, the byte select bit is not required. Therefore, PC<0> is always set to ‘0’. An instruction fetch example is shown in Figure 4-2. Note that incrementing PC<22:1> by one is equivalent to adding 2 to PC<22:0>. Figure 4-2: Instruction Fetch Example 4.3 Data Access from Program Memory There are two methods by which data can be transferred between the program memory and data memory spaces: via special table instructions, or through the remapping of a 32-Kbyte program space page into the upper half of data space. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the LSWord of any address within program space without going through data space, which is preferable for some applications. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8-bits of a program word can be accessed as data. 22 0 Program Counter 0 0x000000 0x7FFFFE 24-bits Instruction Instruction 23 +1(1) Note 1: Increment of PC<22:1> is equivalent to PC<22:0>+2. 24 23 User Space Latch © 2005 Microchip Technology Inc. DS70051D-page 4-5 Section 4. Program Memory P r o g r a m Memory 4 4.3.1 Table Instruction Summary A set of table instructions is provided to move byte or word-sized data between program space and data space. The table read instructions are used to read from the program memory space into data memory space. The table write instructions allow data memory to be written to the program memory space. The four available table instructions are listed below: • TBLRDL: Table Read Low • TBLWTL: Table Write Low • TBLRDH: Table Read High • TBLWTH: Table Write High For table instructions, program memory can be regarded as two 16-bit word wide address spaces residing side by side, each with the same address range as shown in Figure 4-3. This allows program space to be accessed as byte or aligned word addressable, 16-bit wide, 64-Kbyte pages (i.e., same as data space). TBLRDL and TBLWTL access the LS Data Word of the program memory, and TBLRDH and TBLWTH access the upper word. As program memory is only 24-bits wide, the upper byte from this latter space does not exist, though it is addressable. It is, therefore, termed the ‘phantom’ byte. Figure 4-3: High and Low Address Regions for Table Operations Note: Detailed code examples using table instructions can be found in Section 5. “Flash and EEPROM Programming”. 16 8 0 PC Address 0x000100 0x000102 0x000104 0x000106 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) ‘HIGH’ Table Address Range ‘LOW’ Table Address Range dsPIC30F Family Reference Manual DS70051D-page 4-6 © 2005 Microchip Technology Inc. 4.3.2 Table Address Generation For all table instructions, a W register address value is concatenated with the 8-bit Data Table Page register, TBLPAG, to form a 23-bit effective program space address plus a byte select bit, as shown in Figure 4-4. As there are 15 bits of program space address provided from the W register, the data table page size in program memory is, therefore, 32K words. Figure 4-4: Address Generation for Table Operations 4.3.3 Program Memory Low Word Access The TBLRDL and TBLWTL instructions are used to access the lower 16 bits of program memory data. The LSb of the W register address is ignored for word-wide table accesses. For byte-wide accesses, the LSb of the W register address determines which byte is read. Figure 4-5 demonstrates the program memory data regions accessed by the TBLRDL and TBLWTL instructions. Figure 4-5: Program Data Table Access (LSWord) TBLPAG 8 bits from TBLPAG EA EA<0> Selects Byte 24-bit EA TBLPAG<7> Selects User/Configuration Space 7 0 15 0 16 bits from Wn 16 8 0 PC Address 0x000100 0x000102 0x000104 0x000106 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) TBLRDL.W TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) © 2005 Microchip Technology Inc. DS70051D-page 4-7 Section 4. Program Memory P r o g r a m Memory 4 4.3.4 Program Memory High Word Access The TBLRDH and TBLWTH instructions are used to access the upper 8 bits of the program memory data. These instructions also support Word or Byte Access modes for orthogonality, but the high byte of the program memory data will always return ‘0’, as shown in Figure 4-6. Figure 4-6: Program Data Table Access (MS Byte) 4.3.5 Data Storage in Program Memory It is assumed that for most applications, the high byte (P<23:16>) will not be used for data, making the program memory appear 16-bits wide for data storage. It is recommended that the upper byte of program data be programmed either as a NOP, or as an illegal opcode value, to protect the device from accidental execution of stored data. The TBLRDH and TBLWTH instructions are primarily provided for array program/verification purposes and for those applications that require compressed data storage. 16 8 0 PC Address 0x000100 0x000102 0x000104 0x000106 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) TBLRDH.W TBLRDH.B (Wn<0> = 1) TBLRDH.B (Wn<0> = 0) dsPIC30F Family Reference Manual DS70051D-page 4-8 © 2005 Microchip Technology Inc. 4.4 Program Space Visibility from Data Space The upper 32 Kbytes of the dsPIC30F data memory address space may optionally be mapped into any 16K word program space page. This mode of operation is called Program Space Visibility (PSV) and provides transparent access of stored constant data from X data space without the need to use special instructions (i.e., TBLRD, TBLWT instructions). 4.4.1 PSV Configuration Program Space Visibility is enabled by setting the PSV bit (CORCON<2>). A description of the CORCON register can be found in Section 2. “CPU”. When PSV is enabled, each data space address in the upper half of the data memory map will map directly into a program address (see Figure 4-7). The PSV window allows access to the lower 16 bits of the 24-bit program word. The upper 8 bits of the program memory data should be programmed to force an illegal instruction, or a NOP, to maintain machine robustness. Note that table instructions provide the only method of reading the upper 8 bits of each program memory word. Figure 4-8 shows how the PSV address is generated. The 15 LSbs of the PSV address are provided by the W register that contains the effective address. The MSb of the W register is not used to form the address. Instead, the MSb specifies whether to perform a PSV access from program space or a normal access from data memory space. If a W register effective address of 0x8000 or greater is used, the data access will occur from program memory space when PSV is enabled. All accesses will occur from data memory when the W register effective address is less than 0x8000. The remaining address bits are provided by the PSVPAG register (PSVPAG<7:0>), as shown in Figure 4-8. The PSVPAG bits are concatenated with the 15 LSbs of the W register, holding the effective address to form a 23-bit program memory address. PSV can only be used to access values in program memory space. Table instructions must be used to access values in the user configuration space. The LSb of the W register value is used as a byte select bit, which allows instructions using PSV to operate in Byte or Word mode. 4.4.2 PSV Mapping with X and Y Data Spaces The Y data space is located outside of the upper half of data space for most dsPIC30F variants, such that the PSV area will map into X data space. The X and Y mapping will have an effect on how PSV is used in algorithms. As an example, the PSV mapping can be used to store coefficient data for Finite Impulse Response (FIR) filter algorithms. The FIR filter multiplies each value of a data buffer containing historical filter input data with elements of a data buffer that contains constant filter coefficients. The FIR algorithm is executed using the MAC instruction within a REPEAT loop. Each iteration of the MAC instruction pre-fetches one historical input value and one coefficient value to be multiplied in the next iteration. One of the pre-fetched values must be located in X data memory space and the other must be located in Y data memory space. To satisfy the PSV mapping requirements for the FIR filter algorithm, the user must locate the historical input data in the Y memory space and the filter coefficients in X memory space. © 2005 Microchip Technology Inc. DS70051D-page 4-9 Section 4. Program Memory P r o g r a m Memory 4 Figure 4-7: Program Space Visibility Operation Figure 4-8: Program Space Visibility Address Generation 23 15 0 PSVPAG EA<15> = 1 Data Space Program Space 8 15 23 0x0000 0x8000 0xFFFF 0x01 0x008000 Data Read Upper 8 bits of Program Memory Data cannot be read using Program Space Visibility. 0x000100 0x017FFF 23 bits 1 PSVPAG Reg 8 bits Wn 15 bits Select 23-bit EA Wn<0> is Byte Select dsPIC30F Family Reference Manual DS70051D-page 4-10 © 2005 Microchip Technology Inc. 4.4.3 PSV Timing Instructions that use PSV will require two extra instruction cycles to complete execution, except the following instructions that require only one extra cycle to complete execution: - The MAC class of instructions with data pre-fetch operands - All MOV instructions including the MOV.D instruction The additional instruction cycles are used to fetch the PSV data on the program memory bus. 4.4.3.1 Using PSV in a Repeat Loop Instructions that use PSV within a REPEAT loop eliminate the extra instruction cycle(s) required for the data access from program memory, hence incurring no overhead in execution time. However, the following iterations of the REPEAT loop will incur an overhead of two instruction cycles to complete execution: - The first iteration - The last iteration - Instruction execution prior to exiting the loop due to an interrupt - Instruction execution upon re-entering the loop after an interrupt is serviced 4.4.3.2 PSV and Instruction Stalls Refer to Section 2. “CPU” for more information about instruction stalls using PSV. 4.5 Program Memory Writes The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are two methods by which the user can program this memory: 1. Run-Time Self Programming (RTSP) 2. In-Circuit Serial Programming™ (ICSP™) RTSP is accomplished using TBLWT instructions. ICSP is accomplished using the SPI interface and integral bootloader software. Refer to Section 5. “Flash and EEPROM Programming” for further details about RTSP. ICSP specifications can be downloaded from the Microchip Technology web site (www.microchip.com). © 2005 Microchip Technology Inc. DS70051D-page 4-11 Section 4. Program Memory P r o g r a m Memory 4 4.6 PSV Code Examples 4.6.1 PSV Code Example in C: // PSV code example in C // When defined as below the const string uses the PSV feature of dsPIC const unsigned char hello[] = {"Hello World:\r\n"}; unsigned char *TXPtr; // Transmit pointer int main(void) { // Initialize the UART1 U1MODE = 0x8000; U1STA = 0x0000; U1BRG = ((FCY/16)/BAUD) - 1; // set baud rate = BAUD TXPtr = &hello[0]; // point to first char in string U1STAbits.UTXEN = 1; // Initiate transmission while (1) { while (*TXPtr) // while valid char in string ... if (!U1STAbits.UTXBF) // and buffer not full ... U1TXREG = *TXPtr++; // transmit string via UART DelayNmSec(500); // delay for 500 mS TXPtr = &hello[0]; // re-initialize pointer to first char } } // end main 4.6.2 PSV code Example in Assembly: .equ CORCONL, CORCON .section .const, "r" hello: .ascii "Hello World:\n\r\0" .global __reset ;Declare the label for the start of code .text ;Start of Code section __reset: clr U1STA mov #0x8000,W0 ; enable UART module mov W0,U1MODE mov #BR,W0 ; set baudrate using formula value mov W0, U1BRG ; / bset U1STA,#UTXEN ; initiate transmission Again: rcall Delay500mSec ; delay for 500 mS mov #psvpage(hello),w0 mov w0, PSVPAG bset.b CORCONL,#PSV mov #psvoffset(hello),w0 TxSend: mov.b [w0++], w1 ; get char in string cp w1,#0 ; if Null bra Z,Again ; then re-initialize BufferTest: btsc U1STA,#UTXBF ; see if buffer full bra BufferTest ; wait till empty mov w1,U1TXREG ; load value in TX buffer bra TxSend ; repeat for next char. dsPIC30F Family Reference Manual DS70051D-page 4-12 © 2005 Microchip Technology Inc. 4.7 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Program Memory module are: Title Application Note # No related application notes at this time. Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. © 2005 Microchip Technology Inc. DS70051D-page 4-13 Section 4. Program Memory P r o g r a m Memory 4 4.8 Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual. Revision C This revision incorporates all known errata at the time of this document update. Revision D Section 4.6 “PSV Code Examples”, has been added. dsPIC30F Family Reference Manual DS70051D-page 4-14 © 2005 Microchip Technology Inc. NOTES: © 2005 Microchip Technology Inc. DS70052D-page 5-1 Fla s h a n d E E P R O M Programming 5 Section 5. Flash and EEPROM Programming HIGHLIGHTS This section of the manual contains the following topics: 5.1 Introduction .................................................................................................................... 5-2 5.2 Table Instruction Operation............................................................................................ 5-2 5.3 Control Registers ........................................................................................................... 5-5 5.4 Run-Time Self-Programming (RTSP) .......................................................................... 5-10 5.5 Data EEPROM Programming ...................................................................................... 5-15 5.6 Design Tips .................................................................................................................. 5-21 5.7 Related Application Notes............................................................................................5-22 5.8 Revision History ........................................................................................................... 5-23 dsPIC30F Family Reference Manual DS70052D-page 5-2 © 2005 Microchip Technology Inc. 5.1 Introduction This section describes programming techniques for Flash program memory and data EEPROM memory. The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are two methods by which the user can program this memory: 1. Run-Time Self Programming (RTSP) 2. In-Circuit Serial Programming™ (ICSP™) RTSP is performed by the user’s software. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. RTSP techniques are described in this chapter. The ICSP protocol is described in the dsPIC30F Programming Specification document, which may be downloaded from the Microchip web site. The data EEPROM is mapped into the program memory space. The EEPROM is organized as 16-bit wide memory and the memory size can be up to 2K words (4 Kbytes). The amount of EEPROM is device dependent. Refer to the device data sheet for further information. The programming techniques used for the data EEPROM are similar to those used for Flash program memory RTSP. The key difference between Flash and data EEPROM programming operations is the amount of data that can be programmed or erased during each program/erase cycle. 5.2 Table Instruction Operation The table instructions provide one method of transferring data between the program memory space and the data memory space of dsPIC30F devices. A summary of the table instructions is provided here since they are used during programming of the Flash program memory and data EEPROM. There are four basic table instructions: • TBLRDL: Table Read Low • TBLRDH: Table Read High • TBLWTL: Table Write Low • TBLWTH: Table Write High The TBLRDL and the TBLWTL instructions are used to read and write to bits <15:0> of program memory space. TBLRDL and TBLWTL can access program memory in Word or Byte mode. The TBLRDH and TBLWTH instructions are used to read or write to bits <23:16> of program memory space. TBLRDH and TBLWTH can access program memory in Word or Byte mode. Since the program memory is only 24-bits wide, the TBLRDH and TBLWTH instructions have the ability to address an upper byte of program memory that does not exist. This byte is called the ‘phantom byte’. Any read of the phantom byte will return 0x00 and a write to the phantom byte has no effect. Always remember that the 24-bit program memory can be regarded as two side-by-side 16-bit spaces, with each space sharing the same address range. Therefore, the TBLRDL and TBLWTL instructions access the ‘low’ program memory space (PM<15:0>). The TBLRDH and TBLWTH instructions access the ‘high’ program memory space (PM<31:16>). Any reads or writes to PM<31:24> will access the phantom (unimplemented) byte. When any of the table instructions are used in Byte mode, the LSb of the table address will be used as the byte select bit. The LSb determines which byte in the high or low program memory space is accessed. Figure 5-1 shows how the program memory is addressed using the table instructions. A 24-bit program memory address is formed using bits <7:0> of the TBLPAG register and the effective address (EA) from a W register, specified in the table instruction. The 24-bit program counter is shown in Figure 5-1 for reference. The upper 23 bits of the EA are used to select the program memory location. For the Byte mode table instructions, the LSb of the W register EA is used to pick which byte of the 16-bit program memory word is addressed. A ‘1’ selects bits <15:8>, a ‘0’ selects bits <7:0>. The LSb of the W register EA is ignored for a table instruction in Word mode. In addition to the program memory address, the table instruction also specifies a W register (or a W register pointer to a memory location) that is the source of the program memory data to be written, or the destination for a program memory read. For a table write operation in Byte mode, bits <15:8> of the source working register are ignored. © 2005 Microchip Technology Inc. DS70052D-page 5-3 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 Figure 5-1: Addressing for Table Instructions 5.2.1 Using Table Read Instructions Table reads require two steps. First, an address pointer is setup using the TBLPAG register and one of the W registers. Then, the program memory contents at the address location may be read. 5.2.1.1 Read Word Mode The following code example shows how to read a word of program memory using the table instructions in Word mode: ; Setup the address pointer to program space MOV #tblpage(PROG_ADDR),W0 ; get table page value MOV W0,TBLPAG ; load TBLPAG register MOV #tbloffset(PROG_ADDR),W0 ; load address LS word ; Read the program memory location TBLRDH [W0],W3 ; Read high byte to W3 TBLRDL [W0],W4 ; Read low word to W4 5.2.1.2 Read Byte Mode ; Setup the address pointer to program space MOV #tblpage(PROG_ADDR),W0 ; get table page value MOV W0,TBLPAG ; load TBLPAG register MOV #tbloffset(PROG_ADDR),W0 ; load address LS word ; Read the program memory location TBLRDH.B [W0],W3 ; Read high byte to W3 TBLRDL.B [W0++],W4 ; Read low byte to W4 TBLRDL.B [W0++],W5 ; Read middle byte to W5 In the code example above, the post-increment operator on the read of the low byte causes the address in the working register to increment by one. This sets EA<0> to a ‘1’ for access to the middle byte in the third write instruction. The last post-increment sets W0 back to an even address, pointing to the next program memory location. TBLPAG 8 bits from TBLPAG EA EA<0> Selects Byte 24-bit EA TBLPAG<7> Selects User/Configuration Space 7 0 15 0 16 bits from Wn Note: The tblpage() and tbloffset() directives are provided by the Microchip assembler for the dsPIC30F. These directives select the appropriate TBLPAG and W register values for the table instruction from a program memory address value. Refer to the MPLAB ASM 30, MPLAB LINK30 and Utilities User’s Guide (DS51317) for further details. dsPIC30F Family Reference Manual DS70052D-page 5-4 © 2005 Microchip Technology Inc. 5.2.2 Using Table Write Instructions The effect of a table write instruction will depend on the type of memory technology that is present in the device program memory address space. The program memory address space could contain volatile or non-volatile program memory, non-volatile data memory, and an External Bus Interface (EBI). If a table write instruction occurs within the EBI address region, for example, the write data will be placed onto the EBI data lines. 5.2.2.1 Table Write Holding Latches Table write instructions do not write directly to the non-volatile program and data memory. Instead, the table write instructions load holding latches that store the write data. The holding latches are not memory mapped and can only be accessed using table write instructions. When all of the holding latches have been loaded, the actual memory programming operation is started by executing a special sequence of instructions. The number of holding latches will determine the maximum memory block size that can be programmed and may vary depending on the type of non-volatile memory and the device variant. For example, the number of holding latches could be different for program memory, data EEPROM memory and Device Configuration registers for a given device. In general, the program memory is segmented into rows and panels. Each panel will have its own set of table write holding latches. This allows multiple memory panels to be programmed at once, reducing the overall programming time for the device. For each memory panel, there are generally enough holding latches to program one row of memory at a time. The memory logic automatically decides which set of write latches to load based on the address value used in the table write instruction. Please refer to the specific device data sheet for further details. 5.2.2.2 Write Word Mode The following sequence can be used to write a single program memory latch location in Word mode: ; Setup the address pointer to program space MOV #tblpage(PROG_ADDR),W0 ; get table page value MOV W0,TBLPAG ; load TBLPAG register MOV #tbloffset(PROG_ADDR),W0 ; load address LS word ; Load write data into W registers MOV #PROG_LOW_WORD,W2 MOV #PROG_HI_BYTE,W3 ; Perform the table writes to load the latch TBLWTL W2,[W0] TBLWTH W3,[W0++] In this example, the contents of the upper byte of W3 does not matter because this data will be written to the phantom byte location. W0 is post-incremented by 2, after the second TBLWTH instruction, to prepare for the write to the next program memory location. © 2005 Microchip Technology Inc. DS70052D-page 5-5 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 5.2.2.3 Write Byte Mode To write a single program memory latch location in Byte mode, the following code sequence can be used: ; Setup the address pointer to program space MOV #tblpage(PROG_ADDR),W0 ; get table page value MOV W0,TBLPAG ; load TBLPAG register MOV #tbloffset(PROG_ADDR),W0 ; load address LS word ; Load data into working registers MOV #LOW_BYTE,W2 MOV #MID_BYTE,W3 MOV #HIGH_BYTE,W4 ; Write data to the latch TBLWTH.B W4,[W0] ; write high byte TBLWTL.B W2,[W0++] ; write low byte TBLWTL.B W3,[W0++] ; write middle byte In the code example above, the post-increment operator on the write to the low byte causes the address in W0 to increment by one. This sets EA<0> = 1 for access to the middle byte in the third write instruction. The last post-increment sets W0 back to an even address pointing to the next program memory location. 5.3 Control Registers Flash and data EEPROM programming operations are controlled using the following Non-Volatile Memory (NVM) control registers: • NVMCON: Non-Volatile Memory Control Register • NVMKEY: Non-Volatile Memory Key Register • NVMADR: Non-Volatile Memory Address Register 5.3.1 NVMCON Register The NVMCON register is the primary control register for Flash and EEPROM program/erase operations. This register selects Flash or EEPROM memory, whether an erase or program operation will be performed, and is used to start the program or erase cycle. The NVMCON register is shown in Register 5-1. The lower byte of NVMCOM configures the type of NVM operation that will be performed. For convenience, a summary of NVMCON setup values for various program and erase operations is given in Table 5-1. Table 5-1: NVMCON Register Values NVMCON Register Values for RTSP Program and Erase Operations Memory Type Operation Data Size NVMCON Value Flash PM Erase 1 row (32 instr. words) 0x4041 Program 1 row (32 instr. words) 0x4001 Data EEPROM Erase 1 data word 0x4044 16 data words 0x4045 Entire EEPROM 0x4046 Program 1 data word 0x4004 16 data words 0x4005 Configuration Register Write(1) 1 config. register 0x4008 Note 1: The Device Configuration registers, except for FG5, may be written to a new value without performing an erase cycle. dsPIC30F Family Reference Manual DS70052D-page 5-6 © 2005 Microchip Technology Inc. 5.3.2 NVM Address Register There are two NVM Address Registers - NVMADRU and NVMADR. These two registers when concatenated form the 24-bit effective address (EA) of the selected row or word for programming operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA. The register pair, NVMADRU:NVMADR, capture the EA<23:0> of the last table-write instruction that has been executed and select the row of Flash or EEPROM memory to write/erase. Figure 5-2 shows how the program memory EA is formed for programming and erase operations. Although the NVMADRU and NVMADR registers are automatically loaded by the table-write instructions, the user can also directly modify their contents before the programming operation begins. A write to these registers will be required prior to an erase operation, because no table-write instructions are required for any erase operation. Figure 5-2: NVM Addressing with TBLPAG and NVM Address Registers 5.3.3 NVMKEY Register NVMKEY is a write only register that is used to prevent accidental writes/erasures of Flash or EEPROM memory. To start a programming or an erase sequence, the following steps must be taken in the exact order shown: 1. Write 0x55 to NVMKEY. 2. Write 0xAA to NVMKEY. 3. Execute two NOP instructions. After this sequence, a write will be allowed to the NVMCON register for one instruction cycle. In most cases, the user will simply need to set the WR bit in the NVMCON register to start the program or erase cycle. Interrupts should be disabled during the unlock sequence. The code example below shows how the unlock sequence is performed: PUSH SR ; Disable interrupts, if enabled MOV #0x00E0,W0 IOR SR MOV #0x55,W0 MOV #0xAA,W0 MOV W0,NVMKEY MOV W0,NVMKEY ; NOP not required BSET NVMCON,#WR ; Start the program/erase cycle NOP NOP POP SR ; Re-enable interrupts Refer to Section 5.4.2 “Flash Programming Operations” for further programming examples. 24-bit PM address TBLPAG Reg 8 bits 16 bits Using NVMADR Addressing NVMADR Register NVMADR register loaded with contents of W register EA used during last table-write instruction. W Register EA EA<0> is Byte Select TBLPAG<7> selects User or Configuration Space NVMADRU Register TBLPAG register during last table-write instruction NVMADRU register loaded with contents of © 2005 Microchip Technology Inc. DS70052D-page 5-7 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 Register 5-1: NVMCON: Non-Volatile Memory Control Register Upper Byte: R/S-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PROGOP<7:0> bit 7 bit 0 bit 15 WR: Write (Program or Erase) Control bit 1 = Initiates a data EEPROM or program Flash erase or write cycle (the WR bit can be set but not cleared in software) 0 = Write cycle is complete bit 14 WREN: Write (Erase or Program) Enable bit 1 = Enable an erase or program operation 0 = No operation allowed (Device clears this bit on completion of the write/erase operation) bit 13 WRERR: Flash Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or WDT Reset during programming operation) 0 = The write operation completed successfully bit 12-8 Reserved: User code should write ‘0’s to these locations bit 7-0 PROGOP<7:0>: Programming Operation Command Byte bits Erase Operations: 0x41 = Erase 1 row (32 instruction words) of program Flash 0x44 = Erase 1 data word from data EEPROM 0x45 = Erase 1 row (16 data words) from data EEPROM 0x46 = Erase entire data EEPROM Programming Operations: 0x01 = Program 1 row (32 instruction words) into Flash program memory 0x04 = Program 1 data word into data EEPROM 0x05 = Program 1 row (16 data words) into data EEPROM 0x08 = Program 1 data word into device configuration register Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70052D-page 5-8 © 2005 Microchip Technology Inc. Register 5-2: NVMADR: Non-Volatile Memory Address Register Upper Byte: R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<15:8> bit 15 bit 8 Lower Byte: R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<7:0> bit 7 bit 0 bit 15-0 NVMADR<15:0>: NV Memory Write Address bits Selects the location to program or erase in program or data Flash memory. This register may be read or written by user. This register will contain the address of EA<15:0> of the last table write instruction executed, until written by the user. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2005 Microchip Technology Inc. DS70052D-page 5-9 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 Register 5-3: NVMADRU: Non-Volatile Memory Upper Address Register Register 5-4: NVMKEY: Non-Volatile Memory Key Register Upper Byte: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 Lower Byte: R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADRU<7:0> bit 7 bit 0 bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMADRU<7:0>: NV Memory Upper Write Address bits Selects the upper 8 bits of the location to program or erase in program or data Flash memory. This register may be read or written by the user. This register will contain the value of the TBLPAG register when the last table write instruction executed, until written by the user. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Upper Byte: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 Lower Byte: W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (Write Only) bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70052D-page 5-10 © 2005 Microchip Technology Inc. 5.4 Run-Time Self-Programming (RTSP) RTSP allows the user code to modify Flash program memory contents. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions, and the NVM Control registers. With RTSP, the user may erase program memory, 32 instructions (96 bytes) at a time and can write program memory data, 32 instructions (96 bytes) at a time. 5.4.1 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions or 96 bytes. The panel size may vary depending on the dsPIC30F device variant. Refer to the device data sheet for further information. Typically, each panel consists of 128 rows, or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program 32 instructions at one time. Each panel of program memory contains write latches that hold 32 instructions of programming data. These latches are not memory mapped. The only way for the user to access the write latches is through the use of table write instructions. Prior to the actual programming operation, the write data must be loaded into the panel write latches with table write instructions. The data to be programmed into the panel is typically loaded in sequential order into the write latches: instruction 0, instruction 1, etc. The instruction words loaded must always be from an ‘even’ group of four address boundaries (e.g., loading of instructions 3, 4, 5, 6 is not allowed). Another way of stating this requirement is that the starting program memory address of the four instructions must have the 3 LSb’s equal to ‘0’. All 32 write latches must be written during a programming operation to ensure that any old data held in the latches is overwritten. The basic sequence for RTSP programming is to setup a table pointer, then do a series of TBLWT instructions to load the write latches. Programming is performed by setting special bits in the NVMCON register. 32 TBLWTL and 32 TBLWTH instructions are required to load the four instructions. If multiple, discontinuous regions of program memory need to be programmed, the table pointer should be changed for each region and the next set of write latches written. All of the table write operations to the Flash program memory take 2 instruction cycles each, because only the table latches are written. The actual programming operation is initiated using the NVMCON register. 5.4.2 Flash Programming Operations A program/erase operation is necessary for programming or erasing the internal Flash program memory in RTSP mode. The program or erase operation is automatically timed by the device and is nominally 2 msec in duration. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. The CPU stalls (waits) until the programming operation is finished. The CPU will not execute any instruction or respond to interrupts during this time. If any interrupts do occur during the programming cycle, then they will remain pending until the cycle completes. © 2005 Microchip Technology Inc. DS70052D-page 5-11 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 5.4.2.1 Flash Program Memory Programming Algorithm The user can erase and program Flash Program Memory by rows (32 instruction words). The general process is as follows: 1. Read one row of program Flash (32 instruction words) and store into data RAM as a data “image”. The RAM image must be read from an even 32-word program memory address boundary. 2. Update the RAM data image with the new program memory data. 3. Erase program Flash row. • Setup NVMCON register to erase 1 row of Flash program memory. • Write address of row to be erased into NVMADRU and NVMADR registers. • Disable interrupts. • Write the key sequence to NVMKEY to enable the erase. • Set the WR bit. This will begin erase cycle. • CPU will stall for the duration of the erase cycle. • The WR bit is cleared when erase cycle ends. • Re-enable interrupts. 4. Write 32 instruction words of data from RAM into the Flash program memory write latches. 5. Program 32 instruction words into program Flash. • Setup NVMCON to program one row of Flash program memory. • Disable interrupts. • Write the key sequence to NVMKEY to enable the program cycle. • Set the WR bit. This will begin the program cycle. • CPU will stall for duration of the program cycle. • The WR bit is cleared by the hardware when program cycle ends. • Re-enable interrupts. 6. Repeat steps 1 through 6, as needed, to program the desired amount of Flash program memory Note: The user should remember that the minimum amount of program memory that can be modified using RTSP is 32 instruction word locations. Therefore, it is important that an image of these locations be stored in general purpose RAM before an erase cycle is initiated. An erase cycle must be performed on any previously written locations before any programming is done. dsPIC30F Family Reference Manual DS70052D-page 5-12 © 2005 Microchip Technology Inc. 5.4.2.2 Erasing a Row of Program Memory The following is a code sequence that can be used to erase a row (32 instructions) of program memory. The NVMCON register is configured to erase one row of program memory. The NVMADRU and NVMADR registers are loaded with the address of the row to be erased. The program memory must be erased at ‘even’ row boundaries. Therefore, the 6 LSbits of the value written to the NVMADR register have no effect when a row is erased. The erase operation is initiated by writing a special unlock, or key sequence to the NVMKEY register before setting the WR control bit (NVMCON<15>). The unlock sequence needs to be executed in the exact order shown without interruption. Therefore, interrupts should be disabled prior to writing the sequence. Two NOP instructions should be inserted in the code at the point where the CPU will resume operation. Finally, interrupts can be enabled (if required). ; Setup NVMCON to erase one row of Flash program memory MOV #0x4041,W0 MOV W0,NVMCON ; Setup address pointer to row to be ERASED MOV #tblpage(PROG_ADDR),W0 MOV W0,NVMADRU MOV #tbloffset(PROG_ADDR),W0 MOV W0,NVMADR ; Disable interrupts, if enabled PUSH SR MOV #0x00E0,W0 IOR SR ; Write the KEY sequence MOV #0x55,W0 MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY ; Start the erase operation BSET NVMCON,#WR ; Insert two NOPs after the erase cycle (required) NOP NOP ; Re-enable interrupts, if needed POP SR Note: When erasing a row of program memory, the user writes the upper 8 bits of the erase address directly to the NVMADRU and NVMADR registers. Together, the contents of the NVMADRU and NVMADR registers form the complete address of the program memory row to be erased. The NVMADRU and NVMADR registers specify the address for all Flash erase and program operations. However, these two registers do not have to be directly written by the user for Flash program operations. This is because the table write instructions used to write the program memory data automatically transfers the TBLPAG register contents and the table write address into the NVMADRU and NVMADR registers. The above code example could be modified to perform a ‘dummy’ table write operation to capture the program memory erase address. © 2005 Microchip Technology Inc. DS70052D-page 5-13 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 5.4.2.3 Loading Write Latches The following is a sequence of instructions that can be used to load the 768-bits of write latches (32 instruction words). 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. The TBLPAG register is loaded with the 8 MSbits of the program memory address. The user does not need to write the NVMADRU:NVMADR register-pair for a Flash programming operation. The 24-bits of the program memory address are automatically captured into the NVMADRU:NVMADR register-pair when each table write instruction is executed. The program memory must be programmed at an ‘even’ 32 instruction word address boundary. In effect, the 6 LSbits of the value captured in the NVMADR register are not used during the programming operation. The row of 32 instruction words do not necessarily have to be written in sequential order. The 6 LSbits of the table write address determine which of the latches will be written. However, all 32 instruction words should be written for each programming cycle to overwrite old data. ; Set up a pointer to the first program memory location to be written. MOV #tblpage(PROG_ADDR),W0 MOV W0,TBLPAG MOV #tbloffset(PROG_ADDR),W0 ; Perform the TBLWT instructions to write the latches ; W0 is incremented in the TBLWTH instruction to point to the ; next instruction location. MOV #LOW_WORD_0,W2 MOV #HIGH_BYTE_0,W3 TBLWTL W2,[W0] TBLWTH W3,[W0++] ; 1st_program_word MOV #LOW_WORD_1,W2 MOV #HIGH_BYTE_1,W3 TBLWTL W2,[W0] TBLWTH W3,[W0++] ; 2nd_program_word MOV #LOW_WORD_2,W2 MOV #HIGH_BYTE_2,W3 TBLWTL W2, [W0] TBLWTH W3, [W0++] ; 3rd_program_word MOV #LOW_WORD_3,W2 MOV #HIGH_BYTE_3,W3 TBLWTL W2,[W0] TBLWTH W3,[W0++] ; 4th_program_word ........ ........ MOV #LOW_WORD_31,W2 MOV #HIGH_BYTE_31,W3 TBLWTL W2,[W0] TBLWTH W3,[W0++] ; 32nd_program_word Note: The following code example is the ‘Load_Write_Latch’ code referred to in subsequent examples. dsPIC30F Family Reference Manual DS70052D-page 5-14 © 2005 Microchip Technology Inc. 5.4.2.4 Single Row Programming Example An example of single row programming code is: ; Setup NVMCON to write 1 row of program memory MOV #0x4001,W0 MOV W0,NVMCON ; Load the 32 program memory write latches CALL Load_Write_Latch(1) ; Disable interrupts, if enabled PUSH SR MOV #0x00E0,W0 IOR SR ; Write the KEY sequence MOV #0x55,W0 MOV W0,NVMKEY MOV #0xAA,W0 MOV W0,NVMKEY ; Start the programming sequence BSET NVMCON,#WR ; Insert two NOPs after programming NOP NOP ; Re-enable interrupts, if required POP SR Note 1: See Section 5.4.2.3 “Loading Write Latches” 5.4.3 Writing to Device Configuration Registers RTSP may be used to write to the Device Configuration registers. RTSP allows each Configuration register, except the FG5, to be individually rewritten without first performing an erase cycle. Caution must be exercised when writing the Configuration registers since they control critical device operating parameters, such as the system clock source, PLL multiplication ratio and WDT enable. The procedure for programming a Device Configuration register is similar to the procedure for Flash program memory, except that only TBLWTL instructions are required. This is because the upper 8 bits are unused in each Device Configuration register. Furthermore, bit 23 of the table write address must be set to access the Configuration registers. Refer to Section 24. “Device Configuration” and the device data sheet for a full description of the Device Configuration registers. 5.4.3.1 Configuration Register Write Algorithm 1. Write the new configuration value to the table write latch using a TBLWTL instruction. 2. Configure NVMCON for a Configuration register write (NVMCON = 0x4008). 3. Disable interrupts, if enabled. 4. Write the key sequence to NVMKEY. 5. Start the write sequence by setting WR (NVMCON<15>). 6. CPU execution will resume when the write is finished. 7. Re-enable interrupts, if needed. © 2005 Microchip Technology Inc. DS70052D-page 5-15 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 5.4.3.2 Configuration Register Write Code Example The following code sequence can be used to modify a Device Configuration register: ; Set up a pointer to the location to be written. MOV #tblpage(CONFIG_ADDR),W0 MOV W0,TBLPAG MOV #tbloffset(CONFIG_ADDR),W0 ; Get the new data to write to the configuration register MOV #ConfigValue,W1 ; Perform the table write to load the write latch TBLWTL W1,[W0] ; Configure NVMCON for a configuration register write MOV #0x4008,W0 MOV W0,NVMCON ; Disable interrupts, if enabled PUSH SR MOV #0x00E0,W0 IOR SR ; Write the KEY sequence MOV #0x55,W0 MOV W0,NVMKEY MOV #0xAA,W0 MOV W0,NVMKEY ; Start the programming sequence BSET NVMCON,#WR ; Insert two NOPs after programming NOP NOP ; Re-enable interrupts, if required POP SR 5.5 Data EEPROM Programming The EEPROM block is accessed using table read and write operations similar to the program memory. The TBLWTH and TBLRDH instructions are not required for EEPROM operations since the memory is only 16-bits wide. The program and erase procedures for the data EEPROM are similar to those used for the Flash program memory, except they are optimized for fast data access. The following programming operations can be performed on the data EEPROM: • Erase one word • Erase one row (16 words) • Erase entire data EEPROM • Program one word • Program one row (16 words) The data EEPROM is readable and writable during normal operation (full VDD operating range). Unlike the Flash program memory, normal program execution is not stopped during an EEPROM program or erase operation. EEPROM erase and program operations are performed using the NVMCON and NVMKEY registers. The programming software is responsible for waiting for the operation to complete. The software may detect when the EEPROM erase or programming operation is complete by one of three methods: • Poll the WR bit (NVMCON<15>) in software. The WR bit will be cleared when the operation is complete. • Poll the NVMIF bit (IFS0<12>) in software. The NVMIF bit will be set when the operation is complete. • Enable NVM interrupts. The CPU will be interrupted when the operation is complete. Further programming operations can be handled in the ISR. Note: Unexpected results will be obtained should the user attempt to read the EEPROM while a programming or erase operation is underway. dsPIC30F Family Reference Manual DS70052D-page 5-16 © 2005 Microchip Technology Inc. 5.5.1 EEPROM Single Word Programming Algorithm 1. Erase one EEPROM word. • Setup NVMCON register to erase one EEPROM word. • Write address of word to be erased into NVMADRU, NVMADR registers. • Clear NVMIF status bit and enable NVM interrupt (optional). • Write the key sequence to NVMKEY. • Set the WR bit. This will begin erase cycle. • Either poll the WR bit or wait for the NVM interrupt. 2. Write data word into data EEPROM write latch. 3. Program the data word into the EEPROM. • Setup the NVMCON register to program one EEPROM word. • Clear NVMIF status bit and enable NVM interrupt (optional). • Write the key sequence to NVMKEY. • Set the WR bit. This will begin the program cycle. • Either poll the WR bit or wait for the NVM interrupt. 5.5.2 EEPROM Row Programming Algorithm If multiple words need to be programmed into the EEPROM, it is quicker to erase and program 16 words (1 row) at a time. The process to program 16 words of EEPROM is: 1. Read one row of data EEPROM (16 words) and store into data RAM as a data “image”. The section of EEPROM to be modified must fall on an even 16-word address boundary. 2. Update the data image with the new data. 3. Erase the EEPROM row. • Setup the NVMCON register to erase one row of EEPROM. • Write starting address of row to be erased into NUMADRU and NVMADR registers. • Clear NVMIF status bit and enable NVM interrupt (optional). • Write the key sequence to NVMKEY. • Set the WR bit. This will begin the erase cycle. • Either poll the WR bit or wait for the NVM interrupt. 4. Write the 16 data words into the data EEPROM write latches. 5. Program a row into data EEPROM. • Setup the NVMCON register to program one row of EEPROM. • Clear NVMIF status bit and enable NVM interrupt (optional). • Write the key sequence to NVMKEY. • Set the WR bit. This will begin the program cycle. • Either poll the WR bit or wait for the NVM interrupt. © 2005 Microchip Technology Inc. DS70052D-page 5-17 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 5.5.3 Erasing One Word of Data EEPROM Memory The NVMADRU and NVMADR registers must be loaded with the data EEPROM address to be erased. Since one word of the EEPROM is accessed, the LSB of the NVMADR has no effect on the erase operation. The NVMCON register must be configured to erase one word of EEPROM memory. Setting the WR control bit (NVMCON<15>) initiates the erase. A special unlock or key sequence should be written to the NVMKEY register before setting the WR control bit. The unlock sequence needs to be executed in the exact order shown without interruption. Therefore, interrupts should be disabled prior to writing the sequence. ; Set up a pointer to the EEPROM location to be erased. MOV #tblpage(EE_ADDR),W0 MOV W0,NVMADRU MOV #tbloffset(EE_ADDR),W0 MOV W0,NVMADR ; Setup NVMCON to erase one word of data EEPROM MOV #0x4044,W0 MOV W0,NVMCON ; Disable interrupts while the KEY sequence is written PUSH SR MOV #0x00E0,W0 IOR SR ; Write the KEY sequence MOV #0x55,W0 MOV W0,NVMKEY MOV #0xAA,W0 MOV W0,NVMKEY ; Start the erase cycle BSET NVMCON,#WR ; Re-enable interrupts POP SR dsPIC30F Family Reference Manual DS70052D-page 5-18 © 2005 Microchip Technology Inc. 5.5.4 Writing One Word of Data EEPROM Memory Assuming the user has erased the EEPROM location to be programmed, use a table write instruction to write one write latch. The TBLPAG register is loaded with the 8 MSBs of the EEPROM address. The 16 LSBs of the EEPROM address are automatically captured into the NVMADR register when the table write is executed. The LSB of the NVMADR register has no effect on the programming operation. The NVMCON register is configured to program one word of data EEPROM. Setting the WR control bit (NVMCON<15>) initiates the programming operation. A special unlock or key sequence should be written to the NVMKEY register before setting the WR control bit. The unlock sequence needs to be executed in the exact order shown without interruption. Therefore, interrupts should be disabled prior to writing the sequence. ; Setup a pointer to data EEPROM MOV #tblpage(EE_ADDR),W0 MOV W0,TBLPAG MOV #tbloffset(EE_ADDR),W0 ; Write data value to holding latch MOV EE_DATA,W1 TBLWTL W1,[ W0] ; NVMADR captures write address from the TBLWTL instruction. ; Setup NVMCON for programming one word to data EEPROM MOV #0x4004,W0 MOV W0,NVMCON ; Disable interrupts while the KEY sequence is written PUSH SR MOV #0x00E0,W0 IOR SR ; Write the key sequence MOV #0x55,W0 MOV W0,NVMKEY MOV #0xAA,W0 MOV W0,NVMKEY ; Start the write cycle BSET NVMCON,#WR ;Re-enable interrupts, if needed POP SR © 2005 Microchip Technology Inc. DS70052D-page 5-19 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 5.5.5 Erasing One Row of Data EEPROM The NVMCON register is configured to erase one row of EEPROM memory. The NVMADRU and NVMADR registers must point to the row to be erased. The data EEPROM must be erased at even address boundaries. Therefore, the 5 LSBs of the NVMADR register will have no effect on the row that is erased. Setting the WR control bit (NVMCON<15>) initiates the erase. A special unlock or key sequence should be written to the NVMKEY register before setting the WR control bit. The unlock sequence needs to be executed in the exact order shown without interruption. Therefore, interrupts should be disabled prior to writing the sequence. ; Set up a pointer to the EEPROM row to be erased. MOV #tblpage(EE_ADDR),W0 MOV W0,NVMADRU MOV #tbloffset(EE_ADDR),W0 MOV W0,NVMADR ; Setup NVMCON to erase one row of EEPROM MOV #0x4045,W0 MOV W0,NVMCON ; Disable interrupts while the KEY sequence is written PUSH SR MOV #0x00E0,W0 IOR SR ; Write the KEY Sequence MOV #0x55,W0 MOV W0,NVMKEY MOV #0xAA,W0 MOV W0,NVMKEY ; Start the erase operation BSET NVMCON,#WR ;Re-enable interrupts, if needed POP SR dsPIC30F Family Reference Manual DS70052D-page 5-20 © 2005 Microchip Technology Inc. 5.5.6 Write One Row of Data EEPROM Memory To write a row of data EEPROM, all sixteen write latches must be written before the programming sequence is initiated. The TBLPAG register is loaded with the 8 MSbs of the EEPROM address. The 16 LSbs of the EEPROM address are automatically captured into the NVMADR register when each table write is executed. Data EEPROM row programming must occur at even address boundaries, so the 5 LSbs of the NVMADR register have no effect on the row that is programmed. Setting the WR control bit (NVMCON<15>) initiates the programming operation. A special unlock or key sequence should be written to the NVMKEY register before setting the WR control bit. The unlock sequence needs to be executed in the exact order shown without interruption. Therefore, interrupts should be disabled prior to writing the sequence. ; Set up a pointer to the EEPROM row to be programmed. MOV #tblpage(EE_ADDR),W0 MOV W0,TBLPAG MOV #tbloffset(EE_ADDR),W0 ; Write the data to the programming latches. MOV data_ptr,W1 ; Use W1 as pointer to the data. TBLWTL [W1++],[W0++] ; Write 1st data word TBLWTL [W1++],[W0++] ; Write 2nd data word TBLWTL [W1++],[W0++] ; Write 3rd data word TBLWTL [W1++],[W0++] ; Write 4th data word TBLWTL [W1++],[W0++] ; Write 5th data word TBLWTL [W1++],[W0++] ; Write 6th data word TBLWTL [W1++],[W0++] ; Write 7th data word TBLWTL [W1++],[W0++] ; Write 8th data word TBLWTL [W1++],[W0++] ; Write 9th data word TBLWTL [W1++],[W0++] ; Write 10th data word TBLWTL [W1++],[W0++] ; Write 11th data word TBLWTL [W1++],[W0++] ; Write 12th data word TBLWTL [W1++],[W0++] ; Write 13th data word TBLWTL [W1++],[W0++] ; Write 14th data word TBLWTL [W1++],[W0++] ; Write 15th data word TBLWTL [W1++],[W0++] ; Write 16th data word ; The NVMADR captures last table access address. ; Setup NVMCON to write one row of EEPROM MOV #0x4005,W0 MOV W0,NVMCON ; Disable interrupts while the KEY sequence is written PUSH SR MOV #0x00E0,W0 IOR SR ; Write the KEY sequence MOV #0x55,W0 MOV W0,NVMKEY MOV #0xAA,W0 MOV W0,NVMKEY ; Start the programming operation BSET NVMCON,#WR ;Re-enable interrupts, if needed POP SR Note: Sixteen table write instructions have been used in this code segment to provide clarity in the example. The code segment could be simplified by using a single table write instruction in a REPEAT loop. © 2005 Microchip Technology Inc. DS70052D-page 5-21 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 5.5.7 Reading the Data EEPROM Memory A TBLRD instruction reads a word at the current program word address. This example uses W0 as a pointer to data Flash. The result is placed into register W4. ; Setup pointer to EEPROM memory MOV #tblpage(EE_ADDR),W0 MOV W0,TBLPAG MOV #tbloffset(EE_ADDR),W0 ; Read the EEPROM data TBLRDL [W0],W4 5.6 Design Tips Question 1: I cannot get the device to program or erase properly. My code appears to be correct. What could be the cause? Answer: Interrupts should be disabled when a program or erase cycle is initiated to ensure that the key sequence executes without interruption. Interrupts can be disabled by raising the current CPU priority to level 7. The code examples in this chapter disable interrupts by saving the current SR register value on the stack, then ORing the value 0x00E0 with SR to force IPL<2:0> = 111. If no priority level 7 interrupts are enabled, then the DISI instruction provides another method to temporarily disable interrupts, while the key sequence is executed. Question 2: What is an easy way to read data EEPROM without using table instructions? Answer: The data EEPROM is mapped into the program memory space. PSV can be used to map the EEPROM region into data memory space. See Section 4. “Program Memory” for further information about PSV. Note: Program Space Visibility (PSV) can also be used to read locations in the program memory address space. See Section 4. “Program Memory” for further information about PSV. dsPIC30F Family Reference Manual DS70052D-page 5-22 © 2005 Microchip Technology Inc. 5.7 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Flash and EEPROM Programming module are: Title Application Note # Using the dsPIC30F for Sensorless BLDC Control AN901 Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. © 2005 Microchip Technology Inc. DS70052D-page 5-23 Section 5. Flash and EEPROM Programming Fla s h a n d E E P R O M Programming 5 5.8 Revision History Revision A This is the initial released revision of this document. Revision B This revision incorporates technical content changes for the dsPIC30F Flash and EEPROM Programming module. Revision C This revision incorporates all known errata at the time of this document update. Revision D This revision incorporates technical content changes for the dsPIC30F Flash and EEPROM Programming module. dsPIC30F Family Reference Manual DS70052D-page 5-24 © 2005 Microchip Technology Inc. NOTES: © 2004 Microchip Technology Inc. DS70053C-page 6-1 Interrupts 6 Section 6. Reset Interrupts HIGHLIGHTS This section of the manual contains the following topics: 6.1 Introduction .................................................................................................................... 6-2 6.2 Non-Maskable Traps...................................................................................................... 6-6 6.3 Interrupt Processing Timing ......................................................................................... 6-11 6.4 Interrupt Control and Status Registers......................................................................... 6-14 6.5 Interrupt Setup Procedures.......................................................................................... 6-42 6.6 Design Tips .................................................................................................................. 6-44 6.7 Related Application Notes............................................................................................6-45 6.8 Revision History ........................................................................................................... 6-46 dsPIC30F Family Reference Manual DS70053C-page 6-2 © 2004 Microchip Technology Inc. 6.1 Introduction The dsPIC30F interrupt controller module reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC30F CPU and has the following features: • Up to 8 processor exceptions and software traps • 7 user selectable priority levels • Interrupt Vector Table (IVT) with up to 62 vectors • A unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies 6.1.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 6-1. The IVT resides in program memory, starting at location 0x000004. The IVT contains 62 vectors consisting of 8 non-maskable trap vectors plus up to 54 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). 6.1.2 Alternate Vector Table The Alternate Interrupt Vector Table (AIVT) is located after the IVT as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run-time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 6.1.3 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC30F device clears its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000. The user programs a GOTO instruction at the Reset address which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. © 2004 Microchip Technology Inc. DS70053C-page 6-3 Section 6. Interrupts Interrupts 6 Figure 6-1: Interrupt Vector Table Table 6-1: Trap Vector Details Decreasing Natural Order Priority 0x000000 0x000014 Reserved Address Error Trap Vector Stack Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Arithmetic Error Trap Vector Oscillator Fail Trap Vector Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 IVT AIVT 0x000080 0x00007E 0x0000FE Reserved Reserved Address Error Trap Vector Stack Error Trap Vector Reserved Reserved Arithmetic Error Trap Vector Oscillator Fail Trap Vector 0x000094 Reset – GOTO Instruction Reset – GOTO Address 0x000002 Reserved 0x000082 0x000084 0x000004 See Table 6-2 Vector details. for Interrupt Vector Number IVT Address AIVT Address Trap Source 0 0x000004 0x000084 Reserved 1 0x000006 0x000086 Oscillator Failure 2 0x000008 0x000088 Address Error 3 0x00000A 0x00008A Stack Error 4 0x00000C 0x00008C Arithmetic Error 5 0x00000E 0x00008E Reserved 6 0x000010 0x000090 Reserved 7 0x000012 0x000092 Reserved dsPIC30F Family Reference Manual DS70053C-page 6-4 © 2004 Microchip Technology Inc. Table 6-2: Interrupt Vector Details Vector Number IVT Address AIVT Address Interrupt Source 8 0x000014 0x000094 INT0 – External Interrupt 0 9 0x000016 0x000096 IC1 – Input Compare 1 10 0x000018 0x000098 OC1 – Output Compare 1 11 0x00001A 0x00009A T1 – Timer 1 12 0x00001C 0x00009C IC2 – Input Capture 2 13 0x00001E 0x00009E OC2 – Output Compare 2 14 0x000020 0x0000A0 T2 – Timer 2 15 0x000022 0x0000A2 T3 – Timer 3 16 0x000024 0x0000A4 SPI1 17 0x000026 0x0000A6 U1RX – UART1 Receiver 18 0x000028 0x0000A8 U1TX – UART1 Transmitter 19 0x00002A 0x0000AA ADC – ADC Convert Done 20 0x00002C 0x0000AC NVM – NVM Write Complete 21 0x00002E 0x0000AE I 2C Slave Operation – Message Detect 22 0x000030 0x0000B0 I 2C Master Operation – Message Event Complete 23 0x000032 0x0000B2 Change Notice Interrupt 24 0x000034 0x0000B4 INT1 – External Interrupt 1 25 0x000036 0x0000B6 IC7 – Input Capture 7 26 0x000038 0x0000B8 IC8 – Input Capture 8 27 0x00003A 0x0000BA OC3 – Output Compare 3 28 0x00003C 0x0000BC OC4 – Output Compare 4 29 0x00003E 0x0000BE T4 – Timer 4 30 0x000040 0x0000C0 T5 – Timer 5 31 0x000042 0x0000C2 INT2 – External Interrupt 2 32 0x000044 0x0000C4 U2RX – UART2 Receiver 33 0x000046 0x0000C6 U2TX – UART2 Transmitter 34 0x000048 0x0000C8 SPI2 35 0x00004A 0x0000CA CAN1 36 0x00004C 0x0000CC IC3 – Input Capture 3 37 0x00004E 0x0000CE IC4 – Input Capture 4 38 0x000050 0x0000D0 IC5 – Input Capture 5 39 0x000052 0x0000D2 IC6 – Input Capture 6 40 0x000054 0x0000D4 OC5 – Output Compare 5 41 0x000056 0x0000D6 OC6 – Output Compare 6 42 0x000058 0x0000D8 OC7 – Output Compare 7 43 0x00005A 0x0000DA OC8 – Output Compare 8 44 0x00005C 0x0000DC INT3 – External Interrupt 3 45 0x00005E 0x0000DE INT4 – External Interrupt 4 46 0x000060 0x0000E0 CAN2 47 0x000062 0x0000E2 PWM – PWM Period Match 48 0x000064 0x0000E4 QEI – Position Counter Compare 49 0x000066 0x0000E6 DCI – Codec Transfer Done 50 0x000068 0x0000E8 LVD – Low Voltage Detect 51 0x00006A 0x0000EA FLTA – MCPWM Fault A 52 0x00006C 0x0000EC FLTB – MCPWM Fault B 53-61 0x00006E-0x00007E 0x00006E-0x00007E Reserved © 2004 Microchip Technology Inc. DS70053C-page 6-5 Section 6. Interrupts Interrupts 6 6.1.4 CPU Priority Status The CPU can operate at one of sixteen priority levels, 0-15. An interrupt or trap source must have a priority level greater than the current CPU priority in order to initiate an exception process. Peripheral and external interrupt sources can be programmed for level 0-7, while CPU priority levels 8-15 are reserved for trap sources. A trap is a non-maskable interrupt source intended to detect hardware and software problems (see Section 6.2 ”Non-Maskable Traps”). The priority level for each trap source is fixed and only one trap is assigned to a priority level. Note that an interrupt source programmed to priority level 0 is effectively disabled, since it can never be greater than the CPU priority. The current CPU priority level is indicated by the following four status bits: • IPL<2:0> status bits located in SR<7:5> • IPL3 status bit located in CORCON<3> The IPL<2:0> status bits are readable and writable, so the user may modify these bits to disable all sources of interrupts below a given priority level. If IPL<2:0> = 3, for example, the CPU would not be interrupted by any source with a programmed priority level of 0, 1, 2 or 3. Trap events have higher priority than any user interrupt source. When the IPL3 bit is set, a trap event is in progress. The IPL3 bit can be cleared, but not set by the user. In some applications, it may be desirable to clear the IPL3 bit when a trap has occurred and branch to an instruction other than the instruction after the one that originally caused the trap to occur. All user interrupt sources can be disabled by setting IPL<2:0> = 111. 6.1.5 Interrupt Priority Each peripheral interrupt source can be assigned to one of seven priority levels. The user assignable interrupt priority control bits for each individual interrupt are located in the Least Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt. The usable priority levels start at ‘1’ as the lowest priority and level 7 as the highest priority. If the IPC bits associated with an interrupt source are all cleared, then the interrupt source is effectively disabled. Since more than one interrupt request source may be assigned to a specific priority level, a means is provided to resolve priority conflicts within a given user assigned level. Each source of interrupt has a natural order priority based on its location in the IVT. Table 6-2 shows the location of each interrupt source in the IVT. The lower numbered interrupt vectors have higher natural priority, while the higher numbered vectors have lower natural priority. The overall priority level for any pending source of interrupt is determined first by the user assigned priority of that source in the IPCx register, then by the natural order priority within the IVT. Natural order priority is used only to resolve conflicts between simultaneous pending interrupts with the same user assigned priority level. Once the priority conflict is resolved and the exception process begins, the CPU can only be interrupted by a source with higher user assigned priority. Interrupts with the same user assigned priority but a higher natural order priority, that become pending after the exception process begins, will remain pending until the current exception process completes. The ability for the user to assign each interrupt source to one of seven priority levels means that the user can give an interrupt with a low natural order priority a very high overall priority level. For example: the PLVD (Programmable Low Voltage Detect) can be given a priority of 7 and the INT0 (External Interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. Note: The IPL<2:0> bits become read only bits when interrupt nesting is disabled. See Section 6.2.4.2 ”Interrupt Nesting” for more information. Note: The peripherals and sources of interrupt available in the IVT will vary depending on the specific dsPIC30F device. The sources of interrupt shown in this document represent a comprehensive listing of all interrupt sources found on dsPIC30F devices. Refer to the specific device data sheet for further details. dsPIC30F Family Reference Manual DS70053C-page 6-6 © 2004 Microchip Technology Inc. 6.2 Non-Maskable Traps Traps can be considered as non-maskable, nestable interrupts which adhere to a fixed priority structure. Traps are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. If the user does not intend to take corrective action in the event of a trap error condition, these vectors must be loaded with the address of a software routine that will reset the device. Otherwise, the trap vector is programmed with the address of a service routine that will correct the trap condition. The dsPIC30F has four implemented sources of non-maskable traps: • Oscillator Failure Trap • Stack Error Trap • Address Error Trap • Arithmetic Error Trap Note that many of these trap conditions can only be detected when they happen. Consequently, the instruction that caused the trap is allowed to complete before exception processing begins. Therefore, the user may have to correct the action of the instruction that caused the trap. Each trap source has a fixed priority as defined by its position in the IVT. An oscillator failure trap has the highest priority, while an arithmetic error trap has the lowest priority (see Figure 6-1). In addition, trap sources are classified into two distinct categories: ‘Hard’ traps and ‘Soft’ traps. 6.2.1 Soft Traps The arithmetic error trap (priority level 11) and stack error trap (priority level 12) are categorized as ‘soft’ trap sources. Soft traps can be treated like non-maskable sources of interrupt that adhere to the priority assigned by their position in the IVT. Soft traps are processed like interrupts and require 2 cycles to be sampled and Acknowledged prior to exception processing. Therefore, additional instructions may be executed before a soft trap is Acknowledged. 6.2.1.1 Stack Error Trap (Soft Trap, Level 12) The stack is initialized to 0x0800 during Reset. A stack error trap will be generated should the stack pointer address ever be less than 0x0800. There is a Stack Limit register (SPLIM) associated with the stack pointer that is uninitialized at Reset. The stack overflow check is not enabled until a word write to SPLIM occurs. All Effective Addresses (EA) generated using W15 as a source or destination pointer are compared against the value in SPLIM. Should the EA be greater than the contents of the SPLIM register, then a stack error trap is generated. In addition, a stack error trap will be generated should the EA calculation wrap over the end of data space (0xFFFF). A stack error can be detected in software by polling the STKERR status bit (INTCON1<2>). To avoid re-entering the Trap Service Routine, the STKERR status flag must be cleared in software prior to returning from the trap with a RETFIE instruction. © 2004 Microchip Technology Inc. DS70053C-page 6-7 Section 6. Interrupts Interrupts 6 6.2.1.2 Arithmetic Error Trap (Soft Trap, Level 11) Any of the following events will cause an arithmetic error trap to be generated: • Accumulator A Overflow • Accumulator B Overflow • Catastrophic Accumulator Overflow • Divide by Zero • Shift Accumulator (SFTAC) operation exceeding +/-16 bits There are three enable bits in the INTCON1 register that enable the three types of accumulator overflow traps. The OVATE control bit (INTCON1<10>) is used to enable traps for an Accumulator A overflow event. The OVBTE control bit (INTCON1<9>) is used to enable traps for an Accumulator B overflow event. The COVTE control bit (INTCON1<8>) is used to enable traps for a catastrophic overflow of either accumulator. An Accumulator A or Accumulator B overflow event is defined as a carry-out from bit 31. Note that no accumulator overflow can occur if the 31-bit Saturation mode is enabled for the accumulator. A catastrophic accumulator overflow is defined as a carry-out from bit 39 of either accumulator. No catastrophic overflow can occur if accumulator saturation (31-bit or 39-bit) is enabled. Divide-by-zero traps cannot be disabled. The divide-by-zero check is performed during the first iteration of the REPEAT loop that executes the divide instruction. Accumulator shift traps cannot be disabled. The SFTAC instruction can be used to shift the accumulator by a literal value or a value in one of the W registers. If the shift value exceeds +/-16 bits, an arithmetic trap will be generated. The SFTAC instruction will execute, but the results of the shift will not be written to the target accumulator. An arithmetic error trap can be detected in software by polling the MATHERR status bit (INTCON1<4>). To avoid re-entering the Trap Service Routine, the MATHERR status flag must be cleared in software prior to returning from the trap with a RETFIE instruction. Before the MATHERR status bit can be cleared, all conditions that caused the trap to occur must also be cleared. If the trap was due to an accumulator overflow, the OA and OB status bits (SR<15:14>) must be cleared. The OA and OB status bits are read only, so the user software must perform a dummy operation on the overflowed accumulator (such as adding ‘0’) that will cause the hardware to clear the OA or OB status bit. 6.2.2 Hard Traps Hard traps include exceptions of priority level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category. Like soft traps, hard traps can also be viewed as non-maskable sources of interrupt. The difference between hard traps and soft traps is that hard traps force the CPU to stop code execution after the instruction causing the trap has completed. Normal program execution flow will not resume until after the trap has been Acknowledged and processed. 6.2.2.1 Trap Priority and Hard Trap Conflicts If a higher priority trap occurs while any lower priority trap is in progress, processing of the lower priority trap will be suspended and the higher priority trap will be Acknowledged and processed. The lower priority trap will remain pending until processing of the higher priority trap completes. Each hard trap that occurs must be Acknowledged before code execution of any type may continue. If a lower priority hard trap occurs while a higher priority trap is pending, Acknowledged, or is being processed, a hard trap conflict will occur. The conflict occurs because the lower priority trap cannot be Acknowledged until processing for the higher priority trap completes. The device is automatically reset in a hard trap conflict condition. The TRAPR status bit (RCON<15> ) is set when the Reset occurs, so that the condition may be detected in software. dsPIC30F Family Reference Manual DS70053C-page 6-8 © 2004 Microchip Technology Inc. 6.2.2.2 Oscillator Failure Trap (Hard Trap, Level 14) An oscillator failure trap event will be generated for any of the following reasons: • The Fail-Safe Clock Monitor (FSCM) is enabled and has detected a loss of the system clock source. • A loss of PLL lock has been detected during normal operation using the PLL. • The FSCM is enabled and the PLL fails to achieve lock at a Power-On Reset (POR). An oscillator failure trap event can be detected in software by polling the OSCFAIL status bit (INTCON1<1>), or the CF status bit (OSCCON<3>). To avoid re-entering the Trap Service Routine, the OSCFAIL status flag must be cleared in software prior to returning from the trap with a RETFIE instruction. Refer to Section 7. “Oscillator” and Section 24. “Device Configuration” for more information about the FSCM. 6.2.2.3 Address Error Trap (Hard Trap, Level 13) The following paragraphs describe operating scenarios that would cause an address error trap to be generated: 1. A misaligned data word fetch is attempted. This condition occurs when an instruction performs a word access with the LSb of the effective address set to ‘1’. The dsPIC30F CPU requires all word accesses to be aligned to an even address boundary. 2. A bit manipulation instruction using the Indirect Addressing mode with the LSb of the effective address set to ‘1’. 3. A data fetch from unimplemented data address space is attempted. 4. Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where literal is an unimplemented program memory address. 5. Executing instructions after modifying the PC to point to unimplemented program memory addresses. The PC may be modified by loading a value into the stack and executing a RETURN instruction. Data space writes will be inhibited whenever an address error trap occurs, so that data is not destroyed. An address error can be detected in software by polling the ADDRERR status bit (INTCON1<3>). To avoid re-entering the Trap Service Routine, the ADDRERR status flag must be cleared in software prior to returning from the trap with a RETFIE instruction. 6.2.3 Disable Interrupts Instruction The DISI (disable interrupts) instruction has the ability to disable interrupts for up to 16384 instruction cycles. This instruction is useful when time critical code segments must be executed. The DISI instruction only disables interrupts with priority levels 1-6. Priority level 7 interrupts and all trap events still have the ability to interrupt the CPU when the DISI instruction is active. The DISI instruction works in conjunction with the DISICNT register. When the DISICNT register is non-zero, priority level 1-6 interrupts are disabled. The DISICNT register is decremented on each subsequent instruction cycle. When the DISICNT register counts down to ‘0’, priority level 1-6 interrupts will be re-enabled. The value specified in the DISI instruction includes all cycles due to PSV accesses, instruction stalls, etc. The DISICNT register is readable and writable. The user can terminate the effect of a previous DISI instruction early by clearing the DISICNT register. The amount of time that interrupts are disabled can also be increased by writing to or adding to DISICNT. Note: In the MAC class of instructions, the data space is split into X and Y spaces. In these instructions, unimplemented X space includes all of Y space, and unimplemented Y space includes all of X space. © 2004 Microchip Technology Inc. DS70053C-page 6-9 Section 6. Interrupts Interrupts 6 Note that if the DISICNT register is zero, interrupts cannot be disabled by simply writing a non-zero value to the register. Interrupts must first be disabled by using the DISI instruction. Once the DISI instruction has executed and DISICNT holds a non-zero value, the interrupt disable time can be extended by modifying the contents of DISICNT. The DISI status bit (INTCON2<14>) is set whenever interrupts are disabled as a result of the DISI instruction. 6.2.4 Interrupt Operation All interrupt event flags are sampled during each instruction cycle. A pending Interrupt Request (IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSx register. The IRQ will cause an interrupt to occur if the corresponding bit in the Interrupt Enable (IECx) registers is set. For the rest of the instruction cycle in which the IRQ is sampled, the priorities of all pending interrupt requests are evaluated. No instruction will be aborted when the CPU responds to the IRQ. The instruction that was in progress when the IRQ is sampled will be completed before the ISR is executed. If there is a pending IRQ with a user assigned priority level greater than the current processor priority level, indicated by the IPL<2:0> status bits (SR<7:5>), an interrupt will be presented to the processor. The processor then saves the following information on the software stack: • the current PC value • the low byte of the Processor Status register (SRL) • the IPL3 status bit (CORCON<3>) These three values that are saved on the stack allow the return PC address value, MCU status bits, and the current processor priority level to be automatically saved. After the above information is saved on the stack, the CPU writes the priority level of the pending interrupt into the IPL<2:0> bit locations. This action will disable all interrupts of less than, or equal priority, until the Interrupt Service Routine (ISR) is terminated using the RETFIE instruction. Figure 6-2: Stack Operation for Interrupt Event 6.2.4.1 Return from Interrupt The RETFIE (Return from Interrupt) instruction will unstack the PC return address, IPL3 status bit, and SRL register to return the processor to the state and priority level prior to the interrupt sequence. Note: Software modification of the DISICNT register is not recommended. Note: The DISI instruction can be used to quickly disable all user interrupt sources if no source is assigned to CPU priority level 7. PC<15:0> PC<22:16> 15 0 W15 (before IRQ) W15 (after IRQ) Stack Grows Towards Higher Address SR<7:0> This stack location used to store the IPL3 status bit (CORCON<3>). dsPIC30F Family Reference Manual DS70053C-page 6-10 © 2004 Microchip Technology Inc. 6.2.4.2 Interrupt Nesting Interrupts, by default, are nestable. Any ISR that is in progress may be interrupted by another source of interrupt with a higher user assigned priority level. Interrupt nesting may be optionally disabled by setting the NSTDIS control bit (INTCON1<15>). When the NSTDIS control bit is set, all interrupts in progress will force the CPU priority to level 7 by setting IPL<2:0> = 111. This action will effectively mask all other sources of interrupt until a RETFIE instruction is executed. When interrupt nesting is disabled, the user assigned interrupt priority levels will have no effect, except to resolve conflicts between simultaneous pending interrupts. The IPL<2:0> bits become read only when interrupt nesting is disabled. This prevents the user software from setting IPL<2:0> to a lower value, which would effectively re-enable interrupt nesting. 6.2.5 Wake-up from Sleep and Idle Any source of interrupt that is individually enabled, using its corresponding control bit in the IECx registers, can wake-up the processor from Sleep or Idle mode. When the interrupt status flag for a source is set and the interrupt source is enabled via the corresponding bit in the IEC Control registers, a wake-up signal is sent to the dsPIC30F CPU. When the device wakes from Sleep or Idle mode, one of two actions may occur: 1. If the interrupt priority level for that source is greater than the current CPU priority level, then the processor will process the interrupt and branch to the ISR for the interrupt source. 2. If the user assigned interrupt priority level for the source is less than or equal the current CPU priority level, then the processor will simply continue execution, starting with the instruction immediately following the PWRSAV instruction that previously put the CPU in Sleep or Idle mode. 6.2.6 A/D Converter External Conversion Request The INT0 external interrupt request pin is shared with the A/D converter as an external conversion request signal. The INT0 interrupt source has programmable edge polarity, which is also available to the A/D converter external conversion request feature. 6.2.7 External Interrupt Support The dsPIC30F supports up to 5 external interrupt pin sources (INT0-INT4). Each external interrupt pin has edge detection circuitry to detect the interrupt event. The INTCON2 register has five control bits (INT0EP-INT4EP) that select the polarity of the edge detection circuitry. Each external interrupt pin may be programmed to interrupt the CPU on a rising edge or falling edge event. See Register 6-4 for further details. Note: User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Sleep or Idle mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater. © 2004 Microchip Technology Inc. DS70053C-page 6-11 Section 6. Interrupts Interrupts 6 6.3 Interrupt Processing Timing 6.3.1 Interrupt Latency for One-Cycle Instructions Figure 6-3 shows the sequence of events when a peripheral interrupt is asserted during a one-cycle instruction. The interrupt process takes four instruction cycles. Each cycle is numbered in the Figure for reference. The interrupt flag status bit is set during the instruction cycle after the peripheral interrupt occurs. The current instruction completes during this instruction cycle. In the second instruction cycle after the interrupt event, the contents of the PC and SRL registers are saved into a temporary buffer register. The second cycle of the interrupt process is executed as a NOP to maintain consistency with the sequence taken during a two-cycle instruction (see Section 6.3.2 ”Interrupt Latency for Two-Cycle Instructions”). In the third cycle, the PC is loaded with the vector table address for the interrupt source and the starting address of the ISR is fetched. In the fourth cycle, the PC is loaded with the ISR address. The fourth cycle is executed as a NOP while the first instruction in the ISR is fetched. Figure 6-3: Interrupt Timing During a One-Cycle Instruction 4 4 4 6 6 6 INST(PC-2) INST(PC) FNOP FNOP ISR INST Executed Interrupt Flag PUSH Low 16 bits of PC PUSH SRL and High 8 bits of PC 4 6 ISR + 2 ISR + 4 CPU Priority Fetch PC PC PC+2 2000 (ISR) 2002 2004 2006 Vector Save PC in Status bit Vector# Peripheral interrupt event occurs at or before midpoint TCY 1 2 3 4 temporary buffer. of this cycle. (from temporary buffer). (from temporary buffer). dsPIC30F Family Reference Manual DS70053C-page 6-12 © 2004 Microchip Technology Inc. 6.3.2 Interrupt Latency for Two-Cycle Instructions The interrupt latency during a two-cycle instruction is the same as during a one-cycle instruction. The first and second cycle of the interrupt process allow the two-cycle instruction to complete execution. The timing diagram in Figure 6-5 shows the case when the peripheral interrupt event occurs in the instruction cycle prior to execution of the two-cycle instruction. Figure 6-5 shows the timing when a peripheral interrupt is coincident with the first cycle of a two-cycle instruction. In this case, the interrupt process completes as for a one-cycle instruction (see Section 6.3.1 ”Interrupt Latency for One-Cycle Instructions”). Figure 6-4: Interrupt Timing During a Two-Cycle Instruction Figure 6-5: Interrupt Timing, Interrupt Occurs During 1st Cycle of a 2-Cycle Instruction 4 4 4 6 6 6 INST(PC-2) INST(PC) INST(PC) FNOP ISR INST Executed Interrupt Flag PUSH Low 16 bits of PC PUSH SRL and High 8 bits of PC 4 6 ISR + 2 ISR + 4 CPU Priority Fetch PC PC PC+2 2000 (ISR) 2002 2004 2006 Vector Save PC in Status bit Vector# Peripheral interrupt event occurs at or before TCY 1 2 3 4 1st cycle 2nd cycle temporary buffer. midpoint of this cycle. (from temporary buffer). (from temporary buffer). 4 4 4 6 6 6 INST(PC) INST(PC) FNOP ISR INST Executed Interrupt Flag PUSH Low 16 bits of PC PUSH SRL and High 8 bits of PC 4 6 ISR + 2 ISR + 4 CPU Priority Fetch PC PC PC + 2 2000 (ISR) 2002 2004 2006 Vector Save PC in Status bit Vector# Peripheral interrupt event occurs at or before TCY 1 2 3 4 1st cycle 2nd cycle temporary buffer. FNOP midpoint of this cycle. (from temporary buffer). (from temporary buffer). © 2004 Microchip Technology Inc. DS70053C-page 6-13 Section 6. Interrupts Interrupts 6 6.3.3 Returning from Interrupt The “Return from Interrupt” instruction, RETFIE, exits an interrupt or trap routine. During the first cycle of a RETFIE instruction, the upper bits of the PC and the SRL register are popped from the stack. The lower 16 bits of the stacked PC value are popped from the stack during the second cycle. The third instruction cycle is used to fetch the instruction addressed by the updated program counter. This cycle executes as a NOP. Figure 6-6: Return from Interrupt Timing 6.3.4 Special Conditions for Interrupt Latency The dsPIC30F allows the current instruction to complete when a peripheral interrupt source becomes pending. The interrupt latency is the same for both one and two-cycle instructions. However, there are certain conditions that can increase interrupt latency by one cycle, depending on when the interrupt occurs. The user should avoid these conditions if a fixed latency is critical to the application. These conditions are as follows: • A MOV.D instruction is executed that uses PSV to access a value in program memory space. • An instruction stall cycle is appended to any two-cycle instruction. • An instruction stall cycle is appended to any one-cycle instruction that performs a PSV access. • A bit test and skip instruction (BTSC, BTSS) uses PSV to access a value in the program memory space. 6 6 4 4 4 4 CPU Priority INST RETFIE RETFIE PC Executed ISR last FNOP 6 PC + 2 PC + 4 POP Low 16 bits of PC to RAM Stack. POP SRL and High 8 bits of PC. PC ISR ISR + 2 PC PC + 2 PC + 4 PC + 6 2nd cycle TCY instruction dsPIC30F Family Reference Manual DS70053C-page 6-14 © 2004 Microchip Technology Inc. 6.4 Interrupt Control and Status Registers The following registers are associated with the interrupt controller: • INTCON1, INTCON2 Registers Global interrupt control functions are derived from these two registers. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. • IFSx: Interrupt Flag Status Registers All interrupt request flags are maintained in the IFSx registers, where ‘x’ denotes the register number. Each source of interrupt has a Status bit, which is set by the respective peripherals or external signal and is cleared via software. • IECx: Interrupt Enable Control Registers All Interrupt Enable Control bits are maintained in the IECx registers, where ‘x’ denotes the register number. These control bits are used to individually enable interrupts from the peripherals or external signals. • IPCx: Interrupt Priority Control Registers Each user interrupt source can be assigned to one of eight priority levels. The IPC registers are used to set the interrupt priority level for each source of interrupt. • SR: CPU Status Register The SR is not specifically part of the interrupt controller hardware, but it contains the IPL<2:0> Status bits (SR<7:5>) that indicate the current CPU priority level. The user may change the current CPU priority level by writing to the IPL bits. • CORCON: Core Control Register The CORCON is not specifically part of the interrupt controller hardware, but it contains the IPL3 Status bit which indicates the current CPU priority level. IPL3 is a Read Only bit so that trap events cannot be masked by the user software. Each register is described in detail on the following pages. 6.4.1 Assignment of Interrupts to Control Registers The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 6-2. For example, the INT0 (External Interrupt 0) is shown as having vector number and a natural order priority of ‘0’. Thus, the INT0IF Status bit is found in IFS0<0>. The INT0 interrupt uses bit 0 of the IEC0 register as its Enable bit and the IPC0<2:0> bits assign the interrupt priority level for the INT0 interrupt. Note: The total number and type of interrupt sources will depend on the device variant. Refer to the specific device data sheet for further details. © 2004 Microchip Technology Inc. DS70053C-page 6-15 Section 6. Interrupts Interrupts 6 Register 6-1: SR: Status Register (In CPU) Register 6-2: CORCON: Core Control Register Upper Byte: R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0> RA N OV Z C bit 7 bit 0 bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU interrupt priority level. The value in parentheses indicates the IPL if IPL<3> = 1. 2: The IPL<2:0> status bits are read only when NSTDIS = 1 (INTCON1<15>). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Bit can be cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Upper Byte: U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL<1:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF bit 7 bit 0 bit 3 IPL3: CPU Interrupt Priority Level Status bit 3 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Bit can be cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-16 © 2004 Microchip Technology Inc. Register 6-3: INTCON1: Interrupt Control Register 1 Upper Byte: R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 NSTDIS — — — — OVATE OVBTE COVTE bit 15 bit 8 Lower Byte: U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-11 Unimplemented: Read as ‘0’ bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled bit 7-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-17 Section 6. Interrupts Interrupts 6 Register 6-4: INTCON2: Interrupt Control Register 2 Upper Byte: R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 Lower Byte: U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI is not active bit 13-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt #4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt #3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt #2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt #1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt #0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-18 © 2004 Microchip Technology Inc. Register 6-5: IFS0: Interrupt Flag Status Register 0 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 bit 15 CNIF: Input Change Notification Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 MI2CIF: I2C Bus Collision Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 SI2CIF: I2C Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 NVMIF: Non-Volatile Memory Write Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 ADIF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 SPI1IF: SPI1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2004 Microchip Technology Inc. DS70053C-page 6-19 Section 6. Interrupts Interrupts 6 Register 6-5: IFS0: Interrupt Flag Status Register 0 (Continued) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-20 © 2004 Microchip Technology Inc. Register 6-6: IFS1: Interrupt Flag Status Register 1 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF bit 7 bit 0 bit 15 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 C1IF: CAN1 (Combined) Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI2IF: SPI2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2004 Microchip Technology Inc. DS70053C-page 6-21 Section 6. Interrupts Interrupts 6 Register 6-6: IFS1: Interrupt Flag Status Register 1 (Continued) bit 1 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-22 © 2004 Microchip Technology Inc. Register 6-7: IFS2: Interrupt Flag Status Register 2 Upper Byte: U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLTBIF FLTAIF LVDIF DCIIF QEIIF bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWMIF C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF bit 7 bit 0 bit 15-13 Unimplemented: Read as ‘0’ bit 12 FLTBIF: Fault B Input Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 FLTAIF: Fault A Input Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 LVDIF: Programmable Low Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 DCIIF: Data Converter Interface Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 QEIIF: Quadrature Encoder Interface Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 PWMIF: Motor Control Pulse Width Modulation Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 C2IF: CAN2 (Combined) Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 OC8IF: Output Compare Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2004 Microchip Technology Inc. DS70053C-page 6-23 Section 6. Interrupts Interrupts 6 Register 6-7: IFS2: Interrupt Flag Status Register 2 (Continued) bit 1 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-24 © 2004 Microchip Technology Inc. Register 6-8: IEC0: Interrupt Enable Control Register 0 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 bit 15 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 MI2CIE: I2C Bus Collision Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 SI2CIE: I2C Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 NVMIE: Non-Volatile Memory Write Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 ADIE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 SPI1IE: SPI1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2004 Microchip Technology Inc. DS70053C-page 6-25 Section 6. Interrupts Interrupts 6 Register 6-8: IEC0: Interrupt Enable Control Register 0 (Continued) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-26 © 2004 Microchip Technology Inc. Register 6-9: IEC1: Interrupt Enable Control Register 1 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE bit 7 bit 0 bit 15 IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 C1IE: CAN1 (Combined) Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 SPI2IE: SPI2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2004 Microchip Technology Inc. DS70053C-page 6-27 Section 6. Interrupts Interrupts 6 Register 6-9: IEC1: Interrupt Enable Control Register 1 (Continued) bit 1 IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-28 © 2004 Microchip Technology Inc. Register 6-10: IEC2: Interrupt Enable Control Register 2 Upper Byte: U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLTBIE FLTAIE LVDIE DCIIE QEIIE bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWMIE C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE bit 7 bit 0 bit 15-13 Unimplemented: Read as ‘0’ bit 12 FLTBIE: Fault B Input Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 FLTAIE: Fault A Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 LVDIE: Programmable Low Voltage Detect Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 DCIIE: Data Converter Interface Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 QEIIE: Quadrature Encoder Interface Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 PWMIE: Motor Control Pulse Width Modulation Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 C2IE: CAN2 (Combined) Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 INT4IE: External Interrupt 4 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 INT3IE: External Interrupt 3 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 OC8IE: Output Compare Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2004 Microchip Technology Inc. DS70053C-page 6-29 Section 6. Interrupts Interrupts 6 Register 6-10: IEC2: Interrupt Enable Control Register 2 (Continued) bit 1 OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-30 © 2004 Microchip Technology Inc. Register 6-11: IPC0: Interrupt Priority Control Register 0 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP<2:0> — OC1IP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP<2:0> — INT0IP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-31 Section 6. Interrupts Interrupts 6 Register 6-12: IPC1: Interrupt Priority Control Register 1 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T3IP<2:0> — T2IP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC2IP<2:0> — IC2IP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-32 © 2004 Microchip Technology Inc. Register 6-13: IPC2: Interrupt Priority Control Register 2 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADIP<2:0> — U1TXIP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP<2:0> — SPI1IP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADIP<2:0>: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U1TXIP<0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPI1IP<2:0>: SPI1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-33 Section 6. Interrupts Interrupts 6 Register 6-14: IPC3: Interrupt Priority Control Register 3 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP<2:0> — MI2CIP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SI2CIP<2:0> — NVMIP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 MI2CIP<2:0>: I2C Bus Collision Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2CIP<2:0>: I2C Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 NVMIP<2:0>: Non-Volatile Memory Write Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-34 © 2004 Microchip Technology Inc. Register 6-15: IPC4: Interrupt Priority Control Register 4 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC3IP<2:0> — IC8IP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC7IP<2:0> — INT1IP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-35 Section 6. Interrupts Interrupts 6 Register 6-16: IPC5: Interrupt Priority Control Register 5 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP<2:0> — T5IP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP<2:0> — OC4IP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-36 © 2004 Microchip Technology Inc. Register 6-17: IPC6: Interrupt Priority Control Register 6 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — C1IP<2:0> — SPI2IP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP<2:0> — U2RXIP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: CAN1 (Combined) Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI2IP<2:0>: SPI2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-37 Section 6. Interrupts Interrupts 6 Register 6-18: IPC7: Interrupt Priority Control Register 7 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC6IP<2:0> — IC5IP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC4IP<2:0> — IC3IP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-38 © 2004 Microchip Technology Inc. Register 6-19: IPC8: Interrupt Priority Control Register 8 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC8IP<2:0> — OC7IP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC6IP<2:0> — OC5IP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-39 Section 6. Interrupts Interrupts 6 Register 6-20: IPC9: Interrupt Priority Control Register 9 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWMIP<2:0> — C2IP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT4IP<2:0> — INT3IP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWMIP<2:0>: Motor Control Pulse Width Modulation Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 C2IP<2:0>: CAN2 (Combined) Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-40 © 2004 Microchip Technology Inc. Register 6-21: IPC10: Interrupt Priority Control Register 10 Upper Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — FLTAIP<2:0> — LVDIP<2:0> bit 15 bit 8 Lower Byte: U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — DCIIP<2:0> — QEIIP<2:0> bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTAIP<2:0>: Fault A Input Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 LVDIP<2:0>: Programmable Low Voltage Detect Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 DCIIP<2:0>: Data Converter Interface Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 QEIIP<2:0>: Quadrature Encoder Interface Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-41 Section 6. Interrupts Interrupts 6 Register 6-22: IPC11: Interrupt Priority Control Register 11 Upper Byte: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 Lower Byte: U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — FLTBIP<2:0> bit 7 bit 0 bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 FLTBIP<2:0>: Fault B Input Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown dsPIC30F Family Reference Manual DS70053C-page 6-42 © 2004 Microchip Technology Inc. 6.5 Interrupt Setup Procedures 6.5.1 Initialization The following steps describe how to configure a source of interrupt: 1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx Control register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. 3. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx Status register. 4. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx Control register. 6.5.2 Interrupt Service Routine The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., C or assembler) and the language development tool suite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value, and old CPU priority level. 6.5.3 Trap Service Routine A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 6.5.4 Interrupt Disable All user interrupts can be disabled using the following procedure: 1. Push the current SR value onto the software stack using the PUSH instruction. 2. Force the CPU to priority level 7 by inclusive ORing the value 0xE0 with SRL. To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6, for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. Note: At a device Reset, the IPC registers are initialized, such that all user interrupt sources are assigned to priority level 4. Section 6. Interrupts Interrupts 6 © 2004 Microchip Technology Inc. DS70053C-page 6-43 Table 6-3: Special Function Registers Associated with Interrupt Controller SFR Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000 INTCON2 0082 ALTIVT — — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000 IFT0IF 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0 0000 0000 0000 0000 IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000 IFS2 0088 — — — FLTBIF FLTAIF LVDIF DCIIF QEIIF PWMIF C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF 0000 0000 0000 0000 IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000 IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000 IEC2 0090 — — — FLTBIE FLTAIE LVDIE DCIIE QEIIE PWMIE C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE 0000 0000 0000 0000 IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100 IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100 IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100 IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100 IPC4 009C — OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100 IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100 IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100 IPC7 00A2 — IC6IP<2:0> — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0> 0100 0100 0100 0100 IPC8 00A4 — OC8IP<2:0> — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0> 0100 0100 0100 0100 IPC9 00A6 — PWMIP<2:0> — C2IP<2:0> — INT41IP<2:0> — INT3IP<2:0> 0100 0100 0100 0100 IPC10 00A8 — FLTAIP<2:0> — LVDIP<2:0> — DCIIP<2:0> — QEIIP<2:0> 0100 0100 0100 0100 IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0> 0000 0000 0000 0100 Note: All interrupt sources and their associated control bits may not be available on a particular device. Refer to the device data sheet for details. dsPIC30F Family Reference Manual DS70053C-page 6-44 © 2004 Microchip Technology Inc. 6.6 Design Tips Question 1: What happens when two sources of interrupt become pending at the same time and have the same user assigned priority level? Answer: The interrupt source with the highest natural order priority will take precedence. The natural order priority is determined by the Interrupt Vector Table (IVT) address for that source. Interrupt sources with a smaller IVT address have a higher natural order priority. Question 2: Can the DISI instruction be used to disable all sources of interrupt and traps? Answer: The DISI instruction does not disable traps or priority level 7 interrupt sources. However, the DISI instruction can be used as a convenient way to disable all interrupt sources if no priority level 7 interrupt sources are enabled in the user’s application. © 2004 Microchip Technology Inc. DS70053C-page 6-45 Section 6. Interrupts Interrupts 6 6.7 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Interrupts module are: Title Application Note # No related application notes at this time. Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. dsPIC30F Family Reference Manual DS70053C-page 6-46 © 2004 Microchip Technology Inc. 6.8 Revision History Revision A This is the initial released revision of this document. Revision B This revision incorporates additional technical content for the dsPIC30F Interrupts module. Revision C This revision incorporates all known errata at the time of this document update. © 2005 Microchip Technology Inc. DS70054D-page 7-1 Oscillator 7 Section 7. Oscillator HIGHLIGHTS This section of the manual contains the following topics: 7.1 Introduction .................................................................................................................... 7-2 7.2 Device Clocking and MIPS ............................................................................................ 7-5 7.3 Oscillator Configuration.................................................................................................. 7-6 7.4 Oscillator Control Registers – OSCCON and OSCTUN .............................................. 7-13 7.5 Primary Oscillator......................................................................................................... 7-20 7.6 Crystal Oscillators/Ceramic Resonators ......................................................................7-22 7.7 Determining Best Values for Crystals, Clock Mode, C1, C2 and Rs............................ 7-24 7.8 External Clock Input..................................................................................................... 7-25 7.9 External RC Oscillator..................................................................................................7-26 7.10 Phase Locked Loop (PLL) ........................................................................................... 7-30 7.11 Low-Power 32 kHz Crystal Oscillator........................................................................... 7-31 7.12 Oscillator Start-up Timer (OST).................................................................................... 7-31 7.13 Internal Fast RC Oscillator (FRC)................................................................................ 7-31 7.14 Internal Low-Power RC (LPRC) Oscillator................................................................... 7-32 7.15 Fail-Safe Clock Monitor (FSCM) .................................................................................. 7-32 7.16 Programmable Oscillator Postscaler............................................................................ 7-33 7.17 Clock Switching Operation........................................................................................... 7-34 7.18 Design Tips .................................................................................................................. 7-38 7.19 Related Application Notes............................................................................................7-39 7.20 Revision History ........................................................................................................... 7-40 dsPIC30F Family Reference Manual DS70054D-page 7-2 © 2005 Microchip Technology Inc. 7.1 Introduction This section describes the operation of the oscillator system for dsPIC30F devices in the General Purpose, Sensor and Motor Control families. The oscillator system has the following modules and features: • Various external and internal oscillator options as clock sources • An on-chip PLL to boost internal operating frequency • Clock switching between various clock sources • Programmable clock postscaler for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures • Device clocking controlled by Special Function Registers as well as nonvolatile Configuration bits A simplified diagram of the oscillator system is shown in Figure 7-1. 7.1.1 Oscillator System Features Summary dsPIC30F devices in the General Purpose, Sensor and Motor Control families feature one of three versions of the oscillator system – VERSION 1, VERSION 2 and VERSION 3. The features of the three versions of the oscillator system are summarized in Table 7-1. . Note: Refer to the device data sheet to determine the version of the oscillator system featured on the dsPIC30F device you are using. Table 7-1: Device-Specific Oscillator System Feature Summary Oscillator System dsPIC30F Device Feature Summary VERSION 1 30F6010, 30F6011, 30F6012, 30F6013, 30F6014 Oscillator Sources: • Primary oscillator with Multiple Clock modes – XT, EC, HS • Secondary oscillator (Low-Power 32 kHz Crystal oscillator) • FRC oscillator: Fast Internal RC (7.37 MHz) • LPRC oscillator: Low-Power Internal RC (512 kHz) PLL Clock Multiplier: • 4 MHz-10 MHz input frequency range • 4x Multiplier mode (FOUT = 16 MHz-40 MHz) • 8x Multiplier mode (FOUT = 32 MHz-80 MHz) • 16x Multiplier mode (FOUT = 64 MHz-120 MHz) • PLL VCO lock indication plus ‘out of lock’ trap option • PLL input provided by the following sources: - XT or EC Primary oscillator Clock Scaling Options: Generic postscaler for device clock (divide by 4, 16, 64) Fail-Safe Clock Monitor (FSCM): Detects clock failure and switches over to internal FRC oscillator VERSION 2 30F2010, 30F4011, 30F4012, 30F5011, 30F5013 Oscillator System VERSION 2 adds the following capabilities to VERSION 1: • Internal FRC oscillator may also be provided as an input to the PLL to allow fast execution while eliminating the need for an external clock source (This feature is applicable to all devices other than the 30F2010) • User tuning capability added for the Internal FRC oscillator © 2005 Microchip Technology Inc. DS70054D-page 7-3 Section 7. Oscillator Oscillator 7 VERSION 3 30F2011, 30F2012, 30F3010, 30F3011, 30F3012, 30F3013, 30F3014, 30F4013, 30F5015, 30F5016, 30F6010A, 30F6011A, 30F6012A, 30F6013A, 30F6014A, 30F6015 Oscillator System VERSION 3 adds the following capabilities to VERSION 2: • HS oscillator may also be provided as an input to the PLL to allow greater choices of crystal frequency Table 7-1: Device-Specific Oscillator System Feature Summary Oscillator System dsPIC30F Device Feature Summary dsPIC30F Family Reference Manual DS70054D-page 7-4 © 2005 Microchip Technology Inc. Figure 7-1: Oscillator System Block Diagram Primary OSC1 OSC2 SOSCO SOSCI Oscillator Secondary Clock and Control Block Switching x4, x8, x16 PLL Primary Oscillator Stability Detector Stability Detector Secondary Oscillator Programmable Clock Divider Oscillator Start-up Timer Fail-Safe Clock Monitor (FSCM) Internal Fast RC Oscillator (FRC) Internal Low Power RC Oscillator (LPRC) PWRSAV Instruction Wake-up Request Oscillator Configuration bits Oscillator Trap to Timer1 LPRC FRC Secondary Osc POR Primary Osc PLL Oscillator 32 kHz FOSC(1) (2) Note 1: The system clock output, FOSC, is divided by 4 to get the instruction cycle clock. 2: Devices that feature VERSION 2 or VERSION 3 of the Oscillator System allow the internal FRC oscillator to be connected to the PLL. © 2005 Microchip Technology Inc. DS70054D-page 7-5 Section 7. Oscillator Oscillator 7 7.2 Device Clocking and MIPS Referring to Figure 7-1, the system clock source can be provided by one of four sources. These sources are the Primary oscillator, Secondary oscillator, Internal Fast RC (FRC) oscillator or the Low-Power RC (LPRC) oscillator. The Primary oscillator source has the option of using the internal PLL. The frequency of the selected clock source can optionally be reduced by the programmable postscaler (clock divider). The output from the programmable postscaler becomes the system clock source, FOSC. The system clock source is divided by four to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/4. The timing diagram in Figure 7-2 shows the relationship between the system clock source and instruction execution. The internal instruction cycle clock, FCY, can be provided on the OSC2 I/O pin for some Operating modes of the Primary oscillator (see Section 7.3 “Oscillator Configuration”). Figure 7-2: Clock/Instruction Cycle Timing Equation 7-1: MIPS and Source Oscillator Frequency Relationship FOSC PC FCY PC PC + 2 PC + 4 Fetch INST (PC) Execute INST (PC - 2) Fetch INST (PC + 2) Execute INST (PC) Fetch INST (PC + 4) Execute INST (PC + 2) TCY FCY = SOURCE OSCILLATOR FREQUENCY * PLL MULTIPLIER PROGRAMMABLE POSTSCALER * 4 ( ) FOSC 4 = dsPIC30F Family Reference Manual DS70054D-page 7-6 © 2005 Microchip Technology Inc. 7.3 Oscillator Configuration The oscillator source (and Operating mode) that is used at a device Power-on Reset event is selected using nonvolatile Configuration bits. The oscillator Configuration bits are located in the FOSC Configuration register. The FOS bits in the FOSC nonvolatile Configuration register select the oscillator source that is used at a Power-on Reset. The Primary oscillator is the default (unprogrammed) selection. The Secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The FPR bits in the FOSC nonvolatile Configuration register select the Operating mode of the Primary oscillator. dsPIC30F devices in the General Purpose, Sensor and Motor Control families may feature one of three versions of the Oscillator system. The definition of the FOSC nonvolatile Configuration register varies between these versions, as described in the sub-sections below. 7.3.1 Oscillator System VERSION 1 Configuration For devices that feature the Oscillator system VERSION 1, the FOSC nonvolatile Configuration register is shown in Register 7-1. The operating modes for the FPR bits may be selected as shown in Table 7-2. 7.3.2 Oscillator System VERSION 2 Configuration For devices that feature the Oscillator system VERSION 2, the FOSC nonvolatile Configuration register is shown in Register 7-2. The operating modes for the FPR bits may be selected as shown in Table 7-3. 7.3.3 Oscillator System VERSION 3 Configuration For devices that feature the Oscillator system VERSION 3, the FOSC nonvolatile Configuration register is shown in Register 7-3. The operating modes for the FPR bits may be selected as shown in Table 7-4. 7.3.4 Clock Switching Mode Configuration Bits The FCKSM<1:0> Configuration bits (FOSC<15:14>) are used to enable/disable device clock switching and the Fail-Safe Clock Monitor (FSCM). When these bits are unprogrammed (default), clock switching and the FSCM are disabled. These bits carry the same definition and functionality across all versions of the Oscillator system. © 2005 Microchip Technology Inc. DS70054D-page 7-7 Section 7. Oscillator Oscillator 7 Register 7-1: FOSC: Oscillator Configuration Register for Oscillator System VERSION 1 Upper Byte: U U U U UUU U — — — — — — — — bit 23 bit 16 Middle Byte: R/P R/P U U U U R/P R/P FCKSM<1:0> — — — — FOS<1:0> bit 15 bit 8 Lower Byte: U U U U R/P R/P R/P R/P — — — — FPR<3:0> bit 7 bit 0 bit 23-16 Unimplemented: Read as ‘0’ bit 15-14 FCKSM<1:0>: Clock Switching Mode Selection Fuses bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9-8 FOS<1:0>: Oscillator Source Selection on POR bits 11 = Primary Oscillator (Primary Oscillator mode selected by FPR<3:0>) 10 = Internal Low-Power RC Oscillator 01 = Internal Fast RC Oscillator 00 = Low-Power 32 kHz Oscillator (Timer1 oscillator) bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 FPR<3:0>: Oscillator Selection within Primary Group bits, See Table 7-2 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit dsPIC30F Family Reference Manual DS70054D-page 7-8 © 2005 Microchip Technology Inc. Table 7-2: Oscillator System VERSION 1: Configuration Bit Values for Clock Selection Oscillator Mode Oscillator Source FOS<1:0> FPR<3:0> OSC2 Pin Function EC w/ PLL 16x Primary 1 11111 I/O (Note 4) EC w/ PLL 8x Primary 1 11110 I/O EC w/ PLL 4x Primary 1 11101 I/O ECIO Primary 1 11100 I/O EC Primary 1 11011 FOSC/4 Reserved Primary 1 11010 n/a ERC Primary 1 11001 FOSC/4 ERCIO Primary 1 11000 I/O XT w/ PLL 16x Primary 1 10111 (Note 3) XT w/ PLL 8x Primary 1 10110 (Note 3) XT w/ PLL 4x Primary 1 10101 (Note 3) XT Primary 1 10100 (Note 3) HS Primary 1 1001x (Note 3) XTL Primary 1 1000x (Note 3) LP Secondary 0 0 ———— (Notes 1, 2) FRC Internal 0 1 ———— (Notes 1, 2) LPRC Internal 1 0 ———— (Notes 1, 2) Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0> Configuration bits). 2: Note that OSC1 pin cannot be used as an I/O pin, even if the Secondary oscillator or an internal clock source is selected at all times. 3: In these Oscillator modes, a crystal is connected between the OSC1 and OSC2 pins. 4: This is the default Oscillator mode for an unprogrammed (erased) device. An unprogrammed Configuration bit has a value of ‘1’. 5: XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal) 6: XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal) 7: HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal) © 2005 Microchip Technology Inc. DS70054D-page 7-9 Section 7. Oscillator Oscillator 7 Register 7-2: FOSC: Oscillator Configuration Register for Oscillator System VERSION 2 Upper Byte: U U U U UUU U — — — — — — — — bit 23 bit 16 Middle Byte: R/P R/P U U U U R/P R/P FCKSM<1:0> — — — — FOS<1:0> bit 15 bit 8 Lower Byte: U U U U R/P R/P R/P R/P — — — — FPR<3:0> bit 7 bit 0 bit 23-16 Unimplemented: Read as ‘0’ bit 15-14 FCKSM<1:0>: Clock Switching Mode Selection Fuses bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9-8 FOS<1:0>: Oscillator Source Selection on POR bits 11 = Primary Oscillator (Primary Oscillator mode selected by FPR<3:0>) 10 = Internal Low-Power RC Oscillator 01 = Internal Fast RC Oscillator 00 = Low-Power 32 kHz Oscillator (Timer1 oscillator) bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 FPR<3:0>: Oscillator Mode Selection within Primary Group bits, See Table 7-3 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit dsPIC30F Family Reference Manual DS70054D-page 7-10 © 2005 Microchip Technology Inc. Table 7-3: Oscillator System VERSION 2: Configuration Bit Values for Clock Selection: Oscillator Mode Oscillator Source FOS<1:0> FPR<3:0> OSC2 Pin Function EC Primary 1 11011 CLKO ECIO Primary 1 11100 I/O EC w/PLL 4x Primary 1 11101 I/O EC w/PLL 8x Primary 1 11110 I/O EC w/PLL 16x Primary 1 11111 I/O (Note 4) ERC Primary 1 11001 CLKO ERCIO Primary 1 11000 I/O XT Primary 1 10100 (Note 3) XT w/PLL 4x Primary 1 10101 (Note 3) XT w/PLL 8x Primary 1 10110 (Note 3) XT w/PLL 16x Primary 1 10111 (Note 3) XTL Primary 1 10000 (Note 3) HS Primary 1 10010 (Note 3) FRC w/PLL 4x Primary 1 10001 I/O FRC w/PLL 8x Primary 1 11010 I/O FRC w/PLL 16x Primary 1 10011 I/O LP Secondary 0 0 ———— (Notes 1, 2) FRC Internal FRC 0 1 ———— (Notes 1, 2) LPRC Internal LPRC 1 0 ———— (Notes 1, 2) Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0>). 2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock source is selected at all times. 3: In these Oscillator modes, a crystal is connected between the OSC1 and OSC2 pins. 4: This is the default Oscillator mode for an unprogrammed (erased) device. An unprogrammed Configuration bit has a value of ‘1’. 5: XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal) 6: XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal) 7: HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal) © 2005 Microchip Technology Inc. DS70054D-page 7-11 Section 7. Oscillator Oscillator 7 Register 7-3: FOSC: Oscillator Configuration Register for Oscillator System VERSION 3 Upper Byte: U U U U UUU U — — — — — — — — bit 23 bit 16 Middle Byte: R/P R/P U U U R/P R/P R/P FCKSM<1:0> — — — FOS<2:0> bit 15 bit 8 Lower Byte: U U U R/P R/P R/P R/P R/P — — — FPR<4:0> bit 7 bit 0 bit 23-16 Unimplemented: Read as ‘0’ bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9-8 FOS<2:0>: Oscillator Group Selection on POR bit 111 = PLL Oscillator; PLL source selected by FPR<4:0> bits 011 = EXT: External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0> bits 010 = LPRC: Internal Low-Power RC 001 = FRC: Internal Fast RC 000 = LPOSC: Low-Power Crystal Oscillator; SOSCI/SOSCO pins bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 FPR<4:0>: Oscillator Selection within Primary Group bits, See Table 7-4. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ dsPIC30F Family Reference Manual DS70054D-page 7-12 © 2005 Microchip Technology Inc. Table 7-4: Oscillator System VERSION 3: Configuration Bit Values for Clock Selection Oscillator Mode Oscillator Source FOS<2:0> FPR<4:0> OSC2 Pin Function ECIO w/ PLL 4x PLL 1 1 101101 I/O ECIO w/ PLL 8x PLL 1 1 101110 I/O ECIO w/ PLL 16x PLL 1 1 101111 I/O FRC w/ PLL 4x PLL 1 1 100001 I/O FRC w/ PLL 8x PLL 1 1 101010 I/O FRC w/ PLL 16x PLL 1 1 100011 I/O XT w/ PLL 4x PLL 1 1 100101 (Note 3) XT w/ PLL 8x PLL 1 1 100110 (Note 3) XT w/ PLL 16x PLL 1 1 100111 (Note 3) HS2 w/ PLL 4x PLL 1 1 110001 (Note 3) HS2 w/ PLL 8x PLL 1 1 110010 (Note 3) HS2 w/ PLL 16x PLL 1 1 110011 (Note 3) HS3 w/ PLL 4x PLL 1 1 110101 (Note 3) HS3 w/ PLL 8x PLL 1 1 110110 (Note 3) HS3 w/ PLL 16x PLL 1 1 110111 (Note 3) ECIO External 0 1 101100 I/O XT External 0 1 100100 (Note 3) HS External 0 1 100010 (Note 3) EC External 0 1 101011 CLKOUT ERC External 0 1 101001 CLKOUT ERCIO External 0 1 101000 I/O XTL External 0 1 100000 (Note 3) LP Secondary 0 0 0xxxxx (Note 1, 2) FRC Internal FRC 0 0 1xxxxx (Note 1, 2) LPRC Internal LPRC 0 1 0xxxxx (Note 1, 2) Note 1: OSC2 pin function is determined by (FPR<4:0>). 2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is selected at all times. 3: In these Oscillator modes, a crystal is connected between the OSC1 and OSC2 pins. 4: XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal) 5: XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal) 6: HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal) © 2005 Microchip Technology Inc. DS70054D-page 7-13 Section 7. Oscillator Oscillator 7 7.4 Oscillator Control Registers – OSCCON and OSCTUN Run-time control and status of the Oscillator system is provided to the user via Special Function Registers. Table 7-5 summarizes the run-time control features provided in VERSION 1, VERSION 2 and VERSION 3 of the Oscillator System. Refer to the device data sheet to determine the version of the oscillator system featured on the dsPIC30F device you are using. The OSCCON Control register provides control of clock switching and clock source status information. The COSC Status bits in OSCCON are read-only bits that indicate the oscillator source that the device is operating from. The COSC bits are set to the FOS Configuration bit values at a Power-on Reset and will change to indicate the new oscillator source at the end of a clock switch operation. The NOSC Status bits in OSCCON are control bits that select the new clock source for a clock switch operation. The NOSC bits are set to the FOS Configuration bit values at a Power-on Reset or Brown-out Reset and are modified by the user software during a clock switch operation. The POST<1:0> control bits (OSCCON<8:7>) control the system clock divide ratio. The LOCK Status bit (OSCCON<5>) is read-only and indicates the status of the PLL circuit. The CF Status bit (OSCCON<3>) is a readable/writable Status bit that indicates a clock failure. The LPOSCEN control bit (OSCCON<1>) is used to enable or disable the 32 kHz Low-Power Crystal oscillator. The OSWEN control bit (OSCCON<0>) is used to initiate a clock switch operation. The OSWEN bit is cleared automatically after a successful clock switch. The TUN<3:0> bits allow the user to tune the internal FRC oscillator to frequencies higher and lower than the nominal value of 7.37 MHz. 7.4.1 Protection Against Accidental Writes to OSCCON A write to the OSCCON register is intentionally made difficult, because it controls clock switching and clock scaling. To write to the OSCCON low byte, the following code sequence must be executed without any other instructions in between: Byte Write 0x46 to OSCCONL Byte Write 0x57 to OSCCONL After this sequence, a byte write to OSCCONL is allowed for one instruction cycle. Write the desired value or use a bit manipulation instruction. To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write 0x78 to OSCCONH Byte Write 0x9A to OSCCONH After this sequence, a byte write is allowed to OSCCONH for one instruction cycle. Write the desired value or use a bit manipulation instruction. Table 7-5: Oscillator Control SFRs Oscillator System Oscillator Control SFRs Feature Summary VERSION 1 Control via OSCCON SFR. Refer to Register 7-4. VERSION 2 Control via OSCCON SFR. User may tune the FRC oscillator via TUN<3:0> bits in OSCCON. Refer to Register 7-5. VERSION 3 Control via OSCCON and OSCTUN SFRs. User may tune the FRC oscillator via TUN<3:0> bits in OSCTUN. Refer to Register 7-6 and Register 7-7. Note: The OSCCON register is write-protected because it controls the device clock switching mechanism. See Section 7.4.1 “Protection Against Accidental Writes to OSCCON” for instructions on writing to OSCCON. dsPIC30F Family Reference Manual DS70054D-page 7-14 © 2005 Microchip Technology Inc. Register 7-4: OSCCON: Oscillator Control Register – Oscillator System VERSION 1 Upper Byte: U-0 U-0 R-y R-y U-0 U-0 R/W-y R/W-y — — COSC<1:0> — — NOSC<1:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 R/W-0 R/W-0 POST<1:0> LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 COSC<1:0>: Current Oscillator Source Status bits 11 = Primary oscillator 10 = Internal LPRC oscillator 01 = Internal FRC oscillator 00 = Low-Power 32 kHz Crystal oscillator (Timer1) bit 11-10 Unimplemented: Read as ‘0’ bit 9-8 NOSC<1:0>: New Oscillator Group Selection bits 11 = Primary oscillator 10 = Internal LPRC oscillator 01 = Internal FRC oscillator 00 = Low-Power 32 kHz Crystal oscillator (Timer1) bit 7-6 POST<1:0>: Oscillator Postscaler Selection bits 11 = Oscillator postscaler divides clock by 64 10 = Oscillator postscaler divides clock by 16 01 = Oscillator postscaler divides clock by 4 00 = Oscillator postscaler does not alter clock bit 5 LOCK: PLL Lock Status bit 1 = Indicates that PLL is in lock 0 = Indicates that PLL is out of lock (or disabled) Reset on POR or BOR Reset when a valid clock switching sequence is initiated Set when PLL lock is achieved after a PLL start Reset when lock is lost Read zero when PLL is not selected as a system clock bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Status bit 1 = FSCM has detected a clock failure 0 = FSCM has not detected a clock failure Reset on POR or BOR Reset when a valid clock switching sequence is initiated Set when clock fail detected bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: 32 kHz LP Oscillator Enable bit 1 = LP oscillator is enabled 0 = LP oscillator is disabled Reset on POR or BOR bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<1:0> bits 0 = Oscillator switch is complete Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown y = Value set from Configuration bits on POR or BOR © 2005 Microchip Technology Inc. DS70054D-page 7-15 Section 7. Oscillator Oscillator 7 Register 7-5: OSCCON: Oscillator Control Register – Oscillator System VERSION 2 Upper Byte: R/W-0 R/W-0 R-y R-y R/W-0 R/W-0 R/W-y R/W-y TUN3 TUN2 COSC<1:0> TUN1 TUN0 NOSC<1:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 R/W-0 R/W-0 POST<1:0> LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 bit 15-14 TUN<3:2>: Upper 2 bits of the TUN bit-field. Refer to the description of TUN<1:0> (OSCCON<11:10>) bits for details. bit 13-12 COSC<1:0>: Current Oscillator Source Status bits 11 = Primary oscillator 10 = Internal LPRC oscillator 01 = Internal FRC oscillator 00 = Low-Power 32 kHz Crystal oscillator (Timer1) bit 11-10 TUN<1:0>: Lower 2 bits of the TUN bit-field. The four bit field specified by TUN<3:0> allows the user to tune the Internal Fast RC oscillator which has a nominal frequency of 7.37 MHz. For example, the user may be able to tune the frequency of the FRC oscillator within a range of +/- 12% (or 960 kHz) in steps of 1.5% around the factory-calibrated frequency setting, as follows: TUN<3:0> = 0111 provides the highest frequency ...... TUN<3:0> = 0000 provides the factory-calibrated frequency ...... TUN<3:0> = 1000 provides the lowest frequency Note: Refer to the device-specific data sheet for the exact tuning range and tuning step size for the FRC oscillator on your device. bit 9-8 NOSC<1:0>: New Oscillator Group Selection bits 11 = Primary oscillator 10 = Internal LPRC oscillator 01 = Internal FRC oscillator 00 = Low-Power 32 kHz Crystal oscillator (Timer1) bit 7-6 POST<1:0>: Oscillator Postscaler Selection bits 11 = Oscillator postscaler divides clock by 64 10 = Oscillator postscaler divides clock by 16 01 = Oscillator postscaler divides clock by 4 00 = Oscillator postscaler does not alter clock bit 5 LOCK: PLL Lock Status bit 1 = Indicates that PLL is in lock 0 = Indicates that PLL is out of lock (or disabled) Reset on POR or BOR Reset when a valid clock switching sequence is initiated Set when PLL lock is achieved after a PLL start Reset when lock is lost Read zero when PLL is not selected as a system clock bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Status bit 1 = FSCM has detected a clock failure 0 = FSCM has not detected a clock failure Reset on POR or BOR Reset when a valid clock switching sequence is initiated Set when clock fail detected bit 2 Unimplemented: Read as ‘0’ dsPIC30F Family Reference Manual DS70054D-page 7-16 © 2005 Microchip Technology Inc. OSCCON: Oscillator Control Register – Oscillator System VERSION 2 (Continued) bit 1 LPOSCEN: 32 kHz LP Oscillator Enable bit 1 = LP oscillator is enabled 0 = LP oscillator is disabled Reset on POR or BOR bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<1:0> bits 0 = Oscillator switch is complete Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown y = Value set from Configuration bits on POR or BOR © 2005 Microchip Technology Inc. DS70054D-page 7-17 Section 7. Oscillator Oscillator 7 Register 7-6: OSCCON: Oscillator Control Register – Oscillator System VERSION 3 Upper Byte: U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y — COSC<2:0> — NOSC<2:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 R/W-0 R/W-0 POST<1:0> LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Group Selection bits (Read-Only) 111 = PLL Oscillator; PLL source selected by FPR<4:0> bits 011 = External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0> bits 010 = LPRC internal low-power RC 001 = FRC internal fast RC 000 = LP crystal oscillator; SOSCI/SOSCO pins Set to FOS<2:0> values on POR or BOR Loaded with NOSC<2:0> at the completion of a successful clock switch Set to FRC value when FSCM detects a failure and switches clock to FRC bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Group Selection bits 111 = PLL Oscillator; PLL source selected by FPR<4:0> bits 011 = External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0> bits 010 = LPRC internal low-power RC 001 = FRC internal fast RC 000 = LP crystal oscillator; SOSCI/SOSCO pins Set to FOS<2:0> values on POR or BOR bit 7-6 POST<1:0>: Oscillator Postscaler Selection bits 11 = Oscillator postscaler divides clock by 64 10 = Oscillator postscaler divides clock by 16 01 = Oscillator postscaler divides clock by 4 00 = Oscillator postscaler does not alter clock bit 5 LOCK: PLL Lock Status bit (Read-Only) 1 = Indicates that PLL is in lock 0 = Indicates that PLL is out of lock (or disabled) Reset on POR or BOR Reset when a valid clock switching sequence is initiated Set when PLL lock is achieved after a PLL start Reset when lock is lost Read zero when PLL is not selected as a system clock bit 4 Unimplemented: Read as ‘0’ dsPIC30F Family Reference Manual DS70054D-page 7-18 © 2005 Microchip Technology Inc. OSCCON: Oscillator Control Register – Oscillator System VERSION 3 (Continued) bit 3 CF: Clock Fail Detect bit (Read/Clearable by application) 1 = FSCM has detected clock failure 0 = FSCM has NOT detected clock failure Reset on POR or BOR Reset when a valid clock switching sequence is initiated Set when clock fail detected bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: 32 kHz Secondary (LP) Oscillator Enable bit 1 = Secondary Oscillator is enabled 0 = Secondary Oscillator is disabled Reset on POR or BOR bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request Oscillator switch to selection specified by NOSCG<2:0> bits 0 = Oscillator switch is complete Reset on POR or BOR Reset after a successful clock switch Reset after a redundant clock switch (i.e., a clock switch operation is requested to the current oscillator) Reset after FSCM switches the oscillator to (Group 1) FRC Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown y = Value set from Configuration bits on POR © 2005 Microchip Technology Inc. DS70054D-page 7-19 Section 7. Oscillator Oscillator 7 Register 7-7: OSCTUN: FRC Oscillator Tuning Register – Oscillator System VERSION 3 Only Upper Byte: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 Lower Byte: U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — TUN<3:0> bit 7 bit 0 bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 TUN<3:0>: The four bit field specified by TUN<3:0> allows the user to tune the Internal Fast RC oscillator which has a nominal frequency of 7.37 MHz. TUN<3:0> = 0111 provides the highest frequency ...... TUN<3:0> = 0000 provides the factory-calibrated frequency ...... TUN<3:0> = 1000 provides the lowest frequency Note 1: Refer to the device-specific data sheet for the exact tuning range and tuning step size for the FRC oscillator on your device. 2: Certain devices may have more than four TUN bits. Refer to the device-specific data sheet to identify the number of TUN bits available to the user for tuning the FRC oscillator. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown y = Value set from Configuration bits on POR dsPIC30F Family Reference Manual DS70054D-page 7-20 © 2005 Microchip Technology Inc. 7.5 Primary Oscillator The Primary oscillator is available on the OSC1 and OSC2 pins of the dsPIC30F device family. The Primary oscillator has a wide variety of operation modes summarized in Table 7-6. In general, the Primary oscillator can be configured for an external clock input, external RC network, or an external crystal. Further details of the Primary Oscillator Operating modes are described in subsequent sections. The FPR bits in the FOSC nonvolatile Configuration register select the Operating mode of the Primary oscillator. Table 7-6: Primary Oscillator Operating Modes Oscillator Mode(4) Description XTL 200 kHz-4 MHz crystal on OSC1:OSC2. XT 4 MHz-10 MHz crystal on OSC1:OSC2. XT w/ PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled. XT w/ PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled. XT w/ PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled(1). LP 32 kHz crystal on SOSCO:SOSCI(2). HS 10 MHz-25 MHz crystal. HS/2 w/PLL 4x 10 MHz -25 MHz crystal, divide by 2, 4x PLL enabled. HS/2 w/ PLL 8x 10 MHz-25MHz crystal, divide by 2, 8x PLL enabled. HS/2 w/ PLL 16x 10 MHz-25MHz crystal, divide by 2, 16x PLL enabled(1). HS/3 w/PLL 4x 10 MHz-25 MHz crystal, divide by 3, 4x PLL enabled. HS/3 w/ PLL 8x 10 MHz-25MHz crystal, divide by 3, 8x PLL enabled. HS/3 w/ PLL 16x 10 MHz-25MHz crystal, divide by 3, 16x PLL enabled(1). EC External clock input (0-40 MHz). ECIO External clock input (0-40 MHz), OSC2 pin is I/O. EC w/ PLL 4x External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled(1). EC w/ PLL 8x External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled(1). EC w/ PLL 16x External clock input (4-10 MHz), OSC2 pin is I/O, 16x PLL enabled(1). ERC External RC oscillator, OSC2 pin is FOSC/4 output(3). ERCIO External RC oscillator, OSC2 pin is I/O(3). FRC 7.37 MHz internal Fast RC oscillator. FRC w/ PLL 4x 7.37 MHz Internal Fast RC oscillator, 4x PLL enabled. FRC w/ PLL 8x 7.37 MHz Internal Fast RC oscillator, 8x PLL enabled. FRC w/ PLL 16x 7.37 MHz Internal Fast RC oscillator, 16x PLL enabled. LPRC 512 kHz internal Fast RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met. 2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation up to 4 MHz. 4: This table lists a cumulative set of operating modes featured in Oscillator system VERSION 1, VERSION 2 and VERSION 3. © 2005 Microchip Technology Inc. DS70054D-page 7-21 Section 7. Oscillator Oscillator 7 7.5.1 Oscillator Mode Selection Guidelines The main difference between the XT, XTL and HS modes is the gain of the internal inverter of the oscillator circuit, which allows the different frequency ranges. In general, use the oscillator option with the lowest possible gain that still meets specifications. This will result in lower dynamic currents (IDD). The frequency range of each Oscillator mode is the recommended frequency cutoff, but the selection of a different Gain mode is acceptable as long as a thorough validation is performed (voltage, temperature and component variations, such as resistor, capacitor and internal oscillator circuitry). The oscillator feedback circuit is disabled in all EC and ECIO modes. The OSC1 pin is a high impedance input and can be driven by a CMOS driver. The ERC and ERCIO modes provide the least expensive solution for device oscillation (only an external resistor and capacitor is required). These modes also provide the most variation in the oscillation frequency. If the Primary oscillator is configured for an external clock input or an external RC network, the OSC2 pin is not required to support the oscillator function. For these modes, the OSC2 pin can be used as an additional device I/O pin or a clock output pin. When the OSC2 pin is used as a clock output pin, the output frequency is FOSC/4. The XTL mode is a Low Power/Low Frequency mode. This mode of the oscillator consumes the least amount of power of the three Crystal modes. The XT mode is a Medium Power/Medium Frequency mode and HS mode provides the highest oscillator frequencies with a crystal. The EC and XT modes that use the PLL circuit provide the highest device operating frequencies. The oscillator circuit will consume the most current in these modes because the PLL is enabled to multiply the frequency of the oscillator. dsPIC30F Family Reference Manual DS70054D-page 7-22 © 2005 Microchip Technology Inc. 7.6 Crystal Oscillators/Ceramic Resonators In XT, XTL and HS modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 7-3). The dsPIC30F oscillator design requires the use of a parallel cut crystal. Using a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. Figure 7-3: Crystal or Ceramic Resonator Operation (XT, XT or HS Oscillator Mode) 7.6.1 Oscillator/Resonator Start-up As the device voltage increases from VSS, the oscillator will start its oscillations.The time required for the oscillator to start oscillating depends on many factors. These include: • Crystal/resonator frequency • Capacitor values used (C1 and C2 in Figure 7-3) • Device VDD rise time • System temperature • Series resistor value and type if used (Rs in Figure 7-3) • Oscillator mode selection of device (selects the gain of the internal oscillator inverter) • Crystal quality • Oscillator circuit layout • System noise Figure 7-4 shows a plot of a typical oscillator/resonator start-up. Figure 7-4: Example Oscillator/Resonator Start-up Characteristics C1(3) C2(3) XTAL OSC2 RS(1) OSC1 RF(2) Sleep To Internal Logic dsPIC30FXXXX Note 1: A series resistor, Rs, may be required for AT strip cut crystals. 2: The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ. 3: See Section 7.7 “Determining Best Values for Crystals, Clock Mode, C1, C2 and Rs”. Voltage Crystal Start-up Time Time Device VDD Maximum VDD of System 0V VIL VIH © 2005 Microchip Technology Inc. DS70054D-page 7-23 Section 7. Oscillator Oscillator 7 7.6.2 Tuning the Oscillator Circuit Since Microchip devices have wide operating ranges (frequency, voltage and temperature; depending on the part and version ordered) and external components (crystals, capacitors,...) of varying quality and manufacture, validation of operation needs to be performed to ensure that the component selection will comply with the requirements of the application. There are many factors that go into the selection and arrangement of these external components. These factors include: • amplifier gain • desired frequency • resonant frequency(s) of the crystal • temperature of operation • supply voltage range • start-up time • stability • crystal life • power consumption • simplification of the circuit • use of standard components • component count 7.6.3 Oscillator Start-up from Sleep Mode The most difficult time for the oscillator to start-up is when waking up from Sleep mode. This is because the load capacitors have both partially charged to some quiescent value, and phase differential at wake-up is minimal. Thus, more time is required to achieve stable oscillation. Remember also that low voltage, high temperatures and the Lower Frequency Clock modes also impose limitations on loop gain, which in turn affects start-up. Each of the following factors increases the start-up time: • a low frequency design (with a Low Gain Clock mode) • a quiet environment (such as a battery operated device) • operating in a shielded box (away from the noisy RF area) • low voltage • high temperature • wake-up from Sleep mode Noise actually helps lower the oscillator start-up time since it provides a “kick start” to the oscillator. Prior to entering Sleep mode, the application may switch to the Internal FRC(+PLL) oscillator in order to reduce the time taken by the device to wake-up from Sleep. dsPIC30F Family Reference Manual DS70054D-page 7-24 © 2005 Microchip Technology Inc. 7.7 Determining Best Values for Crystals, Clock Mode, C1, C2 and RS The best method for selecting components is to apply a little knowledge and a lot of trial, measurement and testing. Crystals are usually selected by their parallel resonant frequency only, however, other parameters may be important to your design, such as temperature or frequency tolerance. Application Note AN588 “PICmicro® Microcontroller Oscillator Design Guide” is an excellent reference to learn more about crystal operation and their ordering information. The dsPIC30F internal oscillator circuit is a parallel oscillator circuit, which requires that a parallel resonant crystal be selected. The load capacitance is usually specified in the 22 pF to 33 pF range. The crystal will oscillate closest to the desired frequency with a load capacitance in this range. It may be necessary to alter these values, as described later, in order to achieve other benefits. The Clock mode is primarily chosen based on the desired frequency of the crystal oscillator. The main difference between the XT, XTL and HS Oscillator modes is the gain of the internal inverter of the oscillator circuit, which allows the different frequency ranges. In general, use the oscillator option with the lowest possible gain that still meets specifications. This will result in lower dynamic currents (IDD). The frequency range of each Oscillator mode is the recommended frequency cutoff, but the selection of a different Gain mode is acceptable, as long as a thorough validation is performed (voltage, temperature and component variations, such as resistor, capacitor and internal oscillator circuitry). C1 and C2 (see Figure 7-3) should also be initially selected based on the load capacitance as suggested by the crystal manufacturer and the tables supplied in the device data sheet. The values given in the device data sheet can only be used as a starting point since the crystal manufacturer, supply voltage, and other factors already mentioned may cause your circuit to differ from the one used in the factory characterization process. Ideally, the capacitance is chosen so that it will oscillate at the highest temperature and the lowest VDD that the circuit will be expected to perform under. High temperature and low VDD both have a limiting effect on the loop gain, such that if the circuit functions at these extremes, the designer can be more assured of proper operation at other temperatures and supply voltage combinations. The output sine wave should not be clipped in the highest gain environment (highest VDD and lowest temperature) and the sine output amplitude should be large enough in the lowest gain environment (lowest VDD and highest temperature) to cover the logic input requirements of the clock as listed in the device data sheet. A method for improving start-up is to use a value of C2 greater than C1. This causes a greater phase shift across the crystal at power-up, which speeds oscillator start-up. Besides loading the crystal for proper frequency response, these capacitors can have the effect of lowering loop gain if their value is increased. C2 can be selected to affect the overall gain of the circuit. A higher C2 can lower the gain if the crystal is being over driven (also, see discussion on Rs). Capacitance values that are too high can store and dump too much current through the crystal, so C1 and C2 should not become excessively large. Unfortunately, measuring the wattage through a crystal is difficult, but if you do not stray too far from the suggested values you should not have to be concerned with this. A series resistor, Rs, is added to the circuit if, after all other external components are selected to satisfaction, the crystal is still being overdriven. This can be determined by looking at the OSC2 pin, which is the driven pin, with an oscilloscope. Connecting the probe to the OSC1 pin will load the pin too much and negatively affect performance. Remember that a scope probe adds its own capacitance to the circuit, so this may have to be accounted for in your design (i.e., if the circuit worked best with a C2 of 22 pF and scope probe was 10 pF, a 33 pF capacitor may actually be called for). The output signal should not be clipping or flattened. Overdriving the crystal can also lead to the circuit jumping to a higher harmonic level or even crystal damage. © 2005 Microchip Technology Inc. DS70054D-page 7-25 Section 7. Oscillator Oscillator 7 The OSC2 signal should be a clean sine wave that easily spans the input minimum and maximum of the clock input pin (4V to 5V peak-to-peak for a 5V VDD is usually good). An easy way to set this is to again test the circuit at the minimum temperature and maximum VDD that the design will be expected to perform in, then look at the output. This should be the maximum amplitude of the clock output. If there is clipping or the sine wave is distorted near VDD and VSS, increasing load capacitors may cause too much current to flow through the crystal or push the value too far from the manufacturer’s load specification. To adjust the crystal current, add a trimmer potentiometer between the crystal inverter output pin and C2 and adjust it until the sine wave is clean. The crystal will experience the highest drive currents at the low temperature and high VDD extremes. The trimmer potentiometer should be adjusted at these limits to prevent overdriving. A series resistor, Rs, of the closest standard value can now be inserted in place of the trimpot. If Rs is too high, perhaps more than 20 kOhms, the input will be too isolated from the output, making the clock more susceptible to noise. If you find a value this high is needed to prevent overdriving the crystal, try increasing C2 to compensate or changing the Oscillator Operating mode. Try to get a combination where Rs is around 10k or less and load capacitance is not too far from the manufacturer specification. 7.8 External Clock Input Two of the Primary Oscillator modes use an external clock. These modes are EC and ECIO. In the EC mode (Figure 7-5), the OSC1 pin can be driven by CMOS drivers. In this mode, the OSC1 pin is high-impedance and the OSC2 pin is the clock output (FOSC/4). This output clock is useful for testing or synchronization purposes. Figure 7-5: External Clock Input Operation (EC Oscillator Configuration) In the ECIO mode (Figure 7-6), the OSC1 pin can be driven by CMOS drivers. In this mode, the OSC1 pin is high-impedance and the OSC2 pin becomes a general purpose I/O pin. The feedback device between OSC1 and OSC2 is turned off to save current. Figure 7-6: External Clock Input Operation (ECIO Oscillator Configuration) OSC1 FOSC/4 OSC2 Clock from Ext. System dsPIC30F OSC1 I/O I/O (OSC2) Clock from Ext. System dsPIC30F dsPIC30F Family Reference Manual DS70054D-page 7-26 © 2005 Microchip Technology Inc. 7.9 External RC Oscillator For timing insensitive applications, the ERC and ERCIO modes of the Primary oscillator offer additional cost savings. The RC oscillator frequency is a function of the: • Supply voltage • External resistor (REXT) values • External capacitor (CEXT) values • Operating temperature In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external REXT and CEXT components used. Figure 7-7 shows how the RC combination is connected. For REXT values below 2.2 kΩ, oscillator operation may become unstable or stop completely. For very high REXT values (e.g., 1 MΩ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, it is recommended that a REXT value between 3 kΩ and 100 kΩ is used. Figure 7-7: ERC Oscillator Mode Although the oscillator will operate with no external capacitor (CEXT = 0 pF), a value above 20 pF should be used for noise and stability reasons. With no or a small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance and package lead frame capacitance. The oscillator frequency, divided by 4, is available on the OSC2/CLKO pin, and can be used for test purposes or to synchronize other logic. Note: An external clock source should not be connected to the OSC1 pin when the oscillator is configured for ERC or ERCIO modes. OSC2 CEXT VDD REXT VSS dsPIC30F OSC1 FOSC/4 Internal Clock © 2005 Microchip Technology Inc. DS70054D-page 7-27 Section 7. Oscillator Oscillator 7 7.9.1 External RC Oscillator with I/O Enabled The ERCIO Oscillator mode functions in the exact same manner as the ERC Oscillator mode. The only difference is that the OSC2 pin is configured as an I/O pin. As in the RC mode, the user needs to take into account any variation of the clock frequency due to tolerance of external REXT and CEXT components used, process variation, voltage and temperature. Figure 7-8 shows how the RC with the I/O pin combination is connected. Figure 7-8: ERCIO Oscillator Mode 7.9.2 External RC Start-up There is no start-up delay associated with the RC oscillator. Oscillation will begin when VDD is applied. 7.9.3 RC Operating Frequency The following graphs show the external RC oscillator frequency as a function of device voltage for a selection of RC component values. I/O (OSC2) CEXT REXT VSS OSC1 Internal Clock VDD dsPIC30F Note: The user should verify that VDD is within specifications before the device begins to execute code. Note: The following graphs should be used only as approximate guidelines for RC component selection. The actual frequency will vary based on the system temperature and device. Please refer to the specific device data sheet for further RC oscillator characteristic data. dsPIC30F Family Reference Manual DS70054D-page 7-28 © 2005 Microchip Technology Inc. Figure 7-9: Typical External RC Oscillator Frequency vs. VDD, CEXT = 20 pF Figure 7-10: Typical External RC Oscillator Frequency vs. VDD, CEXT = 100 pF 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Freq (MHz) REXT = 10k REXT = 100k Operation above 4 MHz is not recommended. 0.0 1.0 2.0 3.0 4.0 5.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Freq (MHz) REXT = 5.1k REXT = 10k REXT = 100k Operation above 4 MHz is not recommended. © 2005 Microchip Technology Inc. DS70054D-page 7-29 Section 7. Oscillator Oscillator 7 Figure 7-11: Typical External RC Oscillator Frequency vs. VDD, CEXT = 300 pF 0 50 100 150 200 250 300 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Freq (kHz) REXT = 3.3k REXT = 5.1k REXT = 10k REXT = 100k dsPIC30F Family Reference Manual DS70054D-page 7-30 © 2005 Microchip Technology Inc. 7.10 Phase Locked Loop (PLL) The PLL can be enabled for x4, x8 or x16 Operation modes using the FPR<3:0> oscillator Configuration bits. The input and output frequency ranges for each Operating mode are summarized in Table 7-7. Table 7-7: PLL Frequency Range 7.10.1 PLL Lock Status The PLL circuit is able to detect when the PLL enters a phase locked state. It can also detect when the PLL loses lock. The time delay for the PLL to achieve lock is designated as TLOCK. The TLOCK value is nominally 20 μs. Refer to the “Electrical Specifications” in the specific device data sheet for further information. The LOCK bit is a read-only Status bit (OSCCON<5>) that reflects the LOCK status of the PLL. The LOCK bit is cleared at a Power-on Reset. 7.10.1.1 Loss of PLL Lock During Clock Switching When the PLL is selected as a destination clock source in a clock switch operation (including a Power-on Reset), the LOCK bit is cleared. The LOCK bit is set after phase lock has been achieved. If the PLL fails to achieve lock, then the clock switching circuit will NOT switch to the PLL output for system clock; instead, it will continue to run with the old clock source. 7.10.1.2 Loss of PLL Lock During a Power-on Reset If the PLL fails to achieve lock at a Power-on Reset (POR) and the Fail-Safe Clock Monitor (FSCM) is enabled, the FRC oscillator will become the device clock source and a clock failure trap will occur. 7.10.1.3 Loss of PLL Lock During Normal Device Operation If the PLL loses lock during normal operation for at least 4 input clock cycles, then the LOCK bit is cleared, indicating a loss of PLL lock. Furthermore, a clock failure trap will be generated. In this situation, the processor continues to run using the PLL clock source. The user can switch to another clock source in the Trap Service Routine, if desired. Note: Some PLL output frequency ranges can be achieved that exceed the maximum operating frequency of the dsPIC30F device. Refer to the “Electrical Specifications” in the specific device data sheet for further details. FIN PLL Multiplier FOUT 4 MHz-10 MHz x4 16 MHz-40 MHz 4 MHz-10 MHz x8 32 MHz-80 MHz 4 MHz-7.5 MHz x16 64 MHz-120 MHz Note: Refer to Section 6. “Reset Interrupts” for further details about oscillator failure traps. Note: A loss of PLL lock during normal device operation will generate a clock failure trap, but the system clock source will not be changed. The FSCM does not need to be enabled to detect the loss of lock. © 2005 Microchip Technology Inc. DS70054D-page 7-31 Section 7. Oscillator Oscillator 7 7.11 Low-Power 32 kHz Crystal Oscillator The LP or Secondary oscillator is designed specifically for low power operation with a 32 kHz crystal. The LP oscillator is located on the SOSCO and SOSCI device pins and serves as a secondary crystal clock source for low power operation. The LP oscillator can also drive Timer1 for a real-time clock application. 7.11.1 LP Oscillator Enable The following control bits affect the operation of the LP oscillator: 1. The COSC<1:0> bits in the OSCCON register (OSCCON<13:12>). 2. The LPOSCEN bit in the OSCCON register (OSCCON<1>). When the LP Oscillator is enabled, the SOSCO and SOSCI I/O pins are controlled by the oscillator and cannot be used for other I/O functions. 7.11.1.1 LP Oscillator Continuous Operation The LP oscillator will always be enabled if the LPOSCEN control bit (OSCCON<1>) is set. There are two reasons to leave the LP oscillator running. First, keeping the LP oscillator ON at all times allows a fast switch to the 32 kHz system clock for lower power operation. Returning to the faster main oscillator will still require an oscillator start-up time if it is a crystal type source (see Section 7.12 “Oscillator Start-up Timer (OST)”). Second, the oscillator should remain ON at all times when using Timer1 as a real-time clock. 7.11.1.2 LP Oscillator Intermittent Operation When the LPOSCEN control bit (OSCCON<1>) is cleared, the LP oscillator will only operate when it is selected as the current device clock source (COSC<1:0> = 00). The LP oscillator will be disabled if it is the current device clock source and the device enters Sleep mode. 7.11.2 LP Oscillator Operation with Timer1 The LP oscillator can be used as a clock source for Timer1 in a real-time clock application. Refer to Section 12. “Timers” for further details. 7.12 Oscillator Start-up Timer (OST) In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer is provided. It is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The time-out period is designated as TOST. The amplitude of the oscillator signal must reach the VIL and VIH thresholds for the oscillator pins before the OST can begin to count cycles (see Figure 7-4). The TOST time is involved every time the oscillator has to restart (i.e., on POR, BOR and wake-up from Sleep mode). The Oscillator Start-up Timer is applied to the LP oscillator and the XT, XTL and HS modes for the Primary oscillator. 7.13 Internal Fast RC Oscillator (FRC) The FRC oscillator is a fast (7.37 MHz nominal) internal RC oscillator. This oscillator is intended to provide a range of device operating speeds without the use of an external crystal, ceramic resonator or RC network. Devices featuring the Oscillator system VERSIONs 2 or 3 may optionally provide the FRC oscillator as an input frequency to the PLL. dsPIC30F Family Reference Manual DS70054D-page 7-32 © 2005 Microchip Technology Inc. 7.14 Internal Low-Power RC (LPRC) Oscillator The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT and clock monitor circuits. It may also be used to provide a low frequency clock source option for applications where power consumption is critical, and timing accuracy is not required. 7.14.1 Enabling the LPRC Oscillator The LPRC oscillator is always enabled at a Power-on Reset because it is the clock source for the PWRT. After the PWRT expires, the LPRC oscillator will remain ON if one of the following is TRUE: • The Fail-Safe Clock Monitor is enabled. • The WDT is enabled. • The LPRC oscillator is selected as the system clock (COSC<1:0> = 10). If none of the above conditions is true, the LPRC will shut-off after the PWRT expires. 7.15 Fail-Safe Clock Monitor (FSCM) The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming the FCKSM bits (Clock Switch and Monitor bits) in the FOSC Device Configuration register. Refer to 7.3 “Oscillator Configuration” for further details. If the FSCM function is enabled, the LPRC internal oscillator will run at all times (except during Sleep mode). In the event of an oscillator failure, the FSCM will generate a clock failure trap and will switch the system clock to the FRC oscillator. The user will then have the option to either attempt to restart the oscillator or execute a controlled shutdown. The FSCM module will take the following actions when switching to the FRC oscillator: 1. The COSC<1:0> bits are loaded with ‘01’. 2. The CF bit is set to indicate the clock failure. 3. The OSWEN control bit is cleared to cancel any pending clock switches. 7.15.1 FSCM Delay On a POR, BOR or wake-up event from Sleep mode, a nominal 100 μs delay (TFSCM) may be inserted before the FSCM begins to monitor the system clock source. The purpose of the FSCM delay is to provide time for the oscillator and/or PLL to stabilize when the Power-up Timer (PWRT) is not utilized. The FSCM delay will be generated after the internal System Reset signal, SYSRST, has been released. Refer to Section 8. “Reset” for FSCM delay timing information. The FSCM delay, TFSCM, is applied when the FSCM is enabled and any of the following device clock sources is selected as the system clock: • EC+PLL • XT+PLL • XT • HS • HS/2 or HS/3 + PLL • XTL • LP Note: The oscillation frequency of the LPRC oscillator will vary depending on the device voltage and operating temperature. Refer to the “Electrical Specifications” in the specific device data sheet for further details. Note: For more information about the oscillator failure trap, please refer to Section 6. “Reset Interrupts”. Note: Please refer to the “Electrical Specifications” section of the device data sheet for TFSCM specification values. © 2005 Microchip Technology Inc. DS70054D-page 7-33 Section 7. Oscillator Oscillator 7 7.15.2 FSCM and Slow Oscillator Start-up If the chosen device oscillator has a slow start-up time coming out of POR, BOR or Sleep mode, it is possible that the FSCM delay will expire before the oscillator has started. In this case, the FSCM will initiate a clock failure trap. As this happens, the COSC<1:0> bits (OSCCON<13:12>) are loaded with the FRC oscillator selection. This will effectively shut-off the original oscillator that was trying to start. The user can detect this situation and initiate a clock switch back to the desired oscillator in the Trap Service Routine. 7.15.3 FSCM and WDT In the event of a clock failure, the WDT is unaffected and continues to run on the LPRC clock. 7.16 Programmable Oscillator Postscaler The postscaler allows the user to save power by lowering the frequency of the clock which feeds the CPU and the peripherals. Postscale values can be changed at any time via the POST<1:0> control bits (OSCCON<7:6>). To ensure a clean clock transition, there is some delay before a clock change occurs. The clock postscaler does not change the clock selection multiplexer until a falling edge on the divide-by-64 output occurs. In effect, the switching delay could be up to 64 system clock cycles depending on when the POST<1:0> control bits are written. Figure 7-13 shows the postscaler operation for three different postscaler changes. Figure 7-12: Programmable Oscillator Postscaler Counter div. by 4 div. by 16 div. by 64 System POST1 POST0 00 01 10 11 Clock Input Postscaled System Clock (from Clock Switch and Control Logic) Note: The system clock input can be any available source. dsPIC30F Family Reference Manual DS70054D-page 7-34 © 2005 Microchip Technology Inc. Figure 7-13: Postscaler Update Timing 7.17 Clock Switching Operation The selection of clock sources available for clock switching during device operation are as follows: • Primary oscillator on OSC1/OSC2 pins • Low-Power 32 kHz Crystal (Secondary) oscillator on SOSCO/SOSCI pins • Internal Fast RC (FRC) oscillator • Internal Low-Power RC (LPRC) oscillator 7.17.1 Clock Switching Enable To enable clock switching, the FCKSM1 Configuration bit in the FOSC Configuration register must be programmed to a ‘0’. (Refer to 7.3 “Oscillator Configuration” for further details.) If the FCKSM1 Configuration bit is a ‘1’ (unprogrammed), then the clock switching function is disabled. The Fail-Safe Clock Monitor function is also disabled. This is the default setting. The NOSC control bits in OSCCON do not control the clock selection when clock switching is disabled. However, the COSC bits in OSCCON will reflect the clock source selected by the FPR and FOS Configuration bits in the FOSC Configuration register. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at ‘0’ at all times. Divide by 4 Divide by 16 Divide by 64 POST<1:0> 01 10 11 00 Postscaled System Clock System 1:4 1:16 1:1 1:64 Clock Note: This diagram demonstrates the clock postscaler function only. The divide ratios shown in the timing diagram are not correct. Note: The Primary oscillator has multiple operating modes (EC, RC, XT, FRC etc.). The Operating mode of the Primary oscillator is determined by the FPR Configuration bits in the FOSC device Configuration register. (Refer to 7.3 “Oscillator Configuration” for further details.) © 2005 Microchip Technology Inc. DS70054D-page 7-35 Section 7. Oscillator Oscillator 7 7.17.2 Oscillator Switching Sequence The following steps are taken by the hardware and software to change the device clock source. (The steps shown below use the OSCCON register definition for the Oscillator system VERSION 1. For a description of the OSCCON register for the Oscillator system VERSION 2 and VERSION 3, refer to 7.4 “Oscillator Control Registers – OSCCON and OSCTUN”): 1. Read the COSC<1:0> Status bits (OSCCON<13:12>), if desired, to determine current oscillator source. 2. Perform the unlock sequence to allow a write to the OSCCON register high byte. 3. Write the appropriate value to the NOSC<1:0> control bits (OSCCON<9:8>) for the new oscillator source. 4. Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit (OSCCON<0>). This will INITIATE the oscillator switch. 6. The clock switching hardware compares the COSC<1:0> Status bits with the new value of the NOSC<1:0> control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. 7. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) Status bits are cleared. 8. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). 9. The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 10. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC<1:0> bit values are transferred to the COSC<1:0> Status bits. 11. The clock switch is completed. The old clock source will be turned off at this time, with the following exceptions: • The LPRC oscillator will stay on if the WDT or FSCM is enabled. • The LP oscillator will stay on if LPOSCEN = 1 (OSCCON<1>). Figure 7-14: Clock Transition Timing Diagram Note: The processor will continue to execute code throughout the clock switching sequence. Timing sensitive code should not be executed during this time. Old Clock Source New Clock Source System Clock Both Oscillators Active OSWEN 1 2 3 4 5 6 7 8 9 10 New Source Enabled New Source Stable Old Source Disabled Note: The system clock can be any selected source – Primary, Secondary, FRC or LPRC. dsPIC30F Family Reference Manual DS70054D-page 7-36 © 2005 Microchip Technology Inc. 7.17.3 Clock Switching Tips • If the destination clock source is a crystal oscillator, the clock switch time will be dominated by the oscillator start-up time. • If the new clock source does not start, or is not present, then the clock switching hardware will simply wait for the 10 synchronization cycles to occur. The user can detect this situation because the OSWEN bit (OSCCON<0>) remains set indefinitely. • If the new clock source uses the PLL, a clock switch will not occur until lock has been achieved. The user can detect a loss of PLL lock because the LOCK bit will be cleared and the OSWEN bit is set. • The user may wish to consider the settings of the POST<1:0> control bits (OSCCON<7:6>) when executing a clock switch. Switching to a low frequency clock source, such as the LP oscillator with a postscaler ratio greater than 1:1, will result in very slow device operation. 7.17.4 Aborting a Clock Switch In the event the clock switch did not complete, the clock switch logic can be reset by clearing the OSWEN bit. Clearing the OSWEN bit (OSCCON<0>) will: 1. Abandon the clock switch 2. Stop and reset the OST, if applicable 3. Stop the PLL, if applicable A clock switch procedure can be aborted at any time. 7.17.5 Entering Sleep Mode During a Clock Switch If the device enters Sleep mode during a clock switch operation, the clock switch operation is aborted. The processor keeps the old clock selection and the OSWEN bit is cleared. The PWRSAV instruction is then executed normally. 7.17.6 Recommended Code Sequence for Clock Switching The following steps should be taken to change the oscillator source: • Disable interrupts during the OSCCON register unlock and write sequence. • Execute unlock sequence for OSCCON high byte. • Write new oscillator source to NOSC control bits. • Execute unlock sequence for OSCCON low byte. • Set OSWEN bit. • Continue to execute code that is not clock sensitive (optional). • Invoke an appropriate amount of software delay (cycle counting) to allow for oscillator and/or PLL start-up. • Check to see if OSWEN is ‘0’. If it is, we are DONE SUCCESSFULLY. • If OSWEN is still set, then check LOCK bit to determine cause of failure. Note: The application should not attempt to switch to a clock of frequency lower than 100 kHz when the Fail-Safe Clock Monitor is enabled. If such clock switching is performed, the device may generate an oscillator fail trap and switch to the Fast RC oscillator. © 2005 Microchip Technology Inc. DS70054D-page 7-37 Section 7. Oscillator Oscillator 7 7.17.7 Clock Switch Code Examples 7.17.7.1 Starting a Clock Switch The following code sequence shows how to unlock the OSCCON register and begin a clock switch operation: ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.B w2, [w1] MOV.B w3, [w1] ;Set new oscillator selection MOV.B WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV.B #0x01, w0 MOV #0x46, w2 MOV #0x57, w3 MOV.B w2, [w1] MOV.B w3, [w1] ;Start oscillator switch operation MOV.b w0, [w1] 7.17.7.2 Aborting a Clock Switch The following code sequence would be used to ABORT an unsuccessful clock switch: MOV OSCCON,W0 ; Read OSCCON into W0 BCLR W0, #OSWEN ; Clear bit 0 in W0 MOV #OSCCON,W1 ; pointer to OSCCON MOV.B #0x46,W2 ; first unlock code MOV.B #0x57,W3 ; second unlock code MOV.B W2, [W1] ; write first unlock code MOV.B W3, [W1] ; write second unlock code MOV.B W0, [W1] ; ABORT the switch dsPIC30F Family Reference Manual DS70054D-page 7-38 © 2005 Microchip Technology Inc. 7.18 Design Tips Question 1: When looking at the OSC2 pin after power-up with an oscilloscope, there is no clock. What can cause this? Answer: 1. Entering Sleep mode with no source for wake-up (such as, WDT, MCLR, or an interrupt). Verify that the code does not put the device to Sleep without providing for wake-up. If it is possible, try waking it up with a low pulse on MCLR. Powering up with MCLR held low will also give the crystal oscillator more time to start-up, but the Program Counter will not advance until the MCLR pin is high. 2. The wrong Clock mode is selected for the desired frequency. For a blank device, the default oscillator is EC + 16x PLL. Most parts come with the clock selected in the Default mode, which will not start oscillation with a crystal or resonator. Verify that the Clock mode has been programmed correctly. 3. The proper power-up sequence has not been followed. If a CMOS part is powered through an I/O pin prior to power-up, bad things can happen (latch-up, improper start-up, etc.). It is also possible for brown-out conditions, noisy power lines at start-up, and slow VDD rise times to cause problems. Try powering up the device with nothing connected to the I/O, and power-up with a known, good, fast rise, power supply. Refer to the power-up information in the device data sheet for considerations on brown-out and power-up sequences. 4. The C1 and C2 capacitors attached to the crystal have not been connected properly or are not the correct values. Make sure all connections are correct. The device data sheet values for these components will usually get the oscillator running; however, they just might not be the optimal values for your design. Question 2: The device starts, but runs at a frequency much higher than the resonant frequency of the crystal. Answer: The gain is too high for this oscillator circuit. Refer to Section 7.6 “Crystal Oscillators/Ceramic Resonators” to aid in the selection of C2 (may need to be higher), Rs (may be needed) and Clock mode (wrong mode may be selected). This is especially possible for low frequency crystals, like the common 32.768 kHz. Question 3: The design runs fine, but the frequency is slightly off. What can be done to adjust this? Answer: Changing the value of C1 has some effect on the oscillator frequency. If a SERIES resonant crystal is used, it will resonate at a different frequency than a PARALLEL resonant crystal of the same frequency call-out. Ensure that you are using a PARALLEL resonant crystal. Question 4: The board works fine, then suddenly quits or loses time. Answer: Other than the obvious software checks that should be done to investigate losing time, it is possible that the amplitude of the oscillator output is not high enough to reliably trigger the oscillator input. Look at the C1 and C2 values and ensure that the device Configuration bits are correct for the desired oscillator mode. Question 5: If I put an oscilloscope probe on an oscillator pin, I don’t see what I expect. Why? Answer: Remember that an oscilloscope probe has capacitance. Connecting the probe to the oscillator circuitry will modify the oscillator characteristics. Consider using a low capacitance (active) probe. © 2005 Microchip Technology Inc. DS70054D-page 7-39 Section 7. Oscillator Oscillator 7 7.19 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Oscillator module are: Title Application Note # PICmicro® Microcontroller Oscillator Design Guide AN588 Low Power Design using PICmicro® Microcontrollers AN606 Crystal Oscillator Basics and Crystal Selection for rfPIC® and PICmicro® Devices AN826 Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. dsPIC30F Family Reference Manual DS70054D-page 7-40 © 2005 Microchip Technology Inc. 7.20 Revision History Revision A This is the initial released revision of this document. Revision B This revision incorporates technical content changes for the dsPIC30F Oscillator module. Revision C This revision incorporates all known errata at the time of this document update. Revision D This revision incorporates details on the three versions (VERSION 1, VERSION 2 and VERSION 3) of the Oscillator system implemented in dsPIC30F devices in the General Purpose, Sensor and Motor Control families. © 2004 Microchip Technology Inc. DS70055C-page 8-1 Reset 8 Section 8. Reset HIGHLIGHTS This section of the manual contains the following topics: 8.1 Introduction .................................................................................................................... 8-2 8.2 Clock Source Selection at Reset ...................................................................................8-5 8.3 POR: Power-on Reset ................................................................................................... 8-5 8.4 External Reset (EXTR) .................................................................................................. 8-7 8.5 Software Reset Instruction (SWR)................................................................................. 8-7 8.6 Watchdog Time-out Reset (WDTR) ............................................................................... 8-7 8.7 Brown-out Reset (BOR)................................................................................................. 8-8 8.8 Using the RCON Status Bits ........................................................................................ 8-10 8.9 Device Reset Times..................................................................................................... 8-11 8.10 Device Start-up Time Lines.......................................................................................... 8-13 8.11 Special Function Register Reset States....................................................................... 8-16 8.12 Design Tips .................................................................................................................. 8-17 8.13 Related Application Notes............................................................................................8-18 8.14 Revision History ........................................................................................................... 8-19 dsPIC30F Family Reference Manual DS70055C-page 8-2 © 2004 Microchip Technology Inc. 8.1 Introduction The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • POR: Power-on Reset • EXTR: Pin Reset (MCLR) • SWR: RESET Instruction • WDTR: Watchdog Timer Reset • BOR: Brown-out Reset • TRAPR: Trap Conflict Reset • IOPR: Illegal Opcode Reset • UWR: Uninitialized W Register Reset A simplified block diagram of the Reset module is shown in Figure 8-1. Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known “Reset state”. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 8-1). A POR will clear all bits except for the POR and BOR bits (RCON<2:1>), which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Low Voltage Detect module, Watchdog Timer, and device power saving states. The function of these bits is discussed in other sections of this manual. Figure 8-1: Reset System Block Diagram Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. MCLR VDD VDD Rise Detect POR Sleep or Idle Brown-out Reset BOREN RESET Instruction WDT Module Glitch Filter BOR Trap Conflict Illegal Opcode Uninitialized W Register SYSRST © 2004 Microchip Technology Inc. DS70055C-page 8-3 Section 8. Reset Reset 8 Register 8-1: RCON: Reset Control Register Upper Byte: R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 TRAPR IOPUWR BGST LVDEN LVDL<3:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR bit 7 bit 0 bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal Address mode, or uninitialized W register used as an address pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13 BGST: Bandgap Stable bit 1 = The bandgap has stabilized 0 = Bandgap is not stable and LVD interrupts should be disabled bit 12 LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 11-8 LVDL<3:0>: Low Voltage Detection Limit bits Refer to Section 9. “Low Voltage Detect (LVD)” for further details. bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software RESET (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit 1 = WDT is turned on 0 = WDT is turned off Note: If FWDTEN fuse bit is ‘1’ (unprogrammed), the WDT is ALWAYS ENABLED, regardless of the SWDTEN bit setting. bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred 0 = WDT Time-out has not occurred bit 3 SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode dsPIC30F Family Reference Manual DS70055C-page 8-4 © 2004 Microchip Technology Inc. Register 8-1: RCON: Reset Control Register (Continued) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after Power-on Reset. 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred Note: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70055C-page 8-5 Section 8. Reset Reset 8 8.2 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 8-1. If clock switching is disabled, the system clock source is always selected according to the oscillator configuration fuses. Refer to Section 7. “Oscillator” for further details. Table 8-1: Oscillator Selection vs. Type of Reset (Clock Switching Enabled) 8.3 POR: Power-on Reset There are two threshold voltages associated with a Power-on Reset (POR). The first voltage is the device threshold voltage, VPOR. The device threshold voltage is the voltage at which the device logic circuits become operable. The second voltage associated with a POR event is the POR circuit threshold voltage which is nominally 1.85V. A power-on event will generate an internal Power-on Reset pulse when a VDD rise is detected. The Reset pulse will be generated at VPOR. The device supply voltage characteristics must meet specified starting voltage and rise rate requirements to generate the POR pulse. In particular, VDD must fall below VPOR before a new POR is initiated. For more information on the VPOR and the VDD rise rate specifications, please refer to the “Electrical Specifications” section of the device data sheet. The POR pulse will reset a POR timer and place the device in the Reset state. The POR also selects the device clock source identified by the oscillator configuration bits. After the Power-on Reset pulse is generated, the POR circuit inserts a small delay, TPOR, which is nominally 10 μs and ensures that internal device bias circuits are stable. Furthermore, a user selected Power-up Time-out (TPWRT) may be applied. The TPWRT parameter is based on device configuration bits and can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total delay time at device power-up is TPOR + TPWRT. When these delays have expired, SYSRST will be released on the next leading edge of the instruction cycle clock, and the PC will jump to the Reset vector. The timing for the SYSRST signal is shown in Figure 8-2. A Power-on Reset is initialized when VDD falls below a threshold voltage, VT. The POR delay time is inserted when VDD crosses the POR circuit threshold voltage. Finally, the PWRT delay time, TPWRT, is inserted before SYSRST is released. The power-on event will set the POR and BOR status bits (RCON<1:0>). Reset Type Clock Source Selected Based On POR Oscillator Configuration Fuses BOR Oscillator Configuration Fuses EXTR COSC Control bits (OSCCON<13:12>) WDTR COSC Control bits (OSCCON<13:12>) SWR COSC Control bits (OSCCON<13:12>) dsPIC30F Family Reference Manual DS70055C-page 8-6 © 2004 Microchip Technology Inc. Figure 8-2: POR Module Timing Diagram for Rising VDD TPOR VDD POR Circuit Time Time VPOR POR Circuit Threshold Voltage SYSRST Time TPWRT Internal Power-on Reset pulse occurs at VPOR and begins POR delay time, TPOR. POR circuit is initialized at VPOR. System Reset is released after Power-up Timer expires. (0 ms, 4 ms, 16 ms or 64 ms) Note: When the device exits the Reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges, otherwise the device will not function correctly. The user must ensure that the delay between the time power is first applied and the time SYSRST becomes inactive is long enough to get all operating parameters within specification. © 2004 Microchip Technology Inc. DS70055C-page 8-7 Section 8. Reset Reset 8 8.3.1 Using the POR Circuit To take advantage of the POR circuit, just tie the MCLR pin directly to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise time for VDD is required. Refer to the “Electrical Specifications” section in the specific device data sheet for further details. Depending on the application, a resistor may be required between the MCLR pin and VDD. This resistor can be used to decouple the MCLR pin from a noisy power supply rail. The resistor will also be necessary if the device programming voltage, VPP, needs to be placed on the MCLR pin while the device is installed in the application circuit. VPP is 13 volts for most devices. Figure 8-3 shows a possible POR circuit for a slow power supply ramp up. The external Power-on Reset circuit is only required if the device would exit Reset before the device VDD is in the valid operating range. The diode, D, helps discharge the capacitor quickly when VDD powers down. Figure 8-3: External Power-on Reset Circuit (For Slow VDD Rise Time) 8.3.2 Power-up Timer (PWRT) The PWRT provides an optional time delay (TPWRT) before SYSRST is released at a device POR or BOR (Brown-out Reset). The PWRT time delay is provided in addition to the POR delay time (TPOR). The PWRT time delay may be 0 ms, 4 ms, 16 ms or 64 ms nominal (see Figure 8-2). The PWRT delay time is selected using the FPWRT<1:0> configuration fuses in the FBORPOR Device Configuration register. Refer to Section 24. “Device Configuration” for further details. 8.4 External Reset (EXTR) Whenever the MCLR pin is driven low, the device will asynchronously assert SYSRST, provided the input pulse on MCLR is longer than a certain minimum width. (Refer to the “Electrical Specifications” in the specific device data sheet for further details.) When the MCLR pin is released, SYSRST will be released on the next instruction clock cycle, and the Reset vector fetch will commence. The processor will maintain the existing clock source that was in use before the EXTR occurred. The EXTR status bit (RCON<7>) will be set to indicate the MCLR Reset. 8.5 Software RESET Instruction (SWR) Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST will be released at the next instruction cycle, and the Reset vector fetch will commence. 8.6 Watchdog Time-out Reset (WDTR) Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST. The clock source will remain unchanged. Note that a WDT time-out during Sleep or Idle mode will wake-up the processor, but NOT reset the processor. For more information, refer to Section 10. “Watchdog Timer and Power Saving Modes”. Note 1: The value of R should be low enough so that the voltage drop across it does not violate the VIH specification of the MCLR pin. 2: R1 will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). R1 MCLR dsPIC30F D R C VDD VDD dsPIC30F Family Reference Manual DS70055C-page 8-8 © 2004 Microchip Technology Inc. 8.7 Brown-out Reset (BOR) The BOR (Brown-out Reset) module is based on an internal voltage reference circuit. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (i.e., missing waveform portions of the AC cycles due to bad power transmission lines), or voltage sags due to excessive current draw when a large load is energized. The BOR module allows selection of one of the following voltage trip points: • VBOR = 2.0V • VBOR = 2.7V • VBOR = 4.2V • VBOR = 4.5V On a BOR, the device will select the system clock source based on the device configuration bit values (FPR<3:0>, FOS<1:0>). The PWRT time-out (TPWRT), if enabled, will be applied before SYSRST is released. If a crystal oscillator source is selected, the Brown-out Reset will invoke the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If a system clock source is derived from the PLL, then the clock will be held until the LOCK bit (OSCCON<5>) is set. The BOR status bit (RCON<1>) will be set to indicate that a BOR has occurred. The BOR circuit, if enabled, will continue to operate while in Sleep or Idle modes and will reset the device should VDD fall below the BOR threshold voltage. Refer to the “Electrical Specifications” section of the appropriate device data sheet for the BOR electrical specifications. Typical brown-out scenarios are shown in Figure 8-4. As shown, a PWRT delay (if enabled) will be initiated each time VDD rises above the VBOR trip point. Figure 8-4: Brown-out Situations Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. Refer to the “Electrical Specifications” in the specific device data sheet for BOR voltage limit specifications. VDD SYSRST VBOR VDD SYSRST VBOR VDD SYSRST VBOR TPWRT TPWRT TPWRT VDD dips before PWRT expires © 2004 Microchip Technology Inc. DS70055C-page 8-9 Section 8. Reset Reset 8 8.7.1 BOR Configuration The BOR module is enabled/disabled and configured via device configuration fuses. The BOR module is enabled by default and may be disabled (to reduce power consumption) by programming the BOREN device configuration fuse to a ‘0’ (FBORPOR<7>). The BOREN configuration fuse is located in the FBORPOR Device Configuration register. The BOR voltage trip point (VBOR) is selected using the BORV<1:0> configuration fuses (FBOR<5:4>). Refer to Section 24. “Device Configuration” for further details. 8.7.2 Current Consumption for BOR Operation The BOR circuit relies on an internal voltage reference circuit that is shared with other peripheral devices, such as the Low Voltage Detect module. The internal voltage reference will be active whenever one of its associated peripherals is enabled. For this reason, the user may not observe the expected change in current consumption when the BOR is disabled. 8.7.3 Illegal Opcode Reset A device Reset will be generated if the device attempts to execute an illegal opcode value that was fetched from program memory. The Illegal Opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the Illegal Opcode Reset, use only the lower 16 bits of each program memory section to store the data values. The upper 8 bits should be programmed with 0x3F, which is an illegal opcode value. If a device Reset occurs as a result of an illegal opcode value, the IOPUWR status bit (RCON<14>) will be set. 8.7.4 Uninitialized W Register Reset The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. An attempt to use an uninitialized register as an address pointer will reset the device. Furthermore, the IOPUWR status bit (RCON<14>) will be set. 8.7.5 Trap Conflict Reset A device Reset will occur whenever multiple hard trap sources become pending at the same time. The TRAPR status bit (RCON<15>) will be set. Refer to Section 6. “Reset Interrupts” for more information on Trap Conflict Resets. dsPIC30F Family Reference Manual DS70055C-page 8-10 © 2004 Microchip Technology Inc. 8.8 Using the RCON Status Bits The user can read the RCON register after any device Reset to determine the cause of the Reset. Table 8-2 provides a summary of the Reset flag bit operation. Table 8-2: Reset Flag Bit Operation Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap conflict event POR IOPWR (RCON<14>) Illegal opcode or uninitialized W register access POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR IDLE (RCON<2>) PWRSAV #IDLE instruction POR BOR (RCON<1>) POR, BOR POR (RCON<0>) POR Note: All RESET flag bits may be set or cleared by the user software. © 2004 Microchip Technology Inc. DS70055C-page 8-11 Section 8. Reset Reset 8 8.9 Device Reset Times The Reset times for various types of device Reset are summarized in Table 8-3. Note that the system Reset signal, SYSRST, is released after the POR delay time and PWRT delay times expire. The time that the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. Table 8-3: Reset Delay Times for Various Device Resets Reset Type Clock Source SYSRST Delay System Clock Delay FSCM Delay Notes POR EC, EXTRC, FRC, LPRC TPOR + TPWRT — — 1, 2 EC + PLL TPOR + TPWRT TLOCK TFSCM 1, 2, 4, 5 XT, HS, XTL, LP TPOR + TPWRT TOST TFSCM 1, 2, 3, 5 XT + PLL TPOR + TPWRT TOST + TLOCK TFSCM 1, 2, 3, 4, 5 BOR EC, EXTRC, FRC, LPRC TPWRT — — 2 EC + PLL TPWRT TLOCK TFSCM 1, 2, 4, 5 XT, HS, XTL, LP TPWRT TOST TFSCM 1, 2, 3, 5 XT + PLL TPWRT TOST + TLOCK TFSCM 1, 2, 3, 4, 5 MCLR Any Clock — — — WDT Any Clock — — — Software Any clock — — — Illegal Opcode Any Clock — — — Uninitialized W Any Clock — — — Trap Conflict Any Clock — — — Note 1: TPOR = Power-on Reset delay (10 μs nominal). 2: TPWRT = Additional “power-up” delay as determined by the FPWRT<1:0> configuration bits. This delay is 0 ms, 4 ms, 16 ms or 64 ms nominal. 3: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 4: TLOCK = PLL lock time (20 μs nominal). 5: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal). dsPIC30F Family Reference Manual DS70055C-page 8-12 © 2004 Microchip Technology Inc. 8.9.1 POR and Long Oscillator Start-up Times The oscillator start-up circuitry and its associated delay timers is not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate. • The oscillator start-up timer has NOT expired (if a crystal oscillator is used). • The PLL has not achieved a LOCK (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. 8.9.2 Fail-Safe Clock Monitor (FSCM) and Device Resets If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. 8.9.2.1 FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal oscillator and/or the PLL, a small delay, TFSCM, will automatically be inserted after the POR and PWRT delay times. The FSCM will not begin to monitor the system clock source until this delay expires. The FSCM delay time is nominally 100 μs and provides additional time for the oscillator and/or PLL to stabilize. In most cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT is disabled. © 2004 Microchip Technology Inc. DS70055C-page 8-13 Section 8. Reset Reset 8 8.10 Device Start-up Time Lines Figure 8-5 through Figure 8-8 show graphical time lines of the delays associated with device Reset for several operating scenarios. Figure 8-5 shows the delay time line when a crystal oscillator and PLL are used as the system clock and the PWRT is disabled. The internal Power-on Reset pulse occurs at the VPOR threshold. A small POR delay occurs after the internal Reset pulse. (The POR delay is always inserted before device operation begins.) The FSCM, if enabled, begins to monitor the system clock for activity when the FSCM delay expires. Figure 8-5 shows that the oscillator and PLL delays expire before the Fail-Safe Clock Monitor (FSCM) is enabled. However, it is possible that these delays may not expire until after FSCM is enabled. In this case, the FSCM would detect a clock failure and a clock failure trap will be generated. If the FSCM delay does not provide adequate time for the oscillator and PLL to stabilize, the PWRT could be enabled to allow more delay time before device operation begins and the FSCM starts to monitor the system clock. Figure 8-5: Device Reset Delay, Crystal + PLL Clock Source, PWRT Disabled POR Circuit Threshold Voltage SYSRST Oscillator Internal Power-on Reset Pulse TPOR TFSCM TOST TLOCK VDD Oscillator released to system, device operation POR System Reset released. Note 1: Delay times shown are not drawn to scale. 2: FSCM, if enabled, monitors system clock at expiration of TPOR + TFSCM. 3: TLOCK not inserted when PLL is disabled. FSCM FSCM enabled. begins. OSC Delay System OSC dsPIC30F Family Reference Manual DS70055C-page 8-14 © 2004 Microchip Technology Inc. The Reset time line shown in Figure 8-6 is similar to that shown in Figure 8-5, except that the PWRT has been enabled to increase the amount of delay time before SYSRST is released. The FSCM, if enabled, will begin to monitor the system clock after TFSCM expires. Note that the additional PWRT delay time added to TFSCM provides ample time for the system clock source to stabilize in most cases. Figure 8-6: Device Reset Delay, Crystal + PLL Clock Source, PWRT Enabled POR Circuit Threshold Voltage SYSRST Internal Power-on Reset Pulse TPOR TPWRT TOST TLOCK VDD Oscillator released to system. POR Note 1: Delay times shown are not drawn to scale. 2: FSCM, if enabled, monitors system clock at expiration of TPOR + TPWRT + TFSCM. 3: TLOCK not inserted when PLL is is disabled. TFSCM short compared to TPWRT. FSCM Device operation begins. OSC Delay TFSCM © 2004 Microchip Technology Inc. DS70055C-page 8-15 Section 8. Reset Reset 8 The Reset time line in Figure 8-7 shows an example when an EC + PLL clock source is used as the system clock and the PWRT is enabled. This example is similar to the one shown in Figure 8-6, except that the oscillator start-up timer delay, TOST, does not occur. Figure 8-7: Device Reset Delay, EC + PLL Clock, PWRT Enabled POR Circuit Threshold Voltage SYSRST Internal Power-on Reset Pulse TPOR TPWRT TLOCK VDD POR Note 1: Delay times shown are not drawn to scale. 2: FSCM, if enabled, monitors system clock at expiration of TPOR + TPWRT + TFSCM. 3: TLOCK not inserted when PLL is is disabled. TFSCM short compared to TPWRT. FSCM Device operation begins. OSC Delay TFSCM Oscillator released to system. dsPIC30F Family Reference Manual DS70055C-page 8-16 © 2004 Microchip Technology Inc. The Reset time line shown in Figure 8-8 shows an example where an EC without PLL, or RC system clock source is selected and the PWRT is disabled. Note that this configuration provides minimal Reset delays. The POR delay is the only delay time that occurs before device operation begins. No FSCM delay will occur if the FSCM is enabled, because the system clock source is not derived from a crystal oscillator or the PLL. Figure 8-8: Device Reset Delay, EC or RC Clock, PWRT Disabled 8.11 Special Function Register Reset States Most of the special function registers (SFRs) associated with the dsPIC30F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of two registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the oscillator configuration bits in the FOSC Device Configuration register (see Table 8-1). POR Circuit Threshold Voltage SYSRST Internal Power-on Reset Pulse TPOR VDD Oscillator released to system. POR System Reset released. Note 1: Delay times shown are not drawn to scale. 2: If enabled, FSCM will begin to monitor system clock at expiration of TPOR. FSCM OSC Delay © 2004 Microchip Technology Inc. DS70055C-page 8-17 Section 8. Reset Reset 8 8.12 Design Tips Question 1: How do I use the RCON register? Answer: The initialization code after a Reset should examine RCON and confirm the source of the Reset. In certain applications, this information can be used to take appropriate action to correct the problem that caused the Reset to occur. All Reset status bits in the RCON register should be cleared after reading them to ensure the RCON value will provide meaningful results after the next device Reset. Question 2: How should I use BOR in a battery operated application? Answer: The BOR feature is not designed to operate as a low battery detect, and should be disabled in battery operated systems (to save current). The Low Voltage Detect peripheral can be used to detect when the battery has reached its end of life voltage. Question 3: The BOR module does not have the programmable trip points that my application needs. How can I work around this? Answer: There are some applications where the device’s programmable BOR trip point levels may still not be at the desired level for the application. Figure 8-9 shows a possible circuit for external brown-out protection, using the MCP100 system supervisor. Figure 8-9: External Brown-out Protection Using the MCP100 Question 4: I initialized a W register with a 16-bit address, but the device appears to reset when I attempt to use the register as an address. Answer: Because all data addresses are 16 bit values, the uninitialized W register logic only recognizes that a register has been initialized correctly if it was subjected to a word load. Two byte moves to a W register, even if successive, will not work, resulting in a device Reset if the W register is used as an address pointer in an operation. VSS RST MCP100 VDD dsPIC30F VDD MCLR dsPIC30F Family Reference Manual DS70055C-page 8-18 © 2004 Microchip Technology Inc. 8.13 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Reset module are: Title Application Note # Power-up Trouble Shooting AN607 Power-up Considerations AN522 Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. © 2004 Microchip Technology Inc. DS70055C-page 8-19 Section 8. Reset Reset 8 8.14 Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual. Revision C There were no technical content revisions to this section of the manual, however, this section was updated to reflect Revision C throughout the manual. dsPIC30F Family Reference Manual DS70055C-page 8-20 © 2004 Microchip Technology Inc. NOTES: © 2004 Microchip Technology Inc. DS70056C-page 9-1 L o w Volta g e Detect (LVD) 9 Section 9. Low Voltage Detect (LVD) HIGHLIGHTS This section of the manual contains the following topics: 9.1 Introduction .................................................................................................................... 9-2 9.2 LVD Operation ...............................................................................................................9-5 9.3 Design Tips .................................................................................................................... 9-6 9.4 Related Application Notes..............................................................................................9-7 9.5 Revision History ............................................................................................................. 9-8 dsPIC30F Family Reference Manual DS70056C-page 9-2 © 2004 Microchip Technology Inc. 9.1 Introduction The LVD module is applicable to battery operated applications. As the battery drains its energy, the battery voltage slowly drops. The battery source impedance also increases as it loses energy. The LVD module is used to detect when the battery voltage (and therefore, the VDD of the device) drops below a threshold, which is considered near the end of battery life for the application. This allows the application to gracefully shutdown its operation. The LVD module uses an internal reference voltage for comparison. The threshold voltage, VLVD, is programmable during run-time. Figure 9-1 shows a possible application battery voltage curve. Over time, the device voltage decreases. When the device voltage equals voltage VLVD, the LVD logic generates an interrupt. This occurs at time TA. The application software then has until the device voltage is no longer in valid operating range to shutdown the system. Voltage point VB is the minimum valid operating voltage specification. This gives a time TB. The total time for shutdown is TB – TA. Figure 9-1: Typical Low Voltage Detect Application Time Voltage VLVD VMIN TA VLVD = LVD trip point VMIN = Minimum valid device operating voltage Legend: TB © 2004 Microchip Technology Inc. DS70056C-page 9-3 Section 9. Low Voltage Detect L o w Volta g e Detect (LVD) 9 Figure 9-2 shows the block diagram for the LVD module. A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage is lower than the reference voltage, the LVDIF bit (IFS2<10>) is set. Each node in the resistor divider represents a “trip point” voltage. This voltage is software programmable to any one of 16 values. Figure 9-2: Low Voltage Detect (LVD) Block Diagram 9.1.1 LVD Control Bits The LVD module control bits are located in the RCON register. The LVDEN bit (RCON<12>) enables the Low Voltage Detect module. The LVD module is enabled when LVDEN = 1. If power consumption is important, the LVDEN bit can be cleared for maximum power savings. 9.1.1.1 LVD Trip Point Selection The LVDL<3:0> bits (RCON<11:8>) will choose the LVD trip point. There are 15 trip point options that may be selected from the internal voltage divider connected to VDD. If none of the trip point options are suitable for the application, there is one option that allows the LVD sample voltage to be applied externally on the LVDIN pin. (Refer to the specific device data sheet for the pin location.) The nominal trip point voltage for the external LVD input is 1.24 volts. The LVD external input option requires that the user select values for an external voltage divider circuit that will generate a LVD interrupt at the desired VDD. 9.1.2 Internal Voltage Reference The LVD uses an internal bandgap voltage reference circuit that requires a nominal amount of time to stabilize. Refer to the “Electrical Specifications” in the specific device data sheet for details. The BGST status bit (RCON<13>) indicates when the bandgap voltage reference has stabilized. The user should poll the BGST status bit in software after the LVD module is enabled. At the end of the stabilization time, the LVDIF bit (IFS2<10>) should be cleared. Refer to the LVD module setup procedure in Section 9.2 “LVD Operation”. The bandgap voltage reference circuit can also be used by other peripherals on the device so it may already be active (and stabilized) prior to enabling the LVD module. VDD LVDIF 16 to 1 MUX LVDEN Internally Generated Reference Voltage LVDIN LVDL<3:0> External LVD Input pin 4 dsPIC30F Family Reference Manual DS70056C-page 9-4 © 2004 Microchip Technology Inc. Register 9-1: RCON: Reset Control Register Upper Byte: R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 TRAPR IOPUWR BGST LVDEN LVDL<3:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR bit 7 bit 0 bit 13 BGST: Bandgap Stable bit 1 = The bandgap has stabilized 0 = Bandgap is not stable and LVD interrupts should be disabled bit 12 LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 11-8 LVDL<3:0>: Low Voltage Detection Limit bits 1111 = Input to LVD is the LVDIN pin (1.24V threshold, nominal) 1110 = 4.6V 1101 = 4.3V 1100 = 4.1V 1011 = 3.9V 1010 = 3.7V 1001 = 3.6V 1000 = 3.4V 0111 = 3.1V 0110 = 2.9V 0101 = 2.8V (default value at Reset) 0100 = 2.6V 0011 = 2.5V 0010 = 2.3V 0001 = 2.1V 0000 = 1.9V Note: The voltage threshold values shown here are provided for design guidance only. Refer to the “Electrical Specifications” in the device data sheet for further details. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: See Section 8. “Reset” for a description of other bits in the RCON register. © 2004 Microchip Technology Inc. DS70056C-page 9-5 Section 9. Low Voltage Detect L o w Volta g e Detect (LVD) 9 9.2 LVD Operation The LVD module adds robustness to the application because the device can monitor the state of the device voltage. When the device voltage enters a voltage window near the lower limit of the valid operating voltage range, the device can save values to ensure a “clean” shutdown. Depending on the power source for the device, the supply voltage may decrease relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. 9.2.1 LVD Initialization Steps The following steps are required to setup the LVD module: 1. If the external LVD input pin is used (LVDIN), ensure that all other peripherals multiplexed on the pin are disabled and the pin is configured as an input by setting the appropriate bit in the TRISx registers. 2. Write the desired value to the LVDL control bits (RCON<11:8>), which selects the desired LVD threshold voltage. 3. Ensure that LVD interrupts are disabled by clearing the LVDIE bit (IEC2<10>). 4. Enable the LVD module by setting the LVDEN bit (RCON<12>). 5. Wait for the internal voltage reference to become stable by polling the BGST status bit (RCON<13>), if required (see Section 9.1.2 “Internal Voltage Reference”). 6. Ensure that the LVDIF bit (IFS2<10>) is cleared before interrupts are enabled. If LVDIF is set, the device VDD may be below the chosen LVD threshold voltage. 7. Set LVD interrupts to the desired CPU priority level by writing the LVDIP<2:0> control bits (IPC10<10:8>). 8. Enable LVD interrupts by setting the LVDIE control bit. Once the VDD has fallen below the programmed LVD threshold, the LVDIF bit will remain set. When the LVD module has interrupted the CPU, one of two actions may be taken in the ISR: 1. Clear the LVDIE control bit to disable further LVD module interrupts and take the appropriate shutdown procedures. or 2. Decrease the LVD voltage threshold using the LVDL control bits and clear the LDVIF status bit. This technique can be used to track a gradually decreasing battery voltage. 9.2.2 Current Consumption for LVD Operation The LVD circuit relies on an internal voltage reference circuit that is shared with other peripheral devices, such as the Brown-out Reset (BOR) module. The internal voltage reference will be active whenever one of its associated peripherals is enabled. For this reason, the user may not observe the expected change in current consumption when the LVD module is disabled. 9.2.3 Operation in Sleep and Idle Mode When enabled, the LVD circuitry continues to operate during Sleep or Idle modes. If the device voltage crosses the trip point, the LVDIF bit will be set. The criteria for exiting from Sleep or Idle modes are as follows: • If the LVDIE bit (IEC2<10>) is set, the device will wake from Sleep or Idle mode. • If the assigned priority for the LVD interrupt is less than or equal to the current CPU priority, the device will wake-up and continue code execution from the instruction following the PWRSAV instruction that initiated the Sleep or Idle mode. • If the assigned priority level for the LVD interrupt is greater than the current CPU priority, the device will wake-up and the CPU exception process will begin. Code execution will continue from the first instruction of the LVD ISR. Note: The system design should ensure that the application software is given adequate time to save values before the device exits the valid operating range, or is forced into a Brown-out Reset. dsPIC30F Family Reference Manual DS70056C-page 9-6 © 2004 Microchip Technology Inc. 9.3 Design Tips Question 1: The LVD circuitry seems to be generating random interrupts? Answer: Ensure that the internal voltage reference is stable before enabling the LVD interrupt. This is done by polling the BGST status bit (RCON<13>) after the LVD module is enabled. After this time delay, the LVDIF bit should be cleared and then, the LVDIE bit may be set. Question 2: How can I reduce the current consumption of the module? Answer: Low Voltage Detect is used to monitor the device voltage. The power source is normally a battery that ramps down slowly. This means that the LVD circuity can be disabled for most of the time, and only enabled occasionally to do the device voltage check. Question 3: Should I enable the BOR circuit for a battery powered application? Answer: The BOR circuit is intended to protect the device from improper operation due to power supply fluctuations caused by the AC line voltage. The BOR is typically not required for battery applications and can be disabled for lower current consumption. © 2004 Microchip Technology Inc. DS70056C-page 9-7 Section 9. Low Voltage Detect L o w Volta g e Detect (LVD) 9 9.4 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Low Voltage Detect module are: Title Application Note # No related application notes at this time. Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. dsPIC30F Family Reference Manual DS70056C-page 9-8 © 2004 Microchip Technology Inc. 9.5 Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual. Revision C There were no technical content revisions to this section of the manual, however, this section was updated to reflect Revision C throughout the manual. © 2005 Microchip Technology Inc. DS70057D-page 10-1 W D T a n d P o w er Saving Modes 10 Section 10. Watchdog Timer and Power Saving Modes HIGHLIGHTS This section of the manual contains the following topics: 10.1 Introduction .................................................................................................................. 10-2 10.2 Power Saving Modes ................................................................................................... 10-2 10.3 Sleep Mode.................................................................................................................. 10-2 10.4 Idle Mode ..................................................................................................................... 10-4 10.5 Interrupts Coincident with Power Save Instructions.....................................................10-5 10.6 Watchdog Timer........................................................................................................... 10-6 10.7 Peripheral Module Disable (PMD) Registers ............................................................... 10-9 10.8 Design Tips ................................................................................................................ 10-10 10.9 Related Application Notes.......................................................................................... 10-11 10.10 Revision History ......................................................................................................... 10-12 dsPIC30F Family Reference Manual DS70057D-page 10-2 © 2005 Microchip Technology Inc. 10.1 Introduction This section addresses the Watchdog Timer (WDT) and Power Saving modes of the dsPIC30F device family. The dsPIC DSC devices have two reduced Power modes that can be entered through execution of the PWRSAV instruction: • Sleep Mode: The CPU, system clock source, and any peripherals that operate on the system clock source are disabled. This is the lowest Power mode for the device. • Idle Mode: The CPU is disabled, but the system clock source continues to operate. Peripherals continue to operate, but can optionally be disabled. The WDT, when enabled, operates from the internal LPRC clock source and can be used to detect system software malfunctions by resetting the device if the WDT has not been cleared in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. 10.2 Power Saving Modes The dsPIC30F device family has two special Power Saving modes, Sleep mode and Idle mode, that can be entered through the execution of a special PWRSAV instruction. The assembly syntax of the PWRSAV instruction is as follows: PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode The Power Saving modes can be exited as a result of an enabled interrupt, WDT time-out, or a device Reset. When the device exits one of these two Operating modes, it is said to ‘wake-up’. The characteristics of the Power Saving modes are described in subsequent sections. 10.3 Sleep Mode The characteristics of Sleep mode are as follows: • The system clock source is shutdown. If an on-chip oscillator is used, it is turned off. • The device current consumption will be at a minimum provided that no I/O pin is sourcing current. • The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode since the system clock source is disabled. • The LPRC clock will continue to run in Sleep mode if the WDT is enabled. • The Low Voltage Detect circuit, if enabled, remains operative during Sleep mode. • The BOR circuit, if enabled, remains operative during Sleep mode. • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. • Some peripherals may continue to operate in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, or peripherals that use an external clock input. Any peripheral that is operating on the system clock source will be disabled in Sleep mode. The processor will exit, or ‘wake-up’, from Sleep on one of the following events: • On any interrupt source that is individually enabled • On any form of device Reset • On a WDT time-out 10.3.1 Clock Selection on Wake-up from Sleep The processor will restart the same clock source that was active when Sleep mode was entered. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. © 2005 Microchip Technology Inc. DS70057D-page 10-3 Section 10. WDT and Power Saving Modes W D T a n d P o w er Saving Modes 10 10.3.2 Delay on Wake-up from Sleep The power-up and oscillator start-up delays associated with waking up from Sleep mode are shown in Table 10-1. In all cases, the POR delay time (TPOR = 10 μs nominal) is applied to allow internal device circuits to stabilize before the internal system Reset signal, SYSRST, is released. Table 10-1: Delay Times for Exit from Sleep Mode 10.3.3 Wake-up from Sleep Mode with Crystal Oscillator or PLL If the system clock source is derived from a crystal oscillator and/or the PLL, then the Oscillator Start-up Timer (OST) and/or PLL lock times must be applied before the system clock source is made available to the device. As an exception to this rule, no oscillator delays are necessary if the system clock source is the LP oscillator and it was running while in Sleep mode. Note that in spite of various delays applied, the crystal oscillator (and PLL) may not be up and running at the end of the POR delay. 10.3.4 FSCM Delay and Sleep Mode If the following conditions are true, a nominal 100 μs delay (TFSCM) will be applied after the POR delay expires when waking from Sleep mode: • The oscillator was shutdown while in Sleep mode. • The system clock is derived from a crystal oscillator source and/or the PLL. The FSCM delay provides time for the OST to expire and the PLL to stabilize before device execution resumes in most cases. If the FSCM is enabled, it will begin to monitor the system clock source after the FSCM delay expires. 10.3.5 Slow Oscillator Start-up The OST and PLL lock times may not have expired when the power-up delays have expired. If the FSCM is enabled, then the device will detect this condition as a clock failure and a clock fail trap will occur. The device will switch to the FRC oscillator and the user can re-enable the crystal oscillator source in the clock failure Trap Service Routine. If FSCM is NOT enabled, then the device will simply not start executing code until the clock is stable. From the user’s perspective, the device will appear to be in Sleep until the oscillator clock has started. Clock Source SYSRST Delay Oscillator Delay FSCM Delay Notes EC, EXTRC TPOR — — 1 EC + PLL TPOR TLOCK TFSCM 1, 3, 4 XT + PLL TPOR TOST + TLOCK TFSCM 1, 2, 3, 4 XT, HS, XTL TPOR TOST TFSCM 1, 2, 4 LP (OFF during Sleep) TPOR TOST TFSCM 1, 2, 4 LP (ON during Sleep) TPOR — — 1 FRC, LPRC TPOR — — 1 Note 1: TPOR = Power-on Reset delay (10 μs nominal). 2: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 3: TLOCK = PLL lock time (20 μs nominal). 4: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal). Note: Please refer to the “Electrical Specifications” section of the dsPIC30F device data sheet for TPOR, TFSCM and TLOCK specification values. dsPIC30F Family Reference Manual DS70057D-page 10-4 © 2005 Microchip Technology Inc. 10.3.6 Wake-up from Sleep on Interrupt User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Sleep mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater. Any source of interrupt that is individually enabled, using its corresponding IE control bit in the IECx registers, can wake-up the processor from Sleep mode. When the device wakes from Sleep mode, one of two actions may occur: • If the assigned priority for the interrupt is less than or equal to the current CPU priority, the device will wake-up and continue code execution from the instruction following the PWRSAV instruction that initiated Sleep mode. • If the assigned priority level for the interrupt source is greater than the current CPU priority, the device will wake-up and the CPU exception process will begin. Code execution will continue from the first instruction of the ISR. The Sleep status bit (RCON<3>) is set upon wake-up. 10.3.7 Wake-up from Sleep on Reset All sources of device Reset will wake the processor from Sleep mode. Any source of Reset (other than a POR) that wakes the processor will set the Sleep status bit (RCON<3>) to indicate that the device was previously in Sleep mode. On a Power-on Reset, the Sleep bit is cleared. 10.3.8 Wake-up from Sleep on Watchdog Time-out If the Watchdog Timer (WDT) is enabled and expires while the device is in Sleep mode, the processor will wake-up. The Sleep and WDTO status bits (RCON<3>, RCON<4>) are both set to indicate that the device resumed operation due to the WDT expiration. Note that this event does not reset the device. Operation continues from the instruction following the PWRSAV instruction that initiated Sleep mode. 10.4 Idle Mode User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Idle mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater. When the device enters Idle mode, the following events occur: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source will remain active and peripheral modules, by default, will continue to operate normally from the system clock source. Peripherals can optionally be shutdown in Idle mode using their ‘stop-in-idle’ control bit. (See peripheral descriptions for further details.) • If the WDT or FSCM is enabled, the LPRC will also remain active. The processor will wake from Idle mode on the following events: • On any interrupt that is individually enabled. • On any source of device Reset. • On a WDT time-out. Upon wake-up from Idle, the clock is re-applied to the CPU and instruction execution begins immediately starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR. © 2005 Microchip Technology Inc. DS70057D-page 10-5 Section 10. WDT and Power Saving Modes W D T a n d P o w er Saving Modes 10 10.4.1 Wake-up from Idle on Interrupt Any source of interrupt that is individually enabled using the corresponding IE control bit in the IECx register and exceeds the current CPU priority level, will be able to wake-up the processor from Idle mode. When the device wakes from Idle mode, one of two options may occur: • If the assigned priority for the interrupt is less than or equal to the current CPU priority, the device will wake-up and continue code execution from the instruction following the PWRSAV instruction that initiated Idle mode. • If the assigned priority level for the interrupt source is greater than the current CPU priority, the device will wake-up and the CPU exception process will begin. Code execution will continue from the first instruction of the ISR. The Idle status bit (RCON<2>) is set upon wake-up. 10.4.2 Wake-up from Idle on Reset Any Reset, other than a POR, will wake the CPU from Idle mode. On any device Reset, except a POR, the Idle status bit is set (RCON<2>) to indicate that the device was previously in Idle mode. In a Power-on Reset, the Idle bit is cleared. 10.4.3 Wake-up from Idle on WDT Time-out If the WDT is enabled, then the processor will wake from Idle mode on a WDT time-out and continue code execution with the instruction following the PWRSAV instruction that initiated Idle mode. Note that the WDT time-out does not reset the device in this case. The WDTO and Idle status bits (RCON<4>, RCON<2>) will both be set. 10.4.4 Time Delays on Wake from Idle Mode Unlike a wake-up from Sleep mode, there are no time delays associated with wake-up from Idle mode. The system clock is running during Idle mode, therefore, no start-up times are required at wake-up. 10.5 Interrupts Coincident with Power Save Instructions Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. dsPIC30F Family Reference Manual DS70057D-page 10-6 © 2005 Microchip Technology Inc. 10.6 Watchdog Timer The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free running timer, which runs on the internal LPRC oscillator requiring no external components. Therefore, the WDT timer will continue to operate even if the system clock source (e.g., the crystal oscillator) fails. A block diagram of the WDT is shown in Figure 10-1. Figure 10-1: WDT Block Diagram 10.6.1 Enabling and Disabling the WDT The WDT is enabled or disabled by the FWDTEN device configuration bit in the FWDT Device Configuration register. The FWDT Configuration register values are written during device programming. When the FWDTEN configuration bit is set, the WDT is enabled. This is the default value for an erased device. Refer to Section 24. “Device Configuration” for further details on the FWDT Device Configuration register. 10.6.1.1 Software Controlled WDT If the FWDTEN device configuration bit is set, then the WDT is always enabled. However, the WDT can be optionally controlled in the user software when the FWDTEN configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. LPRC WDT Overflow Wake-up Reset WDT 8-bit Watchdog Timer 512 kHz 4 Programmable Prescaler A 1:1, 1:8, 1:64, 1:512 Programmable Prescaler B 1:1, 1:2, 1:3, … 1:15, 1:16 FWC = 128 kHz Enable WDT FWPSB3 FWPSB2 FWPSB1 FWPSB0 FWPSA1 FWPSA0 SWDTEN FWDTEN 2 4 from Sleep Reset All Device Resets Sleep or Idle State LPRC CLRWDT Instr. PWRSAV Instr. Control Oscillator © 2005 Microchip Technology Inc. DS70057D-page 10-7 Section 10. WDT and Power Saving Modes W D T a n d P o w er Saving Modes 10 10.6.2 WDT Operation If enabled, the WDT will increment until it overflows or “times out”. A WDT time-out will force a device Reset, except during Sleep or Idle modes. To prevent a WDT Time-out Reset, the user must periodically clear the Watchdog Timer using the CLRWDT instruction. The CLRWDT instruction also clears the WDT prescalers. If the WDT times out during Sleep or Idle modes, the device will wake-up and continue code execution from where the PWRSAV instruction was executed. In either case, the WDTO bit (RCON<4>) will be set to indicate that the device Reset or wake-up event was due to a WDT time-out. If the WDT wakes the CPU from Sleep or Idle mode, the Sleep status bit (RCON<3>), or Idle status bit (RCON<2>) will also be set to indicate that the device was previously in a Power Saving mode. 10.6.3 WDT Timer Period Selection The WDT clock source is the internal LPRC oscillator, which has a nominal frequency of 512 kHz. The LPRC clock is further divided by 4 to provide a 128 kHz clock to the WDT. The counter for the WDT is 8-bits wide, so the nominal time-out period for the WDT (TWDT) is 2 milliseconds. 10.6.3.1 WDT Prescalers The WDT has two clock prescalers, Prescaler A and Prescaler B, to allow a wide variety of time-out periods. Prescaler A can be configured for 1:1, 1:8, 1:64 or 1:512 divide ratios. Prescaler B can be configured for any divide ratio from 1:1 through 1:16. Time-out periods that range between 2 ms and 16 seconds (nominal) can be achieved using the prescalers. The prescaler settings are selected using the FWPSA<1:0> (Prescaler A) and FWPSB<3:0> (Prescaler B) configuration bits in the FWDT Device Configuration register. The FWPSA<1:0> and FWPSB<3:0> values are written during device programming. For more information on the WDT prescaler configuration bits, please refer to Section 24. “Device Configuration”. The time-out period of the WDT is calculated as follows: Equation 10-1: WDT Time-out Period Note: The WDT time-out period is directly related to the frequency of the LPRC oscillator. The frequency of the LPRC oscillator will vary as a function of device operating voltage and temperature. Please refer to the specific dsPIC30F device data sheet for LPRC clock frequency specifications. WDT Period = 2 ms • Prescale A • Prescale B dsPIC30F Family Reference Manual DS70057D-page 10-8 © 2005 Microchip Technology Inc. Table 10-2 shows time-out periods for various prescaler selections: Table 10-2: WDT Time-out Period vs. Prescale A and Prescale B Settings 10.6.4 Resetting the Watchdog Timer The WDT and all its prescalers are reset: • On ANY device Reset • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • By a CLRWDT instruction during normal execution 10.6.5 Operation of WDT in Sleep and Idle Modes If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The WDT is useful for low power system designs, because it can be used to periodically wake the device from Sleep mode to check system status and provide action if necessary. Note that the SWDTEN bit is very useful in this respect. If the WDT is disabled during normal operation (FWDTEN = 0), then the SWDTEN bit (RCON<5>) can be used to turn on the WDT just before entering Sleep mode. Prescaler B Value Prescaler A Value 1 8 64 512 1 2 16 128 1024 2 4 32 256 2048 3 6 48 384 3072 4 8 64 512 4096 5 10 80 640 5120 6 12 96 768 6144 7 14 112 896 7168 8 16 128 1024 8192 9 18 144 1152 9216 10 20 160 1280 10240 11 22 176 1408 11264 12 24 192 1536 12288 13 26 208 1664 13312 14 28 224 1792 14336 15 30 240 1920 15360 16 32 256 2048 16384 Note: All time values are in milliseconds. © 2005 Microchip Technology Inc. DS70057D-page 10-9 Section 10. WDT and Power Saving Modes W D T a n d P o w er Saving Modes 10 10.7 Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral will also be disabled so writes to those registers will have no effect and read values will be invalid. A peripheral module will only be enabled if both the associated bit in the the PMD register is cleared and the peripheral is supported by the specific dsPIC variant. If the peripheral is present in the device, it is enabled in the PMD register by default. Please check individual device data sheet for specific operational details of the PMD register. Note: If a PMD bit is set, the corresponding module is disabled after a delay of 1 instruction cycle. Similarly, if a PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). dsPIC30F Family Reference Manual DS70057D-page 10-10 © 2005 Microchip Technology Inc. 10.8 Design Tips Question 1: The device resets even though I have inserted a CLRWDT instruction in my main software loop. Answer: Make sure that the software loop that contains the CLRWDT instruction meets the minimum specification of the WDT (not the typical value). Also, make sure that interrupt processing time has been accounted for. Question 2: What should my software do before entering Sleep or Idle mode? Answer: Make sure that the sources intended to wake the device have their IE bits set. In addition, make sure that the particular source of interrupt has the ability to wake the device. Some sources do not function when the device is in Sleep mode. If the device is to be placed in Idle mode, make sure that the ‘stop-in-idle’ control bit for each device peripheral is properly set. These control bits determine whether the peripheral will continue operation in Idle mode. See the individual peripheral sections of this manual for further details. Question 3: How do I tell which peripheral woke the device from Sleep or Idle mode? Answer: You can poll the IF bits for each enabled interrupt source to determine the source of wake-up. © 2005 Microchip Technology Inc. DS70057D-page 10-11 Section 10. WDT and Power Saving Modes W D T a n d P o w er Saving Modes 10 10.9 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Watchdog Timer and Power Saving Modes are: Title Application Note # Low Power Design using PICmicro® Microcontrollers AN606 Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the dsPIC30F Family of devices. dsPIC30F Family Reference Manual DS70057D-page 10-12 © 2005 Microchip Technology Inc. 10.10 Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this sec