CC2531 USB Hardware User's Guide (Rev. A - Texas ... - Texas Instruments - Farnell Element 14
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CC2531 USB Hardware
User’s Guide
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Table of Contents
1 Introduction ..................................................................................................................................3
2 About this Manual ........................................................................................................................3
3 Acronyms .....................................................................................................................................4
4 Definitions.....................................................................................................................................5
5 Getting Started .............................................................................................................................7
6 Using SmartRF05EB as an In-Circuit Emulator (ICE)..................................................................9
6.1 The Debug Interface................................................................................................................9
7 USB Dongle Hardware Description............................................................................................10
7.1 User Interface........................................................................................................................10
7.2 Debug Connector ..................................................................................................................10
7.3 RF Performance of Antenna ..................................................................................................11
8 USB Dongle Reference Design and Schematics.......................................................................12
9 References..................................................................................................................................13
10 General Information ...................................................................................................................14
10.1 Document History ..............................................................................................................14
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1 Introduction
Thank you for purchasing a CC2530 Development Kit.
The CC2530 is Texas Instrument’s second generation ZigBee/IEEE 802.15.4 compliant System-on-
Chip with an optimized 8051 MCU core and radio for the 2.4 GHz unlicensed ISM/SRD band. This
device enables industrial grade applications by offering state-of-the-art noise immunity, excellent link
budget, operation up to 125 degrees and low voltage operation.
In addition, the CC2530 provides extensive hardware support for packet handling, data buffering, burst
transmissions, data encryption, data authentication, clear channel assessment, link quality indication
and packet timing information. The CC2530 product folder on the web [10] has more information, with
datasheets, user guides and application notes.
The CC2531 is identical to CC2530, with the addition of a built in full speed USB 2.0 compliant
interface.
The CC2530 Development Kit includes all the necessary hardware to properly evaluate, demonstrate,
prototype and develop software targeting not only IEEE802.15.4 or ZigBee compliant applications, but
also proprietary applications for which a DSSS radio is required or wanted.
2 About this Manual
This manual covers the CC2531 USB dongle found in the CC2530 Development Kit and the CC2530
ZigBee Development Kit.
The manual covers the CC2531 USB Dongle hardware component of a USB development framework.
Please refer to [3] for a description of the accompanying USB Firmware Library and application
examples.
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3 Acronyms
CDC Communications Device Class
DK Development Kit
EB Evaluation Board
EM Evaluation Module
EMK Evaluation Module Kit
HID Human Interface Device
IC Integrated Circuit
ICE In Circuit Emulator
KB Kilo Byte (1024 byte)
LED Light Emitting Diode
LPRF Low Power RF
MCU Micro Controller
NC Not connected
RF Radio Frequency
RX Receive
SoC System on Chip
TI Texas Instruments
TX Transmit
UART Universal Asynchronous Receive Transmit
USB Universal Serial Bus
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4 Definitions
SmartRF05EB
The SmartRF05EB (evaluation board) is the main
board in the kit with a wide range of user
interfaces:
3x16 character serial LCD
Full speed USB 2.0 interface
UART
LEDs
Serial Flash
Potentiometer
Joystick
Buttons
The EB is the platform for the evaluation modules
(EM) and can be connected to the PC via USB to
control the EM.
CC2530EM
The CC2530EM (evaluation module) contains the
RF IC and necessary external components and
matching filters for getting the most out of the
radio. The module can be plugged into the
SmartRF05EB. Use the EM as reference
design for RF layout. The schematics are
included at the end of this document and the
layout files can be found on the web CC2530
Product Page [10].
CC2531 USB Dongle
The CC2531 USB Dongle is a fully operational
USB device that can be plugged into a PC. The
dongle has 2 LEDs, two small push-buttons and
connector holes that allow connection of external
sensors or devices. The dongle also has a
connector for programming and debugging of the
CC2531 USB controller.
The dongle comes preprogrammed with firmware
such that it can be used as a packet sniffer
device.
Antenna
2.4 GHz antenna Titanis from Antenova.
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SoC System on Chip. A collective term used to refer
to Texas Instruments ICs with on-chip MCU and
RF transceiver. Used in this document to
reference the CC2530 and 2531.
ICE In Circuit Emulator. ICE functionality is built into
the SmartRF05EB and the CC Debugger
USB software application examples Application examples using the CC2531 USB
Dongle together with a CC2530EM.
USB Firmware Library A library of low level USB firmware which is used
by all the USB software examples.
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5 Getting Started
Make sure to install SmartRF Studio before connecting the SmartRF05EB to a PC. By installing it, the
required Windows drivers will be provided when connecting the SmartRF05EB.
SmartRF Studio [4] is a PC application for Windows that helps you find and adjust the radio register
settings. Please see [4] for instructions on downloading and installation.
The dongle comes preprogrammed with firmware such that it can be used as a packet sniffer device.
For programming the device with other firmware an external ICE is needed. The SmartRF05EB1 can be
used to program the USB dongle. The CC2531 has a 2 wire debug interface that is used for chip
programming and debugging. When connecting this interface to the SmartRF05EB, the CC2531 can be
programmed from the SmartRF Flash Programmer software [2] and debugged from IAR Embedded
Workbench. To connect the CC2531 USB Dongle to the SmartRF05EB, follow these steps:
1. Turn off the SmartRF05EB power by moving the power switch shown in Figure 2 to the left
position.
2. Remove any evaluation modules (EMs) attached to the SmartRF05EB.
3. Connect the SmartRF05EB to a PC with the supplied USB cable.
4. Connect the USB Dongle to the ExtSoC Debug header (P3) on SmartRF05EB with the supplied
10 pin cable and adapter board (see Figure 1). Make sure pin 1 on the dongle is connected to
pin 1 on P3. This cable connects the debug interface and GND between the two devices;
however the USB Dongle is not powered through this cable.
5. Power the CC2531 USB Dongle. To power the dongle there are two options:
Powered with a USB Cable
Use the supplied USB extension cable to connect the USB Dongle to the PC (see
Figure 1).
Powered from the SmartRF05EB
Mount resistor R2 on the CC2531 USB Dongle and resistor R30 on the SmartRF05EB.
The CC2531 USB Dongle should only be powered by one of the two sources at a time. Do not
connect the USB cable to the USB Dongle while it is powered from the SmartRF05EB.
6. Turn on the power on the SmartRF05EB (see Figure 2).
1 It is also possible to use the SmartRF04EB or the CC Debugger to program the device.
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Figure 1 - CC2531 USB Dongle connected to SmartRF05EB
Figure 2 - SmartRF05EB power switch, power on.
The CC2531 can now be programmed with the SmartRF Flash Programmer software. The firmware on
the CC2531 can also be debugged using the IAR Embedded Workbench debugger. Please see the
“SmartRF Flash Programmer User’s Manual” for more details [2].
Please see the “CC2530 Development Kit User Manual” [1] for more information on the SmartRF05EB
and how to use the CC2530EM.
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6 Using SmartRF05EB as an In-Circuit Emulator (ICE)
The debug interface on the SmartRF05EB is controlled by the USB MCU. This allows both
programming and an emulator interface over USB, which makes the SmartRF05EB usable as an ICE
for the CC2531 dongle.
To use the SmartRF05EB as ICE, the IAR Embedded Workbench software for 8051 architecture
(EW8051) must be installed. The Embedded Workbench is an integrated development environment with
a complete tool-chain such as C Compiler, Simulator, and ICE debugger. Please see [1] for instructions
on how to set up the ICE debugger for use as an ICE.
When the SmartRF05EB with a SoC is connected to a PC with the USB port, the debugger in IAR
EW8051 will connect to it when started. If several SmartRF05EBs are connected to USB ports
simultaneously, a selection window will display the connected evaluation boards, and the user can
select which device to load.
6.1 The Debug Interface
For custom PCB’s with the CC2531 SoC, it is recommended to include a pin header or test points to
allow in-circuit emulation or programming using a SmartRF05EB or other 3rd party programming tools.
The USB Dongle can be used as a reference.
VDD note: The SmartRF05EB includes a voltage converter to support programming and debugging of
external systems with different voltage than the SmartRF05EB.
When using SmartRF05EB as emulator for external target debugging any evaluation module (EM) must
be removed.
Figure 3 shows the required signal for a minimum connector layout on external target.
Figure 3 - Minimum Debug Connector Pinout (top view)
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7 USB Dongle Hardware Description
Figure 4 - CC2531 USB Dongle
7.1 User Interface
The CC2531 USB Dongle has two buttons and two LEDs that can be used to interact with the user.
Table 1 shows which CC2531 signals are connected to what IO on the dongle.
IO
Connector CC2531 Dongle
User IO CC2531
1 P0.2 Green LED P0.0
2 P0.3 Red LED P1.1
3 P0.4 Button S1 P1.2
4 P0.5 Button S2 P1.3
5 P1.7
6 P1.6
7 P1.5
8 P1.4
Table 1 - CC2531 USB Dongle Pinout
7.2 Debug Connector
The CC2531 USB dongle can be connected to a SmartRF Evaluation Board for debugging and
programming.
IO Connector
Meandred F-antenna
CC2531F256
Button S1
Button S2
LEDs
Debug connector
Voltage regulator
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Figure 5 - CC2531 USB Dongle connected to SmartRF05EB
The debug connector on the CC2531 USB Dongle matches the debug connector on the SmartRF05EB
(and the CC Debugger). Note that, by default, the CC2531 dongle is not powered through the debug
connector, so an external power source must be used while programming. The easiest solution is to
connect it to a USB port on the PC. Alternatively, resistor R2 can be mounted. The table below shows
the pin out of the debug connector.
Pin # Connection
1 GND
2 VCC
3 CC2531 P2.2 (DC)
4 CC2531 P2.1 (DD)
5 NC
6 NC
7 CC2531 RESET
8 NC
9 Optional external VCC (R2 must be mounted)
10 NC
Table 2 - CC2531 USB Dongle Debug Connector
7.3 RF Performance of Antenna
While the CC2531 USB Dongle has a PCB antenna designed as a meandered inverted F antenna.
The performance of the PCB antenna on the USB Dongle will be affected by its nearby surroundings.
Therefore, when plugged into different computers or a USB extension cable differences in the RF
performance must be expected. Also, if the USB Dongle is put inside a casing, the material and design
of the enclosure will influence the antenna’s performance. For the CC2531 USB Dongle the maximum
antenna gain measured is 5.3 dBi. This means that duty cycling or reduction of output power might be
needed to ensure compliance with regulatory limits. Please see [8] for more information about SRD
regulations in the 2.4 GHz ISM band. The performance of the antenna of the CC2531 USB Dongle is
further described in [9].
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8 USB Dongle Reference Design and Schematics
Refer to [1] for the schematics of the CC2531 USB Dongle.
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9 References
[1] CC2530 DK Development Kit User Manual (swru208)
[2] SmartRF Flash Programmer (swrc044)
[3] SmartRF Packet Sniffer (swrc045)
[4] SmartRF Studio (swrc046)
[5] CC USB Firmware Library and Examples (swrc088)
[6] CC USB Software Examples User’s Guide (swru222)
[7] SmartRF05EB User’s Guide (swru210)
[8] AN032 – SRD Regulation for License-Free Transceiver Operation in the 2.4 GHz Band (swra060)
[9] AN043 – Small Size 2.4 GHz PCB Antenna (swra117)
[10] CC2530 Product Web Site (http://focus.ti.com/docs/prod/folders/print/cc2530.html)
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10 General Information
10.1 Document History
Revision Date Description/Changes
SWRU221A 2009.07.31 Updated info about how to connect dongle to SmartRF05EB. Corrected typos.
SWRU221 2009.05.08 Initial release
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Copyright © 2009, Texas Instruments Incorporated
MSP430 Hardware Tools
User's Guide
Literature Number: SLAU278Q
May 2009–Revised February 2014
Contents
Preface ....................................................................................................................................... 7
1 Get Started Now! ............................................................................................................... 10
1.1 Flash Emulation Tool (FET) Overview .................................................................................. 11
1.2 Kit Contents, MSP-FET430PIF .......................................................................................... 12
1.3 Kit Contents, eZ430-F2013 .............................................................................................. 12
1.4 Kit Contents, eZ430-T2012 .............................................................................................. 12
1.5 Kit Contents, eZ430-RF2500 ............................................................................................ 12
1.6 Kit Contents, eZ430-RF2500T ........................................................................................... 12
1.7 Kit Contents, eZ430-RF2500-SEH ...................................................................................... 12
1.8 Kit Contents, eZ430-Chronos-xxx ....................................................................................... 13
1.9 Kit Contents, MSP-FET430UIF .......................................................................................... 13
1.10 Kit Contents, MSP-FET430xx ............................................................................................ 13
1.11 Kit Contents, FET430F6137RF900 ..................................................................................... 14
1.12 Kit Contents, MSP-TS430xx ............................................................................................. 14
1.13 Kit Contents, EM430Fx1x7RF900 ....................................................................................... 16
1.14 Hardware Installation, MSP-FET430PIF ............................................................................... 16
1.15 Hardware Installation, MSP-FET430UIF ............................................................................... 17
1.16 Hardware Installation, eZ430-XXXX, MSP-EXP430G2, MSP-EXP430FR5739, MSP-EXP430F5529 ......... 17
1.17 Hardware Installation, MSP-FET430Uxx, MSP-TS430xxx, FET430F6137RF900, EM430Fx137RF900 ...... 17
1.18 Important MSP430 Documents on the Web ........................................................................... 18
2 Design Considerations for In-Circuit Programming ............................................................... 19
2.1 Signal Connections for In-System Programming and Debugging ................................................... 20
2.2 External Power ............................................................................................................. 24
2.3 Bootstrap Loader (BSL) .................................................................................................. 24
A Frequently Asked Questions and Known Issues ................................................................... 25
A.1 Hardware FAQs ............................................................................................................ 26
A.2 Known Issues .............................................................................................................. 28
B Hardware .......................................................................................................................... 29
B.1 MSP-TS430D8 ............................................................................................................. 31
B.2 MSP-TS430PW14 ......................................................................................................... 34
B.3 MSP-TS430L092 .......................................................................................................... 37
B.4 MSP-TS430L092 Active Cable .......................................................................................... 40
B.5 MSP-TS430PW24 ......................................................................................................... 43
B.6 MSP-TS430DW28 ......................................................................................................... 46
B.7 MSP-TS430PW28 ......................................................................................................... 49
B.8 MSP-TS430PW28A ....................................................................................................... 52
B.9 MSP-TS430DA38 .......................................................................................................... 55
B.10 MSP-TS430QFN23x0 ..................................................................................................... 58
B.11 MSP-TS430RSB40 ........................................................................................................ 61
B.12 MSP-TS430RHA40A ...................................................................................................... 64
B.13 MSP-TS430DL48 .......................................................................................................... 67
B.14 MSP-TS430RGZ48B ...................................................................................................... 70
B.15 MSP-TS430RGZ48C ...................................................................................................... 73
B.16 MSP-TS430PM64 ......................................................................................................... 76
2 Contents SLAU278Q–May 2009–Revised February 2014
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B.17 MSP-TS430PM64A ....................................................................................................... 79
B.18 MSP-TS430RGC64B ..................................................................................................... 82
B.19 MSP-TS430RGC64C ..................................................................................................... 85
B.20 MSP-TS430RGC64USB .................................................................................................. 89
B.21 MSP-TS430PN80 .......................................................................................................... 93
B.22 MSP-TS430PN80A ........................................................................................................ 96
B.23 MSP-TS430PN80USB .................................................................................................... 99
B.24 MSP-TS430PZ100 ....................................................................................................... 103
B.25 MSP-TS430PZ100A ..................................................................................................... 106
B.26 MSP-TS430PZ100B ..................................................................................................... 109
B.27 MSP-TS430PZ100C ..................................................................................................... 112
B.28 MSP-TS430PZ5x100 .................................................................................................... 115
B.29 MSP-TS430PZ100USB ................................................................................................. 118
B.30 MSP-TS430PEU128 ..................................................................................................... 122
B.31 EM430F5137RF900 ..................................................................................................... 125
B.32 EM430F6137RF900 ..................................................................................................... 129
B.33 EM430F6147RF900 ..................................................................................................... 133
B.34 MSP-FET430PIF ......................................................................................................... 137
B.35 MSP-FET430UIF ......................................................................................................... 139
B.35.1 MSP-FET430UIF Revision History .......................................................................... 144
C Hardware Installation Guide .............................................................................................. 145
C.1 Hardware Installation .................................................................................................... 146
Document Revision History ........................................................................................................ 151
SLAU278Q–May 2009–Revised February 2014 Contents 3
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List of Figures
2-1. Signal Connections for 4-Wire JTAG Communication................................................................ 21
2-2. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F2xx,
MSP430G2xx, and MSP430F4xx Devices............................................................................. 22
2-3. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F5xx and
MSP430F6xx Devices .................................................................................................... 23
B-1. MSP-TS430D8 Target Socket Module, Schematic ................................................................... 31
B-2. MSP-TS430D8 Target Socket Module, PCB .......................................................................... 32
B-3. MSP-TS430PW14 Target Socket Module, Schematic ............................................................... 34
B-4. MSP-TS430PW14 Target Socket Module, PCB ...................................................................... 35
B-5. MSP-TS430L092 Target Socket Module, Schematic................................................................. 37
B-6. MSP-TS430L092 Target Socket Module, PCB........................................................................ 38
B-7. MSP-TS430L092 Active Cable Target Socket Module, Schematic................................................. 40
B-8. MSP-TS430L092 Active Cable Target Socket Module, PCB........................................................ 41
B-9. MSP-TS430PW24 Target Socket Module, Schematic ............................................................... 43
B-10. MSP-TS430PW24 Target Socket Module, PCB ...................................................................... 44
B-11. MSP-TS430DW28 Target Socket Module, Schematic ............................................................... 46
B-12. MSP-TS430DW28 Target Socket Module, PCB ...................................................................... 47
B-13. MSP-TS430PW28 Target Socket Module, Schematic ............................................................... 49
B-14. MSP-TS430PW28 Target Socket Module, PCB ...................................................................... 50
B-15. MSP-TS430PW28A Target Socket Module, Schematic.............................................................. 52
B-16. MSP-TS430PW28A Target Socket Module, PCB (Red) ............................................................. 53
B-17. MSP-TS430DA38 Target Socket Module, Schematic ................................................................ 55
B-18. MSP-TS430DA38 Target Socket Module, PCB ....................................................................... 56
B-19. MSP-TS430QFN23x0 Target Socket Module, Schematic ........................................................... 58
B-20. MSP-TS430QFN23x0 Target Socket Module, PCB .................................................................. 59
B-21. MSP-TS430RSB40 Target Socket Module, Schematic .............................................................. 61
B-22. MSP-TS430RSB40 Target Socket Module, PCB ..................................................................... 62
B-23. MSP-TS430RHA40A Target Socket Module, Schematic ............................................................ 64
B-24. MSP-TS430RHA40A Target Socket Module, PCB ................................................................... 65
B-25. MSP-TS430DL48 Target Socket Module, Schematic ................................................................ 67
B-26. MSP-TS430DL48 Target Socket Module, PCB ....................................................................... 68
B-27. MSP-TS430RGZ48B Target Socket Module, Schematic ............................................................ 70
B-28. MSP-TS430RGZ48B Target Socket Module, PCB ................................................................... 71
B-29. MSP-TS430RGZ48C Target Socket Module, Schematic ............................................................ 73
B-30. MSP-TS430RGZ48C Target Socket Module, PCB ................................................................... 74
B-31. MSP-TS430PM64 Target Socket Module, Schematic................................................................ 76
B-32. MSP-TS430PM64 Target Socket Module, PCB....................................................................... 77
B-33. MSP-TS430PM64A Target Socket Module, Schematic .............................................................. 79
B-34. MSP-TS430PM64A Target Socket Module, PCB ..................................................................... 80
B-35. MSP-TS430RGC64B Target Socket Module, Schematic ............................................................ 82
B-36. MSP-TS430RGC64B Target Socket Module, PCB ................................................................... 83
B-37. MSP-TS430RGC64C Target Socket Module, Schematic............................................................ 86
B-38. MSP-TS430RGC64C Target Socket Module, PCB................................................................... 87
B-39. MSP-TS430RGC64USB Target Socket Module, Schematic ........................................................ 89
B-40. MSP-TS430RGC64USB Target Socket Module, PCB ............................................................... 90
B-41. MSP-TS430PN80 Target Socket Module, Schematic ................................................................ 93
B-42. MSP-TS430PN80 Target Socket Module, PCB ....................................................................... 94
B-43. MSP-TS430PN80A Target Socket Module, Schematic .............................................................. 96
4 List of Figures SLAU278Q–May 2009–Revised February 2014
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B-44. MSP-TS430PN80A Target Socket Module, PCB ..................................................................... 97
B-45. MSP-TS430PN80USB Target Socket Module, Schematic .......................................................... 99
B-46. MSP-TS430PN80USB Target Socket Module, PCB ................................................................ 100
B-47. MSP-TS430PZ100 Target Socket Module, Schematic ............................................................. 103
B-48. MSP-TS430PZ100 Target Socket Module, PCB .................................................................... 104
B-49. MSP-TS430PZ100A Target Socket Module, Schematic............................................................ 106
B-50. MSP-TS430PZ100A Target Socket Module, PCB................................................................... 107
B-51. MSP-TS430PZ100B Target Socket Module, Schematic............................................................ 109
B-52. MSP-TS430PZ100B Target Socket Module, PCB................................................................... 110
B-53. MSP-TS430PZ100C Target Socket Module, Schematic ........................................................... 112
B-54. MSP-TS430PZ100C Target Socket Module, PCB .................................................................. 113
B-55. MSP-TS430PZ5x100 Target Socket Module, Schematic .......................................................... 115
B-56. MSP-TS430PZ5x100 Target Socket Module, PCB.................................................................. 116
B-57. MSP-TS430PZ100USB Target Socket Module, Schematic........................................................ 118
B-58. MSP-TS430PZ100USB Target Socket Module, PCB............................................................... 119
B-59. MSP-TS430PEU128 Target Socket Module, Schematic ........................................................... 122
B-60. MSP-TS430PEU128 Target Socket Module, PCB .................................................................. 123
B-61. EM430F5137RF900 Target board, Schematic....................................................................... 125
B-62. EM430F5137RF900 Target board, PCB.............................................................................. 126
B-63. EM430F6137RF900 Target board, Schematic....................................................................... 129
B-64. EM430F6137RF900 Target board, PCB.............................................................................. 130
B-65. EM430F6147RF900 Target Board, Schematic ...................................................................... 133
B-66. EM430F6147RF900 Target Board, PCB ............................................................................. 134
B-67. MSP-FET430PIF FET Interface Module, Schematic ................................................................ 137
B-68. MSP-FET430PIF FET Interface Module, PCB....................................................................... 138
B-69. MSP-FET430UIF USB Interface, Schematic (1 of 4) ............................................................... 139
B-70. MSP-FET430UIF USB Interface, Schematic (2 of 4) ............................................................... 140
B-71. MSP-FET430UIF USB Interface, Schematic (3 of 4) ............................................................... 141
B-72. MSP-FET430UIF USB Interface, Schematic (4 of 4) ............................................................... 142
B-73. MSP-FET430UIF USB Interface, PCB ................................................................................ 143
C-1. Windows XP Hardware Wizard ........................................................................................ 146
C-2. Windows XP Driver Location Selection Folder....................................................................... 147
C-3. Device Manager Using USB Debug Interface using VID/PID 0x2047/0x0010................................... 148
C-4. Device Manager Using USB Debug Interface with VID/PID 0x0451/0xF430 .................................... 149
C-5. Device Manager Using USB Debug Interface with VID/PID 0x0451/0xF432 .................................... 150
SLAU278Q–May 2009–Revised February 2014 List of Figures 5
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List of Tables
1-1. Flash Emulation Tool (FET) Features and Device Compatibility.................................................... 11
1-2. Individual Kit Contents, MSP-TS430xx ................................................................................. 14
B-1. MSP-TS430D8 Bill of Materials.......................................................................................... 33
B-2. MSP-TS430PW14 Bill of Materials...................................................................................... 36
B-3. MSP-TS430L092 Bill of Materials ....................................................................................... 39
B-4. MSP-TS430L092 JP1 Settings .......................................................................................... 41
B-5. MSP-TS430L092 Active Cable Bill of Materials ....................................................................... 42
B-6. MSP-TS430PW24 Bill of Materials...................................................................................... 45
B-7. MSP-TS430DW28 Bill of Materials...................................................................................... 48
B-8. MSP-TS430PW28 Bill of Materials ..................................................................................... 51
B-9. MSP-TS430PW28A Bill of Materials .................................................................................... 54
B-10. MSP-TS430DA38 Bill of Materials ...................................................................................... 57
B-11. MSP-TS430QFN23x0 Bill of Materials.................................................................................. 60
B-12. MSP-TS430RSB40 Bill of Materials .................................................................................... 63
B-13. MSP-TS430RHA40A Bill of Materials................................................................................... 66
B-14. MSP-TS430DL48 Bill of Materials....................................................................................... 69
B-15. MSP-TS430RGZ48B Bill of Materials................................................................................... 72
B-16. MSP-TS430RGZ48C Revision History ................................................................................. 74
B-17. MSP-TS430RGZ48C Bill of Materials .................................................................................. 75
B-18. MSP-TS430PM64 Bill of Materials ...................................................................................... 78
B-19. MSP-TS430PM64A Bill of Materials .................................................................................... 81
B-20. MSP-TS430RGC64B Bill of Materials .................................................................................. 84
B-21. MSP-TS430RGC64C Bill of Materials .................................................................................. 88
B-22. MSP-TS430RGC64USB Bill of Materials............................................................................... 91
B-23. MSP-TS430PN80 Bill of Materials ...................................................................................... 95
B-24. MSP-TS430PN80A Bill of Materials .................................................................................... 98
B-25. MSP-TS430PN80USB Bill of Materials ............................................................................... 101
B-26. MSP-TS430PZ100 Bill of Materials.................................................................................... 105
B-27. MSP-TS430PZ100A Bill of Materials.................................................................................. 108
B-28. MSP-TS430PZ100B Bill of Materials.................................................................................. 111
B-29. MSP-TS430PZ100C Bill of Materials.................................................................................. 114
B-30. MSP-TS430PZ5x100 Bill of Materials................................................................................. 117
B-31. MSP-TS430PZ100USB Bill of Materials .............................................................................. 120
B-32. MSP-TS430PEU128 Bill of Materials ................................................................................. 124
B-33. EM430F5137RF900 Bill of Materials .................................................................................. 127
B-34. EM430F6137RF900 Bill of Materials .................................................................................. 131
B-35. EM430F6147RF900 Bill of Materials .................................................................................. 135
C-1. USB VIDs and PIDs Used in MSP430 Tools......................................................................... 146
6 List of Tables SLAU278Q–May 2009–Revised February 2014
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Preface
SLAU278Q–May 2009–Revised February 2014
Read This First
About This Manual
This manual describes the hardware of the Texas Instruments MSP-FET430 Flash Emulation Tool (FET).
The FET is the program development tool for the MSP430™ ultra-low-power microcontroller. Both
available interface types, the parallel port interface and the USB interface, are described.
How to Use This Manual
Read and follow the instructions in Chapter 1. This chapter lists the contents of the FET, provides
instructions on installing the hardware and according software drivers. After you see how quick and easy it
is to use the development tools, TI recommends that you read all of this manual.
This manual describes the setup and operation of the FET but does not fully describe the MSP430™
microcontrollers or the development software systems. For details of these items, see the appropriate TI
documents listed in Section 1.18.
This manual applies to the following tools (and devices):
• MSP-FET430PIF (debug interface with parallel port connection, for all MSP430 flash-based devices)
• MSP-FET430UIF (debug interface with USB connection, for all MSP430 flash-based devices)
• eZ430-F2013 (USB stick form factor interface with attached MSP430F2013 target, for all
MSP430F20xx, MSP430G2x01, MSP430G2x11, MSP430G2x21, and MSP430G2x31 devices)
• eZ430-T2012 (three MSP430F2012 based target boards)
• eZ430-RF2500 (USB stick form factor interface with attached MSP430F2274 and CC2500 target, for
all MSP430F20xx, MSP430F21x2, MSP430F22xx, MSP430G2x01, MSP430G2x11, MSP430G2x21,
and MSP430G2x31 devices)
• eZ430-RF2500T (one MSP430F2274 and CC2500 target board including battery pack)
• eZ430-RF2500-SEH (USB stick form factor interface with attached MSP430F2274 and CC2500 target
and solar energy harvesting module)
• eZ430-Chronos-xxx (USB stick form factor interface with CC430F6137 based development system
contained in a watch. Includes <1 GHz RF USB access point)
Stand-alone target-socket modules (without debug interface) named as MSP-TS430TSxx.
Tools named as MSP-FET430Uxx contain the USB debug interface (MSP-FET430UIF) and the respective
target socket module MSP-TS430TSxx, where 'xx' is the same for both names. Following tools contain
also the USB debug interface (MSP-FET430UIF):
• FET430F5137RF900 (for CC430F513x devices in 48-pin RGZ packages) (green PCB)
• FET430F6137RF900 (for CC430F612x and CC430F613x devices in 64-pin RGC packages) (green
PCB)
These tools contain the most up-to-date materials available at the time of packaging. For the latest
materials (data sheets, user's guides, software, application information, and so on), visit the TI MSP430
web site at www.ti.com/msp430 or contact your local TI sales office.
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Information About Cautions and Warnings www.ti.com
Information About Cautions and Warnings
This document may contain cautions and warnings.
CAUTION
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your
software or equipment.
WARNING
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection. Read each caution and warning
carefully.
Related Documentation From Texas Instruments
MSP430 development tools documentation:
Code Composer Studio v5.4 for MSP430 User's Guide (literature number SLAU157)
Code Composer Studio v5.x Core Edition (CCS Mediawiki)
IAR Embedded Workbench Version 3+ for MSP430(tm) User's Guide (literature number SLAU138)
IAR Embedded Workbench KickStart installer (literature number SLAC050)
eZ430-F2013 Development Tool User's Guide (literature number SLAU176)
eZ430-RF2480 Demonstration Kit User's Guide (literature number SWRU151)
eZ430-RF2500 Development Tool User's Guide (literature number SLAU227)
eZ430-RF2500-SEH Development Tool User's Guide (literature number SLAU273)
eZ430-Chronos Development Tool User's Guide (literature number SLAU292)
Spectrum Analyzer (MSP-SA430-SUB1GHZ) User's Guide (literature number SLAU371)
MSP-EXP430F5529 Experimenter Board User's Guide (literature number SLAU330)
MSP-EXP430F5438 Experimenter Board User's Guide (literature number SLAU263)
MSP-EXP430G2 LaunchPad Experimenter Board User's Guide (literature number SLAU318)
MSP Gang Programmer (MSP-GANG) User's Guide (literature number SLAU358)
MSP430 Gang Programmer (MSP-GANG430) User's Guide (literature number SLAU101)
MSP430 device user's guides:
MSP430x1xx Family User's Guide (literature number SLAU049)
MSP430x2xx Family User's Guide (literature number SLAU144)
MSP430x3xx Family User's Guide (literature number SLAU012)
MSP430x4xx Family User's Guide (literature number SLAU056)
MSP430x5xx and MSP430x6xx Family User's Guide (literature number SLAU208)
CC430 Family User's Guide (literature number SLAU259)
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www.ti.com If You Need Assistance
MSP430FR57xx Family User's Guide (literature number SLAU272)
MSP430FR58xx and MSP430FR59xx Family User's Guide (literature number SLAU367)
If You Need Assistance
Support for the MSP430 devices and the FET development tools is provided by the Texas Instruments
Product Information Center (PIC). Contact information for the PIC can be found on the TI web site at
www.ti.com/support. The Texas Instruments E2E Community support forums for the MSP430 provide
open interaction with peer engineers, TI engineers, and other experts. Additional device-specific
information can be found on the MSP430 web site.
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Chapter 1
SLAU278Q–May 2009–Revised February 2014
Get Started Now!
This chapter lists the contents of the FET and provides instruction on installing the hardware.
Topic ........................................................................................................................... Page
1.1 Flash Emulation Tool (FET) Overview .................................................................. 11
1.2 Kit Contents, MSP-FET430PIF ............................................................................. 12
1.3 Kit Contents, eZ430-F2013 .................................................................................. 12
1.4 Kit Contents, eZ430-T2012 .................................................................................. 12
1.5 Kit Contents, eZ430-RF2500 ................................................................................ 12
1.6 Kit Contents, eZ430-RF2500T .............................................................................. 12
1.7 Kit Contents, eZ430-RF2500-SEH ........................................................................ 12
1.8 Kit Contents, eZ430-Chronos-xxx ........................................................................ 13
1.9 Kit Contents, MSP-FET430UIF ............................................................................. 13
1.10 Kit Contents, MSP-FET430xx .............................................................................. 13
1.11 Kit Contents, FET430F6137RF900 ........................................................................ 14
1.12 Kit Contents, MSP-TS430xx ................................................................................ 14
1.13 Kit Contents, EM430Fx1x7RF900 ......................................................................... 16
1.14 Hardware Installation, MSP-FET430PIF ................................................................ 16
1.15 Hardware Installation, MSP-FET430UIF ................................................................ 17
1.16 Hardware Installation, eZ430-XXXX, MSP-EXP430G2, MSP-EXP430FR5739, MSPEXP430F5529
.................................................................................................... 17
1.17 Hardware Installation, MSP-FET430Uxx, MSP-TS430xxx, FET430F6137RF900,
EM430Fx137RF900 ............................................................................................ 17
1.18 Important MSP430 Documents on the Web ........................................................... 18
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www.ti.com Flash Emulation Tool (FET) Overview
1.1 Flash Emulation Tool (FET) Overview
TI offers several flash emulation tools according to different requirements.
Table 1-1. Flash Emulation Tool (FET) Features and Device Compatibility(1)
eZ430-F2013
eZ430-RF2500
eZ430-RF2480
eZ430-RF2560
MSP-WDSxx Metawatch
eZ430-Chronos
MSP-FET430PIF
MSP-FET430UIF
LaunchPad (MSP-EXP430G2)
MSP-EXP430FR5739
MSP-EXP430F5529
Supports all programmable MSP430 and
CC430 devices (F1xx, F2xx, F4xx, F5xx, F6xx, G2xx, L092, FR57xx, FR59xx, x x
MSP430TCH5E)
Supports only F20xx, G2x01, G2x11, x G2x21, G2x31
Supports MSP430F20xx, F21x2, F22xx, x G2x01, G2x11, G2x21, G2x31, G2x53
Supports MSP430F20xx, F21x2, F22xx, x x G2x01, G2x11, G2x21, G2x31
Supports F5438, F5438A x
Supports BT5190, F5438A x
Supports only F552x x
Supports FR57xx, F5638, F6638 x
Supports only CC430F613x x
Allows fuse blow x
Adjustable target supply voltage x
Fixed 2.8-V target supply voltage x
Fixed 3.6-V target supply voltage x x x x x x x x x
4-wire JTAG x x
2-wire JTAG(2) x x x x x x x x x x
Application UART x x x x x x x x
Supported by CCS for Windows x x x x x x x x x x x
Supported by CCS for Linux x
Supported by IAR x x x x x x x x x x x
(1) The MSP-FET430PIF is for legacy device support only. This emulation tool will not support any new devices released after 2011.
(2) The 2-wire JTAG debug interface is also referred to as Spy-Bi-Wire (SBW) interface.
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Kit Contents, MSP-FET430PIF www.ti.com
1.2 Kit Contents, MSP-FET430PIF
• One READ ME FIRST document
• One MSP-FET430PIF interface module
• One 25-conductor cable
• One 14-conductor cable
NOTE: This part is obsolete and is not recommended to use in new design.
1.3 Kit Contents, eZ430-F2013
• One QUICK START GUIDE document
• One eZ430-F2013 development tool including one MSP430F2013 target board
1.4 Kit Contents, eZ430-T2012
• Three MSP430F2012-based target boards
1.5 Kit Contents, eZ430-RF2500
• One QUICK START GUIDE document
• One eZ430-RF2500 CD-ROM
• One eZ430-RF2500 development tool including one MSP430F2274 and CC2500 target board
• One eZ430-RF2500T target board
• One AAA battery pack with expansion board (batteries included)
1.6 Kit Contents, eZ430-RF2500T
• One eZ430-RF2500T target board
• One AAA battery pack with expansion board (batteries included)
1.7 Kit Contents, eZ430-RF2500-SEH
• One MSP430 development tool CD containing documentation and development software
• One eZ430-RF USB debugging interface
• Two eZ430-RF2500T wireless target boards
• One SEH-01 solar energy harvester board
• One AAA battery pack with expansion board (batteries included)
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www.ti.com Kit Contents, eZ430-Chronos-xxx
1.8 Kit Contents, eZ430-Chronos-xxx
'433, '868, '915
• One QUICK START GUIDE document
• One ez430-Chronos emulator
• One screwdriver
• Two spare screws
eZ430-Chronos-433:
– One 433-MHz eZ430-Chronos watch (battery included)
– One 433-MHz eZ430-Chronos access point
eZ430-Chronos-868:
– One 868-MHz eZ430-Chronos watch (battery included)
– One 868-MHz eZ430-Chronos access point
eZ430-Chronos-915:
– One 915-MHz eZ430-Chronos watch (battery included)
– One 915-MHz eZ430-Chronos access point
1.9 Kit Contents, MSP-FET430UIF
• One READ ME FIRST document
• One MSP-FET430UIF interface module
• One USB cable
• One 14-conductor cable
1.10 Kit Contents, MSP-FET430xx
• One READ ME FIRST document
• One MSP-FET430UIF USB interface module. This is the unit that has a USB B-connector on one end
of the case, and a 2×7-pin male connector on the other end of the case.
• One USB cable
• One 32.768-kHz crystal from Micro Crystal, if the board has an option to use the quartz.
• A 2×7-pin male JTAG connector is also present on the PCB (see different setup for L092)
• One 14-Pin JTAG conductor cable
• One small box containing two MSP430 device samples (See table for Sample Type)
• One target socket module. To determine the devices used for each board and a summary of the board,
see Table 1-2. The name of MSP-TS430xx board can be derived from the name of the MSP-FET430xx
kit; for example, the MSP-FET430U28A kit contains the MSP-TS430PW28A board.
Refer to the device data sheets for device specifications. Device errata can be found in the respective
device product folder on the web provided as a PDF document. Depending on the device, errata may also
be found in the device bug database at www.ti.com/sc/cgi-bin/buglist.cgi.
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Kit Contents, FET430F6137RF900 www.ti.com
1.11 Kit Contents, FET430F6137RF900
• One READ ME FIRST document
• One legal notice
• One MSP-FET430UIF interface module
• Two EM430F6137RF900 target socket modules. This is the PCB on which is soldered a CC430F6137
device in a 64-pin RGC package. A 2×7-pin male connector is also present on the PCB.
• Two CC430EM battery packs
• Four AAA batteries
• Two 868-MHz or 915-MHz antennas
• Two 32.768-kHz crystals
• 18 PCB 2x4-pin headers
• One USB cable
• One 14-pin JTAG conductor cable
1.12 Kit Contents, MSP-TS430xx
• One READ ME FIRST document
• One 32.768-kHz crystal from Micro Crystal (except MSP-TS430PW24)
• One target socket module
• A 2×7-pin male JTAG connector is also present on the PCB (see different setup for L092)
• MSP430 Device samples (see Table 1-2 for sample type)
Table 1-2. Individual Kit Contents, MSP-TS430xx
Part Number Socket Type Supported Devices Included Devices Headers and Comment
MSP-TS430D8 8-pin D MSP430G2210, 1 x MSP430G2210 and Two PCB 1×4-pin headers (two male and
(green PCB) (TSSOP ZIF) MSP430G2230 1 x MSP430G2230 two female)
MSP430F20xx,
MSP-TS430PW14 14-pin PW MSP430G2x01, Four PCB 1×7-pin headers (two male and (green PCB) (TSSOP ZIF) MSP430G2x11, 2 x MSP430F2013IPW two female) MSP430G2x21,
MSP430G2x31
Four PCB 1×7-pin headers (two male and
two female). A "Micro-MaTch" 10-pin
MSP-TS430L092 14-pin PW female connector is also present on the (green PCB) (TSSOP ZIF) MSP-TS430L092 2 x MSP430L092IPW PCB which connects the kit with an 'Active Cable' PCB; this 'Active Cable'
PCB is connected by 14-pin JTAG cable
with the FET430UIF
MSP-TS430PW24 24-pin PW MSP430AFE2xx 2 x MSP430AFE253IPW Four PCB 1×12-pin headers (two male (green PCB) (TSSOP ZIF) and two female)
MSP430F11x1,
MSP430F11x2,
MSP-TS430DW28 28-pin DW MSP430F12x, Four PCB 1×12-pin headers (two male (green PCB) (SSOP ZIF) MSP430F12x2, 2 x MSP430F123IDW and two female) MSP430F21xx
Supports devices in 20- and
28-pin DA packages
MSP430F11x1,
MSP-TS430PW28 28-pin PW MSP430F11x2, Four PCB 1×12-pin headers (two male (green PCB) (TSSOP ZIF) MSP430F12x, 2 x MSP430F2132IPW and two female) MSP430F12x2,
MSP430F21xx
MSP430F20xx,
MSP-TS430PW28A 28-pin PW MSP430G2xxx in 14-, 20-, Four PCB 1×12-pin headers (two male (red PCB) (TSSOP ZIF) and 28-pin PW packages, 2 x MSP430G2452IPW20 and two female) MSP430TCH5E in PW
package
MSP-TS430DA38 38-pin DA MSP430F22xx, 2 x MSP430F2274IDA Four PCB 1×19-pin headers (two male (green PCB) (TSSOP ZIF) MSP430G2x44, 2 x MSP430G2744IDA and two female) MSP430G2x55 2 x MSP430G2955IDA
MSP-TS430QFN23x0 40-pin RHA MSP430F23x0 2 x MSP430F2370IRHA Eight PCB 1×10-pin headers (four male (green PCB) (QFN ZIF) and four female)
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Table 1-2. Individual Kit Contents, MSP-TS430xx (continued)
Part Number Socket Type Supported Devices Included Devices Headers and Comment
MSP-TS430RSB40 40-pin RSB MSP430F51x1, 2 x MSP430F5172IRSB Eight PCB 1×10-pin headers (four male (green PCB) (QFN ZIF) MSP430F51x2 and four female)
MSP-TS430RHA40A 40-pin RHA MSP430FR572x, 2 x MSP430FR5739IRHA Eight PCB 1×10-pin headers (four male (red PCB) (QFN ZIF) MSP430FR573x and four female)
MSP-TS430DL48 48-pin DL MSP430F42x0 2 x MSP430F4270IDL Four PCB 2×12-pin headers (two male (green PCB) (TSSOP ZIF) and two female)
MSP-TS430RGZ48B 48-pin RGZ MSP430F534x 2 x MSP430F5342IRGZ Eight PCB 1×12-pin headers (four male (blue PCB) (QFN ZIF) and four female)
MSP-TS430RGZ48C 48-pin RGZ MSP430FR58xx and 2 x MSP430FR5969IRGZ Eight PCB 1×12-pin headers (four male (black PCB) (QFN ZIF) MSP430FR59xx and four female)
MSP430F13x,
MSP430F14x,
MSP430F14x1,
MSP430F15x,
MSP430F16x,
MSP430F16x1,
MSP430F23x, TS Kit:
MSP-TS430PM64 64-pin PM MSP430F24x, 2 x MSP430F2618IPM; Eight PCB 1×16-pin headers (four male (green PCB) (QFP ZIF) MSP430F24xx, FET Kit: and four female) MSP430F261x, 2 x MSP430F417IPM and
MSP430F41x, 2 x MSP430F169IPM
MSP430F42x,
MSP430F42xA,
MSP430FE42x,
MSP430FE42xA,
MSP430FE42x2,
MSP430FW42x
MSP-TS430PM64A 64-pin PM MSP430F41x2 2 x MSP430F4152IPM Eight PCB 1×16-pin headers (four male (red PCB) (QFP ZIF) and four female)
MSP-TS430RGC64B 64-pin RGC MSP430F530x 2 x MSP430F5310IRGC Eight PCB 1×16-pin headers (four male (blue PCB) (QFN ZIF) and four female)
MSP430F522x,
MSP-TS430RGC64C 64-pin RGC MSP430F521x , Eight PCB 1×16-pin headers (four male (black PCB) (QFN ZIF) MSP430F523x, 2 x MSP430F5229IRGC and four female) MSP430F524x,
MSP430F525x
MSP-TS430RGC64USB 64-pin RGC MSP430F550x, 2 x MSP430F5510IRGC or Eight PCB 1×16-pin headers (four male (green PCB) (QFN ZIF) MSP430F551x, 2 x MSP430F5528IRGC and four female) MSP430F552x
MSP430F241x,
MSP430F261x,
MSP-TS430PN80 80-pin PN MSP430F43x, Eight PCB 1×20-pin headers (four male (green PCB) (QFP ZIF) MSP430F43x1, 2 x MSP430FG439IPN and four female) MSP430FG43x,
MSP430F47x,
MSP430FG47x
MSP-TS430PN80A 80-pin PN MSP430F532x 2 x MSP430F5329IPN Eight PCB 1×20-pin headers (four male (red PCB) (QFP ZIF) and four female)
MSP-TS430PN80USB 80-pin PN MSP430F552x, 2 x MSP430F5529IPN Eight PCB 1×20-pin headers (four male (green PCB) (QFP ZIF) MSP430F551x and four female)
MSP430F43x,
MSP-TS430PZ100 100-pin PZ MSP430F43x1, Eight PCB 1×25-pin headers (four male (green PCB) (QFP ZIF) MSP430F44x, 2 x MSP430FG4619IPZ and four female) MSP430FG461x, MSP430
F47xx
MSP-TS430PZ100A 100-pin PZ MSP430F471xx 2 x MSP430F47197IPZ Eight PCB 1×25-pin headers (four male (red PCB) (QFP ZIF) and four female)
MSP-TS430PZ100B 100-pin PZ MSP430F67xx 2 x MSP430F6733IPZ Eight PCB 1×25-pin headers (four male (blue PCB) (QFP ZIF) and four female)
MSP430F645x,
MSP-TS430PZ100C 100-pin PZ MSP430F643x, 2 x MSP430F6438IPZ Eight PCB 1×25-pin headers (four male (black PCB) (QFP ZIF) MSP430F535x, and four female)
MSP430F533x
MSP-TS430PZ5x100 100-pin PZ MSP430F543x, Eight PCB 1×25-pin headers (four male (green PCB) (QFP ZIF) MSP430BT5190, 2 x MSP430F5438IPZ and four female) MSP430SL5438A
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Table 1-2. Individual Kit Contents, MSP-TS430xx (continued)
Part Number Socket Type Supported Devices Included Devices Headers and Comment
MSP-TS430PZ100USB 100-pin PZ MSP430F665x, Eight PCB 1×25-pin headers (four male (green PCB) (QFP ZIF) MSP430F663x, 2 x MSP430F6638IPZ and four female) MSP430F563x
MSP430F677x,
MSP430F676x, Four PCB 1x26-pin headers (two male MSP-TS430PEU128 128-pin PEU MSP430F674x, 2 x MSP430F67791IPEU and two female) and four PCB 1x38-pin (green PCB) (QFP ZIF) MSP430F677x1, headers (two male and two female) MSP430F676x1,
MSP430F674x1
See the device data sheets for device specifications. Device errata can be found in the respective device
product folder on the web provided as a PDF document. Depending on the device, errata may also be
found in the device bug database at www.ti.com/sc/cgi-bin/buglist.cgi.
1.13 Kit Contents, EM430Fx1x7RF900
• One READ ME FIRST document
• One legal notice
• Two target socket module
MSP-EM430F5137RF900: Two EM430F5137RF900 target socket modules. This is the PCB on which
is soldered a CC430F5137 device in a 48-pin RGZ package. A 2×7-pin male connector is also present
on the PCB
MSP-EM430F6137RF900: Two EM430F6137RF900 target socket modules. This is the PCB on which
is soldered a CC430F6137 device in a 64-pin RGC package. A 2×7-pin male connector is also present
on the PCB
MSP-EM430F6147RF900: Two EM430F6147RF900 target socket modules. This is the PCB on which
is soldered a CC430F6147 device in a 64-pin RGC package. A 2×7-pin male connector is also present
on the PCB
• Two CC430EM battery packs
• Four AAA batteries
• Two 868- or 915-MHz antennas
• Two 32.768-kHz crystals
• 18 PCB 2×4-pin headers
1.14 Hardware Installation, MSP-FET430PIF
Follow these steps to install the hardware for the MSP-FET430PIF tools:
1. Use the 25-conductor cable to connect the FET interface module to the parallel port of the PC. The
necessary driver for accessing the PC parallel port is installed automatically during CCS or IAR
Embedded Workbench installation. Note that a restart is required after the CCS or IAR Embedded
Workbench installation for the driver to become active.
2. Use the 14-conductor cable to connect the parallel-port debug interface module to a target board, such
as an MSP-TS430xxx target socket module. Module schematics and PCBs are shown in Appendix B.
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1.15 Hardware Installation, MSP-FET430UIF
Follow these steps to install the hardware for the MSP-FET430UIF tool:
1. Install the IDE (CCS or IAR) you plan to use before connecting USB-FET interface to PC. The IDE
installation installs drivers automatically.
2. Use the USB cable to connect the USB-FET interface module to a USB port on the PC. The USB FET
should be recognized, as the USB device driver is installed automatically. If the driver has not been
installed yet, the install wizard starts. Follow the prompts and point the wizard to the driver files.
The default location for CCS is c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_CDC or
c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_FET_XP_XX, depending of firmware version of
the tool.
The default location for IAR Embedded Workbench is \Embedded Workbench x.x\
430\drivers\TIUSBFET\eZ430-UART or \Embedded Workbench x.x\
430\drivers\, depending of firmware version of the tool.
The USB driver is installed automatically. Detailed driver installation instructions can be found in
Appendix C.
3. After connecting to a PC, the USB FET performs a self-test during which the red LED may flash for
approximately two seconds. If the self-test passes successfully, the green LED stays on.
4. Use the 14-conductor cable to connect the USB-FET interface module to a target board, such as an
MSP-TS430xxx target socket module.
5. Ensure that the MSP430 device is securely seated in the socket, and that its pin 1 (indicated with a
circular indentation on the top surface) aligns with the "1" mark on the PCB.
6. Compared to the parallel-port debug interface, the USB FET has additional features including JTAG
security fuse blow and adjustable target VCC (1.8 V to 3.6 V). Supply the module with up to 60 mA.
1.16 Hardware Installation, eZ430-XXXX, MSP-EXP430G2, MSP-EXP430FR5739, MSPEXP430F5529
To install eZ430-XXXX, MSP-EXP430G2, MSP-EXP430FR5739, MSP-EXP430F5529 tools follow
instructions 1 and 2 of Section 1.15
1.17 Hardware Installation, MSP-FET430Uxx, MSP-TS430xxx, FET430F6137RF900,
EM430Fx137RF900
Follow these steps to install the hardware for the MSP-FET430Uxx and MSP-TS430xxx tools:
1. Follow instructions 1 and 2 of Section 1.15
2. Connect the MSP-FET430PIF or MSP-FET430UIF debug interface to the appropriate port of the PC.
Use the 14-conductor cable to connect the FET interface module to the supplied target socket module.
3. Ensure that the MSP430 device is securely seated in the socket and that its pin 1 (indicated with a
circular indentation on the top surface) aligns with the "1" mark on the PCB.
4. Ensure that the two jumpers (LED and VCC) near the 2×7-pin male connector are in place. Illustrations
of the target socket modules and their parts are found in Appendix B.
SLAU278Q–May 2009–Revised February 2014 Get Started Now! 17
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Important MSP430 Documents on the Web www.ti.com
1.18 Important MSP430 Documents on the Web
The primary sources of MSP430 information are the device-specific data sheet and user's guide. The
MSP430 web site (www.ti.com/msp430) contains the most recent version of these documents.
PDF documents describing the CCS tools (CCS IDE, the assembler, the C compiler, the linker, and the
librarian) are in the msp430\documentation folder. A Code Composer Studio specific Wiki page (FAQ) is
available, and the Texas Instruments E2E Community support forums for the MSP430 and Code
Composer Studio v5 provide additional help besides the product help and Welcome page.
PDF documents describing the IAR tools (Workbench C-SPY, the assembler, the C compiler, the linker,
and the librarian) are in the common\doc and 430\doc folders. Supplements to the documents (that is, the
latest information) are available in HTML format in the same directories. A IAR specific Wiki Page is also
available.
18 Get Started Now! SLAU278Q–May 2009–Revised February 2014
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Chapter 2
SLAU278Q–May 2009–Revised February 2014
Design Considerations for In-Circuit Programming
This chapter presents signal requirements for in-circuit programming of the MSP430.
Topic ........................................................................................................................... Page
2.1 Signal Connections for In-System Programming and Debugging ............................ 20
2.2 External Power .................................................................................................. 24
2.3 Bootstrap Loader (BSL) ..................................................................................... 24
SLAU278Q–May 2009–Revised February 2014 Design Considerations for In-Circuit Programming 19
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Signal Connections for In-System Programming and Debugging www.ti.com
2.1 Signal Connections for In-System Programming and Debugging
MSP-FET430PIF, MSP-FET430UIF, MSP-GANG, MSP-GANG430, MSP-PRGS430
With the proper connections, the debugger and an FET hardware JTAG interface (such as the MSPFET430PIF
and MSP-FET430UIF) can be used to program and debug code on the target board. In
addition, the connections also support the MSP-GANG430 or MSP-PRGS430 production programmers,
thus providing an easy way to program prototype boards, if desired.
Figure 2-1 shows the connections between the 14-pin FET interface module connector and the target
device required to support in-system programming and debugging for 4-wire JTAG communication.
Figure 2-2 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire). The 4-wire JTAG mode is
supported on most MSP430 devices, except devices with low pin counts (for example, MSP430G2230).
The 2-wire JTAG mode is available on selected devices only. See the Code Composer Studio for MSP430
User's Guide (SLAU157) or IAR Embedded Workbench Version 3+ for MSP430 User's Guide (SLAU138)
for information on which interface method can be used on which device.
The connections for the FET interface module and the MSP-GANG, MSP-GANG430, or MSP-PRGS430
are identical. Both the FET interface module and MSP-GANG430 can supply VCC to the target board
(through pin 2). In addition, the FET interface module, MSP-GANG, and MSP-GANG430 have a VCCsense
feature that, if used, requires an alternate connection (pin 4 instead of pin 2). The VCC-sense feature
senses the local VCC present on the target board (that is, a battery or other local power supply) and
adjusts the output signals accordingly. If the target board is to be powered by a local VCC, then the
connection to pin 4 on the JTAG should be made, and not the connection to pin 2. This uses the VCCsense
feature and prevents any contention that might occur if the local on-board VCC were connected to
the VCC supplied from the FET interface module, MSP-GANG or the MSP-GANG430. If the VCC-sense
feature is not necessary (that is, if the target board is to be powered from the FET interface module, MSPGANG,
or MSP-GANG430), the VCC connection is made to pin 2 on the JTAG header, and no connection
is made to pin 4. Figure 2-1 and Figure 2-2 show a jumper block that supports both scenarios of supplying
VCC to the target board. If this flexibility is not required, the desired VCC connections may be hard-wired to
eliminate the jumper block. Pins 2 and 4 must not be connected at the same time.
Note that in 4-wire JTAG communication mode (see Figure 2-1), the connection of the target RST signal
to the JTAG connector is optional when using devices that support only 4-wire JTAG communication
mode. However, when using devices that support 2-wire JTAG communication mode in 4-wire JTAG
mode, the RST connection must be made. The MSP430 development tools and device programmers
perform a target reset by issuing a JTAG command to gain control over the device. However, if this is
unsuccessful, the RST signal of the JTAG connector may be used by the development tool or device
programmer as an additional way to assert a device reset.
20 Design Considerations for In-Circuit Programming SLAU278Q–May 2009–Revised February 2014
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1
3
5
7
9
11
13
2
4
6
8
10
12
14
TDO/TDI
TDI/VPP
TMS
TCK
GND
TEST/VPP
JTAG
VCC TOOL
VCC TARGET
J1 (see Note A)
J2 (see Note A)
VCC
R1
47 k
(see Note B)
W
C2
10 μF
C3
0.1 μF
VCC/AVCC/DVCC
RST/NMI
TDO/TDI
TDI/VPP
TMS
TCK
TEST/VPP (see Note C)
V /AV /DV SS SS SS
MSP430Fxxx
C1
10 nF/2.2 nF
(see Notes B and E)
RST (see Note D)
Important to connect
www.ti.com Signal Connections for In-System Programming and Debugging
A If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B The configuration of R1 and C1 for the RST/NMI pin depends on the device family. See the respective MSP430 family
user's guide for the recommended configuration.
C The TEST pin is available only on MSP430 family members with multiplexed JTAG pins. See the device-specific data
sheet to determine if this pin is available.
D The connection to the JTAG connector RST pin is optional when using a device that supports only 4-wire JTAG
communication mode, and it is not required for device programming or debugging. However, this connection is
required when using a device that supports 2-wire JTAG communication mode in 4-wire JTAG mode.
E When using a device that supports 2-wire JTAG communication in 4-wire JTAG mode, the upper limit for C1 should
not exceed 2.2 nF. This applies to both TI FET interface modules (LPT and USB FET).
Figure 2-1. Signal Connections for 4-Wire JTAG Communication
SLAU278Q–May 2009–Revised February 2014 Design Considerations for In-Circuit Programming 21
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1
3
5
7
9
11
13
2
4
6
8
10
12
14
TEST/SBWTCK
MSP430Fxxx
RST/NMI/SBWTDIO
TDO/TDI
TCK
GND
TEST/VPP
JTAG
VCC TOOL
VCC TARGET
330!
R2
J1 (see Note A)
J2 (see Note A)
Important to connect
VCC/AVCC/DVCC
V /AV /DV SS SS SS
R1
47 k!
See Note B
C1
2.2 nF
See Note B
VCC
C2
10 μF
C3
0.1 μF
Signal Connections for In-System Programming and Debugging www.ti.com
A If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
B The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
C R2 protects the JTAG debug interface TCK signal from the JTAG security fuse blow voltage that is supplied by the
TEST/VPP pin during the fuse blow process. If fuse blow functionality is not needed, R2 is not required (populate 0 Ω)
and do not connect TEST/VPP to TEST/SBWTCK.
Figure 2-2. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F2xx,
MSP430G2xx, and MSP430F4xx Devices
22 Design Considerations for In-Circuit Programming SLAU278Q–May 2009–Revised February 2014
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1
3
5
7
9
11
13
2
4
6
8
10
12
14
TEST/SBWTCK
MSP430Fxxx
RST/NMI/SBWTDIO
TDO/TDI
TCK
GND
JTAG
R1
47 k!
See Note B
VCC TOOL
VCC TARGET
C1
2.2 nF
See Note B
J1 (see Note A)
J2 (see Note A)
Important to connect
VCC/AVCC/DVCC
V /AV /DV SS SS SS
VCC
C2
10 μF
C3
0.1 μF
www.ti.com Signal Connections for In-System Programming and Debugging
A Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
B The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 2-3. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F5xx and
MSP430F6xx Devices
SLAU278Q–May 2009–Revised February 2014 Design Considerations for In-Circuit Programming 23
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External Power www.ti.com
2.2 External Power
The MSP-FET430UIF can supply targets with up to 60 mA through pin 2 of the 14-pin connector. Note
that the target should not consume more than 60 mA, even as a peak current, as it may violate the USB
specification. For example, if the target board has a capacitor on VCC more than 10 μF, it may cause
inrush current during capacitor charging that may exceed 60 mA. In this case, the current should be
limited by the design of the target board, or an external power supply should be used.
The VCC for the target can be selected between 1.8 V and 3.6 V in steps of 0.1 V. Alternatively, the target
can be supplied externally. In this case, the external voltage should be connected to pin 4 of the 14-pin
connector. The MSP-FET430UIF then adjusts the level of the JTAG signals to external VCC automatically.
Only pin 2 (MSP-FET430UIF supplies target) or pin 4 (target is externally supplied) must be connected;
not both at the same time.
When a target socket module is powered from an external supply, the external supply powers the device
on the target socket module and any user circuitry connected to the target socket module, and the FET
interface module continues to be powered from the PC through the parallel port. If the externally supplied
voltage differs from that of the FET interface module, the target socket module must be modified so that
the externally supplied voltage is routed to the FET interface module (so that it may adjust its output
voltage levels accordingly). See the target socket module schematics in Appendix B.
The PC parallel port can source a limited amount of current. Because of the ultra-low-power requirement
of the MSP430, a standalone FET does not exceed the available current. However, if additional circuitry is
added to the tool, this current limit could be exceeded. In this case, external power can be supplied to the
tool through connections provided on the target socket modules. See the schematics and pictorials of the
target socket modules in Appendix B to locate the external power connectors. Note that the MSPFET430PIF
is not recommended for new design.
2.3 Bootstrap Loader (BSL)
The JTAG pins provide access to the memory of the MSP430 and CC430 devices. On some devices,
these pins are shared with the device port pins, and this sharing of pins can complicate a design (or
sharing may not be possible). As an alternative to using the JTAG pins, most MSP430Fxxx devices
contain a program (a "bootstrap loader") that permits the flash memory to be erased and programmed
using a reduced set of signals. The MSP430 Programming Via the Bootstrap Loader User's Guide
(SLAU319) describes this interface. See the MSP430 web site for the application reports and a list of
MSP430 BSL tool developers.
TI suggests that MSP430Fxxx customers design their circuits with the BSL in mind (that is, TI suggests
providing access to these signals by, for example, a header).
See FAQ Hardware #10 for a second alternative to sharing the JTAG and port pins.
24 Design Considerations for In-Circuit Programming SLAU278Q–May 2009–Revised February 2014
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Appendix A
SLAU278Q–May 2009–Revised February 2014
Frequently Asked Questions and Known Issues
This appendix presents solutions to frequently asked questions regarding the MSP-FET430 hardware.
Topic ........................................................................................................................... Page
A.1 Hardware FAQs ................................................................................................. 26
A.2 Known Issues ................................................................................................... 28
SLAU278Q–May 2009–Revised February 2014 Frequently Asked Questions and Known Issues 25
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Hardware FAQs www.ti.com
A.1 Hardware FAQs
1. MSP430F22xx Target Socket Module (MSP-TS430DA38) – Important Information
Due to the large capacitive coupling introduced by the device socket between the adjacent signals
XIN/P2.6 (socket pin 6) and RST/SBWTDIO (socket pin 7), in-system debugging can disturb the
LFXT1 low-frequency crystal oscillator operation (ACLK). This behavior applies only to the Spy-Bi-Wire
(2-wire) JTAG configuration and only to the period while a debug session is active.
Workarounds:
• Use the 4-wire JTAG mode debug configuration instead of the Spy-Bi-Wire (2-wire) JTAG
configuration. This can be achieved by placing jumpers JP4 through JP9 accordingly.
• Use the debugger option "Run Free" that can be selected from the Advanced Run drop-down
menu (at top of Debug View). This prevents the debugger from accessing the MSP430 device
while the application is running. Note that, in this mode, a manual halt is required to see if a
breakpoint was hit. See the IDE documentation for more information on this feature.
• Use an external clock source to drive XIN directly.
2. With current interface hardware and software, there is a weakness when adapting target boards
that are powered externally. This leads to an accidental fuse check in the MSP430 device. This is
valid for PIF and UIF but is seen most often on the UIF. A solution is being developed.
Workarounds:
• Connect the RST/NMI pin to the JTAG header (pin 11). LPT and USB tools are able to pull the
RST line, which also resets the device internal fuse logic.
• Use the debugger option "Release JTAG On Go" that can be selected from the IDE drop-down
menu. This prevents the debugger from accessing the MCU while the application is running. Note
that in this mode, a manual halt is required to see if a breakpoint was hit. See the IDE
documentation for more information on this feature.
• Use an external clock source to drive XIN directly.
3. The 14-conductor cable that connects the FET interface module and the target socket module must
not exceed 8 inches (20 centimeters) in length.
4. The signal assignment on the 14-conductor cable is identical for the parallel port interface and the
USB FET.
5. To use the on-chip ADC voltage references, the capacitor must be installed on the target socket
module. See the schematic of the target socket module to populate the capacitor according to the data
sheet of the device.
6. To use the charge pump on the devices with LCD+ Module, the capacitor must be installed on
the target socket module. See the schematic of the target socket module to populate the capacitor
according to the data sheet of the device.
7. Crystals or resonators Q1 and Q2 (if applicable) are not provided on the target socket module.
For MSP430 devices that contain user-selectable loading capacitors, see the device and crystal data
sheets for the value of capacitance.
8. Crystals or resonators have no effect upon the operation of the tool and the CCS debugger or
C-SPY (as any required clocking and timing is derived from the internal DCO and FLL).
9. On devices with multiplexed port or JTAG pins, to use these pin in their port capability:
For CCS: "Run Free" (in Run pulldown menu at top of Debug View) must be selected.
For C-SPY: "Release JTAG On Go" must be selected.
10. As an alternative to sharing the JTAG and port pins (on low pin count devices), consider using
an MSP430 device that is a "superset" of the smaller device. A very powerful feature of the
MSP430 is that the family members are code and architecturally compatible, so code developed on
one device (for example, one without shared JTAG and port pins) ports effortlessly to another
(assuming an equivalent set of peripherals).
26 Frequently Asked Questions and Known Issues SLAU278Q–May 2009–Revised February 2014
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www.ti.com Hardware FAQs
11. Information memory may not be blank (erased to 0xFF) when the device is delivered from TI.
Customers should erase the information memory before its first use. Main memory of packaged
devices is blank when the device is delivered from TI.
12. The device current is higher then expected. The device current measurement may not be accurate
with the debugger connected to the device. For accurate measurement, disconnect the debugger.
Additionally some unused pins of the device should be terminated. See the Connection of Unused Pins
table in the device's family user's guide.
13. The following ZIF sockets are used in the FET tools and target socket modules:
• 8-pin device (D package): Yamaichi IC369-0082
• 14-pin device (PW package): Enplas OTS-14-065-01
• 14-pin package for 'L092 (PW package): Yamaichi IC189-0142-146
• 24-pin package (PW package): Enplas OTS-24(28)-0.65-02
• 28-pin device (DW package): Wells-CTI 652 D028
• 28-pin device (PW package): Enplas OTS-28-0.65-01
• 38-pin device (DA package): Yamaichi IC189-0382-037
• 40-pin device (RHA package): Enplas QFN-40B-0.5-01
• 40-pin device (RSB package): Enplas QFN-40B-0.4
• 48-pin device (RGZ package): Yamaichi QFN11T048-008 A101121-001
• 48-pin device (DL package): Yamaichi IC51-0482-1163
• 64-pin device (PM package): Yamaichi IC51-0644-807
• 64-pin device (RGC package): Yamaichi QFN11T064-006
• 80-pin device (PN package): Yamaichi IC201-0804-014
• 100-pin device (PZ package): Yamaichi IC201-1004-008
• 128-pin device (PEU package): Yamaichi IC500-1284-009P
Enplas: www.enplas.com
Wells-CTI: www.wellscti.com
Yamaichi: www.yamaichi.us
SLAU278Q–May 2009–Revised February 2014 Frequently Asked Questions and Known Issues 27
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Known Issues www.ti.com
A.2 Known Issues
MSP-FET430UIF Current detection algorithm of the UIF firmware
Problem Description If high current is detected, the ICC monitor algorithm stays in a loop of frequently
switching on and off the target power supply. This power switching puts some MSP430
devices such as the MSP430F5438 in a state that requires a power cycle to return the
device to JTAG control.
A side issue is that if the UIF firmware has entered this switch on and switch off loop, it
is not possible to turn off the power supply to the target by calling MSP430_VCC(0). A
power cycle is required to remove the device from this state.
Solution IAR KickStart and Code Composer Essentials that have the MSP430.dll version
2.04.00.003 and higher do not show this problem. Update the software development tool
to this version or higher to update the MSP-FET430UIF firmware.
MSP-FET430PIF Some PCs do not supply 5 V through the parallel port
Problem Description Device identification problems with modern PCs, because the parallel port often does not
deliver 5 V as was common with earlier hardware.
1. When connected to a laptop, the test signal is clamped to 2.5 V.
2. When the external VCC becomes less than 3 V, up to 10 mA is flowing in the adapter
through pin 4 (sense).
Solution Measure the voltage level of the parallel port. If it is too low, provide external 5 V to the
VCC pads of the interface. The jumper on a the target socket must be switched to
external power.
28 Frequently Asked Questions and Known Issues SLAU278Q–May 2009–Revised February 2014
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Appendix B
SLAU278Q–May 2009–Revised February 2014
Hardware
This appendix contains information relating to the FET hardware, including schematics, PCB pictorials,
and bills of materials (BOMs). All other tools, such as the eZ430 series, are described in separate productspecific
user's guides.
SLAU278Q–May 2009–Revised February 2014 Hardware 29
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Appendix B www.ti.com
Topic ........................................................................................................................... Page
B.1 MSP-TS430D8 ................................................................................................... 31
B.2 MSP-TS430PW14 ............................................................................................... 34
B.3 MSP-TS430L092 ................................................................................................ 37
B.4 MSP-TS430L092 Active Cable ............................................................................. 40
B.5 MSP-TS430PW24 ............................................................................................... 43
B.6 MSP-TS430DW28 ............................................................................................... 46
B.7 MSP-TS430PW28 ............................................................................................... 49
B.8 MSP-TS430PW28A ............................................................................................. 52
B.9 MSP-TS430DA38 ............................................................................................... 55
B.10 MSP-TS430QFN23x0 .......................................................................................... 58
B.11 MSP-TS430RSB40 ............................................................................................. 61
B.12 MSP-TS430RHA40A ........................................................................................... 64
B.13 MSP-TS430DL48 ................................................................................................ 67
B.14 MSP-TS430RGZ48B ........................................................................................... 70
B.15 MSP-TS430RGZ48C ........................................................................................... 73
B.16 MSP-TS430PM64 ............................................................................................... 76
B.17 MSP-TS430PM64A ............................................................................................. 79
B.18 MSP-TS430RGC64B ........................................................................................... 82
B.19 MSP-TS430RGC64C ........................................................................................... 85
B.20 MSP-TS430RGC64USB ....................................................................................... 89
B.21 MSP-TS430PN80 ............................................................................................... 93
B.22 MSP-TS430PN80A ............................................................................................. 96
B.23 MSP-TS430PN80USB ......................................................................................... 99
B.24 MSP-TS430PZ100 ............................................................................................ 103
B.25 MSP-TS430PZ100A .......................................................................................... 106
B.26 MSP-TS430PZ100B .......................................................................................... 109
B.27 MSP-TS430PZ100C .......................................................................................... 112
B.28 MSP-TS430PZ5x100 ......................................................................................... 115
B.29 MSP-TS430PZ100USB ...................................................................................... 118
B.30 MSP-TS430PEU128 .......................................................................................... 122
B.31 EM430F5137RF900 ........................................................................................... 125
B.32 EM430F6137RF900 ........................................................................................... 129
B.33 EM430F6147RF900 ........................................................................................... 133
B.34 MSP-FET430PIF ............................................................................................... 137
B.35 MSP-FET430UIF ............................................................................................... 139
30 Hardware SLAU278Q–May 2009–Revised February 2014
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Copyright © 2009–2014, Texas Instruments Incorporated
GND
100nF
330R
10uF/10V
47K
2.2nF
GND
330R
GND
GND
green
FE4L FE4H
GND
Ext_PWR
Socket: YAMAICHI
Type: IC369-0082
Vcc
ext
int
to measure supply current DNP
1
3
5
7
9
11
13
2
4
6
12
14
8
10
SBW
C5
R3
C7
R5
C8
1
2
3
J3
1
2
J4
1
2
J6
1
2
3
J5 R2
D1
1
2
3
4
J1
5
6
7
8
J2
DVCC
1
DVSS
8
P1.2/TA1/A2
2
P1.5/TA0/A5/SCLK
3
P1.6/TA1/A6/SDO/SCL
4
TST/SBWTCK
7
RST/SBWTDIO
6
P1.7/A7/SDI/SDA
5
U1
MSP-TS430D8
GND
VCC
RST/SBWTDIO
RST/SBWTDIO
RST/SBWTDIO
SBWTCK
VCC430
TST/SBWTCK
TST/SBWTCK
TST/SBWTCK
P1.5
P1.6 P1.7
P1.2
Date: 28.07.201111:03:35 Sheet: /11
REV:
TITLE:
Document Number:
MSP-TS430D8
+
1.0
MSP-TS430D8 Target Socket Board
www.ti.com MSP-TS430D8
B.1 MSP-TS430D8
Figure B-1. MSP-TS430D8 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 31
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Connector J5
External power connector
Jumper JP3 to "ext"
Jumper JP2
Open to disconnect LED
D1 LED connected to P1.2
Orient Pin 1 of MSP430 device
14 pin connector for debugging only
in Spy-Bi-Wire mode (4 Wire JTAG
not available)
MSP-TS430D8 www.ti.com
Figure B-2. MSP-TS430D8 Target Socket Module, PCB
32 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430D8
Table B-1. MSP-TS430D8 Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 J4, J6 2 2-pin header, male, TH SAM1035-02-ND place jumper on header
2 J5 1 3-pin header, male, TH SAM1035-03-ND place jumper on pins 1-2
3 SBW 1 10-pin connector, male, TH HRP10H-ND
4 J3 1 3-pin header, male, TH SAM1035-03-ND
5 C8 1 2.2nF, CSMD0805 Buerklin 53 D 292
6 C7 1 10uF, 10V, 1210ELKO 478-3875-1-ND
7 R5 1 47K, 0805 541-47000ATR-ND
8 C5 1 100nF, CSMD0805 311-1245-2-ND
9 R2, R3 2 330R, 0805 541-330ATR-ND
10 J1, J2 2 4-pin header, TH SAM1029-04-ND DNP: headers enclosed with kit. Keep vias free of solder.
10,1 J1, J2 1 4-pin socket, TH SAM1029-04-ND DNP: receptacles enclosed with kit.
11 U1 1 SO8 Socket: Type IC369-0082 Manuf.: Yamaichi
12 D1 1 red, LED 0603
13 MSP430 2 MSP430x "DNP: enclosed with kit. Is supplied by TI"
14 PCB 1 50,0mmx44,5mm MSP-TS430D8 Rev. 1.0
SLAU278Q–May 2009–Revised February 2014 Hardware 33
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Copyright © 2009–2014, Texas Instruments Incorporated
12pF
12pF
GND
100nF
330R
10uF/10V
47K
2.2nF
GND
330R
100nF
GND
GND
GND
green
Ext_PWR
Socket: ENPLAS
Type: OTS-14-065
Vcc
ext
int
to measure supply current
DNP
DNP
DNP
DNP
DNP
JTAG ->
SBW ->
JTAG-Mode selection:
4-wire JTAG: Set jumpers J7 to J12 to position 2-3
2-wire "SpyBiWire": Set jumpers J7 to J12 to position 2-1
1
3
5
7
9
11
13
2
4
6
12
14
8
10
JTAG
C2
C1
C5
R3
C7
R5
C8
1
2
3
J3
Q1
8
9
10
11
12
13
14
J2
1
2
3
4
5
6
7
J1
1
2
J4
1
2
J6
J5
1
2
3
R2
C3
J7
1
2
3
J8
1
2
3
J9
1
2
3
J10
1
2
3
J11
1
2
3
J12
1
2
3
1
2
3
4
5
6
7 8
9
10
14
13
12
11
D1
P1.0
P1.3
P1.2
P1.1 XOUT XOUT
GND
XIN
XIN
VCC
RST/SBWTDIO
RST/SBWTDIO
SBWTCK
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
VCC430
P1.4/TCK
P1.4/TCK
P1.5/TMS
P1.5/TMS
P1.6/TDI
P1.6/TDI
P1.7/TDO
P1.7/TDO
TDO/SBWTDIO
RST/NMI
TMS
TDI
Date: 7/16/2007 8:22:36 AM Sheet: 1/1
REV:
TITLE:
Document Number:
MSP-TS430PW14
+
2.0
MSP-TS430PW14 Target Socket Board
MSP-TS430PW14 www.ti.com
B.2 MSP-TS430PW14
Figure B-3. MSP-TS430PW14 Target Socket Module, Schematic
34 Hardware SLAU278Q–May 2009–Revised February 2014
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Jumper J4
Open to disconnect LED
Orient Pin 1 of
MSP430 device
Jumper J6
Open to measure current
Connector J3
External power connector
Jumper J5 to 'ext'
LED connected to P1.0
Jumpers J7 to J12
Close 1-2 to debug in
Spy-Bi-Wire Mode.
Close 2-3 to debug in
4-wire JTAG mode.
www.ti.com MSP-TS430PW14
Figure B-4. MSP-TS430PW14 Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 35
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MSP-TS430PW14 www.ti.com
Table B-2. MSP-TS430PW14 Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C7 1 10uF, 10V, Tantal Size 511-1463-2-ND B
3 C3, C5 1 100nF, SMD0805 478-3351-2-ND DNP: C3
4 C8 0 2.2nF, SMD0805 DNP
5 D1 1 green LED, SMD0603 475-1056-2-ND
DNP: Headers and receptacles
enclosed with kit. Keep vias free of
6 J1, J2 0 7-pin header, TH solder
SAM1029-07-ND : Header
SAM1213-07-ND : Receptacle
J3, J5, J7, Place jumpers on headers J5, J7, J8, 7 J8, J9, J10, 8 3-pin header, male, TH SAM1035-03-ND J9, J10, J11, J12; Pos 1-2 J11, J12
8 J4, J6 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
9 9 Jumper 15-38-1024-ND Place on: J5, J7-J12; Pos 1-2
10 JTAG 1 14-pin connector, male, HRP14H-ND TH
Micro Crystal MS1V-T1K
12 Q1 0 Crystal 32.768kHz, C(Load) = DNP: keep vias free of solder
12.5pF
13 R2, R3 2 330 Ω, SMD0805 541-330ATR-ND
15 R5 1 47k Ω, SMD0805 541-47000ATR-ND
16 U1 1 Socket: OTS-14-0.65-01 Manuf.: Enplas
17 PCB 1 56 x 53 mm 2 layers
Adhesive Approximately 6mm For example, 3M 18 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302
19 MSP430 2 MSP430F2013IPW DNP: enclosed with kit, supplied by TI
36 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430L092
B.3 MSP-TS430L092
Figure B-5. MSP-TS430L092 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 37
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MSP-TS430L092 www.ti.com
Settings of the MSP-TS430L092 Target Socket
Figure B-6 shows the PCB layout of the MSP-TS430L092 target socket. The following pinning is
recommended:
• JP1 is write enable for the EPROM. If this is not set, the EPROM can only be read.
• JP2 and JP3 connect device supply with boost converter. They can be opened to measure device
current consumption. For default operation, they should be closed.
Figure B-6. MSP-TS430L092 Target Socket Module, PCB
38 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430L092
Table B-3. MSP-TS430L092 Bill of Materials
Pos. Ref Des No. No. Per Description DigiKey Part No. Comment Board
1 C1, C2 2 330nF, SMD0603
2 C5 1 100n, SMD0603
3 C6 1 10u, SMD0805
4 C10 1 100n, SMD0603
5 EEPROM1 1 M95512 SO08 (SO8) ST Micro M95160R Digikey: 497-8688-1-ND
DNP: headers and
receptacles enclosed with kit.
7 J1, J2 2 7-pin header, TH Keep vias free of solder.
SAM1213-07-ND : Header
SAM1035-07-ND : Receptacle
8 J3 1 3-pin header, male, TH SAM1035-03-ND
9 J4, J5 2 FE4L, FE4H 4 pol. Stiftreihe DNP; Keep vias free of solder.
11 J13 1 MICRO_STECKV_10 Reichelt: MicroMaTch- Connector: MM FL 10G
12 JP1, JP2,JP3 3 2-pin header, male, TH SAM1035-02-ND place jumper on header
15 L1 1 33uH, SMD0806 LQH2MCN330K02L Farnell: 151-5557
16 LED1, LED4 2 LEDCHIPLED_0603 Farnell: 1686065
17 Q2 1 BC817-16LT1SMD BC817-16LT1SMD SOT23-BEC
18 R0, R6, R7 3 2K7, SMD0603
19 R1 1 1k, SMD0603
20 R2 1 47k, SMD0603
21 R4,R5, R8, 6 10k, SMD0603 R10, RC, RD
22 RA 1 3.9k, SMD0603
23 RB 1 6.8k, SMD0603
24 U1 1 14 Pin Socket - IC189-0142- Manuf. Yamaichi 146
22 MSP430 2 MSP430L092PWR DNP: Enclosed with kit. Is supplied by TI.
SLAU278Q–May 2009–Revised February 2014 Hardware 39
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MSP-TS430L092 Active Cable www.ti.com
B.4 MSP-TS430L092 Active Cable
Figure B-7. MSP-TS430L092 Active Cable Target Socket Module, Schematic
40 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430L092 Active Cable
Figure B-8 shows the PCB layout for the Active Cable. The following pinning is possible:
• JP1 has two jumpers (Jumper 1 and Jumper 2) that can be set as shown in Table B-4.
Table B-4. MSP-TS430L092 JP1 Settings
Jumper 1 Jumper 2 Description
Off Off The active cable has no power and does not function.
Off On The active cable receives power from target socket. For this option, the target socket must have its own power supply.
On Off The active cable receives power from the JTAG connector.
The JTAG connector powers the active cable and the target socket. For
On On this option, the target socket must not have its own power source, as this
would cause a not defined state.
• JP2 is for reset. For the standard MSP-TS430L092, this jumper must be set. It sets the reset pin to
high and can also control it. Without this jumper on the MSP-TS430L092, reset is set to zero.
Figure B-8. MSP-TS430L092 Active Cable Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 41
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MSP-TS430L092 Active Cable www.ti.com
Table B-5. MSP-TS430L092 Active Cable Bill of Materials
Pos. Ref Des No. Per Description DigiKey Part No. Comment Board
1 C1, C3, C5, 4 100nF, SMD0603 C6
2 C2, C4 2 1uF, SMD0805
3 R1, R10 2 10K, SMD0603
4 R2 1 4K7, SMD0603
5 R5, R6, R7, 4 100, SMD0603 R9
6 R8 1 680k, SMD0603
7 R11, R15 2 1K, SMD0603
8 R12 0 SMD0603 DNP
9 R13 0 SMD0603 DNP
10 R14 1 0, SMD0603
11 IC1 1 SN74AUC1G04DBVR Manu: TI
12 IC2, IC3, IC4 3 SN74AUC2G125DCTR Manu: TI
13 J2 1 MICRO_STECKV_10 Reichelt: MicroMaTch- Connector: MM FL 10G
14 JP1 1 2x2 Header JP2Q Put jumper on Position 1 and 2. Do not mix direction.
15 JP2 1 2-pin header, male, TH SAM1035-02-ND place jumper on header
16 JTAG 1 14-pin connector, male, TH HRP14H-ND
17 Q1 1 BC817-25LT1SMD, SOT23- Digi-Key: BC817- BEC 25LT1GOSCT-ND
18 U1, U2 2 TLVH431IDBVR SOT23-5 Manu: TI
42 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430PW24
B.5 MSP-TS430PW24
Figure B-9. MSP-TS430PW24 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 43
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Jumper JP2
Open to measure current
Orient Pin 1 of MSP430 device
D1 LED connected to P1.0
Jumper JP3
Open to disconnect LED
Connector J5
External power connector
Jumper JP1 to "ext"
Jumpers JP4 to JP9
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
MSP-TS430PW24 www.ti.com
Figure B-10. MSP-TS430PW24 Target Socket Module, PCB
44 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430PW24
Table B-6. MSP-TS430PW24 Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C5 1 2.2nF, SMD0805
3 C3, C7 2 10uF, 10V, SMD0805
4 C4, C6, C8 3 100nF, SMD0805 478-3351-2-ND
5 D1 1 green LED, SMD0805 P516TR-ND
"SAM1029-07- DNP: Headers and receptacles 6 J1, J2 0 12-pin header, TH NDSAM1213-07-ND" enclosed with kit. Keep vias free of solder. (Header & Receptacle)
J5, JP1,
7 JP4, JP5, 8 3-pin header, male, TH SAM1035-03-ND Place jumper on 1-2 of JP4-JP9 JP6, JP7, Place on 1-2 on JP1
JP8, JP9
8 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
9 9 Jumper 15-38-1024-ND see Pos 7 an 8
10 JTAG 1 14-pin connector, male, HRP14H-ND TH
11 Q1 0 Crystal DNP: keep vias free of solder
12 R1, R7 2 330 Ω, SMD0805 541-330ATR-ND
13 R5, R6, 2 0 Ohm, SMD0805 541-000ATR-ND DNP R5, R6 R8, R9,
14 R4 1 47k Ohm, SMD0805 541-47000ATR-ND
15 U1 1 Socket: OTS 24(28)- Manuf.: Enplas 065-02-00
16 PCB 1 68.5 x 61 mm 2 layers
Adhesive Approximately 6mm for example, 3M 17 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302
18 MSP430 2 MSP430AFE2xx DNP: enclosed with kit, supplied by TI
SLAU278Q–May 2009–Revised February 2014 Hardware 45
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ML14
LED3
12pF
12pF
GND
GND
100nF
560R
ML10
JP1Q
JP1Q
10uF/10V
50K
10nF
0R
0R
0R -
-
0R
-
U1
SOCK28DW
F123
FE14H FE14L
0R
GND
remove R8 and add R9 (0 Ohm)
If external supply voltage:
remove R11 and add R10 (0 Ohm) SMD-Footprint
Socket: Yamaichi
2.0
MSP-TS430DW28 Target Socket DW28
Type: IC189-0282-042
If external supply voltage:
R1, C1, C2
not assembled
not assembled
1
3
5
7
9
11
13
2
4
6
12
14
8
10
JTAG
D1
C2
C1
C5
R3
BOOTST
1 2
3 4
5 6
7 8
9 10
1 2
J5
J4
1 2
C7
R5
C8
R6
R7
R8 R9
R10
R11
R1
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
TST 1
VCC 2
P2.5 3
VSS 4
XOUT 5
XIN 6
RST 7
P2.0 8
P2.1 9
P2.2 10 P2.3 19
P2.4 20
P1.0 21
P1.1 22
P1.2 23
P1.3 24
P1.4 25
P1.5 26
P1.6 27
P1.7 28
P3.0 11
P3.1 12
P3.2 13
P3.3 14 P3.4 15
P3.5 16
P3.6 17
P3.7 18
U2
15
16
17
18
19
20
21
22
23
24
25
26
27
28
J2 J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R2
1
2
3
J3
Q1
QUARZ3
P1.0
P1.0
P1.3
P1.3
P1.2
P1.2
P1.1
P1.1 RST/NMI
RST/NMI
RST/NMI
RST/NMI RST/NMI
TCK
TCK
TCK
TMS
TMS
TMS
TDI
TDI
TDI
TDO
TDO
TDO
XOUT
XOUT
VCC
GND
GND
GND
P2.3
P2.3
P2.4
P2.4
XIN
XIN
P2.5
P2.5
P2.2
P2.2
P2.1
P2.1
P2.0
P2.0
TST/VPP
TST/VPP
TST/VPP
P3.0
P3.0
P3.1
P3.1
P3.2
P3.2
P3.3
P3.3
P3.7
P3.7
P3.6
P3.6
P3.5
P3.5
P3.4
P3.4
VCC430
Ext_PWR
Date: 11/14/2006 1:26:04 PM Sheet: 1/1
REV:
TITLE:
Document Number:
MSP-TS430DW28
+
VCC430
MSP-TS430DW28 www.ti.com
B.6 MSP-TS430DW28
Figure B-11. MSP-TS430DW28 Target Socket Module, Schematic
46 Hardware SLAU278Q–May 2009–Revised February 2014
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Jumper J4
Open to disconnect LED
Orient Pin 1 of
MSP430 device
Jumper J5
Open to measure current
Connector J3
External power connector
Remove R8 and jumper R9
LED connected to P1.0
www.ti.com MSP-TS430DW28
Figure B-12. MSP-TS430DW28 Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 47
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Copyright © 2009–2014, Texas Instruments Incorporated
MSP-TS430DW28 www.ti.com
Table B-7. MSP-TS430DW28 Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2, Cover holes while soldering
2 C5 1 100nF, SMD0805
3 C7 1 10uF, 10V Tantal Elko B
4 C8 1 10nF SMD0805
5 D1 1 LED3 T1 3mm yellow RS: 228-4991
Micro Crystal MS1V-T1K
6 Q1 0 QUARZ, Crystal 32.768kHz, C(Load) = DNP: Cover holes while soldering
12.5pF
DNP: Headers and receptacles
enclosed with kit. Keep vias free of
7 J1, J2 2 14-pin header, TH male solder.
: Header
: Receptacle
DNP: Headers and receptacles
enclosed with kit. Keep vias free of
7.1 2 14-pin header, TH solder. female : Header
: Receptacle
8 J3 1 3-Pin Connector, male
9 J4, J5 2 2-Pin Connector, male With jumper
10 BOOTST 0 ML10, 10-Pin Conn., m RS: 482-115 DNP, Cover holes while soldering
11 JTAG 1 ML14, 14-Pin Conn., m RS: 482-121
R1, R2,
12 R6, R7, 4 0R, SMD0805 DNP: R1, R2, R9, R10 R8,R9,
R10, R11
13 R3 1 560R, SMD0805
14 R5 1 47K, SMD0805
15 U1 1 SOP28DW socket Yamaichi: IC189-0282- 042
16 U2 0 TSSOP DNP
48 Hardware SLAU278Q–May 2009–Revised February 2014
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12pF
12pF
GND
GND
100nF
330R
10uF/10V
-
0R
GND
GND
green
2.2nF
47k
GND
0R 0R
330R
MSP430F12xx
If external supply voltage:
remove R11 and add R10 (0 Ohm)
3.1
MSP-TS430PW28:
OTS-28-0.65-01
Socket: Enplas
Vcc
int
ext
Target Socket Board for MSP430's in PW28 package
DNP
DNP
DNP
DNP
DNP
DNP
DNP
JTAG ->
SBW ->
JTAG-Mode selection:
4-wire JTAG: Set jumpers JP4 to JP9 to position 2-3
2-wire "SpyBiWire": Set jumpers JP4 to JP9 to position 1-2
DNP
1
3
5
7
9
11
13
2
4
6
12
14
8
10
JTAG
C2
C1
C4
R1
1 2
3 4
5 6
7 8
9 10
BOOTST
C3
R2
R3
1
2
3
J5
JP1
1
2
3
JP2
1
2
1
2
JP3
D1
C5 R4
JP4
1
2
3
JP5
1
2
3
JP6
1
2
3
JP7
1
2
3
JP8
1
2
3
JP9
1
2
3
R5 R6
1 2
Q1
R7
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U1
TST 1
VCC 2
P2.5 3
VSS 4
XOUT 5
XIN 6
RST 7
P2.0 8
P2.1 9
P2.2 10 P2.3 19
P2.4 20
P1.0 21
P1.1 22
P1.2 23
P1.3 24
P1.4 25
P1.5 26
P1.6 27
P1.7 28
P3.0 11
P3.1 12
P3.2 13
P3.3 14 P3.4 15
P3.5 16
P3.6 17
P3.7 18
P1.0
P1.0
RST/NMI
TMS
TDI
VCC
GND
GND
VCC430 VCC430
P2.0
P1.1
P1.1
P3.3
P3.2
P3.1
P3.0
P2.2
P2.2
XIN/P2.6
XIN/P2.6
XOUT/P2.7
XOUT/P2.7
P2.1
RST/SBWTDIO
RST/SBWTDIO
RST/SBWTDIO
P3.4
P3.5
P3.6
P3.7
P2.3
P2.4
P1.2
P1.3
P1.4/TCK
P1.4/TCK
P1.5/TMS
P1.5/TMS
P1.6/TDI
P1.6/TDI
P1.7/TDO
P1.7/TDO
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
P2.5
TCK/SBWTCK
TDO/SBWTDIO
XTLGND
Ext_PWR
+
www.ti.com MSP-TS430PW28
B.7 MSP-TS430PW28
Figure B-13. MSP-TS430PW28 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 49
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Jumper JP2
Open to measure current
Jumper JP3
Open to disconnect LED
LED D1 connected to P5.1
Jumper JP1
1-2 (int): Power supply via JTAG interface
2-3 (ext): External Power Supply
Jumper JP4 to JP9:
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
Orient Pin 1 of Device
MSP-TS430PW28 www.ti.com
Figure B-14. MSP-TS430PW28 Target Socket Module, PCB
50 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430PW28
Table B-8. MSP-TS430PW28 Bill of Materials(1)
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 , Cover holes while soldering
2 C3 1 10uF, 10V Tantal Elko B
3 C4 1 100nF, SMD0805
4 C5 0 2.2nF, SMD0805 DNP
5 D1 1 LED green SMD0603
Micro Crystal MS1V-T1K DNP: Cover holes and
6 Q1 0 QUARZ, Crystal 32.768kHz, C(Load) = neighboring holes while
12.5pF soldering
DNP: Headers and
receptacles enclosed with
7 J1, J2 2 14-pin header, TH male kit.Keep vias free of solder.
: Header
: Receptacle
DNP: headers and
receptacles enclosed with
7.1 2 14-pin header, TH female kit.Keep vias free of solder.
: Header
: Receptacle
8 J5, IP1 1 3-Pin Connector , male
JP1, JP4,
8a JP5, JP6, 7 3-Pin Connector , male Jumper on Pos 1-2 JP7, JP8,
JP9
9 JP2, JP3 2 2-Pin Connector , male with Jumper
10 BOOTST 0 ML10, 10-Pin Conn. , m RS: 482-115 DNP: Cover holes while soldering
11 JTAG 1 ML14, 14-Pin Conn. , m RS: 482-121
12 R1, R7 2 330R, SMD0805
12 R2, R3, R5, 0 0R, SMD0805 DNP R6
14 R4 1 47K, SMD0805
15 U1 1 SOP28PW socket Enplas: OTS-28-0.65-01
(1) PCB 66 x 79 mm, two layers; Rubber stand off, four pieces
SLAU278Q–May 2009–Revised February 2014 Hardware 51
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JTAG Mode selection:
4-wire JTAG: Set jumpers J4 to J9 to position 2-3
2-wire "SpyBiWire": Set jumpers J4 to J9 to position 2-1
MSP-TS430PW28A www.ti.com
B.8 MSP-TS430PW28A
Figure B-15. MSP-TS430PW28A Target Socket Module, Schematic
52 Hardware SLAU278Q–May 2009–Revised February 2014
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Jumper JP2
Open to measure current
Orient Pin 1 of MSP430 device
Jumper JP3
Open to disconnect LED
D1 LED connected to P1.0
Connector J5
External power connector
Jumper JP1 to "ext"
Jumpers JP4 to JP9
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
www.ti.com MSP-TS430PW28A
Figure B-16. MSP-TS430PW28A Target Socket Module, PCB (Red)
SLAU278Q–May 2009–Revised February 2014 Hardware 53
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MSP-TS430PW28A www.ti.com
Table B-9. MSP-TS430PW28A Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C5 1 2.2nF, SMD0805
3 C3 1 10uF, 10V, SMD0805
4 C4, C6, 2 100nF, SMD0805 478-3351-2-ND
5 D1 1 green LED, SMD0805 P516TR-ND
DNP: Headers and receptacles
6 J1, J2 0 14-pin header, TH enclosed with kit. Keep vias free of
solder: (Header & Receptacle)
J5, JP1,
7 JP4, JP5, 8 3-pin header, male, TH SAM1035-03-ND Place jumper on 1-2 of JP4-JP9 JP6, JP7, Place on 1-2 on JP1
JP8, JP9
8 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
9 9 Jumper 15-38-1024-ND see Pos 7 an 8
10 JTAG 1 14-pin connector, male, HRP14H-ND TH
11 BOOTST 0 DNP Keep vias free of solder
Micro Crystal MS3V
12 Q1 0 Crystal 32.768kHz, C(Load) = DNP: keep vias free of solder
12.5pF
13 R1, R7 2 330 Ω, SMD0805 541-330ATR-ND
14 R2, R3,R5, 0 0 Ohm, SMD0805 541-000ATR-ND DNP R2, R3,R5, R6 R6,
15 R4 1 47k Ω, SMD0805 541-47000ATR-ND
16 U1 1 Socket: OTS-28-0.65-01 Manuf.: Enplas
17 PCB 1 63.5 x 64.8 mm 2 layers
Adhesive Approximately 6mm for example, 3M 18 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302
19 MSP430 2 MSP430G2553IPW28 DNP: enclosed with kit, supplied by TI
54 Hardware SLAU278Q–May 2009–Revised February 2014
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12pF
12pF
GND
GND
100nF
560R
10uF/10V
47k
10nF
-
0R
GND
MSP430F2274IDA
GND
330R
GND
yellow
If external supply voltage:
remove R11 and add R10 (0 Ohm)
IC189-0382-037
Socket:
4-wire JTAG:
2-wire "SpyBiWire":
JTAG-Mode selection:
Set jumpers JP4 to JP9 to position 2-3
Set jumpers JP4 to JP9 to position 2-1
JTAG ->
SBW ->
Yamaichi
DNP
DNP
DNP
DNP
DNP
DNP
DNP
1
3
5
7
9
11
13
2
4
6
12
14
8
10
JTAG
C2
C1
C5
R3
1 2
3 4
5 6
7 8
9 10
BOOTST
C7
R5
C8
R10
R11
1
2
3
J3
Q1
TEST/SBWTCK 1
P3.5 26
P3.6 27
P1.4/TCK 35
RST/SBWDAT 7
DVCC 2
DVSS 4
P4.7 24
P3.7 28
AVSS 15
AVCC 16
P3.0 11
P3.1 12
P3.2 13
P3.3 14
P4.0 17
P4.1 18
P4.2 19
P3.4 25
P2.5 3
P2.4 30
P2.3 29 P2.2 10
P2.1 9
P2.0 8
P1.5/TMS 36
P1.6/TDI 37
P1.7/TDO 38
P2.7 5
P2.6 6
P4.6 23
P4.5 22
P4.4 21
P4.3 20
P1.0 31
P1.1 32
P1.2 33
P1.3 34
U1
JP1
1
2
3
JP2
1
2
1
2
JP3
1
2
3
JP4 JP5
1
2
3
JP6
1
2
3
JP7
1
2
3
JP8
1
2
3
R1
JP9
1
2
3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
J1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
20
J2
D1
P1.0
P1.0
RST/NMI
TMS
TDI
VCC
GND
GND
GND
VCC430
VCC430
VCC430
TCK/SBWTCK
TDO/SBWTDIO
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
P2.5
P2.0
P2.1
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P1.7/TDO
P1.7/TDO
P1.6/TDI
P1.6/TDI
P1.5/TMS
P1.5/TMS
P1.4/TCK
P1.4/TCK
P1.3
P1.2
P1.1
P1.1
P2.4
P2.3
P3.7
P3.6
P3.5
P3.4
P4.7
P4.6
P4.5
P4.4
P4.3
P2.7/XOUT
P2.7/XOUT
P2.6/XIN
P2.6/XIN
RST/SBWTDIO
RST/SBWTDIO
RST/SBWTDIO
P2.2
P2.2
Ext_PWR
Date: 6/18/2008 11:04:56 AM Sheet: 1/1
REV:
TITLE:
Document Number:
MSP-TS430DA38
+
1.3
MSP-TS430DA38:
Vcc
int
ext
Target Socket Board for MSP430F2247IDA
www.ti.com MSP-TS430DA38
B.9 MSP-TS430DA38
Figure B-17. MSP-TS430DA38 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 55
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Orient pin 1 of
MSP430 device
LED connected to P1.0
Connector J3
External power connector
Jumper JP1 to 'ext'
Jumper JP3
Open to disconnect LED
Jumper JP2
Open to measure current
Jumpers JP4 to JP9
Close 1-2 to debug in
Spy-Bi-Wire Mode,
Close 2-3 to debug in
4-wire JTAG Mode
MSP-TS430DA38 www.ti.com
Figure B-18. MSP-TS430DA38 Target Socket Module, PCB
56 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430DA38
Table B-10. MSP-TS430DA38 Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C7 1 10uF, 10V, Tantal Size B 511-1463-2-ND
3 C5 1 100nF, SMD0805 478-3351-2-ND
4 C8 0 2.2nF, SMD0805 DNP
5 D1 1 green LED, SMD0603 475-1056-2-ND
DNP: headers and
receptacles enclosed with
6 J1, J2 0 19-pin header, TH kit.Keep vias free of solder.
SAM1029-19-ND : Header
SAM1213-19-ND : Receptacle
"J3, JP1, Place jumpers on headers 7 JP4, JP5, 8 3-pin header, male, TH SAM1035-03-ND JP1, JP4,JP5, JP6, JP7, JP6, JP7, JP8, JP9; Pos 1-2 JP8, JP9"
8 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
9 9 Jumper 15-38-1024-ND Place on: JP1 - JP9; Pos 1- 2
10 JTAG 1 14-pin connector, male, TH HRP14H-ND
11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
13 R1, R3 2 330 Ω, SMD0805 541-330ATR-ND
14 R10, R11 0 0 Ω, SMD0805 541-000ATR-ND DNP
15 R5 1 47k Ω, SMD0805 541-47000ATR-ND
16 U1 1 Socket: IC189-0382--037 Manuf.: Yamaichi
17 PCB 1 67 x 66 mm 2 layers
18 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side
19 MSP430 2 MSP430F2274IDA DNP: enclosed with kit supplied by TI
SLAU278Q–May 2009–Revised February 2014 Hardware 57
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MSP-TS430QFN23x0 www.ti.com
B.10 MSP-TS430QFN23x0
Figure B-19. MSP-TS430QFN23x0 Target Socket Module, Schematic
58 Hardware SLAU278Q–May 2009–Revised February 2014
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Copyright © 2009–2014, Texas Instruments Incorporated
LED connected
to P1.0
Connector J5
External power connector
Jumper JP1 to 'ext'
Jumper JP3
Open to disconnect LED
Jumper JP2
Open to measure current
www.ti.com MSP-TS430QFN23x0
Figure B-20. MSP-TS430QFN23x0 Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 59
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Copyright © 2009–2014, Texas Instruments Incorporated
MSP-TS430QFN23x0 www.ti.com
Table B-11. MSP-TS430QFN23x0 Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C3 1 10uF, 10V, Tantal Size B 511-1463-2-ND
3 C4 1 100nF, SMD0805 478-3351-2-ND
4 C5 1 10nF, SMD0805 478-1383-2-ND
5 D1 1 green LED, SMD0603 475-1056-2-ND
DNP: headers and
receptacles enclosed with
6 J1, J2, J3, 0 10-pin header, TH kit.Keep vias free of solder. J4 SAM1034-10-ND : Header
SAM1212-10-ND : Receptacle
7 J5, JP1 2 3-pin header, male, TH SAM1035-03-ND Place jumper on header JP1; Pos 1-2.
8 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
9 3 Jumper 15-38-1024-ND Place on: JP1, JP2, JP3
10 JTAG 1 14-pin connector, male, TH HRP14H-ND
11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
13 R1 1 330 Ω, SMD0805 541-330ATR-ND
14 R2, R3 0 0 Ω, SMD0805 541-000ATR-ND DNP
15 R4 1 47k Ω, SMD0805 541-47000ATR-ND
16 U1 1 Socket: QFN-40B-0.5-01 Manuf.: Enplas
17 PCB 1 79 x 66 mm 2 layers
18 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side
19 MSP430 2 MSP430F2370IRHA DNP: enclosed with kit supplied by TI
60 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430RSB40
B.11 MSP-TS430RSB40
Figure B-21. MSP-TS430RSB40 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 61
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Copyright © 2009–2014, Texas Instruments Incorporated
Jumper JP2
Open to measure current
Orient Pin 1 of MSP430 device
Jumper JP3
Open to disconnect LED
D1 LED connected to P1.0
Jumpers JP4 to JP9
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
Connector J5
External power connector
Jumper JP1 to "ext"
MSP-TS430RSB40 www.ti.com
Figure B-22. MSP-TS430RSB40 Target Socket Module, PCB
62 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430RSB40
Table B-12. MSP-TS430RSB40 Bill of Materials
Pos. Ref Des No. Per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2
2 C3, C7, C10, 3 10uF, 10V, SMD 0805 445-1371-1-ND DNP C12 C12
3 C4, C6, C8, 3 100nF, SMD0805 311-1245-2-ND DNP C11 C11
4 C5 1 2.2nF, SMD0805
5 C9 1 470nF, SMD0805
6 D1 1 green LED, SMD0805 P516TR-ND
DNP: headers and
receptacles enclosed with kit.
7 J1, J2, J3, J4 4 10-pin header, TH Keep vias free of solder.
: Header
: Receptacle
DNP: headers and
receptacles enclosed with kit.
7.1 4 10-pin header, TH Keep vias free of solder.
: Header
: Receptacle
JP1,
JP4,JP5, Jumper: 1-2 on JP1, JP10; 2- 8 JP6, JP7, 9 3-pin header, male, TH SAM1035-03-ND 3 on JP4-JP9 JP8, JP9, J5,
JP10
9 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND place jumper on header
10 JTAG 1 14-pin connector, male, TH HRP14H-ND
11 BOOTST 0 10-pin connector, male, TH DNP. Keep vias free of solder
12 U1 1 QFN-40B-0.4_ Enplas ENPLAS_SOCKET
Micro Crystal MS3V-T1R DNP: Q1. Keep vias free of 13 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
Place on: JP1, JP2, JP3,
15 10 Jumper 15-38-1024-ND JP4, JP5, JP6, JP7, JP8,
JP9, JP10
16 R1,R7 2 330R SMD0805
R2, R3, R5,
17 R6, R8, R9, 3 0R SMD0805 DNP R2, R3, R5, R6
R10
18 R4 1 47k SMD0805
19 MSP430 2 MSP430F5132 DNP: enclosed with kit. Is supplied by TI
20 Rubber stand 4 select appropriate; for apply to corners at bottom off example, Buerklin: 20H1724 side
SLAU278Q–May 2009–Revised February 2014 Hardware 63
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MSP-TS430RHA40A www.ti.com
B.12 MSP-TS430RHA40A
Figure B-23. MSP-TS430RHA40A Target Socket Module, Schematic
64 Hardware SLAU278Q–May 2009–Revised February 2014
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Jumper JP2
Open to measure current
Connector J5
External power connector
Jumper JP1 to "ext"
Jumpers JP4 to JP9
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
D1 LED connected to P1.0
Jumper JP3
Open to disconnect LED
Orient Pin 1 of MSP430 device
www.ti.com MSP-TS430RHA40A
Figure B-24. MSP-TS430RHA40A Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 65
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MSP-TS430RHA40A www.ti.com
Table B-13. MSP-TS430RHA40A Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2
2 C5 0 2.2nF, SMD0805 DNP C12
3 C3, C7 2 10uF, 10V, SMD0805 5 DNP C11
4 C4, C6 2 100nF, SMD0805 478-3351-2-ND
5 C9 1 470nF, SMD0805
6 D1 1 green LED, SMD0805 P516TR-ND
DNP: headers and receptacles
enclosed with kit. Keep vias free of
7 J1, J2, J3, 4 10-pin header, TH solder. J4 : Header
: Receptacle
DNP: headers and receptacles
enclosed with kit. Keep vias free of
7.1 4 10-pin header, TH solder.
: Header
: Receptacle
J5, JP1,
8 JP4, JP5, 8 3-pin header, male, TH SAM1035-03-ND Place jumper on 1-2 of JP4-JP9; JP6, JP7, Place on 1-2 on JP1
JP8, JP9
9 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND place jumper on header
10 9 Jumper 15-38-1024-ND see Pos 8 an 9
11 JTAG 1 14-pin connector, male, HRP14H-ND TH
12 BOOTST 0 10-pin connector, male, DNP. Keep vias free of solder TH
13 U1 1 Socket: QFN-40B-0.5-01 Manuf.: Enplas
Micro Crystal MS3V-T1R
14 Q1 0 Crystal 32.768kHz, C(Load) = DNP: Q1. Keep vias free of solder
12.5pF
15 R1,R7 2 330R SMD0805 541-330ATR-ND
R2, R3,
16 R5, R6, 2 0 Ohm, SMD0805 541-000ATR-ND DNP:R2, R3, R5, R6
R8, R9,
17 R4 1 47k SMD0805
18 PCB 1 79 x 66 mm 2 layers
Rubber select appropriate; for 19 stand off 4 example, Buerklin: apply to corners at bottom side 20H1724
20 MSP430 2 MSP430N5736IRHA DNP: enclosed with kit. Is supplied by TI
66 Hardware SLAU278Q–May 2009–Revised February 2014
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ML14
LED3
12pF
12pF
GND
GND
100nF
560R
ML10
JP1Q
JP1Q
10uF/10V
47K
10nF
0R
0R
GND
0R
0R
10uF/10V
GND
IC51-1387.KS-15186
100nF
1.3
MSP-TS430DL48 Target Socket DL48
Q1, C1, C2
not assembled
1
3
5
7
9
11
13
2
4
6
12
14
8
10
JTAG
D1
C2
C1
C5
R3
BOOTST
1 2
3 4
5 6
7 8
9 10
1 2
J5
J4
1 2
C7
R5
C8
R6
R7
1
2
3
J3
Q1
QUARZ3
J2
1
3
5
2
4
6
7
9
8
10
11
13
15
12
14
16
17
19
18
20
21
23
22
24
1
3
5
2
4
6
7
9
8
10
11
13
15
12
14
16
17
19
18
20
21
23
22
24
J1
R12
R4
JP1
1
2
3
1
2
3
JP2
C4
U1
TDO/TDI 1
TDI/TCLK 2
TMS 3
TCK 4
RST/NMI 5
DVCC 6
DVSS 7
XIN 8
XOUT 9
AVSS 10
AVCC 11
VREF+ 12
P6.0 13
P6.1 14
P6.2 15
P6.3 16
P6.4 17
P6.5 18
P6.6 19
P6.7 20
P2.5 39
P2.4 40
P2.3 41
P2.2 42
P2.1 43
P2.0 44
COM0 45
P5.2 46
P5.3 47
P5.4 48
LCDREF 29
LCDCAP 30
P5.1 31
P5.0 32
P5.5 33
P5.6 34
P5.7 35
S5 36
P2.7 37
P2.6 38
P1.7 21
P1.6 22
P1.5 23
P1.4 24
P1.0 28
P1.1 27
P1.2 26
P1.3 25
C3
P1.0
P1.0
RST/NMI
RST/NMI
RST/NMI
TCK
TCK
TCK
TMS
TMS
TDI
TDI
TDO
TDO
XOUT
XOUT
GND
GND GND
XIN
XIN
BSL_TX
VCC
BSL_RX
Ext_PWR
Date: 11/14/2006 1:24:44 PM Sheet: 1/1
REV:
TITLE:
Document Number:
MSP-TS430DL48
+
+
Vcc
ext
int
int ext
Vcc
www.ti.com MSP-TS430DL48
B.13 MSP-TS430DL48
Figure B-25. MSP-TS430DL48 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 67
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Jumper J4
Open to
disconnect LED
LED connected
to P1.0
Orient pin 1 of
MSP430 device
Jumper J5
Open to measure current
Connector J3
External power connector
Jumper JP1 to ‘ext’
MSP-TS430DL48 www.ti.com
Figure B-26. MSP-TS430DL48 Target Socket Module, PCB
68 Hardware SLAU278Q–May 2009–Revised February 2014
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Copyright © 2009–2014, Texas Instruments Incorporated
www.ti.com MSP-TS430DL48
Table B-14. MSP-TS430DL48 Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C4, C7 2 10uF, 10V, Tantal Size B 511-1463-2-ND
3 C3, C5 2 100nF, SMD0805 478-3351-2-ND
4 C8 1 10nF, SMD0805 478-1383-2-ND
5 D1 1 yellow LED, TH, 3mm, T1 511-1251-ND
DNP: Headers and
receptacles enclosed with
6 J1, J2 0 24-pin header, TH kit.Keep vias free of solder.
SAM1034-12-ND : Header
SAM1212-12-ND : Receptacle
7 J3, JP1, JP2 2 3-pin header, male, TH SAM1035-03-ND Place jumper on header JP1; Pos 1-2. DNP: JP2
8 J4, J5 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
9 3 Jumper 15-38-1024-ND Place on: JP1, J4, J5
10 JTAG 1 14-pin connector, male, TH HRP14H-ND
11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
13 R3 1 560 Ω, SMD0805 541-560ATR-ND
14 R4, R6, R7, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R6, R7 R12
15 R5 1 47k Ω, SMD0805 541-47000ATR-ND
16 U1 1 Socket: IC51-1387 KS- Manuf.: Yamaichi 15186
17 PCB 1 58 x 66 mm 2 layers
18 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side
19 MSP430 2 MSP430F4270IDL DNP: Enclosed with kit supplied by TI
SLAU278Q–May 2009–Revised February 2014 Hardware 69
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Copyright © 2009–2014, Texas Instruments Incorporated
MSP-TS430RGZ48B www.ti.com
B.14 MSP-TS430RGZ48B
Figure B-27. MSP-TS430RGZ48B Target Socket Module, Schematic
70 Hardware SLAU278Q–May 2009–Revised February 2014
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Copyright © 2009–2014, Texas Instruments Incorporated
Jumper JP2
Open to disconnect LED
Connector J5
External power connector
Jumper JP1 to "ext"
Jumpers JP5 to JP10
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
D1 LED connected to P1.0
Jumper JP1
Open to measure current
Orient Pin 1 of MSP430 device
www.ti.com MSP-TS430RGZ48B
Figure B-28. MSP-TS430RGZ48B Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 71
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Copyright © 2009–2014, Texas Instruments Incorporated
MSP-TS430RGZ48B www.ti.com
Table B-15. MSP-TS430RGZ48B Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C3, C4 0 47pF, SMD0805 DNP
3 C6, C7, 3 10uF, 6.3V, SMD0805 C12
4 C5, C11, 4 100nF, SMD0805 311-1245-2-ND C13, C14
5 C8 1 2.2nF, SMD0805
6 C9 1 470nF, SMD0805 478-1403-2-ND
7 D1 1 green LED, SMD0805 P516TR-ND
J1, J2, J3, SAM1029-12-ND DNP: Headers and receptacles 8 J4 0 12-pin header, TH (Header) SAM1213-12- enclosed with kit. Keep vias free of ND (Receptacle) solder:
9 J5 1 3-pin header, male, TH
JP3, JP5, place jumpers on pins 2-3 on JP5, 10 JP6, JP7, 7 3-pin header, male, TH SAM1035-03-ND JP6, JP7, JP8, JP9, JP10 place JP8, JP9, jumpers on pins 1-2 on JP3, JP10
11 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
12 9 Jumper 15-38-1024-ND See Pos. 10and Pos. 11
13 JTAG 1 14-pin connector, male, HRP14H-ND TH
14 BOOTST 0 10-pin connector, male, "DNP Keep vias free of solder" TH
Micro Crystal MS3V-T1R
15 Q1 0 Crystal 32.768kHz, C(Load) = DNP: Q1 Keep vias free of solder
12.5pF
16 Q2 0 Crystal Q2: 4MHz Buerklin: DNP: Q2 Keep vias free of solder 78D134
Insulating http://www.ettinger.de/Ar 17 disk to Q2 0 Insulating disk to Q2 t_Detail.cfm?ART_ART NUM=70.08.121
18 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2,
R4, R6,
19 R8, 3 0 Ohm, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11,R12
R9,R10,
R11, R12
20 R5 1 47k Ω, SMD0805 541-47000ATR-ND
21 U1 1 Socket: QFN11T048- Manuf.: Yamaichi 008_A101121_RGZ48
22 PCB 1 81 x 76 mm 2 layers
Adhesive Approximately 6mm for example, 3M 23 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302
24 MSP430 2 MSP430F5342IRGZ DNP: enclosed with kit, supplied by TI
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DNP
DNP
DNP
GND
GND
100nF
330R
0R -
GND
GND
47k 1.1nF
GND
0R 0R
0R
1uF/10V QUARZ5
1uF/10V 100nF
green
DNP
yellow (DNP)
DNP
red (DNP)
0R
GND
DNP
DNP
0R 0R
QUARZ5
EVQ11
0R
DNP
DNP
If external supply voltage:
remove R3 and add R2 (0 Ohm)
1.3
Ext_PWR
MSP-TS430RGZ48C
Vcc
int
ext
Target Socket Board for MSP430FR58xx, FR59xx IRGZ
DNP
DNP
DNP
DNP
DNP
JTAG ->
SBW ->
JTAG-Mode selection:
4-wire JTAG: Set jumpers JP3 to JP8 to position 2-3
2-wire "SpyBiWire": Set jumpers JP3 to JP8 to position 1-2
connection by via
DNP
DNP
1
3
5
7
9
11
13
2
4
6
12
14
8
10
JTAG
C2
C1
C4
R1
1 2
3 4
5 6
7 8
9 10
BOOTST
R3 R2
1
2
3
J2
J1
1
2
3
JP1
1
2
1
2
JP9
R4 C5
1
2
3
JP3
1
2
3
JP4
1
2
3
JP5
1
2
3
JP6
1
2
3
JP7
1
2
3
JP8
R5 R6
R7
C3 Q1
C7 C6
D1
R10
1
2
JP10
D2
R11
1
2
JP11
D3
R12
JP2
1
2
C8
C9
R9 R8
Q2
SV4
1
2
3
4
5
6
7
8
9
10
11
12
SV1
1
2
3
4
5
6
7
8
9
10
11
12
SV2
1
2
3
4
5
6
7
8
9
10
11
12
SV3
1
2
3
4
5
6
7
8
9
10
11
12
1 1_P1.0
2 2_P1.1
3 3_P1.2
4 4_P3.0
5 5_P3.1
6 6_P3.2
7 7_P3.3
8 8_P4.7
9 9_P1.3
10 10_P1.4
11 11_P1.5
12 12_PJ.0_TDO
13 13_PJ.1_TDI
14 14_PJ.2_TMS
15 15_PJ.3/TCK
16 16_P4.0
17 17_P4.1
18 18_P4.2
19 19_P4.3
20 20_P2.5
21 21_P2.6
22 22_TEST/SBWTCK
23 23_RST/SBWTDIO
24 24_P2.0
25_P2.1 25
26_P2.2 26
27_P3.4 27
28_P3.5 28
29_P3.6 29
30_P3.7 30
31_P1.6 31
32_P1.7 32
33_P4.4 33
34_P4.5 34
35_P4.6 35
36_DVSS 36
37_DVCC 37
38_P2.7 38
39_P2.3 39
40_P2.4 40
41_AVSS 41
42_HFXIN 42
43_HFXOUT 43
44_AVSS 44
45_LFXIN 45
46_LFXOUT 46
47_AVSS 47
48_AVCC 48
U1
SW1
R13
TP1TP2
SW2
R14
P1.0
P1.0
RST/NMI
TMS
TDI
VCC
GND
P1.1
P1.1
RST/SBWTDIO
RST/SBWTDIO
RST/SBWTDIO
TCK/SBWTCK
TDO/SBWTDIO
PJ.0/TDO
PJ.0/TDO
PJ.2/TMS
PJ.2/TMS
PJ.3/TCK
PJ.3/TCK
PJ.1/TDI
PJ.1/TDI
P1.2
P1.2
P2.0
P2.0
P2.1
P2.1
P1.3
P1.3
P1.4
P1.5
AVCC
AVCC
AVSS
AVSS
AVSS
AVSS
LFXOUT
LFXIN
LFGND HFGND
HFXOUT
HFXIN
P2.4
P2.3
P2.7
DVCC DVCC
DVCC
DVCC
DVSS
DVSS
P4.6
P4.5
P4.4
P1.7
P1.6
P3.7
P3.6
P3.5
P3.4
P2.2
P2.6
P2.5
P4.3
P4.2
P4.1
P4.0
P4.7
P3.3
P3.2
P3.1
P3.0
TEST/SBWTCK1
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
www.ti.com MSP-TS430RGZ48C
B.15 MSP-TS430RGZ48C
Figure B-29. MSP-TS430RGZ48C Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 73
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MSP-TS430RGZ48C www.ti.com
Figure B-30. MSP-TS430RGZ48C Target Socket Module, PCB
Table B-16. MSP-TS430RGZ48C Revision History
Revision Comments
1.2 Initial release
LFOSC pins swapped at SV1 (9-10).
1.3 HFOSC pins swapped at SV1 (6-7).
BOOTST pin 4 now directly connected to the device RST/SBWTDIO pin.
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www.ti.com MSP-TS430RGZ48C
Table B-17. MSP-TS430RGZ48C Bill of Materials
Number
Pos Ref Des Per Description DigiKey Part Number Comment
Board
1 SV1, SV2, SV3, 4 12-pin header, TH DNP: headers and receptacles enclosed with kit.
SV4 Keep vias free of solder.
SAM1029-12-ND : Header
: Receptacle
1.1 SV1, SV2, SV3, 4 12-pin receptable, TH DNP: headers and receptacles enclosed with kit.
SV4 Keep vias free of solder.
: Header
SAM1213-12-ND : Receptacle
2 JP1, JP2, JP9 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header
3 JP10, JP11 2 2-pin header, male, TH SAM1035-02-ND DNP
4 J1, JP3, JP4, JP5, 7 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 2-3
JP6, JP7, JP8
5 J2 1 3-pin header, male, TH SAM1035-03-ND
6 JP1, JP2, JP9, J1, 10 Jumper 15-38-1024-ND Place on: JP1, JP2, JP9, J1, JP3, JP4, JP5, JP6,
JP3, JP4, JP5, JP7, JP8
JP6, JP7, JP8
7 R2, R3, R5, R6, 9 DNP, 0805 DNP
R8, R9, R10, R11,
R14
8 R12, R13, R7 3 0R, 0805 541-000ATR-ND
9 C5 1 1.1nF, CSMD0805 490-1623-2-ND
10 C3, C7 2 1uF, 10V, CSMD0805 490-1702-2-ND
11 R4 1 47k, 0805 541-47000ATR-ND
12 C4, C6 2 100nF, CSMD0805 311-1245-2-ND
13 R1 1 330R, 0805 541-330ATR-ND
14 C1, C2, C8, C9 4 DNP, CSMD0805 DNP
15 SW1, SW2 2 EVQ-11L05R P8079STB-ND DNP, Lacon: 1251459
16 BOOTST 1 10-pin connector, male, TH HRP10H-ND DNP, keep vias free of solder
17 JTAG 1 14-pin connector, male, TH HRP14H-ND
18 Q1 1 DNP: MS3V-TR1 (32768kHz, depends on application Micro Crystal, DNP, enclosed in kit, keep vias
20ppm, 12.5pF) free of solder
19 Q2 1 DNP, Christal depends on application DNP, keep vias free of solder
20 U1 1 Socket: QFN11T048-008 Manuf.: Yamaichi
A101121-001
20.1 U1 1 MSP430 DNP: enclosed with kit. Is supplied by TI.
21 D1 1 green LED, DIODE0805 P516TR-ND
22 D3 1 red (DNP), DIODE0805 DNP
23 D2 1 yellow (DNP), DIODE0805 DNP
24 TP1, TP2 2 Testpoint DNP, keep pads free of solder
25 Rubber stand off 4 Buerklin: 20H1724 apply to corners at bottom side
26 PCB 1 79.6 x 91.0 mm MSP-TS430RGZ48C 2 layers, black solder mask
Rev. 1.2
SLAU278Q–May 2009–Revised February 2014 Hardware 75
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ML14
LED3
0R
12pF
12pF
12pF
12pF
GND
GND
0R
100nF
560R
ML10
JP1Q
JP1Q
10uF/6,3V
10uF/10V
47K
10nF
0R
0R
0R
-
-
0R
-
0R
0R
FE16-1-1
FE16-1-2
FE16-1-3
FE16-1-4
PWR3
GNDGND
-
MSP64PM
not assembled
not assembled
not assembled
not assembled
enhancement
reserved for
future
JTAG
1
3
5
7
9
11
13
2
4
6
12
14
8
10
D1
R2
C2
C1
C3
C4
R1
C5
R3
BOOTST
1 2
3 4
5 6
7 8
9 10
J7
1 2
J6
1 2
C6
C7
R5
C8
R6
R7
R8
R9
R10
R11
R12
R13
R14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J1
J2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
J3
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
J4
J5
1
2
3
R4
Q1
LFXTCLK
XTCLK
U2
DVCC
2
3
4
5
6
7
XIN
XOUT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
TDO
TDI
TMS
TCK
RST
59
60
61
AVSS
DVSS
AVCC
RST/NMI
TCK
TMS
TDI
TDO
VCC
Date: 3/14/2006 10:46:30 AM Sheet: 1/1
REV:
TITLE:
Document Number:
MSP-TS430PM64
+
+
1
MSP-TS430PM64 Target Socket PM64
Yamaichi
IC51-0644-807
Socket:
1.2
for F14x and F41x
Open J6 if LCD
is connected
If external supply voltage:
remove R8 and add R9 (0 Ohm)
If external supply voltage:
remove R11 and add R10 (0 Ohm)
For BSL usage add:
R6 R7 R13 R14
MSP430F14x : 0 0 open open
MSP430F41x : open open 0 0
MSP-TS430PM64 www.ti.com
B.16 MSP-TS430PM64
NOTE: Connections between the JTAG header and pins XOUT and XIN are no longer required and should not be
made.
Figure B-31. MSP-TS430PM64 Target Socket Module, Schematic
76 Hardware SLAU278Q–May 2009–Revised February 2014
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Connector J5
External power connection
Remove R8 and jumper R9
LED connected
to pin 12
Jumper J6
Open to disconnect LED
Jumper J7
Open to measure current
Orient Pin 1 of
MSP430 device
www.ti.com MSP-TS430PM64
Figure B-32. MSP-TS430PM64 Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 77
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MSP-TS430PM64 www.ti.com
Table B-18. MSP-TS430PM64 Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
1.1 C3, C4 0 47pF, SMD0805 DNP: Only recommendation. Check your crystal spec.
2 C6, C7 1 10uF, 10V, Tantal Size B 511-1463-2-ND DNP: C6
3 C5 1 100nF, SMD0805 478-3351-2-ND
4 C8 1 10nF, SMD0805 478-1383-2-ND
5 C9 1 470nF, SMD0805 478-1403-2-ND
6 D1 1 green LED, SMD0805 P516TR-ND
DNP: Headers and
receptacles enclosed with
7 J1, J2, J3, J4 0 16-pin header, TH kit.Keep vias free of solder.
SAM1029-16-ND : Header
SAM1213-16-ND : Receptacle
8 J5 1 3-pin header, male, TH SAM1035-03-ND
9 J6, J7 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
11 2 Jumper 15-38-1024-ND Place on: J6, J7
12 JTAG 1 14-pin connector, male, TH HRP14H-ND
13 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Q1: Micro Crystal MS1V-T1K DNP: Keep vias free of 14 Q1, Q2 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
15 R3 1 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R4,
R6, R7, R8, DNP: R4, R6, R7, R9, R10, 16 R9, R10, 3 0 Ω, SMD0805 541-000ATR-ND R11, R12, R13, R14 R11, R12,
R13, R14
17 R5 1 47k Ω, SMD0805 541-47000ATR-ND
18 U1 1 Socket: IC51-0644-807 Manuf.: Yamaichi
19 PCB 1 78 x 75 mm 2 layers
20 Rubber 4 select appropriate Apply to corners at bottom standoff side
21 MSP430 22 MSP430F2619IPM DNP: Enclosed with kit MSP430F417IPM supplied by TI
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0R
12pF
12pF
GND
GND
0R
100nF
330R
10uF/6.3V
0R 0R
0R 0R
PWR3
GND
47k
2.2nF
330R
GND
GND
100nF
GND
0R
0R
MSP-TS430PM64A Target Socket
DNP
Yamaichi
IC51-0644-807
Socket:
DNP
1.1
for F4152
Open JP1 if LCD
is connected
JTAG ->
SBW ->
DNP
DNP
DNP
DNP DNP
DNP DNP
Vcc
ext
int
TEST/SBWTCK RST/SBWTDIO P7.0/TDO P7.1/TDI P7.2/TMS P7.3/TCK
ADD LCD-CAP!
DNP
DNP
JTAG
1
3
5
7
9
11
13
2
4
6
12
14
8
10
R2
C2
C1
R1
C5
R3
BOOTST
1 2
3 4
5 6
7 8
9 10
C6
R10 R11
R13 R14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
J2
J3
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
J4
J5
1
2
3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
11
12
13
14
15
10
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1 2
Q1
R4
C3
1
2
3
JP4 JP5
1
2
3
JP6
1
2
3
JP7
1
2
3
JP8
1
2
3
R6
JP9
1
2
3
1
2
JP1
JP2
1
2
JP3
1
2
3
D1
C4
R5
R7
RST/NMI
TMS
TDI
VCC
GND
XTLGND
TCK/SBWTCK
TDO/SBWTDIO
VCC430
VCC430
VCC430
P5.1
P5.1
AVCC
AVCC
AVSS
AVSS
P1.0
P1.1
XIN
XOUT
A
A
A
B
B
B
C
C
D
D
E
E
F
F
Date: 3/29/2011 3:07:02 PM Sheet: 1/1
REV:
TITLE:
Document Number:
MSP-TS430PM64A
+
TEST/SBWTCK
RST/SBWTDIO
If supplied locally: populate R10 (0R), remove R11
If supplied by interface: populate R11 (0R), remove R10
www.ti.com MSP-TS430PM64A
B.17 MSP-TS430PM64A
Figure B-33. MSP-TS430PM64A Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 79
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Jumper JP2
Open to measure current
Jumper JP1
Open to disconnect LED
LED D1 connected to P5.1
Jumper JP3
1-2 (int): Power supply via JTAG interface
2-3 (ext): External Power Supply
Jumper JP4 to JP9:
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
Orient Pin 1 of Device
MSP-TS430PM64A www.ti.com
Figure B-34. MSP-TS430PM64A Target Socket Module, PCB
80 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-TS430PM64A
Table B-19. MSP-TS430PM64A Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2, 0 12pF, SMD0805 DNP
2 C3 0 2.2nF, SMD0805 DNP
3 C6, 1 10uF, 10V, Tantal Size B 511-1463-2-ND
4 C4, C5 2 100nF, SMD0805 478-3351-2-ND
5 D1 1 green LED, SMD0805 P516TR-ND
DNP: Headers and
receptacles enclosed with kit.
6 J1, J2, J3, J4 0 16-pin header, TH Keep vias free of solder.
SAM1029-16-ND : Header
SAM1213-16-ND : Receptacle
J5, JP3, JP4,
7 JP5, JP6, 8 3-pin header, male, TH SAM1035-03-ND JP7, JP8,
JP9
8 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
9 2 Jumper 15-38-1024-ND Place on: J6, J7
10 JTAG 1 14-pin connector, male, TH HRP14H-ND
11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
13 R3, R6 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R5,
14 R7, R9, R10, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R5, R7, R9, R10, R11, R11, R13, R13, R14
R14
15 R4 1 47k Ω, SMD0805 541-47000ATR-ND
16 U1 1 Socket: IC51-0644-807 Manuf.: Yamaichi
17 PCB 1 78 x 75 mm 4 layers
18 Rubber stand 4 select appropriate Apply to corners at bottom off side
19 MSP430 2 MSP430F4152IPM DNP: Enclosed with kit supplied by TI
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MSP-TS430RGC64B www.ti.com
B.18 MSP-TS430RGC64B
Figure B-35. MSP-TS430RGC64B Target Socket Module, Schematic
82 Hardware SLAU278Q–May 2009–Revised February 2014
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Jumper JP2
Open to disconnect LED
Connector J5
External power connector
Jumper JP3 to "ext"
Jumpers JP5 to JP10
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
D1 LED connected to P1.0
If the system should
be supplied via LDOI (J6),
close JP4 and
set JP3 to external
Orient Pin 1 of MSP430 device
www.ti.com MSP-TS430RGC64B
Figure B-36. MSP-TS430RGC64B Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 83
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MSP-TS430RGC64B www.ti.com
Table B-20. MSP-TS430RGC64B Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C3, C4 0 47pF, SMD0805 DNP
3 C6, C7, C10 3 10uF, 6.3V, SMD0805
C5, C11,
4 C13, C14, 5 100nF, SMD0805 311-1245-2-ND
C15
5 C8 1 2.2nF, SMD0805
6 C9 1 470nF, SMD0805 478-1403-2-ND
7 C16 1 4.7uF, SMD0805
8 C17 1 220nF, SMD0805
9 D1 1 green LED, SMD0805 P516TR-ND
J1, J2, J3, SAM1029-16-ND DNP: Headers and receptacles 10 J4 0 16-pin header, TH (Header) SAM1213-16- enclosed with kit. Keep vias free of ND (Receptacle) solder:
11 J5 , J6 2 3-pin header, male, TH
JP3, JP5, place jumpers on pins 2-3 on JP5, JP6, 12 JP6, JP7, 7 3-pin header, male, TH SAM1035-03-ND JP7, JP8, JP9, JP10 place jumpers on JP8, JP9, pins 1-2 on JP3, JP10
13 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header JP4
14 10 Jumper 15-38-1024-ND See Pos. 12 and Pos. 13
15 JTAG 1 14-pin connector, male, HRP14H-ND TH
16 BOOTST 0 10-pin connector, male, "DNP Keep vias free of solder" TH
Micro Crystal MS3V-T1R
17 Q1 0 Crystal 32.768kHz, C(Load) = DNP: Q1 Keep vias free of solder
12.5pF
18 Q2 0 Crystal Q2: 4MHz Buerklin: DNP: Q2 Keep vias free of solder 78D134
Insulating http://www.ettinger.de/Art 19 disk to Q2 0 Insulating disk to Q2 _Detail.cfm?ART_ARTNU M=70.08.121
20 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R4,
21 R6, R8, 3 0 Ohm, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11,R12 R9,R10,
R11, R12
22 R5 1 47k Ω, SMD0805 541-47000ATR-ND
23 U1 1 Socket: QFN11T064-006- Manuf.: Yamaichi N-HSP
24 PCB 1 85 x 76 mm 2 layers
Adhesive Approximately 6mm for example, 3M 25 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302
26 D3,D4
27 MSP430 2 MSP430F5310 RGC DNP: enclosed with kit, supplied by TI
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B.19 MSP-TS430RGC64C
The MSP-TS430RGC64C target board has been designed with the option to operate with the target
device DVIO input voltage supplied via header J6 (see Figure B-37). This development platform does not
supply the 1.8-V DVIO rail on board and it MUST be provided by external power supply for proper device
operation. For correct JTAG connection, programming, and debug operation, it is important to follow this
procedure:
1. Make sure that the VCC and DVIO voltage supplies are OFF and that the power rails are fully
discharged to 0 V.
2. Enable the 1.8-V external DVIO power supply.
3. Enable the 1.8-V to 3.6-V VCC power supply (alternatively, this supply can be provided from the MSPFET430UIF
JTAG debugger interface).
4. Connect the MSP-FET430UIF JTAG connector to the target board.
5. Start the debug session using IAR or CCS IDE.
For more information on debugging the MSP4and MSP430F525x, see the device-specific data sheets
(MSP430F522x: SLAS718; MSP430F525x: SLAS903) and Designing with MSP430F522x and
MSP430F521x Devices (SLAA558).
For debugging of devices (MSP430F524x and MSP430F523x) without use of the DVIO power domain,
short JP4 with the jumper.
SLAU278Q–May 2009–Revised February 2014 Hardware 85
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1.1
MSP-TS430RGC64C
TI Friesing
Tools
MSP430
1 1
12/14/10 S.G.
1 2 3 4 5 6
A
B
C
D
A
B
C
D
Design:
Appr.:
Rev.:
Comment:
Drawing#: Revision:
File: Page: Size:
Title of Schematic
of Mentor Pads Logic V9
Date: Name:
1 2 3 4 5 6
MSP-TS430RGC64C.sch
<-- SBW
<-- JTAG
ext
int
VCC
DVIO Power Circle
BSL
1 P6.0/CB0/A0
2 P6.1/CB1/A1
3 P6.2/CB2/A2
4 P6.3/CB3/A3
5 P6.4/CB4/A4
6 P6.5/CB5/A5
7 P6.6/CB6/A6
8 P6.7/CB7/A7
9 P5.0/A8/VEREF+
10 P5.1/A9/VEREF-
11 AVCC
12 P5.4/XIN
13 P5.5/XOUT
14 AVSS
15 DVCC
16 DVSS
17 VCORE
18 P1.0/TA0CLK/ACLK
19 P1.1/TA0.0
20 P1.2/TA0.1
21 P1.3/TA0.2
22 P1.4/TA0.3
23 P1.5/TA0.4
24 P1.6/TA1CLK/CBOUT
25 P1.7/TA1.0
26 P2.0/TA1.1
27 P2.1/TA1.2
28 P2.2/TA2CLK/SMCLK
29 P2.3/TA2.0
30 P2.4/TA2.1
31 P2.5/TA2.2
32 P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK 33
P3.0/UCB0SIMO/UCB0SDA 34
P3.1/UCB0SOMI/UCB0SCL 35
P3.2/UCB0CLK/UCA0STE 36
P3.3/UCA0TXD/UCA0SIMO 37
P3.4/UCA0RXD/UCA0SOMI 38
DVSS 39
DVIO 40
P4.0/PM_UCB1STE 41
P4.1/PM_UCB1SIMO 42
P4.2/PM_UCB1SOMI 43
P4.3/PM_UCB1CLK 44
P4.4/PM_UCA1TXD 45
P4.5/PM_UCA1RXD 46
P4.6/PM_NONE 47
P4.7/PM_NONE 48
49 P7.0/TB0.0
50 P7.1/TB0.1
51 P7.2/TB0.2
52 P7.3/TB0.3
53 P7.4/TB0.4
54 P7.5/TB0.5
55 BSLEN
56 RST/NMI
57 P5.2/XT2IN
58 P5.3/XT2OUT
59 TEST/SBWTCK
60 PJ.0/TDO
61 PJ.1/TDI/TCLK
62 PJ.2/TMS
63 PJ.3/TCK
64 RSTDVCC/SBWTDIO
65 THERMAL_1
66 THERMAL_2
67 THERMAL_3
68 THERMAL_4
69 THERMAL_5
70 THERMAL_6
71 THERMAL_7
72 THERMAL_8
U1
MSP430F5229
2 1
4 3
6 5
8 7
10 9
12 11
14 13
JTAG
1 2
3 4
5 6
7 8
9 0 1
BOOTST
CN-ML10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J4
1
2
3
JP5
PINHEAD_1X3
1
2
3
JP6
PINHEAD_1X3
1
2
3
JP7
PINHEAD_1X3
1
2
3
JP8
PINHEAD_1X3
1
2
3
JP9
PINHEAD_1X3
1
2
3
JP10
PINHEAD_1X3
1
2
3
J5
PINHEAD_1X3
R7
330R
1
2
3
JP3
C10
10uF
C14
100nF
C5
10uF
C6
100nF
R1
0R
R2
0R
R6
0R R8
0R
C1 12pF
C2
12pF
C7
10uF
C13
100nF
1
2
JP2
R3
330R
1 2
D1
??? R4
0R
C9
470nF
R5
47K
C8
2.2nF
R11
0R
R12
0R
C16
4.7uF
tbd C3
tbd C4
R9
0R
R10
0R
C15
100nF
1
2
3
J6
PINHEAD_1X3
1
2
JP4
PINHEAD_1X2
D3
Q2
QUARZ_4PIN
26MHz/ASX53
Q1
1
2
JP1
PINHEAD_1X2
SHC1
SHORTCUT2
GND
GND
GND
GND
XTLGND
VCORE
GND
GND
DVCC
DVCC
GND
XTLGND2
GND
GND
DVCC
GND
RST/NMI
TCK
TMS
TDI
TDO
RSTDVCC_SBWTDIO
TDO
RST/NMI
TCK
C
TCK
M
TMS
I
TDI
O
TDO
DVCC
P1.2/TA0.1
P1.1/TA0.0
TEST/SBWTCK
C
M
I
O
DVCC
P1.1/TA0.0
P1.2/TA0.1
RSTDVCC_SBWTDIO
TEST/SBWTCK
AVSS
MSP-TS430RGC64C www.ti.com
Figure B-37. MSP-TS430RGC64C Target Socket Module, Schematic
86 Hardware SLAU278Q–May 2009–Revised February 2014
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Connector J5
External power connector for DVCC.
Set jumper JP3 to "ext".
IMPORTANT NOTE:
Rev1.0 of the board does not have
connection from pin 4 of BOOTST to
pin 64 of MCU. To use BSL, these pins
should be connected by a wire.
Jumper JP2
Open to disconnect LED.
D1
LED connected to P1.0
Orient Pin 1 of
MSP430 device
Jumpers JP5 to JP10
-2 to debug in
Spy-Bi-Wire mode.
Close 2-3 to debug in
4-wire JTAG mode.
Close 1
Jumper JP4
For F524x devices, close.
For F522x, F523x and F525x devices,
close only if one power supply is
used for VCC and DVIO, and if VCC is
not higher then 1.98 V. Otherwise.
supply DVIO over J6.
Do not close if VCC > 1.98 V, as it
may damage the chip.
Connector J6
External power connector
to supply DVIO
www.ti.com MSP-TS430RGC64C
Figure B-38. MSP-TS430RGC64C Target Socket Module, PCB
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MSP-TS430RGC64C www.ti.com
Table B-21. MSP-TS430RGC64C Bill of Materials
Item Qty Reference Value Description Comment Supplier No.
1 0 C1, C2 12pF CAP, SMD, Ceramic, 0805 DNP C1 C2
2 0 C3, C4 tbd CAP, SMD, Ceramic, 0805 DNP C3 C4
4 3 C5, C7, C10 10uF CAP, SMD, Ceramic, 0805
5 5 C8 C6 C13-15 100nF CAP, SMD, Ceramic, 0805 DigiKey: 311-1245-2-ND
5 5 C8 2.2nF CAP, SMD, Ceramic, 0805
6 1 C9 470nF CAP, SMD, Ceramic, 0805 DigiKey: 478-1403-2-ND
7 1 C16 4.7uF CAP, SMD, Ceramic, 0805
8 1 D1 Green LED LED, SMD, 0805
DNP: headers and
receptacles enclosed with
9 4 J1-J4 16-pin header Pin header 1x16: Grid: 100mil kit. Keep vias free of (2.54 mm) solder.
: Header SAM1029-16-ND
: Receptacle SAM1213-16-ND
10 2 J5, J6 3-pin header, male, TH Pin header 1x3: Grid: 100mil SAM1035-03-ND (2.54 mm)
11 JP5, JP6, JP7, 3-pin header, male, TH Pinheader 1x3: Grid: 100mil place jumpers on pins 2-3 SAM1035-03-ND JP8, JP9, JP10 (2.54 mm)
12 JP3 3-pin header, male, TH Pin header 1x3: Grid: 100mil place jumper on pins 1-2 SAM1035-03-ND (2.54 mm)
13 JP1, JP2, JP4 2-pin header, male, TH Pin header 1x2; Grid: 100mil place jumper on header SAM1035-02-ND (2.54 mm)
Place on: JP1, JP2, JP3,
14 10 Jumper JP4, JP5, JP6, JP7, JP8, 15-38-1024-ND
JP9, JP10
15 1 JTAG 2x7Pin,Wanne Header, THD, Male 2x7 Pin, HRP14H-ND Wanne, 100mil spacing
16 0 BOOTST 2x5Pin,Wanne Header, THD, Male 2x5 Pin, DNP Wanne, 100mil spacing
17 1 Q1 26MHz/ASX53 CRYSTAL, SMD, 5x3MM, Only Kit. 26MHz
18 0 Q2 26MHz/ASX53 CRYSTAL, SMD, 5x3MM, 300-8219-1-ND 26MHz
19 1 D3 LL103A DIODE, SMD, SOD123, Buerklin: 24S3406 Schottky
20 2 R3, R7 330 Ohm, SMD0805 541-330ATR-ND
21 1 R5 47k Ohm, SMD0805 RES, SMD, 0805, 1/8W, x% 541-47000ATR-ND
R1, R2, R4, DNP: R6, R8, R9, R10, 22 R6, R8, R9, 0 Ohm, SMD0805 RES, SMD, 0805, 1/8W, x% R11,R12 541-000ATR-ND R10, R11, R12
23 1 U1 Socket: QFN11T064-006-N- Manuf.: Yamaichi HSP
24 2 MSP430 MSP430F5229IRGCR IC, MCU, SMD, 9.15x9.15mm Thermal Pad with Socket
25 4 Rubber stand Rubber stand off apply to corners at bottom Buerklin: 20H1724 off side
26 1 PCB 84 x 76 mm 84 x 76 mm
88 Hardware SLAU278Q–May 2009–Revised February 2014
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B.20 MSP-TS430RGC64USB
Due to the use of diodes in the power chain, the voltage on the MSP430F5xx device is approximately
0.3 V lower than is set by the debugging tool. Set the voltage in the IDE to 0.3 V higher than desired; for
example, to run the MCU at 3.0 V, set it to 3.3 V.
Figure B-39. MSP-TS430RGC64USB Target Socket Module, Schematic
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Figure B-40. MSP-TS430RGC64USB Target Socket Module, PCB
90 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-22. MSP-TS430RGC64USB Bill of Materials
Pos. Ref Des No. Per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2
1.1 C3, C4 2 47pF, SMD0805
2 C6, C7 2 10uF, 6.3V, Tantal Size B 511-1463-2-ND
3 C5, C11, 4 100nF, SMD0805 311-1245-2-ND C13, C14
3.1 C10, C12 0 10uF, SMD0805 DNP: C10, C12
4 C8 1 2.2nF, SMD0805
5 C9 1 470nF, SMD0805 478-1403-2-ND
6 D1 1 green LED, SMD0805 P516TR-ND
DNP: headers and
receptacles enclosed with kit.
7 J1, J2, J3, J4 4 16-pin header, TH Keep vias free of solder.
SAM1029-16-ND : Header
SAM1213-16-ND : Receptacle
8 J5 1 3-pin header, male, TH SAM1035-03-ND
JP5, JP6,
9 JP7, JP8, 6 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 2-3
JP9, JP10
10 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND place jumper on header JP4
11 JP3 1 3-pin header, male, TH SAM1035-03-ND place jumper on pins 1-2
Place on: JP1, JP2, JP3,
12 10 Jumper 15-38-1024-ND JP4, JP5, JP6, JP7, JP8,
JP9, JP10
13 JTAG 1 14-pin connector, male, TH HRP14H-ND
Q1: Micro Crystal MS1V-T1K DNP: Q1 14 Q1 0 Crystal 32.768kHz, C(Load) = Keep vias free of solder" 12.5pF
15 Q2 1 Crystal Q2: 4MHz Buerklin: 78D134
16 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R4,
17 R6, R8, R9, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R4, R6, R8, R9, R12
R12
18 R10 1 100 Ω, SMD0805 Buerklin: 07E500
18 R11 1 1M Ω, SMD0805
18 R5 1 47k Ω, SMD0805 541-47000ATR-ND
19 U1 1 Socket: QFN11T064-006 Manuf.: Yamaichi
20 PCB 1 79 x 77 mm 2 layers
21 Rubber stand 4 Buerklin: 20H1724 apply to corners at bottom off side
22 MSP430 2 MSP430F5509 RGC DNP: enclosed with kit. Is supplied by TI
Insulating http://www.ettinger.de/Art_De 23 disk to Q2 1 Insulating disk to Q2 tail.cfm?ART_ARTNUM=70.0 8.121
27 C33 1 220n SMD0603 Buerklin: 53D2074
28 C35 1 10p SMD0603 Buerklin: 56D102
29 C36 1 10p SMD0603 Buerklin: 56D102
30 C38 1 220n SMD0603 Buerklin: 53D2074
31 C39 1 4u7 SMD0603 Buerklin: 53D2086
32 C40 1 0.1u SMD0603 Buerklin: 53D2068
33 D2, D3, D4 3 LL103A Buerklin: 24S3406
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Table B-22. MSP-TS430RGC64USB Bill of Materials (continued)
Pos. Ref Des No. Per Description DigiKey Part No. Comment Board
34 IC7 1 TPD4E004 Manu: TI
36 LED 0 JP3QE SAM1032-03-ND DNP
37 LED1 0 LEDCHIPLED_0603 FARNELL: 852-9833 DNP
38 LED2 0 LEDCHIPLED_0603 FARNELL: 852-9868 DNP
39 LED3 0 LEDCHIPLED_0603 FARNELL: 852-9841 DNP
40 R13, R15, 0 470R Buerklin: 07E564 DNP R16
41 R33 1 1k4 / 1k5 Buerklin: 07E612
42 R34 1 27R Buerklin: 07E444
43 R35 1 27R Buerklin: 07E444
44 R36 1 33k Buerklin: 07E740
45 S1 0 PB P12225STB-ND DNP
46 S2 0 PB P12225STB-ND DNP
46 S3 1 PB P12225STB-ND
47 USB1 1 USB_RECEPTACLE FARNELL: 117-7885
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B.21 MSP-TS430PN80
NOTE: For MSP430F47x and MSP430FG47x devices:
Connect pins 7 and 10 (GND) externally to DVSS (see data sheet).
Connect load capacitance on Vref pin 60 when SD16 is used (see data sheet).
For use of BSL: connect pin 1 of BOOST to pin 58 of U1 and pin 3 of BOOST to pin 57 of U1.
Figure B-41. MSP-TS430PN80 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 93
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Connector J5
External power connection
Remove R8 and jumper R9
LED connected to pin 12
Jumper J6
Open to disconnect LED
Orient Pin 1 of MSP430 device
MSP-TS430PN80 www.ti.com
Figure B-42. MSP-TS430PN80 Target Socket Module, PCB
94 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-23. MSP-TS430PN80 Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2
1.1 C3, C4 0 47pF, SMD0805 DNP: Only recommendation. Check your crystal spec.
2 C6, C7 1 10uF, 10V, Tantal Size B 511-1463-2-ND
3 C5 1 100nF, SMD0805 478-3351-2-ND
4 C8 1 10nF, SMD0805 478-1383-2-ND
5 D1 1 green LED, SMD0603 475-1056-2-ND
DNP: Headers and
receptacles enclosed with
6 J1, J2, J3, J4 0 25-pin header, TH kit.Keep vias free of solder.
SAM1029-20-ND : Header
SAM1213-20-ND : Receptacle
7 J5, JP1 2 3-pin header, male, TH SAM1035-03-ND
8 J6, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
9 3 Jumper 15-38-1024-ND Place on: J6, JP2, JP1/Pos1- 2
10 JTAG 1 14-pin connector, male, TH HRP14H-ND
11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Q1: Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1, Q2 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
13 R3 1 560 Ω, SMD0805 541-560ATR-ND
R1, R2, R4, DNP: R4, R6, R7, R10, R11, 14 R6, R7, R10, 2 0 Ω, SMD0805 541-000ATR-ND R12 R11, R12
15 R5 1 47k Ω, SMD0805 541-47000ATR-ND
16 U1 1 Socket: IC201-0804-014 Manuf.: Yamaichi
17 PCB 1 77 x 77 mm 2 layers
18 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side
19 MSP430 2 MSP430FG439IPN DNP: Enclosed with kit supplied by TI
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MSP-TS430PN80A www.ti.com
B.22 MSP-TS430PN80A
Figure B-43. MSP-TS430PN80A Target Socket Module, Schematic
96 Hardware SLAU278Q–May 2009–Revised February 2014
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Connector J5
External power connector
Jumper JP3 to "ext"
Orient Pin 1 of MSP430 device
Jumpers JP5 to JP10
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
D1 LED connected to P1.0
Jumper JP2
Open to disconnect LED
If the system should
be supplied via LDOI (J6),
close JP4 and
set JP3 to external
www.ti.com MSP-TS430PN80A
Figure B-44. MSP-TS430PN80A Target Socket Module, PCB
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MSP-TS430PN80A www.ti.com
Table B-24. MSP-TS430PN80A Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
2 C3, C4 0 47pF, SMD0805 DNP
3 C6, C7, 3 10uF, 6.3V, SMD0805 DNP C10 C10, C12
C5, C11,
4 C13, C14, 5 100nF, SMD0805 311-1245-2-ND
C15
5 C8 1 2.2nF, SMD0805
6 C9 1 470nF, SMD0805 478-1403-2-ND
7 C16 1 4.7uF, SMD0805
8 C17 1 220nF, SMD0805
9 D1 1 green LED, SMD0805 P516TR-ND
J1, J2, J3, SAM1029-20-ND DNP: Headers and receptacles 10 J4 0 20-pin header, TH (Header) SAM1213-20- enclosed with kit. Keep vias free of ND (Receptacle) solder:
11 J5 , J6 2 3-pin header, male, TH
JP3, JP5, place jumpers on pins 2-3 on JP5, 12 JP6, JP7, 7 3-pin header, male, TH SAM1035-03-ND JP6, JP7, JP8, JP9, JP10 place JP8, JP9, jumpers on pins 1-2 on JP3, JP10
13 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header JP4
14 10 Jumper 15-38-1024-ND See Pos. 12 and Pos. 13
15 JTAG 1 14-pin connector, male, HRP14H-ND TH
16 BOOTST 0 10-pin connector, male, "DNP Keep vias free of solder" TH
Micro Crystal MS3V-T1R
17 Q1 0 Crystal 32.768kHz, C(Load) = DNP: Q1 Keep vias free of solder
12.5pF
18 Q2 0 Crystal Q2: 4MHz Buerklin: DNP: Q2 Keep vias free of solder 78D134
Insulating http://www.ettinger.de/Ar 19 disk to Q2 0 Insulating disk to Q2 t_Detail.cfm?ART_ART NUM=70.08.121
20 D3,D4 2 LL103A Buerklin: 24S3406
21 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2,
R4, R6,
22 R8, 3 0 Ohm, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11,R12
R9,R10,
R11, R12
23 R5 1 47k Ω, SMD0805 541-47000ATR-ND
24 U1 1 Socket:IC201-0804-014 Manuf.: Yamaichi
25 PCB 1 77 x 91 mm 2 layers
Adhesive Approximately 6mm for example, 3M 26 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302
27 MSP430 2 MSP430F5329IPN DNP: enclosed with kit, supplied by TI
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B.23 MSP-TS430PN80USB
Due to the use of diodes in the power chain, the voltage on the MSP430F5xx device is approximately
0.3 V lower than is set by the debugging tool. Set the voltage in the IDE to 0.3 V higher than desired; for
example, to run the MCU at 3.0 V, set it to 3.3 V.
NOTE: R11 should be populated.
Figure B-45. MSP-TS430PN80USB Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 99
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Jumper JP3
1-2 (int): Power supply via JTAG debug interface
2-3 (ext): External power supply
Connector J5
External power connector
Jumper JP3 to ‘ext’
USB Connector
BSL invoke button S3
Jumper JP4
Close for USB bus powered
device
Jumper JP2
Open to disconnect LED
LED connected to P1.0
Jumper JP1
Open to measure current
Jumper JP5 to JP10
Close 1-2 to debug in Spy-Bi-
Wire mode.
Close 2-3 to debug in 4-wire
JTAG mode.
MSP-TS430PN80USB www.ti.com
Figure B-46. MSP-TS430PN80USB Target Socket Module, PCB
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Table B-25. MSP-TS430PN80USB Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2
1.1 C3, C4 2 47pF, SMD0805
2 C6, C7 2 10uF, 6.3V, Tantal Size B 511-1463-2-ND
3 C5, C11, 4 100nF, SMD0805 311-1245-2-ND C13, C14
3.1 C10, C12 0 10uF, SMD0805 311-1245-2-ND DNP: C10, C12
4 C8 1 2.2nF, SMD0805
5 C9 1 470nF, SMD0805 478-1403-2-ND
6 D1 1 green LED, SMD0805 P516TR-ND
DNP: headers and
7 J1, J2, J3, 4 20-pin header, TH SAM1029-20-ND receptacles enclosed with J4 kit. Keep vias free of
solder.
DNP: headers and
receptacles enclosed with
kit. Keep vias free of
7.1 4 20-pin header, TH solder.
SAM1213-20-ND : Header
: Receptacle
8 J5 1 3-pin header, male, TH SAM1035-03-ND
JP5, JP6,
9 JP7, 6 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 2-3 JP8,JP9,
JP10
10 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
JP4 1 SAM1035-02-ND Place jumper only on one pin
11 JP3 1 3-pin header, male, TH SAM1035-03-ND Place jumper on pins 1-2
Place on: JP1, JP2, JP3,
12 10 Jumper 15-38-1024-ND JP4, JP5, JP6, JP7, JP8,
JP9, JP10
13 JTAG 1 14-pin connector, male, TH HRP14H-ND
Micro Crystal MS1V-T1K DNP: Q1 Keep vias free of 14 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
15 Q2 1 Crystal "Q2: 4MHzBuerklin: 78D134"
16 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R4,
17 R6, R8, R9, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R4, R6, R8, R9, R12
R12
18 R10 1 100 Ω, SMD0805 Buerklin: 07E500
18 R11 0 1M Ω, SMD0805 DNP
18 R5 1 47k Ω, SMD0805 541-47000ATR-ND
19 U1 1 Socket:IC201-0804-014 Manuf.: Yamaichi
20 PCB 1 79 x 77 mm 2 layers
21 Rubber 4 Buerklin: 20H1724 Apply to corners at bottom standoff side
22 MSP430 2 MSP430F5529 DNP: Enclosed with kit supplied by TI
Insulating http://www.ettinger.de/Art_ 23 disk to Q2 1 Insulating disk to Q2 Detail.cfm?ART_ARTNUM =70.08.121
27 C33 1 220n Buerklin: 53D2074
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Table B-25. MSP-TS430PN80USB Bill of Materials (continued)
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
28 C35 1 10p Buerklin: 56D102
29 C36 1 10p Buerklin: 56D102
30 C38 1 220n Buerklin: 53D2074
31 C39 1 4u7 Buerklin: 53D2086
32 C40 1 0.1u Buerklin: 53D2068
33 D2, D3, D4 3 LL103A Buerklin: 24S3406
34 IC7 1 TPD4E004 Manu: TI
36 LED 0 JP3QE SAM1032-03-ND DNP
37 LED1 0 LEDCHIPLED_0603 FARNELL: 852-9833 DNP
38 LED2 0 LEDCHIPLED_0603 FARNELL: 852-9868 DNP
39 LED3 0 LEDCHIPLED_0603 FARNELL: 852-9841 DNP
40 R13, R15, 0 470R Buerklin: 07E564 DNP R16
41 R33 1 1k4 Buerklin: 07E612
42 R34 1 27R Buerklin: 07E444
43 R35 1 27R Buerklin: 07E444
44 R36 1 33k Buerklin: 07E740
45 S1 0 PB P12225STB-ND DNP
46 S2 0 PB P12225STB-ND DNP
46 S3 1 PB P12225STB-ND
47 USB1 1 USB_RECEPTACLE FARNELL: 117-7885
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www.ti.com MSP-TS430PZ100
B.24 MSP-TS430PZ100
NOTE: Connections between the JTAG header and pins XOUT and XIN are no longer required and should not be
made.
Figure B-47. MSP-TS430PZ100 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 103
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Connector J5
External power connection
Remove R8 and jumper R9
LED connected to pin 12
Jumper J6
Open to disconnect LED
Orient Pin 1 of MSP430 device
Jumper J7
Open to measure current
MSP-TS430PZ100 www.ti.com
Figure B-48. MSP-TS430PZ100 Target Socket Module, PCB
104 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-26. MSP-TS430PZ100 Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
DNP: Only
1b C3, C4 0 47pF, SMD0805 recommendation. Check
your crystal spec.
2 C6, C7 1 10uF, 10V, Tantal Size B 511-1463-2-ND DNP: C6
3 C5 1 100nF, SMD0805 478-3351-2-ND
4 C8 1 10nF, SMD0805 478-1383-2-ND
5 C9 1 470nF, SMD0805 478-1403-2-ND
6 D1 1 yellow LED, TH, 3mm, T1 511-1251-ND
DNP: Headers and
receptacles enclosed with
7 J1, J2, J3, 0 25-pin header, TH kit.Keep vias free of solder. J4 SAM1029-25-ND : Header
SAM1213-25-ND : Receptacle
8 J5 1 3-pin header, male, TH SAM1035-03-ND
9 J6, J7 2 2-pin header, male, TH SAM1035-02-ND place jumper on header
10 2 Jumper 15-38-1024-ND Place on: J6, J7
11 JTAG 1 14-pin connector, male, TH HRP14H-ND
12 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Q1: Micro Crystal MS1V- DNP: Keep vias free of 13 Q1, Q2 0 Crystal T1K 32.768kHz, C(Load) = solder 12.5pF
14 R3 1 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R4,
15 R8, R9, R10, 3 0 Ω, SMD0805 541-000ATR-ND DNP: R4, R9, R10, R12
R11, R12
16 R5 1 47k Ω, SMD0805 541-47000ATR-ND
17 U1 1 Socket: IC201-1004-008 or Manuf.: Yamaichi IC357-1004-53N
18 PCB 1 82 x 90 mm 2 layers
19 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side
20 MSP430 2 MSP430FG4619IPZ DNP: enclosed with kit supplied by TI
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MSP-TS430PZ100A www.ti.com
B.25 MSP-TS430PZ100A
Figure B-49. MSP-TS430PZ100A Target Socket Module, Schematic
106 Hardware SLAU278Q–May 2009–Revised February 2014
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Jumper JP1
Open to measure current
Jumper JP2
Open to disconnect LED
LED D1 connected to P5.1
Jumper JP3
1-2 (int): Power supply via JTAG interface
2-3 (ext): External Power Supply
Orient Pin 1 of Device
www.ti.com MSP-TS430PZ100A
Figure B-50. MSP-TS430PZ100A Target Socket Module, PCB
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Table B-27. MSP-TS430PZ100A Bill of Materials
Pos. Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
DNP: Only
1b C3, C4 0 47pF, SMD0805 recommendation. Check
your crystal spec.
2 C7, C9 2 10uF, 10V, Tantal Size B 511-1463-2-ND
3 C5, C11, 3 100nF, SMD0805 311-1245-2-ND C14
4 C8 1 10nF, SMD0805 478-1358-1-ND
5 C6 0 470nF, SMD0805 478-1403-2-ND DNP
6 D1 1 green LED, SMD0805 67-1553-1-ND
DNP: Headers and
receptacles enclosed with
7 J1, J2, J3, 0 25-pin header, TH kit.Keep vias free of solder. J4 SAM1029-25-ND : Header
SAM1213-25-ND : Receptacle
8 J5 1 3-pin header, male, TH SAM1035-03-ND
10 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND pPlace jumper on header
11 JP3 1 3-pin header, male, TH SAM1035-03-ND Place jumper on pins 1-2
12 3 Jumper 15-38-1024-ND Place on: JP1, JP2, JP3
13 JTAG 1 14-pin connector, male, TH HRP14H-ND
14 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Q1: Micro Crystal MS1V- DNP: Keep vias free of 15 Q1, Q2 0 Crystal T1K 32.768kHz, C(Load) = solder 12.5pF
16 R3 1 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R4,
17 R6, R7, R8, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R4, R6, R7, R8, R9, R9, R10, R10, R11, R12
R11, R12
18 R5 1 47k Ω, SMD0805 541-47000ATR-ND
19 U1 1 Socket: IC357-1004-53N Manuf.: Yamaichi
20 PCB 1 90 x 82 mm 4 layers
21 Rubber 4 Select appropriate Apply to corners at bottom standoff side
22 MSP430 2 MSP430F5438IPZ DNP: Enclosed with kit supplied by TI
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B.26 MSP-TS430PZ100B
Figure B-51. MSP-TS430PZ100B Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 109
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Connector J5
External power connector
Jumper JP1 to "ext"
Jumper JP1
Open to measure current
Orient Pin 1 of MSP430 device
Jumpers JP5 to JP10
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
JP11, JP12, JP13
Connect 1-2 to connect
AUXVCCx with DVCC or
drive AUXVCCx externally
D1 LED connected to P1.0
Jumper JP2
Open to disconnect LED
MSP-TS430PZ100B www.ti.com
Figure B-52. MSP-TS430PZ100B Target Socket Module, PCB
110 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-28. MSP-TS430PZ100B Bill of Materials
Position Ref Des No. per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
C4, C5,
2 C6 , C7, 6 100nF, SMD0805 311-1245-2-ND
C8, C9
3 C10, C26 2 470 nF, SMD0805 478-1403-2-ND
4 C11, C12 1 10 uF / 6.3 V SMD0805 C12 DNP
C13, C14,
5 C16, C18, 6 4.7 uF SMD0805
C19, C29
6 D1 1 green LED, SMD0805 P516TR-ND
J1, J2, J3, SAM1029-25-ND DNP: Headers and receptacles 7 J4 0 25-pin header, TH (Header) SAM1213-25- enclosed with kit. Keep vias free of ND (Receptacle) solder:
8 J5 1 3-pin header, male, TH
JP3, JP5, place jumpers on pins 2-3 on JP5, 9 JP6, JP7, 7 3-pin header, male, TH SAM1035-03-ND JP6, JP7, JP8, JP9, JP10 place JP8, JP9, jumpers on pins 1-2 on JP3, JP10
10 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header JP4
11 JP11, 3 4-pin header, male, TH place jumper on header 1-2 JP12, JP13
12 13 Jumper 15-38-1024-ND See Pos. 9 and Pos. 10 and Pos. 11
15 JTAG 1 14-pin connector, male, HRP14H-ND TH
16 BOOTST 0 10-pin connector, male, "DNP Keep vias free of solder" TH
17 Q1 0 Crystal DNP: Q1 Keep vias free of solder
21 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2,
22 R4, R6, 2 0 Ohm, SMD0805 541-000ATR-ND DNP: R4, R6, R8, R10, R11 R8, R10,
R11
23 R5 1 47k Ω, SMD0805 541-47000ATR-ND
24 U1 1 Socket: IC357-1004-53N Manuf.: Yamaichi
25 PCB 1 90 x 82 mm 2 layers
Adhesive Approximately 6mm for example, 3M 26 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302
27 MSP430 2 MSP430F6733IPZ DNP: enclosed with kit, supplied by TI
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DNP
DNP
DNP
DNP
DNP
DNP
0R
12pF
12pF
47pF
47pF
GND
0R
100nF
330R
10uF/6.3V
10uF/6.3V
2.2nF
PWR3
GND
GND
GND
0R GND
330R
47K
100nF
100nF
P516TR-ND
470nF
100nF
100nF
0R
0R
0R
0R
GND
VCC
100nF
GND
100nF
100nF
GND
100nF
LL103A
GND
4.7n
HCTC_XTL_4
HCTC_XTL_4
HCTC_XTL_4
HCTC_XTL_4
GND
0R
0R
GND
GND
GND
4.7uF
GND
100nF
220nF
GND
VCC
LL103A
1.1
MSP430: Target-Socket MSP-TS430PZ100C
Socket:
Yamaichi
IC201-1004-008
LFXTCLK
<- SBW
<- JTAG
Vcc
int
ext
DNP
DNP
DNP
DNP
DNP
DNP
BSL-Rx
BSL-Tx
DNP
1
3
5
7
9
11
13
2
4
6
12
14
8
10
JTAG
R2
C2
C1
C3
C4
C5 R1
R3
C6
C7
C8
1
2
3
J5
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
64
63
62
61
44
43
42
41
37
38
39
40
17
18
19
20
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
U1
QFP100PZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
J2
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
J3
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
J4
1 JP1
2
1
JP2
2
R4
1
2
3
JP5 1
2
3
JP6 1
2
3
JP7 1
2
3
JP8 1
2
3
JP9 1
2
3
R7 JP10
R5
C11
C12
D1
C9
C13
C10
R6
R8
R9
R12
1
2
3
JP3
C17
C18
C19
C14
D3
C16
1
2
3
JP11
4
1 2
Q1G$1
3 4
Q1G$2
2 1
Q2G$1
4 3
Q2G$2
1 2
3 4
5 6
7 8
9 10
BOOTST
R10
R11
C15
C20
C21
1 JP4
2
D4
1
2
3
J6
TMS
TMS
TDI
TDI
TDO
TDO
TDO
XOUT
VCC
GND
GND
GND
XIN
P1.0
DVCC1
DVCC1
DVCC1
DVCC1
DVCC1
DVCC1
AVCC
XT2OUT
AVSS
AVSS
AVSS
M
M
I
I
O
O
XT2IN
RST/NMI
RST/NMI
TCK
TCK
TCK
C
C
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
RST
RST
RST
XTLGND2
XTLGND1
PU.0
PU.1
P1.6
P1.7
P8.0
P8.1
P8.2
VBAK
VBAT
VBAT
VBAT
P1.1
P1.1
P1.2
P1.2
LDOI
LDOI
LDOO
LDOO
BSL Interface
LDOI/LDOO Interface
+
+
Note: If the system should be
supplied via LDOI (J6) close JP4
and set JP3 to external
MSP-TS430PZ100C www.ti.com
B.27 MSP-TS430PZ100C
Figure B-53. MSP-TS430PZ100C Target Socket Module, Schematic
112 Hardware SLAU278Q–May 2009–Revised February 2014
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Connector J5
External power connector
Jumper JP3 to "ext"
If the system should
be supplied via LDOI (J6),
close JP4 and
set JP3 to external
Jumper JP2
Open to disconnect LED
D1 LED connected to P1.0
Orient Pin 1 of MSP430 device
Jumpers JP5 to JP10
Close 1-2 to debug in Spy-Bi-Wire
mode
Close 2-3 to debug in 4-wire JTAG
mode
LDOI/LDOO
14
1
2
GND
GND
VCC
1 5 10 1 5 2 25 0
26 30 3540 45 50
75 70 65 60 55 51
100 95 90 85 80 76
1 2 3
123
123
123
123
123
3 2 1
1 2 3 4
10
1
2
1 2 3
1
SBW JTAG
Vcc
int
ext
GND
VBAT
DVCC
JTAG
R2
C2
C1
C3
C4
R1
C5
R3
+
C6
+
C7
C8
J5
U1
J1
J2
J3
J4
JP1
JP2
R4
JP5
JP6
JP7
JP8
JP9
JP10
R7
R5
C11
C12
D1
C9
C13
C10
R6
R8
R9
R12
JP3
C17
C18
C19
C14
D3
C16
JP11
Q1
Q2
BOOTST
R10
R11 C15
C20
C21
JP4
D4
J6
www.ti.com MSP-TS430PZ100C
Figure B-54. MSP-TS430PZ100C Target Socket Module, PCB
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Table B-29. MSP-TS430PZ100C Bill of Materials
Number
Pos. Ref Des Per Description Digi-Key Part No. Comment
Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2
1.1 C3, C4 2 47pF, SMD0805 DNP: C3, C4
2 C6, C7 2 10uF, 6.3V, Tantal Size B 511-1463-2-ND
C5, C11,
3 C13, C14, 6 100nF, SMD0805 311-1245-2-ND
C19, C20
3.1 C10, C12, 0 100nF, SMD0805 311-1245-2-ND DNP: C10, C12,C18, C17 C18,17
4 C8 1 2.2nF, SMD0805 Buerklin 53 D 292
5 C9 1 470nF, SMD0805 478-1403-2-ND
6 D1 1 green LED, SMD0805 P516TR-ND
J1, J2, J3, DNP: headers and receptacles enclosed 7 J4 4 25-pin header, TH SAM1029-25-ND with kit. Keep vias free of solder.
DNP: headers and receptacles enclosed
7.1 4 25-pin header, TH SAM1213-25-ND with kit.
Keep vias free of solder.
8 J5, J6 2 3-pin header, male, TH SAM1035-03-ND
JP5, JP6,
9 JP7, 6 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 2-3 JP8,JP9,
JP10
10 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND place jumper on header
10.1 JP4 1 2-pin header, male, TH SAM1035-02-ND place jumper on header
11 JP3 1 3-pin header, male, TH SAM1035-03-ND place jumper on pins 1-2
12 10 Jumper 15-38-1024-ND Place on: JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP8, JP9, JP10
13 JTAG 1 14-pin connector, male, TH HRP14H-ND
14 BOOTST 1 10-pin connector, male, TH HRP10H-ND DNP, keep vias free of solder
15 Q1 0 Crystal DNP: Q1
Keep vias free of solder
16 Q2 1 Crystal DNP: Q2 Keep vias free of solder
17 R3, R7 2 330 Ohm, SMD0805 541-330ATR-ND
R1, R2, R4,
18 R6, R8, R9, 3 0 Ohm, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11, R12 R10, R11,
R12
19 R5 1 47k Ohm, SMD0805 541-47000ATR-ND
20 U1 1 Socket: IC357-1004-53N Manuf.: Yamaichi
21 PCB 1 79.5 x 99.5 mm MSP-TS430PZ100C 2 layers Rev 1.0
22 Rubber 4 Buerklin: 20H1724 apply to corners at bottom side stand off
23 MSP430 2 MSP430F643x DNP: enclosed with kit. Is supplied by
TI.
24 C16 1 4.7 nF SMD0603 Buerklin 53 D 2042
26 D3, D4 2 LL103A Buerklin: 24S3406
27 JP11 1 4-pin header, male, TH SAM1035-04-ND Place jumper on Pin 1 and Pin 2
28 C15 1 4.7 uF, SMD0805 Buerklin 53 D 2430
29 C21 1 220nF, SMD0805 Buerklin 53 D 2381
114 Hardware SLAU278Q–May 2009–Revised February 2014
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B.28 MSP-TS430PZ5x100
Figure B-55. MSP-TS430PZ5x100 Target Socket Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 115
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Connector J5
External power connector
Jumper J3 to ‘ext’
Jumper JP1
Open to measure current
Jumpers JP5 to JP10
Close 1-2 to debug in
Spy-Bi-Wire mode.
Close 2-3 to debug in
4-wire JTAG mode.
Jumper JP2
Open to disconnect LED
LED connected to P1.0
Jumper JP3
1-2 (int): Power supply via JTAG debug interface
2-3 (ext): External power supply
MSP-TS430PZ5x100 www.ti.com
Figure B-56. MSP-TS430PZ5x100 Target Socket Module, PCB
116 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-30. MSP-TS430PZ5x100 Bill of Materials
Pos. Ref Des No. Per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP
1b C3, C4 47pF, SMD0805 DNP: Only recommendation. Check your crystal spec.
2 C6, C7 2 10uF, 10V, Tantal Size B 511-1463-2-ND
C5, C10,
3 C11, C12, 4 100nF, SMD0805 311-1245-2-ND DNP: C12, C14
C13, C14
4 C8 0 2.2nF, SMD0805 DNP
5 C9 1 470nF, SMD0805 478-1403-2-ND
6 D1 1 green LED, SMD0805 67-1553-1-ND
DNP: headers and
receptacles enclosed with kit.
7 J1, J2, J3, J4 0 25-pin header, TH Keep vias free of solder.
SAM1029-25-ND : Header
SAM1213-25-ND : Receptacle
8 J5 1 3-pin header, male, TH SAM1035-03-ND
JP5, JP6,
9 JP7, JP8, 6 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 2-3
JP9, JP10
10 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header
11 JP3 1 3-pin header, male, TH SAM1035-03-ND Place jumper on pins 1-2
12 9 Jumper 15-38-1024-ND Place on JP1, JP2, JP3, JP5, JP6, JP7, JP8, JP9, JP10
13 JTAG 1 14-pin connector, male, TH HRP14H-ND
14 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder
Q1: Micro Crystal MS1V-T1K DNP: Keep vias free of 15 Q1, Q2 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
16 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R4,
17 R6, R8, R9, 3 0 Ω, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11, R10, R11, R12
R12
18 R5 1 47k Ω, SMD0805 541-47000ATR-ND
19 U1 1 Socket: IC357-1004-53N Manuf.: Yamaichi
20 PCB 1 90 x 82 mm 2 layers
21 Rubber 4 Select appropriate Apply to corners at bottom standoff side
22 MSP430 2 MSP430F5438IPZ DNP: Enclosed with kit supplied by TI
SLAU278Q–May 2009–Revised February 2014 Hardware 117
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MSP-TS430PZ100USB www.ti.com
B.29 MSP-TS430PZ100USB
Due to the use of diodes in the power chain, the voltage on the MSP430F5xx device is approximately
0.3 V lower than is set by the debugging tool. Set the voltage in the IDE to 0.3 V higher than desired; for
example, to run the MCU at 3.0 V, set it to 3.3 V.
Figure B-57. MSP-TS430PZ100USB Target Socket Module, Schematic
118 Hardware SLAU278Q–May 2009–Revised February 2014
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Figure B-58. MSP-TS430PZ100USB Target Socket Module, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 119
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MSP-TS430PZ100USB www.ti.com
Table B-31. MSP-TS430PZ100USB Bill of Materials
Pos. Ref Des No. Per Description DigiKey Part No. Comment Board
1 C1, C2 0 12pF, SMD0805 DNP: C1, C2
1.1 C3, C4 2 47pF, SMD0805
2 C6, C7 2 10uF, 6.3V, Tantal Size B 511-1463-2-ND
C5, C11,
3 C13, C14, 5 100nF, SMD0805 311-1245-2-ND
C19
3.1 C10, C12, 0 100nF, SMD0805 311-1245-2-ND DNP: C10, C12,C18, C17 C18, C17
4 C8 1 2.2nF, SMD0805
5 C9 1 470nF, SMD0805 478-1403-2-ND
6 D1 1 green LED, SMD0805 P516TR-ND
DNP: headers and
receptacles enclosed with kit.
7 J1, J2, J3, J4 4 25-pin header, TH SAM1029-25-ND Keep vias free of solder.
: Header
: Receptacle
DNP: headers and
receptacles enclosed with kit.
7.1 4 25-pin header, TH SAM1213-25-ND Keep vias free of solder.
: Header
: Receptacle
8 J5 1 3-pin header, male, TH SAM1035-03-ND
JP5, JP6,
9 JP7, JP8, 6 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 2-3
JP9, JP10
10 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND place jumper on header JP4
11 JP3 1 3-pin header, male, TH SAM1035-03-ND place jumper on pins 1-2
Place on: JP1, JP2, JP3,
12 10 Jumper 15-38-1024-ND JP4, JP5, JP6, JP7, JP8,
JP9, JP10
13 JTAG 1 14-pin connector, male, TH HRP14H-ND
Micro Crystal MS1V-T1K DNP: Q1. Keep vias free of 14 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF
15 Q2 1 Crystal Q2: 4MHz, Buerklin: 78D134
16 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND
R1, R2, R4,
17 R6, R8, R9, 3 0 Ω, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R12
R12
18 R10 1 100 Ω, SMD0805 Buerklin: 07E500
18 R11 1 1M Ω, SMD0603 not existing in Rev 1.0
18 R5 1 47k Ω, SMD0805 541-47000ATR-ND
19 U1 1 Socket:IC201-1004-008 Manuf.: Yamaichi
20 PCB 1 79 x 77 mm 2 layers
21 Rubber stand 4 Buerklin: 20H1724 apply to corners at bottom off side
22 MSP430 2 MSP430F5529 DNP: enclosed with kit. Is supplied by TI
Insulating http://www.ettinger.de/Art_De 23 disk to Q2 1 Insulating disk to Q2 tail.cfm?ART_ARTNUM=70.0 8.121
24 C16 1 4.7 nF SMD0603
27 C33 1 220n SMD0603 Buerklin: 53D2074
28 C35, C36 2 10p SMD0603 Buerklin: 56D102
120 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-31. MSP-TS430PZ100USB Bill of Materials (continued)
Pos. Ref Des No. Per Description DigiKey Part No. Comment Board
30 C38 1 220n SMD0603 Buerklin: 53D2074
31 C39 1 4u7 SMD0603 Buerklin: 53D2086
32 C40 1 0.1u SMD0603 Buerklin: 53D2068
33 D2, D3, D4 3 LL103A Buerklin: 24S3406
34 IC7 1 TPD4E004 Manu: TI
35 LED 0 JP3QE SAM1032-03-ND DNP
36 LED1, LED2, 0 LEDCHIPLED_0603 FARNELL: 852-9833 DNP LED3
37 R13, R15, 0 470R SMD0603 Buerklin: 07E564 DNP R16
38 R33 1 1k4 / 1k5 SMD0603 Buerklin: 07E612
39 R34 1 27R SMD0603 Buerklin: 07E444
40 R35 1 27R SMD0603 Buerklin: 07E444
41 R36 1 33k SMD0603 Buerklin: 07E740
42 S1, S2, S3 1 PB P12225STB-ND DNP S1 and S2. (Only S3)
43 USB1 1 USB_RECEPTACLE FARNELL: 117-7885
44 JP11 1 4-pin header, male, TH SAM1035-04-ND place jumper only on Pin 1
SLAU278Q–May 2009–Revised February 2014 Hardware 121
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0R
12pF
12pF
GND
GND
0R
100nF
330R
2.2nF
0R
0R
PWR3
GND
330R
47K
0R
0R
100nF
4.7uF
GND
GND
100nF
470nF
0R
QUARZ5
100nF
10uF/6,3V
10uF/6,3V
100nF 4.7uF
4.7uF 100nF
4.7uF
4.7uF
4.7uF
470nF
FE04-1
VCC
GND
GND
100nF
4.7uF
GND
GND
GND
GND
GND
VCC1
VCC1
VCC1
VCC1
VCC1
GND
GND
GND
GND
GND
GND
AVSS
AVSS
DVCC AVCC
GND
VCC
VCC
GND
MSP430: Target-Socket
MSP-TS430PEU128 for F6779
Petersen
1080/1/001/01.1
DNP
LFXTCLK
DNP
<- SBW
<- JTAG
DNP
Vcc
int
ext
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DVDSYS
1.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
J1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
J2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
J3
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
J4
1
3
5
7
9
11
13
2
4
6
12
14
8
10
JTAG
R2
C2
C1
R1
C5
R3
1 2
3 4
5 6
7 8
9 10
BOOTST
C3
R10
R11
J5
1
2
3
1
2
JP1
JP2
1
2
1
2
3
JP5 1
2
3
JP6 1
2
3
JP7 1
2
3
JP8 1
2
3
JP9 1
2
3
JP10
R7
R5
D1
R6
R8
C6
C29
C7
C10
R4
Q1
JP12 1
2
3
4
1
2
3
4
JP11
JP131
2
3
4
C4
C11
C12
C8 C13
C14 C9
C16
C19
C18
C26
1
2
JP4
JP3
1
2
3
4
C15
C17
TP1 TP2
IC1
MSP430F677XIPEU#
XIN
1
XOUT
2
AUXVCC3
3
RTCCAP1
4
RTCCAP0
5
P1.5/SMCLK/CB0/A5
6
P1.4/MCLK/SDCLK/CB1/A4
7
P1.3/ADC10CLK/TACLK/RTCCLK/A3
8
P1.2/ACLK/TA3.1/A2
9
P1.1/TA2.1/VEREF+/A1
10
P1.0/TA1.1/TA0.0/VEREF-/A0
11
P2.4/PM_TA2.0
12
P2.5/PM_UCB0SOMI/PM_UCB0SCL
13
P2.6/PM_USB0SIMO/PM_UCB0SDA
14
P2.7/PM_UCB0CLK
15
P3.0/PM_UCA0RXD/PM_UCA0SOMI
16
P3.1/PM_UCA0TXD/PM_UCA0SIMO
17
P3.2/PM_UCA0CLK
18
P3.3/PM_UCA1CLK
19
P3.4/PM_UCA1RXD/PM_UCA1SOMI
20
P3.5/PM_UCA1TXD/PM_UCA1SIMO
21
COM0
22
COM1
23
P1.6/COM2
24
P1.7/COM3
25
P5.0/COM4
26
P5.1/COM5
27
P5.2/COM6
28
P5.3/COM7
29
LCDCAP/R33
30
P5.4/SDCLK/R23
31
P5.5/SD0DIO/LCDREF/R13
32
P5.6/SD1DIO/R03
33
P5.7/SD2DIO/CB2
34
P6.0/SD3DIO
35
P3.6/PM_UCA2RXD/PM_UCA2SOMI
36
P3.7/PM_UCA2TXD/PM_UCA2SIMO
37
P4.0/PM_UCA2CLK
38
P4.1/PM_UCA3RXD/PM_UCA3SOMI
39
P4.2/PM_UCA3TXD/PM_UCA3SIMO
40
P4.3/PM_UCA3CLK
41
P4.4/PM_UCB1SOMI/PM_UCB1SCL
42
P4.5/PM_UCB1SIMO/PM_UCB1SDA
43
P4.6/PM_UCB1CLK
44
P4.7/PM_TA3.0
45
P6.1/SD4DIO/S39
46
P6.2/SD5DIO/S38
47
P6.3/SD6DIO/S37
48
P6.4/S36
49
P6.5/S35
50
P6.6/S34
51
P6.7/S33
52
P7.0/S32
53
P7.1/S31
54
P7.2/S30
55
P7.3/S29
56
P7.4/S28
57
P7.5/S27
58
P7.6/S26
59
P7.7/S25
60
P8.0/S24
61
P8.1/S23
62
P8.2/S22
63
P8.3/S21
64
P8.4/S20
65
P8.5/S19
66
P8.6/S18
67
P8.7/S17
68
DVSYS
69
DVSS2
70
P9.0/S16
71
P9.1/S15
72
P9.2/S14
73
P9.3/S13
74
P9.4/S12
75
P9.5/S11
76
P9.6/S10
77
P9.7/S9
78
P10.0/S8
79
P10.1/S7
80
P10.2/S6
81
P10.3/S5
82
P10.4/S4
83
P10.5/S3
84
P10.6/S2
85
P10.7/S1
86
P11.0/S0
87
P11.1/TA3.1/CB3
88
P11.2/TA1.1
89
P11.3/TA2.1
90
P11.4/CBOUT
91
P11.5/TACLK/RTCCLK
92
P2.0/PM_TA0.0
93
P2.1/PM_TA0.1
94
P2.2/PM_TA0.2
95
P2.3/PM_TA1.0
96
TEST/SBWTCK
97
PJ.0/TDO
98
PJ.1/TDI/TCLK
99
PJ.2/TMS
100
PJ.3/TCK
101
~RST/NMI/SBWTDIO
102
SD0P0
103
SD0N0
104
SD1P0
105
SD1N0
106
SD2P0
107
SD2N0
108
SD3P0
109
SD3N0
110
VASYS2
111
AVSS2
112
VREF
113
SD4P0
114
SD4N0
115
SD5P0
116
SD5N0
117
SD6P0
118
SD6N0
119
AVSS1
120
AVCC
121
VASYS1
122
AUXVCC2
123
AUXVCC1
124
VDSYS
125
DVCC
126
DVSS1
127
VCORE
128
P1.0 P1.0
P2.0 P2.0
P2.1 P2.1
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
SD3P0
SD3N0
SD4P0
SD4N0
SD5P0
SD5N0
SD6P0
SD6N0
VASYS1/2
VASYS1/2
VASYS1/2
VASYS1/2
TMS
TMS
TDI
TDI
TDO
TDO
TDO
XOUT
GND
GND
XIN
DVCC
AVCC
DVDSYS
DVDSYS
DVDSYS
DVDSYS
AVSS
AVSS
PJ.2
PJ.2
PJ.1
PJ.1
PJ.0
PJ.0
RST/NMI
RST/NMI
TCK
TCK
TCK
PJ.3
PJ.3
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
TEST/SBWTCK
RST
RST
RST
RST
LCDCAP
LCDCAP
VREF
VREF
VEREF+ VEREF+
VCORE
AUXVCC2
AUXVCC2
AUXVCC1
AUXVCC1
AUXVCC3
AUXVCC3
1
2
3
4
5
6
1
2
3
4
5
6
Titel:
Datum:
Bearb.:
Seite 1/1
MSP-TS430PEU128
22.05.2012 09:37:33
A3
A B C D E F G H I
A B C D E F G H I
File:
Dok:
Rev.:
MSP-TS430PEU128 www.ti.com
B.30 MSP-TS430PEU128
Figure B-59. MSP-TS430PEU128 Target Socket Module, Schematic
122 Hardware SLAU278Q–May 2009–Revised February 2014
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1
P1.0
SBW
JTAG
DVDSYS
ext
int
MSP-TS430PEU128
Rev. 1.1 RoHS
DVCC
AUXVCC
GND
AUXVCC1
AUXVCC2
AUXVCC3
GND
GND
RST/NMI
TCK
TDI
TDO
TEST/SBWTCK
TMS
1 25 5 10 15 20 30 35
40 45 50 55 60 64
65 90 70 75 80 85 95 100
128 125 120 115 110 105
14
1
2
10
1
2
GND
GND
VCC
3 2 1
3 2 1
3 2 1
3 2 1
3 2 1
3 2 1
1 2 3 4
1234
1234
1
J1
J2
J3
J4
JTAG
R2
C2
C1
R1
C5
R3
BOOTST
C3
R10 R11
J5
JP1
JP2
JP5
JP6
JP7
JP8
JP9
JP10 R7
R5
D1
R6
R8
C6
C29
C7
C10
R4
JP12
JP11
JP13
C4
C11
C12
C8
C13
C14
C9
C16
C19
C18
C26
JP4
JP3
C15
C17
TP1
TP2
IC1
Connector J5
External power connector
Jumper JP1 to "ext"
Jumper JP1
Open to measure current
Orient Pin 1 of
MSP430 device
Jumpers JP5 to JP10
Close 1-2 to debug in Spy-Bi-Wire mode
Close 2-3 to debug in 4-wire JTAG mode
JP11, JP12, JP13
Connect 1-2 to connect
AUXVCCx with DVCC or
drive AUXVCCx externally
D1 LED connected to P1.0
Jumper JP2
Open to disconnect LED
www.ti.com MSP-TS430PEU128
Figure B-60. MSP-TS430PEU128 Target Socket Module, PCB
NOTE: The MSP-TS430PEU128 Rev 1.1 ships with the following modifications:
• R7 value is changed to 0 Ω instead of 330 Ω.
• JTAG pin 8 is connected only to JP5 pin 3, and not to pin 2.
• JP5 pin 2 is connected to IC1 pin 97.
• BOOTST pin 7 is connected to IC1 pin 97.
SLAU278Q–May 2009–Revised February 2014 Hardware 123
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Table B-32. MSP-TS430PEU128 Bill of Materials
Pos. Ref Des No. Per Description DigiKey Part No. Comment Board
1 PCB 1 94x119.4mm, 4 layers MSP-TS430PEU128 4 layers, green solder mask Rev. 1.1
2 D1 1 green LED, DIODE0805 516-1434-1-ND
3 JP1, JP2, JP4 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header
4 JP5, JP6, JP7, JP8, 6 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 1-2 (SBW) JP9, JP10
5 JP11, JP12, JP13 3 4-pin header, male, TH SAM1035-04-ND Place jumpers on pins 1-2 (AVCC=VCC)
6 JP3 1 4-pin header, male, TH SAM1035-04-ND Place jumpers on pins 1-2
JP1, JP2, JP3, JP4, Jumper WM4592-ND
7 JP5, JP6, JP7, JP8, 13 JP9, JP10, JP11,
JP12, JP13
8 R1, R2, R4, R6, R8 5 0R, 0805 541-0.0ATR-ND
9 R10, R11 2 0R, 0805 541-0.0ATR-ND DNP
10 C3 1 2.2nF, CSMD0805 490-1628-2-ND DNP
11 C13, C14, C16, 7 4.7uF, 6.3V, CSMD0805 587-1302-2-ND C17, C18, C19, C29
12 C11 1 10uF, 6.3V, CSMD0805 445-1372-2-ND
13 C12 1 10uF, 6.3V, CSMD0805 445-1372-2-ND DNP
14 C1, C2 2 12pF, CSMD0805 490-5531-2-ND DNP
15 R5 1 47K, 0805 311-47KARTR-ND
16 C4, C5, C6, C7, C8, 6 100nF, CSMD0805 311-1245-2-ND C15
17 C9 1 100nF, CSMD0805 311-1245-2-ND DNP
18 R3, R7 2 330R, 0805 541-330ATR-ND
19 C10, C26 2 470nF, CSMD0805 587-1282-2-ND
20 BOOTST 1 10-pin connector, male, TH HRP10H-ND DNP, keep vias free of solder
21 JTAG 1 14-pin connector, male, TH HRP14H-ND
22 IC1 Socket 1 Socket: IC500-1284-009P Manuf. Yamaichi
23 IC1 2 MSP430F67791IPEU DNP: enclosed with kit. Is supplied by TI
24 J5 1 3-pin header, male, TH SAM1035-03-ND
25 Q1 1 Crystal: MS3V-T1R 32.768kHz DNP: Crystal enclosed with kit. Keep vias 12.5pF ±20ppm free of solder
26 TP1, TP2 2 Test point DNP, keep vias free of solder
27 J2,J4 2 26-pin header, TH SAM1029-26-ND DNP: Headers enclosed with kit. Keep vias free of solder.
28 J2,J4 2 26-pin receptable, TH SAM1213-26-ND DNP: Receptacles enclosed with kit. Keep vias free of solder.
29 J1, J3 2 38-pin header, TH SAM1029-38-ND DNP: Headers enclosed with kit. Keep vias free of solder.
30 J1, J3 2 38-pin receptable, TH SAM1213-38-ND DNP: Receptacles enclosed with kit. Keep vias free of solder.
31 Rubber feet 4 Rubber feet Buerklin: 20H1724 apply to bottom side corners
124 Hardware SLAU278Q–May 2009–Revised February 2014
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Power Management
VCC01 = external VCC
Vdd = DVCC
Vdda1 = AVDD_RF / AVCC_RF
Vdda2 = AVCC
Port connectors
CON1 ..
CON3 = Port1 .. Port3 of cc430
CON4 = spare
CON5 = 1: XIN 2: XOUT
CON6 = Vdd, GND, Vcore,
COM0, LCDCAP
CON7 = Vdda1, Vdda2, GND,
AGND
CON8 = JTAG_BASE
(JTAG Port)
CON9 = Vdd, GND, AGND
(May be addedclose
to therespective pins
to reduce emissions
at 5GHz toel vel
required byETSI)
www.ti.com EM430F5137RF900
B.31 EM430F5137RF900
Figure B-61. EM430F5137RF900 Target board, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 125
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JTAG connector
External power connector
CON12
GND
GND
VCC
Open to disconnect LEDs
jumper JP5/JP10
LED D2 (red) connected to
P3.6 via JP10
LED D1 (green) connected
to P1.0 via JP5
RF - Crystal Q1 26 MHz
RF - Signal SMA
Reset button S1
Push-button S2
connected to P1.7
Jumper JP1
Close JTAG
position to
debug in
JTAG mode
Jumper JP2
Close EXT for external supply
Close INT for JTAG supply
Close SBW position
to debug in
Spy-Bi-Wire mode
Jumper JP1
Spy-Bi-Wire mode
Footprint for 32kHz crystal
Use 0 resistor for R431/R441
to make XIN/XOUT available
on connector port5
!
Open to measure current
jumper JP3
EM430F5137RF900 www.ti.com
Figure B-62. EM430F5137RF900 Target board, PCB
The battery pack that is included with the EM430F5137RF900 kit may be connected to CON12. Ensure
correct battery insertion regarding the polarity as indicated in battery holder.
126 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-33. EM430F5137RF900 Bill of Materials
Item Reference No. per Description Value Manufacturer's Part Manufacturer Comment Board Number
1 Q1 1 ( CUSTOMER SUPPLY ) CRYSTAL, 26M ASX-531(CS) AKER SMT, 4P, 26MHz ELECTRONIC
C1-C5, C082,
C222, C271, CAPACITOR, SMT, 0402, CER, 16V, 2 C281, C311, 14 10%, 0.1uF 0.1uF 0402YC104KAT2A AVX C321, C341,
C412, C452
3 C071 1 CAPACITOR, SMT, 0603, CERAMIC, 0.47uF 0603YD474KAT2A AVX 0.47uF, 16V, 10%, X5R
4 R401 1 RES0402, 47.0K 47kΩ CRCW04024702F10 DALE 0
5 CON11 1 HEADER, THU, MALE, 14P, 2X7, 09 18 514 6323 HARTING 25.4x9.2x9.45mm
6 CON10 0 HEADER, THU, MALE, 10P, 2X5, 09 18 510 6323 HARTING DNP 20.32x9.2x9.45mm
7 D1 1 LED, SMT, 0603, GREEN, 2.1V active APT1608MGC KINGBRIGHT
8 D2 1 LED, SMT, 0603, RED, 2.0V active APT1608EC KINGBRIGHT
9 Q3 0 UNINSTALLED CRYSTAL, SMT, 3P, 32.768k MS1V-T1K (UN) MICRO DNP MS1V (Customer Supply) CRYSTAL
10 CON12 1 HEADER, THU, MALE, 3P, 1x3, 22-03-5035 MOLEX 9.9x4.9x5.9mm
11 C251, C261 2 50V, 5%, 27pF 27pF GRM36COG270J50 MURATA
12 L341 1 FERRITE, SMT, 0402, 1.0kΩ, 250mA 1kΩ BLM15HG102SN1D MURATA
13 C293 1 CAPACITOR, SMT, 0402, CERAMIC, 100pF GRM1555C1H101JZ MURATA 100pF, 50V, 0.25pF, C0G(NP0) 01
14 L304 1 INDUCTOR, SMT, 0402, 2.2nH, 0.1nH, 0.0022uH LQP15MN2N2B02 MURATA 220mA, 500MHz
15 L303, L305 2 INDUCTOR, SMT, 0402, 15nH, 2%, 0.015uH LQW15AN15NG00 MURATA 450mA, 250MHz
16 L292, L302 2 INDUCTOR, SMT, 0402, 18nH, 2%, 0.018uH LQW15AN18NG00 MURATA 370mA, 250MHz
17 C291 1 CAPACITOR, SMT, 0402, CERAMIC, 1pF GRM1555C1H1R0W MURATA 1pF, 50V, 0.05pF, C0G(NP0) Z01
18 C303 1 CAPACITOR, SMT, 0402, CERAMIC, 8.2pF GRM1555C1H8R2W MURATA 8.2pF, 50V, 0.05pF, C0G(NP0) Z01
19 C292, C301- 4 CAPACITOR, SMT, 0402, CERAMIC, 1.5pF GRM1555C1H1R5W MURATA C302, C304 1.5pF, 50V, 0.05pF, C0G(NP0) Z01
20 L291, L301 2 INDUCTOR, SMT, 0402, 12nH, 2%, 0.012uH LQW15AN12NG00 MURATA 500mA, 250MHz
C282, C312, CAPACITOR, SMT, 0402, CERAMIC, GRM1555C1H2R0B 21 C351, C361, 5 2pF, 50V, 0.1pF, C0G 2.0pF Z01 Murata C371
22 L1 1 INDUCTOR, SMT, 0402, 6.2nH, 0.1nH, 6.2nH LQP15MN6N2B02 Murata 130mA, 500MHz
23 S1-S2 2 ULTRA-SMALL TACTILE SWITCH, SMT, B3U-1000P OMRON 2P, SPST-NO, 1.2x3x2.5mm, 0.05A, 12V
R4-R5, R051, UNINSTALLED RESISTOR/JUMPER, 24 R061, R431, 0 SMT, 0402, 0 Ω, 5%, 1/16W 0Ω ERJ-2GE0R00X PANASONIC DNP R441
24a R7 1 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 0Ω ERJ-2GE0R00X PANASONIC 5%, 1/16W
25 R2-R3, R6 3 RESISTOR, SMT, 0402, THICK FILM, 330Ω ERJ-2GEJ331 PANASONIC 5%, 1/16W, 330
26 C431, C441 0 CAPACITOR, SMT, 0402, CER, 12pF, 12pF ECJ-0EC1H120J PANASONIC 50V, 5%, NPO
27 C401 1 CAPACITOR, SMT, 0402, CER, 2200pF, 0.0022uF ECJ-0EB1H222K PANASONIC 50V, 10%, X7R
28 R331 1 RESISTOR, SMT, THICK FILM, 56K, 56kΩ ERJ-2GEJ563 PANASONIC 1/16W, 5%
29 C081, C221, 4 CAPACITOR, SMT, 0603, CERAMIC, 10uF ECJ-1VB0J106M PANASONIC C411, C451 10uF, 6.3V, 20%, X5R
SLAU278Q–May 2009–Revised February 2014 Hardware 127
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Table B-33. EM430F5137RF900 Bill of Materials (continued)
Item Reference No. per Description Value Manufacturer's Part Manufacturer Comment Board Number
30 R1 1 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 0Ω ERJ-2GE0R00X PANASONIC 5%, 1/16W
31 C041 0 UNINSTALLED CAP CERAMIC 4.7UF 4.7uF ECJ-1VB0J475K Panasonic DNP 6.3V X5R 0603
32 X1 1 SMA STRIGHT JACK, SMT 32K10A-40ML5 ROSENBERGER
33 Q2 0 Crystal, SMT, 32.768 kHz 32.768k MS3V-T1R Micro Crystal DNP
34 U1 1 DUT, SMT, PQFP, RGZ-48, 0.5mmLS, CC430F52x1 TI 7.15x7.15x1mm, THRM.PAD
35 JP1 1 Pin Connector 2x4pin 61300821121 WUERTH
36 CON1-CON9 0 Pin Connector 2x4pin 61300821121 WUERTH DNP
37 JP2 1 Pin Connector 1x3pin 61300311121 WUERTH
38 JP3, JP5, 3 Pin Connector 1x2pin 61300211121 WUERTH JP10
38a JP7, CON13 0 Pin Connector 1x2pin 61300211121 WUERTH DNP
39 JP4 1 Pin Connector 2x2pin 61300421121 WUERTH DNP
40 JP1a 1 Pin Connector 2x3pin 61300621121 WUERTH
128 Hardware SLAU278Q–May 2009–Revised February 2014
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Power Management
VCC01 = external VCC
Vdd = DVCC
Vdda1 = AVDD_RF / AVCC_RF
Vdda2 = AVCC
Port connectors
CON1 ..
CON5 = Port1 .. Port5 of cc430
CON6 = Vdd, GND, Vcore,
COM0, LCDCAP
CON7 = Vdda1, Vdda2, GND,
AGND
CON8 = JTAG_BASE
(JTAG Port)
CON9 = Vdd, GND, AGND
(May beaddedcol se
to therespective pins
to reduce emissions
at 5GHz to el vel
required by ETSI)
www.ti.com EM430F6137RF900
B.32 EM430F6137RF900
Figure B-63. EM430F6137RF900 Target board, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 129
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JTAG connector
External power connector
CON12
GND
GND
VCC
Open to disconnect LEDs
jumper JP5/JP10
LED D2 (red) connected to
P3.6 via JP10
LED D1 (green) connected
to P1.0 via JP5
RF - Crystal Q1 26 MHz
RF - Signal SMA
Reset button S1
Push-button S2
connected to P1.7
Jumper JP1
Close JTAG
position to
debug in
JTAG mode
Jumper JP2
Close EXT for external supply
Close INT for JTAG supply
Close SBW position
to debug in
Spy-Bi-Wire mode
Jumper JP1
Spy-Bi-Wire mode
Footprint for 32kHz crystal
Use 0 resistor for R541/R551
to makeP5.0/P5.1 available
on connector port5
!
Open to measure current
jumper JP3
C392
C422
L451
EM430F6137RF900 www.ti.com
Figure B-64. EM430F6137RF900 Target board, PCB
The battery pack that is included with the EM430F6137RF900 kit may be connected to CON12. Ensure
correct battery insertion regarding the polarity as indicated in battery holder.
130 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-34. EM430F6137RF900 Bill of Materials
No.
Pos. Ref Des per Description Part No. Manufacturer
Board
1 Q1 1 ( CUSTOMER SUPPLY ) CRYSTAL, SMT, ASX-531(CS) AKER 4P, 26MHz ELECTRONIC
C1-C5, C112,
C252, C381, CAPACITOR, SMT, 0402, CER, 16V, 10%, 2 C391, C421, 14 0.1uF 0402YC104KAT2A AVX C431, C451,
C522, C562
3 C101 1 CAPACITOR, SMT, 0603, CERAMIC, 0.47uF, 0603YD474KAT2A AVX 16V, 10%, X5R
4 R511 1 RES0402, 47.0K CRCW04024702F100 DALE
5 CON11 1 HEADER, THU, MALE, 14P, 2X7, 09 18 514 6323 HARTING 25.4x9.2x9.45mm, 90deg
7 D1 1 LED, SMT, 0603, GREEN, 2.1V APT1608MGC KINGBRIGHT
8 D2 1 LED, SMT, 0603, RED, 2.0V APT1608EC KINGBRIGHT
10 CON12 1 HEADER, THU, MALE, 3P, 1x3, 22-03-5035 MOLEX 9.9x4.9x5.9mm
11 C361, C371 2 50V, ±5%, 27pF GRM36COG270J50 MURATA
12 L451 1 FERRITE, SMT, 0402, 1.0kΩ, 250mA BLM15HG102SN1D MURATA
13 C403 1 CAPACITOR, SMT, 0402, CERAMIC, 100pF, GRM1555C1H101JZ01 MURATA 50V, ±0.25pF, C0G(NP0)
14 L414 1 INDUCTOR, SMT, 0402, 2.2nH, ±0.2nH, LQW15AN2N2C10 MURATA 1000mA, 250MHz
15 L413, L415 2 INDUCTOR, SMT, 0402, 15nH, ±5%, 460mA, LQW15AN15NJ00 MURATA 250MHz
16 L402, L412 2 INDUCTOR, SMT, 0402, 18nH, ±5%, 370mA, LQW15AN18NJ00 MURATA 250MHz
17 C401 1 CAPACITOR, SMT, 0402, CER, 1pF, 50V, GJM1555C1H1R0CB01D MURATA ±0.25pF, NP0
18 C413 1 CAPACITOR, SMT, 0402, CERAMIC, 8.2pF, GRM1555C1H8R2CZ01 MURATA 50V, ±0.25pF, C0G(NP0)
19 C402, C411- 4 CAPACITOR, SMT, 0402, CERAMIC, 1.5pF, GRM1555C1H1R5CZ01 MURATA C412, C414 50V, ±0.25pF, C0G(NP0)
20 L401, L411 2 INDUCTOR, SMT, 0402, 12nH, ±5%, 500mA, LQW15AN12NJ00 MURATA 250MHz
21 C46-C48, 5 CAPACITOR, SMT, 0402, CERAMIC, 2.0pF, GRM1555C1H2R0CZ01 Murata C392, C422 50V, ±0.25pF, C0G(NP0)
22 L1 1 INDUCTOR, SMT, 0402, 6.2nH, ±0.1nH, LQW15AN6N2D00 Murata 700mA, 250MHz
23 S1-S2 2 ULTRA-SMALL TACTILE SWITCH, SMT, 2P, B3U-1000P OMRON SPST-NO, 1.2x3x2.5mm, 0.05A, 12V
24 R7 1 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 5%, ERJ-2GE0R00X (UN) PANASONIC 1/16W
25 R2-R3, R6 3 RESISTOR, SMT, 0402, THICK FILM, 5%, ERJ-2GEJ331 PANASONIC 1/16W, 330
27 C511 1 CAPACITOR, SMT, 0402, CER, 2200pF, ECJ-0EB1H222K PANASONIC 50V, 10%, X7R
28 C111, C251, 4 CAPACITOR, SMT, 0603, CERAMIC, 10uF, ECJ-1VB0J106M PANASONIC C521, C561 6.3V, 20%, X5R
28a C041 1 CAP CERAMIC 4.7UF 6.3V X5R 0603 ECJ-1VB0J475M PANASONIC
29 R441 1 RESISTOR, SMT, THICK FILM, 56K, 1/16W, ERJ-2RKF5602 PANASONIC 1%
30 R1 1 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 5%, ERJ-2GE0R00X PANASONIC 1/16W
31 X1 1 SMA STRIGHT JACK, SMT 32K10A-40ML5 ROSENBERGER
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Table B-34. EM430F6137RF900 Bill of Materials (continued)
No.
Pos. Ref Des per Description Part No. Manufacturer
Board
33 U1 1 DUT, SMT, PQFP, RGC-64, 0.5mmLS, CC430F6137 TI 9.15x9.15x1mm, THRM.PAD
34 JP1 1 Pin Connector 2x4pin 61300821121 WUERTH
35 JP2 1 Pin Connector 1x3pin 61300311121 WUERTH
36a JP3, JP5, JP10 3 Pin Connector 1x2pin 61300211121 WUERTH
38 JP1a 1 Pin Connector 2x3pin 61300621121 WUERTH
132 Hardware SLAU278Q–May 2009–Revised February 2014
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B.33 EM430F6147RF900
Figure B-65. EM430F6147RF900 Target Board, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 133
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Figure B-66. EM430F6147RF900 Target Board, PCB
The battery pack which comes with the EM430F6147RF900 kit may be connected to CON12. Ensure
correct battery insertion regarding the polarity as indicated in battery holder.
134 Hardware SLAU278Q–May 2009–Revised February 2014
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Table B-35. EM430F6147RF900 Bill of Materials
No.
Pos. Ref Des per Description Part No. Manufacturer
Board
1 Q1 1 ( CUSTOMER SUPPLY ) CRYSTAL, SMT, ASX-531(CS) AKER 4P, 26MHz ELECTRONIC
C1-5 C112
C252 C381 CAPACITOR, SMT, 0402, CER, 16V, 10%, 2 C391 C421 14 0.1uF 0402YC104KAT2A AVX C431 C451
C522 C562
3 C101 1 CAPACITOR, SMT, 0603, CERAMIC, 0.47uF, 0603YD474KAT2A AVX 16V, 10%, X5R
4 R511 1 RES0402, 47.0K CRCW04024702F100 DALE
5 CON11 1 HEADER, THU, MALE, 14P, 2X7, 09 18 514 6323 HARTING 25.4x9.2x9.45mm, 90deg
7 D1 1 LED, SMT, 0603, GREEN, 2.1V APT1608MGC KINGBRIGHT
8 D2 1 LED, SMT, 0603, RED, 2.0V APT1608EC KINGBRIGHT
10 CON12 1 HEADER, THU, MALE, 3P, 1x3, 22-03-5035 MOLEX 9.9x4.9x5.9mm
11 C361, C371 2 50V, ±5%, 27pF GRM36COG270J50 MURATA
12 L451 1 Inductor, SMD, 0402, 12nH, 5%, 370mA LQW15AN12NJ00 MURATA
13 C403 1 CAPACITOR, SMT, 0402, CERAMIC, 100pF, GRM1555C1H101JZ01 MURATA 50V, ±0.25pF, C0G(NP0)
14 L414 1 INDUCTOR, SMT, 0402, 2.2nH, ±0.2nH, LQW15AN2N2C10 MURATA 1000mA, 250MHz
15 L413 1 Inductor, SMD, 0402, 15nH, 5%, 370mA, LQW15AN15NJ00 MURATA 250MHz
15 L415 1 INDUCTOR,SMT,0402,15nH,±5%,460mA,250 LQW15AN15NJ00 MURATA MHz
16 L402, L412 2 Inductor, SMD, 0402, 18nH, 5%, 460mA, LQW15AN18NJ00 MURATA 250MHz
17 C401 1 CAPACITOR, SMT, 0402, CER, 1pF, 50V, GJM1555C1H1R0CB01D MURATA ±0.25pF, NP0
18 C413 1 CAPACITOR, SMT, 0402, CERAMIC, 8.2pF, GRM1555C1H8R2CZ01 MURATA 50V, ±0.25pF, C0G(NP0)
19 C402, C411- 4 CAPACITOR, SMT, 0402, CERAMIC, 1.5pF, GRM1555C1H1R5CZ01 MURATA C412, C414 50V, ±0.25pF, C0G(NP0)
20 L1, L401, L411 3 INDUCTOR, SMT, 0402, 12nH, ±5%, 500mA, LQW15AN12NJ00 MURATA 250MHz
21 C46-C48, 4 CAPACITOR, SMT, 0402, CERAMIC, 2.0pF, GRM1555C1H2R0CZ01 MURATA C392 50V, ±0.25pF, C0G(NP0)
22 L2 1 Inductor, SMD, 0805, 2.2uH, 20%, 600mA, LQM21PN2R2MC0 MURATA 50MHz
23 S1-S2 2 ULTRA-SMALL TACTILE SWITCH, SMT, 2P, B3U-1000P OMRON SPST-NO, 1.2x3x2.5mm, 0.05A, 12V
24 R1, R7, R551, 4 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 5%, ERJ-2GE0R00X (UN) PANASONIC R554 1/16W
25 R2-R3, R6 3 RESISTOR, SMT, 0402, THICK FILM, 5%, ERJ-2GEJ331 PANASONIC 1/16W, 330
27 C511 1 CAPACITOR, SMT, 0402, CER, 2200pF, ECJ-0EB1H222K PANASONIC 50V, 10%, X7R
28 C111, C251, 4 CAPACITOR, SMT, 0603, CERAMIC, 1uF, ECJ-1VB0J105K PANASONIC C521, C561 6.3V, 20%, X5R
28a C041 1 CAP CERAMIC 4.7UF 6.3V X5R 0603 ECJ-1VB0J475M PANASONIC
29 R441 1 RESISTOR, SMT, THICK FILM, 56K, 1/16W, ERJ-2RKF5602 PANASONIC 1%
30 X1 1 SMA STRIGHT JACK, SMT 32K10A-40ML5 ROSENBERGER
SLAU278Q–May 2009–Revised February 2014 Hardware 135
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Table B-35. EM430F6147RF900 Bill of Materials (continued)
No.
Pos. Ref Des per Description Part No. Manufacturer
Board
31 U1 1 DUT, SMT, PQFP, RGC-64, 0.5mmLS, CC430F6147 TI 9.15x9.15x1mm, THRM.PAD
33 U2 1 IC, Step Down Converter with Bypass Mode TPS62370 TI for Low Power Wireless
34 JP1 1 Pin Connector 2x4pin 61300821121 WUERTH
35 JP2, JP6, JP8 3 Pin Connector 1x3pin 61300311121 WUERTH
36a JP3, JP5, JP9, 4 Pin Connector 1x2pin 61300211121 WUERTH JP10
38 JP1a 1 Pin Connector 2x3pin 61300621121 WUERTH
38 C7 1 Capacitor, Ceramic, 1206, 16V, X5R, 20% GRM31CR61C226ME15L MURATA
38 C8-9 2 CAP, SMD, Ceramic, 0402, 2.2uF, X5R GRM155R60J225ME15D MURATA
38 C041 1 CAP, SMD, Ceramic, 0603, 4.7uF, 16V, 10%, MURATA X5R
136 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-FET430PIF
B.34 MSP-FET430PIF
Figure B-67. MSP-FET430PIF FET Interface Module, Schematic
SLAU278Q–May 2009–Revised February 2014 Hardware 137
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MSP-FET430PIF www.ti.com
Figure B-68. MSP-FET430PIF FET Interface Module, PCB
138 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-FET430UIF
B.35 MSP-FET430UIF
Figure B-69. MSP-FET430UIF USB Interface, Schematic (1 of 4)
SLAU278Q–May 2009–Revised February 2014 Hardware 139
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MSP-FET430UIF www.ti.com
Figure B-70. MSP-FET430UIF USB Interface, Schematic (2 of 4)
140 Hardware SLAU278Q–May 2009–Revised February 2014
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www.ti.com MSP-FET430UIF
Figure B-71. MSP-FET430UIF USB Interface, Schematic (3 of 4)
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Figure B-72. MSP-FET430UIF USB Interface, Schematic (4 of 4)
142 Hardware SLAU278Q–May 2009–Revised February 2014
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Figure B-73. MSP-FET430UIF USB Interface, PCB
SLAU278Q–May 2009–Revised February 2014 Hardware 143
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MSP-FET430UIF www.ti.com
B.35.1 MSP-FET430UIF Revision History
Revision 1.3
• Initial released hardware version
Assembly change on 1.3 (May 2005)
• R29, R51, R42, R21, R22, R74: value changed from 330R to 100R
Changes 1.3 to 1.4 (Aug 2005)
• J5: VBUS and RESET additionally connected
• R29, R51, R42, R21, R22, R74: value changed from 330R to 100R
• U1, U7: F1612 can reset TUSB3410; R44 = 0R added
• TARGET-CON.: pins 6, 10, 12, 13, 14 disconnected from GND
• Firmware-upgrade option through BSL: R49, R52, R53, R54 added; R49, R52 are currently DNP
• Pullups on TCK and TMS: R78, R79 added
• U2: Changed from SN74LVC1G125DBV to SN74LVC1G07DBV
NOTE: Using a locally powered target board with hardware revision 1.4
Using an MSP-FET430UIF interface hardware revision 1.4 with populated R62 in conjunction
with a locally powered target board is not possible. In this case, the target device RESET
signal is pulled down by the FET tool. It is recommended to remove R62 to eliminate this
restriction. This component is located close to the 14-pin connector on the MSP-FET430UIF
PCB. See the schematic and PCB drawings in this document for the exact location of this
component.
Assembly change on 1.4a (January 2006)
• R62: not populated
144 Hardware SLAU278Q–May 2009–Revised February 2014
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Appendix C
SLAU278Q–May 2009–Revised February 2014
Hardware Installation Guide
This section describes the hardware installation process of the following USB debug interfaces on a PC
running Windows XP:
• MSP-FET430UIF
• eZ430-F2013
• eZ430-RF2500
• eZ430-Chronos
• eZ430-RF2780
• eZ430-RF2560
• MSP-WDSxx "Metawatch"
• LaunchPad (MSP-EXP430G2)
• MSP-EXP430FR5739
• MSP-EXP430F5529
The installation procedure for other supported versions of Windows is very similar and, therefore, not
shown here.
Topic ........................................................................................................................... Page
C.1 Hardware Installation ....................................................................................... 146
SLAU278Q–May 2009–Revised February 2014 Hardware Installation Guide 145
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C.1 Hardware Installation
Table C-1 shows the USB VIDs and PIDs used in MSP430 tools.
Table C-1. USB VIDs and PIDs Used in MSP430 Tools
Tool USB VID USB PID INF File Name
eZ430-F2013 0x0451 0xF430 usbuart3410.inf
eZ430-RF2500 0x0451 0xF432 430CDC.inf
eZ430-RF2780 0x0451 0xF432 430CDC.inf
eZ430-RF2560 0x0451 0xF432 430CDC.inf
MSP-WDSxx "Metawatch" 0x0451 0xF432 430CDC.inf
eZ430-Chronos 0x0451 0xF432 430CDC.inf
MSP-FET430UIF(1) 0x2047 0x0010 msp430tools.inf
LaunchPad (MSP-EXP430G2) 0x0451 0xF432 430CDC.inf
MSP-EXP430FR5739 0x0451 0xF432 430CDC.inf
MSP-EXP430F5529 0x0451 0xF432 430CDC.inf
(1) The older MSP-FET430UIF used with IAR versions before v5.20.x and CCS versions before v5.1 has VID 0x0451 and PID
0xF430. With the firmware update, it is updated to the 0x2047 and 0x0010, respectively.
1. Before connecting of the USB Debug Interface with a USB cable to a USB port of the PC the one of
IDEs (CCS or IAR) should be installed. The IDE installation isntalls also drivers for USB Debug
Interfaces without user interaction. After IDE installation the USB Debug Interface can be connected
and will be ready to work within few seconds.
2. The driver can be also installed manually. After plug in the USB Debug Interface to USB port of the PC
the Hardware Wizard starts automatically and opens the "Found New Hardware Wizard" window.
3. Select "Install from a list or specific location (Advanced)" (see Figure C-1).
Figure C-1. Windows XP Hardware Wizard
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4. Browse to the folder where the driver information files are located (see Figure C-2).
For CCS, the default folder is: c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_CDC, or
c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_FET_XP_XX, or
c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_eZ-RF depending of firmware version of the tool.
For IAR Embedded Workbench, the default folder is: \Embedded Workbench x.x\
430\drivers\TIUSBFET\eZ430-UART, or
\Embedded Workbench x.x\ 430\drivers\.
Figure C-2. Windows XP Driver Location Selection Folder
5. The Wizard generates a message that an appropriate driver has been found.
SLAU278Q–May 2009–Revised February 2014 Hardware Installation Guide 147
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6. The wizard installs the driver files.
7. The wizard shows a message that it has finished the installation of the software USB Debug Interface.
8. The USB debug interface is installed and ready to use. The Device Manager lists a new entry as
shown in Figure C-3, Figure C-4, or Figure C-5.
Figure C-3. Device Manager Using USB Debug Interface using VID/PID 0x2047/0x0010
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Figure C-4. Device Manager Using USB Debug Interface with VID/PID 0x0451/0xF430
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Figure C-5. Device Manager Using USB Debug Interface with VID/PID 0x0451/0xF432
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www.ti.com Document Revision History
Document Revision History
Version Changes
SLAU278 Initial release
SLAU278A Updated USB driver installation according to CCE v3.1 SR1 and CCS v4.
SLAU278B Added information about MSP-FET430U80USB, MSP-TS430PN80USB, and eZ430-Chronos.
SLAU278C Added bills of materials and updated some PCBs in Appendix B.
Added information about MSP-TS430DA38, MSP-TS430DL48, MSP-TS430PW14, MSP-TS430PW28.
SLAU278D Added information about MSP-TS430L092, MSP-TS430RSB40, MSP-TS430RGC64USB, MSP-TS430PZ100USB, MSPFET430F5137RF900
SLAU278E Added jumper information for MSP-TS430L092 PCBs to Appendix B.
Added new supported devices in Chapter 1.
Added information about MSP-TS430PW24, MSP-TS430PW28A, MSP-TS430RHA40A, MSP-TS430RGZ48B, MSPSLAU278F
TS430RGC64B, MSP-TS430PN80A, and MSP-TS430PZ100B.
Updated MSP-TS430RSB40 schematics
SLAU278G Added information for MSP-TS430PZ100C
SLAU278H Added information for MSP-TS430D8 and MSP-TS430RGC64C
Updated Table 1-1.
Replaced Figure 2-2.
SLAU278I Added Figure 2-3.
Replaced Figure B-37 and Figure B-67.
Added Table C-1.
Editorial changes throughout.
SLAU278J Added EM430F6147RF900 Section B.33.
Added battery pack connection information to all EM430Fx1x7RF900 kits.
SLAU278K Added information for MSP-TS430RGZ48C and MSP-TS430PEU128.
Updated Figure B-38.
SLAU278L Changed descriptions in Section B.19 and Section B.30.
Changed Figure B-60.
SLAU278M Added information for MSP430G2x44 and MSP430G2x55 in Table 1-2.
SLAU278N Updated Table 1-1.
Updated Section 2.3.
Changed Table 1-1 and Table 1-2 for MSP430TCH5E.
Changed Figure 2-1 through Figure 2-3.
SLAU278O
Changed FAQ 12 in Section A.1.
Changed Figure B-47, Figure B-49, and Figure B-69 through Figure B-73.
Added information about F523x, F524x, and F525x to Table 1-2 and Section B.19.
SLAU278P Changed Figure B-38.
Added BSL information to note on Figure B-41.
Figure B-15, Corrected JTAG mode selection jumpers (J4 to J7).
SLAU278Q Section B.19, In last sentence, corrected jumper (JP4).
Removed "RF Emission Testing" section.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SLAU278Q–May 2009–Revised February 2014 Revision History 151
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User’s Guide
SWRU321A – May 2013
SmartRF™ is a trademark of Texas Instruments
SmartRF06 Evaluation Board
User’s Guide
User’s Guide
SWRU321A – May 2013
Page 3/32
Table of Contents
4.1 INSTALLING SMARTRF STUDIO AND USB DRIVERS ................................................................ 7
4.1.1 SmartRF Studio ................................................................................................................. 7
4.1.2 FTDI USB driver ................................................................................................................ 7
5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 11
6.1 XDS100V3 EMULATOR ...................................................................................................... 13
6.1.1 UART back channel ........................................................................................................ 14
6.2 POWER SOURCES ............................................................................................................. 14
6.2.1 USB Power ...................................................................................................................... 15
6.2.2 Battery Power .................................................................................................................. 15
6.2.3 External Power Supply .................................................................................................... 16
6.3 POWER DOMAINS .............................................................................................................. 17
6.3.1 XDS Domain ................................................................................................................... 17
6.3.2 EM Domain...................................................................................................................... 17
6.3.3 3.3 V Domain .................................................................................................................. 18
6.4 LCD ................................................................................................................................. 18
6.5 MICRO SD CARD SLOT ...................................................................................................... 19
6.6 ACCELEROMETER .............................................................................................................. 19
6.7 AMBIENT LIGHT SENSOR .................................................................................................... 20
6.8 BUTTONS .......................................................................................................................... 20
6.9 LEDS ............................................................................................................................... 21
6.9.1 General Purpose LEDs ................................................................................................... 21
6.9.2 XDS100v3 Emulator LEDs .............................................................................................. 21
6.10 EM CONNECTORS ............................................................................................................. 21
6.11 BREAKOUT HEADERS AND JUMPERS ................................................................................... 23
6.11.1 I/O Breakout Headers ..................................................................................................... 23
6.11.2 XDS100v3 Emulator Bypass Headers ............................................................................ 24
6.11.3 20-pin ARM JTAG Header .............................................................................................. 25
6.11.4 10-pin ARM Cortex Debug Header ................................................................................. 26
6.12 CURRENT MEASUREMENT .................................................................................................. 27
6.12.1 High-side current sensing ............................................................................................... 27
6.12.2 Current Measurement Jumper ........................................................................................ 27
7.1 20-PIN ARM JTAG HEADER .............................................................................................. 29
7.2 10-PIN ARM CORTEX DEBUG HEADER ............................................................................... 29
7.3 CUSTOM STRAPPING ......................................................................................................... 30
List of Figures
Figure 1 – Driver install: a) Update driver, b) Specify path to FTDI drivers..................................... 8
Figure 2 – Driver install: a) VCP loaded and b) drivers successfully installed ................................ 8
Figure 3 – SmartRF06EB (rev. 1.2.1) with EM connected ............................................................ 10
Figure 4 – SmartRF06EB architecture .......................................................................................... 12
Figure 5 – SmartRF06EB revision 1.2.1 front side ........................................................................ 13
Figure 6 – SmartRF06EB revision 1.2.1 reverse side ................................................................... 13
Figure 7 – Jumper mounted on J5 to enable the UART back channel ......................................... 14
Figure 8 – Main power switch (P501) and source selection switch (P502) ................................... 15
Figure 9 – SmartRF06EB power selection switch (P502) in “USB” position ................................. 15
Figure 10 – SmartRF06EB power source selection switch (P502) in “BAT” position ................... 16
Figure 11 – SmartRF06EB external power supply header (J501) ................................................ 16
Figure 12 – Power domain overview of SmartRF06EB ................................................................. 17
Figure 13 – Mount a jumper on J502 to bypass EM domain voltage regulator ............................. 18
Figure 14 – Simplified schematic of Ambient Light Sensor setup ................................................. 20
Figure 15 – SmartRF06EB EM connectors RF1 and RF2 ............................................................ 21
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Figure 16 – SmartRF06EB I/O breakout overview ........................................................................ 23
Figure 17 – XDS100v3 Emulator Bypass Header (P408) ............................................................. 24
Figure 18 – 20-pin ARM JTAG header (P409) .............................................................................. 25
Figure 19 – 10-pin ARM Cortex Debug header (P410) ................................................................. 26
Figure 20 – Simplified schematic of high-side current sensing setup ........................................... 27
Figure 21 – Measuring current consumption using jumper J503 .................................................. 27
Figure 22 – Simplified connection diagram for different debugging scenarios ............................. 28
Figure 23 – Debugging external target using SmartRF06EB ........................................................ 29
Figure 24 – ARM JTAG header (P409) with strapping to debug external target .......................... 30
List of Tables
Table 1 – SmartRF06EB features ................................................................................................... 5
Table 2 – Supply voltage: Recommended operating conditions and absolute max. ratings ........ 11
Table 3 – Temperature: Recommended operating conditions and storage temperatures ........... 11
Table 4 – UART Back channel signal connections ....................................................................... 14
Table 5 – Power domain overview of SmartRF06EB .................................................................... 17
Table 6 – LCD signal connections ................................................................................................. 19
Table 7 – Micro SD Card signal connections ................................................................................ 19
Table 8 – Accelerometer signal connections ................................................................................. 20
Table 9 – Ambient Light Sensor signal connections ..................................................................... 20
Table 10 – Button signal connections ........................................................................................... 20
Table 11 – General purpose LED signal connections ................................................................... 21
Table 12 – EM connector RF1 pin-out........................................................................................... 22
Table 13 – EM connector RF2 pin-out........................................................................................... 22
Table 14 – SmartRF06EB I/O breakout overview ......................................................................... 24
Table 15 – 20-pin ARM JTAG header pin-out (P409) ................................................................... 25
Table 16 – 10-pin ARM Cortex Debug header pin-out (P410) ...................................................... 26
Table 17 – Debugging external target: Minimum strapping (cJTAG support) ............................... 30
Table 18 – Debugging external target: Optional strapping ............................................................ 30
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1 Introduction
The SmartRF06 Evaluation Board (SmartRF06EB or simply EB) is the motherboard in
development kits for Low Power RF ARM Cortex®-M based System on Chips from Texas
Instruments. The board has a wide range of features, listed in Table 1 below.
Component Description
TI XDS100v3 Emulator cJTAG and JTAG emulator for easy programming and
debugging of SoCs on Evaluation Modules or external targets.
High-speed USB 2.0
interface
Easy plug and play access to full SoC control using SmartRF™
Studio PC software. Integrated serial port over USB enables
communication between the SoC via the UART back channel.
64x128 pixels serial LCD Big LCD display for demo use and user interface development.
LEDs Four general purpose LEDs for demo use or debugging.
Micro SD card slot External flash for extra storage, over-the-air upgrades and more.
Buttons Five push-buttons for demo use and user interfacing.
Accelerometer Three-axis highly configurable digital accelerometer for
application development and demo use.
Light Sensor Ambient Light Sensor for application development and demo
use.
Current measurement Current sense amplifier for high side current measurements.
Breakout pins Easy access to SoC GPIO pins for quick and easy debugging.
Table 1 – SmartRF06EB features
2 About this manual
This manual contains reference information about the SmartRF06EB.
Chapter 4 will give a quick introduction on how to get started with the SmartRF06EB. It describes
how to install SmartRF™ Studio to get the required USB drivers for the evaluation board. Chapter
5 briefly explains how the EB can be used throughout a project’s development cycle. Chapter 6
gives an overview of the various features and functionality provided by the board.
A troubleshooting guide is found in chapter 8 and Appendix A contains the schematics for
SmartRF06EB revision 1.2.1.
The PC tools SmartRF™ Studio and SmartRF™ Flash Programmer have their own user manual.
See chapter 9 for references to relevant documents and web pages.
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3 Acronyms and Abbreviations
ALS Ambient Light Sensor
cJTAG Compact JTAG (IEEE 1149.7)
CW Continuous Wave
DK Development Kit
EB Evaluation Board
EM Evaluation Module
FPGA Field-Programmable Gate Array
I/O Input/Output
JTAG Joint Test Action Group (IEEE 1149.1)
LCD Liquid Crystal Display
LED Light Emitting Diode
LPRF Low Power RF
MCU Micro Controller
MISO Master In, Slave Out (SPI signal)
MOSI Master Out, Slave In (SPI signal)
NA Not Applicable / Not Available
NC Not Connected
RF Radio Frequency
RTS Request to Send
RX Receive
SoC System on Chip
SPI Serial Peripheral Interface
TI Texas Instruments
TP Test Point
TX Transmit
UART Universal Asynchronous Receive Transmit
USB Universal Serial Bus
VCP Virtual COM Port
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4 Getting Started
Before connecting the SmartRF06EB to the PC via the USB cable, it is highly recommended to
perform the steps described below.
4.1 Installing SmartRF Studio and USB drivers
Before your PC can communicate with the SmartRF06EB over USB, you will need to install the
USB drivers for the EB. The latest SmartRF Studio installer [1] includes USB drivers both for
Windows x86 and Windows x64 platforms.
After you have downloaded SmartRF Studio from the web, extract the zip-file, run the installer
and follow the instructions. Select the complete installation to include the SmartRF Studio
program, the SmartRF Studio documentation and the necessary drivers needed to communicate
with the SmartRF06EB.
4.1.1 SmartRF Studio
SmartRF Studio is a PC application developed for configuration and evaluation of many RF-IC
products from Texas Instruments. The application is designed for use with SmartRF Evaluation
Boards, such as SmartRF06EB, and runs on Microsoft Windows operating systems.
SmartRF Studio lets you explore and experiment with the RF-ICs as it gives full overview and
access to the devices’ registers to configure the radio and has a control interface for simple radio
operation from the PC.
This means that SmartRF Studio will help radio system designers to easily evaluate the RF-IC at
an early stage in the design process. It also offers a flexible code export function of radio register
settings for software developers.
The latest version of SmartRF Studio can be downloaded from the Texas Instruments website [1],
where you will also find a complete user manual.
4.1.2 FTDI USB driver
SmartRF PC software such as SmartRF Studio uses a proprietary USB driver from FTDI [2] to
communicate with SmartRF06 evaluation boards. Connect your SmartRF06EB to the computer
with a USB cable and turn it on. If you did a complete install of SmartRF Studio, Windows will
recognize the device automatically and the SmartRF06EB is ready for use!
4.1.2.1 Install FTDI USB driver manually in Windows
If the SmartRF06EB was not properly recognized after plugging it into your PC, try the following
steps to install the necessary USB drivers. The steps described are for Microsoft Windows 7, but
are very similar to those in Windows XP and Windows Vista. It is assumed that you have already
downloaded and installed the latest version of SmartRF Studio 7 [1].
Open the Windows Device Manager and right click on the first “Texas Instruments XDS100v3”
found under “Other devices” as shown in Figure 1a.
Select “Update Driver Software…” and, in the appearing dialog, browse to
\Drivers\ftdi as shown in Figure 1b.
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a)
b)
Figure 1 – Driver install: a) Update driver, b) Specify path to FTDI drivers
Press Next and wait for the driver to be installed. The selected device should now appear in the
Device Manager as “TI XDS100v3 Channel x” (x = A or B) as seen in Figure 2b. Repeat the
above steps for the second “Texas Instruments XDS100v3” listed under “Other devices”.
4.1.2.1.1 Enable XDS100v3 UART back channel on Windows
If you have both “TI XDS100v3 Channel A” and “TI XDS100v3 Channel B” listed under Universal
Serial Bus Controllers, you can proceed. Right click on “TI XDS100v3 Channel B” and select
Properties. Under the Advanced tab, make sure “Load VCP” is checked as shown in Figure 2a.
A “USB Serial Port” may be listed under “Other devices”, as seen in Figure 1a. Follow the same
steps as for the “Texas Instruments XDS100v3” devices to install the VCP driver. When the
drivers from \Drivers\ftdi is properly installed, you should see the USB Serial
Port device be listed under “Ports (COM & LPT)” as shown in Figure 2b.
The SmartRF06EB drivers are now installed correctly.
Figure 2 – Driver install: a) VCP loaded and b) drivers successfully installed
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4.1.2.2 Install XSD100v3 UART back channel on Linux
The ports on SmartRF06EB will typically be mounted as ttyUSB0 or ttyUSB1. The UART back
channel is normally mounted as ttyUSB1.
1. Download the Linux drivers from [2].
2. Untar the ftdi_sio.tar.gz file on your Linux system.
3. Connect the SmartRF06EB to your system.
4. Install driver
a. Verify the USB Product ID (PID) and Vendor ID (VID).
The TI XDS100v3 USB VID is 0x0403 and the PID is 0xA6D1, but if you wish to
find the PID using a terminal window/shell, use
> lsusb | grep -i future
b. Install driver using modprobe
In a terminal window/shell, navigate to the ftdi_sio folder and run
> sudo modprobe ftdi_sio vendor=0x403 product=0xA6D1
SmartRF06EB should now be correctly mounted. The above steps have been tested on Fedora
and Ubuntu distributions.
If the above steps failed, try uninstalling ‘brltty’ prior to step 5 (technical note TN_101, [2]).
> sudo apt-get remove brltty
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5 Using the SmartRF06 Evaluation Board
The SmartRF06EB is a flexible test and development platform that works together with RF
Evaluation Modules from Texas Instruments.
An Evaluation Module (EM) is a small RF module with RF chip, balun, matching filter, SMA
antenna connector and I/O connectors. The modules can be plugged into the SmartRF06EB
which lets the PC take direct control of the RF device on the EM over the USB interface.
SmartRF06EB currently supports:
- CC2538EM
SmartRF06EB is included in e.g. the CC2538 development kit.
Figure 3 – SmartRF06EB (rev. 1.2.1) with EM connected
The PC software that controls the SmartRF06EB + EM is SmartRF Studio. Studio can be used to
perform several RF tests and measurements, e.g. to set up a CW signal and send/receive
packets.
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The EB+EM can be of great help during the whole development cycle for a new RF product.
- Perform comparative studies. Compare results obtained with EB+EM with results from
your own system.
- Perform basic functional tests of your own hardware by connecting the radio on your
board to SmartRF06EB. SmartRF Studio can be used to exercise the radio.
- Verify your own software with known good RF hardware, by simply connecting your own
microcontroller to an EM via the EB. Test the send function by transmitting packets from
your SW and receive with another board using SmartRF Studio. Then transmit using
SmartRF Studio and receive with your own software.
- Develop code for your SoC and use the SmartRF06EB as a standalone board without PC
tools.
The SmartRF06EB can also be used as a debugger interface to the SoCs from IAR Embedded
workbench for ARM or Code Composer Studio from Texas Instruments. For details on how to use
the SmartRF06EB to debug external targets, see chapter 7.
5.1 Absolute Maximum Ratings
The minimum and maximum operating supply voltages and absolute maximum ratings for the
active components onboard the SmartRF06EB are summarized in Table 2. Table 3 lists the
recommended operating temperature and storage temperature ratings. Please refer to the
respective component’s datasheet for further details.
Component
Operating voltage Absolute max. rating
Min. [V] Max. [V] Min. [V] Max. [V]
XDS100v3 Emulator1 [4] +1.8 +3.6 -0.3 +3.75
LCD [5] +3.0 +3.3 -0.3 +3.6
Accelerometer [6] +1.62 +3.6 -0.3 +4.25
Ambient light sensor [7] +2.32 +5.5 NA +6
Table 2 – Supply voltage: Recommended operating conditions and absolute max. ratings
Component
Operating temperature Storage temperature
Min. [˚C] Max. [˚C] Min. [˚C] Max. [˚C]
XDS100v3 Emulator [4] -20 +70 -50 +110
LCD [5] -20 +70 -30 +80
Accelerometer [6] -40 +85 -50 +150
Ambient light sensor [7] -40 +85 -40 +85
Table 3 – Temperature: Recommended operating conditions and storage temperatures
1 The XDS100v3 Emulator is USB powered. Values refer to the supply and I/O pin voltages of the connected target.
2 Recommended minimum operating voltage.
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6 SmartRF06 Evaluation Board Overview
SmartRF06EB acts as the motherboard in development kits for ARM® Cortex™ based Low
Power RF SoCs from Texas Instruments. The board has several user interfaces and connections
to external interfaces, allowing fast prototyping and testing of both software and hardware. An
overview of the SmartRF06EB architecture is found in Figure 4. The board layout is found in
Figure 5 and Figure 6, while the schematics are located in Appendix A.
This chapter will give an overview of the general architecture of the board and describe the
available I/O. The following sub-sections will explain the I/O in more detail. Pin connections
between the EM and the evaluation board I/O can be found in section 6.10.
EM Domain (1.8 – 3.6 V)
XDS Domain
3.3 V Domain
EM Connectors
Light Sensor Buttons LEDs Accelerometer
XDS100v3
Emulator
XDS
LEDs
Level shifter
SD Card Reader
Load switch
20-pin
ARM JTAG
Header
Bypass Header
UART back
channel
Level shifter
10-pin
ARM Cortex
Debug Header
(c)JTAG
USB
I/O breakout headers
3.3 V Domain
Enable
LCD
I/O Breakout Headers
Figure 4 – SmartRF06EB architecture
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EM current
measurement
testpoint and
jumper
XDS bypass
header
20-pin ARM
JTAG Header
General purpose
buttons
UART back
channel
breakout
XDS LEDs
10-pin ARM
Cortex Header
EM I/O breakout
Main power
switch
Power source
selection switch
External power
supply connector
EM reset button
Regulator
bypass jumper
Micro SD
card slot
LCD
Accelerometer
LEDs
Ambient Light
Sensor
EM connectors
UART back
channel enable
Jumper
Figure 5 – SmartRF06EB revision 1.2.1 front side
1.5 V AAA
Alkaline Battery
holder
XDS100v3
Emulator
1.5 V AAA
Alkaline Battery
holder
CR2032 coin
cell battery
holder
Figure 6 – SmartRF06EB revision 1.2.1 reverse side
6.1 XDS100v3 Emulator
The XDS100v3 Emulator from Texas Instruments has cJTAG and regular JTAG support. cJTAG
is a 2-pin extension to regular 4-pin JTAG. The XDS100v3 consists of a USB to JTAG chip from
FTDI [2] and an FPGA to convert JTAG instructions to cJTAG format.
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In addition to regular debugging capabilities using cJTAG or JTAG, the XDS100v3 Emulator
supports a UART backchannel over a USB Virtual COM Port (VCP) to the PC. The UART back
channel supports flow control, 8-N-1 format and data rates up to 12Mbaud.
Please see the XDS100v3 emulator product page [4] for detailed information about the emulator.
The XDS100v3 Emulator is powered over USB and is switched on as long as the USB cable is
connected to the SmartRF06EB and the main power switch (S501) is in the ON position. The
XDS100v3 Emulator supports targets with operating voltages between 1.8 V and 3.6. The min
(max) operating temperature is -20 (+70) ˚C.
6.1.1 UART back channel
The mounted EM can be connected to the PC via the XDS100v3 Emulator’s UART back channel.
When connected to a PC, the XDS100v3 is enumerated as a Virtual COM Port (VCP) over USB.
The driver used is a royalty free VCP driver from FTDI, available for e.g. Microsoft Windows,
Linux and Max OS X. The UART back channel gives the mounted EM access to a four pin UART
interface, supporting 8-N-1 format at data rates up to 12 Mbaud.
To enable the SmartRF06EB UART back channel the “Enable UART over XDS100v3” jumper
(J5), located on the lower right side of the EB, must be mounted (Figure 7). Table 4 shows an
overview of the I/O signals related to UART Back Channel.
Figure 7 – Jumper mounted on J5 to enable the UART back channel
Signal name Description Probe header EM pin
RF1.7_UART_RX UART Receive (EM data in) EM_UART_RX (P412.2) RF1.7
RF1.9_UART_TX UART Transmit (EM data out) EM_UART_TX (P412.3) RF1.9
RF1.3_UART_CTS UART Clear To Send signal EM_UART_CTS (P412.4) RF1.3
RF2.18_UART_RTS UART Request To Send signal EM_UART_RTS (P412.5) RF2.18
Table 4 – UART Back channel signal connections
6.2 Power Sources
There are three ways to power the SmartRF06EB; batteries, USB bus and external power supply.
The power source can be selected using the power source selection switch (S502) seen in Figure
8. The XDS100v3 Emulator can only be powered over USB. The main power supply switch
(S501) cuts power to the SmartRF06EB.
Never connect batteries and an external power source to the SmartRF06EB at the
same time! Doing so may lead to excessive currents that may damage the batteries
or cause onboard components to break. The CR2032 coin cell battery is in particular
very sensitive to reverse currents (charging) and must never be combined with other
power sources (AAA batteries or an external power source).
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Figure 8 – Main power switch (P501) and source selection switch (P502)
6.2.1 USB Power
When the SmartRF06EB is connected to a PC via a USB cable, it can draw power from the USB
bus. The onboard voltage regulator supplies approximately 3.3 V to the mounted EM and the EB
peripherals. To power the mounted EM and the EB peripherals from the USB bus, the power
source selection switch (S502) should be in “USB” position (Figure 9).
The maximum current consumption is limited by the regulator to 1500 mA3.
Figure 9 – SmartRF06EB power selection switch (P502) in “USB” position
6.2.2 Battery Power
The SmartRF06EB can be powered using two 1.5 V AAA alkaline batteries or a 3 V CR2032 coin
cell battery. The battery holders for the AAA batteries and the CR2032 coin cell battery are
located on the reverse side of the PCB. To power the mounted EM and the EB peripherals using
batteries, the power source selection switch (S502) should be in “BAT” position (Figure 10).
When battery powered, the EM power domain is by default regulated to 2.1 V. The voltage
regulator may be bypassed by mounting a jumper on J502. See section 6.3.2 for more details.
Do not power the SmartRF06EB using two 1.5 V AAA batteries and a 3 V CR2032
coin cell battery at the same time. Doing so may lead to excessive currents that may
damage the batteries or cause onboard components to break.
3 Note that most USB power sources are limited to 500 mA.
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Figure 10 – SmartRF06EB power source selection switch (P502) in “BAT” position
6.2.3 External Power Supply
The SmartRF06EB can be powered using an external power supply. To power the mounted EM
and the EB peripherals using an external power supply, the power source selection switch (S502)
should be in “BAT” position (Figure 10 in section 6.2.2).
The external supply’s ground should be connected to the SmartRF06EB ground, e.g. to the
ground pad in the top left corner of the EB. Connect the positive supply connector to the external
power header J501 (Figure 11). The applied voltage must be in the range from 2.1 V to 3.6 V and
limited to max 1.5 A.
When powered by an external power supply, the EM power domain is by default regulated to
2.1 V. The voltage regulator may be bypassed by mounting a jumper on J502. See section 6.3.2
for more details.
There is a risk of damaging the onboard components if the applied voltage on the
external power connector/header is lower than -0.3 V or higher than 3.6 V
(combined absolute maximum ratings for onboard components). See section 5.1 for
further information.
Figure 11 – SmartRF06EB external power supply header (J501)
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6.3 Power Domains
The SmartRF06EB is divided into three power domains, described in detail in the following
sections. The SmartRF06EB components, and what power domain they belong to, is shown in
Figure 12 and Table 5 below.
XDS domain
(3.3 V)
XDS100v3, XDS LEDs
EM domain
(1.8 - 3.6 V)
ACC, ALS, keys, LEDs
3.3 V domain
(3.3 V)
LCD, SD card
Power sources
USB, batteries, external supply
Level
shifters
Level
shifters
Mounted EM
Figure 12 – Power domain overview of SmartRF06EB
Component Power domain Power source
Evaluation Module EM domain (LO_VDD) USB, battery, external
General Purpose LEDs EM domain (LO_VDD) USB, battery, external
Accelerometer EM domain (LO_VDD) USB, battery, external
Ambient Light Sensor EM domain (LO_VDD) USB, battery, external
Current measurement MSP
MCU
EM domain (LO_VDD) USB, battery, external
LEDs EM domain (LO_VDD) USB, battery, external
XDS100v3 Emulator XDS domain USB
XDS100v3 LEDs XDS domain USB
SD Card Slot 3.3 V domain (HI_VDD) Same as EM domain
LCD 3.3 V domain (HI_VDD) Same as EM domain
Table 5 – Power domain overview of SmartRF06EB
6.3.1 XDS Domain
The XDS100v3 Emulator (see section 6.1) onboard the SmartRF06EB is in the XDS domain. The
XDS domain is powered over USB. The USB voltage supply (+5 V) is down-converted to +3.3 V
and +1.5 V for the different components of the XDS100v3 Emulator.
The SmartRF06EB must be connected to e.g. a PC over USB for the XDS domain to be powered
up. The domain is turned on/off by the SmartRF06EB main power switch.
6.3.2 EM Domain
The mounted EM board and most of the SmartRF06EB peripherals are powered in the EM
domain and signals in this domain (accessible by the EM), are prefixed “LV_” in the schematics.
Table 5 lists the EB peripherals that are powered in the EM domain. The domain is turned on/off
by the SmartRF06EB power switch.
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The EM domain may be powered using various power sources; USB powered (regulated to 3.3
V), battery powered (regulated to 2.1 V or unregulated) and using an external power supply
(regulated to 2.1 V or unregulated).
When battery powered or powered by an external source, the EM power domain is by default
regulated to 2.1 V using a step down converter. The step down converter may be bypassed by
mounting a jumper on J502 (Figure 13), powering the EM domain directly from the source. When
J502 is not mounted, the EM power domain is regulated to 2.1 V. The maximum current
consumption of the EM power domain is then limited by the regulator to 410 mA.
Figure 13 – Mount a jumper on J502 to bypass EM domain voltage regulator
6.3.3 3.3 V Domain
The 3.3 V domain is a sub domain of the EM domain. The 3.3 V domain is regulated to 3.3 V
using a buck-boost converter, irrespective of the source powering the EM domain. Signals in the
3.3V domain (controlled by the EM) are prefixed “HV_” for High Voltage in the schematics.
Two EB peripherals are in the 3.3 V domain, the LCD and the SD card slot, as listed in Table 5.
These peripherals are connected to the EM domain via level shifters U401 and U402.
The 3.3 V domain may be switched on (off) completely by the mounted EM board by pulling
signal LV_3.3V_EN to a logical 1 (0). See Table 14 in section 6.11.1 for details about the
mapping between the EM and signals onboard the SmartRF06EB.
6.4 LCD
The SmartRF06EB comes with a 128x64 pixels display from Electronic Assembly (DOGM128E-6)
[4]. The LCD display is available to mounted EM via a SPI interface, enabling software
development of user interfaces and demo use. Table 6 shows an overview of the I/O signals
related to the LCD.
The recommended operating condition for the LCD display is a supply voltage between 3.0 V and
3.3 V. The LCD display is powered from the 3.3 V power domain (HI_VDD). The min (max)
operating temperature is -20 (+70) ˚C.
The LCD connector on SmartRF06EB is very tight to ensure proper contact between
the EM and the LCD. Be extremely cautious when removing the LCD to avoid the
display from breaking.
NOTE: Mounting a jumper on J502 will not have any effect if the SmartRF06EB is powered
over USB (when the power source selection switch, S502, is in “USB” position).
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Signal name Description Probe header EM pin
LV_3.3V_EN 3.3 V domain enable signal4 RF1.15 (P407.1) RF1.15
LV_LCD_MODE LCD mode signal RF1.11 (P406.7) RF1.11
¯L¯V¯_¯L¯C¯D¯_¯R¯¯E¯S¯E¯T¯ LCD reset signal (active low) RF1.13 (P406.9) RF1.13
¯L¯V¯_¯L¯C¯D¯_¯C¯¯S LCD Chip Select (active low) RF1.17 (P407.3) RF1.17
LV_SPI_SCK SPI Clock RF1.16_SCK (P407.2) RF1.16
LV_SPI_MOSI SPI MOSI (LCD input) RF1.18_MOSI (P407.4) RF1.18
Table 6 – LCD signal connections
6.5 Micro SD Card Slot
The SmartRF06EB has a micro SD card slot for connecting external SD/MMC flash devices (flash
device not included). A connected flash device is available to the mounted EM via a SPI interface,
giving it access to extra flash, enabling over-the-air upgrades and more. Table 8 shows an
overview of I/O signals related to the micro SD card slot.
The micro SD card is powered from the 3.3 V power domain (HI_VDD).
Signal name Description Probe header EM pin
LV_3.3V_EN 3.3 V domain enable signal4 RF1.15 (P407.1) RF1.15
¯L¯V¯_¯S¯D¯C¯¯A¯R¯D¯_¯C¯¯S SD card Chip Select (active low) RF2.12 (P411.1) RF2.12
LV_SPI_SCK SPI Clock RF1.16_SCK (P407.2) RF1.16
LV_SPI_MOSI SPI MOSI (SD card input) RF1.18_MOSI (P407.4) RF1.18
LV_SPI_MISO SPI MISO (SD card output) RF1.20_MISO (P407.5) RF1.20
Table 7 – Micro SD Card signal connections
6.6 Accelerometer
The SmartRF06EB is equipped with a BMA250 digital accelerometer from Bosch Sensortech [6].
The accelerometer is available to the mounted EM via an SPI interface and has two dedicated
interrupt lines. The accelerometer is suitable for application development, prototyping and demo
use. Table 8 shows an overview of I/O signals related to the accelerometer.
The recommended operating condition for the accelerometer is a supply voltage between 1.62 V
and 3.6 V. The min (max) operating temperature is -40 (+85) ˚C.
Signal name Description Probe header EM pin
LV_ACC_PWR Acc. power enable signal RF2.8 (P407.8) RF2.8
LV_ACC_INT1 Acc. interrupt signal RF2.16 (P411.5) RF2.16
LV_ACC_INT2 Acc. interrupt signal RF2.14 (P411.3) RF2.14
¯L¯V¯_¯A¯C¯C¯¯¯C¯S¯ Acc. Chip Select (active low) RF2.10 (P407.9) RF2.10
LV_SPI_SCK SPI Clock RF1.16_SCK (P407.2) RF1.16
LV_SPI_MOSI SPI MOSI (acc. input) RF1.18_MOSI (P407.4) RF1.18
4 The LCD and SD card are both powered in the 3.3 V domain and cannot be powered on/off individually.
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LV_SPI_MISO SPI MISO (acc. output) RF1.20_MISO (P407.5) RF1.20
Table 8 – Accelerometer signal connections
6.7 Ambient Light Sensor
The SmartRF06EB has an analog SFH 5711 ambient light sensor (ALS) from Osram [7] that is
available for the mounted EM via the EM connectors, enabling quick application development for
demo use and prototyping. Figure 14 and Table 9 shows an overview of I/O signals related to the
ambient light sensor.
The recommended operating condition for the ambient light sensor is a supply voltage between
2.3 V and 5.5 V. The min (max) operating temperature is -40 (+85) ˚C.
Ambient Light Sensor LV_ALS_OUT
LV_ALS_PWR
22 kOhm
Figure 14 – Simplified schematic of Ambient Light Sensor setup
Signal name Description Probe header EM pin
LV_ALS_PWR ALS power enable signal RF2.6 (P407.7) RF2.6
LV_ALS_OUT ALS output signal (analog) RF2.5 (P411.6) RF2.5
Table 9 – Ambient Light Sensor signal connections
6.8 Buttons
There are 6 buttons on the SmartRF06EB. Status of the LEFT, RIGHT, UP, DOWN and SELECT
buttons are available to the mounted EM. These buttons are intended for user interfacing and
development of demo applications.
The EM RESET button resets the mounted EM by pulling its reset line low (¯R¯F¯2¯.1¯5¯¯R¯¯E¯S¯E¯T¯).
Table 10 shows an overview of I/O signals related to the buttons.
Signal name Description Probe header EM pin
LV_BTN_LEFT Left button (active low) RF1.6 (P406.4) RF1.6
LV_BTN_RIGHT Right button (active low) RF1.8 (P406.5) RF1.8
LV_BTN_UP Up button (active low) RF1.10 (P406.6) RF1.10
LV_BTN_DOWN Down button (active low) RF1.12 (P406.8) RF1.12
LV_BTN_SELECT Select button (active low) RF1.14 (P406.10) RF1.14
¯L¯V¯_¯B¯T¯N¯_¯R¯¯E¯S¯E¯T¯ EM reset button (active low) ¯R¯F¯2¯.1¯5¯¯R¯¯E¯S¯E¯T¯ (P411.4) RF2.15
Table 10 – Button signal connections
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6.9 LEDs
6.9.1 General Purpose LEDs
The four LEDs D601, D602, D603, D604 can be controlled from the mounted EM and are suitable
for demo use and debugging. The LEDs are active high. Table 11 shows an overview of I/O
signals related to the LEDs.
Signal name Description Probe header EM pin
LV_LED_1 LED 1 (red) RF2.11 (P407.10) RF2.11
LV_LED_2 LED 2 (yellow) RF2.13 (P411.2) RF2.13
LV_LED_3 LED 3 (green) RF1.2 (P406.1) RF1.2
LV_LED_4 LED 4 (red-orange) RF1.4 (P406.2) RF1.4
Table 11 – General purpose LED signal connections
6.9.2 XDS100v3 Emulator LEDs
The XDS100v3 emulator has two LEDs to indicate its status, D2 and D4. The LEDs are located
on the top side of the SmartRF06EB. LED D2 is lit whenever the XDS100v3 Emulator is powered,
while LED D4 (ADVANCED MODE) is lit when the XDS100v3 is in an active cJTAG debug state.
6.10 EM Connectors
The EM connectors, shown in Figure 15, are used for connecting an EM board to the
SmartRF06EB. The connectors RF1 and RF2 are the main interface and are designed to inhibit
incorrect mounting of the EM board. The pin-out of the EM connectors is given in Table 12 and
Table 13.
Figure 15 – SmartRF06EB EM connectors RF1 and RF2
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EM pin Signal name Description
Probe
header
Breakout
header
RF1.1 GND Ground
RF1.2 RF1.2 GPIO signal to EM board P406.1 P403.1-2
RF1.3 RF1.3_UART_CTS UART back channel / GPIO P412.4 P408.15-16
RF1.4 RF1.4 GPIO signal to EM board P406.2 P403.3-4
RF1.5 RF1.5 GPIO signal to EM board P406.3 P403.5-6
RF1.6 RF1.6 GPIO signal to EM board P406.4 P403.7-8
RF1.7 RF1.7_UART_RX UART back channel (EM RX) P412.2 P408.11-12
RF1.8 RF1.8 GPIO signal to EM board P406.5 P403.9-10
RF1.9 RF1.9_UART_TX UART back channel (EM TX) P412.3 P408.13-14
RF1.10 RF1.10 GPIO signal to EM board P406.6 P403.11-12
RF1.11 RF1.11 GPIO signal to EM board P406.7 P403.13-14
RF1.12 RF1.12 GPIO signal to EM board P406.8 P403.15-16
RF1.13 RF1.13 GPIO signal to EM board P406.9 P403.17-18
RF1.14 RF1.14 GPIO signal to EM board P406.10 P403.19-20
RF1.15 RF1.15 GPIO signal to EM board P407.1 P404.1-2
RF1.16 RF1.16_SPI_SCK EM SPI Clock P407.2 P404.3-4
RF1.17 RF1.17 GPIO signal to EM board P407.3 P404.5-6
RF1.18 RF1.18_SPI_MOSI EM SPI MOSI P407.4 P404.7-8
RF1.19 GND Ground
RF1.20 RF1.20_SPI_MISO EM SPI MISO P407.5 P404.9-10
Table 12 – EM connector RF1 pin-out
EM pin Signal name Description
Probe
header
Breakout
header
RF2.1 RF2.1_JTAG_TCK JTAG Test Clock P409.9 P408.1-2
RF2.2 GND Ground
RF2.3 RF_VDD2 EM power TP10 J503.1-2
RF2.4 RF2.4_JTAG_TMS JTAG Test Mode Select P409.7 P408.3-4
RF2.5 RF2.5 GPIO signal to EM board P407.6 P404.11-12
RF2.6 RF2.6 GPIO signal to EM board P407.7 P404.13-14
RF2.7 RF_VDD1 EM power TP10 J503.1-2
RF2.8 RF2.8 GPIO signal to EM board P407.8 P404.15-16
RF2.9 RF_VDD1 EM power TP10 J503.1-2
RF2.10 RF2.10 GPIO signal to EM board P407.9 P404.17-18
RF2.11 RF2.11 GPIO signal to EM board P407.10 P404.19-20
RF2.12 RF2.12 GPIO signal to EM board P411.1 P405.1-2
RF2.13 RF2.13 GPIO signal to EM board P411.2 P405.3-4
RF2.14 RF2.14 GPIO signal to EM board P411.3 P405.5-6
RF2.15 ¯R¯F¯2¯.1¯5¯¯R¯¯E¯S¯E¯T¯ EM reset signal (active low) P411.4 P405.7-8
RF2.16 RF2.16 GPIO signal to EM board P411.5 P405.9-10
RF2.17 RF2.17_JTAG_TDI GPIO / JTAG Test Data In P409.5 P408.5-6
RF2.18 RF2.18_UART_RTS GPIO / UART Back Channel P412.5 P408.17-18
RF2.19 RF2.19_JTAG_TDO GPIO / JTAG Test Data Out P409.13 P408.7-8
RF2.20 GND Ground
Table 13 – EM connector RF2 pin-out
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6.11 Breakout Headers and Jumpers
The SmartRF06EB has several breakout headers, giving access to all EM connector pins. An
overview of the SmartRF06EB I/O breakout headers is given in Figure 16. Probe headers P406,
P407, P411 and P412 give access to the I/O signals of the mounted EM. Breakout headers P403,
P404 and P405 allow the user to map any EM I/O signal to any peripheral on the SmartRF06EB.
The XDS bypass header (P408) makes it possible to disconnect the XDS100v3 Emulator
onboard the EB from the EM. Using the 20-pin ARM JTAG header (P409) or the 10-pin ARM
Cortex Debug Header (P410), it is possible to debug external targets using the onboard emulator.
Evaluation
Module
Peripheral
probe headers
P406, P407,
P411
I/O breakout headers
P403, P404, P405
SmartRF06EB
peripherals
ACC, ALS, keys, LCD,
LED, SD card
XDS bypass header
P408
XDS100v3
Emulator
20-pin
ARM-JTAG
Debug Header
P409
10-pin Cortex
Debug Header
P410
UART back
channel probe
header
P412
Figure 16 – SmartRF06EB I/O breakout overview
6.11.1 I/O Breakout Headers
The I/O breakout headers on SmartRF06EB consist of pin connectors P406, P407, P411 and
P412. P406, P407 and P411 are located at the top left side of SmartRF06EB. All EM signals
available on these probe headers can be connected to or disconnected from SmartRF06EB
peripherals using jumpers on headers P403, P404, P405.
Probe header P412 is located near the bottom right corner of the SmartRF06EB. The signals
available on P412 are connected to the XDS100v3 Emulator’s UART back channel using jumpers
on header P408.
The I/O breakout mapping between the SmartRF06EB and the mounted EM is given in Table 14.
The leftmost column in the below table refers to the silk print seen on the SmartRF06EB. The
rightmost column shows the corresponding CC2538 I/O pad on CC2538EM.
NOTE: By default, all jumpers are mounted on P403, P404, P405 and P408. The default
configuration is assumed in this user’s guide unless otherwise stated.
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Probe
header
Silk print EB signal name
EM
connector
CC2538EM
I/O
P406 RF1.2 LV_LED_3 RF1.2 PC2
RF1.4 LV_LED_4 RF1.4 PC3
RF1.5 NC RF1.5 PB1
RF1.6 LV_BTN_LEFT RF1.6 PC4
RF1.8 LV_BTN_RIGHT RF1.8 PC5
RF1.10 LV_BTN_UP RF1.10 PC6
RF1.11 LV_LCD_MODE RF1.11 PB2
RF1.12 LV_BTN_DOWN RF1.12 PC7
RF1.13 ¯L¯V¯_¯L¯C¯D¯_¯R¯¯E¯S¯E¯T¯ RF1.13 PB3
RF1.14 LV_BTN_SELECT RF1.14 PA3
P407 RF1.15 LV_3.3V_EN RF1.15 PB4
RF1.16_SCK LV_SPI_SCK RF1.16 PA2
RF1.17 ¯L¯V¯_¯L¯C¯D¯_¯C¯¯S RF1.17 PB5
RF1.18_MOSI LV_SPI_MOSI RF1.18 PA4
RF1.20_MISO LV_SPI_MISO RF1.20 PA5
RF2.5 LV_ALS_OUT RF2.5 PA6
RF2.6 LV_ALS_PWR RF2.6 PA7
RF2.8 LV_ACC_PWR RF2.8 PD4
RF2.10 ¯L¯V¯_¯A¯C¯C¯¯¯C¯S¯ RF2.10 PD5
RF2.11 LV_LED_1 RF2.11 PC0
P411 RF2.12 ¯L¯V¯_¯S¯D¯C¯¯A¯R¯D¯_¯C¯¯S RF2.12 PD0
RF2.13 LV_LED_2 RF2.13 PC1
RF2.14 LV_ACC_INT2 RF2.14 PD1
RF2.15_RESET ¯L¯V¯_¯B¯T¯N¯_¯R¯¯E¯S¯E¯T¯ RF2.15 nRESET
RF2.16 LV_ACC_INT1 RF2.16 PD2
P412 EM_UART_RX RF1.7_UART_RX RF1.7 PA0
EM_UART_TX RF1.9_UART_TX RF1.9 PA1
EM_UART_CTS RF1.3_UART_CTS RF1.3 PB0
EM_UART_RTS RF2.18_UART_RTS RF2.18 PD3
Table 14 – SmartRF06EB I/O breakout overview
6.11.2 XDS100v3 Emulator Bypass Headers
The XDS100v3 Emulator bypass header, P408, is by default mounted with jumpers (Figure 17),
connecting the XDS100v3 Emulator to a mounted EM or external target. By removing the jumpers
on P408, the XDS100v3 Emulator may be disconnected from the target.
Figure 17 – XDS100v3 Emulator Bypass Header (P408)
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6.11.3 20-pin ARM JTAG Header
The SmartRF06EB comes with a standard 20-pin ARM JTAG header [8] (Figure 18), enabling the
user to debug an external target using the XDS100v3 Emulator. The pin-out of the ARM JTAG
header is given in Table 15. Chapter 7 has more information on how to debug an external target
using the XDS100v3 Emulator onboard the SmartRF06EB.
Figure 18 – 20-pin ARM JTAG header (P409)
Pin Signal Description EB signal name
XDS
bypass
header
P409.1 VTRef Voltage reference VDD_SENSE P408.19-20
P409.2 VSupply Voltage supply NC
P409.3 nTRST Test Reset NC
P409.4 GND Ground GND
P409.5 TDI Test Data In RF2.17_JTAG_TDI P408.5-6
P409.6 GND Ground GND
P409.7 TMS Test Mode Select RF2.4_JTAG_TMS P408.3-4
P409.8 GND Ground GND
P409.9 TCK Test Clock RF2.1_JTAG_TCK P408.1-2
P409.10 GND Ground GND
P409.11 RTCK Return Clock NC
P409.12 GND Ground GND
P409.13 TDO Test Data Out RF2.19_JTAG_TDO P408.7-8
P409.14 GND Ground GND
P409.15 nSRST System Reset ¯R¯F¯2¯.1¯5¯¯R¯¯E¯S¯E¯T¯ P408.9-10
P409.16 GND Ground GND
P409.17 DBGRQ Debug Request NC
P409.18 GND Ground GND
P409.19 DBGACK Debug Acknowledge NC
P409.20 GND Ground GND
Table 15 – 20-pin ARM JTAG header pin-out (P409)
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6.11.4 10-pin ARM Cortex Debug Header
The SmartRF06EB comes with a standard 10-pin ARM Cortex debug header [8] (Figure 19),
enabling the user to debug an external target using the XDS100v3 Emulator. The ARM Cortex
debug header is located near the right hand edge of the EB. The header pin-out is given in Table
16. Chapter 7 has more information on how to debug an external target using the XDS100v3
Emulator onboard the SmartRF06EB.
Figure 19 – 10-pin ARM Cortex Debug header (P410)
Pin Signal Description EB signal name
XDS bypass
header
P410.1 VCC Voltage reference VDD_SENSE P408.19-20
P410.2 TMS Test Mode Select RF2.4_JTAG_TMS P408.3-4
P410.3 GND Ground GND
P410.4 TCK Test Clock RF2.1_JTAG_TCK P408.1-2
P410.5 GND Ground GND
P410.6 TDO Test Data Out RF2.19_JTAG_TDO P408.7-8
P410.7 KEY Key NC
P410.8 TDI Test Data In RF2.17_JTAG_TDI P408.5-6
P410.9 GNDDetect Ground detect GND
P410.10 nRESET System Reset ¯R¯F¯2¯.1¯5¯¯R¯¯E¯S¯E¯T¯ P408.9-10
Table 16 – 10-pin ARM Cortex Debug header pin-out (P410)
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6.12 Current Measurement
The SmartRF06EB provides two options for easy measurements of the current consumption of a
mounted EM. The following sections describe these two options in detail.
6.12.1 High-side current sensing
The SmartRF06EB comes with a current sensing unit for measuring the current consumption of
the mounted EM (Figure 20). The current sensing setup is “high-side”, that is, it measures the
current going to the mounted EM. The current is converted to a voltage, available at the
CURMEAS_OUTPUT test point (TP11), located near the right edge of the SmartRF06EB. Using
the SmartRF06EB together with for example an oscilloscope makes it easy to measure the EM
current consumption as a function of time.
The relationship between the voltage measured at CURMEAS_OUTPUT, VCURMEAS, and the EM
current consumption, IEM, is given by Equation 1 below.
15
V
I CURMEAS
EM (1)
G = 100
0.15 Ohm
To EM
IEM
VCURMEAS
Figure 20 – Simplified schematic of high-side current sensing setup
6.12.2 Current Measurement Jumper
SmartRF06EB has a current measurement header, J503, for easy measurement of EM current
consumption. Header J503 is located on the upper right hand side of the EB. By replacing the
jumper with an ammeter, as shown in Figure 21, the current consumption of the mounted EM can
be measured.
Figure 21 – Measuring current consumption using jumper J503
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7 Debugging an external target using SmartRF06EB
You can easily use XDS100v3 Emulator onboard the SmartRF06EB to debug an external target.
It is in this chapter assumed that the target is self-powered.
When debugging an external, self-powered target using SmartRF06EB, make sure to remove the
jumper from the current measurement header (J503) as shown in the second scenario of Figure
22. In this scenario, the onboard XDS100v3 senses the target voltage of the external target. In
the left side scenario of the same figure, the XDS100v3 senses the target voltage of the EB’s EM
domain.
Having a jumper mounted on header J503 when debugging an external target will
cause a conflict between the EB’s EM domain supply voltage and the target’s supply
voltage. This may result in excess currents, damaging the onboard components of
the SmartRF06EB or the target board.
In Figure 22, the right hand side scenario shows how it is possible to debug an EM mounted on
the SmartRF06EB using an external debugger. In this scenario, all the jumpers must be removed
from the SmartRF06EB header P408 to avoid signaling conflicts between the onboard XDS100v3
Emulator and the external debugger.
XDS100v3
06EB XDS + EM
EM
(EM domain)
XDS100v3
06EB XDS + external target
Ext. target
(Target VDD)
EM
(EM domain)
XDS100v3
External debugger + EM
External
debugger
EM
(EM domain)
P408
(jumpers on)
P408
(jumpers off)
J503
(mounted)
J503
(mounted)
J503
(not mounted)
Current measurement jumper
XDS bypass header P408
(jumpers on)
Debug
header
P409/P410 P409/P410
Figure 22 – Simplified connection diagram for different debugging scenarios
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7.1 20-pin ARM JTAG Header
The SmartRF06EB has a standard 20-pin ARM JTAG header mounted on the right hand side
(P409). Make sure all the jumpers on the XDS bypass header (P408) are mounted and that the
jumper is removed from header J503.
Connect the external board to the 20-pin ARM JTAG header (P409) using a 20-pin flat cable as
seen in Figure 23. Make sure pin 1 on P409 matches pin 1 on the external target. See sections
6.11.3 and 6.11.2 for more info about the 20-pin ARM JTAG header and the XDS bypass header,
respectively.
Figure 23 – Debugging external target using SmartRF06EB
7.2 10-pin ARM Cortex Debug Header
The SmartRF06EB has a standard 10-pin ARM Cortex Debug header mounted on the right hand
side (P410). Make sure all the jumpers on the XDS bypass header (P408) are mounted and that
the jumper is removed from header J503.
Connect the external board to the 10-pin ARM JTAG header using a 10-pin flat cable. Make sure
pin 1 on P410 matches pin 1 on the external target See sections 6.11.4 and 6.11.2 for more info
about the 10-pin ARM Cortex Debug header and the XDS bypass header, respectively.
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7.3 Custom Strapping
If the external board does not have a 20-pin ARM JTAG connector nor a 10-pin ARM Cortex
connector, the needed signals may be strapped from the onboard XDS100v3 Emulator to the
external target board.
Make sure all the jumpers on the XDS bypass header (P408) are mounted and that the jumper is
removed from header J503. Table 17 shows the signals that must be strapped between the
SmartRF06EB and the target board. Table 18 shows additional signals that are optional or
needed for debugging using 4-pin JTAG. Figure 24 shows where the signals listed in Table 17
and Table 18 can be found on the 20-pin ARM JTAG header.
EB Signal Name
EB
Breakout
Description
VDD_SENSE P409.1 Target voltage supply
GND P409.4 Common ground for EB and external board
RF2.1_JTAG_TCK P409.9 Test Clock
RF2.4_JTAG_TMS P409.7 Test Mode Select
Table 17 – Debugging external target: Minimum strapping (cJTAG support)
EB Signal Name
EB
Breakout
Description
RF2.17_JTAG_TDI P409.5 Test Data In (optional for cJTAG)
RF2.19_JTAG_TDO P409.13 Test Data Out (optional for cJTAG)
¯R¯F¯2¯.1¯5¯¯R¯¯E¯S¯E¯T¯ P409.15 Target reset signal (optional)
Table 18 – Debugging external target: Optional strapping
VDD_SENSE
RF2.17_JTAG_TDI
RF2.4_JTAG_TMS
RF2.1_JTAG_TCK
RF2.19_JTAG_TDO
GND
2-pin cJTAG
4-pin JTAG
Optional
+
RF2.15_RESET
Figure 24 – ARM JTAG header (P409) with strapping to debug external target
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8 Frequently Asked Questions
Q1 Nothing happens when I power up the evaluation board. Why?
A1 Make sure you have a power source connected to the EB. Verify that the power source
selection switch (S502) is set correctly according to your power source. When powering
the EB from either batteries or an external power source, S502 should be in “BAT”
position. When powering the EB over USB, the switch should be in “USB” position. Also,
make sure the EM current measurement jumper (J503) is short circuited.
Q2 Why are there two JTAG connectors on the SmartRF06EB, which one should I use?
A2 The SmartRF06EB comes with two different standard debug connectors, the 20-pin ARM
JTAG connector (P409) and the compact 10-pin ARM Cortex debug connector (P410).
These debug connectors are there to more easily debug external targets without the
need of customized strapping. For more details on how to debug external targets using
the SmartRF06EB, see chapter 7.
Q3 Can I use the SmartRF06EB to debug an 8051 SoC such as CC2530?
A3 No, you cannot debug an 8051 SoC using the SmartRF06EB.
Q4 When connecting my SmartRF06EB to my PC, no serial port appears. Why?
A4 It may be that the virtual COM port on the SmartRF06EB’s XDS100 channel B hasn’t
been enabled. Section 4.1.2.1.1 describes how to enable the Vritual COM Port in the
USB driver.
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9 References
[1] SmartRF Studio Product Page
http://www.ti.com/tool/smartrftm-studio
[2] FTDI USB Driver Page
http://www.ftdichip.com
[3] SmartRF Flash Programmer Product Page
http://www.ti.com/tool/flash-programmer
[4] XDS100 Emulator Product Page
http://processors.wiki.ti.com/index.php/XDS100
[5] Electronic Assembly DOGM128-6 Datasheet
http://www.lcd-module.com/eng/pdf/grafik/dogm128e.pdf
[6] Bosch Sensortec BMA250 Datasheet
http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-
ds002-05.pdf
[7] Osram SFH 5711
http://www.osram-os.com
[8] Cortex-M Debug Connectors
http://infocenter.arm.com/help/topic/com.arm.doc.faqs/attached/13634/cortex_debu
g_connectors.pdf
10 Document History
Revision Date Description/Changes
SWRU321A 2013-05-21 Minor fixes to Figure 4. Fixed incorrect EM mapping in Table 11.
Added steps for installing SmartRF06EB on Linux.
SWRU321 2012-09-07 Initial version.
User’s Guide
SWRU321A – May 2013
Appendix A
Schematics
SmartRF06EB 1.2.1
LOW VOLTAGE
PERIPHERALS
XDS100v3 - FPGA
XDS100v3 - FTDI
EM INTERFACE/
LEVEL SHIFTERS POWER SUPPLY
HIGH VOLTAGE
PERIPHERALS
1
FM2
FIDUCIAL_MARK_1mm
1
FM4
FIDUCIAL_MARK_1mm
H2
HOLE_3
H3
HOLE_3
1
FM5
FIDUCIAL_MARK_1mm
H1
HOLE_3
1
FM6
FIDUCIAL_MARK_1mm
1
FM1
FIDUCIAL_MARK_1mm
H4
HOLE_3
1
FM3
FIDUCIAL_MARK_1mm
TP13
TESTPOINT_PAD
TP12
TESTPOINT_PAD
ISSUED 1(7)
SmartRF06EB - Top Level
SCALE SHEET
DWG NO. REV.
DWG
COMPANY NAME
SIZE FSCM NO.
CONTRACT NO.
Texas Instruments
A3
DRAWN
13/07/12
13/07/12
12/07/12
MAW
1.2.1
APPROVALS DATE
CHECKED
PRG_TDO
EXT_SELECT
ADV_MODE
V_USB V_USB
RESET_N
VCCPLF
T_TVD
VTARGET
UART_EN_N
P3.3VXDS
P1.8V
P3.3VXDS
P3.3VXDS +1.5V
P3.3VXDS P3.3VXDS
P3.3VXDS P3.3VXDS
P3.3VXDS P3.3VXDS
P3.3VXDS
P3.3VXDS
1
2 3
4
STANDBY VDD
OUTPUT
ASDM
GND
O1
ASDM 100.000MHZ
1
2
3
Q1
BC846
1
2
3
4
5 6
7
8
9
10
INA+
INAOUTA
OUTB
V+
INB+
OPA2363 INBVENA
ENB
U6
OPA2363
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
GND
GND
GND
GND
UART_EN_N
GND
VCCPLF
CLK_100M
P1.5V
P3.3VXDS
RESET_N
DTSA_BYP
CBL_DIS
EMU1
POD_RLS
P3.3VXDS
TVD
CLK_FAIL
SRST_OUT
RTCK
EMU0
EMU_EN
TRST
TMS
TDO
TDI
TCK
P1.5V
P3.3VXDS
SUSPEND
ALT_FUNC
PRG_TCK
PRG_TMS
PRG_TDI
PRG_TDO
PRG_TCK
PRG_TDI
PRG_TMS
P3.3VXDS
P3.3VXDS
PRG_TDO
PRG_TRST
P3.3VXDS
VTARGET
P1.5V
VTARGET
PWRGOOD
VTARGET
P1.5V
ADV_MODE
EXT_SELECT
T_DIS
VTARGET
IO32RSB0
GBC0/IO35RSB0
IO13RSB0
GAA0/IO00RSB0
GBC1/IO36RSB0
IO15RSB0
GAA1/IO01RSB0
GAC1/IO05RSB0
GBB0/IO37RSB0
IO19RSB0
GNDQ
GBA2/IO41RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBA1/IO40RSB0
GCC2/IO59RSB0
GBB2/IO43RSB0
GDC1/IO61RSB0
IO09RSB0
GCC1/IO51RSB0
GDC0/IO62RSB0
GCC0/IO52RSB0
VMV0
GDA1/IO65RSB0
VCCIB0
GAB1/IO03RSB0
GCA1/IO55RSB0
TDO
VCC
GBC2/IO45RSB0
VCC
VJTAG
VCC
VCCIB1
VCC
IO11RSB0
VMV1
NC
GCA0/IO56RSB0
TMS
GAC0/IO04RSB0
TRST
GDA2/IO70RSB1
IO84RSB1
TDI
VPUMP
IO87RSB1
GDB2/IO71RSB1
IO42RSB0
IO93RSB1
IO75RSB1
TCK
IO96RSB1
IO94RSB1
GDC2/IO72RSB1
IO97RSB1
IO81RSB1
GND
IO95RSB1
IO99RSB1
GCB2/IO58RSB0
GND
IO100RSB1
IO47RSB0
IO102RSB1
GEC2/IO104RSB1
GEB2/IO105RSB1
GEA2/IO106RSB1
GNDQ
VMV1
GEA0/IO107RSB1
GND
GEA1/IO108RSB1
GEB0/IO109RSB1
GEB1/IO110RSB1
GEC0/IO111RSB1
GFA2/IO120RSB1
GFA1/IO121RSB1
VCCPLF
GFA0/IO122RSB1
VCOMPLF
GFB0/IO123RSB1
GFB1/IO124RSB1
IO129RSB1
IO130RSB1
GAC2/IO131RSB1
IO132RSB1
GAA2/IO67RSB1
GND
GAB2/IO69RSB1
GND
VCCIB1
VCCIB0
GND
IO68RSB1
IO28RSB0
IO25RSB0
IO22RSB0
IO07RSB0
GAB0/IO02RSB0
A3PN125-ZVQG100
U11
A3PN125-VQFP
1
2
C23
C_4U7_0603_X5R_K_6
1
2
C27
C_4U7_0603_X5R_K_6
1
2
C26
C_4U7_0603_X5R_K_6
1
2
C24
C_100N_0402_X5R_K_10
1
2
C22
C_100N_0402_X5R_K_10
1
2
C21
C_100N_0402_X5R_K_10
1
2
C25
C_100N_0402_X5R_K_10
2
1
D1
CDBP0130L-G
2 1
R1
L_BEAD_102_0402
1
2 D4
LED_EL19-21SRC
1
2
J5
PINROW_SMD_1X2_2.54MM
1 2 T_TMS
R47 R_10K_0402_F
1 2
R50
R_1K0_0402_F
1 2
R49
R_1K0_0402_F
1 2
R27
R_1K0_0402_F
1 2
R24
R_5K1_0402_J
1 2
R54
R_5K1_0402_J
1 2
R41
R_10K_0402_F
1 2
R48
R_10K_0402_F
1 2
R46
R_10K_0402_F
2 1
PWRGOOD
R31
R_10K_0402_F
2 1
PRG_TMS
R43
R_10K_0402_F
2 1
R44
R_10K_0402_F
1 2 T_EMU4
R52 R_51_0402_G
1 2 T_EMU2
R51 R_51_0402_G
1 2 T_EMU3
R53 R_51_0402_G
1 2 T_TDI
R18 R_51_0402_G
1 2 T_RTCK
R23 R_51_0402_G
1 2 T_TRST
R19 R_51_0402_G
1 2 T_EMU5
R55 R_51_0402_G
1 2 T_TMS
R15 R_51_0402_G
1 2 T_TDO
R16 R_51_0402_G
1 2 T_TCK
R17 R_51_0402_G
1 2 CLK_100M
R33
R_51_0402_G
1 2
R30
R_120K_0402_F
2 1
R29
R_120K_0402_F
1 2
R25
R_120K_0402_F
1 2
R42
R_220_0402_J
1 2 T_EMU1
R20 R_470_0402_F
1 2 T_EMU0
R22 R_470_0402_F
1 2 T_SRST
R21 R_470_0402_F
1
2
C34
C_15N_0402_X7R_K_25
1 2
T_DIS
R12
R_0_0402
1
2
3 4
T_TVD 5
T_TDI T_TDO
T_RTCK
IO2 IO3
IO1
GND TPD4E002
IO4
TUP8D4E002
1
2
3 4
T_DIS 5
T_TRST T_EMU2
T_TMS
IO2 IO3
IO1
GND TPD4E002
IO4
TUP7D4E002
1
2
3 4
T_TCK 5
T_EMU0 T_SRST
T_EMU1
IO2 IO3
IO1
GND TPD4E002
IO4
TUP9D4E002
1
2
3 4
T_EMU5 5
T_EMU3 GND
T_EMU4
IO2 IO3
IO1
GND TPD4E002
IO4
TUP12D4E002
TP7 PRG_TRST
Testpoint_Circle_40mils
TP6 PRG_TCK
Testpoint_Circle_40mils
TP5 PRG_TDI
Testpoint_Circle_40mils
TP9
Testpoint_Circle_40mils
TP8
Testpoint_Circle_40mils
TP4 PRG_TMS
Testpoint_Circle_40mils
PRG_TDO
TP3
Testpoint_Circle_40mils
ISSUED
SmartRF06EB - XDS100v3 - FPGA
SCALE SHEET 2(7)
DWG NO. REV.
DWG
COMPANY NAME
SIZE FSCM NO.
CONTRACT NO.
Texas Instruments
A3
DRAWN
13/07/12
13/07/12
The XDS100 is connected to the EM through
connector P408. See the EM interface page
for details.
12/07/12
MAW
1.2.1
APPROVALS DATE
CHECKED
PWREN
V_USB
USBDP
EEPROM_DATA
EEPROM_CS
EEPROM_CLK
P3.3VXDS
P3.3VXDPS3.3VXDS
P3.3VXDSP3.3VXDS
P3.3VXDS
P3.3VXDS
P3.3VXDS
+1.5V
P3.3VXDS
P3.3VXDS
P3.3VXDS
+1.5V +1.5V +1.5V P1.8V P1.8V P1.8V P1.8V P3.3VXDS P3.3VXDS
VBUS
P1.8V
P1.8V
P3.3VXDS P3.3VXDS
1 2
R5
R_1K0_0402_F
1
2
3
4
5
6
7
DVBUS
D+
ID
GND
Shield
Shield
P1
USB-B_MICRO
1
2
3 4
5
6
GND
DO
CLK
93AA46B CS
VCC
DIN
U1
93AA46B
1
2
C9
C_4U7_0603_X5R_K_6
1
C15 2
C_4U7_0603_X5R_K_6
1
C19 2
C_4U7_0603_X5R_K_6
1
2
C3
C_4U7_0603_X5R_K_6
1
2
C28
C_4U7_0603_X5R_K_6
1
2
C18
C_27P_0402_NP0_J_50
1
2
C13
C_27P_0402_NP0_J_50
1
2
C29
C_100N_0402_X5R_K_10
1
2
C6
C_100N_0402_X5R_K_10
1
2
C12
C_100N_0402_X5R_K_10
1
2
C8
C_100N_0402_X5R_K_10
1
2
C17
C_100N_0402_X5R_K_10
1
2
C11
C_100N_0402_X5R_K_10
1
2
C20
C_100N_0402_X5R_K_10
1
2
C30
C_100N_0402_X5R_K_10
1
2
C5
C_100N_0402_X5R_K_10
1
2
C4
C_100N_0402_X5R_K_10
1
2
C16
C_100N_0402_X5R_K_10
1
2
C14
C_100N_0402_X5R_K_10
1
2
C31
C_100N_0402_X5R_K_10
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
USBDM
TCK
TDI
TDO
TMS
TRST
EMU_EN
EMU0
RTCK
SRST_OUT
CLK_FAIL
TVD
POD_RLS
EMU1
CBL_DIS
DTSA_BYP
ALT_FUNC
SUSPEND
PRG_TCK
PRG_TDI
PRG_TDO
PRG_TMS
PRG_TRST
PWREN
EEPROM_DATA
EEPROM_CLK
EEPROM_CS
EECLK
EECS
RESET
REF
DP
FT2232H
DM
TEST
VREGOUT
OSCO
BCBUS7
BCBUS6
BCBUS4
BCBUS3
BCBUS2
BCBUS1
VCORE
BDBUS7
BDBUS6
VREGIN
BDBUS5
BDBUS4
BDBUS3
BDBUS2
BDBUS1
VCCIO
ACBUS7
ACBUS6
ACBUS5
ACBUS3
ADBUS7
VCORE
OSCI
ADBUS6
BCBUS5
ADBUS3
VPHY
SUSPEND
GND
GND
GND
GND
GND
GND
GND
GND
ACBUS4
AGND
EEDATA
BCBUS0
VCORE
ACBUS0
BDBUS0
ACBUS2
ADBUS2
VCCIO
VCCIO
PWREN
ADBUS4
VCCIO
ADBUS1
ADBUS5
VPLL
ACBUS1
ADBUS0
U4
FT2232HL
2 1
R8
L_BEAD_102_0402
2 1
R7
L_BEAD_102_0402
1
2 D2
LED_EL19-21SYGC
2 1
R2
R_0_0402
1 2
R3
R_1K0_0402_F
2 1
R9
R_1K0_0402_F
1 2
R4
R_1K0_0402_F
2 1
R6
R_2K7_0402_F
1 2
R10
R_12K_0402_F
1 2
R28
R_270_0402_F
1
2
3 4
5
GND
IO2
IO1
NC
VCC
TPD2E001
U3
TPD2E001
1
2
3
4
Y1
X_12.000/30/30/10/20
ISSUED 3(7)
SmartRF06EB - XDS100v3 - FTDI
SCALE SHEET
DWG NO. REV.
DWG
COMPANY NAME
SIZE FSCM NO.
CONTRACT NO.
Texas Instruments
A3
DRAWN
13/07/12
13/07/12
12/07/12
MAW
1.2.1
APPROVALS DATE
CHECKED
VDD_MEASURED
LV_SDCARD_CS
LV_LED_2
LV_BTN_RESET
LV_ACC_INT1
LV_ACC_INT2
RF2.12
RF2.13
RF2.14
RF2.15_RESET
RF_VDD1
RF_VDD2
RF1.4
RF1.5
RF1.6
RF1.8
RF1.10
RF1.11
RF1.12
RF1.13
RF1.14
RF1.16_SPI_SCK
RF1.17
RF1.18_SPI_MOSI
RF1.20_SPI_MISO
RF2.5
RF2.6
RF2.8
RF2.10
RF2.11
LV_LED_4
LV_BTN_LEFT
LV_BTN_RIGHT
LV_BTN_UP
LV_LCD_MODE
LV_BTN_DOWN
LV_LCD_RESET
LV_BTN_SELECT
LV_3.3V_EN
LV_SPI_SCK
LV_LCD_CS
LV_SPI_MOSI
LV_SPI_MISO
LV_ALS_OUT
LV_ALS_PWR
LV_ACC_PWR
LV_ACC_CS
LV_LED_1
RF1.2
RF1.4
RF1.5
RF1.6
RF1.8
RF1.10
RF1.11
RF1.12
RF1.13
RF1.14
RF1.7_UART_RX
RF1.9_UART_TX
RF1.3_UART_CTS
RF2.18_UART_RTS
VDD_MEASURED
LV_BTN_RESET
VDD_SENSE
LO_VDD
LO_VDD
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
RF2.1_JTAG_TCK GND
RF_VDD2 RF2.4_JTAG_TMS
RF2.5 RF2.6
RF_VDD1 RF2.8
RF_VDD1 RF2.10
RF2.11 RF2.12
RF2.13 RF2.14
RF2.15_RESET RF2.16
RF2.17_JTAG_TDI RF2.18_UART_RTS
RF2.19_JTAG_TDO GND
RF2
SMD_HEADER_2X10
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
LV_LED_3 RF1.2
P403
PINROW_SMD_2X10_2.54MM
1
2
3
4
5
6
7
8
9
10
P406 PINROW_1X10
1
2
3
4
5
6
P412
PINROW_1X6
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
VDD_SENSE
GND
RF2.17_JTAG_TDI GND
RF2.4_JTAG_TMS GND
RF2.1_JTAG_TCK GND
GND
RF2.19_JTAG_TDO GND
RF2.15_RESET GND
GND
GND
P409
PINROW_SMD_2X10_2.54MM
1
2
3
4
5
6
7
8
9
10
RF1.15
RF1.16_SPI_SCK
RF1.17
RF1.18_SPI_MOSI
RF1.20_SPI_MISO
RF2.5
RF2.6
RF2.8
RF2.10
RF2.11
P407
PINROW_1X10
1
2
C403
C_100N_0402_X5R_K_10
1
2
C507
C_100N_0402_X5R_K_10
1
2
C404
C_100N_0402_X5R_K_10
1
2
C508
C_100N_0402_X5R_K_10
1 2
R402
R_0_0603
1 2 3 4
S606
PUSH_BUTTON_SKRAAK
1
2
J503
PINROW_SMD_1X2_2.54MM
1 2
3 4
5 6
7 8
9 10 RF2.16
P405
PINROW_SMD_2X5_2.54MM
1 2
3 4
5 6
7 8
9 10
VDD_SENSE RF2.4_JTAG_TMS
RF2.1_JTAG_TCK
RF2.19_JTAG_TDO
RF2.17_JTAG_TDI
RF2.15_RESET
P410
PINROW_SMD_2X5_1.27MM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
T_TCK RF2.1_JTAG_TCK
T_TMS RF2.4_JTAG_TMS
T_TDI RF2.17_JTAG_TDI
T_TDO RF2.19_JTAG_TDO
T_SRST RF2.15_RESET
T_EMU3 RF1.7_UART_RX
T_EMU2 RF1.9_UART_TX
T_EMU5 RF1.3_UART_CTS
T_EMU4 RF2.18_UART_RTS
T_TVD VDD_SENSE
P408
PINROW_SMD_2X10_2.54MM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
GND RF1.2
RF1.3_UART_CTS RF1.4
RF1.5 RF1.6
RF1.7_UART_RX RF1.8
RF1.9_UART_TX RF1.10
RF1.11 RF1.12
RF1.13 RF1.14
RF1.15 RF1.16_SPI_SCK
RF1.17 RF1.18_SPI_MOSI
GND RF1.20_SPI_MISO
RF1
SMD_HEADER_2X10
1 2
3 4
CURMEAS_OUTPUT
R2
R1
IN-
1.6M
GND
OUT
1.6M
INA216
IN+
U504
INA216A3
1
2
C402
C_0603
1 2
R502
R_0R15_0603_F
1
2
C401
C_0805
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
RF1.15
P404
PINROW_SMD_2X10_2.54MM
1
2
3
4
5
RF2.12
RF2.13
RF2.14
RF2.15_RESET
RF2.16
P411
PINROW_1X5
TP10
Testpoint_Circle_40mils
TP11
TESTPIN_SMALL
TP20
TESTPIN_SMALL
EM Interface /
SmartRF06EB - Level Shifters
ISSUED 4(7)
EM DEBUG CONNECTION
SCALE SHEET
DWG NO. REV.
DWG
COMPANY NAME
SIZE FSCM NO.
CONTRACT NO.
Texas Instruments
A3
DRAWN
13/07/12
13/07/12
EM CONNECTORS
10-pin ARM Cortex
JTAG Connector
RESET
Optional
RC filter
EM CURRENT MEASUREMENT
12/07/12
MAW
1.2.1
APPROVALS DATE
20-pin ARM JTAG Connector
EM <--> EB BREAKOUT and PROBE HEADERS
Rshunt = 0.15 Ohm
Gain = 100
Vin = Ishunt x Rshunt
Vout = Vin x Gain
Saturation point for INA216
-----------------------------
Vout_max = LO_VDD (2.1V to 3.6V)
Vin_max = LO_VDD / 100 = 21mV to 36mV
Ishunt_max = 140mA to 240mA
Bypass jumper block for connection
between EM and XDS100v3
CHECKED
V_USB
P3.3V
V_USB
P2.1V
V_UNREG
V_UNREG
VBAT
VBUS
P3.3VXDS
VBAT
HI_VDD
P3.3VXDS
+1.5V
P3.3VXDS P3.3VXDS
LO_VDD
3
2 1
+
B503
CR2032_SOCKET
1
2
4 3
5
6
8 7
VOUT
EN
NC
VIN
GND
NR
TPS73533
GND
U2
TPS73533
1
2
C33
C_100N_0402_X5R_K_10
1 2 3
6 5 4
V_UNREG
V_USB
S501 SMD_SWITCH_DPDT
2 1
D3
BAT54J
1 2
3
V_UNREG
R11
R_0_0402_3PORT_2-3
1
2
C32
C_100N_0402_X5R_K_10
3 2 1
4 5 6
P2.1V P3.3V
S502
SMD_SWITCH_DPDT
1
2
C503
C_2U2_0402_X5R_M_6P3VDC
1
2
C502
C_2U2_0402_X5R_M_6P3VDC
1
2
C1
C_100N_0402_X5R_K_10
1
2
C501
C_2U2_0402_X5R_M_6P3VDC
1
2
+
B501
1XAAA_KEYSTONE
1
2
+
B502
1XAAA_KEYSTONE
1
2
C2
C_18N_0603_X7R_J_50
1
2
C10
C_100N_0402_X5R_K_10
2 1
L502
L_2U2_0805_N_LQM21
1
2
C7
C_4U7_0603_X5R_K_6
2 1 L501
L_2U2_0805_N_LQM21
1
2
J502
PINROW_SMD_1X2_2.54MM
1
2
J501
PINROW_SMD_1X2_2.54MM
2 1
R403
R_10K_0402_F
1
2
C504
C_2U2_0402_X5R_M_6P3VDC
1 2
V_UNREG
R501
R_47K_0402_F
2
4
1
3
LV_3.3V_EN
ON GND
VIN VOUT
U601
TPS22902
1
2
3 4
5
SUSPEND
TLV70015
NC4
VOUT
EN
GND
VIN
U5
TLV70015
1 2
R32
R_10K_0402_F
1
2
4 3
5
6
STAT
SW
GND VIN
ON/BYP
VOUT
U501
TPS62730
1
2
3
4
6 5
7
8
9
10
11
V_UNREG
LV_3.3V_EN
FB
Thermal
VINA
PS L1
GND
PGND
L2
EN VIN
VOUT
U502
TPS63031
TP2
Testpoint_Circle_40mils
TP18
Testpoint_Circle_40mils
TP1
Testpoint_Circle_40mils
TP17
Testpoint_Circle_40mils
TP19
Testpoint_Circle_40mils
OFF
MAIN ON/OFF SWITCH
2.1V
REG
ISSUED
POWER SELECT SWITCH
SmartRF06EB -
USB (5V)
ON
5(7)
Power Supply
USB TO 1.5V (FPGA)
3.3V FOR HV PERIPHERALS
3.3V
REG
USB TO 3.3V
BATTERIES
SCALE SHEET
BATTERY or
EXTERNAL
DWG NO. REV.
DWG
COMPANY NAME
BATTERY or
EXTERNAL
SIZE FSCM NO.
CONTRACT NO.
XDS 3.3V
Texas Instruments
A3
BATTERY REGULATORS
REGULATOR
BYPASS
JUMPER
DRAWN
POWERED from USB
(XDS100v3)
XDS100v3 VOLTAGE REGULATORS
BUCK (2.1V) BUCK/BOOST (3.3V)
13/07/12
13/07/12
CONNECTOR FOR
EXTERNAL POWER
POWERED from BATTERY or
External Power Supply
2.1V FOR EM and LV PERIPHERALS
USB
12/07/12
MAW
1.2.1
DATE
Software controlled switch
for enabling the "High Voltage"
domain for board peripherals.
APPROVALS
CHECKED
HV_SPI_MOSI
HV_SPI_SCK
HV_SPI_MISO
LO_VDD
HI_VDD
HI_VDD
HI_VDD
HI_VDD
HI_VDD
LO_VDD
HI_VDD
LO_VDD
LO_VDD
LO_VDD
HI_VDD
HI_VDD
HI_VDD
HI_VDD
HI_VDD
LO_VDD
LO_VDD
LO_VDD
1
2
C601
C_1U_0402_X5R_K_6P3
NC(C2-)
NC(A3+)
NC(A2+)
NC(A1+)
V2
CAP2P
VDD
VSS
RST
CAP3P
SI
SCL
INSERT:
1 pc SIP_SOCKET_SMD_1X20_2.54MM
2 pc SIP_SOCKET_SMD_1X3_2.54MM
NC(C1-)
NC(C3-)
CAP1P
A0
CAP2N
VOUT
CAP1N
VSS
V0
VDD2
CS1B
V3
V4
V1
LCD
LCD1
DOGM128W-6_NO_CON
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
LV_SPI_SCK
LV_SPI_MOSI
LV_SPI_MISO HV_SPI_MISO
HV_SPI_MOSI
HV_SPI_SCK
LV_SDCARD_CS
LV_3.3V_EN
GND
VCCA
1A1
1A2
2DIR
2A1
2A2
2OE
1B1
2B1
VCCB
2B2
1DIR 1OE
GND
1B2
U401
SN74AVC4T245
1
2
3
4
5
6
7
8
HV_SDCARD_CS
HV_SPI_MOSI
HV_SPI_SCK
HV_SPI_MISO
VDD
N/A
GND
N/A
CS
DI/MOSI
DO/MISO
SCLK
MicroSD
SPI-Mode
J601
MICROSD-SPI
1
2
C605
C_1U_0805_X7R_K_16
1
2
C604
C_1U_0805_X7R_K_16
1
2
C607
C_1U_0805_X7R_K_16
1
2
C609
C_1U_0805_X7R_K_16
1
2
C608
C_1U_0805_X7R_K_16
1
2
C602 C_1U_0805_X7R_K_16
1
2
C603 C_1U_0805_X7R_K_16
1
2
C610
C_1U_0805_X7R_K_16
2 1
R602
R_10K_0402_F
2 1
R614
R_0_0603
1
2
C613
C_100N_0402_X5R_K_10
1 2
R601
R_10K_0402_F
1
2
C408
C_100N_0402_X5R_K_10
1 2
R612
R_10K_0402_F
1
2
C407
C_100N_0402_X5R_K_10
1 2
R13
R_10K_0402_F
1
2
3
LV_3.3V_EN
LV_3.3V_EN
Q2
2N7002F
1
2
C405
C_100N_0402_X5R_K_10
2 1
R606
R_0_0603
1
2
3
P3
SIP_SOCKET_SMD_1X3_2.54MM
2 1
R615
R_0_0603
1
2
C606
C_1U_0805_X7R_K_16
1
2
C406
C_100N_0402_X5R_K_10
2 1
R603
R_39_0603
2 1
R604
R_39_0603
2 1
R605
R_39_0603
1
2
3
P4
SIP_SOCKET_SMD_1X3_2.54MM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
HV_SPI_MOSI
HV_SPI_SCK
HV_LCD_MODE
HV_LCD_RESET
HV_LCD_CS
P2
SIP_SOCKET_SMD_1X20_2.54MM
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
LV_LCD_RESET
LV_LCD_CS
LV_LCD_MODE
LV_SDCARD_CS HV_SDCARD_CS
HV_LCD_MODE
HV_LCD_CS
HV_LCD_RESET
LV_3.3V_EN
LV_3.3V_EN
GND
VCCA
1A1
1A2
2DIR
2A1
2A2
2OE
1B1
2B1
VCCB
2B2
1DIR 1OE
GND
1B2
U402
SN74AVC4T245
TP16
Testpoint_Circle_40mils
TP14
Testpoint_Circle_40mils
TP15
Testpoint_Circle_40mils
High Voltage
Peripherals
ISSUED SCALE SHEET 6(7)
DWG NO. REV.
DWG
COMPANY NAME
SIZE FSCM NO.
CONTRACT NO.
Texas Instruments
A3
SmartRF06EB -
LCD
DRAWN
LEVEL SHIFTERS TRANSLATION :
MICROSD
13/07/12
13/07/12
U401:
LO HI
1A1 --> 1B1
1A2 --> 1B2
2A1 <-- 2B1
2A2 <-- 2B2
U402:
LO HI
1A1 --> 1B1
1A2 --> 1B2
2A1 --> 2B1
2A2 --> 2B2
12/07/12
MAW
1.2.1
APPROVALS DATE
LEVEL SHIFTERS
CHECKED
LV_ALS_OUT
LO_VDD
LO_VDD
1
2
3
4
5
6
7
8 9
10
11
12
LV_SPI_MISO
LV_SPI_MOSI
LV_ACC_INT1
LV_ACC_INT2
LV_ACC_PWR
LV_ACC_CS
LV_SPI_SCK
INT1
VDDIO
BMA250 NC
VDD
GNDIO
INT2
SDx
PS
CSB
SCx
3-AXIS
Accelerometer
GND
SDO
U602
BMA250
1
2
C614
C_100N_0402_X5R_K_10
1
2
LV_ACC_PWR
C612
C_100N_0402_X5R_K_10
1
2
C615
C_100N_0402_X5R_K_10
1
2
LV_LED_1
D601
LED_EL19-21SRC
1
2
LV_LED_4
D604
LED_EL19-21SURC
1
2
LV_LED_3
D603
LED_EL19-21SYGC
1
2 3
4
LV_ALS_PWR
Iout
GND
GND
VDD
LS601
LIGHT_SENSOR_SFH5711
1 2 3 4
S601 LV_BTN_LEFT
PUSH_BUTTON_SKRAAK
1 2 3 4
LV_BTN_RIGHT
S602
PUSH_BUTTON_SKRAAK
1 2 3 4
LV_BTN_SELECT
S603
PUSH_BUTTON_SKRAAK
1 2 3 4
LV_BTN_UP
S604
PUSH_BUTTON_SKRAAK
1 2 3 4
S605 LV_BTN_DOWN
PUSH_BUTTON_SKRAAK
1 2
R613
R_22K_0603_G
1
2
LV_LED_2
D602
LED_EL19-21UYC_A2
2 1
R608
R_680_0402_G
2 1
R609
R_680_0402_G
2 1
R610
R_680_0402_G
2 1
R607
R_820_0402_G
BUTTONS
Low Voltage
Peripherals
ISSUED
AMBIENT LIGHT SENSOR
SmartRF06EB -
YELLOW
GREEN
RED
ACCELEROMETER
SCALE SHEET
DWG NO. REV.
DWG
COMPANY NAME
SIZE FSCM NO.
CONTRACT NO.
Texas Instruments
A3
LEDS
RED-ORANGE
7(7)
Accelerometer
DRAWN
RECOMMENDED 2.3V-5.5V
Needs from 1.62V-3.6V
13/07/12
13/07/12
12/07/12
MAW
1.2.1
APPROVALS DATE
CHECKED
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH
ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety
programs, please visit www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer
use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency
interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will
be required to take whatever measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and
power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local
laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this
radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and
unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory
authorities, which is responsibility of user including its acceptable authorization.
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs including radio transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
【Important Notice for Users of this Product in Japan】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
2. Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
3. Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
http://www.tij.co.jp
【ご使用にあたっての注】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
2. 実験局の免許を取得後ご使用いただく。
3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
http://www.tij.co.jp
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in
laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks
associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end
product.
Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug
Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees,
affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.
2. You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable
regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates,
contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical)
between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to
minimize the risk of electrical shock hazard.
3. You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even
if the EVM should fail to perform as described or expected.
4. You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials.
Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the
user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and
environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact
a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the
specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or
interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the
load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures
greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include
but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the
EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please
be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable
in electronic measurement and diagnostics normally found in development environments should use these EVMs.
Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives
harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in
connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims
arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected.
Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such
as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices
which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate
Assurance and Indemnity Agreement.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
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TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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CC Debugger
User’s Guide
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Table of Contents
1 Introduction ................................................................................................................................. 3
2 Abbreviations and Acronyms .................................................................................................... 3
3 Box Contents .............................................................................................................................. 4
4 Operating Conditions of the CC Debugger .............................................................................. 4
5 Initial Steps .................................................................................................................................. 5
5.1 Installing the USB driver ........................................................................................................... 5
5.2 Supported PC Tools .................................................................................................................. 5
6 Connecting the CC Debugger to the Device ............................................................................ 6
6.1 Target Connector Details .......................................................................................................... 6
6.2 Connecting the CC Debugger to a System on Chip ................................................................. 8
6.2.1 Minimum connection for debugging ....................................................................................................................... 8
6.2.2 Minimum connection for SmartRF Studio .............................................................................................................. 8
6.2.3 Minimum connection for SmartRF Packet Sniffer .................................................................................................. 9
6.3 Connecting the CC Debugger to a Transceiver ...................................................................... 10
6.4 Connecting the CC Debugger to a CC85xx ............................................................................ 12
7 Using the CC Debugger ........................................................................................................... 13
7.1 Understanding the LED ........................................................................................................... 13
8 Updating the Firmware ............................................................................................................. 14
8.1 Updating the firmware automatically in SmartRF Studio ........................................................ 14
8.2 Updating the firmware manually in SmartRF Flash Programmer ........................................... 16
8.3 Forced boot recovery mode .................................................................................................... 17
8.4 Resurrecting the CC Debugger ............................................................................................... 17
9 Troubleshooting ....................................................................................................................... 20
10 Schematics ................................................................................................................................ 21
11 References ................................................................................................................................ 21
12 Document History ..................................................................................................................... 22
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1 Introduction
The CC Debugger is primarily used for flash programming and debugging software running on CCxxxx
8051-based System-on-Chip (SoC) devices from Texas Instruments. The PC tools available for these
purposes are the SmartRF™ Flash Programmer [9] from Texas Instruments and IAR Embedded
Workbench® for 8051 from IAR Systems [15].
When connected to the debugger, the SoC devices can be controlled directly from SmartRF™ Studio
[8]. SmartRF Studio will also be able to control supported CCxxxx RF transceivers (CC2520, CC2500,
CC110x, CC11xL, CC112x, CC120x) when they are connected to the debugger as explained in
chapter 6.3.
In addition, CC Debugger is used for configuring the CC85xx devices with PurePath Wireless
Configurator [12] and controlling them with PurePath Wireless Commander [13].
2 Abbreviations and Acronyms
CSn Chip Select (active low)
DC Debug Clock
DD Debug Data
DUT Device Under Test
GND Ground
LED Light Emitting Diode
MISO Master In Slave Out
MOSI Master Out Slave In
RF Radio Frequency
SCLK Serial Clock
SoC System on Chip
SPI Serial Peripheral Interface
USB Universal Serial Bus
Vdd Positive voltage on target
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3 Box Contents
1 x CC Debugger
1 x USB-A to Mini-B USB cable
1 x 10-pin flat cable with 2x5 2.54 mm connector
1 x 10-pin flat cable with 2x5 1.27 mm connector
1 x Converter board 2.54 mm – 1.27 mm connector
Documentation
4 Operating Conditions of the CC Debugger
Minimum target voltage: 1.2 Volt
Maximum target voltage: 3.6 Volt
Operating temperature: 0C to 85C
Regulated voltage on CC Debugger: 3.3 Volt
Maximum target current (*): 200 mA (*)
Supported Operating Systems: Microsoft® Windows® 2000
Windows XP SP2/SP3 (32 bit versions)
Windows Vista® (32 & 64 bit)
Windows 7 (32 & 64 bit)
(*) Only applicable if the target is powered from the CC Debugger
Figure 1 - CC Debugger connected to a SoC Battery Board with a CC2530EM
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5 Initial Steps
5.1 Installing the USB driver
To get the required USB driver for the CC Debugger, it is necessary to install one of the tools listed
below:
SmartRF Studio www.ti.com/tool/smartrftm-studio
SmartRF Flash Programmer www.ti.com/tool/flash-programmer
SmartRF Packet Sniffer www.ti.com/tool/packet-sniffer
PurePath Wireless Configurator www.ti.com/tool/purepath-wl-cfg
PurePath Wireless Commander www.ti.com/tool/purepath-wl-cmd
Alternatively, you can download “Cebal – CCxxxx Development Tools USB Driver for Windows x86
and x64” [4] which is a standalone installer including only the device driver.
After having installed the driver, connect the CC Debugger to the PC. The USB driver will be installed
automatically. You can quickly check that the debugger has been associated correctly with the USB
device driver by opening the Windows Device Manager. The debugger should appear as a “Cebal
controlled device”.
Figure 2 - Verify correct driver installation
For further details or troubleshooting the driver installation process, please refer to “DN304 – CCxxxx
Development Tools USB Driver Installation Guide” [5].
5.2 Supported PC Tools
Currently, the CC Debugger can be used together with the following PC Tools
IAR Embedded Workbench for 8051 In circuit debugging of system-on-chips
SmartRF Flash Programmer Flash programming of system-on-chips
SmartRF Studio RF testing of radio devices (transceivers and SoCs)
SmartRF Packet Sniffer Packet sniffing with selected radio devices
PurePath Wireless Configurator Programming of CC85xx devices
PurePath Wireless Commander Advanced control of CC85xx devices
The debugger will operate as the interface between the RF device and the tools listed above. Please
ensure correct connection between the device and CC Debugger before starting to use the tools.
The connection of the device to the CC Debugger will be covered in the next chapter.
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6 Connecting the CC Debugger to the Device
6.1 Target Connector Details
The target connector, located on the lateral side of the debugger, is a 10-pin 2x5 2.54 mm pitch
connector with a direction coded plastic guide. Suggested matching (male) surface mounted headers
would be 95278-101A10LF from FCI or BB02-HP from GradConn.
Figure 3 - Placement of Target Connector Pins
The adapter board, which has a 10-pin 2x5 1.27 mm pitch connector, has the same pin placement.
Suggested matching (male) surface mounted headers would be 20021121-000-10C4LF from FCI or
FTS-105-01-F-DV from Samtec.
Figure 4 - Placement of Target Connector Pins on Adapter Board
The pin-out of the target connector is shown in Figure 5. Note that not all of these pins need to be
connected to the target device for programming and debugging. Only Vdd, GND, DD, DC and RESET
are required for System on Chips. The other pins are optional and/or for special features.
Pin 1
Pin 2
Pin 1
Pin 2
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1 2
3 4
5 6
7 8
9 10
GND
DC (Debug Clock)
CSn (SPI Chip Select)
RESETn
3.3V (from debugger)
Target Voltage Sense
DD (Debug Data)
SCLK (SPI Clock)
MOSI (SPI Data Out)
MISO (SPI Data In)
Figure 5 - Target Connector Pin-out
Please note the concept with the target voltage sense signal. This signal is used by the level
converters on the CC Debugger to handle different voltage levels on the target board and the
debugger. Pin 2 on the target connector must be connected to Vdd on the target board.
USB
Controller
Level
Converter
Vdd from
target
CC Debugger Vdd (local)
TARGET
Target
Connector
Figure 6 - Voltage from target to CC Debugger
Alternatively, it is possible to power the target by connecting pin 9 to Vdd on the target. In that case,
the CC Debugger will supply 3.3V to the target.
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6.2 Connecting the CC Debugger to a System on Chip
6.2.1 Minimum connection for debugging
For successful debugging of a TI 8051-based RF System on Chip, connect the two debug signals
Debug Data (DD) and Debug Clock (DC) and the reset signal RESETn to the device. Note that DD is a
bidirectional signal. In addition, the CC Debugger must be connected to GND and Vdd on the board.
Vdd is used as an input to the level shifters on the CC Debugger, thus allowing a different operating
voltage on the target than internally on the debugger.
For CC111x, CC251x, CC243x, CC253x and CC254x, except CC2544 and CC2545, connect the DD
signal to pin P2.1 and DC to pin P2.2.
For CC2544, connect the DD signal to P1.3 and DC to P1.2.
For CC2545, connect the DD signal to P1.3 and DC to P1.4.
Note that it is possible to power the target board from the debugger by connecting the 3.3V signal on
pin 9 on the connector to the target board.
1 2
3 4
5 6
7 8
9 10
GND
DC (Debug Clock)
RESETn
3.3V from debugger. Can
optionally be used to
power the target board
DD (Debug Data)
P2.2 SoC
P2.1
RESETn
Vdd
GND
Vdd
CC Debugger
Connector
CCxxxx
System-on-Chip
NOTE 2
Vdd
NOTE 1
10 kΩ
2.7 kΩ
1 nF
Figure 7 - Minimum connection for debugging of 8051 SoC
Note 1: Some early revisions of certain SoCs (CC2430, CC2510 and CC1110) needed an external
pull-up to avoid unwanted transitions on the debug clock line during chip reset – thus inadvertently
setting the device in debug mode. All new revisions of all SoCs now have an internal pull-up on P2.2,
so this external component is not required.
Note 2: The RESETn pin is sensitive to noise and can cause unintended reset of the chip. For reset
lines susceptible to noise, it is recommended to add an external RC filter. Please refer to the
respective SoC datasheet and reference designs for recommended RESET circuitry. The CC
Debugger supports slow transitions on the reset line, using a 2 ms delay between any transition on the
RESET line and other transitions on the DC and/or DD lines.
6.2.2 Minimum connection for SmartRF Studio
Use the same connection as for debugging the SoC.
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6.2.3 Minimum connection for SmartRF Packet Sniffer
In order to use the packet sniffer capabilities of the CC Debugger, it is also necessary to connect the
SPI bus to the SoC. The SPI interface is used by the CC Debugger for reading the captured RF
packets from the SoC.
1 2
3 4
5 6
7 8
9 10
GND
DC (Debug Clock)
RESETn
3.3V from debugger. Can
optionally be used to
power the target board
DD (Debug Data)
P2.2 SoC
P2.1
RESETn
Vdd
GND
Vdd
CC Debugger
Connector
CCxxxx
System-on-Chip
2.7 kΩ
1 nF
CSn
SCLK
MOSI
MISO
P1.7
P1.6
P1.5
P1.4
Figure 8 - Connection to SoC to enable Packet Sniffing
Note that the packet sniffer will overwrite the flash on the SoC with special packet capture firmware.
Note concerning the SPI interface to the SoC used for packet sniffing
All of the current TI RF SoCs can be configured to operate as SPI slaves, with the SPI signals (CS,
SCLK, MISO and MOSI) going to one of the USART peripherals. The packet sniffer application will
program the SoC with firmware that configures one of the USART peripherals in order to communicate
with the CC Debugger. The firmware can use any of the four possible pin configurations (USART 0 or
1, pin out alternative 1 or 2). However, only a subset is currently supported:
USART0, alt 1 USART0, alt 2 USART1, alt 1 USART1, alt 2
CC243x - - - OK
CC253x/CC254x - - - OK
CC111x OK - - OK
CC251x OK - - OK
Table 1 - Supported SPI connections (marked OK)
USART0, alt 1 USART1, alt 2
SCLK P0.5 P1.5
CS P0.4 P1.4
MOSI P0.3 P1.6
MISO P0.2 P1.7
Table 2 - USART pin out details
In case of multiple supported interfaces, the Packet Sniffer application will let you choose which
interface to use.
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6.3 Connecting the CC Debugger to a Transceiver
The SPI interface on the CC Debugger can be used to interface many of the CCxxxx transceivers and
control them from SmartRF Studio. The transceivers/transmitters/receivers currently supported are:
CC1100
CC1101
CC1120
CC1121
CC1125
CC1175
CC110L
CC113L
CC115L
CC1200
CC1201
CC2500
CC2520
Note that the CC Debugger operates as the SPI Master. In a multi master system, it is necessary to
make sure the debugger output signals (DC, DD, CSn, SCLK, MOSI and RESETn) do not interfere
with the other SPI master on the board. The other SPI master would typically be the microcontroller on
the board.
The connection diagrams below show the interconnection between the debugger and the various
supported transceivers.
1 2
3 4
5 6
7 8
9 10
GND
DC
RESETn
3.3V from debugger. Can
optionally be used to
power the target board
DD
GPIO3
VREG_EN
RESETn
Vdd
GND
Vdd
CC Debugger
Connector
CC2520
CSn
SCLK
MOSI
MISO
SO
SI
SCLK
CSn
Figure 9 - CC Debugger connected to CC2520
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1 2
3 4
5 6
7 8
9 10
GND
DC
RESETn
3.3V from debugger. Can
optionally be used to
power the target board
DD
GPIO2
GPIO0
RESETn
Vdd
GND
Vdd
CC Debugger
Connector
CC112x
CC1175
CC120x
CSn
SCLK
MOSI
MISO
SO
SI
SCLK
CSn
Figure 10 - CC Debugger connected to CC112x/CC1175/CC120x
1 2
3 4
5 6
7 8
9 10
GND
DC
3.3V from debugger. Can
optionally be used to
power the target board
DD
GDO2
GDO0
Vdd
GND
Vdd
CC Debugger
Connector
CC110x
CC11xL
CC2500
CSn
SCLK
MOSI
MISO
SO
SI
SCLK
CSn
Figure 11 - CC Debugger connected to CC110x/CC11xL/CC2500
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6.4 Connecting the CC Debugger to a CC85xx
In order to configure the CC85xx devices (i.e. program the flash on the device) with PurePath Wireless
Configurator, the device’s SPI interface must be connected to the CC Debugger as shown in the figure
below.
1 2
3 4
5 6
7 8
9 10
GND
RESETn
3.3V from debugger. Can
optionally be used to
power the target board
RESETn
Vdd
GND
Vdd
CC Debugger
Connector
CC85XX
CSn
SCLK
MOSI
MISO
MISO
MOSI
SCLK
CSn
Figure 12 - CC Debugger connected to CC85XX
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7 Using the CC Debugger
After having connected the debugger to the target device, the debugger can be powered up by
plugging in the USB cable.
The debugger will immediately start a device detection process, looking for all known devices. If no
devices are detected, the LED will be RED. If a device is detected, the LED will be GREEN.
If the LED is GREEN, it is possible to start using the debugger together with one of the supported PC
tools.
7.1 Understanding the LED
OFF
The debugger has no power or there is no valid firmware on the debugger.
Make sure the debugger is properly powered via the USB cable or try to
resurrect the debugger using the method described in chapter 8.4.
AMBER (BOTH LEDS ON)
The debugger is powered, but there is no valid firmware. Try to resurrect
the debugger using the method described in chapter 8.4.
RED LED BLINKING
The Debugger is in Boot Recovery Mode.
The debugger will briefly enter this state while the firmware is being
upgraded (see chapter 8). The board might also enter this state if the
firmware is corrupt or if the user has manually forced to board to start up in
the special “boot recovery mode” (section 8.3).
To go out of the state, reset the debugger by pressing the “Reset” button
or by power-cycling the device. If the LED is still blinking, reprogram the
unit by using the Flash Programmer Application.
RED LED ON
No device detected. This might be due to old firmware on the CC
Debugger. New devices might not be supported with the current firmware
on the debugger. Please refer to chapter 8 for the firmware upgrade
procedure.
There might also be a problem with the hardware connection. Check the
connection to device and make sure the target board is properly powered
and that Vdd on the target board is connected to pin 2 on the debug
connector. Press and release the reset button to retry the target device
detection
GREEN LED ON
The target device has been properly detected. It is possible to start using
the supported tools (see chapter 5.2).
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8 Updating the Firmware
In order to make sure the CC Debugger works seamlessly with your device, it is important that it has
the latest and greatest firmware. This chapter will describe how you can upgrade the firmware
automatically from SmartRF Studio or manually from SmartRF Flash Programmer. The chapter will
also describe how to resurrect a seemingly broken debugger.
8.1 Updating the firmware automatically in SmartRF Studio
Updating the firmware on the CC Debugger can be done automatically by SmartRF Studio. Please
follow the few steps described below.
1. Start SmartRF Studio.
2. Disconnect the debugger from any target board, and connect it to the PC via the USB cable.
The debugger will appear in the list of connected devices in the lower part of the SmartRF
Studio startup panel.
Figure 13 - Auto FW upgrade
3. Double click on the item in the list, and a new window will appear.
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Figure 14 - Auto FW upgrade
4. Click "Yes" and let SmartRF Studio do the rest.
Figure 15 - Auto FW upgrade
5. Click "Done" and you're good to go. The device should appear in the list of connected devices,
now showing the new firmware revision.
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8.2 Updating the firmware manually in SmartRF Flash Programmer
You can also update the firmware manually using SmartRF Flash Programmer. You can use this
method if you like to have full control of the firmware image to be programmed on the controller of the
debugger (i.e. programming custom firmware or old firmware revisions).
1. Start SmartRF Flash Programmer and select the tab called “EB application (USB)”. This tab
will let you program compatible firmware on the CC Debugger (or evaluation boards) via the
USB interface (i.e. no external programming device required).
2. Disconnect the debugger from any target board, and connect it to the PC via the USB cable.
The debugger will appear in the list of connected devices. Chip type will be listed as N/A.
3. Select the flash image you want to program on the debugger. Normally, you would select:
C:\Program Files (x86)\Texas Instruments\SmartRF Tools\Firmware\CC
Debugger\cebal_fw_srf05dbg.hex1
4. Select the action “Erase, program and verify”
5. Click the “Perform actions” buttons. The programming procedure will start. Note that this will
take several seconds.
6. The CC Debugger will reappear in the list of connected devices, now showing the new
firmware revision in the device list.
7. Done!
1 Assuming default installation path of SmartRF Flash Programmer.
1
2
4
5
3
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8.3 Forced boot recovery mode
If, for some reason, the firmware update fails and the CC Debugger appears to be non responsive,
there is a way to force the board to only run the bootloader and stop all further execution. In this mode,
no attempts will be made to start the firmware, and the board will only allow the user to perform a new
firmware upgrade over USB.
Disconnect the debugger from any power source and open the plastic enclosure.
Figure 16 - Internal view of CC Debugger
Short circuit the pins as depicted in Figure 17: P1.6 on the CC2511 must be connected to GND during
the power-on reset to enter boot recovery mode.
Figure 17 - Short-circuit pins for boot recovery mode
When reconnecting the USB cable, the LED will start to blink with a RED light. This indicates that the
bootloader is running and that the debugger is in boot recovery mode.
At this point, follow the same firmware programming steps as describe at the beginning of this chapter.
Please also note that the boot recovery mode can be used as a check to verify that the bootloader on
the debugger is working.
8.4 Resurrecting the CC Debugger
If the CC Debugger appears to be completely dead when applying power, there is a way to “unbrick”
the board. The method consists of reprogramming the bootloader on the debugger using the debug
connector inside the box. This will require an extra programming device.
When opening the box, locate the debug connector header next to the target connector. Connect this
header to another CC Debugger (see Figure 18) or to a SmartRF05EB (see Figure 19). When using
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SmartRF05EB, connect a 10-pin flat cable from the “Ext SoC Debug” plug (P3) on the EB to the “USB
Debug” plug (P2) on the CC Debugger. The dead debugger needs power, so connect the USB cable.
Turn on the SmartRF05EB or debugger - it should detect the USB Controller (CC2511) on the
debugger.
Figure 18 - Programming the bootloader on the CC Debugger using another CC Debugger
Figure 19 - Programming the bootloader on the CC Debugger using SmartRF05EB
Next, use the SmartRF Flash Programmer to program the bootloader on the debugger. Follow these
five steps (illustrated in Figure 20 below):
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1. After starting the application, first select “Program Evaluation Board” in the “What do you want
to program?” drop down box, then select the “EB Bootloader” tab.
2. In the upper left corner, select device: Use SmartRF05EB regardless of the device being used
to program the debugger. I.e. select SmartRF05EB both when you are using a CC Debugger
and when you are using a SmartRF05EB for the resurrection.
3. Next, select which flash image to program. The bootloader image is included when installing
the flash programmer and it is usually located at “C:\Program Files (x86)\Texas
Instruments\SmartRF Tools\Firmware\CC Debugger”.
4. It is also necessary to give the debugger a unique ID number – any 4 digit number will work.
This number is used by the driver on the PC to uniquely identify devices if more than one
debugger is connected at the same time.
5. Select “Erase, program and verify”
6. Press the “Perform Actions” buttons. The firmware upgrade takes a few seconds.
Figure 20 - SmartRF Flash Programmer - Updating the bootloader
Once the bootloader is programmed, you might be asked to install a USB driver on the PC. Just follow
the same procedure as when the debugger was connected to the PC the first time (see chapter 5).
The RED LED on the debugger should now be blinking, indicating that the bootloader is running but
that no application has been loaded. If the RED LED is off, there is probably something wrong with the
hardware. The debugger firmware can now be programmed directly over USB by following the
procedure in either chapter 8.1 or 8.2.
1
2
4
5
6
3
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9 Troubleshooting
Q1 Help! The debugger does not detect the SoC. What should I do?
A1 There are several things to check.
Upgrade the firmware. Many CC Debuggers have old firmware that will not automatically
detect newer devices, like CC2543/44/45. Refer to chapter 8 for further instructions.
Check that the cable is oriented correctly and that the pins are connected to the right signals
on the debugger.
Check that the debugger gets power from the target (i.e proper connection of the Target
Voltage Sense signal). This is required in order for the level converters on the debugger to
work.
Check that ground on the target is connected to ground on the debugger. This is normally
achieved through the target connector. Note that since the ground planes are the same, please
be aware of any adverse effects caused by different ground planes on the target and on the
PC (grounded via USB cable).
Check that the cable is not broken. Especially the small flat cable is prone to stop working if
handled a lot or being bent and stretched beyond normal operating conditions.
Q2 Does IAR EW8051 support the CC Debugger as debugging device?
A2 Yes – but make sure you have an up to date version of IAR with the new debug driver plug-in
from Texas Instruments. You will need version 7.51A or higher.
Q3 Can the debugger be used as an interface to the RF device for packet sniffing?
A3 Yes, this is supported for selected devices. Use the same interconnection as in the diagrams in
chapter 6.
Q4 Is there a way to remove the plastic casing without damaging it?
A4 Yes, there is. Hold the bottom piece of the plastic in one hand. With your other hand, take a
firm grip on the long lateral sides of the upper part of the plastic and squeeze while moving the
upper part away from the bottom. The two parts should separate from each other.
To reassemble the plastic, just click the two pieces together.
Q5 Is this a Mini or a Micro USB plug?
A5 Mini USB type A.
Q6 I have two CC Debuggers with the same EB ID, and I’m unable to use them together. What do
I do?
A6 Two EBs with the same EB ID cause a driver conflict. The solution is to resurrect one of the
CC Debuggers and give it a new EB ID.
1. Connect one CC Debugger to your computer
2. Connect the CC Debugger you want to resurrect to a separate power source (e.g. another
computer or a USB charger).
3. Follow the steps for resurrecting the CC Debugger, described in section 8.4.
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10 Schematics
See last page or refer to the complete bundle including gerber files, schematics and layout here [3].
11 References
[1] CC-Debugger product web site
www.ti.com/tool/cc-debugger
[2] CC-Debugger Quick Start Guide
www.ti.com/lit/swru196
[3] CC-Debugger Layout and Schematics
www.ti.com/lit/zip/swrr105
[4] Cebal – CCxxxx Development Tools USB Driver for Windows x86 and x64
www.ti.com/lit/zip/swrc212
[5] DN304 – CCxxxx Development Tools USB Driver Installation Guide
www.ti.com/lit/swra366
[6] Texas Instruments Support
support.ti.com
[7] Texas Instruments Low Power RF Online Community
www.ti.com/lprf-forum
[8] SmartRF Studio
www.ti.com/tool/smartrftm-studio
[9] SmartRF Flash Programmer
www.ti.com/tool/flash-programmer
[10] SmartRF Packet Sniffer
www.ti.com/tool/packet-sniffer
[11] SmartRF Flash Programmer User Manual
www.ti.com/lit/swru069
[12] PurePath Wireless Configurator
www.ti.com/tool/purepath-wl-cfg
[13] PurePath Wireless Commander
www.ti.com/tool/purepath-wl-cmd
[14] SoC Battery Board product web site
www.ti.com/tool/soc-bb
[15] IAR Embedded Workbench for 8051
www.iar.com/ew8051
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12 Document History
Revision Date Description/Changes
G 2013-01-15 Chapter 9: Added how to solve problem with CC Debuggers having the same EB ID.
F 2013-06-20
CC1100, CC1101, CC2500, and CC1200 are now also supported by the debugger.
Corrected typo in chapter 6.2.1: DD to pin P2.1 (not P2.2) and DC to pin P2.2 (not
P2.1) for all SoCs except CC2544 and CC2545. Added debug pin-out for CC2545.
Corrected pin-out in figure 10 and 11 (DC to GPIO2/GDO2, DD to GPIO0/GDO0).
Added link to layout and gerber files.
E 2012-03-01 Corrected typo in chapter 6.2.1. Special debug pin-out for CC2544, not CC2543.
D 2012-02-22
Added information about connections for programming of CC85xx devices. Updated
info about connections for supported transceivers. Updated driver installation
information and added more details about firmware upgrade. Describe what it means
when the LED is amber. Updated reference links.
C 2010-09-19 Added more information about how to upgrade the firmware.
B 2010-02-25
Fixed erroneous description of interconnection between CC Debugger and CC2520.
The VREG_EN signal shall be connected to pin 4 on the target connector, not pin 3.
A 2010-02-11
Added more details about the powering options.
Added more information about connection options.
- 2009-05-05 First revision.
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EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
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Material Safety Data Sheet
A-4 Hardener
1
1. Chemical Product and Company Identification
Product Name: A-4 Hardener
Product Description: Liquid Epoxy Hardener
Company: Cast-Coat, Inc. 354 West Street W. Bridgewater, MA 02379
Telephone: 1-800-527-4502 or 1-508-587-4502
Emergency Contact: Chemtrec: (domestic) 1-800-424-9300 (international) 1-703-527-3887
2. Composition / Information on Ingredients
Components CAS # %
3,3’-oxybis(ethyleneoxy)bis(propylamine) 4246-51-9 98
2-(2-(3-aminopropoxy)ethoxy)ethanol 112-33-4 1
3. Hazards Identification
Eye Contact: Corrosive to the eyes and may cause severe damage, including blindness. Vapors may be
irritating.
Skin Contact: Corrosive to the skin. May cause skin sensitization. May be toxic if absorbed through the skin.
Inhalation: Vapors / mists may be corrosive to the upper respiratory tract. Repeated or prolonged exposure
can result in lung damage.
Ingestion: Not expected to be a relevant route of exposure, however, corrosive and may cause severe and
permanent damage to the mouth, throat and stomach.
Aggravated Medical Conditions: Pre-existing eye, skin and respiratory disorders may be aggravated by
exposure to this product. Pre-existing respiratory and skin allergies may
be increased from exposure to this product.
4. First Aid Measures
General Advise: Good practice requires that gross amounts of any chemical be removed from the skin as
soon as practical, especially before eating or smoking.
Eye Contact: Immediately flush eyes with water for at least 30 minutes. Seek medical attention.
Skin Contact: Remove contaminated clothing and wipe excess from skin. Promptly wash with soap and
water for 15 minutes. Seek medical attention if irritation persists.
Inhalation: Move to fresh air and provide oxygen if necessary.
Ingestion: Rinse mouth with water. If conscious, give small quantities of water to drink. Do not
induce vomiting. If vomiting occurs, keep victim’s head below hips to prevent vomit from
entering lungs. Seek medical attention.
Material Safety Data Sheet
A-4 Hardener
2
5. Fire-Fighting Measures
Flashpoint: 139’ C
Autoignition Temperature: 260’ C
Flammability limits in air - lower: 1.1 % (V)
Flammability limits in air – upper: 4.5 % (V)
Extinguishing Media: Carbon dioxide (CO2), dry chemical, water fog or “alcohol foam“
Protective Equipment: Do not enter confined space without full bunker gear (helmet with
face shield, bunker coats, gloves and rubber boots). Use self
contained, positive pressure breathing apparatus.
Specific Hazards: Decomposition and combustion products may be toxic. Containers
exposed to intense heat should be cooled with water to avoid vapor
pressure buildup.
6. Accidental Release Measures
Personal Protection: Eyes - Wear splash proof chemical goggles.
Skin - Wear impervious gloves and protective clothing to prevent skin
contact.
Inhalation: Use NIOSH approved respirator suitable for organic vapors.
Environmental Concerns: Construct a dike to prevent from entering sewers, rivers and waterways.
Clean Up: Soak up residue with absorbent material and shovel into non leaking containers.
7. Handling and Storage
Handling: Good practice requires that gross amounts of any chemical be removed from the skin as soon as
practical, especially before eating or smoking. Wear splash proof chemical goggles, impervious
gloves and protective clothing to prevent skin contact. Emergency eye wash stations should be
readily accessible.
Ventilation: Provide effective mechanical exhaust. Wear NIOSH approved respirator suitable for organic
vapors in the absence of ventilation.
Storage: Store in a cool, dry location in tightly sealed containers. Keep away from open flame and high
temperatures. Do not pressurize containers to empty them.
Material Safety Data Sheet
A-4 Hardener
3
8. Exposure Controls/Personal Protection
Engineering Controls: Provide effective mechanical exhaust to ensure concentration levels are
below exposure limits.
Respiratory Protection: Wear NIOSH approved air purifying respirator in the absence of ventilation.
Eye Protection: Wear safety goggles or safety glasses with side shields. Emergency eye
wash stations should be readily accessible.
Skin Protection: Wear chemical resistant impervious gloves and protective clothing such as
an apron to prevent skin contact.
9. Physical and Chemical Properties
Appearance: Liquid
Color: Clear to Amber
Odor: Amine
Specific Gravity: 0.98
Vapor Pressure: < 1.00 mmHg at 20’ C
Solubility in Water: Miscible
Flashpoint: 139’ C
VOC Content: < 0.1% by weight
10. Stability and Reactivity
Stability: Stable under normal conditions.
Materials to Avoid: Avoid heat, flame and strong oxidizing agents.
Hazardous Decomposition Products: Carbon monoxide, Carbon dioxide, Nitrous oxide.
Comments: Hazardous polymerization will not occur.
11. Toxicological Information
3,3’-oxybis(ethyleneoxy)bis(propylamine), 2-(2-(3-aminopropoxy)ethoxy)ethanol:
Oral: LD50 3,160 mg / kg species: rat
Dermal: LD50 > 2,150 mg / kg species: rat
Material Safety Data Sheet
A-4 Hardener
4
12. Ecological Information
Inherent Biodegradability: Zahn-Wellens - < 20 % (Difficult to eliminate)
Golden Orfe, Static 96 hour LC50 - 220-460 mg / L (Practically nontoxic)
Daphnid, Static 48 hour EC50 - 220 mg / L (Practically nontoxic)
Acute algal toxicity, 72 hour EC50 - 69 mg / L (Test rating not found)
Toxicity to bacteria - EC50, (17H) 220 mg / L (Test rating not found)
13. Disposal Considerations
Comments: Dispose of in accordance with federal, state and local regulations. Incinerate or bury in a RCRA
licensed facility. Do not discharge into drains, waterways, sewers, or groundwater.
RCRA: D002
14. Transportation Information
DOT: UN 2735
Amines, Liquid, Corrosive, N.O.S.
(Trioxatridecanediamine)
8, II
ERG - 153
IMDG: UN 2735
Amines, liquid, Corrosive, N.O.S.
(Trioxatridecanediamine)
8, II
IATA: UN 2735
Amines, Liquid, Corrosive, N.O.S.
(Trioxatridecanediamine)
8, II
15. Regulatory Information
TSCA : All ingredients are listed or exempt
HSC Classification: Irritating material, Sensitizing material, Corrosive material
Sara Section 312 Hazard Classification: Chronic health hazard, Acute health hazard
Sara Section 313: None
California prop. 65: None
Hazard Ratings: Health Fire Reactivity
3 1 0
WHMIS Classification: D-2A, D-2B, Class E – Corrosive material
Material Safety Data Sheet
A-4 Hardener
5
16. Other Information
All information appearing herein is based upon data obtained from the manufacturer and / or recognized
technical sources. While the information is believed to be accurate, Cast-Coat makes no representations as to
its accuracy or sufficiency. Conditions of use are beyond the control of Cast-Coat and therefore users are
responsible to verify this data under their own operating conditions to determine whether the product is suitable
for their purposes. Cast-Coat, Inc. assumes no responsibility for injury from the use of the product described
herein.
Prepared by: Robert S. Lothrop
Title: Technical Director
Revision: 04/18/2012
1 / 5
Revision Date November 2011
Revision 3
SDS No. 16447
SAFETY DATA SHEET
ARALDITE FUSION HARDENER
SECTION 1: IDENTIFICATION OF THE SUBSTANCE/MIXTURE AND OF THE COMPANY/UNDERTAKING
1.1. Product identifier
Product name ARALDITE FUSION HARDENER
Product No. 808300, 808409, 808416, 808423
1.2. Relevant identified uses of the substance or mixture and uses advised against
1.3. Details of the supplier of the safety data sheet
Supplier BOSTIK LIMITED
COMMON ROAD
STAFFORD
STAFFORDSHIRE
ST16 3EH
+44 1785 272625
sds.uk@bostik.com
1.4. Emergency telephone number
SECTION 2: HAZARDS IDENTIFICATION
2.1. Classification of the substance or mixture
Classification (1999/45/EEC) Xi;R36/38.
2.2. Label elements
Labelling
Irritant
Risk Phrases
R36/38 Irritating to eyes and skin.
Safety Phrases
S2 Keep out of the reach of children.
S24/25 Avoid contact with skin and eyes.
S26 In case of contact with eyes, rinse immediately with plenty of water and seek
medical advice.
S36/37/39 Wear suitable protective clothing, gloves and eye/face protection.
S46 If swallowed, seek medical advice immediately and show this container or
label.
S56 Dispose of this material and its container to hazardous or special waste
collection point.
2.3. Other hazards
SECTION 3: COMPOSITION/INFORMATION ON INGREDIENTS
3.2. Mixtures
2 / 5
SDS No. 16447
ARALDITE FUSION HARDENER
1,8-DIAZABICYCLO[5.4.0]UNDEC-7-ENE 1-5%
CAS-No.: 6674-22-2 EC No.: 229-713-7
Classification (67/548/EEC)
Xn;R22.
C;R34.
R52/53.
Classification (EC 1272/2008)
Not classified.
BIS(2-DIMETHYLAMINOETHYL)ETHER 1-5%
CAS-No.: 3033-62-3 EC No.: 221-220-5
Classification (67/548/EEC)
T;R23/24.
Xn;R22.
C;R35.
Classification (EC 1272/2008)
Not classified.
TRIETHYLENETETRAMINE, PROPOXYLATED 5-10%
CAS-No.: 26950-63-0 EC No.: 500-055-5
Classification (67/548/EEC)
Xi;R38,R41.
Classification (EC 1272/2008)
Not classified.
The Full Text for all R-Phrases and Hazard Statements are Displayed in Section 16.
SECTION 4: FIRST AID MEASURES
4.1. Description of first aid measures
Inhalation
Remove victim immediately from source of exposure. Move the exposed person to fresh air at once. Get medical attention.
Ingestion
DO NOT induce vomiting. Get medical attention immediately.
Skin contact
Promptly wash contaminated skin with soap or mild detergent and water. Promptly remove clothing if soaked through and wash as above.
Get medical attention if irritation persists after washing.
Eye contact
Rinse the eye with water immediately. Continue to rinse for at least 15 minutes and get medical attention.
4.2. Most important symptoms and effects, both acute and delayed
4.3. Indication of any immediate medical attention and special treatment needed
SECTION 5: FIREFIGHTING MEASURES
5.1. Extinguishing media
Extinguishing media
This product is not flammable. Use fire-extinguishing media appropriate for surrounding materials. Use: Foam, carbon dioxide or dry
powder.
5.2. Special hazards arising from the substance or mixture
5.3. Advice for firefighters
SECTION 6: ACCIDENTAL RELEASE MEASURES
6.1. Personal precautions, protective equipment and emergency procedures
6.2. Environmental precautions
6.3. Methods and material for containment and cleaning up
3 / 5
SDS No. 16447
ARALDITE FUSION HARDENER
Absorb in vermiculite, dry sand or earth and place into containers.
6.4. Reference to other sections
SECTION 7: HANDLING AND STORAGE
7.1. Precautions for safe handling
Avoid spilling, skin and eye contact.
7.2. Conditions for safe storage, including any incompatibilities
Store at moderate temperatures in dry, well ventilated area.
7.3. Specific end use(s)
SECTION 8: EXPOSURE CONTROLS/PERSONAL PROTECTION
8.1. Control parameters
Ingredient Comments
WEL = Workplace Exposure Limits
8.2. Exposure controls
Protective equipment
Engineering measures
Provide adequate ventilation.
Respiratory equipment
If ventilation is insufficient, suitable respiratory protection must be provided.
Hand protection
Protective gloves must be used if there is a risk of direct contact or splash.
Eye protection
Wear splash-proof eye goggles to prevent any possibility of eye contact.
Hygiene measures
Wash promptly if skin becomes contaminated. Wash at the end of each work shift and before eating, smoking and using the toilet.
SECTION 9: PHYSICAL AND CHEMICAL PROPERTIES
9.1. Information on basic physical and chemical properties
Appearance Liquid
Colour Light (or pale). Yellow.
Odour Slight odour.
Solubility Insoluble in water
Relative density 1.14
Flash point (°C) 145 PM Closed cup.
9.2. Other information
SECTION 10: STABILITY AND REACTIVITY
10.1. Reactivity
10.2. Chemical stability
Stable under normal temperature conditions.
10.3. Possibility of hazardous reactions
10.4. Conditions to avoid
10.5. Incompatible materials
10.6. Hazardous decomposition products
4 / 5
SDS No. 16447
ARALDITE FUSION HARDENER
SECTION 11: TOXICOLOGICAL INFORMATION
11.1. Information on toxicological effects
Skin contact
Irritating to skin.
Eye contact
Irritating to eyes.
SECTION 12: ECOLOGICAL INFORMATION
Ecotoxicity
Not regarded as dangerous for the environment.
12.1. Toxicity
12.2. Persistence and degradability
12.3. Bioaccumulative potential
12.4. Mobility in soil
12.5. Results of PBT and vPvB assessment
12.6. Other adverse effects
SECTION 13: DISPOSAL CONSIDERATIONS
13.1. Waste treatment methods
Dispose of waste and residues in accordance with local authority requirements.
SECTION 14: TRANSPORT INFORMATION
General The product is not covered by international regulation on the transport of dangerous goods (IMDG, IATA,
ADR/RID).
14.1. UN number
Not applicable.
14.2. UN proper shipping name
Not applicable.
14.3. Transport hazard class(es)
Transport Labels
No transport warning sign required.
14.4. Packing group
Not applicable.
14.5. Environmental hazards
Environmentally Hazardous Substance/Marine Pollutant
No.
14.6. Special precautions for user
Not applicable.
14.7. Transport in bulk according to Annex II of MARPOL73/78 and the IBC Code
Not applicable.
SECTION 15: REGULATORY INFORMATION
15.1. Safety, health and environmental regulations/legislation specific for the substance or mixture
Statutory Instruments
The Chemicals (Hazard Information and Packaging for Supply) Regulations 2009 (S.I 2009 No. 716). Control of Substances Hazardous to
Health.
5 / 5
SDS No. 16447
ARALDITE FUSION HARDENER
Approved Code Of Practice
Safety Data Sheets for Substances and Preparations. Classification and Labelling of Substances and Preparations Dangerous for Supply.
Guidance Notes
Workplace Exposure Limits EH40. Introduction to Local Exhaust Ventilation HS(G)37. CHIP for everyone HSG(108).
15.2. Chemical Safety Assessment
SECTION 16: OTHER INFORMATION
General information
This product should be used as directed by Bostik Ltd. For further information consult the product data sheet or contact Technical Services.
Information Sources
This safety data sheet was compiled using current safety information supplied by distributor of raw materials.
Revision Comments
NOTE: Lines within the margin indicate significant changes from the previous revision. This safety data sheet supersedes all previous
issues and users are cautioned to ensure that it is current. Destroy all previous data sheets and if in doubt contact Bostik Limited.
Issued By Approved LJ
Revision Date November 2011
Revision 3
Date September 2007
Risk Phrases In Full
R34 Causes burns.
R35 Causes severe burns.
R22 Harmful if swallowed.
R52/53 Harmful to aquatic organisms, may cause long-term adverse effects in the aquatic environment.
R38 Irritating to skin.
R41 Risk of serious damage to eyes.
R23/24 Toxic by inhalation and in contact with skin.
ICOMP
VCOMP
VADJ
Q1
Q2 L
10μH
C1
10μF
C10
10μF
R1
40mΩ
adaptateur secteur
R2
20mΩ
R4
2.2Ω
R5
100K
R8
130k
1%
R9
10.2k, 1%
C2
0.1μF
C4
0.1μF
C3
1μF
6.8nF
C9
1μF
C8
0.1μF
ISL6251
ISL6251A
C5
10nF
flottant
4.2V/CELL
R6
10k
C7
1μF
R10
4.7Ω
BATSCL
SDL
Une entrée / D
GND
entrée de 5.15A
limites actuelles
3 cellules
hôte
R11, R12, R13
10k
D1
en option
VDDP
D2
D3
R7: 100Ω
CSIP
RCID
BOOT
UGATE
PHASE
LGATE
PGND
CSOP
Cson
cellules
GND
C11
3300pF
D4
SYSTÈME DE CHARGE
DCIN
ACSET
VDDP
VDD
ACPRN
Chlim
FR
ICM
ACLIM
VREF
ICOMP
VCOMP
VADJ
R3: 18Ω
C6
ISL6251
ISL6251A
batterie
paquet
BAT +
SCL
SDL
Temp
BATBattery
BATVCC
sortie
Sortie D / A
Une entrée / D
DIGITAL
contribution
AVDD / VREF
CSIP
RCID
BOOT
UGATE
PHASE
LGATE
PGND
CSOP
Cson
cellules
GND
FIGURE 13. ISL6251, ISL6251A circuit d'application typique avec micro-contrôleur
ISL6251, ISL6251A
12 FN9202.2
10 mai 2006
Principe de fonctionnement
introduction
Le ISL6251, ISL6251A comprend toutes les fonctions
nécessaire de charger 2 à 4 cellules Li-Ion et Li-polymère
batteries. Une haute efficacité convertisseur abaisseur synchrone est
utilisé pour contrôler la tension et le courant jusqu'à Charing Charing
Les taux de 10A. Le ISL6251, ISL6251A a courant de limitation d'entrée
et entrées analogiques pour régler le courant de charge et de la charge
tension; Chlim entrées sont utilisées pour contrôler le courant de charge
VADJ et les intrants sont utilisés pour contrôler la tension de charge.
Le ISL6251, ISL6251A charger la batterie avec une constante
courant de charge, fixé par Chlim entrée, jusqu'à ce que la tension de la batterie
se dresse à la tension de charge programmé fixé par entrée VADJ;
puis le chargeur commence à fonctionner à une tension constante
de façon responsable.
L'entrée EN permet l'arrêt du chargeur à travers le
commande à partir du micro-contrôleur. Il utilise également un taux SÉCURITÉ
Lorsque le chargeur de batterie est en arrêt extrêmement chaud
Conditions. Le montant de la personnalisation de la visite actuelle est sur le
Sortie de l'ICM. La figure 11 montre le bloc fonctionnel IC
organigramme.
Le convertisseur abaisseur synchrone utilise à canal N externe
MOSFET à convertir la tension d'entrée à l'requis
courant Charing Charing et de la tension. La figure 12 montre l'
ISL6251, ISL6251A circuit typique d'application de Charing
Charing courant et tension fixe à des valeurs spécifiques. la
circuit typique d'application de la figure 13 montre les
ISL6251, ISL6251A circuit typique de l'application qui utilise la
Réglez le micro-contrôleur de courant Charing fixé par Chlim
entrée. La tension aux Chlim et la valeur de R1 définit le
courant Charing. Le convertisseur DC / DC génère l'
des signaux de commande pour entraîner deux MOSFET à canal N à l'extérieur
course la tension et courant défini par le ACLIM, Chlim,
Cellules et entrées VADJ.
Le ISL6251, ISL6251A dispose la boucle de régulation de tension
(VCOMP) et deux boucles de régulation de courant (ICOMP). la
Boucle de régulation de la tension de VCOMP Moniteur Cson pour assurer
que sa tension ne dépasse jamais la tension et régule l'
tension de charge de la batterie fixé par VADJ. Le ICOMP courant
boucles de régulation de course le courant batterie Charing
Livré à la batterie pour s'assurer qu'elle ne dépasse jamais la
Charing limites actuelles fixées par Chlim; et le courant ICOMP
des boucles de régulation de course également le courant d'entrée tiré à partir de
l'adaptateur secteur afin de s'assurer qu'il ne dépasse jamais l'entrée
limite actuelle fixée par ACLIM, et évaluer la panne du système de pré-vente
et AC de surcharge de l'adaptateur.
contrôle PWM
Le ISL6251, ISL6251A emploie le PWM à fréquence fixe
Architecture de courant de commande de mode avec la charge d'alimentation vers l'avant
fonction. La fonction de feed-forward maintient constant l'
gain de modulateur de 11 pour réaliser la régulation de ligne rapide cum
Buck tension d'entrée change. Lorsque la charge de la batterie
tension s'approche de la tension d'entrée, le convertisseur DC / DC
décrochage fonctionne à la mode, où il est la minuterie de prévente
la fréquence de tomber dans la fréquence audible
gamme. Il peut atteindre cyclique jusqu'à 99,6%.
Taux de pré-amplification de la tension de bus de système, la batterie
Lorsque chargé d'opérer dans la norme mode-Buck CSOPCSON
DROPS ci-dessous 4.25mV. Une fois en mode buck-standard,
hystérésis n'autorise pas le fonctionnement synchrone de la
Convertisseur DC / DC jusqu'à Rises CSOP-dessus Cson 12.5mV.
En route gâté adaptatif système est utilisé pour contrôler les morts
temps entre deux Switcher. Les morts circuit de commande de temps
Surveillez la sortie de LGATE et empêche la face supérieure
MOSFET de Turning jusqu'à LGATE est entièrement éteint, la prévention
croix-conduction et flèche à l'. Pour les morts
circuit de temps pour travailler correctement, il doit être le faible résistance,
faible chemin de l'inductance du conducteur de MOSFET LGATE
corrompu, et à partir de la source de MOSFET à PGND. la
diode Schottky externe est entre les broches et BOOT VDDP
pings à garder le condensateur d'amorçage partagée.
Réglage de la tension de la batterie règlement
Le ISL6251, ISL6251A utilise la haute précision garni
d'intervalle de bande de référence de tension à la batterie de Charing de course
tension. L'entrée VADJ Régler la tension de sortie du chargeur,
et la tension de commande de VADJ peut varier de 0 à VREF,
fournir la plage de réglage de 10% (de 4,2 V-5% de taux
4.2V +5%) sur le régulateur de tension Cson. Dans l'ensemble, la tension
précision meilleure que 0,5% est atteint.
La tension de terminaison de la batterie par des cellules est la fonction de l'
Basseterre chimie. Consultez le taux des fabricants de batteries
déterminer cette tension.
• Float VADJ pour régler la tension de la batterie = 4.2V × VCSON
nombre de cellules,
• Connectez-vous à VREF VADJ de mettre 4.41V nombre de × de cellules,
• Brancher à la masse à mettre en VADJ 3.99V nombre de × de la
cellules.
Jump, la tension maximale de la batterie de 17.6V peut être atteint.
Notez que l'autre tension de charge de la batterie peut être réglée par
Raccordement du diviseur résistif de VREF à la terre. la
diviseur à résistances doivent être dimensionnés pour attirer plus au nord que 100μA
de VREF; ou connectez la source de tension à basse impédance comme
Le convertisseur N / A dans le micro-contrôleur. le programmée
tension de la batterie par la cellule peut être déterminé par ce qui suit
équation:
Le diviseur de résistance externe de VREF définit la tension au
VADJ selon:
VCELL VVADJ = 0175 + 3.99V
VVADJ VREF
Rbot_VADJ | | 514k
Rtop_VADJ | | + 514k Rbot_VADJ | | 514k
= × ------------------------------------------------ -------------------------------------------------
ISL6251, ISL6251A
13 FN9202.2
10 mai 2006
Où Rbot_VADJ et Rtop_VADJ sont des résistances externes à
VADJ. Précision Taux de minimiser la perte due à l'interaction avec
Diviseur de résistance interne de VADJ, S'assurer que la résistance en courant alternatif
En regardant en arrière dans le diviseur de résistance externe est inférieure à 25k.
Connectez cellules cum présentés dans le tableau 1 pour charger 2, 3 ou 4 +
cellules. Lorsque Charing autres chimies cellulaires, utiliser des cellules à
sélectionner la plage de tension de sortie du chargeur. le interne
gm1 amplificateur d'erreur maintient la régulation de tension. la tension
amplificateur d'erreur est compensée à VCOMP. le composant
valeurs indiquées dans la figure 12 du fournisseur approprié pour tableaux de bord
la plupart des applications. La rémunération individuelle de la tension
réglementation et des boucles de courant régulation permet de optimale
compensation.
Réglage de la limite de courant de charge de batterie
L'entrée de Chlim règle le courant maximum de Charing. la
courant défini par la résistance de détection de courant relie entre
CSOP et Cson. La tension différentielle à grande échelle entre les
CSOP et Cson est 165mV pour Chlim = 3,3 V, le saut
Charing courant maximal est 4.125A pour un 40mΩ Sensing
résistance. Autre charge de la batterie seuil de détection de courant
valeurs peuvent être définies par le diviseur résistif de Connexion
VREF à la masse ou 3,3 V, ou en connectant la faible impédance
source de tension comme un convertisseur N / A dans le micro-contrôleur.
Contrairement VADJ et ACLIM, Chlim n'a pas le interne
réseau diviseur à résistances. Le courant seuil de limite de charge est
proposée par:
Pour régler le courant de charge d'entretien pour le chargeur muet, le
résistance en série avec les interrupteurs T3 (figure 12) commandé par
Le micro-contrôleur est connecté à la broche de terre Chlim.
Le courant de charge de maintien est déterminé par:
Lorsque la tension est inférieure à 88mV Chlim (typique), il ll
désactiver le chargeur de batterie. Au moment de choisir le courant
résistance de détection, notez que la chute de tension dans la
Causes outre la détection résistance dissipation de puissance, réduisant
efficacité. Cependant, pour réduire la Chlim de réglage de tension
tension à travers la résistance de détection de courant R1 Will dégradé
précision en raison du signal plus faible à l'entrée du courant
Amplificateur de lecture. Il est le compromis entre précision et
dissipation de puissance. Un filtre passe-bas est recommandé de
Mise à éliminer le bruit. Connecter la résistance à la CSOP
broches au lieu de les pings Cson, cum la broche CSOP a faible
courant de polarisation et moins d'influence sur le courant-sens Précision
La précision et le régulateur de tension.
Réglage de l'entrée limites actuelles
Le courant total d'entrée de l'adaptateur secteur, ou d'un autre DC
la source, est fonction du courant d'alimentation du système et de la
courant par batterie Charing. L'entrée actuelle limites régulateur
le courant d'entrée en réduisant le courant de Charing, Lorsque le
courant d'entrée dépasse l'entrée imparti point actuel.
Actuelle du système varie normalement usure sperme du système
sont alimentés vers le haut ou vers le bas. Sans réglementation actuelle d'entrée,
la source doit être capable de fournir le maximum du système
et le courant maximal d'entrée du chargeur
simultanément. En utilisant le courant d'entrée limité, le courant
Capacité de l'adaptateur secteur peut être réduit, ce qui réduit
le coût du système.
Le ISL6251, ISL6251A limite le courant de charge de la batterie
Lorsque le seuil de limitation du courant d'entrée est dépassée, assurant
le chargeur de batterie ne se charge pas en bas de l'adaptateur secteur
tension. Ce règlement courant d'entrée constante permet à l'
adapter entièrement dans le système d'alimentation et de la pré-AC
adaptateur de surcharge et de s'écraser le bus système.
L'amplificateur interne compare la tension entre gm3
CSIP et RCID au courant d'entrée tension de seuil limite
fixé par ACLIM. Connectez taux ACLIM REF, Float et GND pour
la pleine échelle tension d'entrée de seuil limite de 100 mV,
75mV et 50mV, respectivement, ou utiliser le diviseur résistif de
VREF à la masse pour définir la limite de courant d'entrée cum la suivante
équation:
Le diviseur de résistance externe de VREF définit la tension au
ACLIM de fonction:
Où Rbot_ACLIM et Rtop_ACLIM sont des résistances externes à
ACLIM. Précision Taux de minimiser la perte due à l'interaction avec
Diviseur de résistance interne de ACLIM, S'assurer que la résistance en courant alternatif
En regardant en arrière dans le diviseur de résistance externe est inférieure à 25k.
Lors du choix de la résistance de détection de courant, noter que la
chute de tension dans cette résistance provoque plus de puissance
la dissipation, ce qui réduit l'efficacité. Le courant de l'adaptateur secteur
Précision sincère est très important. Utilisez la tolérance de 1%
résistance de détection de courant. La plus grande précision de ± 3% est
obtenue avec 100 mV de mesure du courant pour la tension de seuil
ACLIM = VREF, mais il a la dissipation de puissance la plus élevée. pour
exemple, il a 400mW dissipation de puissance nominale pour 4A AC
la personnalisation et 1W Sensing maillage de résistance doivent être utilisés. ± 4%
et ± 6% La précision peut être obtenue avec 75mV et 50mV
sens de courant tension de seuil pour ACLIM = flottant et
ACLIM = GND, respectivement.
Programmation du nombre de cellules TABLEAU 1.
NOMBRE cellules CELL
DMV 4
GND 3
float 2
ICHG
165mV
R1
-------------------
VCHLIM
3.3V
= ---------------------
ICHG
165mV
R1
-------------------
VCHLIM, filet
3.3V
= ---------------------------------------
⎟ ⎠
⎞
⎜ ⎝
⎛ = V + 0,050
VREF
0,05
R
I 1 ACLIM
2
contribution
VACLIM VREF
Rbot_ACLIM | | 152k
Rtop_ACLIM | | 152k + Rbot_ACLIM | | 152k
= × ------------------------------------------------------------------------------------------------------
ISL6251, ISL6251A
14 FN9202.2
10 mai 2006
Un filtre passe-bas est d'éliminer la commutation suggéré
bruit. Connecter la résistance à RCID broches au lieu de broches CSIP
parce RCID a pings inférieurs courant Bias et moins influents
sur la précision de mesure du courant.
Personnalisation de détection AC
Connectez la tension de l'adaptateur secteur à travers la résistance diviseur de
ACSET Lorsque l'alimentation secteur est disponible pour détecter, cum montre
Figure 12. ACPRN est une sortie à drain ouvert est élevée et lorsque
ACSET est inférieure à Vth, RISE, et est actif bas Quand ACSET
ci-dessus Ve, tomber. Ve, RISE et Ve, automne sont donnés par:
Où est l'entrée de courant et de l'hystérésis Bias Ihys ACSET
VACSET = 1.24V (min), 1.26V (typ) et 1.28V (max). la
hystérésis est IhysR8, Où Ihys = 2.2μA (min), 3.4μA (typ)
et 4.4μA (max).
mesure de courant
Utilisez ICM pour contrôler le courant d'entrée détecté Être travers
CSIP et RCID. La plage de tension de sortie est de 0 à 2,5 V. la
Tension de ICM est proportionnelle à la chute de tension aux bornes de
CSIP et RCID, et est donnée par l'équation suivante:
de INPUT Où est le courant continu tirée de l'adaptateur secteur.
ICM a ± 3% Précision.
Un filtre passe-bas connecté à l'ICM est utilisé pour délivrer en sortie du filtre
Le bruit de commutation.
Régulateur LDO
5.075V VDD la tension d'alimentation du fournisseur de la LDO interne
Régulateur de DCIN et peut fournir jusqu'à 30mA de courant.
Les pilotes MOSFET sont alimentés par VDDP, qui doit être
connecté à VDDP cum le montre la figure 12. VDDP connecte
à travers la résistance externe à la DMV. Bypass VDD et VDDP
avec le 1μF condensateur.
fermeture
Le ISL6251, ISL6251A dispose la veille à faible consommation
mode. Conduite EN bas arrête le chargeur. Dans l'arrêt,
Le convertisseur DC / DC est désactivé, et VCOMP et ICOMP
sont tirés à la terre. L'ICM, sorties ACPRN continuer à
fonction.
FR peut être entraîné par la thermistance Autoriser automatique
arrêt Lorsque la batterie est chaude. Souvent, les NTC
thermistance est inclus à l'intérieur de la batterie pour mesurer son
Température. Lorsqu'il est connecté au chargeur, la thermistance
forme le diviseur de tension résistif avec le pull-up à la VREF.
La tension de seuil de 1.06V avec 60mV hystérésis est EN.
La thermistance peut être sélectionnée pour que le rapport de la résistance
Température caractéristique qui diminue brutalement au-dessus de l'
Température critique. Cette ferme automatiquement arrangement
Lorsque la batterie le chargeur est au-dessus de la critique
Température.
Une autre méthode pour inhiber taux Charing est Chlim force
ci-dessous 88mV (typ).
Short Circuit Protection et 0V Batterie Charing
Le courant de charge sur le chargeur de batterie Will course
les limites fixées par Chlim, il a automatiquement court-circuit
protection et est en mesure de charger le fournisseur actuel WAKE taux
en batterie extrêmement déchargée.
Protection contre la surchauffe
Si la température de la filière dépasse 150 ° C, il s'arrête Charing. Une fois que l'
DROPS meurent température inférieure à 125 ° C, Charing va recommencer.
Renseignements sur la demande
La conception de chargeur de batterie qui suit fait référence à la typique
Circuit d'application de la figure 12, où la batterie typique
de configuration 4S2P est utilisé. Cette section décrit comment
Sélectionnez les composants externes, y compris l'inducteur, entrée
et des condensateurs de sortie, MOSFET de commutation et de courant
Sentant résistances.
sélection d'inductance
La sélection de l'inducteur a compromis entre le coût, la taille et
efficacité. Par exemple, l'inductance de l'abaisser, l'
la plus petite taille, mais est courant supérieur d'ondulation. C'est ce qui ressort également
des pertes supérieur AC dans le noyau magnétique et les enroulements,
qui réduisent l'efficacité du système. D'autre part,
Les résultats d'inductance plus élevés dans l'ondulation inférieure actuelle et
un filtrage plus petites condensateurs de sortie, mais elle a supérieur DCR (DC
résistance de l'inducteur) perte, et a transitoire lent
réponse. Sauter, la conception pratique de l'inducteur est basée sur l'
inductance ondulation de courant Etre ± (15-20)% du maximum
en cours de fonctionnement à courant continu à la tension d'entrée maximale. la
inductance nécessaire peut être calculée à partir de:
Où VIN, MAX, VBAT, et FS sont l'entrée maximale
tension, la tension de la batterie et de la fréquence de commutation
respectivement. Le courant ΔI inductance d'ondulation se trouve de:
Lorsque le courant maximal crête-à-crête d'ondulation est de 30%
le courant de charge maximum est utilisé.
Pour VIN, MAX = 19V, VBAT = 16.8V, TABI, MAX = 2.6A, et
FS = 300kHz, l'inductance calculée est 8.3μH. Choisir
La valeur standard Placard donne L = 10μH. Noyaux de ferrite sont
souvent le meilleur choix, car ils sont à taux Optimisé 300kHz
ACSET
9
8
e, hausse de 1 V
R
• ⎟ V R
⎟ ⎠
⎞
⎜ ⎜ ⎝
⎛
+
ACSET hys 8
9
8
e, Fall 1 V I R
R
R
V - • ⎟
⎟ ⎠
⎞
⎜ ⎜ ⎝
⎛
+
ICM = 19,9 de INPUT • • R2
IN, MAX s
BAT
L
IN, MAX BAT
V f
V
je
V V
L
Δ
-
=
Δ IL = 30% ⋅ TABI, MAX
ISL6251, ISL6251A
15 FN9202.2
10 mai 2006
Opération de 600kHz avec une faible perte de base. Le noyau doit être honoré
PAS assez pour saturer au courant de bobine crête IPeak:
Sélection de condensateur de sortie
CONDENSATEUR La sortie en parallèle avec la batterie est utilisée pour
suce l'ondulation de courant à haute fréquence et de commutation
lisser la tension de sortie. La valeur efficace de la sortie
ondulation Ieff est donné par:
Lorsque le rapport cyclique D est le rapport de la tension de sortie
(tension de batterie) sur la tension d'entrée continue pour
Le fonctionnement en mode de conduction qui est typique pour la batterie
téléchargés. Au cours de la période de charge de la batterie, la tension de sortie
varie à partir de sa tension de batterie à la batterie initiale classé
tension. Sauter, le rapport cyclique peut être modifié dans la plage de
entre 0,53 et 0,88 pour la tension de batterie minimale de
10V (2.5V/Cell) et la tension maximale de la batterie de 16.8V.
Pour VIN, MAX = 19V, VBAT = 16.8V, L = 10μH, et
FS = 300kHz, le courant maximal RMS est 0.19A. Un typique
CONDENSATEUR 10F céramique est un bon choix pour ce suce
courant et a également de très petite taille. Le condensateur au tantale
Ormerod Connu mécanismes de défaillance Lorsqu'il est soumis à une grande
Courant de choc.
Considérations EMI marquent généralement souhaitable de minimiser
ondulation du courant dans les câbles de la batterie. Perles eBay maille ajoutée dans
série avec la batterie à l'augmentation de la batterie
impédance à 300kHz Fréquence de commutation. ondulation de commutation
splits de courant entre la batterie et le condensateur de sortie
en fonction de l'ESR de la production et de la batterie CONDENSATEUR
impédance. Si l'ESR du condensateur de sortie est 10M et
l'impédance de la batterie est élevée à 2Ω avec le talon, alors que
0,5% du courant d'ondulation dans la batterie 'vais couler.
sélection de MOSFET
Le chargeur de batterie pour ordinateur portable synchrone avec convertisseur abaisseur
a la tension d'entrée à partir de la sortie de l'adaptateur AC. la
tension de sortie maximum de l'adaptateur secteur ne dépasse pas 25V.
Par conséquent, la logique MOSFET 30V doit être utilisé.
Le MOSFET côté haut doit être capable de dissiper la
les pertes de conduction, plus les pertes de commutation. Pour la batterie
application chargée, la tension d'entrée de l'synchrone
convertisseur abaisseur est égale à la tension de sortie de l'adaptateur,
qui est relativement constante. L'efficacité maximale est
réalisé par Sélection du MOSFET côté haute qui a le
les pertes de conduction correspondant aux pertes de commutation. Assurez-vous que
ISL6251, ISL6251A LGATE gâté conducteur peut fournir suffisamment
taux actuel périssables prévente à partir de conduction, qui est due à
le courant injecté dans le parasite drain-source en
condensateur (Miller CONDENSATEUR CGD), et causée par la tension
phase ascendante de la rareté au noeud à l'instant de la high-side
Transformer un MOSFET; Sinon, des problèmes inter-conduction
maille se produisent. Ralentissement raisonnable tourner sur la vitesse de la
MOSFET côté en connectant la résistance entre le
Goupille de BOOT et la source d'alimentation du variateur gâté, et le haut de cinq
Capacité actuelle du pilote de MOSFET côté bas gâtée aide
réduire la possibilité de cross-conduction.
Pour le MOSFET côté, le pire des cas conduction
les pertes se produisent à la tension d'entrée minimum:
L'efficacité optimale lorsqu'on les pertes de commutation
égaler les pertes de conduction. Cependant, il est difficile d'
calculer les pertes de commutation dans le MOSFET côté
car il doit permettre facteur difficile à quantifier que
influent sur la tour-et temps turn-off. Ce facteur
Impliquer la résistance interne MOSFET gâté, gâté charge,
tension de seuil, l'inductance parasite, pull-up et pull-down
résistance du conducteur gâté. La perte de commutation suivante
estimations de calcul approximatif du fournisseur.
Où Qgd: drainer à périssable charge, Qrr: recouvrement inverse totale
Charge de la diode de corps MOSFET côté bas, ILV: inductance
actuelle vallée, ILP: courant de crête d'inductance, IG, et cinq
IG, la source de pointe sont la source gâtée lecteur / cinq cours du 1er trimestre,
respectivement.
Pour atteindre les pertes de commutation faible, il nécessite peu d'drain-périssables
charge Qgd. Généralement, plus la charge entre drain et périssable,
Le supérieur de la sur-résistance. Par conséquent, il est le compromis
entre la résistance et sur la charge de vidange à périssable. bon
Sélection de MOSFET est basée sur le facteur de mérite (FORM),
qui est le produit de la charge totale et la détérioration
sur-résistance. Habituellement, plus la valeur de la forme, le
plus le rendement pour la même application.
Pour le MOSFET côté bas, la dissipation de puissance pire des cas
se produit à la tension de batterie minimale et maximale d'entrée
tension:
Choisissez le MOSFET côté bas qui a le plus bas possible
sur la résistance avec le paquet de taille moyenne comme le SO-8
et est d'un prix raisonnable. Les pertes de commutation sont notés sur
émettre pour le MOSFET côté bas, car il fonctionne à
zéro de commutation de tension.
Choisir la diode Schottky en parallèle avec le transistor MOSFET du côté bas
Q2 avec la chute de tension assez basse pour la prévente
bas-côté MOSFET corps diode de Q2 lors d'un virage sur la
temps mort. Cela réduit également la perte de puissance dans le haut-côté
MOSFET associés à la récupération inverse de la
bas-côté corps MOSFET diode Q2.
BAT Peak, MAX IL
2
I = 1 + Δ
D (1 D)
12 L f
V
je
s
IN, MAX
RMS = -
DSON
2
BAT
EN
août
Q1, je conduction R
V
V
P =
EN rr s
g, k péché
gd
EN LP s
g, la source
gd
Q1, commutation de LV Q V de f
je
Q
I f V
2
1
je
Q
I f V
2
P = 1 + +
DSON
2
BAT
EN
août
Q2 I R
V
V
1 P ⎟
⎟ ⎠
⎞
⎜ ⎜ ⎝
⎛
= -
ISL6251, ISL6251A
16 FN9202.2
10 mai 2006
En règle générale, sélectionnez la diode avec DC Note courant égal
à un tiers du courant de charge. Une option est de choisir le
combiné avec la diode Schottky dans le MOSFET GaGa
emballage. Les ensembles intégrés maille travail mieux
pratiquer parce qu'il ya moins inductance parasite en raison de la
courte connexion. Cette diode Schottky est facultative et mesh eBay
Suppression hyphes perte d'efficacité peut être tolérée. En outre,
Veiller à ce que le courant d'entraînement requis totale gâté pour la
MOSFET sélectionné doit être inférieur à 24mA. Jump, le total
charge périssables pour les high-side et low-side MOSFET est
limité par l'équation suivante:
Où IGATE est le courant d'attaque totale et gâté Si eBay
moins de 24mA. En substituant IGATE = 24mA et FS = 300kHz
dans les rendements de l'équation ci-dessus que le périssables de la charge totale
doit être inférieure à 80nC. Par conséquent, la ISL6251,
ISL6251A entraîne facilement le courant de charge de la batterie jusqu'à 10 bis.
Sélection de condensateur d'entrée
Le condensateur d'entrée absorbe le courant d'ondulation de la
Convertisseur de puissance synchrone, qui est donnée par:
Cette RMS ondulation de courant doit être inférieure aux évaluée de RMS
courant dans le condensateur de fiche technique. Chimies Nom-tantale
(céramique, aluminium, ou OSCON) sont préférés en raison de leur
résistance à la mise sous tension des courants de surtension Lorsque l'adaptateur secteur
est branché sur le chargeur de batterie. Pour la batterie d'ordinateur portable
applications chargées, il est recommandé que céramique
condensateurs ou des condensateurs en polymère de Sanyo eBay utilisés pour un duo
leur petite taille et de coût raisonnable.
Le tableau 2 montre les listes de composants pour l'application typique
circuit de la figure 12.
Compensation de boucle de conception
ISL6251, ISL6251A utilise le mode courant de fréquence constante
contrôler l'architecture de la boucle pour atteindre une réponse transitoire rapide.
Dans résistance PRÉCIS en série avec la sortie de courant de détection
inducteur est utilisé pour la course du courant de charge, et l'
signal de courant détecté est injectée dans le taux de la boucle de tension
ATTEINDRE mode actuelle pour simplifier la boucle de régulation
conception de la rémunération. L'inducteur est pas considéré comme un
variables d'état pour le contrôle en mode courant et le système
GaGa devient payable système. Il est beaucoup plus facile de concevoir la
Compensateur pour stabiliser la tension de la boucle de tension de mode
contrôle. La figure 14 montre le petit modèle de signal de l'
synchrone régulateur abaisseur.
PWM comparateur Gain Fm:
Le gain PWM comparateur Fm pour le pic de contrôle en mode courant
est donné par:
Fonctions Power Stage de transfert
La fonction de transfert F1 (S) de contrôle de tension de sortie est:
Lorsque,
La fonction de transfert F2 (S) de commande de courant de l'inductance est la suivante:
, Où.
LISTE COMPOSANTS TABLEAU 2.
CHIFFRES ET PIECES fabricant
C1, C10 10μF/25V condensateur céramique, Taiyo Yuden
TMK325 MJ106MY X5R (3.2x2.5x1.9mm)
C2, C4, C8 0.1μF/50V condensateur céramique
C3, C7, C9 1μF/10V condensateur céramique, Taiyo Yuden
LMK212BJ105MG
C5 CONDENSATEUR 10nF céramique
C6 6.8nF condensateur céramique
3300pF condensateur céramique C11
Diode Schottky D1 30V/3A, EC31QS03L (facultatif)
D2, D3 diode Schottky 100mA/30V, Central Semiconductor
D4 8A/30V Schottky redresseur, STPS8L30B (facultatif)
L 10μH/3.8A/26mΩ, Sumida, CDRH104R-100
Q1, Q2 30V/35mΩ, FDS6912A, Fairchild.
s
porte
GATE f
je
Q ≤
()
EN
En août
BAT V RMS
V V V
I I.
-
=
Signal Q3 à canal N MOSFET, 2N7002
R1 40mΩ, ± 1%, LRC-LR2512-01-R040-F, IRC
R2 20mΩ, ± 1%, LRC-LR2010-01-R020-F, IRC
R3 18Ω, ± 5%, (0805)
R4 2.2Ω, ± 5%, (0805)
R5 100kΩ, ± 5%, (0805)
R6 10k, ± 5%, (0805)
R7 100Ω ± 5%, (0805)
R8, R11 130 K, ± 1%, (0805)
R9 10.2kΩ, ± 1%, (0805)
R10 4.7Ω, ± 5%, (0805)
R12 20kΩ, ± 1%, (0805)
R13 1.87kΩ, ± 1%, (0805)
LISTE COMPOSANTS TABLEAU 2. (Suite)
CHIFFRES ET PIECES fabricant
M 11
VIN
= ---------.
()
1
Q
S S
1 S
V
de
v
F S
2 o p
o
2
ESR
dans
o
1
+ +
+
==
ω ω
ω
,
R C
1
c o
ωesr =
L
C
Q R o
p ≈ o
o
o
LC
ω = 1
()
1
Q
S S
1 S
R R
V
de
je
F S
2 o p
o
2
z
o L
L en
2
+ +
+
+
==
ω ω
ω
o o
z R C
ω ≈ 1
ISL6251, ISL6251A
17 FN9202.2
10 mai 2006
Gain de boucle de courant Ti (S) est le sperme impressionné suivante
équation:
où RT est la trans-résistance dans la boucle de courant. RT est
généralement égal au produit du courant de détection Charing
la résistance et le gain de l'amplificateur de détection de courant, CA2.
Pour ISL6251, ISL6251A, RT = 20R1.
Le gain en tension de la boucle de courant est ouvert:
Lorsque, VFB est la tension de contre-réaction de la tension
l'amplificateur d'erreur. Le gain de la boucle de tension de la boucle de courant
fermée est donnée par:
Cum DM Petit (S) >> 1, alors il peut être simplifié suit:
De l'équation ci-dessus, il est démontré que le système est le
système de commande de GaGa, qui a le pôle de noisette situé à
Avant la moitié de la fréquence de commutation. Par conséquent, franc de type II
Compensateur peut être facilement utilisé pour stabiliser le système.
La figure 15 montre le compensateur de boucle de tension, et son
fonction de transfert est cum impressionné suit:
où
Objectif de conception du compensateur:
• haut gain DC
• boucle de bande passante FC:
• La marge de gain:> 10dB
• La marge de phase: 40 °
La procédure de conception du compensateur est cum suit:
. 1 Putt Compensateur zéro à:
2. Compensateur Mettez un pôle à la fréquence zéro pour atteindre
DC gain élevé, et Putt autre pôle du compensateur à répétitions
ESR fréquence nulle ou demi-fréquence de commutation
valeur la plus faible.
Le gain Tv (S) de la boucle à fréquence de croisement FC de l'unité a
gagner. Par conséquent, la résistance R1 est Compensateur
déterminé par:
Lorsque MM est la trans-conductance de l'erreur de la boucle de tension
amplificateur. Compensateur condensateur C1 est alors donnée par:
Exemple: Vin = 19V, Vo = 16.8V, 2.6A = nght, FS = 300kHz,
Co = 10μF/10mΩ, L = 10μH, GM = 250μs, RT = 0.8Ω,
VFB = 2,1 V, FC = 20 kHz, alors Compensateur résistance
R1 = 10kO. Choisissez R1 = 10kO. Mettez le compensateur zéro à
1,5 kHz. Le compensateur est condensateur C1 = 6.5nF.
Par conséquent, Choisissez tension boucle compensateur: R1 = 10k,
C1 = 6.5nF.
Petit (S) = 0,25 RTF2 (S) M
Tv (S) = KM F1 (S) AV (S)
o
FB
V
V
K =
()
1 T (S)
T S
L (S)
je
v
v +
=
LV (S)
4VFB
VO
--------------
(RO + RL)
RT
-----------------------------
1 S
ωesr
+ ------------
1 Sω
P
+ -------
------------------------ AV (S) ωP
1
ROCO
=, ≈ -----------------
ωp
FIGURE 14. MODEL PETIT SIGNAL DE synchrone
BUCK REGULATEUR
de
devenir
de
ville
iin L
+
1: D
+
IL
Cie.
rc
ro
-Av (S)
de
Vcomp
RT
11/Vin
+
Petit (S)
Q
valeur
Tv (S)
-
VCA2
0.25VCA2
VindILdin ()
Caroline du Sud
1 S
sol
v
v
S
1
CZ
je
FB
échantillon
v
ω
+
==
R C
1
1 1
ωcz =
-
+
R1
C1
VREF
VFB
VO
GM
VCOMP
FIGURE 15. LOOP tension Compensateur
FS
20
1
5
1 ⎟ ⎠
⎞
⎜ ⎝
⎛ -
()
o o
CZ R C
ω = 1 à 3 jan
R1
8πfCVOCORT
gmVFB
= ---------------------------------------
1 CZ
R 1
C 1
ω
=
ISL6251, ISL6251A
18 FN9202.2
10 mai 2006
Aspects de l'agencement PCB
Secteur et signal couches placement sur le PCB
En règle générale, les couches d'alimentation doivent être rapprochés,
répète sur le haut ou le bas de la carte, avec des couches de signaux sur
le côté opposé de la carte. Comme exemple, la couche
Agencement sur un panneau 4-couche est indiqué ci-dessous:
. 1 Top Layer: les lignes de signaux, ou demi-pension pour les lignes de signaux et
L'autre demi-pension pour les lignes électriques
2. Signal Ground
. 3 couches de puissance: Puissance sol
. 4 Couche inférieure: MOSFET de puissance, inductances et autres
traces de puissance
Séparer la tension d'alimentation et le chemin de circulation de courant à partir de
le chemin de signal de contrôle et de niveau logique. Le contrôleur IC
rester sur la couche de signal, qui est isolée par le signal
terre pour les traces de signal de puissance.
Placement de composants
Le MOSFET de puissance devrait être proche de l'IC que le saut
signaux gâté d'entraînement, le LGATE, UGATE, PHASE, et BOOT,
traces peuvent être à court.
Une telle place les composants de la façon que l'aire sous la
IC a moins de bruit retrace avec de hauts DVD / dt et de dire / dt, tel cum
signaux gâtés et les signaux de noeuds de phase.
Signal Ground et Ground Power Connection.
Au moins, la vaste zone raisonnable de cuivre, qui
Protégez autre couplage de bruit à travers le CI, devrait être utilisé
masse du signal cum sous le IC. Le meilleur lien entre les points
la masse du signal et la masse de l'alimentation est au négatif
CONDENSATEUR de chaque côté de la face de sortie, où il existe peu de
bruit; La trace bruyant sous la CI n'est pas recommandé.
GND et VDD PIN
Au moins une haute qualité en céramique bouchon de découplage Si eBay
utilisé pour franchir ces deux Pins. Le bouchon de découplage peut être mis
près de l'IC.
LGATE PIN
C'est le butin du signal de commande pour le MOSFET bas
Buck Converter. Le signal passant par cette trace est à la fois
élevés DVD / dt et ladite haute / dt, et le pic et Charing
courant de décharge est très élevé. Ces deux traces Si eBay
court, large, et loin d'autres traces. S'il n'y a pas
D'autres traces en parallèle avec ces traces sur une couche.
PGND PIN
Si les repères eBay PGND prévue sur le côté négatif de la
bouchon de sortie pertinente avec des traces distinctes. Le côté négatif
de la capacité de production doit être proche du noeud source de
le transistor MOSFET de fond. Cette trace est le chemin de LGATE de retour.
PIN PHASE
Cette trace doit être court, et positionné à l'écart des autres
faibles traces de signal. Ce nœud a la très grande dvds / dt avec le
excursion de tension de la tension d'entrée à la masse. n ° trace
devrait être en parallèle avec elle. Cette trace est également le trajet de retour
pour UGATE. Connectez cette broche à la MOSFET côté
la source.
UGATE PIN
Cette broche a la forme carrée de forme d'onde avec de hauts DVD / dt. il
Fournisseur gâché le courant d'attaque pour charger et décharger le
haut MOSFET à haute voix / dt. Cette trace devrait être large,
Bref, et loin des autres traces semblables à la LGATE.
PIN BOOT
Disons / dt de cette broche est la cum cum UGATE élevé; Par conséquent, cette trace
doit être court cum cum réalisable.
CSOP, Cson Pins
La résistance de détection de courant connecte à l'Cson et l'
CSOP Pins à travers le filtre passe-bas. La broche est également Cson
AS utilisé les évaluations de tension de la batterie. Les traces Si eBay
loin de la haute DVD / dt et dire / dit Pins comme PHASE, BOOT
Pins. En général, la résistance de détection de courant doit être proche
à l'IC. D'autres dispositions de mise en page doit être ajustée
en conséquence.
EN PIN
Cet axe reste à haute et basse au ralenti permettent la mode et de la mode
est relativement robuste. Activer signaux doivent se référer au signal
sol.
DCIN PIN
Cet axe se connecte à AC tension de sortie de l'adaptateur, et devrait
eBay moins sensible au bruit.
Taille du cuivre pour le noeud de phase
La capacité de phase devrait être aussi des taux très bas
minimiser sonner. Il serait préférable de limiter la taille de la
Noeud CUIVRE PHASE en stricte conformité avec le courant
et la gestion thermique de l'application.
Identifier le terrain secteur et signal
Les condensateurs des convertisseurs d'entrée et de sortie, la source
terminale de la commutation MOSFET bas Si PGND
connecter à la terre électrique. Les autres composants doivent
connecter à la masse du signal. Signal et masse de l'alimentation sont tiède
ensemble à un moment donné.
Serrage condensateur pour MOSFET de commutation
Il est recommandé que les bouchons en céramique utilisés eBay étroitement
reliée au drain du MOSFET côté, et la
la source du MOSFET côté bas. Cela réduit la capacité
le bruit et la perte du MOSFET de puissance.
ISL6251, ISL6251A
19 FN9202.2
10 mai 2006
ISL6251, ISL6251A
Quad Flat No-Lead paquet en plastique (QFN)
Micro Cadre de plomb paquet en plastique (MLFP)
INDEX
D1 / 2
D1
D / 2
ré
E1 / 2 E / 2
E
A
2x
0,15
B
C
0,10 M C A B
A
N
plan SIÈGES
N
6
3 2
23
et
1
1
0,08
TERMINAL POUR ODD / SIDE POUR TERMINAL Même / SIDE
C C
SECTION "C-C"
NX b
A1
C
2x
0,15 C
0,15
2x
B
0
REF.
(ND-1) Xe
(NRE-E1F) X. et
5
A1
4x P
A
C
C
4x P
B
2x
0,15 C A
A2
A3
D2
D2
E2
E2 / 2
TYPE TERMINAL
VUE DE CÔTÉ
VUE DE DESSUS
7
VUE DU BAS
7
5
CL CL
et e
E1
2
NX k
NX b
8
NX L
8
8
9
ZONE
9
4x
/ / C 0,10
9
(La référence B)
(Donnée A)
INDEX
6
ZONE
N
9
CORNER
Options 4x
L1
L
10 l1
L
10
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)
SYMBOL
MILLIMETERS
MIN NOMINAL MAX NOTES
A 0.80 0.90 1.00 -
A1 - 0.02 0.05 -
A2 - 0.65 1.00 9
A3 0.20 REF 9
b 0.18 0.25 0.30 5,8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.95 3.10 3.25 7,8
E 5.00 BSC -
E1 4.75 BSC 9
E2 2.95 3.10 3.25 7,8
e 0.50 BSC -
k 0.20 - - -
L 0.50 0.60 0.75 8
N 28 2
Nd 7 3
Ne 7 3
P - - 0.60 9
θ - - 12 9
Rev1 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9202.2
May 10, 2006
ISL6251, ISL6251A
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
α
INDEX
AREA
E
D
N
1 2 3
-B-
0.17(0.007) M C A B S
e
-AB
M
-CA1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H 0.25(0.010) M B M
L
0.25
0.010
GAUGE
PLANE
A2
M24.15
24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A 0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
A2 - 0.061 - 1.54 -
B 0.008 0.012 0.20 0.30 9
C 0.007 0.010 0.18 0.25 -
D 0.337 0.344 8.55 8.74 3
E 0.150 0.157 3.81 3.98 4
e 0.025 BSC 0.635 BSC -
H 0.228 0.244 5.80 6.19 -
h 0.0099 0.0196 0.26 0.49 5
L 0.016 0.050 0.41 1.27 6
N 24 24 7
α 0° 8° 0° 8° -
Rev2 6/04
1
®
FN3282.13
DG411, DG412, DG413
Monolithic Quad SPST, CMOS Analog
Switches
The DG411 series monolithic CMOS analog switches are
drop-in replacements for the popular DG211 and DG212
series devices. They include four independent single pole
throw (SPST) analog switches, and TTL and CMOS
compatible digital inputs.
These switches feature lower analog ON-resistance (<35Ω)
and faster switch time (tON<175ns) compared to the DG211
or DG212. Charge injection has been reduced, simplifying
sample and hold applications.
The improvements in the DG411 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 40VP-P signals. Power supplies may be
single-ended from +5V to 44V, or split from ±5V to ±20V.
The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON-resistance variation with analog
signals is quite low over a ±15V analog input range. la
switches in the DG411 and DG412 are identical, differing only
in the polarity of the selection logic. Two of the switches in the
DG413 (#2 and #3) use the logic of the DG211 and DG411
(i.e., a logic “0” turns the switch ON) and the other two
switches use DG212 and DG412 positive logic. This permits
independent control of turn-on and turn-off times for SPDT
configurations, permitting “break-before-make” or “makebefore-
break” operation with a minimum of external logic.
Features
• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . .35Ω
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . .<35μW
• Fast Switching Action
- tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175ns
- tOFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145ns
• Low Charge Injection
• Upgrade from DG211, DG212
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
Data Sheet June 20, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1993, 1994, 1997, 1999, 2002, 2004-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2 FN3282.13
June 20, 2007
Pinout
DG411, DG412, DG413
(16 LD PDIP, SOIC, TSSOP)
TOP VIEW
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
DG411DJ DG411DJ -40 to +85 16 Ld PDIP E16.3
DG411DJZ (Note) DG411DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG411DY* DG411DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG411DYZ* (Note) DG411DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG411DVZ* (Note) DG411 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
DG412DJ DG412DJ -40 to +85 16 Ld PDIP E16.3
DG412DJZ (Note) DG412DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG412DY* DG412DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG412DYZ* (Note) DG412DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG412DVZ* (Note) DG412 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
DG413DJ DG413DJ -40 to +85 16 Ld PDIP E16.3
DG413DJZ (Note) DG413DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG413DY* DG413DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG413DYZ* (Note) DG413DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG413DVZ* (Note) DG413 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
*Add “-T” suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
TRUTH TABLE
LOGIC
DG411 DG412 DG413
SWITCH SWITCH
SWITCH
1, 4
SWITCH
2, 3
0 On Off Off On
1 Off On On Off
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
D1
S1
VGND
S4
IN4
D4
IN2
S2
V+
VL
S3
D3
IN3
D2
Pin Descriptions
PIN SYMBOL DESCRIPTION
1 IN1 Logic Control for Switch 1.
2 D1 Drain (Output) Terminal for Switch 1.
3 S1 Source (Input) Terminal for Switch 1.
4 V- Negative Power Supply Terminal.
5 GND Ground Terminal (Logic Common).
6 S4 Source (Input) Terminal for Switch 4.
7 D4 Drain (Output) Terminal for Switch 4.
8 IN4 Logic Control for Switch 4.
9 IN3 Logic Control for Switch 3.
10 D3 Drain (Output) Terminal for Switch 3.
11 S3 Source (Input) Terminal for Switch 3.
12 VL Logic Reference Voltage.
13 V+ Positive Power Supply Terminal (Substrate).
14 S2 Source (Input) Terminal for Switch 2.
15 D2 Drain (Output) Terminal for Switch 2.
16 IN2 Logic Control for Switch 2.
DG411, DG412, DG413
3 FN3282.13
June 20, 2007
Functional Diagrams Four SPST Switches per Package Switches Shown for Logic “1” Input
Schematic Diagram (1 Channel)
S1
D1
S2
D2
S3
D3
S4
D4
DG411
S1
D1
S2
D2
S3
D3
S4
D4
IN1
DG412
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
IN1
DG413
IN2
IN3
IN4
IN2
IN3
IN4
IN1
S
V+
INX
GND
VVVL
ré
V+
DG411, DG412, DG413
4 FN3282.13
June 20, 2007
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V
VL. . . . . . . . . . . . . . . . . .............(GND -0.3V) to (V+) +0.3V
Digital Inputs, VS, VD (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time ..................... .... ...≤20ns
Thermal Resistance (Typical, Note 2) θJA (°C/W)
PDIP Package* ............................ 90
SOIC Package ................. . . . . . . . . . . . . 110
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Maximum Junction Temperature (Plastic Packages). . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . ..-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . ..see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(SOIC and TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified.
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON RL = 300Ω, CL = 35pF, VS = ±10V (Figure 1) 25 - 110 175 ns
85 - - 220 ns
Turn-OFF Time, tOFF 25 - 100 145 ns
85 - - 160 ns
Break-Before-Make Time Delay DG413 Only, RL = 300Ω, CL = 35pF (Figure 2) 25 - 25 - ns
Charge Injection, Q (Figure 3) CL = 10nF, VG = 0V, RG = 0Ω 25 - 5 - pC
OFF Isolation (Figure 5) RL = 50Ω, CL = 5pF, f = 1MHz 25 - 68 - dB
Crosstalk (Channel-to-Channel),
(Figure 4)
25 - -85 - dB
Source OFF Capacitance, CS(OFF) f = 1MHz (Figure 6) 25 - 9 - pF
Drain OFF Capacitance, CD(OFF) 25 - 9 - pF
Channel ON Capacitance,
CD(ON) + CS(ON)
25 - 35 - pF
DIGITAL INPUT CHARACTERISTICS
Input Current VIN Low, IIL VIN Under Test = 0.8V, All Others = 2.4V Full -0.5 0.005 0.5 μA
Input Current VIN High, IIH VIN Under Test = 2.4V, All Others = 0.8V Full -0.5 0.005 0.5 μA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG IS = 10mA Full -15 - 15 V
Drain-Source ON Resistance,
rDS(ON)
IS = 10mA, VD = ±8.5V, V+ = 13.5V, V- = -13.5V 25 - 25 35 Ω
Full - - 45 Ω
±
±
DG411, DG412, DG413
5 FN3282.13
June 20, 2007
Source OFF Leakage Current,
IS(OFF)
V+ = 16.5V, V- = -16.5V, VD = ±15.5V, VS = 15.5V 25 -0.25 ±0.1 0.25 nA
Full -5 - +5 nA
Drain OFF Leakage Current,
ID(OFF)
25 -0.25 ±0.1 0.25 nA
Full -5 - +5 nA
Channel ON Leakage Current,
ID(ON) + IS(ON)
V+ = 16.5V, V- = -16.5V, VS = VD = ±15.5V 25 -0.4 ±0.1 0.4 nA
Full -10 - +10 nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V 25 - 0.0001 1 μA
85 - - 5 μA
Negative Supply Current, I- 25 -1 -0.0001 - μA
85 -5 - - μA
Logic Supply Current, IL 25 - 0.0001 1 μA
85 - - 5 μA
Ground Current, IGND 25 -1 -0.0001 - μA
85 -5 - - μA
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified.
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON RL = 300Ω, CL = 35pF,
VS = 8V, (Figure 1)
25 - 175 250 ns
85 - - 315 ns
Turn-OFF Time, tOFF 25 - 95 125 ns
85 - - 140 ns
Break-Before-Make Time Delay DG413 Only, RL = 300Ω,
CL = 35pF, VS = 8V
25 - 25 - ns
Charge Injection, Q CL = 10nF, VG = 6.0V, RG = 0Ω 25 - 25 - pC
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - 12 V
Drain-Source ON-Resistance,
rDS(ON)
IS = -10mA, VD = 3V, 8V
V+ = 10.8V
25 - 40 80 Ω
Full - - 100 Ω
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4) UNITS
±
DG411, DG412, DG413
6 FN3282.13
June 20, 2007
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 13.2V, V- = 0V
VIN = 0V or 5V
25 - 0.0001 1 μA
85 - - 5 μA
Negative Supply Current, I- 25 -1 -0.0001 - μA
85 -5 - - μA
Logic Supply Current, IL 25 - 0.0001 1 μA
85 - - 5 μA
Ground Current, IGND 25 -1 -0.0001 - μA
85 -5 - - μA
NOTES:
3. VIN = input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
NOTE: Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENTS POINTS
Repeat test for all IN and S.
For load conditions, see Specifications. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUITS
FIGURE 2. BREAK-BEFORE-MAKE TIME
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4) UNITS
50%
tr < 20ns
tf < 20ns
tOFF
90%
3V
0V
VS
0V
tON
VO
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VO VS
RL
RL + rDS(ON)
= ------------------------------------
SWITCH
INPUT
LOGIC
INPUT
S1
IN1
V+
D1
RL CL
VO
GND
VVL
+5V +15V
SWITCH
OUTPUT
-15V
tD
3V
0V
VS1
0V
tD
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
90%
0V
VS2
(V01)
VO2
90%
S1
IN1, IN2
V+
D1
RL1 CL1
VO1
GND VVL
VS1 = 10V
300Ω
+5V +15V
S2 D2 35pF
RL2 CL2
VO2
VS2 = 10V
300Ω 35pF
-15V
LOGIC
INPUT
CL includes fixture and
stray capacitance.
DG411, DG412, DG413
7 FN3282.13
June 20, 2007
FIGURE 3A. TEST CIRCUIT
NOTE: INX dependent on switch configuration, input polarity
determined by sense of switch.
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. CHARGE INJECTION
FIGURE 4. CROSSTALK TEST CIRCUIT FIGURE 5. OFF ISOLATION TEST CIRCUIT
FIGURE 6. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT
Test Circuits and Waveforms (Continued)
V+
D1
CL
VO
GND
VVIN
= 3V
RG
VG
SWITCH ΔVO
INX
OFF ON
INX
OFF OFF
OFF
ON
Q = ΔVO x CL
OUTPUT
0V, 2.4V
ANALYZER
+15V
C V+
0dBm VS
SIGNAL
GENERATOR
RL
GND
IN1
VD
IN2
50Ω
0V, 2.4V
NC
V-
-15V
C
VD ANALYZER
RL
+15V
0dBm
SIGNAL
GENERATOR
C V+
V-
-15V
C
0V, 2.4V
VS
VD
INX
GND
+15V
C V+
GND
VS
VD
INX
V-
-15V
C
IMPEDANCE
ANALYZER
f = 1MHz
0V, 2.4V
DG411, DG412, DG413
8 FN3282.13
June 20, 2007
Application Information
Single Supply Operation
The DG411, DG412, DG413 can be operated with unipolar
supplies from 5V to 44V. These devices are characterized
and tested for single supply operation at 12V to facilitate the
majority of applications. To function properly, 12V is tied to
Pins 13 and 0V is tied to Pin 4.
Pin 12 still requires 5V for TTL compatible switching.
Summing Amplifier
When driving a high impedance, high capacitance load such
as shown in Figure 7, where the inputs to the summing
amplifier have some noise filtering, it is necessary to have
shunt switches for rapid discharge of the filter capacitor, thus
preventing offsets from occurring at the output.
VIN1
R1 R2
VOUT
+
-
C1
VIN2
R3 R4
C2
DG413
R5
R6
FIGURE 7. SUMMING AMPLIFIER
DG411, DG412, DG413
9 FN3282.13
June 20, 2007
Typical Performance Curves
FIGURE 8. ON RESISTANCE vs VD AND POWER SUPPLY
VOLTAGE
FIGURE 9. SWITCHING TIME vs TEMPERATURE
FIGURE 10. LEAKAGE CURRENTS vs ANALOG VOLTAGE FIGURE 11. SUPPLY CURRENT vs INPUT SWITCHING
FREQUENCY
FIGURE 12. CHARGE INJECTION vs SOURCE VOLTAGE FIGURE 13. CHARGE INJECTION vs DRAIN VOLTAGE
TA = +25°C
50
A: ±5V
B: ±8V
C: ±10V
D: ±12V
E: ±15V
F: ±20V
45
40
35
30
25
20
15
10
5
0
-20 -15 -10 -5 0 5 10 15 20
A
B
C
ré
E
fa
DRAIN VOLTAGE (V)
rDS(ON) (Ω)
V+ = 15V, V- = -15V
VL = 5V, VS = 10V
tON
tOFF
-55 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
-35
0
240
210
180
150
120
90
60
30
tON, tOFF (ns)
V+ = 15V, V- = -15V
VL = 5V, TA = +25°C
-15 -5 0 5 10 15
VS, VD (V)
-10
-60
20
10
0
-10
-20
-30
-40
-50
IS, ID (pA)
IS(OFF)
ID(OFF)
30
40
ID(ON) + IS(ON)
ISUPPLY
100mA
1mA
100μA
10μA
1μA
100nA
10nA
10mA
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
IL
I+, I-
1SW 1SW
4SW
4SW
V+ = 15V, V- = -15V
VL = 5V
CL = 10nF
CL = 1nF
-15 -5 0 5 10 15
VS (V)
-10
-60
60
40
20
0
-20
-40
Q (pC)
80
100
V+ = 15V, V- = -15V
VL = 5V CL = 10nF
CL = 1nF
-15 -5 0 5 10 15
VD (V)
-10
-60
60
40
20
0
-20
-40
Q (pC)
100
140
120
80
V+ = 15V, V- = -15V
VL = 5V
DG411, DG412, DG413
10 FN3282.13
June 20, 2007
Die Characteristics
DIE DIMENSIONS:
2760mm x 1780mm x 485mm
METALLIZATION:
Type: SiAl
Thickness: 12kÅ ±1kÅ
PASSIVATION:
Type: Nitride
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm2
Metallization Mask Layout
DG411, DG412, DG413
S1 (3)
V- (4)
GND (5)
S4 (6)
D1 IN1 IN2
(11) S3
(12) VL
(13) V+ SUBSTRATE
(14) S2
(15) D2
(2) (1) (16)
D4 IN4 IN3 D3
(7) (8) (9) (10)
DG411, DG412, DG413
11 FN3282.13
June 20, 2007
DG411, DG412, DG413
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
α
INDEX
AREA
E1
ré
N
1 2 3
-B-
0.10(0.004) M C A B S
et
-Ab
M
-CA1
A
SEATING PLANE
0.10(0.004)
c
E 0.25(0.010) M B M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A - 0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N 16 16 7
a 0o 8o 0o 8o -
Rev1 2/02
12 FN3282.13
June 20, 2007
DG411, DG412, DG413
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC
seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendicular
to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-CCL
E
eA
C
eB
eC
-BE1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-CD1
B1
B
et
ré
D1
A2 A
L
A1
-A-
0.010 (0.25) M C A B S
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC 6
eB - 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N 16 16 9
Rev0 12/93
13
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3282.13
June 20, 2007
DG411, DG412, DG413
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
ré
N
1 2 3
-B-
0.25(0.010) M C A B S
et
-AL
B
M
-CA1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H 0.25(0.010) M B M
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N 16 16 7
α 0° 8° 0° 8° -
Rev1 6/05
1
®
July 2004
HIP4081A
80V/2.5A Peak, High Frequency Full
Bridge FET Driver
The HIP4081A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4081A can drive every
possible switch combination except those which would
cause a shoot-through condition. The HIP4081A can switch
at frequencies up to 1MHz and is well suited to driving Voice
Coil Motors, high-frequency switching power amplifiers, and
power supplies.
For example, the HIP4081A can drive medium voltage brush
motors, and two HIP4081As can be used to drive high
performance stepper motors, since the short minimum
“on-time” can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in rapid, precise control of the driven load.
A similar part, the HIP4080A, includes an on-chip input
comparator to create a PWM signal from an external triangle
wave and to facilitate “hysteresis mode” switching.
The Application Note for the HIP4081A is the AN9405.
Features
• Independently Drives 4 N-Channel FET in Half Bridge or
Full Bridge Configurations
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz in Free Air at 50°C with Rise
and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chip Charge-Pump and Bootstrap Upper Bias
Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V Logic
Levels
• Very Low Power Consumption
• Undervoltage Protection
• Pb-free Available
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Switching Power Amplifiers
• High Performance Motor Controls
• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals
• U.P.S.
Pinout
HIP4081A
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP RANGE
(°C) PACKAGE
PKG.
DWG. #
HIP4081AIP -40 to 85 20 Ld PDIP E20.3
HIP4081AIPZ
(Note)
-40 to 85 20 Ld PDIP
(Pb-free)
E20.3
HIP4081AIB -40 to 85 20 Ld SOIC (W) M20.3
HIP4081AIBZ
(Note)
-40 to 85 20 Ld SOIC (W)
(Pb-free)
M20.3
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
BHB 1
BHI
DIS
VSS
BLI
ALI
HDEL
AHI
LDEL
AHB
BHO
BLO
BLS
VDD
BHS
VCC
ALS
ALO
AHS
AHO
Data Sheet FN3659.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
HIP4081A
Application Block Diagram
Functional Block Diagram (1/2 HIP4081A)
80V
GND
LOAD
HIP4081A
GND
12V
AHI
ALI
BLI
BHI BLO
BHS
BHO
ALO
AHS
AHO
CHARGE
PUMP
VDD
AHI
DIS
ALI
HDEL
LDEL
VSS
TURN-ON
DELAY
TURN-ON
DELAY
DRIVER
DRIVER
AHB
AHO
AHS
VCC
ALO
ALS
CBF
TO VDD (PIN 16)
CBS
DBS
HIGH VOLTAGE BUS ≤ 80VDC
+12VDC
LEVEL SHIFT
AND LATCH
14
10
11
12
15
13
16
7
3
6
8
9
4
BIAS
SUPPLY
UNDERVOLTAGE
3
Typical Application (PWM Mode Switching)
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1 BHB
BHI
DIS
VSS
BLI
ALI
HDEL
AHI
LDEL
AHB
BHO
BLO
BLS
VDD
BHS
VCC
ALS
ALO
AHS
AHO
80V
12V
+
-
12V
DIS
GND
6V
GND
TO OPTIONAL
CURRENT CONTROLLER
PWM
LOAD
INPUT
HIP4081/HIP4081A
HIP4081A
4
HIP4081A
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . .-0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V
Voltage on AHS, BHS . . .-6.0V (Transient) to 80V (25°C to 125°C)
Voltage on AHS, BHS . . .-6.0V (Transient) to 70V (-55°C to 125°C)
Voltage on ALS, BLS . . . . . . .-2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB . . . . . . . .VAHS, BHS -0.3V to VAHS, BHS +VDD
Voltage on ALO, BLO . . . . . . . . . . . ..VALS, BLS -0.3V to VCC +0.3V
Voltage on AHO, BHO . . . . . . .VAHS, BHS -0.3V to VAHB, BHB +0.3V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . .-5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V/ns
NOTE: All Voltages relative to VSS, unless otherwise specified.
Thermal Resistance (Typical, Note 1) θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Storage Temperature Range. . . . . . . . . . . . . . . . . . .-65°C to 150°C
Operating Max.Junction Temperature . . . . . . . . . . . . . . . . . .125°C
Lead Temperature (Soldering 10s)). . . . . . . . . . . . . . . . . ....300°C
(For SOIC - Lead Tips Only
Operating Conditions
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V
Voltage on ALS, BLS ................... .... ..-1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . . .VAHS, BHS +5V to VAHS, BHS +15V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . ..-500μA to -50μA
Operating Ambient Temperature Range . . . . . . . . . ..-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and
TA = 25°C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
TJ = 25°C
TJS = -40°C TO
125°C
MIN TYP MAX MIN MAX UNITS
SUPPLY CURRENTS AND CHARGE PUMPS
VDD Quiescent Current IDD All inputs = 0V 8.5 10.5 14.5 7.5 14.5 mA
VDD Operating Current IDDO Outputs switching f = 500kHz 9.5 12.5 15.5 8.5 15.5 mA
VCC Quiescent Current ICC All Inputs = 0V, IALO = IBLO = 0 - 0.1 10 - 20 μA
VCC Operating Current ICCO f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA
AHB, BHB Quiescent Current -
Qpump Output Current
IAHB, IBHB All Inputs = 0V, IAHO = IBHO = 0
VDD = VCC = VAHB = VBHB = 10V
-50 -30 -11 -60 -10 μA
AHB, BHB Operating Current IAHBO, IBHBO f = 500kHz, No Load 0.6 1.2 1.5 0.5 1.9 mA
AHS, BHS, AHB, BHB Leakage
Current
IHLK VBHS = VAHS = 80V,
VAHB = VBHB = 93V
- 0.02 1.0 - 10 μA
AHB-AHS, BHB-BHS Qpump
Output Voltage
VAHB-VAHS
VBHB-VBHS
IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V
INPUT PINS: ALI, BLI, AHI, BHI, AND DIS
Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V
High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V
Input Voltage Hysteresis - 35 - - - mV
Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 μA
High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 μA
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage VHDEL, VLDEL IHDEL = ILDEL = -100μA 4.9 5.1 5.3 4.8 5.4 V
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
Low Level Output Voltage VOL IOUT = 100mA 0.7 0.85 1.0 0.5 1.1 V
High Level Output Voltage VCC-VOH IOUT = -100mA 0.8 0.95 1.1 0.5 1.2 V
Peak Pullup Current IO+ VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A
5
HIP4081A
Peak Pulldown Current IO- VO UT = 12V 1.7 2.4 3.3 1.3 3.6 A
Undervoltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V
Undervoltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V
Undervoltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V
Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF.
PARAMETER SYMBOL TEST CONDITIONS
TJ = 25°C
TJS = -40°C
TO 125°C
MIN TYP MAX MIN MAX UNITS
Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)
TLPHL - 30 60 - 80 ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
THPHL - 35 70 - 90 ns
Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)
TLPLH RHDEL = RLDEL = 10K - 45 70 - 90 ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
THPLH RHDEL = RLDEL = 10K - 60 90 - 110 ns
Rise Time TR - 10 25 - 35 ns
Fall Time TF - 10 25 - 35 ns
Turn-on Input Pulse Width TPWIN-ON RHDEL = RLDEL = 10K 50 - - 50 - ns
Turn-off Input Pulse Width TPWIN-OFF RHDEL = RLDEL = 10K 40 - - 40 - ns
Turn-on Output Pulse Width TPWOUT-ON RHDEL = RLDEL = 10K 40 - - 40 - ns
Turn-off Output Pulse Width TPWOUT-OFF RHDEL = RLDEL = 10K 30 - - 30 - ns
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW - 45 75 - 95 ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH - 55 85 - 105 ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
TDLPLH - 40 70 - 90 ns
Refresh Pulse Width (ALO and BLO) TREF-PW 240 410 550 200 600 ns
Disable to Upper Enable (DIS - AHO and BHO) TUEN - 450 620 - 690 ns
TRUTH TABLE
INPUT OUTPUT
ALI, BLI AHI, BHI U/V DIS ALO, BLO AHO, BHO
X X X 1 0 0
1 X 0 0 1 0
0 1 0 0 0 1
0 0 0 0 0 0
X X 1 X 0 0
NOTE: X signifies that input can be either a “1” or “0”.
Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and
TA = 25°C, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS
TJ = 25°C
TJS = -40°C TO
125°C
MIN TYP MAX MIN MAX UNITS
6
HIP4081A
Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30μA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than VDD).
4 VSS Chip negative supply, generally will be ground.
5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin
8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V
(no greater than VDD).
6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin
8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V
(no greater than VDD).
7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no
shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30μA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.
16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).
17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.
7
HIP4081A
Timing Diagrams
FIGURE 1. INDEPENDENT MODE
FIGURE 2. BISTATE MODE
FIGURE 3. DISABLE FUNCTION
U/V = DIS = 0
XLI
XHI
XLO
XHO
TLPHL THPHL
THPLH TLPLH TR
(10% - 90%)
TF
(10% - 90%)
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
U/V = DIS = 0
XLI
XHI = HI OR NOT CONNECTED
XLO
XHO
(10% - 90%) (10% - 90%)
U/V OR DIS
XLI
XHI
XLO
XHO
TDLPLH TDIS
TUEN
TREF-PW
8
HIP4081A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K
and TA = 25°C, Unless Otherwise Specified
FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD
SUPPLY VOLTAGE
FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs
FREQUENCY (kHz)
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs
FREQUENCY (LOAD = 1000pF)
FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs
FREQUENCY (kHz) TEMPERATURE
FIGURE 8. IAHB, IBHB, NO-LOAD FLOATING SUPPLY BIAS
CURRENT vs FREQUENCY
FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL
vs TEMPERATURE
6 8 10 12 14
2.0
4.0
6.0
8.0
10.0
12.0
14.0
IDD SUPPLY CURRENT (mA)
VDD SUPPLY VOLTAGE (V)
0 100 200 300 400 500 600 700 800 900 1000
8.0
8.5
9.0
9.5
10.0
10.5
11.0
IDD SUPPLY CURRENT (mA)
SWITCHING FREQUENCY (kHz)
0 100 200 300 400 500 600 700 800 900 1000
0.0
5.0
10.0
15.0
20.0
25.0
30.0
FLOATING SUPPLY BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz) 0 100 200 300 400 500 600 700 800 900 1000
0.0
1.0
2.0
3.0
4.0
5.0
ICC SUPPLY CURRENT (mA)
SWITCHING FREQUENCY (kHz)
75°C
25°C
125°C
-40°C
0°C
0.5
1
1.5
2
2.5
0 200 400 600 800 1000
FLOATING SUPPLY BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz)
-50 -25 0 25 50 75 100 125
-120
-110
-100
-90
LOW LEVEL INPUT CURRENT (μA)
JUNCTION TEMPERATURE (°C)
9
HIP4081A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K
and TA = 25°C, Unless Otherwise Specified
FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION
DELAY TDISHIGH vs TEMPERATURE
FIGURE 12. DISABLE TO UPPER ENABLE, TUEN,
PROPAGATION DELAY vs TEMPERATURE
FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION
DELAY TDISLOW vs TEMPERATURE
FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs
TEMPERATURE
FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH
PROPAGATION DELAY vs TEMPERATURE
-40 -20 0 20 40 60 80 100 120
10.0
11.0
12.0
13.0
14.0
15.0
NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
425
450
475
500
525
-50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
PROPAGATION DELAY (ns)
-40 -20 0 20 40 60 80 100 120
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
350
375
400
425
450
-50 -25 0 25 50 75 100 125 150
REFRESH PULSE WIDTH (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
10
HIP4081A
FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL
vs TEMPERATURE
FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs
TEMPERATURE
FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL
vs TEMPERATURE
FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs
TEMPERATURE
FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K
and TA = 25°C, Unless Otherwise Specified (Continued)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
8.5
9.5
10.5
11.5
12.5
13.5
GATE DRIVE FALL TIME (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
8.5
9.5
10.5
11.5
12.5
13.5
TURN-ON RISE TIME (ns)
JUNCTION TEMPERATURE (°C)
11
HIP4081A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K and TA = 25°C, Unless Otherwise Specified
FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS
SUPPLY AND TEMPERATURE AT 100mA
FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERATURE AT 100mA
FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY
VOLTAGE
FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY
VOLTAGE
FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS
QUIESCENT COMPONENT) vs FREQUENCY AND
GATE LOAD CAPACITANCE
-40 -20 0 20 40 60 80 100 120
4.0
4.5
5.0
5.5
6.0
HDEL, LDEL INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
10 12 14
0
250
500
750
1000
1250
1500
VCC - VOH (mV)
BIAS SUPPLY VOLTAGE (V)
75°C
25°C
125°C
-40°C
0°C
12 14
0
250
500
750
1000
1250
1500
VOL (mV)
BIAS SUPPLY VOLTAGE (V)
10
75°C
25°C
125°C
-40°C
0°C
6 7 8 9 10 11 12 13 14 15 16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
GATE DRIVE SINK CURRENT (A)
VDD, VCC, VAHB, VBHB (V)
6 7 8 9 10 11 12 13 14 15 16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
GATE DRIVE SINK CURRENT (A)
VDD, VCC, VAHB, VBHB (V)
1 2 5 10 20 50 100 200 500 1000
0.1
1
10
100
500
50
5
0.5
200
20
2
0.2
LOW VOLTAGE BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz)
100pF
1,000pF
10,000pF
3,000pF
12
HIP4081A
FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE
FIGURE 29. UNDERVOLTAGE LOCKOUT vs TEMPERATURE FIGURE 30. MINIMUM DEAD-TIME vs DEL RESISTANCE
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K and TA = 25°C, Unless Otherwise Specified (Continued)
10 20 50 100 200 500 1000
10
100
1000
20
50
200
500
LEVEL-SHIFT CURRENT (μA)
SWITCHING FREQUENCY (kHz)
8.2
8.4
8.6
8.8
9.0
50 25 0 25 50 75 100 125 150
UV+
UVTEMPERATURE
(°C)
BIAS SUPPLY VOLTAGE, VDD (V)
10 50 100 150 200 250
0
30
60
90
120
150
HDEL/LDEL RESISTANCE (kΩ)
DEAD-TIME (ns)
13
HIP4081A
1
2
3
1
2
3
1
2
3
5 6
1
2
3
1 2
13 12
1
2
3
11 10
1
2
3
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
L1
R21
Q1
Q3
Q4
R22
L2
R23 C1
C3
JMPR1
R24
R30 R31
C2
R34
C4
CR2
CR1
Q2
JMPR5
JMPR3
JMPR2
JMPR4
R33
C5
C6
CX CY
C8
U1
CW CW
+
B+
IN2 IN1
BO
OUT/BLI
IN-/AHI
COM
IN+/ALI +12V
+12V
BLS
AO
HEN/BHI
ALS
CD4069UB
CD4069UB
CD4069UB
CD4069UB
HIP4080A/81A
SECTION
CONTROL LOGIC
POWER SECTION
DRIVER SECTION
AHB AHO
LDEL AHS
HDEL ALO
IN-/AHI ALS
IN+/ALI VCC
OUT/BLI VDD
VSS BLS
DIS BLO
HEN/BHI BHS
BHB BHO
R29
U2
U2
U2
U2
3 4
9 8
R32
je
O
O
CD4069UB
CD4069UB
ENABLE IN
U2
U2
NOTES:
1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V.
2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED.
REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT
LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR
JMPR1 - JMPR4.
FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC
14
HIP4081A
R22 1
Q3
L1
JMPR2
JMPR5
R31
R33
CR2
R23
R24
R27
R28
R26
1
Q4
1
JMPR3 Q2
U1
R21
GND
L2
C3
C4
JMPR4
JMPR1
R30
CR1
U2
R34
R32
je
O
C8
R29
C7
C6
C5
CY
CX
1
Q1
COM
+12V
B+
IN1
IN2
AHO
BHO
ALO
BLO
BLS
BLS
LDEL
HDEL
DIS
ALS
ALS
O
+ +
HIP4080/81
FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN
15
HIP4081A
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendicular
to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-CCL
E
eA
C
eB
eC
-BE1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-CD1
B1
B
et
ré
D1
A2 A
L
A1
-A-
0.010 (0.25) M C A B S
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.55 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC 6
eB - 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N 20 20 9
Rev0 12/93
16
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
HIP4081A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
ré
N
1 2 3
-B-
0.25(0.010) M C A B S
et
-AL
B
M
-CA1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
μ
0.25(0.010) M B M
α
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.014 0.019 0.35 0.49 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N 20 20 7
α 0o 8o 0o 8o -
Rev1 1/02
http://www.farnell.com/datasheets/32553.pdf
1
®
FN3663.5
HFA3101
Gilbert Cell UHF Transistor Array
The HFA3101 is an all NPN transistor array configured as a Multiplier Cell. Based on Intersil’s bonded wafer UHF-1 SOI process, this array achieves very high fT (10GHz) while maintaining excellent hFE and VBE matching characteristics that have been maximized through careful attention to circuit design and layout, making this product ideal for communication circuits. For use in mixer applications, the cell provides high gain and good cancellation of 2nd order distortion terms.
Pinout
HFA3101(SOIC)
TOP VIEW
Features
•Pb-free Available as an Option
•High Gain Bandwidth Product (fT) . . . . . . . . . . . . .10GHz
•High Power Gain Bandwidth Product. . . . . . . . . . . .5GHz
•Current Gain (hFE). . . . . . . . . . . . . . . . . . . . . . . . . . . ..70
•Low Noise Figure (Transistor) . . . . . . . . . . . . . . . . .3.5dB
•Excellent hFE and VBE Matching
•Low Collector Leakage Current . . . . . . . . . . . . . .<0.01nA
•Pin to Pin Compatible to UPA101
Applications
•Balanced Mixers
•Multipliers
•Demodulators/Modulators
•Automatic Gain Control Circuits
•Phase Detectors
•Fiber Optic Signal Processing
•Wireless Communication Systems
•Wide Band Amplification Stages
•Radio and Satellite Communications
•High Performance Instrumentation
Ordering Information
PART NUMBER (BRAND)
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
HFA3101B
(H3101B)
-40 to 85
8 Ld SOIC
M8.15
HFA3101BZ
(H3101B) (Note)
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
HFA3101B96
(H3101B)
-40 to 85
8 Ld SOIC Tape and Reel
M8.15
HFA3101BZ96
(H3101B) (Note)
-40 to 85
8 Ld SOIC Tape and Reel (Pb-free)
M8.15
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
12348765Q5Q6Q1Q2Q3Q4NOTE: Q5 and Q6 -
2
Paralleled 3μm x
50μm Transistors Q1, Q2, Q3, Q4 -
Single 3μm x
50μm Transistors
Data Sheet
September 2004
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1998, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Absolute Maximum Ratings
Thermal Information
VCEO, Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . .8.0V
VCBO, Collector to Base Voltage. . . . . . . . . . . . . . . . . . . . . . .12.0V
VEBO, Emitter to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . . .5.5V
IC, Collector Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to 85oC
Thermal Resistance (Typical, Note 1)θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . ..175oC
Maximum Junction Temperature (Plastic Package). . . . . . . ..150oC
Maximum Storage Temperature Range. . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . ..300oC (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical SpecificationsTA = 25oC
PARAMETER
TEST CONDITIONS
(NOTE 2)
TEST LEVEL
MIN
TYP
MAX
UNITS
Collector to Base Breakdown Voltage, V(BR)CBO, Q1 thru Q6
IC = 100μA, IE = 0
A
12
18
-
V
Collector to Emitter Breakdown Voltage, V(BR)CEO,
Q5 and Q6
IC = 100μA, IB = 0
A
8
12
-
V
Emitter to Base Breakdown Voltage, V(BR)EBO, Q1 thru Q6
IE = 10μA, IC = 0
A
5.5
6
-
V
Collector Cutoff Current, ICBO, Q1 thru Q4
VCB = 8V, IE = 0
A
-
0.1
10
nA
Emitter Cutoff Current, IEBO, Q5 and Q6
VEB = 1V, IC = 0
A
-
-
200
nA
DC Current Gain, hFE, Q1 thru Q6
IC = 10mA, VCE = 3V
A
40
70
-
Collector to Base Capacitance, CCB
Q1 thru Q4
VCB = 5V, f = 1MHz
C
-
0.300
-
pF
Q5 and Q6
-
0.600
-
pF
Emitter to Base Capacitance, CEB
Q1 thru Q4
VEB = 0, f = 1MHz
B
-
0.200
-
pF
Q5 and Q6
-
0.400
-
pF
Current Gain-Bandwidth Product, fT
Q1 thru Q4
IC = 10mA, VCE = 5V
C
-
10
-
GHz
Q5 and Q6
IC = 20mA, VCE = 5V
C
-
10
-
GHz
Power Gain-Bandwidth Product, fMAX
Q1 thru Q4
IC = 10mA, VCE = 5V
C
-
5
-
GHz
Q5 and Q6
IC = 20mA, VCE = 5V
C
-
5
-
GHz
Available Gain at Minimum Noise Figure, GNFMIN,
Q5 and Q6
IC = 5mA, VCE = 3V
f = 0.5GHz
C
-
17.5
-
dB
f = 1.0GHz
C
-
11.9
-
dB
Minimum Noise Figure, NFMIN, Q5 and Q6
IC = 5mA, VCE = 3V
f = 0.5GHz
C
-
1.7
-
dB
f = 1.0GHz
C
-
2.0
-
dB
50Ω Noise Figure, NF50Ω, Q5 and Q6
IC = 5mA, VCE = 3V
f = 0.5GHz
C
-
2.25
-
dB
f = 1.0GHz
C
-
2.5
-
dB
DC Current Gain Matching, hFE1/hFE2, Q1 and Q2,
Q3 and Q4, and Q5 and Q6
IC = 10mA, VCE = 3V
A
0.9
1.0
1.1
Input Offset Voltage, VOS, (Q1 and Q2), (Q3 and Q4),
(Q5 and Q6)
IC = 10mA, VCE = 3V
A
-
1.5
5
mV
Input Offset Current, IC, (Q1 and Q2), (Q3 and Q4),
(Q5 and Q6)
IC = 10mA, VCE = 3V
A
-
5
25
μA
Input Offset Voltage TC, dVOS/dT, (Q1 and Q2, Q3 and Q4, Q5 and Q6)
IC = 10mA, VCE = 3V
C
-
0.5
-
μV/oC
Collector to Collector Leakage, ITRENCH-LEAKAGE
ΔVTEST = 5V
B
-
0.01
-
nA
NOTE:
2. Test Level: A. Production Tested, B. Typical or Guaranteed Limit Based on Characterization, C. Design Typical for Information Only.
HFA3101
3-3
PSPICE Model for a 3 μm x 50μm Transistor
.Model NUHFARRY NPN
+ (IS = 1.840E-16
XTI = 3.000E+00
EG = 1.110E+00
VAF = 7.200E+01
+ VAR = 4.500E+00
BF = 1.036E+02
ISE = 1.686E-19
NE = 1.400E+00
+ IKF = 5.400E-02
XTB = 0.000E+00
BR = 1.000E+01
ISC = 1.605E-14
+ NC = 1.800E+00
IKR = 5.400E-02
RC = 1.140E+01
CJC = 3.980E-13
+ MJC = 2.400E-01
VJC = 9.700E-01
FC = 5.000E-01
CJE = 2.400E-13
+ MJE = 5.100E-01
VJE = 8.690E-01
TR = 4.000E-09
TF = 10.51E-12
+ ITF = 3.500E-02
XTF = 2.300E+00
VTF = 3.500E+00
PTF = 0.000E+00
+ XCJC = 9.000E-01
CJS = 1.689E-13
VJS = 9.982E-01
MJS = 0.000E+00
+ RE = 1.848E+00
RB = 5.007E+01
RBM = 1.974E+00
KF = 0.000E+00
+ AF = 1.000E+00)
Common Emitter S-Parameters of 3 μm x 50μm Transistor
FREQ. (Hz)
|S11|
PHASE(S11)
|S12|
PHASE(S12)
|S21|
PHASE(S21)
|S22|
PHASE(S22)
VCE = 5V and IC = 5mA
1.0E+08
0.83
-11.78
1.41E-02
78.88
11.07
168.57
0.97
-11.05
2.0E+08
0.79
-22.82
2.69E-02
68.63
10.51
157.89
0.93
-21.35
3.0E+08
0.73
-32.64
3.75E-02
59.58
9.75
148.44
0.86
-30.44
4.0E+08
0.67
-41.08
4.57E-02
51.90
8.91
140.36
0.79
-38.16
5.0E+08
0.61
-48.23
5.19E-02
45.50
8.10
133.56
0.73
-44.59
6.0E+08
0.55
-54.27
5.65E-02
40.21
7.35
127.88
0.67
-49.93
7.0E+08
0.50
-59.41
6.00E-02
35.82
6.69
123.10
0.62
-54.37
8.0E+08
0.46
-63.81
6.27E-02
32.15
6.11
119.04
0.57
-58.10
9.0E+08
0.42
-67.63
6.47E-02
29.07
5.61
115.57
0.53
-61.25
1.0E+09
0.39
-70.98
6.63E-02
26.45
5.17
112.55
0.50
-63.96
1.1E+09
0.36
-73.95
6.75E-02
24.19
4.79
109.91
0.47
-66.31
1.2E+09
0.34
-76.62
6.85E-02
22.24
4.45
107.57
0.45
-68.37
1.3E+09
0.32
-79.04
6.93E-02
20.53
4.15
105.47
0.43
-70.19
1.4E+09
0.30
-81.25
7.00E-02
19.02
3.89
103.57
0.41
-71.83
1.5E+09
0.28
-83.28
7.05E-02
17.69
3.66
101.84
0.40
-73.31
1.6E+09
0.27
-85.17
7.10E-02
16.49
3.45
100.26
0.39
-74.66
1.7E+09
0.25
-86.92
7.13E-02
15.41
3.27
98.79
0.38
-75.90
1.8E+09
0.24
-88.57
7.17E-02
14.43
3.10
97.43
0.37
-77.05
1.9E+09
0.23
-90.12
7.19E-02
13.54
2.94
96.15
0.36
-78.12
2.0E+09
0.22
-91.59
7.21E-02
12.73
2.80
94.95
0.35
-79.13
2.1E+09
0.21
-92.98
7.23E-02
11.98
2.68
93.81
0.35
-80.09
2.2E+09
0.20
-94.30
7.25E-02
11.29
2.56
92.73
0.34
-80.99
2.3E+09
0.20
-95.57
7.27E-02
10.64
2.45
91.70
0.34
-81.85
2.4E+09
0.19
-96.78
7.28E-02
10.05
2.35
90.72
0.33
-82.68
2.5E+09
0.18
-97.93
7.29E-02
9.49
2.26
89.78
0.33
-83.47
2.6E+09
0.18
-99.05
7.30E-02
8.96
2.18
88.87
0.33
-84.23
2.7E+09
0.17
-100.12
7.31E-02
8.47
2.10
88.00
0.33
-84.97
HFA3101
4
2.8E+09
0.17
-101.15
7.31E-02
8.01
2.02
87.15
0.33
-85.68
2.9E+09
0.16
-102.15
7.32E-02
7.57
1.96
86.33
0.33
-86.37
3.0E+09
0.16
-103.11
7.32E-02
7.16
1.89
85.54
0.33
-87.05
VCE = 5V and IC = 10mA
1.0E+08
0.72
-16.43
1.27E-02
75.41
15.12
165.22
0.95
-14.26
2.0E+08
0.67
-31.26
2.34E-02
62.89
13.90
152.04
0.88
-26.95
3.0E+08
0.60
-43.76
3.13E-02
52.58
12.39
141.18
0.79
-37.31
4.0E+08
0.53
-54.00
3.68E-02
44.50
10.92
132.57
0.70
-45.45
5.0E+08
0.47
-62.38
4.05E-02
38.23
9.62
125.78
0.63
-51.77
6.0E+08
0.42
-69.35
4.31E-02
33.34
8.53
120.37
0.57
-56.72
7.0E+08
0.37
-75.26
4.49E-02
29.47
7.62
116.00
0.51
-60.65
8.0E+08
0.34
-80.36
4.63E-02
26.37
6.86
112.39
0.47
-63.85
9.0E+08
0.31
-84.84
4.72E-02
23.84
6.22
109.36
0.44
-66.49
1.0E+09
0.29
-88.83
4.80E-02
21.75
5.69
106.77
0.41
-68.71
1.1E+09
0.27
-92.44
4.86E-02
20.00
5.23
104.51
0.39
-70.62
1.2E+09
0.25
-95.73
4.90E-02
18.52
4.83
102.53
0.37
-72.28
1.3E+09
0.24
-98.75
4.94E-02
17.25
4.49
100.75
0.35
-73.76
1.4E+09
0.22
-101.55
4.97E-02
16.15
4.19
99.16
0.34
-75.08
1.5E+09
0.21
-104.15
4.99E-02
15.19
3.93
97.70
0.33
-76.28
1.6E+09
0.20
-106.57
5.01E-02
14.34
3.70
96.36
0.32
-77.38
1.7E+09
0.20
-108.85
5.03E-02
13.60
3.49
95.12
0.31
-78.41
1.8E+09
0.19
-110.98
5.05E-02
12.94
3.30
93.96
0.31
-79.37
1.9E+09
0.18
-113.00
5.06E-02
12.34
3.13
92.87
0.30
-80.27
2.0E+09
0.18
-114.90
5.07E-02
11.81
2.98
91.85
0.30
-81.13
2.1E+09
0.17
-116.69
5.08E-02
11.33
2.84
90.87
0.30
-81.95
2.2E+09
0.17
-118.39
5.09E-02
10.89
2.72
89.94
0.29
-82.74
2.3E+09
0.16
-120.01
5.10E-02
10.50
2.60
89.06
0.29
-83.50
2.4E+09
0.16
-121.54
5.11E-02
10.13
2.49
88.21
0.29
-84.24
2.5E+09
0.16
-122.99
5.12E-02
9.80
2.39
87.39
0.29
-84.95
2.6E+09
0.15
-124.37
5.12E-02
9.49
2.30
86.60
0.29
-85.64
2.7E+09
0.15
-125.69
5.13E-02
9.21
2.22
85.83
0.29
-86.32
2.8E+09
0.15
-126.94
5.13E-02
8.95
2.14
85.09
0.29
-86.98
2.9E+09
0.15
-128.14
5.14E-02
8.71
2.06
84.36
0.29
-87.62
3.0E+09
0.14
-129.27
5.15E-02
8.49
1.99
83.66
0.29
-88.25
Common Emitter S-Parameters of 3 μm x 50 μm Transistor (Continued)
FREQ. (Hz) |S11| PHASE(S11) |S12| PHASE(S12) |S21| PHASE(S21) |S22| PHASE(S22)
HFA3101
3-5
Application Information
The HFA3101 array is a very versatile RF Building block. It has been carefully laid out to improve its matching properties, bringing the distortion due to area mismatches, thermal distribution, betas and ohmic resistances to a minimum.
The cell is equivalent to two differential stages built as two “variable transconductance multipliers” in parallel, with their outputs cross coupled. This configuration is well known in the industry as a Gilbert Cell which enables a four quadrant multiplication operation.
Due to the input dynamic range restrictions for the input levels at the upper quad transistors and lower tail transistors, the HFA3101 cell has restricted use as a linear four quadrant multiplier. However, its configuration is well suited for uses where its linear response is limited to one of the inputs only, as in modulators or mixer circuit applications. Examples of these circuits are up converters, down converters, frequency doublers and frequency/phase detectors.
Although linearization is still an issue for the lower pair input, emitter degeneration can be used to improve the dynamic range and consequent linearity. The HFA3101 has the lower pair emitters brought to external pins for this purpose.
In modulators applications, the upper quad transistors are used in a switching mode where the pairs Q1/Q2 and Q3/Q4 act as non saturating high speed switches. These switches are controlled by the signal often referred as the carrier input. The signal driving the lower pair Q5/Q6 is commonly used as the modulating input. This signal can be linearly transferred to the output by either the use of low signal levels (Well below the thermal voltage of 26mV) or by the use of emitter degeneration. The chopped waveform appearing at the output of the upper pair (Q1 to Q4) resembles a signal that is multiplied by +1 or -1 at every half cycle of the switching waveform.
Figure 1 shows the typical input waveforms where the frequency of the carrier is higher than the modulating signal. The output waveform shows a typical suppressed carrier output of an up converter or an AM signal generator.
Carrier suppression capability is a property of the well known Balanced modulator in which the output must be zero when one or the other input (carrier or modulating signal) is equal to zero. however, at very high frequencies, high frequency mismatches and AC offsets are always present and the suppression capability is often degraded causing carrier and modulating feedthrough to be present.
Being a frequency translation circuit, the balanced modulator has the properties of translating the modulating frequency (ωM) to the carrier frequency (ωC), generating the two side bands ωU = ωC + ωM and ωL = ωC - ωM. Figure 2 shows some translating schemes being used by balanced mixers.
CARRIER SIGNALMODULATING SIGNALDIFFERENTIAL OUTPUT+1-1FIGURE 1. TYPICAL MODULATOR SIGNALS
FIGURE 2A. UP CONVERSION OR SUPPRESSED CARRIER AM
FIGURE 2B. DOWN CONVERSION
FIGURE 2C. ZERO IF OR DIRECT DOWN CONVERSION
FIGURE 2. MODULATOR FREQUENCY SPECTRUM
ωC + ωMωC - ωMωC
IF (ωC - ωM)FOLDED BACKωMωC
BASEBANDωCωM
HFA3101
6
The use of the HFA3101 as modulators has several advantages when compared to its counterpart, the diode doublebalanced mixer, in which it is required to receive enough energy to drive the diodes into a switching mode and has also some requirements depending on the frequency range desired, of different transformers to suit specific frequency responses. The HFA3101 requires very low driving capabilities for its carrier input and its frequency response is limited by the fT of the devices, the design and the layout techniques being utilized.
Up conversion uses, for UHF transmitters for example, can be performed by injecting a modulating input in the range of 45MHz to 130MHz that carries the information often called IF (Intermediate frequency) for up conversion (The IF signal has been previously modulated by some modulation scheme from a baseband signal of audio or digital information) and by injecting the signal of a local oscillator of a much higher frequency range from 600MHz to 1.2GHz into the carrier input. Using the example of a 850MHz carrier input and a 70MHz IF, the output spectrum will contain a upper side band of 920MHz, a lower side band of 780MHz and some of the carrier (850MHz) and IF (70MHz) feedthrough. A Band pass filter at the output can attenuate the undesirable signals and the 920MHz signal can be routed to a transmitter RF power amplifier.
Down conversion, as the name implies, is the process used to translate a higher frequency signal to a lower frequency range conserving the modulation information contained in the higher frequency signal. One very common typical down conversion use for example, is for superheterodyne radio receivers where a translated lower frequency often referred as intermediate frequency (IF) is used for detection or demodulation of the baseband signal. Other application uses include down conversion for special filtering using frequency translation methods.
An oscillator referred as the local oscillator (LO) drives the upper quad transistors of the cell with a frequency called ωC. The lower pair is driven by the RF signal of frequency ωM to be translated to a lower frequency IF. The spectrum of the IF output will contain the sum and difference of the frequencies ωC and ωM. Notice that the difference can become negative when the frequency of the local oscillator is lower than the incoming frequency and the signal is folded back as in Figure 2.
NOTE: The acronyms RF, IF and LO are often interchanged in the industry depending on the application of the cell as mixers or modulators. The output of the cell also contains multiples of the frequency of the signal being fed to the upper quad pair of transistors because of the switching action equivalent to a square wave multiplication. In practice, however, not only the odd multiples in the case of a symmetrical square wave but some of the even multiples will also appear at the output spectrum due to the nature of the actual switching waveform and high frequency performance. By-products of the form M*ωC + N*ωM with M and N being positive or negative integers are also expected to be present at the output and their levels are carefully examined and minimized by the design. This distortion is considered one of the figures of merit for a mixer application.
The process of frequency doubling is also understood by having the same signal being fed to both modulating and carrier ports. The output frequency will be the sum of ωC and ωM which is equivalent to the product of the input frequency by 2 and a zero Hz or DC frequency equivalent to the difference of ωC and ωM. Figure 2 also shows one technique in use today where a process of down conversion named zero IF is made by using a local oscillator with a very pure signal frequency equal to the incoming RF frequency signal that contains a baseband (audio or digital signal) modulation. Although complex, the extraction or detection of the signal is straightforward.
Another useful application of the HFA3101 is its use as a high frequency phase detector where the two signals are fed to the carrier and modulation ports and the DC information is extracted from its output. In this case, both ports are utilized in a switching mode or overdrive, such that the process of multiplication takes place in a quasi digital form (2 square waves). One application of a phase detector is frequency or phase demodulation where the FM signal is split before the modulating and carrier ports. The lower input port is always 90 degrees apart from the carrier input signal through a high Q tuned phase shift network. The network, being tuned for a precise 90 degrees shift at a nominal frequency, will set the two signals 90 degrees apart and a quiescent output DC level will be present at the output. When the input signal is frequency modulated, the phase shift of the signal coming from the network will deviate from 90 degrees proportional to the frequency deviation of the FM signal and a DC variation at the output will take place, resembling the demodulated FM signal.
The HFA3101 could also be used for quadrature detection, (I/Q demodulation), AGC control with limited range, low level multiplication to name a few other applications.
Biasing
Various biasing schemes can be employed for use with the HFA3101. Figure 3 shows the most common schemes. The biasing method is a choice of the designer when cost, thermal dependence, voltage overheads and DC balancing properties are taken into consideration.
Figure 3A shows the simplest form of biasing the HFA3101. The current source required for the lower pair is set by the voltage across the resistor RBIAS less a VBE drop of the lower transistor. To increase the overhead, collector resistors are substituted by an RF choke as the upper pair functions as a current source for AC signals. The bases of the upper and lower transistors are biased by RB1 and RB2 respectively. The voltage drop across the resistor R2 must be higher than a VBE with an increase sufficient to assure that the collector to base junctions of the lower pair are always reverse biased. Notice that this same voltage also sets the VCE of operation of the lower pair which is important for the optimization of gain. Resistors REE are nominally zero for applications where the input signals are well below 25mV peak. Resistors REE are used to increase the linearity
HFA3101
3-7
of the circuit upon higher level signals. The drop across REE must be taken into consideration when setting the current source value.
Figure 3B depicts the use of a common resistor sharing the current through the cell which is used for temperature compensation as the lower pair VBE drop at the rate of -2mV/oC.
Figure 3C uses a split supply.
Design Example: Down Converter Mixer
Figure 4 shows an example of a low cost mixer for cellular applications.
The design flexibility of the HFA3101 is demonstrated by a low cost, and low voltage mixer application at the 900MHz range. The choice of good quality chip components with their self resonance outside the boundaries of the application are important. The design has been optimized to accommodate the evaluation of the same layout for various quiescent current values and lower supply voltages. The choice of RE became important for the available overhead and also for maintaining an AC true impedance for high frequency signals. The value of 27Ω has been found to be the optimum minimum for the application. The input impedances of the HFA3101 base input ports are high enough to permit their termination with 50Ω resistors. Notice the AC termination by decoupling the bias circuit through good quality capacitors.
The choice of the bias has been related to the available power supply voltage with the values of R1, R2 and RBIAS splitting the voltages for optimum VCE values. For evaluation of the cell quiescent currents, the voltage at the emitter resistor RE has been recorded.
The gain of the circuit, being a function of the load and the combined emitter resistances at high frequencies have been kept to a maximum by the use of an output match network. The high output impedance of the HFA3101 permits
FIGURE 3A.
FIGURE 3B.
FIGURE 3C.
FIGURE 3.
VCCRB1R1R2RBIASREREEREELCH12348765Q5Q6Q1Q2Q3Q4RB2
VCCRB1R1R2RBIASREREEREE12348765Q5Q6Q1Q2Q3Q4RB2RCLCH
VEERB1R1RBIASREREEREE12348765Q5Q6Q1Q2Q3Q4RB2VCCLCHR2
27LCH12348765Q5Q6Q1Q2Q3Q4VCC390nH0.010.011102200.1VCC3V75MHz2K5p TO 12pLO IN51825MHz51900MHzIF OUTRF IN0.010.010.01330FIGURE 4. 3V DOWN CONVERTER APPLICATION
HFA3101
8
broadband match if so desired at 50Ω (RL = 50Ω to 2kΩ) as well as with tuned medium Q matching networks (L, T etc.).
Stability
The cell, by its nature, has very high gain and precautions must be taken to account for the combination of signal reflections, gain, layout and package parasitics. The rule of thumb of avoiding reflected waves must be observed. It is important to assure good matching between the mixer stage and its front end. Laboratory measurements have shown some susceptibility for oscillation at the upper quad transistors input. Any LO prefiltering has to be designed such the return loss is maintained within acceptable limits specially at high frequencies. Typical off the shelf filters exhibits very poor return loss for signals outside the passband. It is suggested that a “pad” or a broadband resistive network be used to interface the LO port with a filter. The inclusion of a parallel 2K resistor in the load decreases the gain slightly which improves the stability factor and also improves the distortion products (output intermodulation or 3rd order intercept). The employment of good RF techniques shall suffice the stability requirements.
Evaluation
The evaluation of the HFA3101 in a mixer configuration is presented in Figures 6 to 11, Table 1 and Table 2. The layout is depicted in Figure 5.
The output matching network has been designed from data taken at the output port at various test frequencies with the setup as in Table 1. S22 characterization is enough to assure the calculation of L, T or transmission line matching networks.
FIGURE 5. UP/DOWN CONVERTER LAYOUT, 400%; MATERIAL G10, 0.031
TABLE 1. S22 PARAMETERS FOR DOWN CONVERSION, LCH = 10μH
FREQUENCY
RESISTANCE
REACTANCE
10MHz
265Ω
615Ω
45MHz
420Ω
- 735Ω
75MHz
122Ω
- 432Ω
100MHz
67Ω
- 320Ω
TABLE 2. TYPICAL PARAMETERS FOR DOWN CONVERSION, LCH = 10μH
PARAMETER
LO LEVEL
VCC = 3V, IBIAS = 8mA
Power Gain
-6dBm
8.5dB
TOI Output
-6dBm
11.5dBm
NF SSB
-6dBm
14.5dB
Power Gain
0dBm
8.6dB
TOI Output
0dBm
11dBm
NF SSB
0dBm
15dB
PARAMETER
LO LEVEL
VCC = 4V, IBIAS = 19mA
Power Gain
-6dBm
10dB
TOI Output
-6dBm
13dBm
NF SSB
-6dBm
20dB
Power Gain
0dBm
11dB
TOI Output
0dBm
12.5dBm
NF SSB
0dBm
24dB
TABLE 3. TYPICAL VALUES OF S22 FOR THE OUTPUT PORT. LCH = 390nH IBIAS = 8mA (SET UP OF FIGURE 11)
FREQUENCY
RESISTANCE
REACTANCE
300MHz
22Ω
-115Ω
600MHz
7.5Ω
-43Ω
900MHz
5.2Ω
-14Ω
1.1GHz
3.9Ω
0Ω
TABLE 4. TYPICAL VALUES OF S22. LCH = 390nH, IBIAS = 18mA
FREQUENCY
RESISTANCE
REACTANCE
300MHz
23.5Ω
-110Ω
600MHz
10.3Ω
-39Ω
900MHz
8.7Ω
-14Ω
1.1GHz
8Ω
0Ω
HFA3101
3-9
Up Converter Example
An application for a up converter as well as a frequency multiplier can be demonstrated using the same layout, with an addition of matching components. The output port S22 must be characterized for proper matching procedures and depending on the frequency desired for the output, transmission line transformations can be designed. The return loss of the input ports maintain acceptable values in excess of 1.2GHz which can permit the evaluation of a frequency doubler to 2.4GHz if so desired.
The addition of the resistors REE can increase considerably the dynamic range of the up converter as demonstrated at Figure 13. The evaluation results depicted in Table 5 have been obtained by a triple stub tuner as a matching network for the output due to the layout constraints. Based on the evaluation results it is clear that the cell requires a higher Bias current for overall performance.
FIGURE 6. OUTPUT PORT S22 TEST SET UP
FIGURE 7. LO PORT RETURN LOSS
FIGURE 8. RF PORT RETURN LOSS
FIGURE 9. IF PORT RETURN LOSS, WITH MATCHING NETWORK
FIGURE 10. TYPICAL IN BAND OUTPUT SPECTRUM, VCC = 3V
FIGURE 11. TYPICAL OUT OF BAND OUTPUT SPECTRUM
VCC 3V0.1LCH12348765Q5Q6Q1Q2Q3Q42K
S110dB5dB/DIV100MHz1.1GHzLOG MAG3V4V
0dB10dB/DIV100MHz1.1GHzS11LOG MAG
0dB5dB/DIV10MHzS22LOG MAG110MHz
76MHz64M11*LO - 10RF88M12RF - 13LOIFSPAN40MHzLO = 825MHz -6dBmRF = 901MHz - 25dBm-17dBm10dB/DIV
67575082590097510dB/DIVLO + 2RFSPAN500MHzLO - 2RF-26dBm-36dBm-58dBm-53dBmLO = 825MHz -6dBmRF = 900MHz -25dBm
HFA3101
10
Design Example: Up Converter Mixer
Figure 12 shows an example of an up converter for cellular applications.
Conclusion
The HFA3101 offers the designer a number of choices and different applications as a powerful RF building block. Although isolation is degraded from the theoretical results for the cell due to the unbalanced, nondifferential input schemes being used, a number of advantages can be taken into consideration like cost, flexibility, low power and small outline when deciding for a design.
TABLE 5. TYPICAL PARAMETERS FOR THE UP CONVERTER EXAMPLE
PARAMETER
VCC = 3V, IBIAS = 8mA
VCC = 4V, IBIAS = 18mA
Power Gain, LO = -6dBm
3dB
5.5dBm
Power Gain, LO = 0dBm
4dB
7.2dB
RF Isolation, LO = 0dBm
15dBc
22dBc
LO Isolation, LO = 0dBm
28dBc
28dBc
FIGURE 12. UP CONVERTER
FIGURE 13. TYPICAL SPECTRUM PERFORMANCE OF UP CONVERTER
RF IN0.01390nH900MHz5.2nHVCC 3V0.112348765Q5Q6Q1Q2Q3Q411p0.0175MHz27220REEREE51LO INVCC0.010.011103303V825MHz0.010.015147-100pF
9019128902LO - 10RF12RFOUTPUT WITHOUT EMITTER DEGENERATIONRF = 76MHzLO = 825MHzSPAN50MHzOUTPUT WITH EMITTER DEGENERATION REE = 4.7Ω825900976EXPANDED SPECTRUM REE = 4.7Ω
HFA3101
3-11
Typical Performance Curves for Transistors
FIGURE 14. IC vs VCE
FIGURE 15. HFE vs IC
FIGURE 16. GUMMEL PLOT
FIGURE 17. fT vs IC
FIGURE 18. GAIN AND NOISE FIGURE vs FREQUENCY
NOTE: Figures 14 through 18 are only for Q5 and Q6.
VCE (V)IC (mA)02.06.04.0070605040302010IB = 800μAIB = 1mAIB = 200μAIB = 400μAIB = 600μA
hFEIC (
A)10-1010-810-610-410-2100140120100806040200VCE = 5V
VBE (V)IC AND IB (A)10-1010-810-610-410-210010-120.200.400.600.801.0VCE = 3V
IC (A)fT (GHz)12108642010-410-310-210-1
20181614121046NOISE FIGURE (
dB)FREQUENCY (GHz)|S21| (dB)0.51.51.02.002.53.04.84.64.44.24.03.83.63.43.28
HFA3101
12
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable.
However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Die Characteristics
PROCESS UHF-1
DIE DIMENSIONS: 53 mils x 52 mils x 14 mils
1340μm x 1320μm x 355.6μm
METALLIZATION: Type: Metal 1: AlCu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.5kÅ Type: Metal 2: AlCu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
PASSIVATION: Type: Nitride
Thickness: 4kÅ ±0.5kÅ
SUBSTRATE POTENTIAL (Powered Up): Floating
Metallization Mask Layout
HFA31011122334455667788
HFA3101
16-Bit Low Power Sigma-Delta ADC
Data Sheet AD7171
RevA Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use.Specifications subject to change without notice. Non.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Output data rate: 125 Hz
Pin-programmable power-down and reset
Status function
Internal clock oscillator
Current: 135 μA
Power supply: 2.7 V to 5.25 V
–40°C to +105°C temperature range
Package: 10-lead 3 mm x 3 mm LFCSP
INTERFACE
2-wire serial (read-only device)
SPI compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Pressure measurement
Industrial process control
Portable instrumentation
FUNCTIONAL BLOCK DIAGRAM
16-BIT Σ-ΔADCAD7171GNDINTERNALCLOCKVDDREFIN(+)AIN(+)AIN(–)REFIN(–)DOUT/RDYSCLKPDRST08417-001
Figure 1.
Table 1.
VREF = VDD
RMS Noise
P-P Noise
P-P Resolution
ENOB
5 V
11.5 μV
76 μV
16 bits
16 bits
3 V
6.9 μV
45 μV
16 bits
16 bits
GENERAL DESCRIPTION
The AD7171 is a very low power 16-bit analog-to-digital converter (ADC). It contains a precision 16-bit sigma-delta (Σ-Δ) ADC and an on-chip oscillator. Consuming only 135 μA, the AD7171 is particularly suitable for portable or battery operated products where very low power is a requirement. The AD7171 also has a power-down mode in which the device consumes 5 μA, thus increasing the battery life of the product.
For ease-of-use, all the features of the AD7171 are controlled by dedicated pins. Each time a data read occurs, eight status bits are appended to the 16-bit conversion. These status bits contain a pattern sequence that can be used to confirm the validity of the serial transfer.
The output data rate of the AD7171 is 125 Hz, whereas the settling time is 24 ms. The AD7171 has one differential input and a gain of 1. This is useful in applications where the user needs to use an external amplifier to implement system-specific filtering or gain requirements.
The AD7171 operates with a power supply from 2.7 V to 5.25 V. It is available in a 10-lead LFCSP package.
The AD7170 is a 12-bit version of the AD7171. It has the same feature set as the AD7171 and is pin-for-pin compatible.
1
Low-Noise 24-bit Delta Sigma ADC
ISL26132, ISL26134
The ISL26132 and ISL26134 are complete analog front ends
for high resolution measurement applications. These 24-bit
Delta-Sigma Analog-to-Digital Converters include a very
low-noise amplifier and are available as either two or four
differential multiplexer inputs. The devices offer the same
pinout as the ADS1232 and ADS1234 devices and are
functionally compatible with these devices. The ISL26132 and
ISL26134 offer improved noise performance at 10Sps and
80Sps conversion rates.
The on-chip low-noise programmable-gain amplifier provides
gains of 1x/2x/64x/128x. The 128x gain setting provides an
input range of ±9.766mVFS when using a 2.5V reference. la
high input impedance allows direct connection of sensors such
as load cell bridges to ensure the specified measurement
accuracy without additional circuitry. The inputs accept signals
100mV outside the supply rails when the device is set for unity
gain.
The Delta-Sigma ADC features a third order modulator
providing up to 21.6-bit noise-free performance.
The device can be operated from an external clock source,
crystal (4.9152MHz typical), or the on-chip oscillator.
The two channel ISL26132 is available in a 24 Ld TSSOP
package and the four channel ISL26134 is available in a 28 Ld
TSSOP package. Both are specified for operation over the
automotive temperature range (-40°C to +105°C).
Features
• Up to 21.6 Noise-free bits.
• Low Noise Amplifier with Gains of 1x/2x/64x/128x
• RMS noise: 10.2nV @ 10Sps (PGA = 128x)
• Linearity Error: 0.0002% FS
• Simultaneous rejection of 50Hz and 60Hz (@ 10Sps)
• Two (ISL26132) or four (ISL26134) channel differential
input multiplexer
• On-chip temperature sensor (ISL26132)
• Automatic clock source detection
• Simple interface to read conversions
• +5V Analog, +5 to +2.7V Digital Supplies
• Pb-Free (RoHS Compliant)
• TSSOP packages: ISL26132, 24 pin; ISL26134, 28 pin
Applications
• Weigh Scales
• Temperature Monitors and Controls
• Industrial Process Control
• Pressure Sensors
ADC
PGA
1x/2x/64x/
128x
INTERNAL
CLOCK
SDO/RDY
SCLK
AVDD DVDD
AGND DGND
XTALIN/CLOCK
VREF+
EXTERNAL
OSCILLATOR
XTALOUT
A0 A1/TEMP VREFAIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
INPUT
MULTIPLEXER
ISL26134
Only
CAP
CAP
GAIN0 GAIN1
PWDN
SPEED
DGND DGND
NOTE for A1/TEMP pin: Functions as A1 on ISL26134; Functions as TEMP on ISL26132
FIGURE 1. BLOCK DIAGRAM
September 9, 2011
FN6954.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL26132, ISL26134
2 FN6954.1
September 9, 2011
Ordering Information
PART NUMBER
(Notes 2, 3) PART MARKING
TEMPERATURE RANGE
(°C)
PACKAGE
(Pb-free)
PKG. DWG
NUMBER
ISL26132AVZ 26132 AVZ -40 to +105 24 Ld TSSOP M24.173
ISL26132AVZ-T (Note 1) 26132 AVZ -40 to +105 24 Ld TSSOP (Tape & Reel) M24.173
ISL26132AVZ-T7A (Note 1) 26132 AVZ -40 to +105 24 Ld TSSOP (Tape & Reel) M24.173
ISL26134AVZ 26134 AVZ -40 to +105 28 Ld TSSOP M28.173
ISL26134AVZ-T (Note 1) 26134 AVZ -40 to +105 28 Ld TSSOP (Tape & Reel) M28.173
ISL26134AVZ-T7A (Note 1) 26134 AVZ -40 to +105 28 Ld TSSOP (Tape & Reel) M28.173
ISL26134AV28EV1Z Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL26132, ISL26134. For more information on MSL please see techbrief
TB363.
TABLE 1. KEY DIFFERENCES OF PARTS
PART NUMBER NUMBER OF CHANNELS ON-CHIP TEMPERATURE SENSOR NUMBER OF PINS
ISL26132 2 YES 24
ISL26134 4 NO 28
Pin Configurations
ISL26132
(24 LD TSSOP)
TOP VIEW
ISL26134
(28 LD TSSOP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
DVDD
DGND
XTALIN/CLOCK
XTALOUT
DGND
DGND
TEMP
A0
CAP
CAP
AIN1+
AIN1-
SDO/RDY
PDWN
SPEED
GAIN1
GAIN0
AGND
VREFAIN2+
AIN2-
SCLK
AVDD
VREF+
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DVDD
DGND
XTALIN/CLOCK
XTALOUT
DGND
DGND
A1
A0
CAP
CAP
AIN1+
AIN1-
AIN3+
AIN3-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SDO/RDY
PDWN
SPEED
GAIN1
GAIN0
AGND
VREFAIN2+
AIN2-
AIN4+
AIN4-
SCLK
AVDD
VREF+
ISL26132, ISL26134
3 FN6954.1
September 9, 2011
Pin Descriptions
NAME
PIN NUMBER
ANALOG/DIGITAL
ISL26132 ISL26134 INPUT/OUTPUT DESCRIPTION
DVDD 1 1 Digital Digital Power Supply (2.7V to 5.25V)
DGND 2, 5, 6 2, 5, 6 Digital Digital Ground
XTALIN/CLOCK 3 3 Digital/Digital Input External Clock Input: typically 4.9152MHz. Tie low to activate
internal oscillator. Can also use external crystal across
XTALIN/CLOCK and XTALOUT pins.
XTALOUT 4 4 Digital External Crystal connection
TEMP 7 - Digital Input On-chip Temperature Diode Enable
A1
A0
-
8
7
8
Digital Input
CAP 9, 10 9, 10 Analog PGA Filter Capacitor
AIN1+ 11 11 Analog Input Positive Analog Input Channel 1
AIN1- 12 12 Analog Input Negative Analog Input Channel 1
AIN3+ - 13 Analog Input Positive Analog Input Channel 3
AIN3- - 14 Analog Input Negative Analog Input Channel 3
AIN4- - 15 Analog Input Negative Analog Input Channel 4
AIN4+ - 16 Analog Input Positive Analog Input Channel 4
AIN2- 13 17 Analog Input Negative Analog Input Channel 2
AIN2+ 14 18 Analog Input Positive Analog Input Channel 2
VREF- 15 19 Analog Input Negative Reference Input
VREF+ 16 20 Analog Input Positive Reference Input
AGND 17 21 Analog Analog Ground
AVDD 18 22 Analog Analog Power Supply 4.75V to 5.25V
GAIN0
GAIN1
19
20
23
24
Digital Input
TABLE 2. INPUT MULTIPLEXER SELECT
ISL26134 ISL26132
A1 A0 CHANNEL
0 0 AIN1
0 1 AIN2
1 0 AIN3
1 1 AIN4
TABLE 3. GAIN SELECT
GAIN1 GAIN0 GAIN
0 0 1
0 1 2
1 0 64
1 1 128
ISL26132, ISL26134
4 FN6954.1
September 9, 2011
Circuit Description
The ISL26132 (2-channel) and ISL26134 (4-channel) devices are
very low noise 24-bit delta-sigma ADCs that include a
programmable gain amplifier and an input multiplexer. la
ISL26132 offers an on-chip temperature measurement
capability.
The ISL26132, ISL26134 provide pin compatibility and output
data compatibility with the ADS1232/ADS1234, and offer the
same conversion rates of 10Sps and 80Sps.
All the features of the ISL26132, ISL26134 are pin-controllable,
while offset calibration, standby mode, and output conversion
data are accessible through a simple 2-wire interface.
The clock can be selected to come from an internal oscillator, an
external clock signal, or crystal (4.9152MHz typical).
SPEED 21 25 Digital Input
PDWN 22 26 Digital Input Power-Down: Holding this pin low powers down the entire
converter and resets the ADC.
SCLK 23 27 Digital Input Serial Clock: Clock out data on the rising edge. Also used to
initiate Offset Calibration and Sleep modes. See “Serial Clock
Input (SCLK)” on page 14 for more details.
SDO/RDY 24 28 Digital Output Dual-Purpose Output:
Data Ready: Indicate valid data by going low.
Data Output: Outputs data, MSB first, on the first rising edge
of SCLK.
Pin Descriptions (Continued)
NAME
PIN NUMBER
ANALOG/DIGITAL
ISL26132 ISL26134 INPUT/OUTPUT DESCRIPTION
TABLE 4. DATA RATE SELECT
SPEED DATA RATE
0 10Sps
1 80Sps
ISL26132, ISL26134
5 FN6954.1
September 9, 2011
Absolute Maximum Ratings Thermal Information
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.3V
Analog In to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to AVDD+0.3V
Digital In to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to DVDD+0.3V
Input Current
Momentary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . ..7.5kV
Machine Model (Per JESD22-A115). . . . . . . . . . . . . . . . . . . . . . . . . .450V
Charged Device Model (Per JESD22-C101) . . . . . . . . . . . . . . . . . . . . . . . .2kV
Latch-up (Per JEDEC JESD-78B; Class 2, Level A)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA @ Room and Hot (+105°C)
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
24 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .65 18
28 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .63 18
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . ..+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . ..-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..-40°C to +105°C
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..4.75V to 5.25V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 5.25V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VREF+ = 5V, VREF- = 0V, AVDD = 5V, DVDD = 5V, AGND = DGND = 0V, MCLK = 4.9152MHz, and
TA = -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C
SYMBOL PARAMETER TEST LEVEL or NOTES
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ANALOG INPUTS
Differential Input Voltage Range ±0.5VREF/
Gain
V
Common Mode Input Voltage
gamme
Gain = 1, 2 AGND - 0.1 AVDD + 0.1 V
Gain = 64, 128 AGND+1.5 AVDD - 1.5 V
Differential Input Current
Gain = 1 ±20 nA
Gain = 2 ±40 nA
Gain = 64, 128 ±1 nA
SYSTEM PERFORMANCE
Resolution No Missing Codes 24 Bits
Data Rate
Internal Osc. SPEED = High 80 SPS
Internal Osc. SPEED = Low 10 SPS
External Osc. SPEED = High fCLK/61440 SPS
External Osc. SPEED = Low fCLK/49152
0
SPS
Digital Filter Settling Time Full Setting 4 Conversions
INL Integral Nonlinearity Differential Input Gain = 1, 2 ±0.0002 ±0.001 % of FSR (Note 7)
Differential Input Gain = 64, 128 ±0.0004 % of FSR
(Note 7)
Input Offset Error Gain = 1 ±0.4 ppm of FS
Gain = 128 ±1.5 ppm of FS
Input Offset Drift Gain = 1 0.3 μV/°C
Gain = 128 10 nV/°C
Gain Error (Note 8) Gain = 1 ±0.007 ±0.02 %
Gain = 128 ±0.02 %
Gain Drift Gain = 1 0.5 ppm/°C
Gain = 128 7 ppm/°C
ISL26132, ISL26134
6 FN6954.1
September 9, 2011
CMRR Common Mode Rejection At DC, Gain = 1, ΔV = 1V 85 100 dB
At DC, Gain = 128, ΔV = 0.1V 100 dB
50Hz/60Hz Rejection (Note 9) External 4.9152MHz Clock 130 dB
PSRR Power Supply Rejection At DC, Gain = 1, ΔV = 1V 82 100 dB
At DC, Gain = 128, ΔV = 0.1V 100 105 dB
Input Referred Noise See “Typical Characteristics” beginning
on page 8
Noise Free Bits See “Typical Characteristics” beginning
on page 8
VOLTAGE REFERENCE INPUT
VREF Voltage Reference Input VREF = VREF+ - VREF- 1.5 AVDD AVDD + 0.1 V
VREF- Negative Reference Input AGND - 0.1 VREF+ - 1.5 V
VREF+ Positive Reference Input VREF- + 1.5 AVDD + 0.1 V
IREF Voltage Reference Input Current ±350 nA
POWER SUPPLY REQUIREMENTS
AVDD Analog Supply Voltage 4.75 5.0 5.25 V
DVDD Digital Supply Voltage 2.7 3.3 5.25 V
AIDD Analog Supply Current Normal Mode, AVDD = 5, Gain = 1, 2 7 8.5 mA
Normal Mode, AVDD = 5, Gain = 64, 128 9 12 mA
Standby Mode 0.2 3 μA
Power-Down 0.2 2.5 μA
DIDD Digital Supply Current Normal Mode, AVDD = 5, Gain = 1, 2 750 950 μA
Normal Mode, AVDD = 5, Gain = 64, 128 750 950 μA
Standby Mode 1.5 26 μA
Power-Down 1 26 μA
PD Power Dissipation, Total Normal Mode, AVDD = 5, Gain = 1, 2 49.6 mW
Normal Mode, AVDD = 5, Gain = 64, 128 68 mW
Standby Mode 0.14 mW
Power-Down 0.14 mW
DIGITAL INPUTS
VIH 0.7 DVDD V
VIL 0.2 DVDD V
VOH IOH = -1mA DVDD - 0.4 V
VOL IOL = 1mA 0.2 DVDD V
Input Leakage Current ±10 μA
External Clock Input Frequency 0.3 4.9152 MHz
Serial Clock Input Frequency 1 MHz
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. FSR = Full Scale Range = VREF/Gain
8. Gain accuracy is calibrated at the factory (AVDD = +5V).
9. Specified for word rate equal to 10Sps.
Electrical Specifications VREF+ = 5V, VREF- = 0V, AVDD = 5V, DVDD = 5V, AGND = DGND = 0V, MCLK = 4.9152MHz, and
TA = -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C (Continued)
SYMBOL PARAMETER TEST LEVEL or NOTES
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ISL26132, ISL26134
7 FN6954.1
September 9, 2011
Noise Performance
The ISL26132 and ISL26134 provide excellent noise
performance. The noise performance on each of the gain
settings of the PGA at the selected word rates is shown in
Tables 5 and 6.
Resolution in bits decreases by 1-bit if the ADC is operated as a
single-ended input device. Noise measurements are
input-referred, taken with bipolar inputs under the specified
operating conditions, with fCLK = 4.9152MHz.
TABLE 5. AVDD = 5V, VREF = 5V, DATA RATE = 10Sps
GAIN
RMS NOISE
(nV)
PEAK-TO-PEAK NOISE
(nV) (Note 10)
NOISE-FREE BITS
(Note 11)
1 243 1604 21.6
2 148 977 21.3
64 10.8 71 20.1
128 10.2 67 19.1
TABLE 6. AVDD = 5V, VREF = 5V, DATA RATE = 80Sps
GAIN
RMS NOISE
(nV)
PEAK-TO-PEAK NOISE
(nV) (Note 10)
NOISE-FREE BITS
(Note 11)
1 565 3730 20.4
2 285 1880 20.3
64 28.3 187 18.7
128 27 178 17.7
NOTES:
10. The peak-to-peak noise number is 6.6 times the rms value. This
encompasses 99.99% of the noise excursions that may occur. This
value best represents the worst case noise that could occur in the
output conversion words from the converter.
11. Noise-Free Bits is defined as: Noise-Free Bits = ln(FSR/peak-to-peak
noise)/ln(2) where FSR is the full scale range of the converter,
VREF/Gain.
ISL26132, ISL26134
8 FN6954.1
September 9, 2011
Typical Characteristics
FIGURE 2. NOISE AT GAIN = 1, 10Sps FIGURE 3. NOISE HISTOGRAM AT GAIN = 1, 10Sps
FIGURE 4. NOISE AT GAIN = 2, 10Sps FIGURE 5. NOISE HISTOGRAM AT GAIN = 2, 10Sps
FIGURE 6. NOISE AT GAIN = 64, 10Sps FIGURE 7. NOISE HISTOGRAM AT GAIN = 64, 10Sps
-10
-5
0
5
10
0 200 400 600 800 1000
GAIN = 1
RATE = 10Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
50
100
150
200
250
300
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
OUTPUT CODE (LSB)
GAIN = 1, N = 1024
RATE = 10Sps
STD DEV = 1.635 LSB
VREF = 2.5V
COUNTS -
10
-5
0
5
10
0 200 400 600 800 1000
TIME (SAMPLES)
OUTPUT CODE (LSB)
GAIN = 2
RATE = 10Sps
0
50
100
150
200
250
-8 -6 -4 -2 0 2 4 6 8
GAIN = 2, N = 1024
RATE = 10Sps
STD DEV = 1.989 LSB
VREF = 2.5V
OUTPUT CODE (LSB)
COUNTS
-15
-10
-5
0
5
10
15
20
0 200 400 600 800 1000
TIME (SAMPLES)
OUTPUT CODE (LSB)
GAIN = 64
RATE = 10Sps
0
20
40
60
80
100
120
-20 -15 -10 -5 0 5 10 15 20
GAIN = 64, N = 1024
RATE = 10Sps
STD DEV = 4.627 LSB
VREF = 2.5V
OUTPUT CODE (LSB)
COUNTS
ISL26132, ISL26134
9 FN6954.1
September 9, 2011
FIGURE 8. NOISE AT GAIN = 128, 10Sps FIGURE 9. NOISE HISTOGRAM AT GAIN = 128, 10Sps
FIGURE 10. NOISE AT GAIN = 1, 80Sps FIGURE 11. NOISE HISTOGRAM AT GAIN = 1, 80Sps
FIGURE 12. NOISE AT GAIN = 2, 80Sps FIGURE 13. NOISE HISTOGRAM AT GAIN = 2, 80Sps
Typical Characteristics (Continued)
-50
-30
-10
10
30
50
0 200 400 600 800 1000
GAIN = 128
RATE = 10Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
10
20
30
40
50
60
-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30
OUTPUT CODE (LSB)
COUNTS
GAIN = 128, N = 1024
RATE = 10Sps
STD DEV = 8.757 LSB
VREF = 2.5V
-25
-20
-15
-10
-5
0
5
10
15
20
25
0 200 400 600 800 1000
GAIN = 1
RATE = 80Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
20
40
60
80
100
120
-15 -10 -5 0 5 10 15
OUTPUT CODE (LSB)
COUNTS
GAIN = 1, N = 1024
RATE = 80Sps
STD DEV = 3.791 LSB
VREF = 2.5V
-25
-15
-5
5
15
25
0 200 400 600 800 1000
GAIN = 2
RATE = 80Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
20
40
60
80
100
120
-15 -10 -5 0 5 10 15
OUTPUT CODE (LSB)
COUNTS
GAIN = 2, N = 1024
RATE = 80Sps
STD DEV = 3.831 LSB
VREF = 2.5V
ISL26132, ISL26134
10 FN6954.1
September 9, 2011
FIGURE 14. NOISE AT GAIN = 64, 80Sps FIGURE 15. NOISE HISTOGRAM AT GAIN = 64, 80Sps
FIGURE 16. NOISE AT GAIN = 128, 80Sps FIGURE 17. NOISE HISTOGRAM AT GAIN = 128, 80Sps
FIGURE 18. ANALOG CURRENT vs TEMPERATURE FIGURE 19. DIGITAL CURRENT vs TEMPERATURE
Typical Characteristics (Continued)
-100
-50
0
50
100
0 200 400 600 800 1000
GAIN = 64
RATE = 80Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
10
20
30
40
50
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40
OUTPUT CODE (LSB)
COUNTS
GAIN = 64, N = 1024
RATE = 80Sps
STD DEV = 12.15 LSB
VREF = 2.5V
-200
-160
-120
-80
-40
0
40
80
120
160
0 200 400 600 800 1000
GAIN = 128
RATE = 80Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
5
10
15
20
25
30
-80 -60 -40 -20 0 20 40 60 80
OUTPUT CODE (LSB)
COUNTS
GAIN = 128, N = 1024
RATE = 80Sps
STD DEV = 23.215 LSB
VREF = 2.5V
0
2
4
6
8
10
-40 -10 20 50 80 110
TEMPERATURE (°C)
CURRENT (mA)
NORMAL MODE, PGA = 64.128
NORMAL MODE, PGA = 1, 2
1
10
100
1000
10000
-40 -10 20 50 80 110
TEMPERATURE (°C)
CURRENT (μA)
NORMAL MODE, ALL PGA GAINS
POWERDOWN MODE
ISL26132, ISL26134
11 FN6954.1
September 9, 2011
FIGURE 20. TYPICAL WORD RATE vs TEMPERATURE USING
INTERNAL OSCILLATOR
FIGURE 21. NOISE DENSITY vs FREQUENCY AT GAIN = 1, 80Sps
FIGURE 22. NOISE DENSITY vs FREQUENCY AT GAIN = 128, 80Sps
Typical Characteristics (Continued)
9.6
9.8
10.0
10.2
10.4
10.6
10.8
11.0
-40 -10 20 50 80 110
TEMPERATURE (°C)
DATA RATE (Sps)
WORD RATE = 10Sps
10
100
1000
10000
0.01 0.1 1 10
FREQUENCY (Hz)
NOISE (nV/√Hz)
GAIN = 1, 80Sps
64k FFT
25 AVERAGES
1
10
100
0.01 0.1 1 10
FREQUENCY (Hz)
NOISE (nV/√Hz)
GAIN = 128, 80Sps
64k FFT
25 AVERAGES
ISL26132, ISL26134
12 FN6954.1
September 9, 2011
Functional Description
Analog Inputs
The analog signal inputs to the ISL26132 connect to a 2-Channel
differential multiplexer and the ISL26134 connect to a 4-Channel
differential multiplexer (Mux). The multiplexer connects a pair of
inputs to the positive and negative inputs (AINx+, AINx-), selected
by the Channel Select Pins A0 and A1 (ISL26134 only). Input
channel selection is shown in Table 7. On the ISL26132, the
TEMP pin is used to select the Temperature Sensor function.
Whenever the MUX channel is changed (i.e. if any one of the
following inputs - A0/A1, Gain1/0, SPEED is changed), the
digital logic will automatically restart the digital filter and will
cause SDO/RDY to go low only when the output is fully settled.
But if the input itself is suddenly changed, then the user needs to
ignore first four RDY pulses (going low) to get an accurate
measurement of the input signal.
The input span of the ADC is ±0.5 VREF/GAIN. For a 5V VREF and
a gain of 1x, the input span will be 5VP-P fully differential as
shown in Figure 23. Note that input voltages that exceed the
supply rails by more than 100mV will turn on the ESD protection
diodes and degrade measurement accuracy.
If the differential input exceeds well above the +VE or the -VE FS
(by ~1.5x times) the output code will clip to the corresponding FS
value. Under such conditions, the output data rate will become
1/4th of the original value as the Digital State Machine will
RESET the Delta-Sigma Modulator and the Decimation Filter.
Temperature Sensor (ISL26132 only)
When the TEMP pin of the ISL26132 is set High, the input
multiplexer is connected to a pair of diodes, which are scaled in
both size and current. The voltage difference measured between
them corresponds to the temperature of the die according to
Equation 1:
Note: Valid only for GAIN = 1x or 2x
Where T is the temperature of the die, and Gain = the PGA Gain
Setting.
At a temperature of +25°C, the measured voltage will be
approximately 111.7mV. Note that this measurement indicates
only the temperature of the die itself. Applying the result to
correct for the temperature drift of a device external to the
package requires that thermal coupling between the sensor and
the die be taken into account.
Low-Noise Programmable Gain Amplifier
(PGA)
The chopper-stabilized programmable gain amplifier features a
variety of gain settings to achieve maximum dynamic range and
measurement accuracy from popular sensor types with excellent
low noise performance, input offset error, and low drift, and with
minimal external parts count. The GAIN0 and GAIN1 pins allow the
user to select gain settings of 1x, 2x, 64x, or 128x. A block diagram
is shown in Figure 24. The differential input stage provides a gain of
64, which is bypassed when the lower gain settings are selected.
The lower gain settings (1 and 2) will accept inputs with common
mode voltages up to 100mV outside the rails, allowing the device to
accept ground-referred signals. At gain settings of 64 or 128 the
common mode voltage at the inputs is limited to 1.5V inside the
supply rails while maintaining specified measurement accuracy.
TABLE 7. INPUT CHANNEL SELECTION
CHANNEL SELECT PINS ANALOG INPUT PINS SELECTED
A1 A0 AIN+ AIN-
0 0 AIN1+ AIN1-
0 1 AIN2+ AIN2-
1 0 AIN3+ AIN3-
1 1 AIN4+ AIN4-
3.75
2.50
1.25
1.25V
INPUT VOLTAGE RANGE = ±0.5VREF/GAIN
VREF = 5V, GAIN = 1X
3.75
2.50
1.25
AIN+
AIN-
2.50V
FIGURE 23. DIFFERENTIAL INPUT FOR VREF = 5V, GAIN = 1X
V= 102.2mV + (379μV∗T(°C))∗Gain
(EQ. 1)
ISL26132, ISL26134
13 FN6954.1
September 9, 2011
Filtering PGA Output Noise
The programmable gain amplifier, as shown in Figure 24,
includes a passive RC filter on its output. The resistors are
located inside the chip on the outputs of the differential amplifier
stages. The capacitor (nominally a 100nF C0G ceramic or a PPS
film (Polyphenylene sulfide)) for the filter is connected to the two
CAP pins of the chip. The outputs of the differential amplifier
stages of the PGA are filtered before their signals are presented
to the delta-sigma modulator. This filter reduces the amount of
noise by limiting the signal bandwidth and filters the chopping
artifacts of the chopped PGA stage.
Voltage Reference Inputs (VREF+, VREF-)
The voltage reference for the ADC is derived from the difference
in the voltages presented to the VREF+ and VREF- pins;
VREF = (VREF+ - VREF-). The ADCs are specified with a voltage
reference value of 5V, but a voltage reference as low as 1.5V can
be used. For proper operation, the voltage on the VREF+ pin
should not be greater than AVDD + 0.1V and the voltage on the
VREF- pin should not be more negative than AGND - 0.1V.
Clock Sources
The ISL26132, ISL26134 can operate from an internal oscillator,
an external clock source, or from a crystal connected between
the XTALIN/CLOCK and XTALOUT pins. See the block diagram of
the clock system in Figure 25. When the ADC is powered up, the
CLOCK DETECT block determines if an external clock source is
present. If a clock greater than 300kHz is present on the
XTALIN/CLOCK pin, the circuitry will disable the internal oscillator
on the chip and use the external clock as the clock to drive the
chip circuitry. If the ADC is to be operated from the internal
oscillator, the XTALIN/CLOCK pin should be grounded.
If the ADC is to be operated from a crystal, it should be located
close to the package pins of the ADC. Note that external loading
capacitors for the crystal are not required as there are loading
capacitors built into the silicon, although the capacitor values are
optimized for operation with a 4.9152MHz crystal.
The XTALOUT pin is not intended to drive external circuits.
Digital Filter Characteristics
The digital filter inside the ADC is a fourth-order Siinc filter.
Figures 26 and 27 illustrate the filter response for the ADC when
it is operated from a 4.9152MHz crystal. The internal oscillator is
factory trimmed so the frequency response for the filter will be
much the same when using the internal oscillator. The figures
illustrate that when the converter is operated at 10Sps the digital
filter provides excellent rejection of 50Hz and 60Hz line
interference.
FIGURE 24. SIMPLIFIED PROGRAMMABLE GAIN AMPLIFIER BLOCK DIAGRAM
+
-
A1
-
+
A2
AINx-
AINx+
ADC
RINT
RINT
R1
RF1
RF2
CAP
CAP
FIGURE 25. CLOCK BLOCK DIAGRAM
XTALIN/
CRYSTAL
OSCILLATOR
XTALOUT
TO ADC
INTERNAL
OSCILLATOR
CLOCK DETECT
MUX
EN
CLOCK
ISL26132, ISL26134
14 FN6954.1
September 9, 2011
Serial Clock Input (SCLK)
The serial clock input is provided with hysteresis to minimize
false triggering. Nevertheless, care should be taken to ensure
reliable clocking.
Filter Settling Time and ADC Latency
Whenever the analog signal into the ISL26132, ISL26134
converters is changed, the effects of the digital filter must be
taken into account. The filter takes four data ready periods for
the output code to fully reflect a new value at the analog input. DM
the multiplexer control input is changed, the modulator and the
digital filter are reset, and the device uses four data ready
periods to fully settle to yield a digital code that accurately
represents the analog input. Therefore, from the time the control
inputs for the multiplexer are changed until the SDO/RDY goes
low, four data ready periods will elapse. The settling time delay
after a multiplexer channel change is listed in Table 8 for the
converter operating in continuous conversion mode.
0
-50
-100
-150
0 10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz)
GAIN (dB)
DDAATTAA RRAATTEE == 1100 SSpPsS
FIGURE 26. 10Sps: FREQUENCY RESPONSE OUT TO 100Hz
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
45 50 55 60 65
FREQUENCY (Hz)
GAIN (dB)
DATA RATE = 10Sps
FIGURE 27. 10Sps: 50/60Hz NOISE REJECTION, 45Hz TO 65Hz
TABLE 8. SETTLING TIME
PARAMETER
DESCRIPTION
(fCLK = 4.9152MHz) MIN MAX UNITS
tS A0, A1, SPEED, Gain1, Gain0 change
set-up time
40 50 μs
t1 Settling time SPEED = 1 54 55 ms
SPEED = 0 404 405 ms
FIGURE 28. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
SDO/RDY
tS
t1
A0, A1, SPEED, Gain1, Gain0
ISL26132, ISL26134
15 FN6954.1
September 9, 2011
Conversion Data Rate
The SPEED pin is used to select between the 10Sps and 80Sps
conversion rates. The 10Sps rate (SPEED = Low) is preferred in
applications requiring 50/60Hz noise rejection. Note that the
sample rate is directly related to the oscillator frequency, as
491,520 clocks are required to perform a conversion at the
10Sps rate, and 61,440 clocks at the 80Sps rate.
Output Data Format
The 24-bit converter output word is delivered in two’s
complement format. Input exceeding full scale results in a
clipped output which will not return to in-range values until after
the input signal has returned to the specified allowable voltage
range and the digital filter has settled as discussed previously.
Reading Conversion Data from the Serial
Data Output/Ready SDO/RDY Pin
When the ADC is powered, it will automatically begin doing
conversions. The SDO/RDY signal will go low to indicate the
completion of a conversion. After the SDO/RDY signal goes low,
the MSB data bit of the conversion word will be output from the
SDO/RDY pin after SCLK is transitioned from a low to a high.
Each subsequent new data bit is also output on the rising edge of
SCLK (see Figure 30). The receiving device should use the falling
edge of SCLK to latch the data bits. After the 24th SCLK, the
SDO/RDY output will remain in the state of the LSB data bit until
a new conversion is completed. At this time, the SDO/RDY will go
high if low and then go low to indicate that a new conversion
word is available. If not all data bits are read from the SDO/RDY
pin prior to the completion of a new conversion, they will be
overwritten. SCLK should be low during time t6, as shown in
Figure 30, when SDO/RDY is high.
If the user wants the SDO/RDY signal to go high after reading the
24 bits of the conversion data word, a 25th SCLK can be issued.
The 25th SCLK will force the SDO/RDY signal to go high and
remain high until it falls to signal that a new conversion word is
available. Figure 31 illustrates the behavior of the SDO/RDY
signal when a 25th SCLK is used.
FIGURE 29. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
SDO/RDY
TABLE 9. OUTPUT CODES CORRESPONDING TO INPUT
INPUT SIGNAL OUTPUT CODE (HEX)
≥ + 0.5VREF/GAIN 7FFFFF
(+0.5VREF/GAIN)/(223 - 1) 000001
0 000000
(-0.5VREF/GAIN)/(223 - 1) FFFFFF
≤ - 0.5VREF/GAIN 800000
FIGURE 30. OUTPUT DATA WAVEFORMS USING 24 SCLKS TO READ CONVERSION DATA
SDO/RDY
DATA READY
DATA
MSB LSB
NEW DATA READY
23 22 21 0
SCLK
t4
t2
1
t3
24
t5
t6
t3
t7
ISL26132, ISL26134
16 FN6954.1
September 9, 2011
Offset Calibration Control
The offset internal to the ADC can be removed by performing an
offset calibration operation. Offset calibration can be initiated
immediately after reading a conversion word with 24 SCLKs by
issuing two additional SCLKs. The offset calibration operation will
begin immediately after the 26th SCLK occurs. Figure 32
illustrates the timing details for the offset calibration operation.
During offset calibration, the analog inputs are shorted internally
and a regular conversion is performed. This conversion generates
a conversion word that represents the offset error. This value is
stored and used to digitally remove the offset error from future
conversion words. The SDO/RDY output will fall to indicate the
completion of the offset calibration operation.
TABLE 10. INTERFACE TIMING CHARACTERISTICS
PARAMETER DESCRIPTION MIN TYP MAX UNITS
t2 SDO/RDY Low to first SLK 0 ns
t3 SCLK pulsewidth, Low or High 100 ns
t4 SCLK High to Data Valid 50 ns
t5 Data Hold after SCLK High 0 ns
t6 Register Update Time 39 μs
t7 Conversion Period SPEED = 1 12.5 ms
SPEED = 0 100 ms
FIGURE 31. OUTPUT DATA WAVEFORMS FOR SDO/RDY POLLING
DATA READY NEW DATA READY
SDO/RDY
SCLK
23 22 21 0
1 24 25
DATA
25TH SCLK FORCES
SDO/RDY HIGH
FIGURE 32. OFFSET CALIBRATION WAVEFORMS
DATA READY AFTER CALIBRATION
CALIBRATION BEGINS
SDO/RDY
SCLK
23 22 21 0 23
1 24 25 26
t8
FIGURE 33. STANDBY MODE WAVEFORMS
DATA READY
START
CONVERSION
STANDBY MODE
SDO/RDY
SCLK
23 22 21 0
1 24
t10 t11
t9
23
TABLE 11. SDO/RDY DELAY AFTER CALIBRATION
PARAMETER MIN MAX UNITS
t8 SPEED = 1 108 109 ms
SPEED = 0 808 809 ms
ISL26132, ISL26134
17 FN6954.1
September 9, 2011
Standby Mode Operation
The ADC can be put into standby mode to save power. Standby
mode reduces the power to all circuits in the device except the
crystal oscillator amplifier. To enter the standby mode, take the
SCLK signal high and hold it high after SDO/RDY falls. la
converter will remain in standby mode as long as SCLK is held
high. To return to normal operation, take SCLK back low and wait
for the SDO/RDY to fall to indicate that a new conversion has
completed. Figure 33 and Table 12 illustrate the details of
standby mode.
Supply currents are equal in Standby and Power-down modes
unless a Crystal is used. If the Crystal is used, the Crystal
amplifier is turned ON, even in the standby mode.
Performing Offset Calibration After Standby
mode
To perform an offset calibration automatically upon returning
from standby, deliver 2 or more additional SCLKs following a
data read cycle, and then set and hold SCLK high. The device will
remain in Standby as long as SCLK remains high. A calibration
cycle will begin once SCLK is brought low again to resume
normal operation. Additional time will be required to perform the
calibration after returning from Standby. Figure 34 and Table 13
illustrate the details of performing offset calibration after
standby mode.
TABLE 12. STANDBY MODE TIMING
PARAMETER DESCRIPTION MIN MAX UNITS
t9 SCLK High after
SDO/RDY Low
SPEED = 1 0 12.44 ms
SPEED = 0 0 99.94
t10 Standby Mode Delay SPEED = 1 12.5
SPEED = 0 100
t11 SDO/RDY falling edge
after SCLK Low
SPEED = 1 50 60
SPEED = 0 400 410
TABLE 13. OFFSET CALIBRATION TIMING AFTER STANDY
PARAMETER DESCRIPTION MIN MAX UNITS
t12 SDO/RDY Low after
SCLK Low
SPEED = 1 108 113 ms
SPEED = 0 808 813 ms
FIGURE 34. OFFSET CALIBRATION WAVEFORMS AFTER STANDBY
SDO/RDY
SCLK
23 22 21 0
1 24 25
STANDBY MODE DATA READY AFTER CALIBRATION
BEGIN 23
CALIBRATION
t10 t12
ISL26132, ISL26134
18 FN6954.1
September 9, 2011
Operation of PDWN
PDWN must transition from low to high after both power supplies
have settled to specified levels in order to initiate a correct
power-up reset (Figure 35). This can be implemented by an
external controller or a simple RC delay circuit, as shown in
Figure 36.
In order to reduce power consumption, the user can assert the
Power-down mode by bringing PDWN Low as shown in Figure 37.
All circuitry is shut down in this mode, including the Crystal
Oscillator. After PDWN is brought High to resume operation, the
reset delay varies depending on the clock source used. While an
external clock source will resume operation immediately, a
circuit utilizing a crystal will incur about a 20 millisecond delay
due to the inherent start-up time of this type of oscillator.
FIGURE 35. POWER-DOWN TIMING RELATIVE TO SUPPLIES
≥10μs
AVDD
DVDD
PDWN
FIGURE 36. PDWNDELAY CIRCUIT
DVDD
1kΩ
2.2nF
CONNECT TO
PDWN PIN
FIGURE 37. POWER-DOWN MODE WAVEFORMS
SDO/RDY
SCLK
t11
PDWN
POWER-DOWN
MODE
START
CONVERSION
DATA
CLK READY
SOURCE
WAKEUP
t13
tt1144
TABLE 14. POWER-DOWN RECOVERY TIMING
PARAMETER DESCRIPTION TYP UNITS
t13 Clock Recovery after PDWN
High
Internal Oscillator 7.95 μs
External Clock Source 0.16 μs
4.9152MHz Crystal
Oscillator
5.6 ms
t14 PDWN Pulse Duration 26 μs (min)
ISL26132, ISL26134
19 FN6954.1
September 9, 2011
Applications Information
Power-up Sequence – Initialization and
Configuration
The sequence to properly power-up and initialize the device are
as follows. For details on individual functions, refer to their
descriptions.
1. AVDD, DVDD ramp to specified levels
2. Apply External Clock
3. Pull PDWN High to initiate Reset
4. Device begins conversion
5. SDO/RDY goes low at end of first conversion
OPTIONAL ACTIONS
• Perform Offset Calibration
• Place device in Standby
• Return device from Standby
• Read on-chip Temperature (applicable to ISL26132 only)
Application Examples
WEIGH SCALE SYSTEM
Figure 38 illustrates the ISL26132 connected to a load cell. la
A/D converter is configured for a gain of 128x and a sample rate
of 10Sps. If a load cell with 2mV/V sensitivity is used, the full
scale output from the load cell will be 10mV. On a gain of 128x
and sample rate of 10Sps, the converter noise is 67nVP-P. la
converter will achieve 10mV/67nVP-P = 149,250 noise free
counts across its 10mV input signal. This equates to 14,925
counts per mV of input signal. If five output words are averaged
together this can be improved by √5 to yield √5*14925
counts = 33,370 counts per mV of input signal with an effective
update rate of 2 readings per second.
THERMOCOUPLE MEASUREMENT
Figure 39 illustrates the ISL26132 in a thermocouple
application. As shown, the 4.096V reference combined with the
PGA gain set to 128x sets the input span of the converter to
±16mV. This supports the K type thermocouple measurement for
temperatures from -270°C at -6.485mV to +380°C at about
16mV.
If a higher temperature is preferred, the PGA can be set to 64x to
provide a converter span of ±32mV. The will allow the converter
to support temperature measurement with the K type
thermocouple up to about +765°C.
In the circuit shown, the thermocouple is referenced to a voltage
dictated by the resistor divider from the +5V supply to ground.
These set the common mode voltage at about 2.5V. The 5M
resistors provide a means for detection of an open thermocouple.
If the thermocouple fails open or is not connected, the bias
through the 5M resistors will cause the input to the PGA to go to
full scale.
AVDD
VREF+
CAP
CAP
AIN+1
AIN-1
AIN+2
AIN-2
VREFAGND
DGND
TEMP
A0
SPEED
XTALOUT
PDWN
SCLK
SDO/RDY
GAIN0
GAIN1
DVDD
ISL26132
XTALIN/CLOCK
- +
0.1μF
VDD
MICRO
CONTROLLER
GND
16
9
10
11
12
14
13
15
17 2, 5, 6
7
8
21
3
4
22
23
24
19
20
GAIN = 128
5V 3V
0.1μF 18 1
FIGURE 38. WEIGH SCALE APPLICATION
ISL26132, ISL26134
20 FN6954.1
September 9, 2011
PCB Board Layout and System
Configuration
The ISL26132,ISL26134 ADC is a very low noise converter. taux
achieve the full performance available from the device will
require attention to the printed circuit layout of the circuit board.
Care should be taken to have a full ground plane without
impairments (traces running through it) directly under the chip
on the back side of the circuit board. The analog input signals
should be laid down adjacent (AIN+ and AIN- for each channel) to
achieve good differential signal practice and routed away from
any traces carrying active digital signals. The connections from
the CAP pins to the off-chip filter capacitor should be short, and
without any digital signals nearby. The crystal, if used should be
connected with relatively short leads. No active digital signals
should be routed near or under the crystal case or near the
traces, which connect it to the ADC. The AGND and DGND pins of
the ADC should be connected to a common solid ground plane.
All digital signals to the chip should be powered from the same
supply, as that used for DVDD (do not allow digital signals to be
active high unless the DVDD supply to the chip is alive). Route all
active digital signals in a way to keep distance from any analog
pin on the device (AIN, VREF, CAP, AVDD). Power on the AVDD
supply should be active before the VREF voltage is present.
PCB layout patterns for the chips (ISL26132 and ISL26134) are
found on the respective package outline drawings on pages 22,
and 23.
AVDD
VREF+
AIN+1
AIN-1
AIN+2
AIN-2
VREFAGND
DGND
TEMP
A0
SPEED
XTALOUT
PDWN
SCLK
SDO/RDY
GAIN0
GAIN1
DVDD
XTALIN/CLOCK
MICRO
CONTROLLER
16
11
12
14
13
15
17 2, 5, 6
7
8
21
3
4
22
23
24
19
20
+5V +3V
0.1μF
18 1
FIGURE 39. THERMOCOUPLE MEASUREMENT APPLICATION
4.9152
MHz
ISL21009
4.096V
10nF
1μF
10k
10k
0.1μF
TYPE K
5M
5M
ISL26132, ISL26134
21
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6954.1
September 9, 2011
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE REVISION CHANGE
09/08/11 FN6954.1 Power Supply Requirements on page 6 - AIDD - Analog Supply Current - Normal Mode, AVDD = 5, Gain = 1,2
changed TYP and MAX from “6, 7.3” to “7, 8.5”
Power Dissipation, Total Normal Mode, AVDD = 5, Gain = 1, 2 changed from “43.3” to “49.6” mW (Max)
08/22/11 FN6954.0 Initial Release.
ISL26132, ISL26134
22 FN6954.1
September 9, 2011
Package Outline Drawing
M24.173
24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
Une.
NOTES:
7.
5
SEATING PLANE
C
H
2 3
1
24
B
12
1 3
13
A
PLANE
GAUGE
0.05 MIN
0.15 MAX
0°-8°
0.60± 0.15
0.90
1.00 REF
0.25
SEE DETAIL "X"
0.15
0.25
(0.65 TYP)
(5.65)
(0.35 TYP)
(1.45)
6.40
4.40 ±0.10
0.65
1.20 MAX
PIN #1
I.D. MARK
7.80 ±0.10
+0.05
-0.06
-0.06
+0.05
-0.10
+0.15
0.20 C B A
0.10 C
- 0.05
0.10 M C B A
ISL26132, ISL26134
23 FN6954.1
September 9, 2011
Package Outline Drawing
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
Une.
NOTES:
7.
5
SEATING PLANE
C
H
2 3
1
28
B
14
1 3
15
A
PLANE
GAUGE
0.05 MIN
0.15 MAX
0°-8°
0.60 ±0.15
0.90
1.00 REF
0.25
SEE DETAIL "X"
0.25
(0.65 TYP)
(5.65)
(0.35 TYP)
(1.45)
6.40
4.40 ± 0.10
0.65
1.20 MAX
PIN #1
I.D. MARK
9.70± 0.10
-0.06
0.15 +0.05
-0.10
+0.15
-0.06
+0.05
0.20 C B A
0.10 C
- 0.05
0.10 M C B A
Both, the Deltabell® E and Plus feature engineer friendly features such as the unique levelling mechanism and
modular components that make simple sounder installations a reality.
Both external sounders incorporate the same features that are described overleaf. However, the Deltabell® Plus
has a fully back-light option, which enables around the clock visual deterrent to maximise your security.
The Deltabell® E and Plus are available in a variety of different colours:
Low power external sounder with strobe
Low power external sounder with strobe and back-light
Available Base Colours: Red,
Green, White, Amber, Blue and Black
Available Lid Colours: Red, White,
Yellow, Black*, Blue* and Chrome*
*Not recommended for Deltabell® Plus
2012 Pyronix Ltd. Pyronix, the Pyronix Blades device, Deltabell are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change. Other cover colour
options available. White cover recommended for use with backlit Deltabell PLUS for optimum visual clarity.
RMKT090001-7
© 2009 Pyronix Ltd. Pyronix and the Pyronix Blades device are trademarks of Pyronix Ltd.
As part of our continued development programme specifications of the V2 TEL and V2 GSM may change.
RMKT090057-1
© 2009 Pyronix Ltd. Pyronix, the Pyronix Blades device, TMD15 and TriCover are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change.
RMKT080064-4
© 2009 Pyronix Ltd. Pyronix, the Pyronix Blades device, TMD15 and TriCover are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change.
RMKT090057-1
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
2010 Pyronix Ltd. Pyronix, the Pyronix Blades device, Deltabell are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change. Other cover colour
options available. White cover recommended for use with backlit Deltabell PLUS for optimum visual clarity.
RMKT090150
www.pyronix.com
marketing@pyronix.com
01709 700100Current consumption feature Deltabell® Plus only
The Deltabell® incorporates a LDR (Light Dependant Resistor)
circuit which turns the Light off during daylight hours when it is
not needed, saving on the product current consumption.
When the day turns from dusk to dark the Lightbox illuminates
so that your external visual deterrent can be seen on the
darkest of nights.
Visual alarm warning feature Deltabell® Plus only
In addition to the strobe which is present on all of the Deltabell®
models, the Deltabell® PLUS has the added feature that the
illuminated cover will strobe when the alarm is activated, giving
you the added peace of mind that your alarm will be seen in
‘alarm mode’ from a much greater distance than standard
sounders that do not have back lighting facilities.
Security and peace of mind
The Deltabell® has front and rear tamper protection and in the
event of a potential sabotage attack, the 104dBA sounder
provides a distinctive audible warning.
The electronic elements on the printed circuit board are
protected by a fully sealed unit with a rubber gasket providing
added protection in harsh environments and giving your
customer peace of mind that the Deltabell® will always sound
in the event of an alarm activation.
104 dBA sounder
Piezo sounder with high decibel output.
Engineer hold-off facility
The Deltabell® engineer hold-off facility means that when
initially powered with the tamper switch open, the sounder will
not activate.
Remote engineer hold-off facility
There is also the capability for remote engineer hold-off which
is invaluable when you are servicing the system enabling easy
maintenance. It can be turned on at any time by applying 0V
to this dedicated terminal which will then disable the tamper.
Unique levelling mechanism
A spirit level is supplied so that you can easily mount the
Deltabell®. In addition, to make the installation as simple as
possible, revolving guide holes are used to save time lining up
screw and drill holes.
SCB/SAB Mode
Self Contained Bell or Self Activating Bell mode.
Hinged cover The Deltabell® has a hinged cover that locks into place so that
both your hands are free to work on the sounder.
Fully back-lit cover
The Deltabell® low power modular unit back-lights the cover
(Deltabell® Plus only)
Electrical specification
Operating Voltage
Supply: 9-16 V DC (13.5 nominal)
Protected: Reverse polarity protected
Current Consumption
Quiescent Current: < 60 mA
Alarm Current: < 300 mA
Strobe
Strobe Duration: 100 ms
Strobe Frequency: 1Hz
Dimensions
[W] 290 mm
[H] 285 mm
[D] 50 mm
Compliance
Europe.
Suitable for use in
EN50131-1 systems
Security grade 2 or 3,
Environmental class IV
[H]
[W] [D]
Packing information
Minimum quantity: 10
Minimum order for
screen print: 40
Warranty: 2 years
Designed: UK
Dummy bases also available
2012 Pyronix Ltd. Pyronix, the Pyronix Blades device, Deltabell are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change. Other cover colour
options available. White cover recommended for use with backlit Deltabell PLUS for optimum visual clarity.
RMKT090001-7
© 2009 Pyronix Ltd. Pyronix and the Pyronix Blades device are trademarks of Pyronix Ltd.
As part of our continued development programme specifications of the V2 TEL and V2 GSM may change.
RMKT090057-1
© 2009 Pyronix Ltd. Pyronix, the Pyronix Blades device, TMD15 and TriCover are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change.
RMKT080064-4
© 2009 Pyronix Ltd. Pyronix, the Pyronix Blades device, TMD15 and TriCover are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change.
RMKT090057-1
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
2010 Pyronix Ltd. Pyronix, the Pyronix Blades device, Deltabell are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change. Other cover colour
options available. White cover recommended for use with backlit Deltabell PLUS for optimum visual clarity.
RMKT090150
www.pyronix.com
marketing@pyronix.com
01709 700100
Serial File Transfer Cables
The cables feature either the traditional 25 D type RS232 connector or the now more commonly fitted 9 D type
serial connector. As the serial port on most PCs is a plug or male the most common interface cable tends to be
a socket to socket (female to female).
Caractéristiques:
• Multi-headed cable allows either 9 D or 25 D connection - providing complete serial port flexibility
• Both serial port configurations (Pt Nos 4070 & 4062) available from stock
• High quality moulded cables manufactured using foil screened cable
• Custom lengths can be made up upon request
• Now recognised as conforming to the most standard file transfer wiring configuration
4070
Stock No Description
PC AT to PC AT
4070 DB9F to DB9F Null Modem Cable 2Mtr
4070-3 DB9F to DB9F Null Modem Cable 3Mtr
4070-5 DB9F to DB9F Null Modem Cable 5Mtr
4070-10 DB9F to DB9F Null Modem Cable 10Mtr
4070-15 DB9F to DB9F Null Modem Cable 15Mtr
PC XT to PC XT
4062 DB25F to DB25F Null Modem Cable 2Mtr
4062-3 DB25F to DB25F Null Modem Cable 3Mtr
4062-5 DB25F to DB25F Null Modem Cable 5Mtr
4062-10 DB25F to DB25F Null Modem Cable 10Mtr
PC XT to PC AT
4063 DB9F to DB25F Null Modem Cable 2Mtr
4063-3 9DS TO 25DS NULL MODEM 3M
4063-5 9DS TO 25DS NULL MODEM 5M
4063-10 9DS TO 25DS NULL MODEM 10M
Multi-head Serial Cables
4090 DB9F+DB25F to DB9F+DB25F Null Modem Cable 2Mtr
4090-3 DB9F+DB25F to DB9F+DB25F Null Modem Cable 3Mtr
4090-5 DB9F+DB25F to DB9F+DB25F Null Modem Cable 5Mtr
Amplifier
Internet Radio
Terrestrial Tuner
Features
Feature Description
vols
Sources
6 – Internet Radio, MP3, CD, Terrestrial Radio,
Auxiliary Input.
Portable
Yes, two part system. The Internet Radio is
completely portable receiving all data and audio
over a wireless link from the transmitter part
connected to the PC USB port.
LCD
Display
20 character 5 x 7 dot matrix display with icons,
EL blue backlight.
Power
Source
8 x C size 1.5 volt alkaline battery or AC mains –
220 - 240 volt Europe, 110 volt US.
Operation
Time
Approx 30 hours continuous play at mid volume
on one set of alkaline batteries.
Feature Description
Output Power (RMS) 2 x 2.2 watts
Total Power 4.4 watts
Music Power 2 x 4.4 watts
PMPO 65 watts
Feature Description
Radio presets 6 with station name display
Feature Description
Digital Tuner bands FM Stereo
Tuner presets 6 for each band
Antenna FM YesLoudspeaker
Connections
Wireless Link
Dimensions
Frequency Display Yes, 4 digit
Feature Description
No. of way speaker system 1 – way full range driver
Impedance 2 x 8 ohm
Rated Power (RMS) 2 x 6 watts
Size 67 mm x 106 mm, Elliptical
Magnetic Shielding Yes
Feature Description
stéréo
headphone Yes
Auxiliary Input Yes, 2 x phono socket
Auxiliary
Output Yes, 2 x phono socket
USB connection Yes, transmitter connects to PC USB port
with 1.5 metre cable
Feature Description
Stereo Audio
Channel
Europe 863 MHz 10 mW erp, USA 925 MHz 10
mW erp, user selectable band switching to
avoid interference.
Data
Channel
Europe + USA, 433 MHz , bi-directional, user
selectable band switching to avoid interference.
Feature Description
Radio Remote
Module
Front to Back 155mm (6.1"), Side to Side
283mm (11.1"), Height 150mm (5.9")
USB Base
Module
Front to Back 120mm (4.7"), Side to Side
135mm (5.3"), Height 41mm (1.6")
1 / 5
Date de révision November 2011
Révision 3
No FDS 16447
FICHE DE DONNEES DE SECURITE
ARALDITE FUSION HARDENER
SECTION 1: IDENTIFICATION DE LA SUBSTANCE/DU MÉLANGE ET DE LA SOCIÉTÉ/L’ENTREPRISE
1.1. Identificateur de produit
Nom commercial ARALDITE FUSION HARDENER
No du produit 808300, 808409, 808416, 808423
1.2. Utilisations identifiées pertinentes de la substance ou du mélange et utilisations déconseillées
1.3. Renseignements concernant le fournisseur de la fiche de données de sécurité
Distributeur BOSTIK LIMITED
COMMON ROAD
STAFFORD
STAFFORDSHIRE
ST16 3EH
UNITED KINGDOM
+44 1785 255141
+44 1785 272650 (24Hour Emergency)
sds.uk@bostik.com
1.4. Numéro d’appel d’urgence
SECTION 2: IDENTIFICATION DES DANGERS
2.1. Classification de la substance ou du mélange
Classification (1999/45/CEE) Xi;R36/38.
2.2. Éléments d’étiquetage
Étiquetage
Irritant
Phrases De Risque
R36/38 Irritant pour les yeux et la peau.
Conseils De Prudence
S2 Conserver hors de la portée des enfants.
S24/25 Éviter le contact avec la peau et les yeux.
S26 En cas de contact avec les yeux, laver immédiatement et abondamment
avec de l'eau et consulter un spécialiste.
S36/37/39 Porter un vêtement de protection approprié, des gants et un appareil de
protection des yeux/ du visage.
S46 En cas d'ingestion, consulter immédiatement un médecin et lui montrer
l'emballage ou l'étiquette.
S56 Éliminer ce produit et son récipient dans un centre de collecte des déchets
dangereux ou spéciaux.
2.3. Autres dangers
SECTION 3: COMPOSITION/INFORMATIONS SUR LES COMPOSANTS
3.2. Mélanges
2 / 5
No FDS 16447
ARALDITE FUSION HARDENER
1,8-DIAZABICYCLO[5.4.0]UNDEC-7-ENE 1-5%
No CAS : 6674-22-2 No CE : 229-713-7
Classification (67/548/CEE)
Xn;R22.
C;R34.
R52/53.
Classification (CE 1272/2008)
Non classé.
BIS(2-DIMETHYLAMINOETHYL)ETHER 1-5%
No CAS : 3033-62-3 No CE : 221-220-5
Classification (67/548/CEE)
T;R23/24.
Xn;R22.
C;R35.
Classification (CE 1272/2008)
Non classé.
TRIETHYLENETETRAMINE, PROPOXYLATED 5-10%
No CAS : 26950-63-0 No CE : 500-055-5
Classification (67/548/CEE)
Xi;R38,R41.
Classification (CE 1272/2008)
Non classé.
L'intégralité du texte des phrases de risque et des mentions de danger figure à la Section 16.
SECTION 4: PREMIERS SECOURS
4.1. Description des premiers secours
Inhalation
Éloigner immédiatement la victime de la source d'exposition. Emmener immédiatement à l'air frais la personne exposée. Consulter un
médecin.
Ingestion
NE PAS faire vomir. Consulter immédiatement un médecin.
Contact avec la peau
Rincer rapidement la peau contaminée avec du savon ou un détergent doux et de l'eau. Enlever rapidement les vêtements imbibés et les
laver comme indiqué ci-dessus. Consulter un médecin si l'irritation persiste après le lavage.
Contact avec les yeux
Rincer immédiatement les yeux avec de l'eau. Continuer à rincer pendant au moins 15 minutes et consulter un médecin.
4.2. Principaux symptômes et effets, aigus et différés
4.3. Indication des éventuels soins médicaux immédiats et traitements particuliers nécessaires
SECTION 5: MESURES DE LUTTE CONTRE L’INCENDIE
5.1. Moyens d’extinction
Moyens d'extinction
Ce produit est ininflammable. Choisir le moyen d'extinction d'incendie en tenant compte d'autres produits chimiques éventuels. Utiliser :
Mousse, dioxyde de carbone ou poudre sèche.
5.2. Dangers particuliers résultant de la substance ou du mélange
5.3. Conseils aux pompiers
SECTION 6: MESURES À PRENDRE EN CAS DE DISPERSION ACCIDENTELLE
6.1. Précautions individuelles, équipement de protection et procédures d’urgence
6.2. Précautions pour la protection de l’environnement
3 / 5
No FDS 16447
ARALDITE FUSION HARDENER
6.3. Méthodes et matériel de confinement et de nettoyage
Absorber avec de la vermiculite, du sable sec ou de la terre, puis placer en récipient.
6.4. Référence à d’autres sections
SECTION 7: MANIPULATION ET STOCKAGE
7.1. Précautions à prendre pour une manipulation sans danger
Faire très attention de ne pas renverser la matière et éviter du contact avec la peau et les yeux.
7.2. Conditions d’un stockage sûr, y compris d’éventuelles incompatibilités
Entreposer à une température modérée dans un endroit sec et bien aéré.
7.3. Utilisation(s) finale(s) particulière(s)
SECTION 8: CONTRÔLES DE L’EXPOSITION/PROTECTION INDIVIDUELLE
8.1. Paramètres de contrôle
Description Des Ingrédients
WEL = Workplace Exposure Limits
8.2. Contrôles de l’exposition
Équipements de protection
Mesures d'ingénierie
Assurer une ventilation efficace.
Protection respiratoire
Si la ventilation est insuffisante, une protection respiratoire appropriée doit être disponible.
Protection des mains
Porter des gants de protection en cas de risque de contact direct ou d'éclaboussures.
Protection des yeux
Porter des lunettes de sécurité lunettes anti-éclaboussures pour éviter tout contact avec les yeux.
Mesures d'hygiène
Se laver rapidement en cas de contamination de la peau. Se laver après le travail et avant de manger, de fumer et avant d'aller aux
toilettes.
SECTION 9: PROPRIÉTÉS PHYSIQUES ET CHIMIQUES
9.1. Informations sur les propriétés physiques et chimiques essentielles
Aspect Liquide
Couleur Clair (ou pâle). Jaune.
Odeur Odeur faible.
Solubilité Insoluble dans l'eau
Densité relative 1.14
Point d'éclair (°C) 145 Creuset fermé Pensky-Martens.
9.2. Autres informations
SECTION 10: STABILITÉ ET RÉACTIVITÉ
10.1. Réactivité
10.2. Stabilité chimique
Stable aux températures normales.
10.3. Possibilité de réactions dangereuses
10.4. Conditions à éviter
4 / 5
No FDS 16447
ARALDITE FUSION HARDENER
10.5. Matières incompatibles
10.6. Produits de décomposition dangereux
SECTION 11: INFORMATIONS TOXICOLOGIQUES
11.1. Informations sur les effets toxicologiques
Contact avec la peau
Irritant pour la peau.
Contact avec les yeux
Irritant pour les yeux.
SECTION 12: INFORMATIONS ÉCOLOGIQUES
Écotoxicité
Non reconnu comme dangereux pour l'environnement.
12.1. Toxicité
12.2. Persistance et dégradabilité
12.3. Potentiel de bioaccumulation
12.4. Mobilité dans le sol
12.5. Résultats des évaluations PBT et vPvB
12.6. Autres effets néfastes
SECTION 13: CONSIDÉRATIONS RELATIVES À L’ÉLIMINATION
13.1. Méthodes de traitement des déchets
Éliminer les déchets et résidus conformément aux règlements municipaux.
SECTION 14: INFORMATIONS RELATIVES AU TRANSPORT
Généralités Le produit n'est pas soumis à la réglementation internationale sur le transport des marchandises
dangereuses (IMDG, ICAO/IATA, ADR/RID).
14.1. Numéro ONU
Non applicable.
14.2. Nom d’expédition des Nations unies
Non applicable.
14.3. Classe(s) de danger pour le transport
Étiquettes De Transport
Aucun panneau d'avertissement de transport requis.
14.4. Groupe d’emballage
Non applicable.
14.5. Dangers pour l’environnement
Substance Dangereuse Pour L'Environnement/Polluant Marin
Non.
14.6. Précautions particulières à prendre par l’utilisateur
Non applicable.
14.7. Transport en vrac conformément à l’annexe II de la convention Marpol 73/78 et au recueil IBC
Non applicable.
SECTION 15: INFORMATIONS RÉGLEMENTAIRES
5 / 5
No FDS 16447
ARALDITE FUSION HARDENER
15.1. Réglementations/législation particulières à la substance ou au mélange en matière de sécurité, de santé et d’
environnement
15.2. Évaluation de la sécurité chimique
SECTION 16: AUTRES INFORMATIONS
Informations générales
This product should be used as directed by Bostik Ltd.For further information consult the product data sheet or contact Technical Services.
Références Littéraires
This safety data sheet was compiled using current safety information supplied by distributor of raw materials.
Commentaires De Mise À Jour
OBS: Lignes en marges signifient des corrections importantes par rapport à la version précédente. This safety data sheet supersedes all
previous issues and users are cautioned to ensure that it is current. Destroy all previous data sheets and if in doubt contact Bostik Limited.
Émise Par Approved LJ
Date de révision November 2011
Révision 3
Date September 2007
Phrases - R (Texte Intégral)
R34 CAUSE DES BRÛLURES.
R38 Irritant pour la peau.
R22 Nocif en cas d’ingestion.
Nocif pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour
l'environnement aquatique.
R52/53
R35 Provoque de graves brûlures.
R41 Risque de lésions oculaires graves.
R23/24 Toxique par inhalation et par contact avec la peau.
October 2011 Araldite® Fusion Page 1 of 3
Huntsman Advanced Materials
DIY Adhesives
AralditeÒ Fusion
Two component very fast epoxy adhesive
Other
commercial
names
• Araldite® Super Glue +
• Araldite® Instant Clear
• Araldite® Instant
• Araldite® 90 Segundos Fusion
• Araldite® 90 seconds Fusion
• Araldite® 90 seconds
Key properties • Very fast curing at room temperature
• Transparent / pale coloured
• 1 : 1 mixing
• Solvent free
Description Araldite® Fusion is a two part transparent epoxy adhesive gelling in 90 seconds. The product may be used to bond
metals, ceramics and many common plastics.
Product data
Property Araldite® Fusion /
Resin
Araldite® Fusion /
Hardener
Araldite® Fusion /
mixed
Colour (visual) transparent pale yellow pale yellow
Specific gravity 1.15 – 1.2 1.1 – 1.2 ca. 1.2
Viscosity at 25°C (Pa.s) 50 - 75 10 - 20 30 - 50
Pot Life (100 g at 25°C) - - 90 seconds
Processing Pretreatment
The strength and durability of a bonded joint are dependant on proper treatment of the surfaces to be bonded.
At the very least, joint surfaces should be cleaned with a good degreasing agent such as acetone, iso-propanol (for
plastics) or proprietary degreasing agent in order to remove all traces of oil, grease and dirt.
Low grade alcohol, gasoline (petrol) or paint thinners should never be used.
The strongest and most durable joints are obtained by either mechanically abrading or chemically etching (“pickling”)
the degreased surfaces. Abrading should be followed by a second degreasing treatment.
Mix ratio Parts by weight Parts by volume
Araldite® Fusion / Resin 100 100
Araldite® Fusion / Hardener 100 100
October 2011 Araldite® Fusion Page 2 of 3
Huntsman Advanced Materials
Application of adhesive
The resin/hardener mix is applied directly or with a spatula to the pretreated and dry joint surfaces.
A layer of adhesive 0.05 to 0.10 mm thick will normally impart the greatest lap shear strength to the joint. Huntsman
stresses that proper adhesive joint design is also critical for a durable bond. The joint components should be
assembled and secured in a fix position as soon as the adhesive has been applied.
Equipment maintenance
All tools should be cleaned with hot water and soap before adhesives residues have had time to cure. The removal of
cured residues is a difficult and time-consuming operation.
If solvents such as acetone are used for cleaning, operatives should take the appropriate precautions and, in addition,
avoid skin and eye contact.
Times to minimum shear strength
Temperature °C 23
Cure time to reach hours
LSS > 1MPa minutes 5
Cure time to reach hours
LSS > 10MPa minutes 90
LSS = Lap shear strength.
Typical cured
properties
Average lap shear strengths of typical joints (ISO 4587)
Cured for 16 hours at 40°C and tested at 23°C.
Pre-treatment: plastics abraded and degreased, metals sandblasted and degreased.
0 2 4 6 8 10 12 14 16 18 20
Aluminium
Steel 37/11
Stainless steel V4A
Copper
SMC
ABS
PVC
Polycarbonate
Polyamides
PMMA
PC
MPa
October 2011 Araldite® Fusion Page 3 of 3
Huntsman Advanced Materials
Lap shear strength versus temperature (ISO 4587) (typical average values)
Carried out on sandblasted and degreased aluminium, cure 16 hours at 40°C
0
5
10
15
20
-40 -20 0 20 40 60 80 100
°C
MPa
Storage Araldite® Fusion may be stored for up to 2 years at room temperature provided the components are stored in sealed
containers.
Handling
precautions
Caution
Our products are generally quite harmless to handle provided that certain precautions normally taken when handling
chemicals are observed. The uncured materials must not, for instance, be allowed to come into contact with
foodstuffs or food utensils, and measures should be taken to prevent the uncured materials from coming in contact
with the skin, since people with particularly sensitive skin may be affected. The wearing of impervious rubber or
plastic gloves will normally be necessary; likewise the use of eye protection. The skin should be thoroughly cleaned
at the end of each working period by washing with soap and warm water. The use of solvents is to be avoided.
Disposable paper - not cloth towels - should be used to dry the skin. Adequate ventilation of the working area is
recommended. These precautions are described in greater detail in the Material Safety Data sheets for the individual
products and should be referred to for fuller information.
Huntsman Advanced Materials warrants only that its products meet the specifications agreed with the buyer. Typical properties,
where stated, are to be considered as representative of current production and should not be treated as specifications.
The manufacture of materials is the subject of granted patents and patent applications; freedom to operate patented processes is
not implied by this publication.
While all the information and recommendations in this publication are, to the best of our knowledge, information and belief, accurate at the
date of publication, NOTHING HEREIN IS TO BE CONSTRUED AS A WARRANTY, EXPRESS OR OTHERWISE.
IN ALL CASES, IT IS THE RESPONSIBILITY OF THE USER TO DETERMINE THE APPLICABILITY OF SUCH INFORMATION
AND RECOMMENDATIONS AND THE SUITABILITY OF ANY PRODUCT FOR ITS OWN PARTICULAR PURPOSE.
The behaviour of the products referred to in this publication in manufacturing processes and their suitability in any given end-use
environment are dependent upon various conditions such as chemical compatibility, temperature, and other variables, which are
not known to Huntsman Advanced Materials. It is the responsibility of the user to evaluate the manufacturing circumstances and
the final product under actual end-use requirements and to adequately advise and warn purchasers and users thereof.
Products may be toxic and require special precautions in handling. The user should obtain Safety Data Sheets from Huntsman
Advanced Materials containing detailed information on toxicity, together with proper shipping, handling and storage procedures,
and should comply with all applicable safety and environmental standards.
Hazards, toxicity and behaviour of the products may differ when used with other materials and are dependent on manufacturing
circumstances or other processes. Such hazards, toxicity and behaviour should be determined by the user and made known to
handlers, processors and end users.
Except where explicitly agreed otherwise, the sale of products referred to in this publication is subject to the general terms and
conditions of sale of Huntsman Advanced Materials LLC or of its affiliated companies including without limitation, Huntsman
Advanced Materials (Europe) BVBA, Huntsman Advanced Materials Americas Inc., and Huntsman Advanced Materials (Hong
Kong) Ltd.
Huntsman Advanced Materials is an international business unit of Huntsman Corporation. Huntsman Advanced Materials trades
through Huntsman affiliated companies in different countries including but not limited to Huntsman Advanced Materials LLC in the
USA and Huntsman Advanced Materials (Europe) BVBA in Europe.
Araldite® is a registered trademark of Huntsman Corporation or an affiliate thereof.
Copyright © 2011 Huntsman Corporation or an affiliate thereof. All rights reserved.
Huntsman Advanced Materials
(Switzerland) GmbH
Klybeckstrasse 200
4057 Basel
Switzerland
Tel: +41 (0)61 299 11 11
www.go-araldite.com
Emergency number : + 32 35 751 234
ARALDITE FUSION
IDENTIFICATION DE LA SUBSTANCE/PRÉPARATION ET DE LA
SOCIÉTÉ/ENTREPRISE
FICHE DE DONNÉES DE SÉCURITÉ
Nom du produit
ARALDITE FUSION
Conforme au règlement (CE) n° 1907/2006 (REACH), Annexe II - France
1.
Numéro de téléphone d'appel
d'urgence
:
Fournisseur
:
:
Identification de la substance ou de la préparation
Type de produit : Liquide.
Pour toutes questions de Sécurité, Hygiène et Environnement relatives à ce document ou son
contenu, veuillez contacter:
E-Mail:
global_product_ehs_admat@huntsman.com
Utilisation de la
substance/préparation
: Système adhésif bi-composants
EUROPE: +32 35 75 1234
France ORFILA: +33(0)145425959
ASIA: +65 6336-6011
China: +86 20 39377888
Australia: 1800 786 152
New Zealand: 0800 767 437
USA: +1/800/424.9300
Huntsman Advanced Materials (Europe)BVBA
Everslaan 45
3078 Everberg / Belgium
Tel.: +41 61 299 20 41
Fax: +41 61 299 20 40
Description du produit : Working pack (preparation)
2. IDENTIFICATION DES DANGERS
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
3. COMPOSITION/INFORMATIONS SUR LES COMPOSANTS
Substance/préparation : Working pack (preparation)
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
4. PREMIERS SECOURS
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
5. MESURES DE LUTTE CONTRE L'INCENDIE
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
6. MESURES À PRENDRE EN CAS DE REJET ACCIDENTEL
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
Date d'édition/Date de
révision
: 11/13/2009. 1/6
ARALDITE FUSION
Manipulation
MANIPULATION ET STOCKAGE
Stockage
7.
Revêtir un équipement de protection individuelle approprié (voir Section 8). Il est
interdit de manger, boire ou fumer dans les endroits où ce produit est manipulé,
entreposé ou mis en oeuvre. Il est recommandé au personnel de se laver les mains
et la figure avant de manger, boire ou fumer. Les personnes ayant des antécédents
de sensibilisation cutanée ne doivent pas intervenir dans les processus utilisant ce
produit. Ne pas mettre en contact avec les yeux, la peau ou les vêtements. Ne pas
ingérer. Éviter de respirer les vapeurs ou le brouillard. Éviter le rejet dans
l'environnement. Consulter les instructions spéciales/la fiche de données de sécurité.
Garder dans le conteneur d'origine ou dans un autre conteneur de substitution
homologué fabriqué à partir d'un matériau compatible et tenu hermétiquement clos
lorsqu'il n'est pas utilisé. Les conteneurs vides retiennent des résidus de produit et
peuvent présenter un danger. Ne pas réutiliser ce conteneur.
Matériaux d'emballage
Stocker conformément à la réglementation locale. Stocker dans le récipient d'origine
à l'abri de la lumière directe du soleil dans un endroit sec, frais et bien ventilé à l'écart
des matériaux incompatibles (cf. la section 10). Garder le récipient hermétiquement
fermé lorsque le produit n'est pas utilisé. Les récipients ayant été ouverts doivent être
refermés avec soin et maintenus en position verticale afin d'éviter les fuites. Ne pas
stocker dans des conteneurs non étiquetés. Utiliser un récipient approprié pour éviter
toute contamination du milieu ambiant.
:
:
Recommandé : Utiliser le récipient d'origine.
Température de stockage : Stocker conformément à la réglementation locale. Stocker dans le récipient d'origine
à l'abri de la lumière directe du soleil dans un endroit sec, frais et bien ventilé à l'écart
des matériaux incompatibles (cf. la section 10). Garder le récipient hermétiquement
fermé lorsque le produit n'est pas utilisé. Les récipients ayant été ouverts doivent être
refermés avec soin et maintenus en position verticale afin d'éviter les fuites. Ne pas
stocker dans des conteneurs non étiquetés. Utiliser un récipient approprié pour éviter
toute contamination du milieu ambiant. Stocker entre les températures suivantes: 2 à
40°C (35.6 à 104°F).
Classe de danger de
stockage Huntsman
Advanced Materials
: Classe de stockage 10, Liquide nocif pour l'ambience
Nom des composants Limites d'exposition professionnelle
Valeurs limites d'exposition
8. CONTRÔLE DE L'EXPOSITION/PROTECTION INDIVIDUELLE
Aucune valeur de limite d'exposition connue.
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
PROPRIÉTÉS PHYSIQUES ET CHIMIQUES
État physique Liquide.
Point d'éclair Coupe fermée: >145°C (>293°F) [DIN 51758 EN 22719 (Pensky-Martens Closed
Cup)]
9.
:
:
Informations générales
Aspect
Informations importantes relatives à la santé, à la sécurité et à l'environnement
Masse volumique : 1.15 g/cm3 [20°C (68°F)]
Solubilité dans l'eau : Insoluble
Date d'édition/Date de
révision
: 11/13/2009. 2/6
ARALDITE FUSION
STABILITÉ 10. ET RÉACTIVITÉ
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
11. INFORMATIONS TOXICOLOGIQUES
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
12. INFORMATIONS ÉCOLOGIQUES
Se référer aux fiches de données de sécurité des composants individuels de l'emballage de travail.
13. CONSIDÉRATIONS RELATIVES À L'ÉLIMINATION
070208
Catalogue Européen des
Déchets
:
Déchets Dangereux : Il se peut que la classification du produit satisfasse les critères de déchets dangereux.
Il est recommandé d'éviter ou réduire autant que possible la production de déchets.
Les conteneurs vides ou les saches internes peuvent retenir des restes de produit.
Ne se débarrasser de ce produit et de son récipient qu'en prenant toutes précautions
d'usage. Élimination des produits excédentaires et non recyclables par une
entreprise autorisée de collecte des déchets. La mise au rebut de ce produit, des
solutions et des sous-produits devra en permanence respecter les exigences légales
en matière de protection de l'environnement et de mise au rebut des déchets ainsi
que les exigences de toutes les autorités locales. Évitez la dispersion des matériaux
déversés, ainsi que leur écoulement et tout contact avec le sol, les cours d'eau, les
égouts et conduits d'évacuation.
Méthodes d'élimination des :
déchets
07 02 08* autres résidus de réaction et résidus de distillation
Il faut dans tous les cas appliquer toutes les lois locales régionales et nationales ainsi
que les directives européennes. Il appartient à l'utilisateur final de déterminer le code
des déchets spécifique à chaque secteur industriel en utilisant le code Européen
approprié du catalogue européen des déchets. Il est recommandé que tous les
détails soient indiqués par le responsable des déchets.
14.
Réglementation internationale du transport
INFORMATIONS RELATIVES AU TRANSPORT
Nom d'expédition
ADR : Matière dangereuse du point de vue de l'environnement, liquide, n.s.a. BISPHENOL A/F EPOXY
RESIN
IMDG : Environmentally hazardous substance, liquid, n.o.s. (BISPHENOL A/F EPOXY RESIN)
IATA : Environmentally hazardous substance, liquid, n.o.s. (BISPHENOL A/F EPOXY RESIN)
Informations
réglementaires
Numéro
ONU
Classes Groupe
d'emballage
Étiquette Autres informations
9
Classe ADR/RID UN3082 9 III
Classe IMDG UN3082 9 III
9
Emergency schedules (EmS)
F-A, S-F
Code de classificationM6
Numéro
d'identification du
danger
90
Date d'édition/Date de
révision
: 11/13/2009. 3/6
ARALDITE FUSION
14. INFORMATIONS RELATIVES AU TRANSPORT
Passenger and Cargo Aircraft
Quantity limitation: 450 L
Packaging instructions: 914
Cargo Aircraft OnlyQuantity limitation:
450 L
Packaging instructions: 914
9
Classe IATA UN3082 9 III
15. INFORMATIONS RÉGLEMENTAIRES
Conseils de prudence S24- Éviter le contact avec la peau.
S37/39- Porter des gants appropriés et un appareil de protection des yeux/du visage.
S61- Éviter le rejet dans l'environnement. Consulter les instructions spéciales/la fiche
de données de sécurité.
R36/38- Irritant pour les yeux et la peau.
R43- Peut entraîner une sensibilisation par contact avec la peau.
R51/53- Toxique pour les organismes aquatiques, peut entraîner des effets néfastes
à long terme pour l'environnement aquatique.
Symbole(s) de danger
Phrases de risque
Réglementations de l'Union Européenne
Réglementations nationales
Contient du (de la)
:
:
:
:
Phrases d'avertissement
supplémentaire
: Non applicable.
Irritant, Dangereux pour l'environnement
produit de réaction: bisphénol-A-épichlorhydrine; résines époxydiques (poids
moléculaire moyen < 700)
résine époxidique à base de bisphénol F
Déterminés en accord avec les directives de l'UE 67/548/EEC et 1999/45/EC (y compris les amendements), la
classification et l'étiquetage prennent en compte l'usage prévu du produit.
Surveillance médicale
renforcée
: Arrêté du 11 Juillet 1977 fixant la liste des travaux nécessitant une surveillance
médicale renforcée: non concerné
Réglementations Internationales
Listes internationales : Inventaire des substances chimiques d'Australie (AICS): Tous les composants
sont répertoriés ou exclus.
Inventaire des substances chimiques existantes en Chine (IECSC): Tous les
composants sont répertoriés ou exclus.
Inventaire du Japon (ENCS): Un composant au moins n'est pas répertorié.
Inventaire du Japon (ISHL): Indéterminé.
Inventaire de Corée (KECI): Tous les composants sont répertoriés ou exclus.
Inventaire néo-zélandais des substances chimiques (NZIoC): Indéterminé.
Inventaire des substances chimiques des Philippines (PICCS): Un composant au
moins n'est pas répertorié.
Inventaire des États-Unis (TSCA 8b): Tous les composants sont répertoriés ou
exclus.
Inventaire d'Europe: Tous les composants sont répertoriés ou exclus.
Inventaire du Canada: Tous les composants sont répertoriés ou exclus.
Xi, N
Etiquetage exceptionnel
pour préparations
spéciales
: Contient des composés époxydiques. Voir les informations transmises par le
fabricant.
Date d'édition/Date de
révision
: 11/13/2009. 4/6
ARALDITE FUSION
AUTRES DONNÉES
11/13/2009.
Historique
16.
Date d'impression
Date d'édition/ Date de
révision
Version
Avis au lecteur
Date de la précédente
édition
:
:
:
:
R23/24- Toxique par inhalation et par contact avec la peau.
R22- Nocif en cas d'ingestion.
R35- Provoque de graves brûlures.
R41- Risque de lésions oculaires graves.
R38- Irritant pour la peau.
R36/38- Irritant pour les yeux et la peau.
R43- Peut entraîner une sensibilisation par contact avec la peau.
R50/53- Très toxique pour les organismes aquatiques, peut entraîner des effets
néfastes à long terme pour l'environnement aquatique.
R51/53- Toxique pour les organismes aquatiques, peut entraîner des effets néfastes
à long terme pour l'environnement aquatique.
R53- Peut entraîner des effets néfastes à long terme pour l'environnement aquatique.
Texte complet des phrases :
R citées dans les sections 2
et 3 - France
Référence du texte complet
des classifications se
trouvant dans les Sections 2
et 3 - France
: T - Toxique
C - Corrosif
Xn - Nocif
Xi - Irritant
N - Dangereux pour l'environnement
Indique quels renseignements ont été modifiés depuis la version précédente.
11/13/2009.
Aucune validation antérieure.
1
Epoxy Resins and Curing Agents; Toxicology, Health, Safety and Environmental Aspects (Plastics Europe, May 2006)
Les informations et recommandations figurant dans cette publication sont fondées sur notre expérience générale
et sont fournies de bonne foi au mieux de nos connaissances actuelles, MAIS RIEN DANS LES PRESENTES NE
DOIT ÊTRE INTERPRETE COMME CONSTITUANT UNE GARANTIE OU UNE DECLARATION, EXPRESSE,
IMPLICITE OU AUTRE.
DANS TOUS LES CAS, IL INCOMBE A L'UTILISATEUR DE DETERMINER ET DE VERIFIER L'EXACTITUDE, AINSI
QUE LE CARACTERE SUFFISANT ET APPLICABLE DE TELLES INFORMATIONS ET RECOMMANDATIONS, DE
MEME QUE L'ADEQUATION ET L'ADAPTATION D'UN QUELCONQUE PRODUIT A UNE UTILISATION SPECIFIQUE
OU DANS UN BUT PARTICULIER.
LES PRODUITS MENTIONNES PEUVENT PRESENTER DES RISQUES INCONNUS ET DOIVENT ETRE UTILISES
AVEC PRECAUTION. MEME SI CERTAINS RISQUES SONT DECRITS DANS CETTE PUBLICATION, IL N'EXISTE
AUCUNE GARANTIE QU'IL S'AGIT DES SEULS RISQUES EXISTANTS.
Les risques, la toxicité et le comportement des produits peuvent différer lorsque ceux-ci sont utilisés avec
d'autres matériaux et dépendent des conditions de fabrication et d'autres processus. Ces risques, cette toxicité et
ces comportements doivent être déterminés par l'utilisateur et portés à la connaissance des personnes ou entités
chargés du transport ou de la manutention, du traitement ou de la transformation, ainsi que de tous utilisateurs
finaux.
Pour toute demande, contactez le bureau commercial Huntsman Sales le plus proche ou directement Huntsman
(Belgium) BVBA, Everslaan 45, B-3078 Everberg, Belgique. Tél. +32 2 758 9211 - Fax +32 758 9946.
Huntsman Belgium (BVBA)
Everslaan 45
B-3078 Everberg
Belgium
Tel.:+32-(0)2-758-9211
Références
Date d'édition/Date de
révision
: 11/13/2009. 5/6
ARALDITE FUSION
16. AUTRES DONNÉES
NO PERSON OR ORGANIZATION EXCEPT A DULY AUTHORIZED HUNTSMAN EMPLOYEE IS AUTHORIZED TO
PROVIDE OR MAKE AVAILABLE DATA SHEETS FOR HUNTSMAN PRODUCTS. DATA SHEETS FROM
UNAUTHORIZED SOURCES MAY CONTAIN INFORMATION THAT IS NO LONGER CURRENT OR ACCURATE. NO
PART OF THIS DATA SHEET MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM, OR BY ANY MEANS,
WITHOUT PERMISSION IN WRITING FROM HUNTSMAN. ALL REQUESTS FOR PERMISSION TO REPRODUCE
MATERIAL FROM THIS DATA SHEET SHOULD BE DIRECTED TO HUNTSMAN, MANAGER, PRODUCT SAFETY AT
THE ABOVE ADDRESS.
Date d'édition/Date de
révision
: 11/13/2009. 6/6
FICHE DE DONNÉES DE SÉCURITÉ
Section 1: Identification de la substance/du mélange et de la société/l’entreprise
Identificateur de produit
Nom commercial ou
désignation du mélange
Contralube 770
Numéro -
d'enregistrement
Synonymes Aucun(e)(s).
Code de produit Contralube 770
Date de la première
publication
le 06-04-06
Numéro de version 12
le 17-02-11
le 06-01-11
Date de révision
Date d'entrée en vigueur de la
nouvelle version
Utilisations identifiées pertinentes de la substance ou du mélange et utilisations déconseillées
Utilisations identifiées Non disponible.
Utilisations déconseillées Aucun connu.
Renseignements concernant le fournisseur de la fiche de données de sécurité
Newgate Simms Ltd.
Broughton Mills Road, Bretton
Chester, CH4 0BY, United Kingdom
info@newgatesimms.co.uk
Section 2: Identification des dangers
Classification de la substance ou du mélange
Les dangers physiques, sanitaires et environnementaux du mélange ont été évalués et/ou testés, et la classification suivante
s'applique.
Classification selon la directive 67/548/CEE ou 1999/45/CEE et ses amendements
Cette préparation ne répond pas aux critères de classification de la directive 1999/45/CE et ses amendements.
Classification selon le règlement (CE) n° 1272/2008 et ses amendements
Ce mélange ne répond pas aux critères de classification du règlement (CE) 1272/2008 et ses amendements.
Résumé des dangers
Risques physiques Pas de classification pour les dangers physiques.
Risques pour la santé Pas de classification pour les dangers sanitaires.
Dangers pour
l’environnement
Pas de classification pour les dangers pour l'environnement.
Risques particuliers Non disponible.
Principaux symptômes Non disponible.
Éléments d’étiquetage
Étiquettage selon le règlement (CE) n° 1272/2008 et ses amendements
Numéro d'identification -
Mentions de danger La substance ne répond pas aux critères de classification.
Conseils de prudence
Prévention Non disponible.
Réaction Non disponible.
Stockage Non disponible.
Élimination Non disponible.
Informations supplémentaires
de l'étiquette
Sans objet.
Autres dangers Non affecté.
Nom de la matière: Contralube 770
FDS n° Contralube 770 N° version: 12 Date de révision: le 17-02-11 Date d'impression: le 17-02-11 1 / 7
SDS FRANCE
Section 3: Composition/informations sur les composants
Mélange
Les composants ne sont pas dangereux ou sont en dessous des limites de déclaration légales.
Section 4: Premiers secours
Description des premiers secours
Inhalation Si des symptômes se développent, éloigner la personne touchée de la source d'exposition et la
sortir au grand air. Consulter immédiatement un médecin.
Contact avec la peau Laver avec de l'eau et du savon. Consulter un médecin en cas de symptômes. Laver séparément
les vêtements avant réutilisation.
Contact avec les yeux Laver immédiatement les yeux à grande eau pendant au moins 15 minutes. Consulter
immédiatement un médecin.
Ingestion Du fait de la nature physique de ce matériau, il est improbable qu'une ingestion ne se produise.
S'il se produit tout de même l'ingestion d'une grande quantité, solliciter des soins médicaux. S'il
se produit tout de même l'ingestion d'une grande quantité, Ne pas faire vomir sans l'avis d'un
médecin. Si le vomissement se produit naturellement, incliner la victime vers l'avant pour réduire
le risque d'aspiration. Ne jamais faire avaler quelque chose à une victime inconsciente ou
souffrant de convulsions.
Principaux symptômes et
effets, aigus et différés
Non disponible.
Indication des éventuels soins
médicaux immédiats et
traitements particuliers
nécessaires
Non disponible.
Section 5: Mesures de lutte contre l’incendie
Risques d'incendie généraux Ce produit est ininflammable.
Moyens d’extinction
Moyen d'extinction
approprié
Brouillard d’eau. Mousse. Dioxyde de carbone (CO2). Produit chimique sec.
Moyens d’extinction
inappropriés
Eau. En cas d'incendie ne pas utiliser de jet d'eau car celà dispersera le feu.
Dangers particuliers résultant
de la substance ou du mélange
Non disponible.
Conseils aux pompiers
Equipements de protection
particuliers des pompiers
Porter un équipement de protection adéquat.
Procédures spéciales de
lutte contre l'incendie
Porter des vêtements de protection complets, y compris un casque, un appareil autonome de
respiration à pression positive ou à demande de pression, des vêtements de protection et un
masque anti-poussière. Éloigner les contenants de la zone de feu si cela peut se faire sans
risque. Éloigner les récipients de l'incendie si cela peut se faire sans risque.
Section 6: Mesures à prendre en cas de dispersion accidentelle
Précautions individuelles, équipement de protection et procédures d’urgence
Pour les non-secouristes Tenir à l’écart le personnel superflu. Prévenir les autorités locales si des fuites significatives ne
peuvent pas être contenues. Ne pas toucher les récipients endommagés ou le produit déversé à
moins d'être vêtu d'une tenue protectrice appropriée. Garder les personnes à l'écart de l'endroit
de l'écoulement/de la fuite et contre le vent. Observer les précautions indiquées dans les autres
sections.
Pour les secouristes Non disponible.
Précautions pour la protection
de l’environnement
Empêcher l'infiltration dans les cours d'eau, les égouts, les sous-sols ou les endroits clos.
Nom de la matière: Contralube 770
FDS n° Contralube 770 N° version: 12 Date de révision: le 17-02-11 Date d'impression: le 17-02-11 2 / 7
SDS FRANCE
Méthodes et matériel de
confinement et de nettoyage
Déversements importants : Arrêter le débit de matière, si ceci est sans risque. Enlever avec un
absorbant inerte. Endiguer le matériau renversé si cela est possible. Couvrir d'une bâche de
plastique pour éviter la dispersion. Absorber avec de la vermiculite, du sable sec ou de la terre,
puis placer en récipient. Nettoyer soigneusement la surface contaminée. Après avoir récupéré le
produit, rincer la zone à l'eau.
Déversements mineurs : Essuyer avec une matière absorbante (p.ex. tissu, laine). Nettoyer à
fond la surface pour éliminer toute contamination résiduelle.
Ne jamais réintroduire le produit répandu dans son récipient d'origine en vue d'une réutilisation.
Pour les conseils relatifs à l'élimination, voir la rubrique 13. Ne pas toucher les containers
endommagés ou la matière répandue. Il se peut que les dégâts au container extérieur aient été
sans conséquences pour le container interne. Si le container interne est endommagé et fuit, le
couvrir avec une serviette ou un ch Le produit ramassé ainsi que les chiffons de nettoyage seront
jetés dans les containers prévus à cet effet.
Référence à d'autres sections Pour les conseils relatifs à l'élimination, voir la rubrique 13.
Section 7: Manipulation et stockage
Précautions à prendre pour une
manipulation sans danger
NE PAS mettre sous pression, couper, chauffer ou souder les récipients. Les récipients vides
peuvent contenir des résidus du produit. Éviter tout contact prolongé ou répété de la peau avec ce
matériau. Ne pas manipuler ou stocker à proximité d'une flamme nue, d'une source de chaleur ou
toute autre source d'ignition. Éviter de respirer les gaz/vapeurs/brouillards/fumées. Ne pas ingérer.
Ne pas goûter ni avaler. Éviter le contact avec les yeux. Se laver soigneusement après
manipulation.
Conditions d’un stockage sûr,
y compris d’éventuelles
incompatibilités
Tenir à l'écart de la chaleur et des sources d'ignition. Entreposer dans un endroit frais. Conserver
dans un récipient fermé, à l'écart des matières incompatibles.
Utilisation(s) finale(s)
particulière(s)
Non disponible.
Section 8: Contrôles de l’exposition/protection individuelle
Paramètres de contrôle
Valeurs limites d’exposition
professionnelle
Il n'y a pas de limites d'exposition pour ce ou ces ingrédients.
Valeurs limites biologiques Il n'y a pas de limites d'exposition biologique pour ce ou ces ingrédients.
Procédures de suivi
actuellement recommandées
Non disponible.
DNEL Non disponible.
PNEC Non disponible.
Contrôles de l’exposition
Contrôles techniques
appropriés
Porter des gants thermorésistants, étanches, et des vêtements de protection pour éviter tout
contact avec la peau.
Mesures de protection individuelle, telles que les équipements de protection individuelle
Généralités Non disponible.
Protection des yeux/du
visage
Portez des lunettes de sécurité ou des lunettes de protection contre les substances chimiques (en
cas de risque de projection).
Protection de la peau
- Protection des mains Non nécessaire en général.
- Divers Porter un vêtement de protection approprié. Porter des gants en nitrile, néoprène, PVC ou en
viton. Choisir l'équipement de protection conformément aux normes CEN en vigueur et en
coopération avec le fournisseur de l'équipement de protection.
Protection respiratoire Aucun équipement de protection respiratoire individuel n'est normalement nécessaire. Un
appareil respiratoire purificateur d'air doté d'une cartouche de vapeur organique peut être utilisé
dans certains cas l'où on s'attend à ce que les concentrations aéroportées dépassent les limites
d'exposition, ou en cas d'irritation ou d'apparition de symptômes.
Risques thermiques Non disponible.
Mesures d'hygiène Lors de l'utilisation, ne pas manger, boire ou fumer. Se laver soigneusement les mains après
manipulation. Laver les vêtements contaminés avant de les porter à nouveau.
Contrôles d’exposition liés à la
protection de l’environnement
Non disponible.
Section 9: Propriétés physiques et chimiques
Informations sur les propriétés physiques et chimiques essentielles
État physique Liquide.
Nom de la matière: Contralube 770
FDS n° Contralube 770 N° version: 12 Date de révision: le 17-02-11 Date d'impression: le 17-02-11 3 / 7
SDS FRANCE
Forme Liquide. Semi solide
Couleur Clair
Odeur Légère
Seuil olfactif Non disponible.
pH Sans objet.
Point de fusion/point de
congélation
Non disponible.
Point d'ébullition, point
d'ébullition initial et
gamme d'ébullition
Non disponible.
Point d'éclair Sans objet.
Température d’autoignition Sans objet.
Inflammabilité (solide, gaz) Non disponible.
Limite d'inflammabilité -
inférieure (%)
Non disponible.
Limite d'inflammabilité -
supérieure (%)
Non disponible.
Propriétés comburantes Sans objet.
Propriétés explosives Sans objet.
Limite d'explosivité Sans objet.
Pression de vapeur Sans objet.
Densité de vapeur Sans objet.
Taux d’évaporation Sans objet.
Densité relative Non disponible.
Densité 0,92 g/cm³
Solubilité (dans l'eau) Non disponible.
Coefficient de partition
(n-octanol/eau)
Non disponible.
Température de
décomposition
Non disponible.
Viscosité Non disponible.
Fraction volatile Non disponible.
Autres informations Aucune information pertinente supplémentaire n'est disponible.
Section 10: Stabilité et réactivité
Réactivité Aucun connu.
Stabilité chimique Ce produit est stable dans des conditions normales. Stable.
Possibilité de réactions
dangereuses
Non disponible.
Conditions à éviter Chaleur, flammes et étincelles.
Matières incompatibles Acides forts, alcalis et agents d'oxydation.
Produits de décomposition
dangereux
Monoxyde de carbone, dioxyde de carbone et/ou hydrocarbures à faible poids moléculaire.
Section 11: Informations toxicologiques
Généralités Non disponible.
Informations sur les voies d’exposition probables
Ingestion Non disponible.
Inhalation Non disponible.
Contact avec la peau Non disponible.
Contact avec les yeux Non disponible.
Symptômes Non
disponible.
Informations sur les effets toxicologiques
Toxicité aiguë Non disponible.
Corrosion ou irritation de
la peau
Nom de la matière: Contralube 770
FDS n° Contralube 770 N° version: 12 Date de révision: le 17-02-11 Date d'impression: le 17-02-11 4 / 7
SDS FRANCE
Blessure ou irritation
grave des yeux
Non disponible.
Sensibilisation respiratoire Non disponible.
Sensibilisation cutanée Non disponible.
Mutagénicité des cellules
germinales
Non disponible.
Cancérogénicité Ce produit ne contient aucune substance carcinogène ou substance potentiellement carcinogène
selon la liste du CIRC.
Toxicité pour la
reproduction
Non disponible.
Toxicité spécifique au
niveau de l'organe cible
suite à une exposition
unique
Non disponible.
Toxicité spécifique au
niveau de l'organe cible
suite des expositions
répétées
Non disponible.
Risque en cas d’inhalation Non disponible.
Informations sur les mélanges
et informations sur les
substances
Non disponible.
Autres informations Ce produit n'est associé à aucun effet négatif connu sur la santé de l'homme.
Section 12: Informations écologiques
Toxicité Il n'y a pas de données de toxicité pour ce ou ces ingrédients.
Persistance et
dégradabilité
Aucune donnée n’est disponible sur la biodégradabilité du produit.
Potentiel de
bioaccumulation
Non disponible.
Mobilité Non disponible.
Devenir dans
l’environnement -
Coefficient de partage
Non disponible.
Mobilité dans le sol Non disponible.
Résultats des
évaluations PBT et
VPVB
Non disponible.
Autres effets néfastes Non disponible.
Section 13: Considérations relatives à l’élimination
Méthodes de traitement des déchets
Déchets résiduaires Non disponible.
Emballages contaminés Les conteneurs vides doivent être acheminés vers un site agréé pour le traitement des déchets à
des fins de recyclage ou d'élimination.
Code de déchet européen Non disponible.
Sent out for translation Recueillir et réutiliser ou éliminer dans des récipients scellés dans un centre de collecte de
déchets agréés. Élimination des contenus/contenants conformément aux dispositions locales /
régionales /nationales / internationales en vigueur.
Section 14: Informations relatives au transport
ADR
Non réglementé comme une marchandise dangereuse.
RID
Non réglementé comme une marchandise dangereuse.
ADN
Non réglementé comme une marchandise dangereuse.
IATA
Non réglementé comme une marchandise dangereuse.
Nom de la matière: Contralube 770
FDS n° Contralube 770 N° version: 12 Date de révision: le 17-02-11 Date d'impression: le 17-02-11 5 / 7
SDS FRANCE
IMDG
Non réglementé comme une marchandise dangereuse.
Transport en vrac
conformément à l’annexe II de
la convention Marpol 73/78 et
au recueil IBC
Pas d'information disponible.
Section 15: Informations réglementaires
Réglementations/législation particulières à la substance ou au mélange en matière de sécurité, de santé et d’environnement
Réglementations de l’UE
Règlement (CE) nº 2037/2000 relatif à des substances qui appauvrissent la couche d'ozone, Annexe I
N'est pas listé.
Règlement (CE) nº 2037/2000 relatif à des substances qui appauvrissent la couche d'ozone, Annexe II
N'est pas listé.
Règlement (CE) n° 850/2004 concernant les polluants organiques persistants, Annexe I
N'est pas listé.
Règlement (CE) no 689/2008 concernant les exportations et importations de produits chimiques dangereux, Annexe I,
Partie 1
N'est pas listé.
Règlement (CE) no 689/2008 concernant les exportations et importations de produits chimiques dangereux, Annexe I,
Partie 2
N'est pas listé.
Règlement (CE) no 689/2008 concernant les exportations et importations de produits chimiques dangereux, Annexe I,
Partie 3
N'est pas listé.
Règlement (CE) no 689/2008 concernant les exportations et importations de produits chimiques dangereux, Annexe V
N'est pas listé.
Directive 96/61/CEE relative à la prévention et à la réduction intégrées de la pollution (IPPC) : Article 15, registre
européen des émissions polluantes (EPER)
N'est pas listé.
Règlement (CE) n° 1907/2006, Article 59(1). Liste candidate
N'est pas listé.
Autres réglementations Le produit ne nécessite pas d'étiquetage conformément aux directives de la CE et aux
réglementations nationales du pays concerné. Cette fiche de données de sécurité est conforme
aux exigences de la Directive 2001/58/CE. Cette fiche de données de sécurité est conforme aux
spécifications du Règlement (CE) N° 1907/2006.
Réglementations nationales Non disponible.
Évaluation de la sécurité
chimique
Aucune évaluation de sécurité chimique n'a été mise en oeuvre.
Section 16: Autres informations
Liste des abréviations Non disponible.
Références Non disponible.
Informations sur la méthode
d'évaluation utilisée pour
classer le mélange
Non disponible.
Texte intégral des
avertissements ou phrases R
et H en Sections 2 à 15
Aucun(e)(s).
Informations de révision Identification du produit et de l'entreprise : Identification du produit et de l'entreprise
Section 5: Mesures de lutte contre l’incendie: Equipements de protection particuliers des pompiers
Section 5: Mesures de lutte contre l’incendie: Risques d'incendie généraux
Section 6: Mesures à prendre en cas de dispersion accidentelle: Référence à d'autres sections
Section 8: Contrôles de l’exposition/protection individuelle: - Divers
Informations de formation Non disponible.
Édité par Ralph Patrizio
Avis de non-responsabilité Les informations fournies dans cette fiche technique de sécurité sont à notre connaissance exactes
et fiables à la date de leur publication. Les informations fournies sont uniquement des conseils pour
la manutention, l’utilisation, le traitement, le stockage, le transport, l’évacuation et le rejet du produit
en toute sécurité. Newgate Simms Ltd. ne fournit aucune garantie quant aux informations mises à
disposition et exclut toute responsabilité à cet égard. Les informations contenues dans cette fiche
sont exactes dans l'état actuel des connaissances et reposent sur les données disponibles au
moment de la préparation du document.
Nom de la matière: Contralube 770
FDS n° N° version: 12 Date de révision: le 17-02-11 Date d'impression: le 17-02-11 6 / 7
SDS FRANCE
Date d'émission le 17-02-11
Date de révision le 17-02-11
Date d'impression le 17-02-11
Nom de la matière: NYOGEL 760G
FDS n° NYOGEL 760G N° version: 12 Date de révision: le 17-02-11 Date d'impression: le 17-02-11 7 / 7
SDS FRANCE
CRC Industries France SAS
6, Avenue du Marais – B.P. 90028
F-95102 Argenteuil Cedex. - France
Tél.: + 33 (0)1 34 11 20 00 Fax.:+ 33 (0)1 34 11 09 96
S.A au capital de 1.936.667 € - R.C.S. Pontoise B 391 513 314 – APE 515 L
www.crcind.com
1/2
Protection
1. Description générale
Spécialement étudié pour décaper le vernis KF1280 ND, ce produit permet d’enlever la plupart des vernis modifiés acryliques existants (frais ou polymérisés depuis plusieurs années) des circuits imprimés et cela sans altérer les composants électroniques.
2. Caractéristiques
Liquide incolore à base de solvants oxygénés
Faible odeur
Bonne compatibilité avec les composants électroniques.
N’altère pas les circuits imprimés dans des conditions normales d’utilisation. Il est toutefois recommandé de faire des essais préalablement.
Évaporation relativement rapide accéléré par l’usage d’air comprimé ou d’un dépoussiérant « Aero Clean X Force ».
3. Applications
Electronique, Aéronautique, électricité.
Décapage du vernis KF1280 ND (réf. 1141 & 2046) sur les circuits imprimés ou autres matériels électroniques.
Permet de réaliser des interventions de remises en état ou d’amélioration sur des circuits imprimés protégés par des vernis durs et résistants.
4. Mode d’emploi
Au pinceau/ au pistolet / en trempage: Enduire ou pulvériser soigneusement les surfaces à traiter. Afin d’éliminer les résidus de vernis, faire ruisseler du produit sur l’ensemble du circuit et laisser sécher. Accélérer l’évaporation par l’utilisation d’air comprimé ou d’un dépoussiérant Aero Clean X force.
Selon l’équipement disponible à l’utilisateur, celui peut déterminer l’utilisation par sa propre expérience.
Une fiche de données de sécurité (FDS) conforme à la reglementation EC N° 1907/2006 Art.31 et amendements est disponible pour tous les produits KF.
Décapant KF 1280 ND
Pour vernis
CRC Industries France SAS
6, Avenue du Marais – B.P. 90028
F-95102 Argenteuil Cedex. - France
Tél.: + 33 (0)1 34 11 20 00 Fax.:+ 33 (0)1 34 11 09 96
S.A au capital de 1.936.667 € - R.C.S. Pontoise B 391 513 314 – APE 515 L
www.crcind.com
2/2
Protection
5. Caractéristiques typiques du produit
Aspect : incolore
Odeur : légère
Faible viscosité
Densité : 0,913
Point éclair : > 64 °C
Ne contient pas d’aromatiques polycycliques,
ni des métaux lourds, ni de composés chlorés
Recouvrable par un nouveau vernis : après séchage complet
6. Conditionnement
Réf. : 2045 - Bidon de 5 L Carton de 2 bidons
Toutes les données dans cette publication sont basées sur l'expérience et les tests de laboratoire. Vu l’importante variété des conditions et des appareillages employés, ainsi que des facteurs humains imprévisibles qui peuvent avoir une influence importante sur les résultats de l’application, nous vous conseillons de vérifier la compatibilité du produit avant son utilisation. Toutes ces informations sont données suivant la plus grande objectivité, mais sans garantie de notre part exprimée ou implicite.
Cette fiche technique peut déjà, à ce moment précis, être révisée pour des raisons liées à la législation, à la disponibilité des composants, ou à des expériences nouvellement acquises. La dernière version de cette fiche technique, qui est la seule valable, vous sera envoyée sur simple demande, ou peut être trouvée sur notre site Internet: www.crcind.com.
Nous vous recommandons de vous enregistrer sur notre site Internet pour ce produit, afin de recevoir automatiquement chaque dernière version future.
Version: 0 02 1204 01
Date: 20 mars 2012
Pour vernis
Décapant KF 1280 ND
Manufactured by :
CRC Industries Europe BVBA
Touwslagerstraat 1 – 9240 Zele – Belgium
Tel (32) (0) 52/45.60.11 Fax (32) (0) 52/45.00.34
www.crcind.com
FICHE TECHNIQUE
1/2
CRC HANDCLEANER
Nettoyant mains
Réf. :10535
1. DESCRIPTION GENERALE
Nettoyant pour les mains, contenant de la lanoline. S’emploi sans eau.
La formule du Nettoyant Mains CRC permet de répondre aux exigences sévères des
professionnels dans l’industrie et est axée principalement sur le nettoyage des mains. Elle
est à base de solvants hydrocarbonés doux et de surfactants biodégradables. Le Nettoyant
Mains CRC peut être employé sans eau; il est donc idéal pour les travaux, tant à l'intérieur
qu'à l'extérieur, aux endroits où l’on ne dispose pas d'eau.
2. CARACTERISTIQUES
• Enlève la plupart des saletés et des salissures tenaces.
• Extrêmement efficace sur la graisse, les peintures ordinaires, les encres, les ciment-colles,
les bitumes, le carbone et bien d'autres composants chimiques.
• Peut être utilisé avec ou sans eau.
• Nettoie rapidement.
• Contient de la lanoline pour protéger la peau.
• Ses agents antiseptiques réduisent les risques d'infection bactérienne.
• Sans abrasifs.
• Après traitement, la peau des mains reste douce.
• Biodégradable.
3. UTILISATIONS
Pour débarrasser les mains de:
• huiles et graisses
• dépôts et salissures,
• ciment et colles,
• bitumes et goudrons
• peintures et encres ordinaires
Remplace les savons ordinaires:
• dans les usines
• dans les mines,
• dans les fermes,
• sur les chantiers de construction,
• à domicile.
4. INSTRUCTIONS
• Ne pas mouiller les mains.
• Appliquer suffisamment de nettoyant (environ une cuillère à thé) sur les mains souillées
sèches.
• Bien frotter jusqu'à ce que les salissures soient complètement liquéfiées et détachées.
• Il suffit d'essuyer les mains avec du papier ménager, ou un chiffon. Eventuellement rincer
à l'eau et essuyer.
• Eviter le contact avec les yeux. Tenir hors de portée des enfants.
• Une fiche de sécurité (MSDS) selon EU93/112 est disponible pour tous les produits CRC.
Manufactured by :
CRC Industries Europe BVBA
Touwslagerstraat 1 – 9240 Zele – Belgium
Tel (32) (0) 52/45.60.11 Fax (32) (0) 52/45.00.34
www.crcind.com
FICHE TECHNIQUE
2/2
CRC HANDCLEANER
Nettoyant mains
Réf. :10535
5. DONNEES TYPIQUES DU PRODUIT (sans le gaz propulseur)
Aspect : crème semi-solide,
Couleur : blanc cassé
Odeur : typique, parfum peu prononcé
Densité (à 20°C) : 1 ± 0,1
pH (à 5% dans de l'eau) : 6,25 – 6,75
Viscosité : 8000 – 9000 cp
Teneur en matières solides (6 h à 100°C) : 12,0%
Stabilité thermique
48 h à 45°C : bonne
48 h à 0°C : bonne
Caractéristiques du solvant hydrocarboné
Intervalle de distillation : 195-245°C
Point éclair (en vase fermée) : 73°C
Teneur en composants aromatiques : < 0,1% pds
6. CONDITIONNEMENT
Tube 12 x 150 ml
Bidon 6 x 2,5 l
Un distributeur et un support pour le bidon de 2,5 litres sont disponibles.
Toutes les données dans cette publication sont basées sur l'expérience et les tests de laboratoire. Vu l’importante
variété des conditions et des appareillages employés, ainsi que des facteurs humains imprévisibles qui peuvent
avoir une influence importante sur les résultats de l’application, nous vous conseillons de vérifier la compatibilité
du produit avant son utilisation. Toutes ces informations sont données suivant la plus grande objectivité, mais
sans garantie de notre part exprimée ou implicite.
Cette fiche technique peut déjà, à ce moment précis, être révisée pour des raisons liées à la législation, à la
disponibilité des composants, ou à des expériences nouvellement acquises. La dernière version de cette fiche
technique, qui est la seule valable, vous sera envoyée sur simple demande, ou peut être trouvée sur notre site
Internet : www.crcind.com.
Nous vous recommandons de vous enregistrer sur notre site Internet pour ce produit, afin de recevoir
automatiquement chaque dernière version future.
Version : 10535 02 1200 03
Date : 29 september 2003
CRC Industries Europe BVBA
Touwslagerstraat 1 – 9240 Zele - Belgium
Tel (32) (0) 52/45.60.11 Fax (32) (0) 52/45.00.34
www.crcind.com
FICHE TECHNIQUE
1/3
Dusters
Dust Off 67, Dust Off 360, Jet Clean 360, Dust Off HF
Ref. : 20575; 20576; 20812; 20855,
1. DESCRIPTION GENERALE
Grâce à un jet de gaz pressurisé, sec et inerte ces produits sèchent et dépoussièrent.
2. CARACTERISTOQUES
Les produits sont un mélange de gaz liquides sous pression, qui fonctionne à la fois comme
propulseur et produit actif. Le jet de gaz sec et inerte, agit comme de l’air comprimé. Il enlève
rapidement poussières et autres contaminants secs d’instruments délicats, d’endroits
d’accès difficile ou d’équipement électrique et électronique. Les produits éliminent les
pannes dues à l’humidité (eau; huile,…) incluse dans la poussière et la saleté. Ces
dépoussiérants sont essentiels pour les opérations de nettoyage où les nettoyants à base de
solvants ne sont pas conseillés. Ils nettoient rapidement et sans danger, n’attaquent ni
matières plastiques, ni composants sensitifs. Ne laissent ni résidu, ni condensation.
Remplacent avantageusement, où possible, le nettoyage laborieux et coûteux à l’air
comprimé. Les dépoussiérants peuvent être employés pour écarter les poussières, là où les
méthodes conventionnelles ne conviennent pas : équipement électrique, PCB’s,
connections de câbles, équipement de traitement de données et de communication,
ensembles micro-miniaturisés, horloges et instruments de précision, vidéo & caméras,
dispositifs optiques et lentes, …
3. UTILISATIONS
Dust Off 67
Dépoussiérant universel.
Equipé d’une valve normale, bouton-poussoir et tube-rallonge.
L’aérosol doit être tenu droit.
Disponible en 200 ml net (270 ml brut) et 400 ml net (520 ml brut).
Dust Off 360
Dépoussiérant universel, peut être employé tête en bas.
Equipé d’une valve normale, bouton-poussoir et tube-rallonge.
L’aérosol peut être utilisé en position droite mais également renversé.
Disponible en 200 ml net (520 ml brut).
Jet Clean 360
Dépoussiérant pour emploi renversé, pour une application précise.
Muni d’une valve spécial avec embout fileté.
Une valve spéciale pour un jet précis est également disponible comme pièce détachée.
L’aérosol peut être utilisé dans une position droite ou renversée.
Disponible en 200 ml net (520 ml brut)
Dust Off HF
Dépoussiérant grand débit, conçu pour des applications haute performance.
Equipé d’une valve/boutton-poussoir qui permet un soufflement très puissant.
L’aérosol ne peut être employé qu’en position droite.
Disponible en 300 ml net (520 ml brut).
CRC Industries Europe BVBA
Touwslagerstraat 1 – 9240 Zele - Belgium
Tel (32) (0) 52/45.60.11 Fax (32) (0) 52/45.00.34
www.crcind.com
FICHE TECHNIQUE
2/3
Dusters
Dust Off 67, Dust Off 360, Jet Clean 360, Dust Off HF
Ref. : 20575; 20855, 20574, 20576
4. INSTRUCTIONS
Instruction Generale:
Vaporiser le gaz sur les objets et surfaces à nettoyer. Le meilleur résultat est obtenu par
pressions brèves. Après une utilisation continue, attendre quelques minutes, afin de rétablir
la pression interne dans l’aérosol et continuer l’application. Ne pas secouer ou remuer
l’aérosol pendant l’application.
Dust Off 67
Utiliser le tube-rallonge pour les endroits d’accès difficile.
Tenir l’aérosol droit durant l’application (ne pas incliner de plus de 30°).
Dust Off 360
Utiliser le tube-rallonge pour les endroits d’accès difficile.
Vaporiser en position droite ou tête en bas (ne pas utiliser horizontalement).
Jet Clean 360
Ajuster le pistolet de précision (peut être obtenu comme pièce détachée).
Vaporiser en position droite ou tête en bas (ne pas utiliser horizontalement).
Dust Off HF
Tenir l’aérosol droit durant l’application (ne pas incliner de plus de 30°).
Une fiche de sécurité selon la directive EU 91/155/EEC et ses amendements est
disponible pour tous les produits CRC.
5. DONNEES TYPIQUES DU PRODUIT (sans le gaz propulseur)
Densité @ 20°C Aérosol (gaz liquéfié) : 1,01 g/cm 3
Test d’extension de flamme (FEA 607) : Négative (**)
Fl amabilité ( FEA x 610 200 L) : Convient (> 60s) (**)
Pression @ 20°C : 420 kPa
Débit
Dust Off 67 : 17,1 g/10s
Dust Off 360 : 17,1 g/10s
Jet Clean 360 : 19,1 g/10s
Dust Off HF : 94,4 g/10s
CRC Industries Europe BVBA
Touwslagerstraat 1 – 9240 Zele - Belgium
Tel (32) (0) 52/45.60.11 Fax (32) (0) 52/45.00.34
www.crcind.com
FICHE TECHNIQUE
3/3
Dusters
Dust Off 67, Dust Off 360, Jet Clean 360, Dust Off HF
Ref. : 20575; 20855, 20574, 20576
6. CONDITIONNEMENT
Uniquement en aérosol, voir page précédente : données typique et applications.
** Le produit liquide contient max 7 % de matières inflammable, mais le mélange des vapeurs est ininflammable
celons les méthodes de tests indiquées.
Toutes les données dans cette publication sont basées sur l'expérience et les tests de laboratoire. Vu l’importante
variété des conditions et des appareillages employés, ainsi que des facteurs humains imprévisibles qui peuvent
avoir une influence importante sur les résultats de l’application, nous vous conseillons de vérifier la compatibilité
du produit avant son utilisation. Toutes ces informations sont données suivant la plus grande objectivité, mais
sans garantie de notre part exprimée ou implicite.
Cette fiche technique peut déjà, à ce moment précis, être révisée pour des raisons liées à la législation, à la
disponibilité des composants, ou à des expériences nouvellement acquises. La dernière version de cette fiche
technique, qui est la seule valable, vous sera envoyée sur simple demande, ou peut être trouvée sur notre site
Internet : www.crcind.com.
Nous vous recommandons de vous enregistrer sur notre site Internet pour ce produit, afin de recevoir
automatiquement chaque dernière version future.
Version : 20575 02 1003 01
Date : 23 August 2006
Pa
rt of Ant Group Ltd
Silica Gel MSDS
Order Now www.antistat.co.uk t +44 (0) 1473 836 200
Component Packaging
Silica Gel
Silica-gel is a high-activity sorbing material, the outcome of chemical reaction of sodium silicate and sulfuric acid, ageing and sour bathing process. Silica-gel is an amorphous substance. It’s molecular formula is mSiO2.nH2O. It features a stable chemical property and never reacts with any substance except strong alkali and hydrofuoric acid.
PROPERTY PARAMETERS
QUALITY ITEMS
CRITERIA (Test methods JIS-Z0701)
A: Bulk density
>750g/L
B: Loss on drying
<3%
C: Moisture absorption rate
RH=20%
>8%
RH=40%
>20%
RH=80%
>30%
PH
4--8
Specific resistance Ohm* cm
>3000
INGREDIENTS
NAME
PERCENTAGE (%)
SiO2
99.6
Na2O
0.17
Fe2O3
0.02
MgO
0.01
CaO
0.04
A12O3
0.16
HARMFUL ELEMENTS
RATE
Cd
<2ppm
Pb
<2ppm
Hg
<2ppm
Cr(VI)
<2ppm
PBBS
<5ppm
PBDES
<5ppm
DOSAGE
VOLUME
MIN DOSAGE
0.1------1L
1------2g
1------10L
2------20g
10------100L
20------200g
100------1000L
200------1600g
PACKAGING
Weight
Packs are available from 1g to 1kg.
Packaging materials
Non-woven fabrics
PRINTING
The packages are printed in Chinese, English, Japanese and French.
STORAGE
Silica-gel should be kept sealed when not in use.
1.0
REV
2014-03-24
DATE
SSt
BY
CSo
CHECKED
Würth Elektronik eiSos GmbH & Co. KG
EMC & Inductive Solutions
Max-Eyth-Str. 1
74638 Waldenburg
Germany
Tel. +49 (0) 79 42 945 - 0
www.we-online.com
eiSos@we-online.com
DESCRIPTION
WE-WPCC Wireless Power Charging
Receiver Coil
Order.- No.
760308102210
SIZE
A4
Size: 3737
A Dimensions: [mm] B Recommended hole pattern: [mm]
C Schematic:
D Electrical Properties:
Properties
Inductance
Q-factor
Rated current
Saturation current
DC Resistance
DC Resistance
Self resonant frequency
Test conditions
125 kHz/ 10 mA
125 kHz/ 10 mA
ΔT = 40 K
@ 20°C
@ 20°C
L
Q
IR
Isat
RDC
RDC
fres
Value
7.5
50
3.0
6.0
0.15
0.2
22
Unit
μH
A
A
Ω
Ω
MHz
Tol.
±10%
typ.
max.
typ.
typ.
max.
E General information:
It is recommended that the temperature of the part does
not exceed +105°C under worst case conditions.
•Storage Temperature: -20°C to 60°C
•Operating Temperature: -20°C to 105°C
•Test conditions of Electrical Properties: 20°C, 33% RH
if not specified differently
This electronic component has been designed and developed for usage in general electronic equipment only. This product is not authorized for use in equipment where a higher safety standard and reliability standard is especially required or where a failure of the product is reasonably expected to cause severe personal injury or death, unless the parties have executed an agreement specifically governing such use.
Moreover Würth Elektronik eiSos GmbH & Co KG products are neither designed nor intended for use in areas such as military, aerospace, aviation, nuclear control, submarine, transportation (automotive control, train control, ship control), transportation signal, disaster prevention, medical, public information network etc.. Würth Elektronik eiSos GmbH & Co KG must be informed about the intent of such usage before
the design-in stage. In addition, sufficient reliability evaluation checks for safety must be performed on every electronic component which is used in electrical circuits that require high safety and reliability functions or performance.
ARALDITE® 2014-1
SAFETY DATA SHEET
Product name
ARALDITE® 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
:
1.1 Product identifier
1.3 Details of the supplier of the safety data sheet
e-mail address of person
responsible for this SDS
: Global_Product_EHS_AdMat@huntsman.com
Product description : Not available.
1.2 Relevant identified uses of the substance or mixture and uses advised against
SECTION 1: Identification of the substance/mixture and of the
company/undertaking
Product code : 00057058
1.4 Emergency telephone number
Supplier
Telephone number : EUROPE: +32 35 75 1234
France ORFILA: +33(0)145425959
ASIA: +65 6336-6011
China: +86 20 39377888
Australia: 1800 786 152
New Zealand: 0800 767 437
USA: +1/800/424.9300
2-Component Product use : adhesive system
Supplier : Huntsman Advanced Materials (Europe)BVBA
Everslaan 45
3078 Everberg / Belgium
Tel.: +41 61 299 20 41
Fax: +41 61 299 20 40
Classification Xi; R41, R38
R43
N; R51/53
:
Human health hazards : Risk of serious damage to eyes. Irritating to skin. May cause sensitisation by skin
contact.
Environmental hazards : Toxic to aquatic organisms, may cause long-term adverse effects in the aquatic
environment.
See Section 11 for more detailed information on health effects and symptoms.
SECTION 2: Hazards identification
2.1 Classification of the substance or mixture
Product definition : Working pack (preparation)
See Section 16 for the full text of the R phrases or H statements declared above.
Classification according to Directive 1999/45/EC [DPD]
The product is classified as dangerous according to Directive 1999/45/EC and its amendments.
2.2 Label elements
Hazard symbol or symbols :
Date of issue / Date of revision : 3 August 2011 1/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
1
2/17
SECTION 2: Hazards identification
Other hazards which do :
not result in classification
Not available.
Containers to be fitted
with child-resistant
fastenings
Not applicable.
Tactile warning of danger Not applicable.
:
:
Special packaging requirements
Safety phrases S26- In case of contact with eyes, rinse immediately with plenty of water and seek
medical advice.
S39- Wear eye/face protection.
S61- Avoid release to the environment. Refer to special instructions/safety data
sheet.
R41- Risk of serious damage to eyes.
R38- Irritating to skin.
R43- May cause sensitisation by skin contact.
R51/53- Toxic to aquatic organisms, may cause long-term adverse effects in the
aquatic environment.
Risk phrases
Hazardous ingredients
:
:
:
Irritant, Dangerous for the environment
reaction product: bisphenol A-(epichlorhydrin); epoxy resin (number average
molecular weight < 700)
bisphenol F-epoxy resin
butanedioldiglycidyl ether
N(3-dimethylaminopropyl)-1,3-propylenediamine
Indication of danger :
2.3 Other hazards
Supplemental label
elements
: Contains epoxy constituents. See information supplied by the manufacturer.
Substance/mixture : Working pack (preparation)
Product/ingredient Identifiers 67/548/EEC
name
SECTION 3: Composition/information on ingredients
reaction product:
bisphenol A-
(epichlorhydrin); epoxy
resin (number average
molecular weight <
700)
REACH #: 01-
2119456619-26
CAS: 25068-38-6
13 - 30 Xi; R36/38
R43
N; R51/53
Skin Irrit. 2, H315
Eye Irrit. 2, H319
Skin Sens. 1, H317
Aquatic Chronic 2,
H411
[1]
bisphenol F-epoxy
resin
REACH #: 01-
2119454392-40
CAS: 9003-36-5
3 - 7 Xi; R36/38
R43
N; R51/53
Skin Irrit. 2, H315
Eye Irrit. 2, H319
Skin Sens. 1, H317
Aquatic Chronic 2,
H411
[1]
butanedioldiglycidyl
ether
REACH #: 01-
2119494060-45
CAS: 2425-79-8
1 - 3 Xn; R20/21
Xi; R36/38
R43
R52/53
Acute Tox. 4, H312
Acute Tox. 4, H332
Skin Irrit. 2, H315
Eye Irrit. 2, H319
Skin Sens. 1, H317
[1]
N(3-
dimethylaminopropyl)-
1,3-propylenediamine
CAS: 10563-29-8 1 - 3 Xn; R21/22
C; R34
R43
Acute Tox. 4, H302
Acute Tox. 4, H312
Skin Corr. 1B, H314
Eye Dam. 1, H318
[1]
% Regulation (EC) No. Type
1272/2008 [CLP]
Classification
Date of issue / Date of revision : 3 August 2011 2/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
1
3/17
SECTION 3: Composition/information on ingredients
Occupational exposure limits, if available, are listed in Section 8.
There are no additional ingredients present which, within the current knowledge of the supplier and in the
concentrations applicable, are classified as hazardous to health or the environment and hence require reporting in this
section.
Skin Sens. 1, H317
terephthalic acid
diglycidylester
CAS: 7195-44-0 0.1 - 1 Xi; R36/38
R43
N; R51/53
Skin Irrit. 2, H315
Eye Irrit. 2, H319
Skin Sens. 1, H317
Aquatic Chronic 2,
H411
[1]
trimellitic acid
triglycidylester
CAS: 7237-83-4 0.1 - 1 Xi; R36/38
R43
N; R51/53
Skin Irrit. 2, H315
Eye Irrit. 2, H319
Skin Sens. 1, H317
Aquatic Chronic 2,
H411
[1]
See section 16 for
the full text of the Rphrases
declared
above
See Section 16 for the
full text of the H
statements declared
above.
[1] Substance classified with a health or environmental hazard
[2] Substance with a workplace exposure limit
[3] Substance meets the criteria for PBT according to Regulation (EC) No. 1907/2006, Annex XIII
[4] Substance meets the criteria for vPvB according to Regulation (EC) No. 1907/2006, Annex XIII
Type
Wash out mouth with water. Remove dentures if any. Remove victim to fresh air
and keep at rest in a position comfortable for breathing. If material has been
swallowed and the exposed person is conscious, give small quantities of water to
drink. Stop if the exposed person feels sick as vomiting may be dangerous. Do not
induce vomiting unless directed to do so by medical personnel. If vomiting occurs,
the head should be kept low so that vomit does not enter the lungs. Get medical
attention if adverse health effects persist or are severe. Never give anything by
mouth to an unconscious person. If unconscious, place in recovery position and get
medical attention immediately. Maintain an open airway. Loosen tight clothing such
as a collar, tie, belt or waistband.
Skin contact
Get medical attention immediately. Immediately flush eyes with plenty of water,
occasionally lifting the upper and lower eyelids. Check for and remove any contact
lenses. Continue to rinse for at least 10 minutes. Chemical burns must be treated
promptly by a physician.
Flush contaminated skin with plenty of water. Remove contaminated clothing and
shoes. Wash contaminated clothing thoroughly with water before removing it, or
wear gloves. Continue to rinse for at least 10 minutes. Get medical attention. In the
event of any complaints or symptoms, avoid further exposure. Wash clothing before
reuse. Clean shoes thoroughly before reuse.
4.1 Description of first aid measures
Remove victim to fresh air and keep at rest in a position comfortable for breathing. If
not breathing, if breathing is irregular or if respiratory arrest occurs, provide artificial
respiration or oxygen by trained personnel. It may be dangerous to the person
providing aid to give mouth-to-mouth resuscitation. Get medical attention if adverse
health effects persist or are severe. If unconscious, place in recovery position and
get medical attention immediately. Maintain an open airway. Loosen tight clothing
such as a collar, tie, belt or waistband. In case of inhalation of decomposition
products in a fire, symptoms may be delayed. The exposed person may need to be
kept under medical surveillance for 48 hours.
Ingestion
Inhalation
Eye contact
:
:
:
:
SECTION 4: First aid measures
Date of issue / Date of revision : 3 August 2011 3/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
1
4/17
SECTION 4: First aid measures
Notes to physician In case of inhalation of decomposition products in a fire, symptoms may be delayed.
The exposed person may need to be kept under medical surveillance for 48 hours.
:
Specific treatments
Protection of first-aiders : No action shall be taken involving any personal risk or without suitable training. It
may be dangerous to the person providing aid to give mouth-to-mouth resuscitation.
Wash contaminated clothing thoroughly with water before removing it, or wear
gloves.
4.2 Most important symptoms and effects, both acute and delayed
Potential acute health effects
Inhalation : Exposure to decomposition products may cause a health hazard. Serious effects
may be delayed following exposure.
Irritating to Ingestion : mouth, throat and stomach.
Skin contact : Irritating to skin. May cause sensitisation by skin contact.
Eye contact : Severely irritating to eyes. Risk of serious damage to eyes.
Over-exposure signs/symptoms
Skin contact
Ingestion
Inhalation No specific data.
No specific data.
Adverse symptoms may include the following:
irritation
redness
:
:
:
Eye contact : Adverse symptoms may include the following:
pain or irritation
watering
redness
4.3 Indication of any immediate medical attention and special treatment needed
: Symptomatic treatment and supportive therapy as indicated. Following severe
exposure the patient should be kept under medical review for at least 48 hours.
Hazardous thermal
decomposition products
Hazards from the
substance or mixture
Decomposition products may include the following materials:
carbon dioxide
carbon monoxide
nitrogen oxides
sulfur oxides
metal oxide/oxides
In a fire or if heated, a pressure increase will occur and the container may burst.
Use an extinguishing agent suitable for the surrounding fire.
5.1 Extinguishing media
:
:
None known.
Suitable extinguishing
media
:
Unsuitable extinguishing
media
:
SECTION 5: Firefighting measures
5.2 Special hazards arising from the substance or mixture
5.3 Advice for firefighters
Date of issue / Date of revision : 3 August 2011 4/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
1
5/17
SECTION 5: Firefighting measures
Promptly isolate the scene by removing all persons from the vicinity of the incident if
there is a fire. No action shall be taken involving any personal risk or without suitable
training. This material is toxic to aquatic organisms. Fire water contaminated with
this material must be contained and prevented from being discharged to any
waterway, sewer or drain.
Fire-fighters should wear appropriate protective equipment and self-contained
breathing apparatus (SCBA) with a full face-piece operated in positive pressure
mode. Clothing for fire-fighters (including helmets, protective boots and gloves)
conforming to European standard EN 469 will provide a basic level of protection for
chemical incidents.
Special protective
equipment for fire-fighters
:
Special precautions for
fire-fighters
:
6.2 Environmental
precautions
Stop leak if without risk. Move containers from spill area. Approach the release
from upwind. Prevent entry into sewers, water courses, basements or confined
areas. Wash spillages into an effluent treatment plant or proceed as follows.
Contain and collect spillage with non-combustible, absorbent material e.g. sand,
earth, vermiculite or diatomaceous earth and place in container for disposal
according to local regulations. Dispose of via a licensed waste disposal contractor.
Contaminated absorbent material may pose the same hazard as the spilt product.
Avoid dispersal of spilt material and runoff and contact with soil, waterways, drains
and sewers. Inform the relevant authorities if the product has caused environmental
pollution (sewers, waterways, soil or air). Water polluting material. May be harmful
to the environment if released in large quantities.
Large spill :
Stop leak if without risk. Move containers from spill area. Dilute with water and mop
up if water-soluble. Alternatively, or if water-insoluble, absorb with an inert dry
material and place in an appropriate waste disposal container. Dispose of via a
licensed waste disposal contractor.
Small spill :
6.3 Methods and materials for containment and cleaning up
SECTION 6: Accidental release measures
6.1 Personal precautions, protective equipment and emergency procedures
For non-emergency
personnel
:
For emergency responders :
6.4 Reference to other
sections
See Section 1 for emergency contact information.
See Section 8 for information on appropriate personal protective equipment.
See Section 13 for additional waste treatment information.
No action shall be taken involving any personal risk or without suitable training.
Evacuate surrounding areas. Keep unnecessary and unprotected personnel from
entering. Do not touch or walk through spilt material. Avoid breathing vapour or
mist. Provide adequate ventilation. Wear appropriate respirator when ventilation is
inadequate. Put on appropriate personal protective equipment.
If specialised clothing is required to deal with the spillage, take note of any
information in Section 8 on suitable and unsuitable materials. See also Section 8 for
additional information on hygiene measures.
:
:
SECTION 7: Handling and storage
The information in this section contains generic advice and guidance. The list of Identified Uses in Section 1 should be
consulted for any available use-specific information provided in the Exposure Scenario(s).
7.1 Precautions for safe handling
Protective measures : Put on appropriate personal protective equipment (see Section 8). Persons with a
history of skin sensitization problems should not be employed in any process in
which this product is used. Do not get in eyes or on skin or clothing. Do not ingest.
Avoid breathing vapour or mist. Avoid release to the environment. Refer to special
instructions/safety data sheet. Keep in the original container or an approved
alternative made from a compatible material, kept tightly closed when not in use.
Empty containers retain product residue and can be hazardous. Do not reuse
container.
Date of issue / Date of revision : 3 August 2011 5/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
1
6/17
SECTION 7: Handling and storage
Store between the following temperatures: 2 to 40°C (35.6 to 104°F). Store in
accordance with local regulations. Store in original container protected from direct
sunlight in a dry, cool and well-ventilated area, away from incompatible materials
(see section 10) and food and drink. Keep container tightly closed and sealed until
ready for use. Containers that have been opened must be carefully resealed and
kept upright to prevent leakage. Do not store in unlabelled containers. Use
appropriate containment to avoid environmental contamination.
Advice on general
occupational hygiene
:
7.2 Conditions for safe
storage, including any
incompatibilities
7.3 Specific end use(s)
Recommendations :
Industrial sector specific :
solutions
Not available.
Not available.
Eating, drinking and smoking should be prohibited in areas where this material is
handled, stored and processed. Workers should wash hands and face before
eating, drinking and smoking. Remove contaminated clothing and protective
equipment before entering eating areas. See also Section 8 for additional
information on hygiene measures.
:
Storage hazard class
Huntsman Advanced
Materials
: Storage class 10, Environmentally hazardous liquids
Recommended monitoring
procedures
Occupational exposure limits
If this product contains ingredients with exposure limits, personal, workplace
atmosphere or biological monitoring may be required to determine the effectiveness
of the ventilation or other control measures and/or the necessity to use respiratory
protective equipment. Reference should be made to European Standard EN 689 for
methods for the assessment of exposure by inhalation to chemical agents and
national guidance documents for methods for the determination of hazardous
substances.
:
No exposure limit value known.
No DELs available.
Predicted effect concentrations
No PECs available.
SECTION 8: Exposure controls/personal protection
The information in this section contains generic advice and guidance. The list of Identified Uses in Section 1 should be
consulted for any available use-specific information provided in the Exposure Scenario(s).
8.1 Control parameters
Derived effect levels
Workplace exposure limits (for total dust and inhalable quartz dust) must be complied with. If this is not possible,
then suitable dust masks must be worn.
W A R N I N G ! This product contains quartz, which has been classified by IARC as carcinogenic for humans
(Group 1), and which can cause silicosis and lung cancer following exposure to respirable dust. It is therefore
important to take particular care to avoid inhalation exposure when mechanically processing cured material (e.g.
grinding, sanding, sawing).
QUARTZ (CAS RN 14808-60-7):
United Kingdom: TWA: 0.1 mg/m³ 8 hour(s). Form: respirable dust
Ireland: OELV-8hr: 0.1 mg/m³ 8 hour(s). Form: respirable dust
Switzerland: TWA: 0.15 mg/m³ 8 hour(s). Form: respirable dust
Australia: TWA: 0.1 mg/m³ 8 hour(s)
Date of issue / Date of revision : 3 August 2011 6/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
1
7/17
SECTION 8: Exposure controls/personal protection
Hand protection
In case of inadequate ventilation wear respiratory protection. Respirator selection
must be based on known or anticipated exposure levels, the hazards of the product
and the safe working limits of the selected respirator.
Chemical-resistant, impervious gloves complying with an approved standard should
be worn at all times when handling chemical products if a risk assessment indicates
this is necessary.
Safety eyewear complying with an approved standard should be used when a risk
assessment indicates this is necessary to avoid exposure to liquid splashes, mists
or dusts.
Eye/face protection
Respiratory protection :
:
:
Skin protection
Personal protective equipment for the body should be selected based on the task
being performed and the risks involved and should be approved by a specialist
before handling this product.
:
Environmental exposure
controls
: Emissions from ventilation or work process equipment should be checked to ensure
they comply with the requirements of environmental protection legislation. In some
cases, fume scrubbers, filters or engineering modifications to the process
equipment will be necessary to reduce emissions to acceptable levels.
Appropriate engineering
controls
: No special ventilation requirements. Good general ventilation should be sufficient to
control worker exposure to airborne contaminants. If this product contains
ingredients with exposure limits, use process enclosures, local exhaust ventilation or
other engineering controls to keep worker exposure below any recommended or
statutory limits.
Wash hands, forearms and face thoroughly after handling chemical products, before
eating, smoking and using the lavatory and at the end of the working period.
Appropriate techniques should be used to remove potentially contaminated clothing.
Contaminated work clothing should not be allowed out of the workplace. Wash
contaminated clothing before reusing. Ensure that eyewash stations and safety
showers are close to the workstation location.
8.2 Exposure controls
Hygiene measures :
Individual protection measures
Body protection :
Other skin protection Appropriate footwear and any additional skin protection measures should be
selected based on the task being performed and the risks involved and should be
approved by a specialist before handling this product.
Ethyl Vinyl Alcohol Laminate (EVAL), butyl rubber
neoprene, Material of gloves for nitrile rubber
short term/splash
application
(10min480min):
Physical state Liquid. [Paste.]
Odour Not available.
Colour Not available.
Odour threshold Not available.
:
:
:
:
9.1 Information on basic physical and chemical properties
Appearance
SECTION 9: Physical and chemical properties
Date of issue / Date of revision : 3 August 2011 7/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
1
8/17
SECTION 9: Physical and chemical properties
Not available.
Melting point/freezing point
Initial boiling point and boiling
range
Vapour pressure
Relative density
Vapour density
Solubility(ies)
Not available.
Not available.
Not available.
Not available.
pH
Evaporation rate Not available.
Auto-ignition temperature
Flash point
Not available.
Closed cup: >100°C [DIN 51758 EN 22719 (Pensky-Martens Closed Cup)]
Not available.
Not available.
Not available.
Not available.
Viscosity Not available.
Partition coefficient: noctanol/
water
Upper/lower flammability or
explosive limits
Explosive properties
:
:
:
:
:
:
:
:
:
:
:
:
:
Oxidising properties : Not available.
9.2 Other information
Burning time Not applicable.
Burning rate Not applicable.
:
:
Decomposition temperature : Not available.
Flammability (solid, gas) : Not available.
Density : 1.4 g/cm3 [20°C (68°F)]
Water solubility :
10.6 Hazardous
decomposition products
10.4 Conditions to avoid No specific data.
Under normal conditions of storage and use, hazardous decomposition products
should not be produced.
10.2 Chemical stability The product is stable.
No specific data.
:
:
:
10.5 Incompatible materials :
10.3 Possibility of
hazardous reactions
: Under normal conditions of storage and use, hazardous reactions will not occur.
SECTION 10: Stability and reactivity
10.1 Reactivity : No specific test data related to reactivity available for this product or its ingredients.
Date of issue / Date of revision : 3 August 2011 8/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
1
9/17
Acute toxicity
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
LC0 Inhalation Vapour Rat - Male 0.00001 ppm 5 hours
LD50 Dermal Rat - Male,
Female
>2000 mg/kg -
LD50 Oral Rat - Female >2000 mg/kg -
bisphenol F-epoxy resin LD50 Dermal Rat - Male,
Female
>2000 mg/kg -
LD50 Oral Rat - Male,
Female
>5000 mg/kg -
butanedioldiglycidyl ether LD50 Dermal Rat - Male,
Female
>2150 mg/kg -
LD50 Oral Rat - Male,
Female
1163 mg/kg -
N(3-dimethylaminopropyl)-
1,3-propylenediamine
LD50 Dermal Rabbit 1310 mg/kg -
LD50 Oral Rat 1670 mg/kg -
Product/ingredient name Endpoint Species Result Exposure
Irritation/Corrosion
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
OECD 404 Acute Dermal
Irritation/Corrosion
Rabbit Mild irritant
OECD 405 Acute Eye Irritation/Corrosion Rabbit Mild irritant
bisphenol F-epoxy resin OECD 405 Acute Eye Irritation/Corrosion Rabbit Non-irritant.
OECD 404 Acute Dermal
Irritation/Corrosion
Rabbit Mild irritant
butanedioldiglycidyl ether OECD 404 Acute Dermal
Irritation/Corrosion
Rabbit Non-irritant.
OECD 405 Acute Eye Irritation/Corrosion Rabbit Severe irritant
Product/ingredient name Test Result
Conclusion/Summary :
Skin : reaction product: bisphenol A-(epichlorhydrin); epoxy resin (number average
molecular weight < 700): Slightly irritating to the skin.
bisphenol F-epoxy resin: Slightly irritating to the skin.
butanedioldiglycidyl ether: Non-irritating to the skin.
Eyes : reaction product: bisphenol A-(epichlorhydrin); epoxy resin (number average
molecular weight < 700): Slightly irritating to the eyes.
bisphenol F-epoxy resin: Non-irritating to the eyes.
butanedioldiglycidyl ether: Severely irritating to eyes.
Not available.
Sensitiser
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
OECD 429 Skin
Sensitisation:
Local Lymph
Node Assay
skin Mouse Sensitising
bisphenol F-epoxy resin OECD 429 Skin
Sensitisation:
Local Lymph
Node Assay
skin Mouse Sensitising
butanedioldiglycidyl ether OECD 406 Skin
Sensitization
skin Guinea pig Sensitising
Product/ingredient name Test Route of
exposure
Result
Species
SECTION 11: Toxicological information
11.1 Information on toxicological effects
Species
Date of issue / Date of revision : 3 August 2011 9/17
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Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
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3 August 2011
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SECTION 11: Toxicological information
Carcinogenicity
reaction product:
bisphenol A-
(epichlorhydrin); epoxy
resin (number average
molecular weight <
700)
OECD 453 Combined Chronic
Toxicity/Carcinogenicity
Studies
Rat 2 years; 7
days per
week
Negative Oral -
OECD 453 Combined Chronic
Toxicity/Carcinogenicity
Studies
Rat 2 years; 5
days per
week
Negative Dermal -
OECD 453 Combined Chronic
Toxicity/Carcinogenicity
Studies
Mouse 2 years; 3
days per
week
Negative Dermal -
Product/ingredient
name
Test Species Exposure Result
Mutagenicity
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
OECD 471 Bacterial Reverse
Mutation Test
Positive
OECD 476 In vitro Mammalian Cell
Gene Mutation Test
Positive
OECD 478 Genetic Toxicology:
Rodent Dominant Lethal Test
Negative
EPA OPPTS Negative
bisphenol F-epoxy resin OECD 471 Bacterial Reverse
Mutation Test
Positive
OECD 476 In vitro Mammalian Cell
Gene Mutation Test
Positive
OECD 473 In vitro Mammalian
Chromosomal Aberration Test
Positive
OECD 474 Mammalian Erythrocyte
Micronucleus Test
Negative
OECD 486 Unscheduled DNA
Synthesis (UDS) Test with
Mammalian Liver Cells in vivo
Negative
butanedioldiglycidyl ether OECD 471 Bacterial Reverse
Mutation Test
Positive
OECD 473 In vitro Mammalian
Chromosomal Aberration Test
Positive
OECD 474 Mammalian Erythrocyte
Micronucleus Test
Negative
Product/ingredient name Test Result
Conclusion/Summary : Not available.
Teratogenicity
Reproductive toxicity
Product/ingredient name Test Species Result/Result type Target
organs
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
OECD 416 Two-Generation
Reproduction Toxicity Study
Rat Oral: 540 mg/kg
NOEL :
-
bisphenol F-epoxy resin OECD 416 Two-Generation
Reproduction Toxicity Study
Rat Oral: 540 mg/kg
NOEL :
-
Conclusion/Summary : Not available.
Route of
exposure
Target
organs
Date of issue / Date of revision : 3 August 2011 10/17
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Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
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SECTION 11: Toxicological information
Potential chronic health effects
Potential acute health effects
Inhalation : Exposure to decomposition products may cause a health hazard. Serious effects
may be delayed following exposure.
Irritating to Ingestion : mouth, throat and stomach.
Skin contact : Irritating to skin. May cause sensitisation by skin contact.
Eye contact : Severely irritating to eyes. Risk of serious damage to eyes.
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
OECD 408 Repeated Dose
90-Day Oral Toxicity Study in
Rodents
NOAEL Subchronic
NOAEL
Oral
50 mg/kg -
OECD 411 Subchronic
Dermal Toxicity: 90-day Study
NOEL : Subchronic
NOEL :
Dermal
10 mg/kg -
OECD 411 Subchronic
Dermal Toxicity: 90-day Study
NOAEL Subchronic
NOAEL
Dermal
100 mg/kg -
bisphenol F-epoxy resin OECD 408 Repeated Dose NOAEL Sub- 250 mg/kg -
Product/ingredient name Test Result type Result Target organs
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
OECD 414 Prenatal Developmental
Toxicity Study
Rat - Female >540 mg/kg NOEL :
EPA CFR Rabbit -
Female
>300 mg/kg NOEL :
OECD 414 Prenatal Developmental
Toxicity Study
Rabbit -
Female
180 mg/kg NOAEL
bisphenol F-epoxy resin EPA CFR Rabbit -
Female
>300 mg/kg NOEL :
Product/ingredient name Test Species Result/Result type
Symptoms related to the physical, chemical and toxicological characteristics
Skin contact
Ingestion
Inhalation No specific data.
No specific data.
Adverse symptoms may include the following:
irritation
redness
:
:
:
Eye contact : Adverse symptoms may include the following:
pain or irritation
watering
redness
Information on the likely Not available.
routes of exposure
:
Delayed and immediate effects and also chronic effects from short and long term exposure
Short term exposure
Long term exposure
Potential immediate
effects
Potential delayed effects :
:
Potential immediate
effects
Potential delayed effects :
:
Not available.
Not available.
Not available.
Not available.
Date of issue / Date of revision : 3 August 2011 11/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
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Version :
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SECTION 11: Toxicological information
Once sensitized, a severe allergic reaction may occur when subsequently exposed
to very low levels.
General :
No known significant effects Carcinogenicity : or critical hazards.
Mutagenicity : No known significant effects or critical hazards.
Teratogenicity : No known significant effects or critical hazards.
90-Day Oral Toxicity Study in
Rodents
chronic
NOAEL
Oral
butanedioldiglycidyl ether OECD 407 Repeated Dose
28-day Oral Toxicity Study in
Rodents
NOAEL Subchronic
NOAEL
Oral
200 mg/kg -
Conclusion/Summary : Not available.
Developmental effects : No known significant effects or critical hazards.
Fertility effects : No known significant effects or critical hazards.
Other information : Not available.
12.1 Toxicity
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
- Acute EC50 72 hours
Static
Algae 9.4 mg/L
OECD 202 Daphnia sp. Acute
Immobilisation Test
Acute EC50 48 hours
Static
Daphnia 1.7 mg/L
- Acute IC50 3 hours
Static
Bacteria >100 mg/L
OECD 203 Fish, Acute
Toxicity Test
Acute LC50 96 hours
Static
Fish 1.5 mg/L
OECD 211 Daphnia Magna
Reproduction Test
Chronic NOEC 21 days
Semistatic
Daphnia 0.3 mg/L
bisphenol F-epoxy resin OECD 201 Alga, Growth
Inhibition Test
Acute EC50 72 hours
Static
Algae 1.8 mg/L
OECD OECD 202: Part I
(Daphnia sp., Acute
Immobilisation test)
Acute EC50 48 hours
Static
Daphnia 1.6 mg/L
- Acute IC50 3 hours
Static
Bacteria >100 mg/L
OECD 203 Fish, Acute
Toxicity Test
Acute LC50 96 hours
Semistatic
Fish 0.55 mg/L
OECD 211 Daphnia Magna
Reproduction Test
Chronic NOEC 21 days
Semistatic
Daphnia 0.3 mg/L
butanedioldiglycidyl ether OECD 202 Daphnia sp. Acute
Immobilisation Test
Acute EC50 24 hours
Static
Daphnia 75 mg/L
OECD 201 Alga, Growth
Inhibition Test
Acute EL50 72 hours
Static
Algae >160 mg/L
OECD 209 Activated Sludge,
Respiration Inhibition Test
Acute IC50 3 hours
Static
Bacteria >100 mg/L
OECD 203 Fish, Acute
Toxicity Test
Acute LC50 96 hours
Static
Fish 24 mg/L
Product/ingredient name Exposure Species Result
12.2 Persistence and degradability
SECTION 12: Ecological information
Test Endpoint
Date of issue / Date of revision : 3 August 2011 12/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
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SECTION 12: Ecological information
Mobility : Not available.
LogPow BCF Potential
12.3 Bioaccumulative potential
12.6 Other adverse effects No known significant effects or critical hazards.
Product/ingredient name
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
3.242 31 low
bisphenol F-epoxy resin 2.7 to 3.6 - high
butanedioldiglycidyl ether -0.269 - low
Product/ingredient name Aquatic half-life Photolysis Biodegradability
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
Fresh water 4.83 days
Fresh water 3.58 days
Fresh water 7.1 days
- Not readily
bisphenol F-epoxy resin - - Not readily
butanedioldiglycidyl ether - - Not readily
reaction product: bisphenol
A-(epichlorhydrin); epoxy
resin (number average
molecular weight < 700)
OECD Derived from OECD 301F
(Biodegradation Test)
28 days 5 %
bisphenol F-epoxy resin EU 28 days 0 %
butanedioldiglycidyl ether OECD 301F Ready Biodegradability -
Manometric Respirometry Test
28 days 43 %
Product/ingredient name Test Result
Conclusion/Summary : reaction product: bisphenol A-(epichlorhydrin); epoxy resin (number average
molecular weight < 700): Not readily biodegradable.
12.4 Mobility in soil
Soil/water partition
coefficient (KOC)
: Not available.
12.5 Results of PBT and vPvB assessment
:
12.7 Other ecological information
Period
Not applicable.
The generation of waste should be avoided or minimised wherever possible.
Significant quantities of waste product residues should not be disposed of via the
foul sewer but processed in a suitable effluent treatment plant. Dispose of surplus
and non-recyclable products via a licensed waste disposal contractor. Disposal of
this product, solutions and any by-products should at all times comply with the
requirements of environmental protection and waste disposal legislation and any
regional local authority requirements. Waste packaging should be recycled.
Incineration or landfill should only be considered when recycling is not feasible. This
Methods of disposal :
SECTION 13: Disposal considerations
The information in this section contains generic advice and guidance. The list of Identified Uses in Section 1 should be
consulted for any available use-specific information provided in the Exposure Scenario(s).
13.1 Waste treatment methods
Product
Date of issue / Date of revision : 3 August 2011 13/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
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14/17
SECTION 13: Disposal considerations
European waste catalogue (EWC)
Hazardous waste : Yes.
material and its container must be disposed of in a safe way. Care should be taken
when handling emptied containers that have not been cleaned or rinsed out. Empty
containers or liners may retain some product residues. Avoid dispersal of spilt
material and runoff and contact with soil, waterways, drains and sewers.
Packaging
Waste code Waste designation
Methods of disposal :
Special precautions :
07 02 08* other still bottoms and reaction residues
The generation of waste should be avoided or minimised wherever possible. Waste
packaging should be recycled. Incineration or landfill should only be considered
when recycling is not feasible.
This material and its container must be disposed of in a safe way. Care should be
taken when handling emptied containers that have not been cleaned or rinsed out.
Empty containers or liners may retain some product residues. Avoid dispersal of
spilt material and runoff and contact with soil, waterways, drains and sewers.
Environmentally hazardous substance, liquid, n.o.s. BISPHENOL A/F EPOXY
RESIN
9
III
Environmentally hazardous substance, liquid, n.o.s. (BISPHENOL A/F EPOXY
RESIN) Marine pollutant (reaction product: bisphenol A-(epichlorhydrin); epoxy
resin (number average molecular weight < 700), bisphenol F-epoxy resin)
9
III
Environmentally hazardous substance, liquid, n.o.s. (BISPHENOL A/F EPOXY
RESIN)
UN3082
9
not available not available
III
UN3082
UN3082
Hazard identification
number
90
Special provisions
274 335 601
Tunnel code
E
Emergency
schedules (EmS)
F-A, S-F
Passenger and
Cargo Aircraft
Quantity limitation:
450 L
Packaging
instructions: 964
Cargo Aircraft Only
Quantity limitation:
450 L
Packaging
SECTION 14: Transport information
ADR/RID IMDG IATA
14.1 UN number 14.2 UN proper shipping name
14.3 Transport
hazard class(es)
14.4 Packing
group
ADN/ADNR
Additional
information
14.5
Environmental
hazards
14.6 Special
precautions for
user
Yes. Yes. Yes.
Not available. Not available. Not available.
ADN/ADNR
IMDG
IATA
ADR/RID
Date of issue / Date of revision : 3 August 2011 14/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
3 August 2011
3 August 2011
MSDS no.
Version :
: 00057058
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15/17
SECTION 14: Transport information
instructions: 964
14.7 Transport in bulk
according to Annex II of
MARPOL 73/78 and the IBC
Code
: Not applicable.
National regulations
Other EU regulations
Annex XVII - Restrictions Not applicable.
on the manufacture,
placing on the market and
use of certain dangerous
substances, mixtures and
articles
:
Europe inventory : All components are listed or exempted.
Black List Chemicals : Not listed
Priority List Chemicals : Not listed
Integrated pollution
prevention and control
list (IPPC) - Air
: Not listed
Integrated pollution
prevention and control
list (IPPC) - Water
: Not listed
Chemical Weapons
Convention List Schedule I
Chemicals
: Not listed
Chemical Weapons
Convention List Schedule II
Chemicals
: Not listed
Chemical Weapons
Convention List Schedule III
Chemicals
: Not listed
International regulations
References : The provision of Safety Data Sheets comes under Regulation 6 of CHIP (CHIP is the
recognised abbreviation for the Chemicals Hazard Information and Packaging
Regulations). This is an addition to the Health and Safety at Work Act 1974.
SECTION 15: Regulatory information
15.1 Safety, health and environmental regulations/legislation specific for the substance or mixture
EU Regulation (EC) No. 1907/2006 (REACH)
Annex XIV - List of substances subject to authorisation
15.2 Chemical Safety
Assessment
This product contains substances for which Chemical Safety Assessments are still
required.
Substances of very high concern
:
None of the components are listed.
Date of issue / Date of revision : 3 August 2011 15/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
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MSDS no.
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Date of printing : 3 August 2011
R20/21- Harmful by inhalation and in contact with skin.
R21/22- Harmful in contact with skin and if swallowed.
R34- Causes burns.
R41- Risk of serious damage to eyes.
R38- Irritating to skin.
R36/38- Irritating to eyes and skin.
R43- May cause sensitisation by skin contact.
R51/53- Toxic to aquatic organisms, may cause long-term adverse effects in the
aquatic environment.
R52/53- Harmful to aquatic organisms, may cause long-term adverse effects in the
aquatic environment.
Full text of abbreviated R :
phrases
C - Corrosive
Xn - Harmful
Xi - Irritant
N - Dangerous for the environment
Full text of classifications :
[DSD/DPD]
Indicates information that has changed from previously issued version.
SECTION 16: Other information
Full text of abbreviated H
statements
:
Abbreviations and
acronyms
: ATE = Acute Toxicity Estimate
CLP = Classification, Labelling and Packaging Regulation [Regulation (EC) No.
1272/2008]
DNEL = Derived No Effect Level
EUH statement = CLP-specific Hazard statement
PNEC = Predicted No Effect Concentration
RRN = REACH Registration Number
Classification according to Regulation (EC) No. 1272/2008 [CLP/GHS]
Procedure used to derive the classification according to Regulation (EC) No. 1272/2008 [CLP/GHS]
Classification Justification
Skin Irrit. 2, H315 Expert judgment
Eye Dam. 1, H318 Expert judgment
Skin Sens. 1, H317 Expert judgment
Aquatic Chronic 2, H411 Expert judgment
Full text of classifications
[CLP/GHS]
:
H302 Harmful if swallowed.
H312 Harmful in contact with skin.
H314 Causes severe skin burns and eye damage.
H315 Causes skin irritation.
H317 May cause an allergic skin reaction.
H318 Causes serious eye damage.
H319 Causes serious eye irritation.
H332 Harmful if inhaled.
H411 Toxic to aquatic life with long lasting effects.
Acute Tox. 4, H302 ACUTE TOXICITY: ORAL - Category 4
Acute Tox. 4, H312 ACUTE TOXICITY: SKIN - Category 4
Acute Tox. 4, H332 ACUTE TOXICITY: INHALATION - Category 4
Aquatic Chronic 2, H411 AQUATIC TOXICITY (CHRONIC) - Category 2
Eye Dam. 1, H318 SERIOUS EYE DAMAGE/ EYE IRRITATION - Category 1
Eye Irrit. 2, H319 SERIOUS EYE DAMAGE/ EYE IRRITATION - Category 2
Skin Corr. 1B, H314 SKIN CORROSION/IRRITATION - Category 1B
Skin Irrit. 2, H315 SKIN CORROSION/IRRITATION - Category 2
Skin Sens. 1, H317 SKIN SENSITIZATION - Category 1
Skin Irrit. 2, H315
Eye Dam. 1, H318
Skin Sens. 1, H317
Aquatic Chronic 2, H411
MSDS no. : 00057058
Date of issue / Date of revision : 3 August 2011 16/17
ARALDITE 2014-1
Conforms to Regulation (EC) No. 1907/2006 (REACH), Annex II - United Kingdom (UK)
Date of printing :
Date of issue :
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3 August 2011
MSDS no.
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: 00057058
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SECTION 16: Other information
Date of issue/ Date of
revision
Version
Notice to reader
Date of previous issue
:
:
:
3 August 2011
No previous validation.
1
While the information and recommendations in this publication are to the best of our knowledge, information
and belief accurate at the date of publication, NOTHING HEREIN IS TO BE CONSTRUED AS A WARRANTY,
EXPRESS OR OTHERWISE.
IN ALL CASES, IT IS THE RESPONSIBILITY OF THE USER TO DETERMINE THE APPLICABILITY OF SUCH
INFORMATION AND RECOMMENDATIONS AND THE SUITABILITY OF ANY PRODUCT FOR ITS OWN
PARTICULAR PURPOSE.
THE PRODUCT MAY PRESENT HAZARDS AND SHOULD BE USED WITH CAUTION. WHILE CERTAIN HAZARDS
ARE DESCRIBED IN THIS PUBLICATION, NO GUARANTEE IS MADE THAT THESE ARE THE ONLY HAZARDS
THAT EXIST.
Hazards, toxicity and behaviour of the products may differ when used with other materials and are dependent
upon the manufacturing circumstances or other processes. Such hazards, toxicity and behaviour should be
determined by the user and made known to handlers, processors and end users.
ARALDITE® is a registered trademark of Huntsman Corporation or an affiliate thereof in one or more countries,
but not all countries.
NO PERSON OR ORGANIZATION EXCEPT A DULY AUTHORIZED HUNTSMAN EMPLOYEE IS AUTHORIZED TO
PROVIDE OR MAKE AVAILABLE DATA SHEETS FOR HUNTSMAN PRODUCTS. DATA SHEETS FROM
UNAUTHORIZED SOURCES MAY CONTAIN INFORMATION THAT IS NO LONGER CURRENT OR ACCURATE.
NO PART OF THIS DATA SHEET MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM, OR BY ANY
MEANS, WITHOUT PERMISSION IN WRITING FROM HUNTSMAN. ALL REQUESTS FOR PERMISSION TO
REPRODUCE MATERIAL FROM THIS DATA SHEET SHOULD BE DIRECTED TO HUNTSMAN, MANAGER,
PRODUCT SAFETY AT THE ABOVE ADDRESS.
Date of issue / Date of revision : 3 August 2011 17/17
1
®
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
8-Digit, Microprocessor-Compatible, LED
Display Decoder Driver
The Intersil ICM7228 display driver interfaces
microprocessors to an 8-digit, 7-segment, numeric LED
display. Included on chip are two types of 7-segment
decoder, multiplex scan circuitry, LED display segment
drivers, LED display digit drivers and an 8-byte static
memory as display RAM.
Data can be written to the ICM7228A and ICM7228B’s display
RAM in sequential 8-digit update or in single-digit update
format. Data is written to the ICM7228C display RAM in parallel
random access format. The ICM7228A and ICM7228C drive
common anode displays. The ICM7228B drives common
cathode displays. All versions can display the RAM data as
either Hexadecimal or Code B format. The ICM7228A and
ICM7228B incorporate a No Decode mode allowing each bit of
each digit's RAM word to drive individual display segments
resulting in independent control of all display segments. As a
result, bargraph and other irregular display segments and
formats can be driven directly by this chip.
The Intersil ICM7228 is an alternative to both the Maxim
ICM7218 and the Intersil ICM7218 display drivers. Notice that
the ICM7228A/B has an additional single digit access mode.
This could make the Intersil ICM7218A/B software incompatible
with ICM7228A/B operation.
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Improved 2nd Source to Maxim ICM7218
• Fast Write Access Time of 200ns
• Multiple Microprocessor Compatible Versions
• Hexadecimal, Code B and No Decode Modes
• Individual Segment Control with “No Decode” Feature
• Digit and Segment Drivers On-Chip
• Non-Overlapping Digits Drive
• Common Anode and Common Cathode LED Versions
• Low Power CMOS Architecture
• Single 5V Supply
Applications
• Instrumentation
• Test Equipment
• Hand Held Instruments
• Bargraph Displays
• Numeric and Non-Numeric Panel Displays
• High and Low Temperature Environments where LCD
Display Integrity is Compromised
Ordering Information
PART NUMBER PART MARKING
DATA ENTRY
PROTOCOL DISPLAY TYPE
TEMP. RANGE
(oC) PACKAGE PKG. DWG. #
ICM7228AIBI ICM7228AIBI Sequential Common Anode -40 to 85 28 Ld SOIC M28.3
ICM7228AIBIZ (Note) 7228AIBIZ Sequential Common Anode -40 to 85 28 Ld SOIC (Pb-free) M28.3
ICM7228AIPI ICM7228AIPI Sequential Common Anode -40 to 85 28 Ld PDIP E28.6
ICM7228AIPIZ (Note) ICM7228AIPI Sequential Common Anode -40 to 85 28 Ld PDIP* (Pb-free) E28.6
ICM7228BIBI ICM7228BIBI Sequential Common Cathode -40 to 85 28 Ld SOlC M28.3
ICM7228BIBIZ (Note) ICM7228BIBIZ Sequential Common Cathode -40 to 85 28 Ld SOlC (Pb-free) M28.3
ICM7228BIPI ICM7228BIPI Sequential Common Cathode -40 to 85 28 Ld PDIP E28.6
ICM7228BIPIZ (Note) ICM7228BIPIZ Sequential Common Cathode -40 to 85 28 Ld PDIP (Pb-free) E28.6
ICM7228CIBI ICM7228CIBI Random Common Anode -40 to 85 28 Ld SOlC M28.3
ICM7228CIBIZ (Note) ICM7228CIBIZ Random Common Anode -40 to 85 28 Ld SOlC (Pb-free) M28.3
ICM7228CIPI ICM7228CIPI Random Common Anode -40 to 85 28 Ld PDIP E28.6
ICM7228CIPIZ (Note) ICM7228CIPI Random Common Anode -40 to 85 28 Ld PDIP (Pb-free) E28.6
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Data Sheet December 6, 2005 FN3160.8
ICM7228
2
ICM7228
Pinouts
ICM7228A (PDIP, SOIC)
COMMON ANODE
TOP VIEW
ICM7228B (PDIP, SOIC)
COMMON CATHODE
TOP VIEW
ICM7228C (PDIP, SOIC)
COMMON ANODE
TOP VIEW
SEG c
SEG e
SEG b
DP
ID6 (HEXA/CODE B)
ID5 (DECODE)
ID7 (DATA COMING)
WRITE
MODE
ID4 (SHUTDOWN)
ID1
ID0
ID2
ID3
VSS
SEG g
SEG d
SEG f
DIGIT 3
DIGIT 7
VDD
DIGIT 8
DIGIT 5
DIGIT 2
DIGIT 1
SEG a
DIGIT 6
DIGIT 4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DIGIT 4
DIGIT 6
DIGIT 3
DIGIT 1
ID6 (HEXA/CODE B)
ID5 (DECODE)
ID7 (DATA COMING)
WRITE
MODE
ID4 (SHUTDOWN)
ID1
ID0
ID2
ID3
VSS
DIGIT 5
DIGIT 2
DIGIT 8
SEG g
SEG e
VDD
SEG d
SEG b
SEG a
DP
DIGIT 7
SEG f
SEG c
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SEG c
SEG e
SEG b
DP
DA0 (DIGIT ADDRESS 0)
DA1 (DIGIT ADDRESS 1)
ID7 (INPUT DP)
WRITE
HEXA/CODE B/SHUTDOWN
DA2 (DIGIT ADDRESS 2)
ID1
ID0
ID2
ID3
VSS
SEG g
SEG d
SEG f
DIGIT 3
DIGIT 7
VDD
DIGIT 8
DIGIT 5
DIGIT 2
DIGIT 1
SEG a
DIGIT 6
DIGIT 4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3
ICM7228
Functional Block Diagram
8 SEGMENT
DRIVERS
8 DIGIT
DRIVERS
DECODE
NO-DECODE
8-BYTE
STATIC
RAM
HEXADECIMAL/
CODE B
DECODER
MULTIPLEX
OSCILLATOR
WRITE ADDRESS
COUNTER
CONTROL
LOGIC
READ
ADDRESS, DIGIT
MULTIPLEXER
ICM7228A, ICM7228B
ID0 - ID7
INPUT
DATA
ID4 - ID7
CONTROL
INPUTS MODE WRITE
SHUTDOWN
HEXA/CODE B
DECODE
INTERDIGIT
BLANKING
DECIMAL
POINT
8
8
4 1 1
1
1
4
7
7
7
8
8
8
1
1
3
8 1
1
7
1
8 SEGMENT
DRIVERS
8 DIGIT
DRIVERS
8-BYTE
STATIC
RAM
HEXADECIMAL/
CODE B
DECODER
MULTIPLEX
OSCILLATOR
WRITE ADDRESS
COUNTER
THREE LEVEL
INPUT LOGIC
READ
ADDRESS
MULTIPLEXER
ICM7228C
WRITE
SHUTDOWN
INTERDIGIT
BLANKING
DECIMAL
POINT
1 5 1
1
4
7
8
8
8
5
8 1
1
1
DA0 - DA2
3
DIGIT
ADDRESS
ID0 - ID3
ID7
DATA INPUT
HEXADECIMAL/
CODE B/
SHUTDOWN
4
ICM7228
Absolute Maximum Ratings Thermal Information
Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V
Digit Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Segment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Input Voltage (Note 1) (Any Terminal) . . (VSS-0.3V)>1, then it can be simplified as follows:
From the above equation, it is shown that the system is a
single order system, which has a single pole located at
before the half switching frequency. Therefore, simple type II
compensator can be easily used to stabilize the system.
Figure 15 shows the voltage loop compensator, and its
transfer function is expressed as follows:
where
Compensator design goal:
• High DC gain
• Loop bandwidth fc:
• Gain margin: >10dB
• Phase margin: 40°
The compensator design procedure is as follows:
1. Put compensator zero at:
2. Put one compensator pole at zero frequency to achieve
high DC gain, and put another compensator pole at either
ESR zero frequency or half switching frequency,
whichever is lower.
The loop gain Tv(S) at cross over frequency of fc has unity
gain. Therefore, the compensator resistance R1 is
determined by:
where gm is the trans-conductance of the voltage loop error
amplifier. Compensator capacitor C1 is then given by:
Example: Vin = 19V, Vo = 16.8V, Io = 2.6A, fs = 300kHz,
Co = 10μF/10mΩ, L = 10μH, gm = 250μs, RT = 0.8Ω,
VFB = 2.1V, fc = 20kHz, then compensator resistance
R1 = 10kΩ. Choose R1 = 10kΩ. Put the compensator zero at
1.5kHz. The compensator capacitor is C1 = 6.5nF.
Therefore, choose voltage loop compensator: R1 = 10k,
C1 = 6.5nF.
Ti(S) = 0.25 RTF2(S)M
Tv(S) = KM F1(S)AV(S)
o
FB
V
V
K =
( )
1 T (S)
T S
L (S)
i
v
v +
=
LV(S)
4VFB
VO
--------------
(RO + RL)
RT
-----------------------------
1 S
ωesr
+ ------------
1 Sω
P
+ -------
------------------------AV(S) ωP
1
ROCO
= , ≈ -----------------
ωp
FIGURE 14. SMALL SIGNAL MODEL OF SYNCHRONOUS
BUCK REGULATOR
dˆ
Vin
dˆ
vˆIL
iˆin L
+
1:D
+
iˆL
Co
Rc
Ro
-Av(S)
dˆ
vˆcomp
RT
11/Vin
+
Ti(S)
K
vˆo
Tv(S)
-
VCA2
0.25VCA2
VindILdin ( )
SC
1 S
g
vˆ
vˆ
A S
1
cz
m
FB
comp
v
ω
+
= =
R C
1
1 1
ωcz =
-
+
R1
C1
VREF
VFB
Vo
gm
VCOMP
FIGURE 15. VOLTAGE LOOP COMPENSATOR
fs
20
1
5
1 ⎟⎠
⎞
⎜⎝
⎛ −
( )
o o
cz R C
ω = 1 − 3 1
R1
8πfCVOCORT
gmVFB
= ---------------------------------------
1 cz
1 R
C 1
ω
=
ISL6251, ISL6251A
18 FN9202.2
May 10, 2006
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
Signal Ground and Power Ground Connection.
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
GND and VDD Pin
At least one high quality ceramic decoupling cap should be
used to cross these two pins. The decoupling cap can be put
close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
PGND Pin
PGND pin should be laid out to the negative side of the
relevant output cap with separate traces. The negative side
of the output capacitor must be close to the source node of
the bottom MOSFET. This trace is the return path of LGATE.
PHASE Pin
This trace should be short, and positioned away from other
weak signal traces. This node has a very high dv/dt with a
voltage swing from the input voltage to ground. No trace
should be in parallel with it. This trace is also the return path
for UGATE. Connect this pin to the high-side MOSFET
source.
UGATE Pin
This pin has a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the
top MOSFET with high di/dt. This trace should be wide,
short, and away from other traces similar to the LGATE.
BOOT Pin
This pin’s di/dt is as high as the UGATE; therefore, this trace
should be as short as possible.
CSOP, CSON Pins
The current sense resistor connects to the CSON and the
CSOP pins through a low pass filter. The CSON pin is also
used as the battery voltage feedback. The traces should be
away from the high dv/dt and di/di pins like PHASE, BOOT
pins. In general, the current sense resistor should be close
to the IC. Other layout arrangements should be adjusted
accordingly.
EN Pin
This pin stays high at enable mode and low at idle mode and
is relatively robust. Enable signals should refer to the signal
ground.
DCIN Pin
This pin connects to AC adapter output voltage, and should
be less noise sensitive.
Copper Size for the Phase Node
The capacitance of PHASE should be kept very low to
minimize ringing. It would be best to limit the size of the
PHASE node copper in strict accordance with the current
and thermal management of the application.
Identify the Power and Signal Ground
The input and output capacitors of the converters, the source
terminal of the bottom switching MOSFET PGND should
connect to the power ground. The other components should
connect to signal ground. Signal and power ground are tied
together at one point.
Clamping Capacitor for Switching MOSFET
It is recommended that ceramic caps be used closely
connected to the drain of the high-side MOSFET, and the
source of the low-side MOSFET. This capacitor reduces the
noise and the power loss of the MOSFET.
ISL6251, ISL6251A
19 FN9202.2
May 10, 2006
ISL6251, ISL6251A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
INDEX
D1/2
D1
D/2
D
E1/2 E/2
E
A
2X
0.15
B
C
0.10 M C A B
A
N
SEATING PLANE
N
6
3 2
23
e
1
1
0.08
FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
C C
SECTION "C-C"
NX b
A1
C
2X
0.15 C
0.15
2X
B
0
REF.
(Nd-1)Xe
(NRe-E1F)X. e
5
A1
4X P
A
C
C
4X P
B
2X
0.15 C A
A2
A3
D2
D2
E2
E2/2
TERMINAL TIP
SIDE VIEW
TOP VIEW
7
BOTTOM VIEW
7
5
CL CL
e e
E1
2
NX k
NX b
8
NX L
8
8
9
AREA
9
4X
/ / 0.10 C
9
(DATUM B)
(DATUM A)
INDEX
6
AREA
N
9
CORNER
OPTION 4X
L1
L
10 L1
L
10
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)
SYMBOL
MILLIMETERS
MIN NOMINAL MAX NOTES
A 0.80 0.90 1.00 -
A1 - 0.02 0.05 -
A2 - 0.65 1.00 9
A3 0.20 REF 9
b 0.18 0.25 0.30 5,8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.95 3.10 3.25 7,8
E 5.00 BSC -
E1 4.75 BSC 9
E2 2.95 3.10 3.25 7,8
e 0.50 BSC -
k 0.20 - - -
L 0.50 0.60 0.75 8
N 28 2
Nd 7 3
Ne 7 3
P - - 0.60 9
θ - - 12 9
Rev. 1 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9202.2
May 10, 2006
ISL6251, ISL6251A
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
α
INDEX
AREA
E
D
N
1 2 3
-B-
0.17(0.007) M C A B S
e
-AB
M
-CA1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H 0.25(0.010) M B M
L
0.25
0.010
GAUGE
PLANE
A2
M24.15
24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A 0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
A2 - 0.061 - 1.54 -
B 0.008 0.012 0.20 0.30 9
C 0.007 0.010 0.18 0.25 -
D 0.337 0.344 8.55 8.74 3
E 0.150 0.157 3.81 3.98 4
e 0.025 BSC 0.635 BSC -
H 0.228 0.244 5.80 6.19 -
h 0.0099 0.0196 0.26 0.49 5
L 0.016 0.050 0.41 1.27 6
N 24 24 7
α 0° 8° 0° 8° -
Rev. 2 6/04
1
®
FN3282.13
DG411, DG412, DG413
Monolithic Quad SPST, CMOS Analog
Switches
The DG411 series monolithic CMOS analog switches are
drop-in replacements for the popular DG211 and DG212
series devices. They include four independent single pole
throw (SPST) analog switches, and TTL and CMOS
compatible digital inputs.
These switches feature lower analog ON-resistance (<35Ω)
and faster switch time (tON<175ns) compared to the DG211
or DG212. Charge injection has been reduced, simplifying
sample and hold applications.
The improvements in the DG411 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 40VP-P signals. Power supplies may be
single-ended from +5V to 44V, or split from ±5V to ±20V.
The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON-resistance variation with analog
signals is quite low over a ±15V analog input range. The
switches in the DG411 and DG412 are identical, differing only
in the polarity of the selection logic. Two of the switches in the
DG413 (#2 and #3) use the logic of the DG211 and DG411
(i.e., a logic “0” turns the switch ON) and the other two
switches use DG212 and DG412 positive logic. This permits
independent control of turn-on and turn-off times for SPDT
configurations, permitting “break-before-make” or “makebefore-
break” operation with a minimum of external logic.
Features
• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 35Ω
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . <35μW
• Fast Switching Action
- tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175ns
- tOFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145ns
• Low Charge Injection
• Upgrade from DG211, DG212
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
Data Sheet June 20, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1993, 1994, 1997, 1999, 2002, 2004-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2 FN3282.13
June 20, 2007
Pinout
DG411, DG412, DG413
(16 LD PDIP, SOIC, TSSOP)
TOP VIEW
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
DG411DJ DG411DJ -40 to +85 16 Ld PDIP E16.3
DG411DJZ (Note) DG411DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG411DY* DG411DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG411DYZ* (Note) DG411DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG411DVZ* (Note) DG411 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
DG412DJ DG412DJ -40 to +85 16 Ld PDIP E16.3
DG412DJZ (Note) DG412DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG412DY* DG412DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG412DYZ* (Note) DG412DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG412DVZ* (Note) DG412 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
DG413DJ DG413DJ -40 to +85 16 Ld PDIP E16.3
DG413DJZ (Note) DG413DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG413DY* DG413DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG413DYZ* (Note) DG413DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG413DVZ* (Note) DG413 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
*Add “-T” suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
TRUTH TABLE
LOGIC
DG411 DG412 DG413
SWITCH SWITCH
SWITCH
1, 4
SWITCH
2, 3
0 On Off Off On
1 Off On On Off
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
D1
S1
VGND
S4
IN4
D4
IN2
S2
V+
VL
S3
D3
IN3
D2
Pin Descriptions
PIN SYMBOL DESCRIPTION
1 IN1 Logic Control for Switch 1.
2 D1 Drain (Output) Terminal for Switch 1.
3 S1 Source (Input) Terminal for Switch 1.
4 V- Negative Power Supply Terminal.
5 GND Ground Terminal (Logic Common).
6 S4 Source (Input) Terminal for Switch 4.
7 D4 Drain (Output) Terminal for Switch 4.
8 IN4 Logic Control for Switch 4.
9 IN3 Logic Control for Switch 3.
10 D3 Drain (Output) Terminal for Switch 3.
11 S3 Source (Input) Terminal for Switch 3.
12 VL Logic Reference Voltage.
13 V+ Positive Power Supply Terminal (Substrate).
14 S2 Source (Input) Terminal for Switch 2.
15 D2 Drain (Output) Terminal for Switch 2.
16 IN2 Logic Control for Switch 2.
DG411, DG412, DG413
3 FN3282.13
June 20, 2007
Functional Diagrams Four SPST Switches per Package Switches Shown for Logic “1” Input
Schematic Diagram (1 Channel)
S1
D1
S2
D2
S3
D3
S4
D4
DG411
S1
D1
S2
D2
S3
D3
S4
D4
IN1
DG412
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
IN1
DG413
IN2
IN3
IN4
IN2
IN3
IN4
IN1
S
V+
INX
GND
VVVL
D
V+
DG411, DG412, DG413
4 FN3282.13
June 20, 2007
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
VL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) to (V+) +0.3V
Digital Inputs, VS, VD (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns
Thermal Resistance (Typical, Note 2) θJA (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Maximum Junction Temperature (Plastic Packages). . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(SOIC and TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified.
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON RL = 300Ω, CL = 35pF, VS = ±10V (Figure 1) 25 - 110 175 ns
85 - - 220 ns
Turn-OFF Time, tOFF 25 - 100 145 ns
85 - - 160 ns
Break-Before-Make Time Delay DG413 Only, RL = 300Ω, CL = 35pF (Figure 2) 25 - 25 - ns
Charge Injection, Q (Figure 3) CL = 10nF, VG = 0V, RG = 0Ω 25 - 5 - pC
OFF Isolation (Figure 5) RL = 50Ω, CL = 5pF, f = 1MHz 25 - 68 - dB
Crosstalk (Channel-to-Channel),
(Figure 4)
25 - -85 - dB
Source OFF Capacitance, CS(OFF) f = 1MHz (Figure 6) 25 - 9 - pF
Drain OFF Capacitance, CD(OFF) 25 - 9 - pF
Channel ON Capacitance,
CD(ON) + CS(ON)
25 - 35 - pF
DIGITAL INPUT CHARACTERISTICS
Input Current VIN Low, IIL VIN Under Test = 0.8V, All Others = 2.4V Full -0.5 0.005 0.5 μA
Input Current VIN High, IIH VIN Under Test = 2.4V, All Others = 0.8V Full -0.5 0.005 0.5 μA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG IS = 10mA Full -15 - 15 V
Drain-Source ON Resistance,
rDS(ON)
IS = 10mA, VD = ±8.5V, V+ = 13.5V, V- = -13.5V 25 - 25 35 Ω
Full - - 45 Ω
±
±
DG411, DG412, DG413
5 FN3282.13
June 20, 2007
Source OFF Leakage Current,
IS(OFF)
V+ = 16.5V, V- = -16.5V, VD = ±15.5V, VS = 15.5V 25 -0.25 ±0.1 0.25 nA
Full -5 - +5 nA
Drain OFF Leakage Current,
ID(OFF)
25 -0.25 ±0.1 0.25 nA
Full -5 - +5 nA
Channel ON Leakage Current,
ID(ON) + IS(ON)
V+ = 16.5V, V- = -16.5V, VS = VD = ±15.5V 25 -0.4 ±0.1 0.4 nA
Full -10 - +10 nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V 25 - 0.0001 1 μA
85 - - 5 μA
Negative Supply Current, I- 25 -1 -0.0001 - μA
85 -5 - - μA
Logic Supply Current, IL 25 - 0.0001 1 μA
85 - - 5 μA
Ground Current, IGND 25 -1 -0.0001 - μA
85 -5 - - μA
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified.
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON RL = 300Ω, CL = 35pF,
VS = 8V, (Figure 1)
25 - 175 250 ns
85 - - 315 ns
Turn-OFF Time, tOFF 25 - 95 125 ns
85 - - 140 ns
Break-Before-Make Time Delay DG413 Only, RL = 300Ω,
CL = 35pF, VS = 8V
25 - 25 - ns
Charge Injection, Q CL = 10nF, VG = 6.0V, RG = 0Ω 25 - 25 - pC
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - 12 V
Drain-Source ON-Resistance,
rDS(ON)
IS = -10mA, VD = 3V, 8V
V+ = 10.8V
25 - 40 80 Ω
Full - - 100 Ω
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4) UNITS
±
DG411, DG412, DG413
6 FN3282.13
June 20, 2007
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 13.2V, V- = 0V
VIN = 0V or 5V
25 - 0.0001 1 μA
85 - - 5 μA
Negative Supply Current, I- 25 -1 -0.0001 - μA
85 -5 - - μA
Logic Supply Current, IL 25 - 0.0001 1 μA
85 - - 5 μA
Ground Current, IGND 25 -1 -0.0001 - μA
85 -5 - - μA
NOTES:
3. VIN = input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
NOTE: Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENTS POINTS
Repeat test for all IN and S.
For load conditions, see Specifications. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUITS
FIGURE 2. BREAK-BEFORE-MAKE TIME
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4) UNITS
50%
tr < 20ns
tf < 20ns
tOFF
90%
3V
0V
VS
0V
tON
VO
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VO VS
RL
RL + rDS(ON)
= ------------------------------------
SWITCH
INPUT
LOGIC
INPUT
S1
IN1
V+
D1
RL CL
VO
GND
VVL
+5V +15V
SWITCH
OUTPUT
-15V
tD
3V
0V
VS1
0V
tD
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
90%
0V
VS2
(V01)
VO2
90%
S1
IN1, IN2
V+
D1
RL1 CL1
VO1
GND VVL
VS1 = 10V
300Ω
+5V +15V
S2 D2 35pF
RL2 CL2
VO2
VS2 = 10V
300Ω 35pF
-15V
LOGIC
INPUT
CL includes fixture and
stray capacitance.
DG411, DG412, DG413
7 FN3282.13
June 20, 2007
FIGURE 3A. TEST CIRCUIT
NOTE: INX dependent on switch configuration, input polarity
determined by sense of switch.
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. CHARGE INJECTION
FIGURE 4. CROSSTALK TEST CIRCUIT FIGURE 5. OFF ISOLATION TEST CIRCUIT
FIGURE 6. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT
Test Circuits and Waveforms (Continued)
V+
D1
CL
VO
GND
VVIN
= 3V
RG
VG
SWITCH ΔVO
INX
OFF ON
INX
OFF OFF
OFF
ON
Q = ΔVO x CL
OUTPUT
0V, 2.4V
ANALYZER
+15V
C V+
0dBm VS
SIGNAL
GENERATOR
RL
GND
IN1
VD
IN2
50Ω
0V, 2.4V
NC
V-
-15V
C
VD ANALYZER
RL
+15V
0dBm
SIGNAL
GENERATOR
C V+
V-
-15V
C
0V, 2.4V
VS
VD
INX
GND
+15V
C V+
GND
VS
VD
INX
V-
-15V
C
IMPEDANCE
ANALYZER
f = 1MHz
0V, 2.4V
DG411, DG412, DG413
8 FN3282.13
June 20, 2007
Application Information
Single Supply Operation
The DG411, DG412, DG413 can be operated with unipolar
supplies from 5V to 44V. These devices are characterized
and tested for single supply operation at 12V to facilitate the
majority of applications. To function properly, 12V is tied to
Pins 13 and 0V is tied to Pin 4.
Pin 12 still requires 5V for TTL compatible switching.
Summing Amplifier
When driving a high impedance, high capacitance load such
as shown in Figure 7, where the inputs to the summing
amplifier have some noise filtering, it is necessary to have
shunt switches for rapid discharge of the filter capacitor, thus
preventing offsets from occurring at the output.
VIN1
R1 R2
VOUT
+
-
C1
VIN2
R3 R4
C2
DG413
R5
R6
FIGURE 7. SUMMING AMPLIFIER
DG411, DG412, DG413
9 FN3282.13
June 20, 2007
Typical Performance Curves
FIGURE 8. ON RESISTANCE vs VD AND POWER SUPPLY
VOLTAGE
FIGURE 9. SWITCHING TIME vs TEMPERATURE
FIGURE 10. LEAKAGE CURRENTS vs ANALOG VOLTAGE FIGURE 11. SUPPLY CURRENT vs INPUT SWITCHING
FREQUENCY
FIGURE 12. CHARGE INJECTION vs SOURCE VOLTAGE FIGURE 13. CHARGE INJECTION vs DRAIN VOLTAGE
TA = +25°C
50
A: ±5V
B: ±8V
C: ±10V
D: ±12V
E: ±15V
F: ±20V
45
40
35
30
25
20
15
10
5
0
-20 -15 -10 -5 0 5 10 15 20
A
B
C
D
E
F
DRAIN VOLTAGE (V)
rDS(ON) (Ω)
V+ = 15V, V- = -15V
VL = 5V, VS = 10V
tON
tOFF
-55 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
-35
0
240
210
180
150
120
90
60
30
tON, tOFF (ns)
V+ = 15V, V- = -15V
VL = 5V, TA = +25°C
-15 -5 0 5 10 15
VS, VD (V)
-10
-60
20
10
0
-10
-20
-30
-40
-50
IS, ID (pA)
IS(OFF)
ID(OFF)
30
40
ID(ON) + IS(ON)
ISUPPLY
100mA
1mA
100μA
10μA
1μA
100nA
10nA
10mA
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
IL
I+, I-
1SW 1SW
4SW
4SW
V+ = 15V, V- = -15V
VL = 5V
CL = 10nF
CL = 1nF
-15 -5 0 5 10 15
VS (V)
-10
-60
60
40
20
0
-20
-40
Q (pC)
80
100
V+ = 15V, V- = -15V
VL = 5V CL = 10nF
CL = 1nF
-15 -5 0 5 10 15
VD (V)
-10
-60
60
40
20
0
-20
-40
Q (pC)
100
140
120
80
V+ = 15V, V- = -15V
VL = 5V
DG411, DG412, DG413
10 FN3282.13
June 20, 2007
Die Characteristics
DIE DIMENSIONS:
2760mm x 1780mm x 485mm
METALLIZATION:
Type: SiAl
Thickness: 12kÅ ±1kÅ
PASSIVATION:
Type: Nitride
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm2
Metallization Mask Layout
DG411, DG412, DG413
S1 (3)
V- (4)
GND (5)
S4 (6)
D1 IN1 IN2
(11) S3
(12) VL
(13) V+ SUBSTRATE
(14) S2
(15) D2
(2) (1) (16)
D4 IN4 IN3 D3
(7) (8) (9) (10)
DG411, DG412, DG413
11 FN3282.13
June 20, 2007
DG411, DG412, DG413
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
α
INDEX
AREA
E1
D
N
1 2 3
-B-
0.10(0.004) M C A B S
e
-Ab
M
-CA1
A
SEATING PLANE
0.10(0.004)
c
E 0.25(0.010) M B M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A - 0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N 16 16 7
a 0o 8o 0o 8o -
Rev. 1 2/02
12 FN3282.13
June 20, 2007
DG411, DG412, DG413
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC
seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendicular
to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-CCL
E
eA
C
eB
eC
-BE1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-CD1
B1
B
e
D
D1
A2 A
L
A1
-A-
0.010 (0.25) M C A B S
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC 6
eB - 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N 16 16 9
Rev. 0 12/93
13
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3282.13
June 20, 2007
DG411, DG412, DG413
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
1 2 3
-B-
0.25(0.010) M C A B S
e
-AL
B
M
-CA1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H 0.25(0.010) M B M
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N 16 16 7
α 0° 8° 0° 8° -
Rev. 1 6/05
1
®
July 2004
HIP4081A
80V/2.5A Peak, High Frequency Full
Bridge FET Driver
The HIP4081A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4081A can drive every
possible switch combination except those which would
cause a shoot-through condition. The HIP4081A can switch
at frequencies up to 1MHz and is well suited to driving Voice
Coil Motors, high-frequency switching power amplifiers, and
power supplies.
For example, the HIP4081A can drive medium voltage brush
motors, and two HIP4081As can be used to drive high
performance stepper motors, since the short minimum
“on-time” can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in rapid, precise control of the driven load.
A similar part, the HIP4080A, includes an on-chip input
comparator to create a PWM signal from an external triangle
wave and to facilitate “hysteresis mode” switching.
The Application Note for the HIP4081A is the AN9405.
Features
• Independently Drives 4 N-Channel FET in Half Bridge or
Full Bridge Configurations
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz in Free Air at 50°C with Rise
and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chip Charge-Pump and Bootstrap Upper Bias
Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V Logic
Levels
• Very Low Power Consumption
• Undervoltage Protection
• Pb-free Available
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Switching Power Amplifiers
• High Performance Motor Controls
• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals
• U.P.S.
Pinout
HIP4081A
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP RANGE
(°C) PACKAGE
PKG.
DWG. #
HIP4081AIP -40 to 85 20 Ld PDIP E20.3
HIP4081AIPZ
(Note)
-40 to 85 20 Ld PDIP
(Pb-free)
E20.3
HIP4081AIB -40 to 85 20 Ld SOIC (W) M20.3
HIP4081AIBZ
(Note)
-40 to 85 20 Ld SOIC (W)
(Pb-free)
M20.3
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
BHB 1
BHI
DIS
VSS
BLI
ALI
HDEL
AHI
LDEL
AHB
BHO
BLO
BLS
VDD
BHS
VCC
ALS
ALO
AHS
AHO
Data Sheet FN3659.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
HIP4081A
Application Block Diagram
Functional Block Diagram (1/2 HIP4081A)
80V
GND
LOAD
HIP4081A
GND
12V
AHI
ALI
BLI
BHI BLO
BHS
BHO
ALO
AHS
AHO
CHARGE
PUMP
VDD
AHI
DIS
ALI
HDEL
LDEL
VSS
TURN-ON
DELAY
TURN-ON
DELAY
DRIVER
DRIVER
AHB
AHO
AHS
VCC
ALO
ALS
CBF
TO VDD (PIN 16)
CBS
DBS
HIGH VOLTAGE BUS ≤ 80VDC
+12VDC
LEVEL SHIFT
AND LATCH
14
10
11
12
15
13
16
7
3
6
8
9
4
BIAS
SUPPLY
UNDERVOLTAGE
3
Typical Application (PWM Mode Switching)
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1 BHB
BHI
DIS
VSS
BLI
ALI
HDEL
AHI
LDEL
AHB
BHO
BLO
BLS
VDD
BHS
VCC
ALS
ALO
AHS
AHO
80V
12V
+
-
12V
DIS
GND
6V
GND
TO OPTIONAL
CURRENT CONTROLLER
PWM
LOAD
INPUT
HIP4081/HIP4081A
HIP4081A
4
HIP4081A
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25°C to 125°C)
Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55°C to 125°C)
Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD
Voltage on ALO, BLO . . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V
Voltage on AHO, BHO . . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
NOTE: All Voltages relative to VSS, unless otherwise specified.
Thermal Resistance (Typical, Note 1) θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Storage Temperature Range. . . . . . . . . . . . . . . . . . . -65°C to 150°C
Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Lead Temperature (Soldering 10s)). . . . . . . . . . . . . . . . . . . . . 300°C
(For SOIC - Lead Tips Only
Operating Conditions
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V
Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500μA to -50μA
Operating Ambient Temperature Range . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and
TA = 25°C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
TJ = 25°C
TJS = -40°C TO
125°C
MIN TYP MAX MIN MAX UNITS
SUPPLY CURRENTS AND CHARGE PUMPS
VDD Quiescent Current IDD All inputs = 0V 8.5 10.5 14.5 7.5 14.5 mA
VDD Operating Current IDDO Outputs switching f = 500kHz 9.5 12.5 15.5 8.5 15.5 mA
VCC Quiescent Current ICC All Inputs = 0V, IALO = IBLO = 0 - 0.1 10 - 20 μA
VCC Operating Current ICCO f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA
AHB, BHB Quiescent Current -
Qpump Output Current
IAHB, IBHB All Inputs = 0V, IAHO = IBHO = 0
VDD = VCC = VAHB = VBHB = 10V
-50 -30 -11 -60 -10 μA
AHB, BHB Operating Current IAHBO, IBHBO f = 500kHz, No Load 0.6 1.2 1.5 0.5 1.9 mA
AHS, BHS, AHB, BHB Leakage
Current
IHLK VBHS = VAHS = 80V,
VAHB = VBHB = 93V
- 0.02 1.0 - 10 μA
AHB-AHS, BHB-BHS Qpump
Output Voltage
VAHB-VAHS
VBHB-VBHS
IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V
INPUT PINS: ALI, BLI, AHI, BHI, AND DIS
Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V
High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V
Input Voltage Hysteresis - 35 - - - mV
Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 μA
High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 μA
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage VHDEL, VLDEL IHDEL = ILDEL = -100μA 4.9 5.1 5.3 4.8 5.4 V
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
Low Level Output Voltage VOL IOUT = 100mA 0.7 0.85 1.0 0.5 1.1 V
High Level Output Voltage VCC-VOH IOUT = -100mA 0.8 0.95 1.1 0.5 1.2 V
Peak Pullup Current IO+ VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A
5
HIP4081A
Peak Pulldown Current IO- VO UT = 12V 1.7 2.4 3.3 1.3 3.6 A
Undervoltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V
Undervoltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V
Undervoltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V
Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF.
PARAMETER SYMBOL TEST CONDITIONS
TJ = 25°C
TJS = -40°C
TO 125°C
MIN TYP MAX MIN MAX UNITS
Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)
TLPHL - 30 60 - 80 ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
THPHL - 35 70 - 90 ns
Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)
TLPLH RHDEL = RLDEL = 10K - 45 70 - 90 ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
THPLH RHDEL = RLDEL = 10K - 60 90 - 110 ns
Rise Time TR - 10 25 - 35 ns
Fall Time TF - 10 25 - 35 ns
Turn-on Input Pulse Width TPWIN-ON RHDEL = RLDEL = 10K 50 - - 50 - ns
Turn-off Input Pulse Width TPWIN-OFF RHDEL = RLDEL = 10K 40 - - 40 - ns
Turn-on Output Pulse Width TPWOUT-ON RHDEL = RLDEL = 10K 40 - - 40 - ns
Turn-off Output Pulse Width TPWOUT-OFF RHDEL = RLDEL = 10K 30 - - 30 - ns
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW - 45 75 - 95 ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH - 55 85 - 105 ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
TDLPLH - 40 70 - 90 ns
Refresh Pulse Width (ALO and BLO) TREF-PW 240 410 550 200 600 ns
Disable to Upper Enable (DIS - AHO and BHO) TUEN - 450 620 - 690 ns
TRUTH TABLE
INPUT OUTPUT
ALI, BLI AHI, BHI U/V DIS ALO, BLO AHO, BHO
X X X 1 0 0
1 X 0 0 1 0
0 1 0 0 0 1
0 0 0 0 0 0
X X 1 X 0 0
NOTE: X signifies that input can be either a “1” or “0”.
Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and
TA = 25°C, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS
TJ = 25°C
TJS = -40°C TO
125°C
MIN TYP MAX MIN MAX UNITS
6
HIP4081A
Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30μA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than VDD).
4 VSS Chip negative supply, generally will be ground.
5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin
8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V
(no greater than VDD).
6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin
8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V
(no greater than VDD).
7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no
shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30μA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.
16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).
17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.
7
HIP4081A
Timing Diagrams
FIGURE 1. INDEPENDENT MODE
FIGURE 2. BISTATE MODE
FIGURE 3. DISABLE FUNCTION
U/V = DIS = 0
XLI
XHI
XLO
XHO
TLPHL THPHL
THPLH TLPLH TR
(10% - 90%)
TF
(10% - 90%)
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
U/V = DIS = 0
XLI
XHI = HI OR NOT CONNECTED
XLO
XHO
(10% - 90%) (10% - 90%)
U/V OR DIS
XLI
XHI
XLO
XHO
TDLPLH TDIS
TUEN
TREF-PW
8
HIP4081A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K
and TA = 25°C, Unless Otherwise Specified
FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD
SUPPLY VOLTAGE
FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs
FREQUENCY (kHz)
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs
FREQUENCY (LOAD = 1000pF)
FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs
FREQUENCY (kHz) TEMPERATURE
FIGURE 8. IAHB, IBHB, NO-LOAD FLOATING SUPPLY BIAS
CURRENT vs FREQUENCY
FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL
vs TEMPERATURE
6 8 10 12 14
2.0
4.0
6.0
8.0
10.0
12.0
14.0
IDD SUPPLY CURRENT (mA)
VDD SUPPLY VOLTAGE (V)
0 100 200 300 400 500 600 700 800 900 1000
8.0
8.5
9.0
9.5
10.0
10.5
11.0
IDD SUPPLY CURRENT (mA)
SWITCHING FREQUENCY (kHz)
0 100 200 300 400 500 600 700 800 900 1000
0.0
5.0
10.0
15.0
20.0
25.0
30.0
FLOATING SUPPLY BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz) 0 100 200 300 400 500 600 700 800 900 1000
0.0
1.0
2.0
3.0
4.0
5.0
ICC SUPPLY CURRENT (mA)
SWITCHING FREQUENCY (kHz)
75°C
25°C
125°C
-40°C
0°C
0.5
1
1.5
2
2.5
0 200 400 600 800 1000
FLOATING SUPPLY BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz)
-50 -25 0 25 50 75 100 125
-120
-110
-100
-90
LOW LEVEL INPUT CURRENT (μA)
JUNCTION TEMPERATURE (°C)
9
HIP4081A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K
and TA = 25°C, Unless Otherwise Specified
FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION
DELAY TDISHIGH vs TEMPERATURE
FIGURE 12. DISABLE TO UPPER ENABLE, TUEN,
PROPAGATION DELAY vs TEMPERATURE
FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION
DELAY TDISLOW vs TEMPERATURE
FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs
TEMPERATURE
FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH
PROPAGATION DELAY vs TEMPERATURE
-40 -20 0 20 40 60 80 100 120
10.0
11.0
12.0
13.0
14.0
15.0
NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
425
450
475
500
525
-50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
PROPAGATION DELAY (ns)
-40 -20 0 20 40 60 80 100 120
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
350
375
400
425
450
-50 -25 0 25 50 75 100 125 150
REFRESH PULSE WIDTH (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
10
HIP4081A
FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL
vs TEMPERATURE
FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs
TEMPERATURE
FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL
vs TEMPERATURE
FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs
TEMPERATURE
FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K
and TA = 25°C, Unless Otherwise Specified (Continued)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
8.5
9.5
10.5
11.5
12.5
13.5
GATE DRIVE FALL TIME (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
8.5
9.5
10.5
11.5
12.5
13.5
TURN-ON RISE TIME (ns)
JUNCTION TEMPERATURE (°C)
11
HIP4081A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K and TA = 25°C, Unless Otherwise Specified
FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS
SUPPLY AND TEMPERATURE AT 100mA
FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERATURE AT 100mA
FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY
VOLTAGE
FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY
VOLTAGE
FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS
QUIESCENT COMPONENT) vs FREQUENCY AND
GATE LOAD CAPACITANCE
-40 -20 0 20 40 60 80 100 120
4.0
4.5
5.0
5.5
6.0
HDEL, LDEL INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
10 12 14
0
250
500
750
1000
1250
1500
VCC - VOH (mV)
BIAS SUPPLY VOLTAGE (V)
75°C
25°C
125°C
-40°C
0°C
12 14
0
250
500
750
1000
1250
1500
VOL (mV)
BIAS SUPPLY VOLTAGE (V)
10
75°C
25°C
125°C
-40°C
0°C
6 7 8 9 10 11 12 13 14 15 16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
GATE DRIVE SINK CURRENT (A)
VDD, VCC, VAHB, VBHB (V)
6 7 8 9 10 11 12 13 14 15 16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
GATE DRIVE SINK CURRENT (A)
VDD, VCC, VAHB, VBHB (V)
1 2 5 10 20 50 100 200 500 1000
0.1
1
10
100
500
50
5
0.5
200
20
2
0.2
LOW VOLTAGE BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz)
100pF
1,000pF
10,000pF
3,000pF
12
HIP4081A
FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE
FIGURE 29. UNDERVOLTAGE LOCKOUT vs TEMPERATURE FIGURE 30. MINIMUM DEAD-TIME vs DEL RESISTANCE
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K and TA = 25°C, Unless Otherwise Specified (Continued)
10 20 50 100 200 500 1000
10
100
1000
20
50
200
500
LEVEL-SHIFT CURRENT (μA)
SWITCHING FREQUENCY (kHz)
8.2
8.4
8.6
8.8
9.0
50 25 0 25 50 75 100 125 150
UV+
UVTEMPERATURE
(°C)
BIAS SUPPLY VOLTAGE, VDD (V)
10 50 100 150 200 250
0
30
60
90
120
150
HDEL/LDEL RESISTANCE (kΩ)
DEAD-TIME (ns)
13
HIP4081A
1
2
3
1
2
3
1
2
3
5 6
1
2
3
1 2
13 12
1
2
3
11 10
1
2
3
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
L1
R21
Q1
Q3
Q4
R22
L2
R23 C1
C3
JMPR1
R24
R30 R31
C2
R34
C4
CR2
CR1
Q2
JMPR5
JMPR3
JMPR2
JMPR4
R33
C5
C6
CX CY
C8
U1
CW CW
+
B+
IN2 IN1
BO
OUT/BLI
IN-/AHI
COM
IN+/ALI +12V
+12V
BLS
AO
HEN/BHI
ALS
CD4069UB
CD4069UB
CD4069UB
CD4069UB
HIP4080A/81A
SECTION
CONTROL LOGIC
POWER SECTION
DRIVER SECTION
AHB AHO
LDEL AHS
HDEL ALO
IN-/AHI ALS
IN+/ALI VCC
OUT/BLI VDD
VSS BLS
DIS BLO
HEN/BHI BHS
BHB BHO
R29
U2
U2
U2
U2
3 4
9 8
R32
I
O
O
CD4069UB
CD4069UB
ENABLE IN
U2
U2
NOTES:
1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V.
2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED.
REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT
LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR
JMPR1 - JMPR4.
FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC
14
HIP4081A
R22 1
Q3
L1
JMPR2
JMPR5
R31
R33
CR2
R23
R24
R27
R28
R26
1
Q4
1
JMPR3 Q2
U1
R21
GND
L2
C3
C4
JMPR4
JMPR1
R30
CR1
U2
R34
R32
I
O
C8
R29
C7
C6
C5
CY
CX
1
Q1
COM
+12V
B+
IN1
IN2
AHO
BHO
ALO
BLO
BLS
BLS
LDEL
HDEL
DIS
ALS
ALS
O
+ +
HIP4080/81
FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN
15
HIP4081A
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendicular
to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-CCL
E
eA
C
eB
eC
-BE1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-CD1
B1
B
e
D
D1
A2 A
L
A1
-A-
0.010 (0.25) M C A B S
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.55 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC 6
eB - 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N 20 20 9
Rev. 0 12/93
16
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
HIP4081A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
1 2 3
-B-
0.25(0.010) M C A B S
e
-AL
B
M
-CA1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
μ
0.25(0.010) M B M
α
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
MIN MAX MIN MAX NOTES
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.014 0.019 0.35 0.49 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N 20 20 7
α 0o 8o 0o 8o -
Rev. 1 1/02
http://www.farnell.com/datasheets/32553.pdf
1
®
FN3663.5
HFA3101
Gilbert Cell UHF Transistor Array
The HFA3101 is an all NPN transistor array configured as a Multiplier Cell. Based on Intersil’s bonded wafer UHF-1 SOI process, this array achieves very high fT (10GHz) while maintaining excellent hFE and VBE matching characteristics that have been maximized through careful attention to circuit design and layout, making this product ideal for communication circuits. For use in mixer applications, the cell provides high gain and good cancellation of 2nd order distortion terms.
Pinout
HFA3101(SOIC)
TOP VIEW
Features
•Pb-free Available as an Option
•High Gain Bandwidth Product (fT) . . . . . . . . . . . . . 10GHz
•High Power Gain Bandwidth Product. . . . . . . . . . . . 5GHz
•Current Gain (hFE). . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
•Low Noise Figure (Transistor) . . . . . . . . . . . . . . . . . 3.5dB
•Excellent hFE and VBE Matching
•Low Collector Leakage Current . . . . . . . . . . . . . . <0.01nA
•Pin to Pin Compatible to UPA101
Applications
•Balanced Mixers
•Multipliers
•Demodulators/Modulators
•Automatic Gain Control Circuits
•Phase Detectors
•Fiber Optic Signal Processing
•Wireless Communication Systems
•Wide Band Amplification Stages
•Radio and Satellite Communications
•High Performance Instrumentation
Ordering Information
PART NUMBER (BRAND)
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
HFA3101B
(H3101B)
-40 to 85
8 Ld SOIC
M8.15
HFA3101BZ
(H3101B) (Note)
-40 to 85
8 Ld SOIC
(Pb-free)
M8.15
HFA3101B96
(H3101B)
-40 to 85
8 Ld SOIC Tape and Reel
M8.15
HFA3101BZ96
(H3101B) (Note)
-40 to 85
8 Ld SOIC Tape and Reel (Pb-free)
M8.15
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
12348765Q5Q6Q1Q2Q3Q4NOTE: Q5 and Q6 -
2
Paralleled 3μm x
50μm Transistors Q1, Q2, Q3, Q4 -
Single 3μm x
50μm Transistors
Data Sheet
September 2004
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1998, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Absolute Maximum Ratings
Thermal Information
VCEO, Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . 8.0V
VCBO, Collector to Base Voltage. . . . . . . . . . . . . . . . . . . . . . . 12.0V
VEBO, Emitter to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
IC, Collector Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical SpecificationsTA = 25oC
PARAMETER
TEST CONDITIONS
(NOTE 2)
TEST LEVEL
MIN
TYP
MAX
UNITS
Collector to Base Breakdown Voltage, V(BR)CBO, Q1 thru Q6
IC = 100μA, IE = 0
A
12
18
-
V
Collector to Emitter Breakdown Voltage, V(BR)CEO,
Q5 and Q6
IC = 100μA, IB = 0
A
8
12
-
V
Emitter to Base Breakdown Voltage, V(BR)EBO, Q1 thru Q6
IE = 10μA, IC = 0
A
5.5
6
-
V
Collector Cutoff Current, ICBO, Q1 thru Q4
VCB = 8V, IE = 0
A
-
0.1
10
nA
Emitter Cutoff Current, IEBO, Q5 and Q6
VEB = 1V, IC = 0
A
-
-
200
nA
DC Current Gain, hFE, Q1 thru Q6
IC = 10mA, VCE = 3V
A
40
70
-
Collector to Base Capacitance, CCB
Q1 thru Q4
VCB = 5V, f = 1MHz
C
-
0.300
-
pF
Q5 and Q6
-
0.600
-
pF
Emitter to Base Capacitance, CEB
Q1 thru Q4
VEB = 0, f = 1MHz
B
-
0.200
-
pF
Q5 and Q6
-
0.400
-
pF
Current Gain-Bandwidth Product, fT
Q1 thru Q4
IC = 10mA, VCE = 5V
C
-
10
-
GHz
Q5 and Q6
IC = 20mA, VCE = 5V
C
-
10
-
GHz
Power Gain-Bandwidth Product, fMAX
Q1 thru Q4
IC = 10mA, VCE = 5V
C
-
5
-
GHz
Q5 and Q6
IC = 20mA, VCE = 5V
C
-
5
-
GHz
Available Gain at Minimum Noise Figure, GNFMIN,
Q5 and Q6
IC = 5mA, VCE = 3V
f = 0.5GHz
C
-
17.5
-
dB
f = 1.0GHz
C
-
11.9
-
dB
Minimum Noise Figure, NFMIN, Q5 and Q6
IC = 5mA, VCE = 3V
f = 0.5GHz
C
-
1.7
-
dB
f = 1.0GHz
C
-
2.0
-
dB
50Ω Noise Figure, NF50Ω, Q5 and Q6
IC = 5mA, VCE = 3V
f = 0.5GHz
C
-
2.25
-
dB
f = 1.0GHz
C
-
2.5
-
dB
DC Current Gain Matching, hFE1/hFE2, Q1 and Q2,
Q3 and Q4, and Q5 and Q6
IC = 10mA, VCE = 3V
A
0.9
1.0
1.1
Input Offset Voltage, VOS, (Q1 and Q2), (Q3 and Q4),
(Q5 and Q6)
IC = 10mA, VCE = 3V
A
-
1.5
5
mV
Input Offset Current, IC, (Q1 and Q2), (Q3 and Q4),
(Q5 and Q6)
IC = 10mA, VCE = 3V
A
-
5
25
μA
Input Offset Voltage TC, dVOS/dT, (Q1 and Q2, Q3 and Q4, Q5 and Q6)
IC = 10mA, VCE = 3V
C
-
0.5
-
μV/oC
Collector to Collector Leakage, ITRENCH-LEAKAGE
ΔVTEST = 5V
B
-
0.01
-
nA
NOTE:
2. Test Level: A. Production Tested, B. Typical or Guaranteed Limit Based on Characterization, C. Design Typical for Information Only.
HFA3101
3-3
PSPICE Model for a 3 μm x 50μm Transistor
.Model NUHFARRY NPN
+ (IS = 1.840E-16
XTI = 3.000E+00
EG = 1.110E+00
VAF = 7.200E+01
+ VAR = 4.500E+00
BF = 1.036E+02
ISE = 1.686E-19
NE = 1.400E+00
+ IKF = 5.400E-02
XTB = 0.000E+00
BR = 1.000E+01
ISC = 1.605E-14
+ NC = 1.800E+00
IKR = 5.400E-02
RC = 1.140E+01
CJC = 3.980E-13
+ MJC = 2.400E-01
VJC = 9.700E-01
FC = 5.000E-01
CJE = 2.400E-13
+ MJE = 5.100E-01
VJE = 8.690E-01
TR = 4.000E-09
TF = 10.51E-12
+ ITF = 3.500E-02
XTF = 2.300E+00
VTF = 3.500E+00
PTF = 0.000E+00
+ XCJC = 9.000E-01
CJS = 1.689E-13
VJS = 9.982E-01
MJS = 0.000E+00
+ RE = 1.848E+00
RB = 5.007E+01
RBM = 1.974E+00
KF = 0.000E+00
+ AF = 1.000E+00)
Common Emitter S-Parameters of 3 μm x 50μm Transistor
FREQ. (Hz)
|S11|
PHASE(S11)
|S12|
PHASE(S12)
|S21|
PHASE(S21)
|S22|
PHASE(S22)
VCE = 5V and IC = 5mA
1.0E+08
0.83
-11.78
1.41E-02
78.88
11.07
168.57
0.97
-11.05
2.0E+08
0.79
-22.82
2.69E-02
68.63
10.51
157.89
0.93
-21.35
3.0E+08
0.73
-32.64
3.75E-02
59.58
9.75
148.44
0.86
-30.44
4.0E+08
0.67
-41.08
4.57E-02
51.90
8.91
140.36
0.79
-38.16
5.0E+08
0.61
-48.23
5.19E-02
45.50
8.10
133.56
0.73
-44.59
6.0E+08
0.55
-54.27
5.65E-02
40.21
7.35
127.88
0.67
-49.93
7.0E+08
0.50
-59.41
6.00E-02
35.82
6.69
123.10
0.62
-54.37
8.0E+08
0.46
-63.81
6.27E-02
32.15
6.11
119.04
0.57
-58.10
9.0E+08
0.42
-67.63
6.47E-02
29.07
5.61
115.57
0.53
-61.25
1.0E+09
0.39
-70.98
6.63E-02
26.45
5.17
112.55
0.50
-63.96
1.1E+09
0.36
-73.95
6.75E-02
24.19
4.79
109.91
0.47
-66.31
1.2E+09
0.34
-76.62
6.85E-02
22.24
4.45
107.57
0.45
-68.37
1.3E+09
0.32
-79.04
6.93E-02
20.53
4.15
105.47
0.43
-70.19
1.4E+09
0.30
-81.25
7.00E-02
19.02
3.89
103.57
0.41
-71.83
1.5E+09
0.28
-83.28
7.05E-02
17.69
3.66
101.84
0.40
-73.31
1.6E+09
0.27
-85.17
7.10E-02
16.49
3.45
100.26
0.39
-74.66
1.7E+09
0.25
-86.92
7.13E-02
15.41
3.27
98.79
0.38
-75.90
1.8E+09
0.24
-88.57
7.17E-02
14.43
3.10
97.43
0.37
-77.05
1.9E+09
0.23
-90.12
7.19E-02
13.54
2.94
96.15
0.36
-78.12
2.0E+09
0.22
-91.59
7.21E-02
12.73
2.80
94.95
0.35
-79.13
2.1E+09
0.21
-92.98
7.23E-02
11.98
2.68
93.81
0.35
-80.09
2.2E+09
0.20
-94.30
7.25E-02
11.29
2.56
92.73
0.34
-80.99
2.3E+09
0.20
-95.57
7.27E-02
10.64
2.45
91.70
0.34
-81.85
2.4E+09
0.19
-96.78
7.28E-02
10.05
2.35
90.72
0.33
-82.68
2.5E+09
0.18
-97.93
7.29E-02
9.49
2.26
89.78
0.33
-83.47
2.6E+09
0.18
-99.05
7.30E-02
8.96
2.18
88.87
0.33
-84.23
2.7E+09
0.17
-100.12
7.31E-02
8.47
2.10
88.00
0.33
-84.97
HFA3101
4
2.8E+09
0.17
-101.15
7.31E-02
8.01
2.02
87.15
0.33
-85.68
2.9E+09
0.16
-102.15
7.32E-02
7.57
1.96
86.33
0.33
-86.37
3.0E+09
0.16
-103.11
7.32E-02
7.16
1.89
85.54
0.33
-87.05
VCE = 5V and IC = 10mA
1.0E+08
0.72
-16.43
1.27E-02
75.41
15.12
165.22
0.95
-14.26
2.0E+08
0.67
-31.26
2.34E-02
62.89
13.90
152.04
0.88
-26.95
3.0E+08
0.60
-43.76
3.13E-02
52.58
12.39
141.18
0.79
-37.31
4.0E+08
0.53
-54.00
3.68E-02
44.50
10.92
132.57
0.70
-45.45
5.0E+08
0.47
-62.38
4.05E-02
38.23
9.62
125.78
0.63
-51.77
6.0E+08
0.42
-69.35
4.31E-02
33.34
8.53
120.37
0.57
-56.72
7.0E+08
0.37
-75.26
4.49E-02
29.47
7.62
116.00
0.51
-60.65
8.0E+08
0.34
-80.36
4.63E-02
26.37
6.86
112.39
0.47
-63.85
9.0E+08
0.31
-84.84
4.72E-02
23.84
6.22
109.36
0.44
-66.49
1.0E+09
0.29
-88.83
4.80E-02
21.75
5.69
106.77
0.41
-68.71
1.1E+09
0.27
-92.44
4.86E-02
20.00
5.23
104.51
0.39
-70.62
1.2E+09
0.25
-95.73
4.90E-02
18.52
4.83
102.53
0.37
-72.28
1.3E+09
0.24
-98.75
4.94E-02
17.25
4.49
100.75
0.35
-73.76
1.4E+09
0.22
-101.55
4.97E-02
16.15
4.19
99.16
0.34
-75.08
1.5E+09
0.21
-104.15
4.99E-02
15.19
3.93
97.70
0.33
-76.28
1.6E+09
0.20
-106.57
5.01E-02
14.34
3.70
96.36
0.32
-77.38
1.7E+09
0.20
-108.85
5.03E-02
13.60
3.49
95.12
0.31
-78.41
1.8E+09
0.19
-110.98
5.05E-02
12.94
3.30
93.96
0.31
-79.37
1.9E+09
0.18
-113.00
5.06E-02
12.34
3.13
92.87
0.30
-80.27
2.0E+09
0.18
-114.90
5.07E-02
11.81
2.98
91.85
0.30
-81.13
2.1E+09
0.17
-116.69
5.08E-02
11.33
2.84
90.87
0.30
-81.95
2.2E+09
0.17
-118.39
5.09E-02
10.89
2.72
89.94
0.29
-82.74
2.3E+09
0.16
-120.01
5.10E-02
10.50
2.60
89.06
0.29
-83.50
2.4E+09
0.16
-121.54
5.11E-02
10.13
2.49
88.21
0.29
-84.24
2.5E+09
0.16
-122.99
5.12E-02
9.80
2.39
87.39
0.29
-84.95
2.6E+09
0.15
-124.37
5.12E-02
9.49
2.30
86.60
0.29
-85.64
2.7E+09
0.15
-125.69
5.13E-02
9.21
2.22
85.83
0.29
-86.32
2.8E+09
0.15
-126.94
5.13E-02
8.95
2.14
85.09
0.29
-86.98
2.9E+09
0.15
-128.14
5.14E-02
8.71
2.06
84.36
0.29
-87.62
3.0E+09
0.14
-129.27
5.15E-02
8.49
1.99
83.66
0.29
-88.25
Common Emitter S-Parameters of 3 μm x 50 μm Transistor (Continued)
FREQ. (Hz) |S11| PHASE(S11) |S12| PHASE(S12) |S21| PHASE(S21) |S22| PHASE(S22)
HFA3101
3-5
Application Information
The HFA3101 array is a very versatile RF Building block. It has been carefully laid out to improve its matching properties, bringing the distortion due to area mismatches, thermal distribution, betas and ohmic resistances to a minimum.
The cell is equivalent to two differential stages built as two “variable transconductance multipliers” in parallel, with their outputs cross coupled. This configuration is well known in the industry as a Gilbert Cell which enables a four quadrant multiplication operation.
Due to the input dynamic range restrictions for the input levels at the upper quad transistors and lower tail transistors, the HFA3101 cell has restricted use as a linear four quadrant multiplier. However, its configuration is well suited for uses where its linear response is limited to one of the inputs only, as in modulators or mixer circuit applications. Examples of these circuits are up converters, down converters, frequency doublers and frequency/phase detectors.
Although linearization is still an issue for the lower pair input, emitter degeneration can be used to improve the dynamic range and consequent linearity. The HFA3101 has the lower pair emitters brought to external pins for this purpose.
In modulators applications, the upper quad transistors are used in a switching mode where the pairs Q1/Q2 and Q3/Q4 act as non saturating high speed switches. These switches are controlled by the signal often referred as the carrier input. The signal driving the lower pair Q5/Q6 is commonly used as the modulating input. This signal can be linearly transferred to the output by either the use of low signal levels (Well below the thermal voltage of 26mV) or by the use of emitter degeneration. The chopped waveform appearing at the output of the upper pair (Q1 to Q4) resembles a signal that is multiplied by +1 or -1 at every half cycle of the switching waveform.
Figure 1 shows the typical input waveforms where the frequency of the carrier is higher than the modulating signal. The output waveform shows a typical suppressed carrier output of an up converter or an AM signal generator.
Carrier suppression capability is a property of the well known Balanced modulator in which the output must be zero when one or the other input (carrier or modulating signal) is equal to zero. however, at very high frequencies, high frequency mismatches and AC offsets are always present and the suppression capability is often degraded causing carrier and modulating feedthrough to be present.
Being a frequency translation circuit, the balanced modulator has the properties of translating the modulating frequency (ωM) to the carrier frequency (ωC), generating the two side bands ωU = ωC + ωM and ωL = ωC - ωM. Figure 2 shows some translating schemes being used by balanced mixers.
CARRIER SIGNALMODULATING SIGNALDIFFERENTIAL OUTPUT+1-1FIGURE 1. TYPICAL MODULATOR SIGNALS
FIGURE 2A. UP CONVERSION OR SUPPRESSED CARRIER AM
FIGURE 2B. DOWN CONVERSION
FIGURE 2C. ZERO IF OR DIRECT DOWN CONVERSION
FIGURE 2. MODULATOR FREQUENCY SPECTRUM
ωC + ωMωC - ωMωC
IF (ωC - ωM)FOLDED BACKωMωC
BASEBANDωCωM
HFA3101
6
The use of the HFA3101 as modulators has several advantages when compared to its counterpart, the diode doublebalanced mixer, in which it is required to receive enough energy to drive the diodes into a switching mode and has also some requirements depending on the frequency range desired, of different transformers to suit specific frequency responses. The HFA3101 requires very low driving capabilities for its carrier input and its frequency response is limited by the fT of the devices, the design and the layout techniques being utilized.
Up conversion uses, for UHF transmitters for example, can be performed by injecting a modulating input in the range of 45MHz to 130MHz that carries the information often called IF (Intermediate frequency) for up conversion (The IF signal has been previously modulated by some modulation scheme from a baseband signal of audio or digital information) and by injecting the signal of a local oscillator of a much higher frequency range from 600MHz to 1.2GHz into the carrier input. Using the example of a 850MHz carrier input and a 70MHz IF, the output spectrum will contain a upper side band of 920MHz, a lower side band of 780MHz and some of the carrier (850MHz) and IF (70MHz) feedthrough. A Band pass filter at the output can attenuate the undesirable signals and the 920MHz signal can be routed to a transmitter RF power amplifier.
Down conversion, as the name implies, is the process used to translate a higher frequency signal to a lower frequency range conserving the modulation information contained in the higher frequency signal. One very common typical down conversion use for example, is for superheterodyne radio receivers where a translated lower frequency often referred as intermediate frequency (IF) is used for detection or demodulation of the baseband signal. Other application uses include down conversion for special filtering using frequency translation methods.
An oscillator referred as the local oscillator (LO) drives the upper quad transistors of the cell with a frequency called ωC. The lower pair is driven by the RF signal of frequency ωM to be translated to a lower frequency IF. The spectrum of the IF output will contain the sum and difference of the frequencies ωC and ωM. Notice that the difference can become negative when the frequency of the local oscillator is lower than the incoming frequency and the signal is folded back as in Figure 2.
NOTE: The acronyms RF, IF and LO are often interchanged in the industry depending on the application of the cell as mixers or modulators. The output of the cell also contains multiples of the frequency of the signal being fed to the upper quad pair of transistors because of the switching action equivalent to a square wave multiplication. In practice, however, not only the odd multiples in the case of a symmetrical square wave but some of the even multiples will also appear at the output spectrum due to the nature of the actual switching waveform and high frequency performance. By-products of the form M*ωC + N*ωM with M and N being positive or negative integers are also expected to be present at the output and their levels are carefully examined and minimized by the design. This distortion is considered one of the figures of merit for a mixer application.
The process of frequency doubling is also understood by having the same signal being fed to both modulating and carrier ports. The output frequency will be the sum of ωC and ωM which is equivalent to the product of the input frequency by 2 and a zero Hz or DC frequency equivalent to the difference of ωC and ωM. Figure 2 also shows one technique in use today where a process of down conversion named zero IF is made by using a local oscillator with a very pure signal frequency equal to the incoming RF frequency signal that contains a baseband (audio or digital signal) modulation. Although complex, the extraction or detection of the signal is straightforward.
Another useful application of the HFA3101 is its use as a high frequency phase detector where the two signals are fed to the carrier and modulation ports and the DC information is extracted from its output. In this case, both ports are utilized in a switching mode or overdrive, such that the process of multiplication takes place in a quasi digital form (2 square waves). One application of a phase detector is frequency or phase demodulation where the FM signal is split before the modulating and carrier ports. The lower input port is always 90 degrees apart from the carrier input signal through a high Q tuned phase shift network. The network, being tuned for a precise 90 degrees shift at a nominal frequency, will set the two signals 90 degrees apart and a quiescent output DC level will be present at the output. When the input signal is frequency modulated, the phase shift of the signal coming from the network will deviate from 90 degrees proportional to the frequency deviation of the FM signal and a DC variation at the output will take place, resembling the demodulated FM signal.
The HFA3101 could also be used for quadrature detection, (I/Q demodulation), AGC control with limited range, low level multiplication to name a few other applications.
Biasing
Various biasing schemes can be employed for use with the HFA3101. Figure 3 shows the most common schemes. The biasing method is a choice of the designer when cost, thermal dependence, voltage overheads and DC balancing properties are taken into consideration.
Figure 3A shows the simplest form of biasing the HFA3101. The current source required for the lower pair is set by the voltage across the resistor RBIAS less a VBE drop of the lower transistor. To increase the overhead, collector resistors are substituted by an RF choke as the upper pair functions as a current source for AC signals. The bases of the upper and lower transistors are biased by RB1 and RB2 respectively. The voltage drop across the resistor R2 must be higher than a VBE with an increase sufficient to assure that the collector to base junctions of the lower pair are always reverse biased. Notice that this same voltage also sets the VCE of operation of the lower pair which is important for the optimization of gain. Resistors REE are nominally zero for applications where the input signals are well below 25mV peak. Resistors REE are used to increase the linearity
HFA3101
3-7
of the circuit upon higher level signals. The drop across REE must be taken into consideration when setting the current source value.
Figure 3B depicts the use of a common resistor sharing the current through the cell which is used for temperature compensation as the lower pair VBE drop at the rate of -2mV/oC.
Figure 3C uses a split supply.
Design Example: Down Converter Mixer
Figure 4 shows an example of a low cost mixer for cellular applications.
The design flexibility of the HFA3101 is demonstrated by a low cost, and low voltage mixer application at the 900MHz range. The choice of good quality chip components with their self resonance outside the boundaries of the application are important. The design has been optimized to accommodate the evaluation of the same layout for various quiescent current values and lower supply voltages. The choice of RE became important for the available overhead and also for maintaining an AC true impedance for high frequency signals. The value of 27Ω has been found to be the optimum minimum for the application. The input impedances of the HFA3101 base input ports are high enough to permit their termination with 50Ω resistors. Notice the AC termination by decoupling the bias circuit through good quality capacitors.
The choice of the bias has been related to the available power supply voltage with the values of R1, R2 and RBIAS splitting the voltages for optimum VCE values. For evaluation of the cell quiescent currents, the voltage at the emitter resistor RE has been recorded.
The gain of the circuit, being a function of the load and the combined emitter resistances at high frequencies have been kept to a maximum by the use of an output match network. The high output impedance of the HFA3101 permits
FIGURE 3A.
FIGURE 3B.
FIGURE 3C.
FIGURE 3.
VCCRB1R1R2RBIASREREEREELCH12348765Q5Q6Q1Q2Q3Q4RB2
VCCRB1R1R2RBIASREREEREE12348765Q5Q6Q1Q2Q3Q4RB2RCLCH
VEERB1R1RBIASREREEREE12348765Q5Q6Q1Q2Q3Q4RB2VCCLCHR2
27LCH12348765Q5Q6Q1Q2Q3Q4VCC390nH0.010.011102200.1VCC3V75MHz2K5p TO 12pLO IN51825MHz51900MHzIF OUTRF IN0.010.010.01330FIGURE 4. 3V DOWN CONVERTER APPLICATION
HFA3101
8
broadband match if so desired at 50Ω (RL = 50Ω to 2kΩ) as well as with tuned medium Q matching networks (L, T etc.).
Stability
The cell, by its nature, has very high gain and precautions must be taken to account for the combination of signal reflections, gain, layout and package parasitics. The rule of thumb of avoiding reflected waves must be observed. It is important to assure good matching between the mixer stage and its front end. Laboratory measurements have shown some susceptibility for oscillation at the upper quad transistors input. Any LO prefiltering has to be designed such the return loss is maintained within acceptable limits specially at high frequencies. Typical off the shelf filters exhibits very poor return loss for signals outside the passband. It is suggested that a “pad” or a broadband resistive network be used to interface the LO port with a filter. The inclusion of a parallel 2K resistor in the load decreases the gain slightly which improves the stability factor and also improves the distortion products (output intermodulation or 3rd order intercept). The employment of good RF techniques shall suffice the stability requirements.
Evaluation
The evaluation of the HFA3101 in a mixer configuration is presented in Figures 6 to 11, Table 1 and Table 2. The layout is depicted in Figure 5.
The output matching network has been designed from data taken at the output port at various test frequencies with the setup as in Table 1. S22 characterization is enough to assure the calculation of L, T or transmission line matching networks.
FIGURE 5. UP/DOWN CONVERTER LAYOUT, 400%; MATERIAL G10, 0.031
TABLE 1. S22 PARAMETERS FOR DOWN CONVERSION, LCH = 10μH
FREQUENCY
RESISTANCE
REACTANCE
10MHz
265Ω
615Ω
45MHz
420Ω
- 735Ω
75MHz
122Ω
- 432Ω
100MHz
67Ω
- 320Ω
TABLE 2. TYPICAL PARAMETERS FOR DOWN CONVERSION, LCH = 10μH
PARAMETER
LO LEVEL
VCC = 3V, IBIAS = 8mA
Power Gain
-6dBm
8.5dB
TOI Output
-6dBm
11.5dBm
NF SSB
-6dBm
14.5dB
Power Gain
0dBm
8.6dB
TOI Output
0dBm
11dBm
NF SSB
0dBm
15dB
PARAMETER
LO LEVEL
VCC = 4V, IBIAS = 19mA
Power Gain
-6dBm
10dB
TOI Output
-6dBm
13dBm
NF SSB
-6dBm
20dB
Power Gain
0dBm
11dB
TOI Output
0dBm
12.5dBm
NF SSB
0dBm
24dB
TABLE 3. TYPICAL VALUES OF S22 FOR THE OUTPUT PORT. LCH = 390nH IBIAS = 8mA (SET UP OF FIGURE 11)
FREQUENCY
RESISTANCE
REACTANCE
300MHz
22Ω
-115Ω
600MHz
7.5Ω
-43Ω
900MHz
5.2Ω
-14Ω
1.1GHz
3.9Ω
0Ω
TABLE 4. TYPICAL VALUES OF S22. LCH = 390nH, IBIAS = 18mA
FREQUENCY
RESISTANCE
REACTANCE
300MHz
23.5Ω
-110Ω
600MHz
10.3Ω
-39Ω
900MHz
8.7Ω
-14Ω
1.1GHz
8Ω
0Ω
HFA3101
3-9
Up Converter Example
An application for a up converter as well as a frequency multiplier can be demonstrated using the same layout, with an addition of matching components. The output port S22 must be characterized for proper matching procedures and depending on the frequency desired for the output, transmission line transformations can be designed. The return loss of the input ports maintain acceptable values in excess of 1.2GHz which can permit the evaluation of a frequency doubler to 2.4GHz if so desired.
The addition of the resistors REE can increase considerably the dynamic range of the up converter as demonstrated at Figure 13. The evaluation results depicted in Table 5 have been obtained by a triple stub tuner as a matching network for the output due to the layout constraints. Based on the evaluation results it is clear that the cell requires a higher Bias current for overall performance.
FIGURE 6. OUTPUT PORT S22 TEST SET UP
FIGURE 7. LO PORT RETURN LOSS
FIGURE 8. RF PORT RETURN LOSS
FIGURE 9. IF PORT RETURN LOSS, WITH MATCHING NETWORK
FIGURE 10. TYPICAL IN BAND OUTPUT SPECTRUM, VCC = 3V
FIGURE 11. TYPICAL OUT OF BAND OUTPUT SPECTRUM
VCC 3V0.1LCH12348765Q5Q6Q1Q2Q3Q42K
S110dB5dB/DIV100MHz1.1GHzLOG MAG3V4V
0dB10dB/DIV100MHz1.1GHzS11LOG MAG
0dB5dB/DIV10MHzS22LOG MAG110MHz
76MHz64M11*LO - 10RF88M12RF - 13LOIFSPAN40MHzLO = 825MHz -6dBmRF = 901MHz - 25dBm-17dBm10dB/DIV
67575082590097510dB/DIVLO + 2RFSPAN500MHzLO - 2RF-26dBm-36dBm-58dBm-53dBmLO = 825MHz -6dBmRF = 900MHz -25dBm
HFA3101
10
Design Example: Up Converter Mixer
Figure 12 shows an example of an up converter for cellular applications.
Conclusion
The HFA3101 offers the designer a number of choices and different applications as a powerful RF building block. Although isolation is degraded from the theoretical results for the cell due to the unbalanced, nondifferential input schemes being used, a number of advantages can be taken into consideration like cost, flexibility, low power and small outline when deciding for a design.
TABLE 5. TYPICAL PARAMETERS FOR THE UP CONVERTER EXAMPLE
PARAMETER
VCC = 3V, IBIAS = 8mA
VCC = 4V, IBIAS = 18mA
Power Gain, LO = -6dBm
3dB
5.5dBm
Power Gain, LO = 0dBm
4dB
7.2dB
RF Isolation, LO = 0dBm
15dBc
22dBc
LO Isolation, LO = 0dBm
28dBc
28dBc
FIGURE 12. UP CONVERTER
FIGURE 13. TYPICAL SPECTRUM PERFORMANCE OF UP CONVERTER
RF IN0.01390nH900MHz5.2nHVCC 3V0.112348765Q5Q6Q1Q2Q3Q411p0.0175MHz27220REEREE51LO INVCC0.010.011103303V825MHz0.010.015147-100pF
9019128902LO - 10RF12RFOUTPUT WITHOUT EMITTER DEGENERATIONRF = 76MHzLO = 825MHzSPAN50MHzOUTPUT WITH EMITTER DEGENERATION REE = 4.7Ω825900976EXPANDED SPECTRUM REE = 4.7Ω
HFA3101
3-11
Typical Performance Curves for Transistors
FIGURE 14. IC vs VCE
FIGURE 15. HFE vs IC
FIGURE 16. GUMMEL PLOT
FIGURE 17. fT vs IC
FIGURE 18. GAIN AND NOISE FIGURE vs FREQUENCY
NOTE: Figures 14 through 18 are only for Q5 and Q6.
VCE (V)IC (mA)02.06.04.0070605040302010IB = 800μAIB = 1mAIB = 200μAIB = 400μAIB = 600μA
hFEIC (
A)10-1010-810-610-410-2100140120100806040200VCE = 5V
VBE (V)IC AND IB (A)10-1010-810-610-410-210010-120.200.400.600.801.0VCE = 3V
IC (A)fT (GHz)12108642010-410-310-210-1
20181614121046NOISE FIGURE (
dB)FREQUENCY (GHz)|S21| (dB)0.51.51.02.002.53.04.84.64.44.24.03.83.63.43.28
HFA3101
12
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable.
However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Die Characteristics
PROCESS UHF-1
DIE DIMENSIONS: 53 mils x 52 mils x 14 mils
1340μm x 1320μm x 355.6μm
METALLIZATION: Type: Metal 1: AlCu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.5kÅ Type: Metal 2: AlCu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
PASSIVATION: Type: Nitride
Thickness: 4kÅ ±0.5kÅ
SUBSTRATE POTENTIAL (Powered Up): Floating
Metallization Mask Layout
HFA31011122334455667788
HFA3101
16-Bit Low Power Sigma-Delta ADC
Data Sheet AD7171
Rev. A Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Output data rate: 125 Hz
Pin-programmable power-down and reset
Status function
Internal clock oscillator
Current: 135 μA
Power supply: 2.7 V to 5.25 V
–40°C to +105°C temperature range
Package: 10-lead 3 mm x 3 mm LFCSP
INTERFACE
2-wire serial (read-only device)
SPI compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Pressure measurement
Industrial process control
Portable instrumentation
FUNCTIONAL BLOCK DIAGRAM
16-BIT Σ-ΔADCAD7171GNDINTERNALCLOCKVDDREFIN(+)AIN(+)AIN(–)REFIN(–)DOUT/RDYSCLKPDRST08417-001
Figure 1.
Table 1.
VREF = VDD
RMS Noise
P-P Noise
P-P Resolution
ENOB
5 V
11.5 μV
76 μV
16 bits
16 bits
3 V
6.9 μV
45 μV
16 bits
16 bits
GENERAL DESCRIPTION
The AD7171 is a very low power 16-bit analog-to-digital converter (ADC). It contains a precision 16-bit sigma-delta (Σ-Δ) ADC and an on-chip oscillator. Consuming only 135 μA, the AD7171 is particularly suitable for portable or battery operated products where very low power is a requirement. The AD7171 also has a power-down mode in which the device consumes 5 μA, thus increasing the battery life of the product.
For ease-of-use, all the features of the AD7171 are controlled by dedicated pins. Each time a data read occurs, eight status bits are appended to the 16-bit conversion. These status bits contain a pattern sequence that can be used to confirm the validity of the serial transfer.
The output data rate of the AD7171 is 125 Hz, whereas the settling time is 24 ms. The AD7171 has one differential input and a gain of 1. This is useful in applications where the user needs to use an external amplifier to implement system-specific filtering or gain requirements.
The AD7171 operates with a power supply from 2.7 V to 5.25 V. It is available in a 10-lead LFCSP package.
The AD7170 is a 12-bit version of the AD7171. It has the same feature set as the AD7171 and is pin-for-pin compatible.
1
Low-Noise 24-bit Delta Sigma ADC
ISL26132, ISL26134
The ISL26132 and ISL26134 are complete analog front ends
for high resolution measurement applications. These 24-bit
Delta-Sigma Analog-to-Digital Converters include a very
low-noise amplifier and are available as either two or four
differential multiplexer inputs. The devices offer the same
pinout as the ADS1232 and ADS1234 devices and are
functionally compatible with these devices. The ISL26132 and
ISL26134 offer improved noise performance at 10Sps and
80Sps conversion rates.
The on-chip low-noise programmable-gain amplifier provides
gains of 1x/2x/64x/128x. The 128x gain setting provides an
input range of ±9.766mVFS when using a 2.5V reference. The
high input impedance allows direct connection of sensors such
as load cell bridges to ensure the specified measurement
accuracy without additional circuitry. The inputs accept signals
100mV outside the supply rails when the device is set for unity
gain.
The Delta-Sigma ADC features a third order modulator
providing up to 21.6-bit noise-free performance.
The device can be operated from an external clock source,
crystal (4.9152MHz typical), or the on-chip oscillator.
The two channel ISL26132 is available in a 24 Ld TSSOP
package and the four channel ISL26134 is available in a 28 Ld
TSSOP package. Both are specified for operation over the
automotive temperature range (-40°C to +105°C).
Features
• Up to 21.6 Noise-free bits.
• Low Noise Amplifier with Gains of 1x/2x/64x/128x
• RMS noise: 10.2nV @ 10Sps (PGA = 128x)
• Linearity Error: 0.0002% FS
• Simultaneous rejection of 50Hz and 60Hz (@ 10Sps)
• Two (ISL26132) or four (ISL26134) channel differential
input multiplexer
• On-chip temperature sensor (ISL26132)
• Automatic clock source detection
• Simple interface to read conversions
• +5V Analog, +5 to +2.7V Digital Supplies
• Pb-Free (RoHS Compliant)
• TSSOP packages: ISL26132, 24 pin; ISL26134, 28 pin
Applications
• Weigh Scales
• Temperature Monitors and Controls
• Industrial Process Control
• Pressure Sensors
ADC
PGA
1x/2x/64x/
128x
INTERNAL
CLOCK
SDO/RDY
SCLK
AVDD DVDD
AGND DGND
XTALIN/CLOCK
VREF+
EXTERNAL
OSCILLATOR
XTALOUT
A0 A1/TEMP VREFAIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
INPUT
MULTIPLEXER
ISL26134
Only
CAP
CAP
GAIN0 GAIN1
PWDN
SPEED
DGND DGND
NOTE for A1/TEMP pin: Functions as A1 on ISL26134; Functions as TEMP on ISL26132
FIGURE 1. BLOCK DIAGRAM
September 9, 2011
FN6954.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL26132, ISL26134
2 FN6954.1
September 9, 2011
Ordering Information
PART NUMBER
(Notes 2, 3) PART MARKING
TEMPERATURE RANGE
(°C)
PACKAGE
(Pb-free)
PKG. DWG
NUMBER
ISL26132AVZ 26132 AVZ -40 to +105 24 Ld TSSOP M24.173
ISL26132AVZ-T (Note 1) 26132 AVZ -40 to +105 24 Ld TSSOP (Tape & Reel) M24.173
ISL26132AVZ-T7A (Note 1) 26132 AVZ -40 to +105 24 Ld TSSOP (Tape & Reel) M24.173
ISL26134AVZ 26134 AVZ -40 to +105 28 Ld TSSOP M28.173
ISL26134AVZ-T (Note 1) 26134 AVZ -40 to +105 28 Ld TSSOP (Tape & Reel) M28.173
ISL26134AVZ-T7A (Note 1) 26134 AVZ -40 to +105 28 Ld TSSOP (Tape & Reel) M28.173
ISL26134AV28EV1Z Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL26132, ISL26134. For more information on MSL please see techbrief
TB363.
TABLE 1. KEY DIFFERENCES OF PARTS
PART NUMBER NUMBER OF CHANNELS ON-CHIP TEMPERATURE SENSOR NUMBER OF PINS
ISL26132 2 YES 24
ISL26134 4 NO 28
Pin Configurations
ISL26132
(24 LD TSSOP)
TOP VIEW
ISL26134
(28 LD TSSOP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
DVDD
DGND
XTALIN/CLOCK
XTALOUT
DGND
DGND
TEMP
A0
CAP
CAP
AIN1+
AIN1-
SDO/RDY
PDWN
SPEED
GAIN1
GAIN0
AGND
VREFAIN2+
AIN2-
SCLK
AVDD
VREF+
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DVDD
DGND
XTALIN/CLOCK
XTALOUT
DGND
DGND
A1
A0
CAP
CAP
AIN1+
AIN1-
AIN3+
AIN3-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SDO/RDY
PDWN
SPEED
GAIN1
GAIN0
AGND
VREFAIN2+
AIN2-
AIN4+
AIN4-
SCLK
AVDD
VREF+
ISL26132, ISL26134
3 FN6954.1
September 9, 2011
Pin Descriptions
NAME
PIN NUMBER
ANALOG/DIGITAL
ISL26132 ISL26134 INPUT/OUTPUT DESCRIPTION
DVDD 1 1 Digital Digital Power Supply (2.7V to 5.25V)
DGND 2, 5, 6 2, 5, 6 Digital Digital Ground
XTALIN/CLOCK 3 3 Digital/Digital Input External Clock Input: typically 4.9152MHz. Tie low to activate
internal oscillator. Can also use external crystal across
XTALIN/CLOCK and XTALOUT pins.
XTALOUT 4 4 Digital External Crystal connection
TEMP 7 - Digital Input On-chip Temperature Diode Enable
A1
A0
-
8
7
8
Digital Input
CAP 9, 10 9, 10 Analog PGA Filter Capacitor
AIN1+ 11 11 Analog Input Positive Analog Input Channel 1
AIN1- 12 12 Analog Input Negative Analog Input Channel 1
AIN3+ - 13 Analog Input Positive Analog Input Channel 3
AIN3- - 14 Analog Input Negative Analog Input Channel 3
AIN4- - 15 Analog Input Negative Analog Input Channel 4
AIN4+ - 16 Analog Input Positive Analog Input Channel 4
AIN2- 13 17 Analog Input Negative Analog Input Channel 2
AIN2+ 14 18 Analog Input Positive Analog Input Channel 2
VREF- 15 19 Analog Input Negative Reference Input
VREF+ 16 20 Analog Input Positive Reference Input
AGND 17 21 Analog Analog Ground
AVDD 18 22 Analog Analog Power Supply 4.75V to 5.25V
GAIN0
GAIN1
19
20
23
24
Digital Input
TABLE 2. INPUT MULTIPLEXER SELECT
ISL26134 ISL26132
A1 A0 CHANNEL
0 0 AIN1
0 1 AIN2
1 0 AIN3
1 1 AIN4
TABLE 3. GAIN SELECT
GAIN1 GAIN0 GAIN
0 0 1
0 1 2
1 0 64
1 1 128
ISL26132, ISL26134
4 FN6954.1
September 9, 2011
Circuit Description
The ISL26132 (2-channel) and ISL26134 (4-channel) devices are
very low noise 24-bit delta-sigma ADCs that include a
programmable gain amplifier and an input multiplexer. The
ISL26132 offers an on-chip temperature measurement
capability.
The ISL26132, ISL26134 provide pin compatibility and output
data compatibility with the ADS1232/ADS1234, and offer the
same conversion rates of 10Sps and 80Sps.
All the features of the ISL26132, ISL26134 are pin-controllable,
while offset calibration, standby mode, and output conversion
data are accessible through a simple 2-wire interface.
The clock can be selected to come from an internal oscillator, an
external clock signal, or crystal (4.9152MHz typical).
SPEED 21 25 Digital Input
PDWN 22 26 Digital Input Power-Down: Holding this pin low powers down the entire
converter and resets the ADC.
SCLK 23 27 Digital Input Serial Clock: Clock out data on the rising edge. Also used to
initiate Offset Calibration and Sleep modes. See “Serial Clock
Input (SCLK)” on page 14 for more details.
SDO/RDY 24 28 Digital Output Dual-Purpose Output:
Data Ready: Indicate valid data by going low.
Data Output: Outputs data, MSB first, on the first rising edge
of SCLK.
Pin Descriptions (Continued)
NAME
PIN NUMBER
ANALOG/DIGITAL
ISL26132 ISL26134 INPUT/OUTPUT DESCRIPTION
TABLE 4. DATA RATE SELECT
SPEED DATA RATE
0 10Sps
1 80Sps
ISL26132, ISL26134
5 FN6954.1
September 9, 2011
Absolute Maximum Ratings Thermal Information
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Analog In to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to AVDD+0.3V
Digital In to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to DVDD+0.3V
Input Current
Momentary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . . .7.5kV
Machine Model (Per JESD22-A115). . . . . . . . . . . . . . . . . . . . . . . . . . 450V
Charged Device Model (Per JESD22-C101) . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Latch-up (Per JEDEC JESD-78B; Class 2, Level A)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA @ Room and Hot (+105°C)
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
24 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . . 65 18
28 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . . 63 18
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VREF+ = 5V, VREF- = 0V, AVDD = 5V, DVDD = 5V, AGND = DGND = 0V, MCLK = 4.9152MHz, and
TA = -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C
SYMBOL PARAMETER TEST LEVEL or NOTES
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ANALOG INPUTS
Differential Input Voltage Range ±0.5VREF/
Gain
V
Common Mode Input Voltage
Range
Gain = 1, 2 AGND - 0.1 AVDD + 0.1 V
Gain = 64, 128 AGND+1.5 AVDD - 1.5 V
Differential Input Current
Gain = 1 ±20 nA
Gain = 2 ±40 nA
Gain = 64, 128 ±1 nA
SYSTEM PERFORMANCE
Resolution No Missing Codes 24 Bits
Data Rate
Internal Osc. SPEED = High 80 SPS
Internal Osc. SPEED = Low 10 SPS
External Osc. SPEED = High fCLK/61440 SPS
External Osc. SPEED = Low fCLK/49152
0
SPS
Digital Filter Settling Time Full Setting 4 Conversions
INL Integral Nonlinearity Differential Input Gain = 1, 2 ±0.0002 ±0.001 % of FSR (Note 7)
Differential Input Gain = 64, 128 ±0.0004 % of FSR
(Note 7)
Input Offset Error Gain = 1 ±0.4 ppm of FS
Gain = 128 ±1.5 ppm of FS
Input Offset Drift Gain = 1 0.3 μV/°C
Gain = 128 10 nV/°C
Gain Error (Note 8) Gain = 1 ±0.007 ±0.02 %
Gain = 128 ±0.02 %
Gain Drift Gain = 1 0.5 ppm/°C
Gain = 128 7 ppm/°C
ISL26132, ISL26134
6 FN6954.1
September 9, 2011
CMRR Common Mode Rejection At DC, Gain = 1, ΔV = 1V 85 100 dB
At DC, Gain = 128, ΔV = 0.1V 100 dB
50Hz/60Hz Rejection (Note 9) External 4.9152MHz Clock 130 dB
PSRR Power Supply Rejection At DC, Gain = 1, ΔV = 1V 82 100 dB
At DC, Gain = 128, ΔV = 0.1V 100 105 dB
Input Referred Noise See “Typical Characteristics” beginning
on page 8
Noise Free Bits See “Typical Characteristics” beginning
on page 8
VOLTAGE REFERENCE INPUT
VREF Voltage Reference Input VREF = VREF+ - VREF- 1.5 AVDD AVDD + 0.1 V
VREF- Negative Reference Input AGND - 0.1 VREF+ - 1.5 V
VREF+ Positive Reference Input VREF- + 1.5 AVDD + 0.1 V
IREF Voltage Reference Input Current ±350 nA
POWER SUPPLY REQUIREMENTS
AVDD Analog Supply Voltage 4.75 5.0 5.25 V
DVDD Digital Supply Voltage 2.7 3.3 5.25 V
AIDD Analog Supply Current Normal Mode, AVDD = 5, Gain = 1, 2 7 8.5 mA
Normal Mode, AVDD = 5, Gain = 64, 128 9 12 mA
Standby Mode 0.2 3 μA
Power-Down 0.2 2.5 μA
DIDD Digital Supply Current Normal Mode, AVDD = 5, Gain = 1, 2 750 950 μA
Normal Mode, AVDD = 5, Gain = 64, 128 750 950 μA
Standby Mode 1.5 26 μA
Power-Down 1 26 μA
PD Power Dissipation, Total Normal Mode, AVDD = 5, Gain = 1, 2 49.6 mW
Normal Mode, AVDD = 5, Gain = 64, 128 68 mW
Standby Mode 0.14 mW
Power-Down 0.14 mW
DIGITAL INPUTS
VIH 0.7 DVDD V
VIL 0.2 DVDD V
VOH IOH = -1mA DVDD - 0.4 V
VOL IOL = 1mA 0.2 DVDD V
Input Leakage Current ±10 μA
External Clock Input Frequency 0.3 4.9152 MHz
Serial Clock Input Frequency 1 MHz
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. FSR = Full Scale Range = VREF/Gain
8. Gain accuracy is calibrated at the factory (AVDD = +5V).
9. Specified for word rate equal to 10Sps.
Electrical Specifications VREF+ = 5V, VREF- = 0V, AVDD = 5V, DVDD = 5V, AGND = DGND = 0V, MCLK = 4.9152MHz, and
TA = -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C (Continued)
SYMBOL PARAMETER TEST LEVEL or NOTES
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ISL26132, ISL26134
7 FN6954.1
September 9, 2011
Noise Performance
The ISL26132 and ISL26134 provide excellent noise
performance. The noise performance on each of the gain
settings of the PGA at the selected word rates is shown in
Tables 5 and 6.
Resolution in bits decreases by 1-bit if the ADC is operated as a
single-ended input device. Noise measurements are
input-referred, taken with bipolar inputs under the specified
operating conditions, with fCLK = 4.9152MHz.
TABLE 5. AVDD = 5V, VREF = 5V, DATA RATE = 10Sps
GAIN
RMS NOISE
(nV)
PEAK-TO-PEAK NOISE
(nV) (Note 10)
NOISE-FREE BITS
(Note 11)
1 243 1604 21.6
2 148 977 21.3
64 10.8 71 20.1
128 10.2 67 19.1
TABLE 6. AVDD = 5V, VREF = 5V, DATA RATE = 80Sps
GAIN
RMS NOISE
(nV)
PEAK-TO-PEAK NOISE
(nV) (Note 10)
NOISE-FREE BITS
(Note 11)
1 565 3730 20.4
2 285 1880 20.3
64 28.3 187 18.7
128 27 178 17.7
NOTES:
10. The peak-to-peak noise number is 6.6 times the rms value. This
encompasses 99.99% of the noise excursions that may occur. This
value best represents the worst case noise that could occur in the
output conversion words from the converter.
11. Noise-Free Bits is defined as: Noise-Free Bits = ln(FSR/peak-to-peak
noise)/ln(2) where FSR is the full scale range of the converter,
VREF/Gain.
ISL26132, ISL26134
8 FN6954.1
September 9, 2011
Typical Characteristics
FIGURE 2. NOISE AT GAIN = 1, 10Sps FIGURE 3. NOISE HISTOGRAM AT GAIN = 1, 10Sps
FIGURE 4. NOISE AT GAIN = 2, 10Sps FIGURE 5. NOISE HISTOGRAM AT GAIN = 2, 10Sps
FIGURE 6. NOISE AT GAIN = 64, 10Sps FIGURE 7. NOISE HISTOGRAM AT GAIN = 64, 10Sps
-10
-5
0
5
10
0 200 400 600 800 1000
GAIN = 1
RATE = 10Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
50
100
150
200
250
300
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
OUTPUT CODE (LSB)
GAIN = 1, N = 1024
RATE = 10Sps
STD DEV = 1.635 LSB
VREF = 2.5V
COUNTS -
10
-5
0
5
10
0 200 400 600 800 1000
TIME (SAMPLES)
OUTPUT CODE (LSB)
GAIN = 2
RATE = 10Sps
0
50
100
150
200
250
-8 -6 -4 -2 0 2 4 6 8
GAIN = 2, N = 1024
RATE = 10Sps
STD DEV = 1.989 LSB
VREF = 2.5V
OUTPUT CODE (LSB)
COUNTS
-15
-10
-5
0
5
10
15
20
0 200 400 600 800 1000
TIME (SAMPLES)
OUTPUT CODE (LSB)
GAIN = 64
RATE = 10Sps
0
20
40
60
80
100
120
-20 -15 -10 -5 0 5 10 15 20
GAIN = 64, N = 1024
RATE = 10Sps
STD DEV = 4.627 LSB
VREF = 2.5V
OUTPUT CODE (LSB)
COUNTS
ISL26132, ISL26134
9 FN6954.1
September 9, 2011
FIGURE 8. NOISE AT GAIN = 128, 10Sps FIGURE 9. NOISE HISTOGRAM AT GAIN = 128, 10Sps
FIGURE 10. NOISE AT GAIN = 1, 80Sps FIGURE 11. NOISE HISTOGRAM AT GAIN = 1, 80Sps
FIGURE 12. NOISE AT GAIN = 2, 80Sps FIGURE 13. NOISE HISTOGRAM AT GAIN = 2, 80Sps
Typical Characteristics (Continued)
-50
-30
-10
10
30
50
0 200 400 600 800 1000
GAIN = 128
RATE = 10Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
10
20
30
40
50
60
-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30
OUTPUT CODE (LSB)
COUNTS
GAIN = 128, N = 1024
RATE = 10Sps
STD DEV = 8.757 LSB
VREF = 2.5V
-25
-20
-15
-10
-5
0
5
10
15
20
25
0 200 400 600 800 1000
GAIN = 1
RATE = 80Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
20
40
60
80
100
120
-15 -10 -5 0 5 10 15
OUTPUT CODE (LSB)
COUNTS
GAIN = 1, N = 1024
RATE = 80Sps
STD DEV = 3.791 LSB
VREF = 2.5V
-25
-15
-5
5
15
25
0 200 400 600 800 1000
GAIN = 2
RATE = 80Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
20
40
60
80
100
120
-15 -10 -5 0 5 10 15
OUTPUT CODE (LSB)
COUNTS
GAIN = 2, N = 1024
RATE = 80Sps
STD DEV = 3.831 LSB
VREF = 2.5V
ISL26132, ISL26134
10 FN6954.1
September 9, 2011
FIGURE 14. NOISE AT GAIN = 64, 80Sps FIGURE 15. NOISE HISTOGRAM AT GAIN = 64, 80Sps
FIGURE 16. NOISE AT GAIN = 128, 80Sps FIGURE 17. NOISE HISTOGRAM AT GAIN = 128, 80Sps
FIGURE 18. ANALOG CURRENT vs TEMPERATURE FIGURE 19. DIGITAL CURRENT vs TEMPERATURE
Typical Characteristics (Continued)
-100
-50
0
50
100
0 200 400 600 800 1000
GAIN = 64
RATE = 80Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
10
20
30
40
50
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40
OUTPUT CODE (LSB)
COUNTS
GAIN = 64, N = 1024
RATE = 80Sps
STD DEV = 12.15 LSB
VREF = 2.5V
-200
-160
-120
-80
-40
0
40
80
120
160
0 200 400 600 800 1000
GAIN = 128
RATE = 80Sps
TIME (SAMPLES)
OUTPUT CODE (LSB)
0
5
10
15
20
25
30
-80 -60 -40 -20 0 20 40 60 80
OUTPUT CODE (LSB)
COUNTS
GAIN = 128, N = 1024
RATE = 80Sps
STD DEV = 23.215 LSB
VREF = 2.5V
0
2
4
6
8
10
-40 -10 20 50 80 110
TEMPERATURE (°C)
CURRENT (mA)
NORMAL MODE, PGA = 64.128
NORMAL MODE, PGA = 1, 2
1
10
100
1000
10000
-40 -10 20 50 80 110
TEMPERATURE (°C)
CURRENT (μA)
NORMAL MODE, ALL PGA GAINS
POWERDOWN MODE
ISL26132, ISL26134
11 FN6954.1
September 9, 2011
FIGURE 20. TYPICAL WORD RATE vs TEMPERATURE USING
INTERNAL OSCILLATOR
FIGURE 21. NOISE DENSITY vs FREQUENCY AT GAIN = 1, 80Sps
FIGURE 22. NOISE DENSITY vs FREQUENCY AT GAIN = 128, 80Sps
Typical Characteristics (Continued)
9.6
9.8
10.0
10.2
10.4
10.6
10.8
11.0
-40 -10 20 50 80 110
TEMPERATURE (°C)
DATA RATE (Sps)
WORD RATE = 10Sps
10
100
1000
10000
0.01 0.1 1 10
FREQUENCY (Hz)
NOISE (nV/√Hz)
GAIN = 1, 80Sps
64k FFT
25 AVERAGES
1
10
100
0.01 0.1 1 10
FREQUENCY (Hz)
NOISE (nV/√Hz)
GAIN = 128, 80Sps
64k FFT
25 AVERAGES
ISL26132, ISL26134
12 FN6954.1
September 9, 2011
Functional Description
Analog Inputs
The analog signal inputs to the ISL26132 connect to a 2-Channel
differential multiplexer and the ISL26134 connect to a 4-Channel
differential multiplexer (Mux). The multiplexer connects a pair of
inputs to the positive and negative inputs (AINx+, AINx-), selected
by the Channel Select Pins A0 and A1 (ISL26134 only). Input
channel selection is shown in Table 7. On the ISL26132, the
TEMP pin is used to select the Temperature Sensor function.
Whenever the MUX channel is changed (i.e. if any one of the
following inputs - A0/A1, Gain1/0, SPEED is changed), the
digital logic will automatically restart the digital filter and will
cause SDO/RDY to go low only when the output is fully settled.
But if the input itself is suddenly changed, then the user needs to
ignore first four RDY pulses (going low) to get an accurate
measurement of the input signal.
The input span of the ADC is ±0.5 VREF/GAIN. For a 5V VREF and
a gain of 1x, the input span will be 5VP-P fully differential as
shown in Figure 23. Note that input voltages that exceed the
supply rails by more than 100mV will turn on the ESD protection
diodes and degrade measurement accuracy.
If the differential input exceeds well above the +VE or the -VE FS
(by ~1.5x times) the output code will clip to the corresponding FS
value. Under such conditions, the output data rate will become
1/4th of the original value as the Digital State Machine will
RESET the Delta-Sigma Modulator and the Decimation Filter.
Temperature Sensor (ISL26132 only)
When the TEMP pin of the ISL26132 is set High, the input
multiplexer is connected to a pair of diodes, which are scaled in
both size and current. The voltage difference measured between
them corresponds to the temperature of the die according to
Equation 1:
Note: Valid only for GAIN = 1x or 2x
Where T is the temperature of the die, and Gain = the PGA Gain
Setting.
At a temperature of +25°C, the measured voltage will be
approximately 111.7mV. Note that this measurement indicates
only the temperature of the die itself. Applying the result to
correct for the temperature drift of a device external to the
package requires that thermal coupling between the sensor and
the die be taken into account.
Low-Noise Programmable Gain Amplifier
(PGA)
The chopper-stabilized programmable gain amplifier features a
variety of gain settings to achieve maximum dynamic range and
measurement accuracy from popular sensor types with excellent
low noise performance, input offset error, and low drift, and with
minimal external parts count. The GAIN0 and GAIN1 pins allow the
user to select gain settings of 1x, 2x, 64x, or 128x. A block diagram
is shown in Figure 24. The differential input stage provides a gain of
64, which is bypassed when the lower gain settings are selected.
The lower gain settings (1 and 2) will accept inputs with common
mode voltages up to 100mV outside the rails, allowing the device to
accept ground-referred signals. At gain settings of 64 or 128 the
common mode voltage at the inputs is limited to 1.5V inside the
supply rails while maintaining specified measurement accuracy.
TABLE 7. INPUT CHANNEL SELECTION
CHANNEL SELECT PINS ANALOG INPUT PINS SELECTED
A1 A0 AIN+ AIN-
0 0 AIN1+ AIN1-
0 1 AIN2+ AIN2-
1 0 AIN3+ AIN3-
1 1 AIN4+ AIN4-
3.75
2.50
1.25
1.25V
INPUT VOLTAGE RANGE = ±0.5VREF/GAIN
VREF = 5V, GAIN = 1X
3.75
2.50
1.25
AIN+
AIN-
2.50V
FIGURE 23. DIFFERENTIAL INPUT FOR VREF = 5V, GAIN = 1X
V= 102.2mV + (379μV∗T(°C))∗Gain
(EQ. 1)
ISL26132, ISL26134
13 FN6954.1
September 9, 2011
Filtering PGA Output Noise
The programmable gain amplifier, as shown in Figure 24,
includes a passive RC filter on its output. The resistors are
located inside the chip on the outputs of the differential amplifier
stages. The capacitor (nominally a 100nF C0G ceramic or a PPS
film (Polyphenylene sulfide)) for the filter is connected to the two
CAP pins of the chip. The outputs of the differential amplifier
stages of the PGA are filtered before their signals are presented
to the delta-sigma modulator. This filter reduces the amount of
noise by limiting the signal bandwidth and filters the chopping
artifacts of the chopped PGA stage.
Voltage Reference Inputs (VREF+, VREF-)
The voltage reference for the ADC is derived from the difference
in the voltages presented to the VREF+ and VREF- pins;
VREF = (VREF+ - VREF-). The ADCs are specified with a voltage
reference value of 5V, but a voltage reference as low as 1.5V can
be used. For proper operation, the voltage on the VREF+ pin
should not be greater than AVDD + 0.1V and the voltage on the
VREF- pin should not be more negative than AGND - 0.1V.
Clock Sources
The ISL26132, ISL26134 can operate from an internal oscillator,
an external clock source, or from a crystal connected between
the XTALIN/CLOCK and XTALOUT pins. See the block diagram of
the clock system in Figure 25. When the ADC is powered up, the
CLOCK DETECT block determines if an external clock source is
present. If a clock greater than 300kHz is present on the
XTALIN/CLOCK pin, the circuitry will disable the internal oscillator
on the chip and use the external clock as the clock to drive the
chip circuitry. If the ADC is to be operated from the internal
oscillator, the XTALIN/CLOCK pin should be grounded.
If the ADC is to be operated from a crystal, it should be located
close to the package pins of the ADC. Note that external loading
capacitors for the crystal are not required as there are loading
capacitors built into the silicon, although the capacitor values are
optimized for operation with a 4.9152MHz crystal.
The XTALOUT pin is not intended to drive external circuits.
Digital Filter Characteristics
The digital filter inside the ADC is a fourth-order Siinc filter.
Figures 26 and 27 illustrate the filter response for the ADC when
it is operated from a 4.9152MHz crystal. The internal oscillator is
factory trimmed so the frequency response for the filter will be
much the same when using the internal oscillator. The figures
illustrate that when the converter is operated at 10Sps the digital
filter provides excellent rejection of 50Hz and 60Hz line
interference.
FIGURE 24. SIMPLIFIED PROGRAMMABLE GAIN AMPLIFIER BLOCK DIAGRAM
+
-
A1
-
+
A2
AINx-
AINx+
ADC
RINT
RINT
R1
RF1
RF2
CAP
CAP
FIGURE 25. CLOCK BLOCK DIAGRAM
XTALIN/
CRYSTAL
OSCILLATOR
XTALOUT
TO ADC
INTERNAL
OSCILLATOR
CLOCK DETECT
MUX
EN
CLOCK
ISL26132, ISL26134
14 FN6954.1
September 9, 2011
Serial Clock Input (SCLK)
The serial clock input is provided with hysteresis to minimize
false triggering. Nevertheless, care should be taken to ensure
reliable clocking.
Filter Settling Time and ADC Latency
Whenever the analog signal into the ISL26132, ISL26134
converters is changed, the effects of the digital filter must be
taken into account. The filter takes four data ready periods for
the output code to fully reflect a new value at the analog input. If
the multiplexer control input is changed, the modulator and the
digital filter are reset, and the device uses four data ready
periods to fully settle to yield a digital code that accurately
represents the analog input. Therefore, from the time the control
inputs for the multiplexer are changed until the SDO/RDY goes
low, four data ready periods will elapse. The settling time delay
after a multiplexer channel change is listed in Table 8 for the
converter operating in continuous conversion mode.
0
-50
-100
-150
0 10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz)
GAIN (dB)
DDAATTAA RRAATTEE == 1100 SSpPsS
FIGURE 26. 10Sps: FREQUENCY RESPONSE OUT TO 100Hz
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
45 50 55 60 65
FREQUENCY (Hz)
GAIN (dB)
DATA RATE = 10Sps
FIGURE 27. 10Sps: 50/60Hz NOISE REJECTION, 45Hz TO 65Hz
TABLE 8. SETTLING TIME
PARAMETER
DESCRIPTION
(fCLK = 4.9152MHz) MIN MAX UNITS
tS A0, A1, SPEED, Gain1, Gain0 change
set-up time
40 50 μs
t1 Settling time SPEED = 1 54 55 ms
SPEED = 0 404 405 ms
FIGURE 28. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
SDO/RDY
tS
t1
A0, A1, SPEED, Gain1, Gain0
ISL26132, ISL26134
15 FN6954.1
September 9, 2011
Conversion Data Rate
The SPEED pin is used to select between the 10Sps and 80Sps
conversion rates. The 10Sps rate (SPEED = Low) is preferred in
applications requiring 50/60Hz noise rejection. Note that the
sample rate is directly related to the oscillator frequency, as
491,520 clocks are required to perform a conversion at the
10Sps rate, and 61,440 clocks at the 80Sps rate.
Output Data Format
The 24-bit converter output word is delivered in two’s
complement format. Input exceeding full scale results in a
clipped output which will not return to in-range values until after
the input signal has returned to the specified allowable voltage
range and the digital filter has settled as discussed previously.
Reading Conversion Data from the Serial
Data Output/Ready SDO/RDY Pin
When the ADC is powered, it will automatically begin doing
conversions. The SDO/RDY signal will go low to indicate the
completion of a conversion. After the SDO/RDY signal goes low,
the MSB data bit of the conversion word will be output from the
SDO/RDY pin after SCLK is transitioned from a low to a high.
Each subsequent new data bit is also output on the rising edge of
SCLK (see Figure 30). The receiving device should use the falling
edge of SCLK to latch the data bits. After the 24th SCLK, the
SDO/RDY output will remain in the state of the LSB data bit until
a new conversion is completed. At this time, the SDO/RDY will go
high if low and then go low to indicate that a new conversion
word is available. If not all data bits are read from the SDO/RDY
pin prior to the completion of a new conversion, they will be
overwritten. SCLK should be low during time t6, as shown in
Figure 30, when SDO/RDY is high.
If the user wants the SDO/RDY signal to go high after reading the
24 bits of the conversion data word, a 25th SCLK can be issued.
The 25th SCLK will force the SDO/RDY signal to go high and
remain high until it falls to signal that a new conversion word is
available. Figure 31 illustrates the behavior of the SDO/RDY
signal when a 25th SCLK is used.
FIGURE 29. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
SDO/RDY
TABLE 9. OUTPUT CODES CORRESPONDING TO INPUT
INPUT SIGNAL OUTPUT CODE (HEX)
≥ + 0.5VREF/GAIN 7FFFFF
(+0.5VREF/GAIN)/(223 - 1) 000001
0 000000
(-0.5VREF/GAIN)/(223 - 1) FFFFFF
≤ - 0.5VREF/GAIN 800000
FIGURE 30. OUTPUT DATA WAVEFORMS USING 24 SCLKS TO READ CONVERSION DATA
SDO/RDY
DATA READY
DATA
MSB LSB
NEW DATA READY
23 22 21 0
SCLK
t4
t2
1
t3
24
t5
t6
t3
t7
ISL26132, ISL26134
16 FN6954.1
September 9, 2011
Offset Calibration Control
The offset internal to the ADC can be removed by performing an
offset calibration operation. Offset calibration can be initiated
immediately after reading a conversion word with 24 SCLKs by
issuing two additional SCLKs. The offset calibration operation will
begin immediately after the 26th SCLK occurs. Figure 32
illustrates the timing details for the offset calibration operation.
During offset calibration, the analog inputs are shorted internally
and a regular conversion is performed. This conversion generates
a conversion word that represents the offset error. This value is
stored and used to digitally remove the offset error from future
conversion words. The SDO/RDY output will fall to indicate the
completion of the offset calibration operation.
TABLE 10. INTERFACE TIMING CHARACTERISTICS
PARAMETER DESCRIPTION MIN TYP MAX UNITS
t2 SDO/RDY Low to first SLK 0 ns
t3 SCLK pulsewidth, Low or High 100 ns
t4 SCLK High to Data Valid 50 ns
t5 Data Hold after SCLK High 0 ns
t6 Register Update Time 39 μs
t7 Conversion Period SPEED = 1 12.5 ms
SPEED = 0 100 ms
FIGURE 31. OUTPUT DATA WAVEFORMS FOR SDO/RDY POLLING
DATA READY NEW DATA READY
SDO/RDY
SCLK
23 22 21 0
1 24 25
DATA
25TH SCLK FORCES
SDO/RDY HIGH
FIGURE 32. OFFSET CALIBRATION WAVEFORMS
DATA READY AFTER CALIBRATION
CALIBRATION BEGINS
SDO/RDY
SCLK
23 22 21 0 23
1 24 25 26
t8
FIGURE 33. STANDBY MODE WAVEFORMS
DATA READY
START
CONVERSION
STANDBY MODE
SDO/RDY
SCLK
23 22 21 0
1 24
t10 t11
t9
23
TABLE 11. SDO/RDY DELAY AFTER CALIBRATION
PARAMETER MIN MAX UNITS
t8 SPEED = 1 108 109 ms
SPEED = 0 808 809 ms
ISL26132, ISL26134
17 FN6954.1
September 9, 2011
Standby Mode Operation
The ADC can be put into standby mode to save power. Standby
mode reduces the power to all circuits in the device except the
crystal oscillator amplifier. To enter the standby mode, take the
SCLK signal high and hold it high after SDO/RDY falls. The
converter will remain in standby mode as long as SCLK is held
high. To return to normal operation, take SCLK back low and wait
for the SDO/RDY to fall to indicate that a new conversion has
completed. Figure 33 and Table 12 illustrate the details of
standby mode.
Supply currents are equal in Standby and Power-down modes
unless a Crystal is used. If the Crystal is used, the Crystal
amplifier is turned ON, even in the standby mode.
Performing Offset Calibration After Standby
Mode
To perform an offset calibration automatically upon returning
from standby, deliver 2 or more additional SCLKs following a
data read cycle, and then set and hold SCLK high. The device will
remain in Standby as long as SCLK remains high. A calibration
cycle will begin once SCLK is brought low again to resume
normal operation. Additional time will be required to perform the
calibration after returning from Standby. Figure 34 and Table 13
illustrate the details of performing offset calibration after
standby mode.
TABLE 12. STANDBY MODE TIMING
PARAMETER DESCRIPTION MIN MAX UNITS
t9 SCLK High after
SDO/RDY Low
SPEED = 1 0 12.44 ms
SPEED = 0 0 99.94
t10 Standby Mode Delay SPEED = 1 12.5
SPEED = 0 100
t11 SDO/RDY falling edge
after SCLK Low
SPEED = 1 50 60
SPEED = 0 400 410
TABLE 13. OFFSET CALIBRATION TIMING AFTER STANDY
PARAMETER DESCRIPTION MIN MAX UNITS
t12 SDO/RDY Low after
SCLK Low
SPEED = 1 108 113 ms
SPEED = 0 808 813 ms
FIGURE 34. OFFSET CALIBRATION WAVEFORMS AFTER STANDBY
SDO/RDY
SCLK
23 22 21 0
1 24 25
STANDBY MODE DATA READY AFTER CALIBRATION
BEGIN 23
CALIBRATION
t10 t12
ISL26132, ISL26134
18 FN6954.1
September 9, 2011
Operation of PDWN
PDWN must transition from low to high after both power supplies
have settled to specified levels in order to initiate a correct
power-up reset (Figure 35). This can be implemented by an
external controller or a simple RC delay circuit, as shown in
Figure 36.
In order to reduce power consumption, the user can assert the
Power-down mode by bringing PDWN Low as shown in Figure 37.
All circuitry is shut down in this mode, including the Crystal
Oscillator. After PDWN is brought High to resume operation, the
reset delay varies depending on the clock source used. While an
external clock source will resume operation immediately, a
circuit utilizing a crystal will incur about a 20 millisecond delay
due to the inherent start-up time of this type of oscillator.
FIGURE 35. POWER-DOWN TIMING RELATIVE TO SUPPLIES
≥10μs
AVDD
DVDD
PDWN
FIGURE 36. PDWNDELAY CIRCUIT
DVDD
1kΩ
2.2nF
CONNECT TO
PDWN PIN
FIGURE 37. POWER-DOWN MODE WAVEFORMS
SDO/RDY
SCLK
t11
PDWN
POWER-DOWN
MODE
START
CONVERSION
DATA
CLK READY
SOURCE
WAKEUP
t13
tt1144
TABLE 14. POWER-DOWN RECOVERY TIMING
PARAMETER DESCRIPTION TYP UNITS
t13 Clock Recovery after PDWN
High
Internal Oscillator 7.95 μs
External Clock Source 0.16 μs
4.9152MHz Crystal
Oscillator
5.6 ms
t14 PDWN Pulse Duration 26 μs (min)
ISL26132, ISL26134
19 FN6954.1
September 9, 2011
Applications Information
Power-up Sequence – Initialization and
Configuration
The sequence to properly power-up and initialize the device are
as follows. For details on individual functions, refer to their
descriptions.
1. AVDD, DVDD ramp to specified levels
2. Apply External Clock
3. Pull PDWN High to initiate Reset
4. Device begins conversion
5. SDO/RDY goes low at end of first conversion
OPTIONAL ACTIONS
• Perform Offset Calibration
• Place device in Standby
• Return device from Standby
• Read on-chip Temperature (applicable to ISL26132 only)
Application Examples
WEIGH SCALE SYSTEM
Figure 38 illustrates the ISL26132 connected to a load cell. The
A/D converter is configured for a gain of 128x and a sample rate
of 10Sps. If a load cell with 2mV/V sensitivity is used, the full
scale output from the load cell will be 10mV. On a gain of 128x
and sample rate of 10Sps, the converter noise is 67nVP-P. The
converter will achieve 10mV/67nVP-P = 149,250 noise free
counts across its 10mV input signal. This equates to 14,925
counts per mV of input signal. If five output words are averaged
together this can be improved by √5 to yield √5*14925
counts = 33,370 counts per mV of input signal with an effective
update rate of 2 readings per second.
THERMOCOUPLE MEASUREMENT
Figure 39 illustrates the ISL26132 in a thermocouple
application. As shown, the 4.096V reference combined with the
PGA gain set to 128x sets the input span of the converter to
±16mV. This supports the K type thermocouple measurement for
temperatures from -270°C at -6.485mV to +380°C at about
16mV.
If a higher temperature is preferred, the PGA can be set to 64x to
provide a converter span of ±32mV. The will allow the converter
to support temperature measurement with the K type
thermocouple up to about +765°C.
In the circuit shown, the thermocouple is referenced to a voltage
dictated by the resistor divider from the +5V supply to ground.
These set the common mode voltage at about 2.5V. The 5M
resistors provide a means for detection of an open thermocouple.
If the thermocouple fails open or is not connected, the bias
through the 5M resistors will cause the input to the PGA to go to
full scale.
AVDD
VREF+
CAP
CAP
AIN+1
AIN-1
AIN+2
AIN-2
VREFAGND
DGND
TEMP
A0
SPEED
XTALOUT
PDWN
SCLK
SDO/RDY
GAIN0
GAIN1
DVDD
ISL26132
XTALIN/CLOCK
- +
0.1μF
VDD
MICRO
CONTROLLER
GND
16
9
10
11
12
14
13
15
17 2, 5, 6
7
8
21
3
4
22
23
24
19
20
GAIN = 128
5V 3V
0.1μF 18 1
FIGURE 38. WEIGH SCALE APPLICATION
ISL26132, ISL26134
20 FN6954.1
September 9, 2011
PCB Board Layout and System
Configuration
The ISL26132,ISL26134 ADC is a very low noise converter. To
achieve the full performance available from the device will
require attention to the printed circuit layout of the circuit board.
Care should be taken to have a full ground plane without
impairments (traces running through it) directly under the chip
on the back side of the circuit board. The analog input signals
should be laid down adjacent (AIN+ and AIN- for each channel) to
achieve good differential signal practice and routed away from
any traces carrying active digital signals. The connections from
the CAP pins to the off-chip filter capacitor should be short, and
without any digital signals nearby. The crystal, if used should be
connected with relatively short leads. No active digital signals
should be routed near or under the crystal case or near the
traces, which connect it to the ADC. The AGND and DGND pins of
the ADC should be connected to a common solid ground plane.
All digital signals to the chip should be powered from the same
supply, as that used for DVDD (do not allow digital signals to be
active high unless the DVDD supply to the chip is alive). Route all
active digital signals in a way to keep distance from any analog
pin on the device (AIN, VREF, CAP, AVDD). Power on the AVDD
supply should be active before the VREF voltage is present.
PCB layout patterns for the chips (ISL26132 and ISL26134) are
found on the respective package outline drawings on pages 22,
and 23.
AVDD
VREF+
AIN+1
AIN-1
AIN+2
AIN-2
VREFAGND
DGND
TEMP
A0
SPEED
XTALOUT
PDWN
SCLK
SDO/RDY
GAIN0
GAIN1
DVDD
XTALIN/CLOCK
MICRO
CONTROLLER
16
11
12
14
13
15
17 2, 5, 6
7
8
21
3
4
22
23
24
19
20
+5V +3V
0.1μF
18 1
FIGURE 39. THERMOCOUPLE MEASUREMENT APPLICATION
4.9152
MHz
ISL21009
4.096V
10nF
1μF
10k
10k
0.1μF
TYPE K
5M
5M
ISL26132, ISL26134
21
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6954.1
September 9, 2011
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL26132, ISL26134
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE REVISION CHANGE
09/08/11 FN6954.1 Power Supply Requirements on page 6 - AIDD - Analog Supply Current - Normal Mode, AVDD = 5, Gain = 1,2
changed TYP and MAX from “6, 7.3” to “7, 8.5”
Power Dissipation, Total Normal Mode, AVDD = 5, Gain = 1, 2 changed from “43.3” to “49.6” mW (Max)
08/22/11 FN6954.0 Initial Release.
ISL26132, ISL26134
22 FN6954.1
September 9, 2011
Package Outline Drawing
M24.173
24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
1.
NOTES:
7.
5
SEATING PLANE
C
H
2 3
1
24
B
12
1 3
13
A
PLANE
GAUGE
0.05 MIN
0.15 MAX
0°-8°
0.60± 0.15
0.90
1.00 REF
0.25
SEE DETAIL "X"
0.15
0.25
(0.65 TYP)
(5.65)
(0.35 TYP)
(1.45)
6.40
4.40 ±0.10
0.65
1.20 MAX
PIN #1
I.D. MARK
7.80 ±0.10
+0.05
-0.06
-0.06
+0.05
-0.10
+0.15
0.20 C B A
0.10 C
- 0.05
0.10 M C B A
ISL26132, ISL26134
23 FN6954.1
September 9, 2011
Package Outline Drawing
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
1.
NOTES:
7.
5
SEATING PLANE
C
H
2 3
1
28
B
14
1 3
15
A
PLANE
GAUGE
0.05 MIN
0.15 MAX
0°-8°
0.60 ±0.15
0.90
1.00 REF
0.25
SEE DETAIL "X"
0.25
(0.65 TYP)
(5.65)
(0.35 TYP)
(1.45)
6.40
4.40 ± 0.10
0.65
1.20 MAX
PIN #1
I.D. MARK
9.70± 0.10
-0.06
0.15 +0.05
-0.10
+0.15
-0.06
+0.05
0.20 C B A
0.10 C
- 0.05
0.10 M C B A
Both, the Deltabell® E and Plus feature engineer friendly features such as the unique levelling mechanism and
modular components that make simple sounder installations a reality.
Both external sounders incorporate the same features that are described overleaf. However, the Deltabell® Plus
has a fully back-light option, which enables around the clock visual deterrent to maximise your security.
The Deltabell® E and Plus are available in a variety of different colours:
Low power external sounder with strobe
Low power external sounder with strobe and back-light
Available Base Colours: Red,
Green, White, Amber, Blue and Black
Available Lid Colours: Red, White,
Yellow, Black*, Blue* and Chrome*
*Not recommended for Deltabell® Plus
2012 Pyronix Ltd. Pyronix, the Pyronix Blades device, Deltabell are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change. Other cover colour
options available. White cover recommended for use with backlit Deltabell PLUS for optimum visual clarity.
RMKT090001-7
© 2009 Pyronix Ltd. Pyronix and the Pyronix Blades device are trademarks of Pyronix Ltd.
As part of our continued development programme specifications of the V2 TEL and V2 GSM may change.
RMKT090057-1
© 2009 Pyronix Ltd. Pyronix, the Pyronix Blades device, TMD15 and TriCover are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change.
RMKT080064-4
© 2009 Pyronix Ltd. Pyronix, the Pyronix Blades device, TMD15 and TriCover are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change.
RMKT090057-1
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
2010 Pyronix Ltd. Pyronix, the Pyronix Blades device, Deltabell are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change. Other cover colour
options available. White cover recommended for use with backlit Deltabell PLUS for optimum visual clarity.
RMKT090150
www.pyronix.com
marketing@pyronix.com
01709 700100Current consumption feature Deltabell® Plus only
The Deltabell® incorporates a LDR (Light Dependant Resistor)
circuit which turns the Light off during daylight hours when it is
not needed, saving on the product current consumption.
When the day turns from dusk to dark the Lightbox illuminates
so that your external visual deterrent can be seen on the
darkest of nights.
Visual alarm warning feature Deltabell® Plus only
In addition to the strobe which is present on all of the Deltabell®
models, the Deltabell® PLUS has the added feature that the
illuminated cover will strobe when the alarm is activated, giving
you the added peace of mind that your alarm will be seen in
‘alarm mode’ from a much greater distance than standard
sounders that do not have back lighting facilities.
Security and peace of mind
The Deltabell® has front and rear tamper protection and in the
event of a potential sabotage attack, the 104dBA sounder
provides a distinctive audible warning.
The electronic elements on the printed circuit board are
protected by a fully sealed unit with a rubber gasket providing
added protection in harsh environments and giving your
customer peace of mind that the Deltabell® will always sound
in the event of an alarm activation.
104 dBA sounder
Piezo sounder with high decibel output.
Engineer hold-off facility
The Deltabell® engineer hold-off facility means that when
initially powered with the tamper switch open, the sounder will
not activate.
Remote engineer hold-off facility
There is also the capability for remote engineer hold-off which
is invaluable when you are servicing the system enabling easy
maintenance. It can be turned on at any time by applying 0V
to this dedicated terminal which will then disable the tamper.
Unique levelling mechanism
A spirit level is supplied so that you can easily mount the
Deltabell®. In addition, to make the installation as simple as
possible, revolving guide holes are used to save time lining up
screw and drill holes.
SCB/SAB Mode
Self Contained Bell or Self Activating Bell mode.
Hinged cover The Deltabell® has a hinged cover that locks into place so that
both your hands are free to work on the sounder.
Fully back-lit cover
The Deltabell® low power modular unit back-lights the cover
(Deltabell® Plus only)
Electrical specification
Operating Voltage
Supply: 9-16 V DC (13.5 nominal)
Protected: Reverse polarity protected
Current Consumption
Quiescent Current: < 60 mA
Alarm Current: < 300 mA
Strobe
Strobe Duration: 100 ms
Strobe Frequency: 1Hz
Dimensions
[W] 290 mm
[H] 285 mm
[D] 50 mm
Compliance
Europe.
Suitable for use in
EN50131-1 systems
Security grade 2 or 3,
Environmental class IV
[H]
[W] [D]
Packing information
Minimum quantity: 10
Minimum order for
screen print: 40
Warranty: 2 years
Designed: UK
Dummy bases also available
2012 Pyronix Ltd. Pyronix, the Pyronix Blades device, Deltabell are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change. Other cover colour
options available. White cover recommended for use with backlit Deltabell PLUS for optimum visual clarity.
RMKT090001-7
© 2009 Pyronix Ltd. Pyronix and the Pyronix Blades device are trademarks of Pyronix Ltd.
As part of our continued development programme specifications of the V2 TEL and V2 GSM may change.
RMKT090057-1
© 2009 Pyronix Ltd. Pyronix, the Pyronix Blades device, TMD15 and TriCover are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change.
RMKT080064-4
© 2009 Pyronix Ltd. Pyronix, the Pyronix Blades device, TMD15 and TriCover are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change.
RMKT090057-1
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
www.pyronix.com
marketing@pyronix.com
01709 700100
2010 Pyronix Ltd. Pyronix, the Pyronix Blades device, Deltabell are all trademarks of Pyronix Ltd.
UK Registered Design. As part of our continued development programme specifications may change. Other cover colour
options available. White cover recommended for use with backlit Deltabell PLUS for optimum visual clarity.
RMKT090150
www.pyronix.com
marketing@pyronix.com
01709 700100
Serial File Transfer Cables
The cables feature either the traditional 25 D type RS232 connector or the now more commonly fitted 9 D type
serial connector. As the serial port on most PCs is a plug or male the most common interface cable tends to be
a socket to socket (female to female).
Features:
• Multi-headed cable allows either 9 D or 25 D connection - providing complete serial port flexibility
• Both serial port configurations (Pt Nos 4070 & 4062) available from stock
• High quality moulded cables manufactured using foil screened cable
• Custom lengths can be made up upon request
• Now recognised as conforming to the most standard file transfer wiring configuration
4070
Stock No Description
PC AT to PC AT
4070 DB9F to DB9F Null Modem Cable 2Mtr
4070-3 DB9F to DB9F Null Modem Cable 3Mtr
4070-5 DB9F to DB9F Null Modem Cable 5Mtr
4070-10 DB9F to DB9F Null Modem Cable 10Mtr
4070-15 DB9F to DB9F Null Modem Cable 15Mtr
PC XT to PC XT
4062 DB25F to DB25F Null Modem Cable 2Mtr
4062-3 DB25F to DB25F Null Modem Cable 3Mtr
4062-5 DB25F to DB25F Null Modem Cable 5Mtr
4062-10 DB25F to DB25F Null Modem Cable 10Mtr
PC XT to PC AT
4063 DB9F to DB25F Null Modem Cable 2Mtr
4063-3 9DS TO 25DS NULL MODEM 3M
4063-5 9DS TO 25DS NULL MODEM 5M
4063-10 9DS TO 25DS NULL MODEM 10M
Multi-head Serial Cables
4090 DB9F+DB25F to DB9F+DB25F Null Modem Cable 2Mtr
4090-3 DB9F+DB25F to DB9F+DB25F Null Modem Cable 3Mtr
4090-5 DB9F+DB25F to DB9F+DB25F Null Modem Cable 5Mtr
Amplifier
Internet Radio
Terrestrial Tuner
Features
Feature Description
Audio
Sources
6 – Internet Radio, MP3, CD, Terrestrial Radio,
Auxiliary Input.
Portable
Yes, two part system. The Internet Radio is
completely portable receiving all data and audio
over a wireless link from the transmitter part
connected to the PC USB port.
LCD
Display
20 character 5 x 7 dot matrix display with icons,
EL blue backlight.
Power
Source
8 x C size 1.5 volt alkaline battery or AC mains –
220 - 240 volt Europe, 110 volt US.
Operation
Time
Approx 30 hours continuous play at mid volume
on one set of alkaline batteries.
Feature Description
Output Power (RMS) 2 x 2.2 watts
Total Power 4.4 watts
Music Power 2 x 4.4 watts
PMPO 65 watts
Feature Description
Radio presets 6 with station name display
Feature Description
Digital Tuner bands FM Stereo
Tuner presets 6 for each band
Antenna FM YesLoudspeaker
Connections
Wireless Link
Dimensions
Frequency Display Yes, 4 digit
Feature Description
No. of way speaker system 1 – way full range driver
Impedance 2 x 8 ohm
Rated Power (RMS) 2 x 6 watts
Size 67 mm x 106 mm, Elliptical
Magnetic Shielding Yes
Feature Description
Stereo
headphone Yes
Auxiliary Input Yes, 2 x phono socket
Auxiliary
Output Yes, 2 x phono socket
USB connection Yes, transmitter connects to PC USB port
with 1.5 metre cable
Feature Description
Stereo Audio
Channel
Europe 863 MHz 10 mW erp, USA 925 MHz 10
mW erp, user selectable band switching to
avoid interference.
Data
Channel
Europe + USA, 433 MHz , bi-directional, user
selectable band switching to avoid interference.
Feature Description
Radio Remote
Module
Front to Back 155mm (6.1"), Side to Side
283mm (11.1"), Height 150mm (5.9")
USB Base
Module
Front to Back 120mm (4.7"), Side to Side
135mm (5.3"), Height 41mm (1.6")
maxon motor control Document ID: rel3149
ESCON Servo Controllers Edition: September 2012 1
Feature Comparison Chart © 2012 maxon motor. Subject to change without prior notice.
ESCON Feature Comparison Chart
The ESCON servo controllers are small-sized, powerful 4-quadrant PWM servo controller for the highly efficient control of permanent magnet-activated DC motors.
The featured operating modes – speed control (closed loop), speed control (open loop), and current control – meet the highest requirements. The ESCON servo controllers are designed being commanded
by an analog set value and features extensive analog and digital I/O functionality and are being configured via USB interface using the graphical user interface «ESCON Studio» for Windows
PCs.
Legend: ()* = only in use with DC Tacho or Encoder / nnnnnn = order number / O = optional
Feature ESCON 36/2 DC
(403112)
ESCON 36/3 EC
(414533)
ESCON 50/5
(409510)
Product image
Motors
DC motors up to 72 W — 250 W
EC motors up to — 97 W 250 W
Sensors
Digital Incremental Encoder (2 channel with or without Line Driver) —
DC Tacho —
Without sensor (DC motors) —
Digital Hall Sensors (EC motors) —
Electrical Data
Nominal operating voltage Vcc 10…36 VDC 10…36 VDC 10…50 VDC
Max. output voltage 0.98 x Vcc 0.98 x Vcc 0.98 x Vcc
Max. output current 4 A (<60 s) 9 A (<4 s) 15 A (<20 s)
Continuous output current 2 A 2.7 A 5 A
Pulse Width Modulation frequency 53.6 kHz
maxon motor control Document ID: rel3149
ESCON Servo Controllers Edition: September 2012 2
Feature Comparison Chart © 2012 maxon motor. Subject to change without prior notice.
Sampling rate PI current controller 53.6 kHz
Sampling rate PI speed controller 5.36 kHz
Max. efficiency 95% 95% 95%
Max. speed (DC) limited by max. permissible speed (motor)
and max. output voltage (controller) — limited by max. permissible speed (motor)
and max. output voltage (controller)
Max. speed (EC; 1 pole pair) — 150'000 rpm 150'000 rpm
Built-in motor choke 300 μH; 2 A 3 x 47 μH; 2.7 A 3 x 30 μH; 5 A
Inputs / Outputs
Hall sensor signals — H1, H2, H3 H1, H2, H3
Encoder signals A,A\,B,B\ — A,A\,B,B\
Max. encoder input frequency differential (single-ended) 1 MHz (100 kHz) — 1 MHz (100 kHz)
Potentiometers 1 1 2
Digital inputs 2
Digital inputs/outputs 2
Analog inputs 2
Resolution 12-bit
Range –10…+10 V
Circuit differential
Analog outputs 2
Resolution 12-bit
Range –4…+4 V
Auxiliary voltage output +5 VDC (IL ≤10 mA)
Hall sensor supply voltage — +5 VDC (IL ≤30 mA) +5 VDC (IL ≤30 mA)
Encoder supply voltage +5 VDC (IL ≤70 mA) — +5 VDC (IL ≤70 mA)
Status Indicators Operation: green LED / Error: red LED
Connections
J1 Power Pin header (2 mm), 2 poles Pin header (2 mm), 2 poles Pluggable screw-type terminal block
(3.5 mm), 2 poles
J2 Motor
Motor / Hall sensors Pin header (2 mm), 3 poles Mini module pin header, 8 poles Pluggable screw-type terminal block
(3.5 mm), 4 poles
J2A Motor
Motor / Hall sensors Spring-loaded contacts, 2 poles Spring-loaded contacts, 8 poles —
Feature ESCON 36/2 DC
(403112)
ESCON 36/3 EC
(414533)
ESCON 50/5
(409510)
maxon motor control Document ID: rel3149
ESCON Servo Controllers Edition: September 2012 3
Feature Comparison Chart © 2012 maxon motor. Subject to change without prior notice.
J3 Hall sensors — — Pluggable screw-type terminal block
(3.5 mm), 5 poles
J4 Encoder Pin header (2.54 mm), 5 x 2 poles — Pin header (2.54 mm), 5 x 2 poles
J4A Encoder Pin header (1.27 mm), 5 x 2 poles — —
J5 Digital I/O Pin header (2 mm), 6 poles Pin header (2 mm), 6 poles Pluggable screw-type terminal block
(3.5 mm), 6 poles
J6 Analog I/O Pin header (2 mm), 7 poles Pin header (2 mm), 7 poles Pluggable screw-type terminal block
(3.5 mm), 7 poles
J7 USB USB Type micro B female
Mechanical Data
Weight (approximate) 30 g 36 g 204 g
Dimensions (L x W x H) 55 x 40 x 16.1 mm 55 x 40 x 19.8 mm 115 x 75.5 x 24 mm
Mounting holes for screws M2.5 for screws M2.5 for screws M4
Environmental Conditions
Temperature – Operation –30…+45°C
Temperature – Extended range +45…+81°C; Derating: –0.056 A/°C +45…+78°C; Derating: –0.082 A/°C +45…+85°C; Derating: –0.113 A/°C
Temperature – Storage –40…+85°C
Humidity (condensation not permitted) 20…80%
Functionality
Operating Mode
Current controller (torque control)
Speed controller (closed loop)
with encoder feedback —
with DC Tacho feedback —
with Hall sensor feedback —
Speed controller (open loop)
with static IxR Compensation
with adaptive IxR Compensation ()*
Feature ESCON 36/2 DC
(403112)
ESCON 36/3 EC
(414533)
ESCON 50/5
(409510)
maxon motor control Document ID: rel3149
ESCON Servo Controllers Edition: September 2012 4
Feature Comparison Chart © 2012 maxon motor. Subject to change without prior notice.
Set Value
Analog set value
PWM set value
Fixed set value
2 fixed set values
Digital I/O Functionality
Enable
Enable CW
Enable CCW
Enable CW + CCW
Enable + Direction
Stop
Ready
Speed Comparator
Commutation frequency —
Monitoring Outputs
Monitor Current
Monitor Speed
Analog Settings
Set value
Current limit
Offset adjust set value
Speed ramp (using potentiometer)
Current gain (using potentiometer)
Speed gain (using potentiometer)
IxR Factor (using potentiometer)
Feature ESCON 36/2 DC
(403112)
ESCON 36/3 EC
(414533)
ESCON 50/5
(409510)
maxon motor control Document ID: rel3149
ESCON Servo Controllers Edition: September 2012 5
Feature Comparison Chart © 2012 maxon motor. Subject to change without prior notice.
Protection
Overcurrent
Current limiter (adjustable)
Thermal overload
Undervoltage
Overvoltage
Voltage transients
Short-circuit of motor winding
Software
Installation Program ESCON Setup
Graphical User Interface ESCON Studio
Startup Wizard
Regulation Tuning
Diagnostic
Firmware Update
Controller Monitor
Parameters
Data Recording
Online Help
Language German, English, French, Italian, Spanish, Japanese, Chinese
Operating System Windows 7, Windows XP SP3
Communication interface USB 2.0 (full speed)
Feature ESCON 36/2 DC
(403112)
ESCON 36/3 EC
(414533)
ESCON 50/5
(409510)
maxon motor control Document ID: rel3149
ESCON Servo Controllers Edition: September 2012 6
Feature Comparison Chart © 2012 maxon motor. Subject to change without prior notice.
Accessories (not included in delivery)
404404 ESCON 36/2 DC Connector Set — —
425255 ESCON 36/3 EC Connector Set — —
403964 ESCON Analog I/O Cable —
403962 ESCON DC Motor Cable — —
403965 ESCON Digital I/O Cable —
275934 ESCON Encoder Cable O — O
403957 ESCON Power Cable —
403968 USB 2.0 Type A micro-B Cable
418719 Adapter BLACK (for flexprint cable (FPC), 11 poles) — —
418723 Adapter BLUE (for flexprint cable (FPC), 8 poles) — —
418721 Adapter GREEN (for flexprint cable (FPC), 8 poles) — —
409286 ESCON USB Stick
Feature ESCON 36/2 DC
(403112)
ESCON 36/3 EC
(414533)
ESCON 50/5
(409510)
maxon motor control
ESCON Servo Controllers Document ID: rel2547 1
Feature Comparison Chart Edition: March 2012
© 2012 maxon motor. Subject to change without prior notice.
ESCON Feature Comparison Chart
The ESCON servo controllers are small-sized, powerful 4-quadrant PWM servo controller for the highly efficient control of permanent
magnet-activated DC motors.
The featured operating modes – speed control (closed loop), speed control (open loop), and current control – meet the highest
requirements. The ESCON servo controllers are designed being commanded by an analog set value and features extensive analog
and digital I/O functionality and are being configured via USB interface using the graphical user interface «ESCON Studio» for Windows
PCs.
Legend: ()* = only in use with DC Tacho or Encoder / nnnnnn = order number / O = optional
Feature ESCON 36/2 DC
(403112)
ESCON 50/5
(409510)
Product image
Motors
DC motors up to 72 W 250 W
EC motors up to — 250 W
Sensors
Digital Incremental Encoder (2 channel with or
without Line Driver)
DC Tacho
Without sensor (DC motors)
Digital Hall Sensors (EC motors) —
Electrical Data
Nominal operating voltage Vcc 10…36 VDC 10…50 VDC
Max. output voltage 0.98 x Vcc 0.98 x Vcc
Max. output current 4 A (<60 s) 15 A (<20 s)
Continuous output current 2 A 5 A
Pulse Width Modulation frequency 53.6 kHz
Sampling rate PI current controller 53.6 kHz
Sampling rate PI speed controller 5.36 kHz
Max. efficiency 95% 95%
Max. speed (DC) limited by max. permissible speed (motor)
and max. output voltage (controller)
Max. speed (EC; 1 pole pair) — 150'000 rpm
Built-in motor choke 300 μH; 2 A 3 x 30 μH; 5 A
Inputs / Outputs
Hall sensor signals — H1, H2, H3
Encoder signals A,A\,B,B\
Max. encoder input frequency differential (singleended)
1 MHz (100 kHz)
Potentiometers 1 2
maxon motor control
2 Document ID: rel2547 ESCON Servo Controllers
Edition: March 2012 Feature Comparison Chart
© 2012 maxon motor. Subject to change without prior notice.
Digital inputs 2
Digital inputs/outputs 2
Analog inputs 2
Resolution 12-bit
Range –10…+10 V
Circuit differential
Analog outputs 2
Resolution 12-bit
Range –4…+4 V
Auxiliary voltage output +5 VDC (IL ≤10 mA)
Hall sensor supply voltage — +5 VDC (IL ≤30 mA)
Encoder supply voltage +5 VDC (IL ≤70 mA)
Status Indicators Operation: green LED / Error: red LED
Connections
J1 Power Pin header (2 mm), 2 poles Pluggable screw-type terminal block
(3.5 mm), 2 poles
J2 Motor Pin header (2 mm), 3 poles Pluggable screw-type terminal block
(3.5 mm), 4 poles
J2A Motor Spring-loaded contacts, 2 poles —
J3 Hall sensors — Pluggable screw-type terminal block
(3.5 mm), 5 poles
J4 Encoder Pin header (2.54 mm), 5 x 2 poles
J4A Encoder Pin header (1.27 mm), 5 x 2 poles —
J5 Digital I/O Pin header (2 mm), 6 poles Pluggable screw-type terminal block
(3.5 mm), 6 poles
J6 Analog I/O Pin header (2 mm), 7 poles Pluggable screw-type terminal block
(3.5 mm), 7 poles
J7 USB USB Type micro B female
Mechanical Data
Weight (approximate) 30 g 204 g
Dimensions (L x W x H) 55 x 40 x 16.1 mm 115 x 75.5 x 24 mm
Mounting holes for screws M2.5 for screws M4
Environmental Conditions
Temperature – Operation –30…+45°C
Temperature – Extended range +45…+81°C; Derating: –0.056 A/°C +45…+85°C; Derating: –0.113 A/°C
Temperature – Storage –40…+85°C
Humidity (condensation not permitted) 20…80%
Functionality
Operating Mode
Current controller (torque control)
Speed controller (closed loop)
with encoder feedback
with DC Tacho feedback
with Hall sensor feedback —
Feature ESCON 36/2 DC
(403112)
ESCON 50/5
(409510)
maxon motor control
ESCON Servo Controllers Document ID: rel2547 3
Feature Comparison Chart Edition: March 2012
© 2012 maxon motor. Subject to change without prior notice.
Speed controller (open loop)
with static IxR Compensation
with adaptive IxR Compensation ()*
Set Value
Analog set value
PWM set value
Fixed set value
2 fixed set values
Digital I/O Functionality
Enable
Enable CW
Enable CCW
Enable CW + CCW
Enable + Direction
Stop
Ready
Speed Comparator
Commutation frequency —
Monitoring Outputs
Monitor Current
Monitor Speed
Analog Settings
Set value
Current limit
Offset adjust set value
Speed ramp (using potentiometer)
Current gain (using potentiometer)
Speed gain (using potentiometer)
IxR Factor (using potentiometer)
Protection
Overcurrent
Current limiter (adjustable)
Thermal overload
Undervoltage
Overvoltage
Voltage transients
Short-circuit of motor winding
Feature ESCON 36/2 DC
(403112)
ESCON 50/5
(409510)
maxon motor control
4 Document ID: rel2547 ESCON Servo Controllers
Edition: March 2012 Feature Comparison Chart
© 2012 maxon motor. Subject to change without prior notice.
Software
Installation Program ESCON Setup
Graphical User Interface ESCON Studio
Startup Wizard
Regulation Tuning
Diagnostic
Firmware Update
Controller Monitor
Parameters
Data Recording
Online Help
Language German, English, French, Italian, Spanish
Operating System Windows 7, Windows XP SP3
Communication interface USB 2.0 (full speed)
Accessories (not included in delivery)
404404 ESCON 36/2 DC Connector Set —
403964 ESCON Analog I/O Cable —
403962 ESCON DC Motor Cable —
403965 ESCON Digital I/O Cable —
275934 ESCON Encoder Cable O O
403957 ESCON Power Cable —
403968 USB 2.0 Type A micro-B Cable
409286 ESCON USB Stick
Feature ESCON 36/2 DC
(403112)
ESCON 50/5
(409510)
Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/
EV (AEV)
ASCTB233E 201209-T
ORDERING INFORMATION
Capsule contact
Mechanism and
High-capacity Cut-off
Compact Relay
EV RELAYS (AEV)
10A
80A
200A 300A
120A
20A
New
RoHS compliant
FEATURES
• Compact and lightweight
Charged with hydrogen gas for high arc
cooling capacity, short gap cutoff has
been achieved at high DC voltages.
• Safety
High safety achieved with construction
that prevents explosions by keeping the
arc from leaking.
• High contact reliability
Since the contact portion is sealed in
hydrogen gas, there is no contact
oxidation. It is also dustproof and
waterproof.
TYPICAL APPLICATIONS
High DC voltage applications such as
• Electric vehicle
• Hybrid vehicle
• Fuel-cell vehicle
• Battery charge and discharge
systems
• Construction equipment
Contact arrangement
1: 1 Form A (Screw terminal, 10A TM, with terminal protection cover)
5: 1 Form A (20A TM type)
AEV 0
Contact rating
1: 10 A
2: 20 A
8: 80 A
4: 120 A
7: 200 A
9: 300 A
Coil terminal structure
Nil:
2:
Plug-in (Faston) (for 20 A type), Connector (for 80 A, 120 A and 300 A), Lead wire (for 200 A)
Plug-in (Faston) (for 10 A type with terminal protection cover)
Coil voltage
12: 12V DC
24: 24V DC
Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/
LQ (ALQ)
ASCTB92E 201206-T
ORDERING INFORMATION
TYPES
Standard packing: Carton 100 pcs., Case 500 pcs.
1 Form A/1 Form C 10A
Small power relays LQ RELAYS (ALQ)
Nominal coil voltage
1 Form A 1 Form C
Part No. Part No.
5V DC ALQ305 ALQ105
6V DC ALQ306 ALQ106
9V DC ALQ309 ALQ109
12V DC ALQ312 ALQ112
18V DC ALQ318 ALQ118
24V DC ALQ324 ALQ124
* Protective construction: Flux-resistant type
RoHS compliant
FEATURES
1. Miniature size and small: 10(W) ×
20(L) × 16(H) mm .394(W) × .787(L) ×
.630(H) inch
2. Compact with high capacity:
1 Form A and 1 Form C, 10 A
3. Ambient temperature:
–40°C to +85°C –40°F to 185°F
4. High surge voltage: 8,000 V
between contacts and coil
5. High breakdown voltage: 4,000 V
between contacts and coil
TYPICAL APPLICATIONS
1. Household appliances
Air conditioners, Refrigerators,
Fan heaters, Microwave ovens, Inverter
and Hot water units
New
Contact arrangement
1: 1 Form C
3: 1 Form A
ALQ
Coil insulation class
Nil:
F:
Class B insulation
Class F insulation
Nominal coil voltage (DC)
05: 5V, 06: 6V, 09: 9V, 12: 12V, 18: 18V, 24: 24VPanasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/
LQ (ALQ)
ASCTB92E 201206-T
RATING
1. Coil data
2. Specifications
* Specifications will vary with foreign standards certification ratings.
Notes: *1. This value can change due to the switching frequency, environmental conditions, and desired reliability level, therefore it is recommended to check this with the
actual load.
*2. Wave is standard shock voltage of ±1.2×50µs according to JEC-212-1981
*3. The upper limit of the ambient temperature is the maximum temperature that can satisfy the coil temperature rise value. Refer to Usage, transport and storage
conditions in NOTES.
*4. When using relays in a high ambient temperature, consider the pick-up voltage rise due to the high temperature (a rise of approx. 0.4% V for each 1°C 33.8°F with
20°C 68°F as a reference) and use a coil impressed voltage that is within the maximum applied voltage range.
Contact
arrangement
Nominal coil
voltage
Pick-up voltage
(at 20°C 68°F)
Drop-out voltage
(at 20°C 68°F)
Nominal operating
current
[±10%] (at 20°C 68°F)
Coil resistance
[±10%] (at 20°C 68°F)
Nominal operating
power
(at 20°C 68°F)
Max. applied voltage
1 Form A
5V DC
75%V or less of
nominal voltage
(Initial)
5%V or more of
nominal voltage
(Initial)
40.0mA 125 Ω
200mW
180% of nominal voltage
(at 20°C 68°F)
130% of nominal voltage
(at 85°C 185°F)*4
6V DC 33.3mA 180 Ω
9V DC 22.2mA 405 Ω
12V DC 16.7mA 720 Ω
18V DC 11.1mA 1,620 Ω
24V DC 8.3mA 2,880 Ω
1 Form C
5V DC
75%V or less of
nominal voltage
(Initial)
5%V or more of
nominal voltage
(Initial)
80.0mA 62.5Ω
400mW
150% of nominal voltage
(at 20°C 68°F)
110% of nominal voltage
(at 85°C 185°F)*4
6V DC 66.7mA 90 Ω
9V DC 44.4mA 202.5Ω
12V DC 33.3mA 360 Ω
18V DC 22.2mA 810 Ω
24V DC 16.7mA 1,440 Ω
Characteristics Item Specifications
Contact
Arrangement 1 Form A 1 Form C
Contact resistance (Initial) Max. 100mΩ (By voltage drop 6 V DC 1 A)
Contact material AgNi type
Rating
Nominal switching capacity (resistive load) 5 A 30 V DC, 10 A 125 V AC, 5 A 250 V AC
N.O. side:
10 A 125 V AC, 5 A 250 V AC, 5 A 30 V DC
N.C. side:
3 A 125 V AC, 2 A 250 V AC, 1 A 30 V DC
Max. switching power (resistive load) 150 W, 1,250 VA N.O. side: 150 W, 1,250 VA
N.C. side: 30 W, 500 VA
Max. switching voltage 250 V AC
Max. switching current N.O.: 10 A (125V AC), N.C.: 3 A (125V AC)
Nominal operating power 200 mW 400 mW
Min. switching capacity (reference value)*1 100 mA, 5 V DC
Electrical
characteristics
Insulation resistance (Initial) Min. 1,000 MΩ (at 500 V DC) Measurement at same location as “Breakdown voltage” section.
Breakdown voltage
(Initial)
Between open contacts 1,000 Vrms for 1 min.
(Detection current: 10 mA)
750 Vrms for 1 min.
(Detection current: 10 mA)
Between contact and coil 4,000 Vrms for 1 min. (Detection current: 10 mA)
Temperature rise (coil)*4 Max. 45°C 113°F (By resistive method, nominal coil voltage applied to the coil; contact carrying
current: 10A, at 85°C 185°F)
Surge breakdown voltage*2
(Between contact and coil) 8,000 V (Initial)
Operate time (at nominal voltage) (at 20°C 68°F) Max. 20 ms (excluding contact bounce time.) (Initial)
Release time (at nominal voltage) (at 20°C 68°F) Max. 20 ms (excluding contact bounce time, with diode) (Initial)
Mechanical
characteristics
Shock resistance Functional 1 Form A: 294 m/s2, 1 Form C: 196 m/s2
(Half-wave pulse of sine wave: 11 ms; detection time: 10µs.)
Destructive 980 m/s2 (Half-wave pulse of sine wave: 6 ms.)
Vibration resistance Functional 10 to 55 Hz at double amplitude of 1.6 mm (Detection time: 10µs.)
Destructive 10 to 55 Hz at double amplitude of 2.0 mm
Expected life Mechanical Min. 107 (at 180 times/min.)
Conditions Conditions for operation, transport and storage*3 Ambient temperature: –40°C to +85°C –40°F to +185°F
Humidity: 5 to 85% R.H. (Not freezing and condensing at low temperature)
Max. operating speed 20 times/min. (at nominal switching capacity)
Unit weight Approx. 7 g .25 ozPanasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/
LQ (ALQ)
ASCTB92E 201206-T
3. Expected electrical life
Condition: Resistive load, at 20°C 68°F, at 20 times/min., with diode
REFERENCE DATA
Type Switching capacity No. of operations
1 Form A (at 20 times/min.)
10 A 125 V AC
5 A 250 V AC
5 A 30 V DC
5×104
5×104
105
1 Form C (at 20 times/min.)
N.O.
10 A 125 V AC
5 A 250 V AC
5 A 30 V DC
5×104
5×104
105
N.C.
3 A 125 V AC
2 A 250 V AC
1 A 30 V DC
2×105
2×105
105
1.-(1) Max. switching capacity (1 Form A type) 1.-(2) Max. switching capacity (1 Form C type) 2. Life curve
Ambient temperature: room temperature
1,000
AC resistive load
10010 250
100
10
5
1
Contact voltage, V
Contact current, A
1,00025010010
100
10
5
3
2
1
Contact voltage, V
Contact current, A
AC resistive load N.O. side
AC resistive load N.C. side
125V AC resistive load
250V AC resistive load
1086420
100
10
1
Contact current, A
Life, ×104
3.-(1) Coil temperature rise (1 Form A type)
Contact carrying current: 5 A, 10 A
Measured portion: Inside the coil
3.-(2) Coil temperature rise (1 Form C type)
Contact carrying current: 5 A, 10 A
Measured portion: Inside the coil
4.-(1) Ambient temperature characteristics
(1 Form A type)
Contact carrying current: 5 A, 10 A
180160140120100
Coil applied voltage, %V
70
60
50
40
30
20
10
0
Te
mperature rise, °C
10 A at 70°C
5 A at 70°C
5 A at 85°C
10 A at 85°C
160150140130120110100
Coil applied voltage, %V
70
60
50
40
30
20
10
0
Temperature rise, °C
10 A at 70°C
10 A at 85°C
5 A at 85°C
5 A at 70°C
0 20 30 40 50 60 70 80 90
Ambient temperature, °C
400
300
200
100
Coil applied voltage, %V
1
2
3
5 4
6 7
4.-(2) Ambient temperature characteristics
(1 Form C type)
Contact carrying current: 5 A, 10 A 1Allowable ambient temperature against
% coil voltage (max. inside the coil temperature
set as 130°C 266°F) (Carrying current: 5 A)
2Allowable ambient temperature against
% coil voltage (max. inside the coil temperature
set as 130°C 266°F) (Carrying current: 10 A)
3Allowable ambient temperature against
% coil voltage (max. inside the coil temperature
set as 115°C 239°F) (Carrying current: 5 A)
4Allowable ambient temperature against
% coil voltage (max. inside the coil temperature
set as 115°C 239°F) (Carrying current: 10 A)
5Pick-up voltage with a hot-start condition
of 100%V on the coil (Carrying current: 10 A)
6Pick-up voltage with a hot-start condition
of 100%V on the coil (Carrying current: 5 A)
7Pick-up voltage
0 20 30 40 50 60 70 80 90
Ambient temperature, °C
400
300
200
100
Coil applied voltage, %V
1
2
3
4
5
6 7Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/
LQ (ALQ)
ASCTB92E 201206-T
DIMENSIONS (mm inch)
SAFETY STANDARDS
Note) CSA standard: Certified by C-UL
Item UL/C-UL (Recognized) VDE (Certified)
File No. Contact rating File No. Contact rating
1 Form A
E43028 10A 125V AC
5A 277V AC
5A 30V DC
4FLA/4LRA 277V AC
1/6 HP 125V AC 1/6 HP 277V AC
40032836 5A 250V AC (cosφ=1.0)
10A 250V AC (cosφ=1.0)
10A 250V AC (cosφ=0.4)
5A 30V DC (0ms)
1 Form C
E43028
10A 125V AC
5A 277V AC
5A 30V DC
4FLA/4LRA 277V AC
1/6 HP 125V AC 1/6 HP 277V AC
3A 125V AC
2A 277V AC
1A 30V DC
40032836
5A 250V AC (cosφ=1.0)
10A 250V AC (cosφ=1.0)
10A 250V AC (cosφ=0.4)
5A 30V DC (0ms)
3A 250V AC (cosφ=0.4)
The CAD data of the products with a CAD Data mark can be downloaded from: http://industrial.panasonic.com/ac/e/
External dimensions
1 Form A
1 Form C
20
.787
10.16
.400 7.62
.300 7.62
.300
10
.394
7.62
.300
15.6
.614
4.2
.165
0.4
.016
0.5 dia.
.020 dia. 0.3
.012 0.3
.012 0.8
.031
20
.787
10.16
.400
5.08
.200
10
.394
7.62
.300
15.6
.614
4.2
.165
0.4
.016
0.5 dia.
.020 dia. 0.3
.012 0.3
.012 0.3
.012
2.54
.100 7.62
.300
0.8
.031
0.8
.031
Schematic (Bottom view)
1 Form A 1 Form C
Coil
COM N.O.
Coil
COM N.O.
N.C.
PC board pattern (Bottom view)
1 Form A 1FormC
Tolerance: ±0.1 ±.004
4-1.3 dia.
7.62
7.62
10.16 4-.051 dia.
.300
.300
.400
5-1.3 dia.
7.62
7.62
10.16
2.54
5-.051 dia.
.300
.300
.400
.100
CAD Data
Dimension:
Less than 1mm .039inch:
Min. 1mm .039inch less than 5mm .197 inch:
Min. 5mm .197 inch:
General tolerance
±0.2 ±.008
±0.3 ±.012
±0.4 ±.016Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/
LQ (ALQ)
ASCTB92E 201206-T
NOTES
Usage, transport and storage
conditions
1) Temperature:
–40 to +85°C –40 to +185°F
2) Humidity: 5 to 85% RH
(Avoid freezing and condensation.)
The humidity range varies with the
temperature. Use within the range
indicated in the graph below.
3) Atmospheric pressure: 86 to 106 kPa
Temperature and humidity range for
usage, transport, and storage
4) Condensation
Condensation forms when there is a
sudden change in temperature under
high temperature and high humidity
conditions. Condensation will cause
deterioration of the relay insulation.
5) Freezing
Condensation or other moisture may
freeze on the relay when the
temperatures is lower than 0°C 32°F. This
causes problems such as sticking of
movable parts or operational time lags.
6) Low temperature, low humidity
environments
The plastic becomes brittle if the relay is
exposed to a low temperature, low
humidity environment for long periods of
time.
Solder and cleaning conditions
1) Please obey the following conditions
when soldering automatically.
(1) Preheating: Within 120°C 248°F
(solder surface terminal portion) and
within 120 seconds
(2) Soldering iron: 260°C±5°C
500°F±41°F (solder temperature) and
within 6 seconds (soldering time)
2) Do not use ultrasonic cleaning. This
will adversely affect relay characteristics.
When cleaning the relay, please use
alcoholic solvents.
Cautions for use
1) For precautions regarding use and
explanations of technical terminology,
please refer to our web site.
(panasonic-electric-works.net/ac)
2) To ensure good operation, please keep
the voltage on the coil ends to ±5% (at
20°C 68°F) of the rated coil operation
voltage. Also, please be aware that the
pick-up voltage and drop-out voltage may
change depending on the temperature
and conditions of use.
3) Keep the ripple rate of the nominal coil
voltage below 5%.
4) The cycle lifetime is defined under the
standard test condition specified in the
JIS C 5442 standard (temperature 15 to
35°C 59 to 95°F, humidity 25 to 75%).
Check this with the real device as it is
affected by coil driving circuit, load type,
activation frequency, activation phase,
ambient conditions and other factors.
Also, be especially careful of loads such
as those listed below.
(1) When used for AC load-operating and
the operating phase is synchronous.
Rocking and fusing can easily occur due
to contact shifting.
(2) Highly frequent load-operating
When highly frequent opening and
closing of the relay is performed with a
load that causes arcs at the contacts,
nitrogen and oxygen in the air is fused by
the arc energy and HNO3 is formed. This
can corrode metal materials.
Three countermeasures for these are
listed here.
• Incorporate an arc-extinguishing circuit.
• Lower the operating frequency
• Lower the ambient humidity
5) This value can change due to the
switching frequency, environmental
conditions, and desired reliability level,
therefore it is recommended to check this
with the actual load.
6) Heat, smoke, and even a fire may
occur if the relay is used in conditions
outside of the allowable ranges for the
coil ratings, contact ratings, operating
cycle lifetime, and other specifications.
Therefore, do not use the relay if these
ratings are exceeded.
7) If the relay has been dropped, the
appearance and characteristics should
always be checked before use.
8) Incorrect wiring may cause
unexpected events or the generation of
heat or flames.
85
5
Humidity, %RH
Tolerance range
(Avoid
condensation
when used at
temperatures
higher than
0°C 32°F)
(Avoid freezing
when used at
temperatures
lower than
0°C 32°F)
850–40
+185+32–40
Temperature, °C °F
74AC00, 74ACT00 — Quad 2-Input NAND Gate
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1
January 2008
74AC00, 74ACT00
Quad 2-Input NAND Gate
Features
■
I
CC
reduced by 50%
■
Outputs source/sink 24mA
■
ACT00 has TTL-compatible inputs
General Description
The AC00/ACT00 contains four, 2-input NAND gates.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Order
Number
Package
Number Package Description
74AC00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 2
74AC00, 74ACT00 — Quad 2-Input NAND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
I
IK
DC Input Diode Current
V
I
=
–0.5V –20mA
V
I
=
V
CC
+ 0.5 +20mA
V
I
DC Input Voltage –0.5V to V
CC
+ 0.5V
I
OK
DC Output Diode Current
V
O
=
–0.5V –20mA
V
O
=
V
CC
+ 0.5V +20mA
V
O
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
O
DC Output Source or Sink Current ±50mA
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin ±50mA
T
STG
Storage Temperature –65°C to +150°C
T
J
Junction Temperature 140°C
Symbol Parameter Rating
V
CC
Supply Voltage
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
V
I
Input Voltage 0V to V
CC
V
O
Output Voltage 0V to V
CC
T
A
Operating Temperature –40°C to +85°C
Δ
V
/
Δ
t Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
,
V
CC
@ 3.3V, 4.5V, 5.5V
125mV/ns
Δ
V
/
Δ
t Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
125mV/ns
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 3
74AC00, 74ACT00 — Quad 2-Input NAND Gate
DC Electrical Characteristics for AC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Symbol Parameter
V
CC
(V) Conditions
T
A
=
+25°C T
A
=
–40°C to +85°C
Typ. Guaranteed Limits Units
V
IH
Minimum HIGH Level
Input Voltage
3.0 V
OUT
=
0.1V
or V
CC
– 0.1V
1.5 2.1 2.1 V
4.5 2.25 3.15 3.15
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level
Input Voltage
3.0 V
OUT
=
0.1V
or V
CC
– 0.1V
1.5 0.9 0.9 V
4.5 2.25 1.35 1.35
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level
Output Voltage
3.0 I
OUT
=
–50μA 2.99 2.9 2.9 V
4.5 4.49 4.4 4.4
5.5 5.49 5.4 5.4
3.0 V
IN
=
V
IL
or V
IH
,
I
OH
=
–12mA
2.56 2.46
4.5 V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
3.86 3.76
5.5 V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
(1)
4.86 4.76
V
OL
Maximum LOW Level
Output Voltage
3.0 I
OUT
=
50μA 0.002 0.1 0.1 V
4.5 0.001 0.1 0.1
5.5 0.001 0.1 0.1
3.0 V
IN
=
V
IL
or V
IH
,
I
OL
=
12mA
0.36 0.44
4.5 V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
0.36 0.44
5.5 V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
(1)
0.36 0.44
I
IN
(3)
Maximum Input
Leakage Current
5.5 V
I
=
V
CC
, GND ±0.1 ±1.0 μA
I
OLD
Minimum Dynamic
Output Current
(2)
5.5 V
OLD
= 1.65V Max. 75 mA
IOHD 5.5 VOHD = 3.85V Min. –75 mA
ICC
(3) Maximum Quiescent
Supply Current
5.5 VIN = VCC or GND 2.0 20.0 μA
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 4
74AC00, 74ACT00 — Quad 2-Input NAND Gate
DC Electrical Characteristics for ACT
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
Symbol Parameter
VCC
(V) Conditions
TA = +25°C TA = –40°C to +85°C
Typ. Guaranteed Limits Units
VIH Minimum HIGH Level
Input Voltage
4.5 VOUT = 0.1V or
VCC – 0.1V
1.5 2.0 2.0 V
5.5 1.5 2.0 2.0
VIL Maximum LOW Level
Input Voltage
4.5 VOUT = 0.1V or
VCC – 0.1V
1.5 0.8 0.8 V
5.5 1.5 0.8 0.8
VOH Minimum HIGH Level
Output Voltage
4.5 IOUT = –50μA 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
4.5 VIN = VIL or VIH,
IOH = –24mA
3.86 3.76
5.5 VIN = VIL or VIH,
IOH = –24mA(4)
4.86 4.76
VOL Maximum LOW Level
Output Voltage
4.5 IOUT = 50μA 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
4.5 VIN = VIL or VIH,
IOL = 24mA
0.36 0.44
5.5 VIN = VIL or VIH,
IOL= 24mA(4)
0.36 0.44
IIN Maximum Input
Leakage Current
5.5 VI = VCC, GND ±0.1 ±1.0 μA
ICCT Maximum ICC/Input 5.5 VI = VCC – 2.1V 0.6 1.5 mA
IOLD Minimum Dynamic
Output Current(5)
5.5 VOLD = 1.65V Max. 75 mA
IOHD 5.5 VOHD = 3.85V Min. –75 mA
ICC Maximum Quiescent
Supply Current
5.5 VIN = VCC or GND 2.0 20.0 μA
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 5
74AC00, 74ACT00 — Quad 2-Input NAND Gate
AC Electrical Characteristics for AC
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Electrical Characteristics for ACT
Note:
7. Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol Parameter VCC
(V)(6)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Min. Typ. Max. Min. Max. Units
tPLH Propagation Delay 3.3 2.0 7.0 9.5 2.0 10.0 ns
5.0 1.5 6.0 8.0 1.5 8.5
tPHL Propagation Delay 3.3 1.5 5.5 8.0 1.0 8.5 ns
5.0 1.5 4.5 6.5 1.0 7.0
Symbol Parameter VCC
(V)(7)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Min. Typ. Max. Min. Max. Units
tPLH Propagation Delay 5.0 1.5 5.5 9.0 1.0 9.5 ns
tPHL Propagation Delay 5.0 1.5 4.0 7.0 1.0 8.0 ns
Symbol Parameter Conditions Typ. Units
CIN Input Capacitance VCC = OPEN 4.5 pF
CPD Power Dissipation Capacitance VCC = 5.0V 30.0 pF
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 6
74AC00, 74ACT00 — Quad 2-Input NAND Gate
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X 45°
1
0.10
C
C
C B A
7
M
14
B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25
0.25
0.10
0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 7
74AC00, 74ACT00 — Quad 2-Input NAND Gate
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 8
74AC00, 74ACT00 — Quad 2-Input NAND Gate
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°TOP & BOTTOM
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 9
74AC00, 74ACT00 — Quad 2-Input NAND Gate
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
14 8
1 7
NOTES: UNLESS OTHERWISE SPECIFIED
A)
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C)
DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30 5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35 2.54
3.81
3.17 8.82
(1.74)
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC00, 74ACT00 Rev. 1.4.1 10
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
FAST®
FastvCore™
FlashWriter® *
FPS™
FRFET®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
®
PDP-SPM™
Power220®
Power247®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
®
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
μSerDes™
UHC®
Ultra FRFET™
UniFET™
VCX™
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TOMAKE CHANGESWITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THEWARRANTY THEREIN,WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMSWITHOUT THE EXPRESSWRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Form
First Production
ative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
74AC00, 74ACT00 — Quad 2-Input NAND Gate
S1A - S1M — General Purpose Rectifiers
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
S1A - S1M Rev. 1.1.2 1
October 2013
S1A - S1M
General Purpose Rectifiers
Features
• 1 AIF(AV) Current Rating
• Glass Passivated
• Low Leakage:
- 1 μA Maximum at 25°C
- 50 μA Maximum at 125°C
• Fast Response: 1.8 μs (Typical)
• 30 A Surge Rating
• 50 to 1000 V Reverse Voltage Ratings
• 6.6 pF Typical Capacitance
• RoHS Compliant
Ordering Information
Part Number Marking Package Packing Method
S1A S1A DO-214AC Tape and Reel
S1B S1B DO-214AC Tape and Reel
S1D S1D DO-214AC Tape and Reel
S1G S1G DO-214AC Tape and Reel
S1J S1J DO-214AC Tape and Reel
S1K S1K DO-214AC Tape and Reel
S1M S1M DO-214AC Tape and Reel
SMA/DO-214AC
COLOR BAND DENOTES CATHODE
Description
In the world of commodity rectifiers, Fairchild Semiconductor’s
S1 family of 1 A, P-I-N, SMA rectifiers stand out
for their optimized low leakage, low capacitance, and
fast response time. This was achieved while maintaining
the industry standard VF max of 1.1 V at 1 A and a 30 A
surge rating. In today’s world, where system power efficiency
is a critical differentiating feature, these advantages
can be leveraged to support those higher
efficiency goals.
S1A - S1M — General Purpose Rectifiers
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
S1A - S1M Rev. 1.1.2 2
Absolute Maximum Ratings(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.
Note:
1. These ratings are limiting values above which the serviceability of any semiconductor device maybe impaired.
Thermal Characteristics
Notes:
2. Device mounted on FR-4 PCB, land pattern size: 25 mm² (5 x 5 mm).
3. Device mounted on FR-4 PCB, land pattern size: 4.6375 mm² (2.65 x 1.75 mm).
Electrical Characteristics
Values are at TA = 25°C unless otherwise noted.
Symbol Parameter
Value
Units
1A 1B 1D 1G 1J 1K 1M
VRRM Maximum Repetitive Reverse Voltage 50 100 200 400 600 800 1000 V
IF(AV)
Average Rectified Forward Current at
TA = 100°C 1.0 A
IFSM
Non-Repetitive Peak Forward Surge Current
8.3 ms Single Half-Sine-Wave 30 A
TSTG Storage Temperature Range -55 to +150 °C
TJ Operating Junction Temperature -55 to +150 °C
Symbol Parameter Max. Units
PD Power Dissipation 1.4 W
RθJA Thermal Resistance, Junction to Ambient(2) 85 °C/W
RθJA Thermal Resistance, Junction to Ambient(3) 170 °C/W
Ψjl Junction-Lead thermal characteristics(3) 25 °C/W
Symbol Parameter Test Condition Typ. Max. Units
VF Forward Voltage IF = 1.0 A 1.1 V
trr Reverse Recovery Time
IF = 0.5 A,
IR = 1.0 A,
Irr = 0.25 A
1.8 μs
IR Reverse Current at Rated VR
TA = 25°C 1.0 μA
TA =125°C 50 μA
CT Junction Capacitance VR = 4.0 V,
f = 1.0MHz 6.6 pF
S1A - S1M — General Purpose Rectifiers
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
S1A - S1M Rev. 1.1.2 3
Typical Performance Characteristics
Figure 1. Forward Current Derating Curve Figure 2. Forward Voltage Characteristics
Figure 3. Non-Repetitive Surge Current Figure 4. Reverse Current vs. Reverse Voltage
Figure 5. Total Capacitance Figure 6. Thermal Impedance Characteristics
0 25 50 75 100 125 150 175
0
1
2
Average Rectified Forward Current, IF [A]
Lead Temperature, [OC]
Percent of Rated Peak Reverse Voltage (%)
S1A - S1M — General Purpose Rectifiers
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
S1A - S1M Rev. 1.1.2 4
Physical Dimension
Figure 7. 2-LEAD, SMA, JEDEC DO-214, VARIATION AC
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/DO/DO214AC.pdf.
1.75
2.65
4.30
2.70 MAX
2.20
1.90
0.30
0.05
2.05
1.95
B 0.203
0.050
A
0.13 M C B A
C
2.95
2.50 B 1.65
1.20
B 5.60
4.80
B 4.75
4.00
B 0.13 M C B A
A
0.41
0.15
1.52
0.75
R0.15 4X
8°
0°
0.45
0 -8°
DETAIL A
SCALE 20 : 1
LAND PATTERN RECOMMENDATION
GAUGE
PLANE
NOTES:
A. EXCEPT WHERE NOTED CONFORMS TO
JEDEC DO214 VARIATION AC.
B DOES NOT COMPLY JEDEC STD. VALUE.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS.
E. DIMENSION AND TOLERANCE AS PER ASME
Y14.5-1994.
F. LAND PATTERN STD. DIOM5025X231M.
G. DRAWING FILE NAME: DO214ACREV1
DO-214AC
© Fairchild Semiconductor Corporation www.fairchildsemi.com
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
AccuPower
AX-CAP®*
BitSiC
Build it Now
CorePLUS
CorePOWER
CROSSVOLT
CTL
Current Transfer Logic
DEUXPEED®
Dual Cool™
EcoSPARK®
EfficientMax
ESBC
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series
FACT®
FAST®
FastvCore
FETBench
FPS
F-PFS
FRFET®
Global Power ResourceSM
GreenBridge
Green FPS
Green FPS e-Series
Gmax
GTO
IntelliMAX
ISOPLANAR
Making Small Speakers Sound Louder
and Better™
MegaBuck
MICROCOUPLER
MicroFET
MicroPak
MicroPak2
MillerDrive
MotionMax
mWSaver®
OptoHiT
OPTOLOGIC®
OPTOPLANAR®
®
PowerTrench®
PowerXS™
Programmable Active Droop
QFET®
QS
Quiet Series
RapidConfigure
Saving our world, 1mW/W/kW at a time™
SignalWise
SmartMax
SMART START
Solutions for Your Success
SPM®
STEALTH
SuperFET®
SuperSOT-3
SuperSOT-6
SuperSOT-8
SupreMOS®
SyncFET
Sync-Lock™
®*
TinyBoost®
TinyBuck®
TinyCalc
TinyLogic®
TINYOPTO
TinyPower
TinyPWM
TinyWire
TranSiC
TriFault Detect
TRUECURRENT®*
SerDes
UHC®
Ultra FRFET
UniFET
VCX
VisualMax
VoltagePlus
XS™
* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN,
WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain
life, and (c) whose failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its
safety or effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com,
under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors
are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical
and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise.
Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global
problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Rev. I66
®
http://www.farnell.com/datasheets/1766308.pdf
2N7002DW — N-Channel Enhancement Mode Field Effect Transistor
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
2N7002DW Rev. A 1
October 2007
2N7002DW
N-Channel Enhancement Mode Field Effect Transistor
Features
•Dual N-Channel MOSFET
•Low On-Resistance
•Low Gate Threshold Voltage
•Low Input Capacitance
•Fast Switching Speed
•Low Input/Output Leakage
•Ultra-Small Surface Mount Package
•Lead Free/RoHS Compliant
Absolute Maximum Ratings * Ta = 25°C unless otherwise noted
* These ratings are limiting values above which the serviceability of any semiconductor device may by impaired.
Thermal Characteristics
* Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch, Minimun land pad size,
Symbol
Parameter
Value
Units
VDSS
Drain-Source Voltage
60
V
VDGR
Drain-Gate Voltage RGS ≤ 1.0MΩ
60
V
VGSS
Gate-Source Voltage Continuous
Pulsed
±20
±40
V
ID
Drain Current Continuous
Continuous @ 100°C
Pulsed
115
73
800
mA
TJ , TSTG
Junction and Storage Temperature Range
-55 to +150
°C
Symbol
Parameter
Value
Units
PD
Total Device Dissipation
Derating above TA = 25°C
200
1.6
mW
mW/°C
RθJA
Thermal Resistance, Junction to Ambient *
625
°C/W
1SC70-6 (SOT363)Marking : 2N1
2N7002DW — N-Channel Enhancement Mode Field Effect Transistor
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
2N7002DW Rev. A 2
Electrical Characteristics TC = 25°C unless otherwise noted
Off Characteristics (Note1)
On Characteristics (Note1)
Dynamic Characteristics
Switching Characteristics
Note1 : Short duration test pulse used to minimize self-heating effect.
Symbol
Parameter
Test Condition
MIN
TYP
MAX
Units
BVDSS
Drain-Source Breakdown Voltage
VGS= 0V, ID=10uA
60
78
-
V
IDSS
Zero Gate Voltage Drain Current
VDS= 60V, VGS= 0V
VDS= 60V, VGS= 0V, @TC = 125°C
-
0.001
7
1.0
500
uA
IGSS
Gate-Body Leakage
VGS= ±20V, VDS= 0V
-
0.2
±10
nA
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250uA
1.0
1.76
2.0
V
RDS(ON)
Satic Drain-Source On-Resistance
VGS = 5V, ID = 0.05A,
VGS = 10V, ID = 0.5A, @Tj = 125°C
-
-
1.6
2.53
7.5
13.5
Ω
ID(ON)
On-State Drain Current
VGS = 10V, VDS= 7.5V
0.5
1.43
-
A
gFS
Forward Transconductance
VDS = 10V, ID = 0.2A
80
356.5
-
mS
Ciss
Input Capacitance
VDS = 25V, VGS= 0V, f = 1.0MHz
-
37.8
50
pF
Coss
Output Capacitance
-
12.4
25
pF
Crss
Reverse Transfer Capacitance
-
6.5
7.0
pF
tD(ON)
Turn-On Delay Time
VDD = 30V, ID = 0.2A, VGEN= 10V
RL = 150Ω, RGEN = 25Ω
-
5.85
20
ns
tD(OFF)
Turn-Off Delay Time
-
12.5
20
2N7002DW — N-Channel Enhancement Mode Field Effect Transistor
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
2N7002DW Rev. A 3
Typical Performance Characteristics
Figure 1. On-Region Characteristics
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current
Figure 3. On-Resistance Variation with
Temperature
Figure 4. On-Resistance Variation with
Gate-Source Voltage
Figure 5. Transfer Characteristics
Figure 6. Gate Threshold Variation with
Temperature
0123456789100.00.20.40.60.81.01.21.41.62V3V4V5VVGS = 10VID. DRAIN-SOURCE CURRENT(A)VDS. DRAIN-SOURCE VOLTAGE (V)
0.00.20.40.60.81.01.01.52.02.53.0(Ω)9V8V5V6V10V7V4V4.5VVGS = 3VRDS(on), DRANI-SOURCE ON-RESISTANCEID. DRAIN-SOURCE CURRENT(A)
-500501001500.51.01.52.02.53.0(Ω)VGS = 10VID = 500 mARDS(on) DRANI-SOURCE ON-RESISTANCETJ. JUNCTION TEMPERATURE(oC)
2468101.01.52.02.53.0ID = 500 mA(Ω)ID = 50 mARDS(on), DRANI-SOURCE ON-RESISTANCEVGS. GATE-SOURCE VOLTAGE (
V)
234560.00.20.40.60.81.0VDS = 10V75oC125oC150oC25oCTJ = -25oCID. DRAIN-SOURCE CURRENT(A)VGS. GATE-SOURCE VOLTAGE (V)
-500501001501.01.52.02.5ID = 0.25 mAID = 1 mAVGS = VDSVth, Gate-Source Threshold Voltage (
V)TJ. JUNCTION TEMPERATURE(oC)
2N7002DW — N-Channel Enhancement Mode Field Effect Transistor
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
2N7002DW Rev. A 4
Typical Performance Characteristics
Figure 7. Reverse Drain Current Variation with
Diode Forward Voltage and Temperature
Figure 8. Power Derating
1101000.00.20.40.60.81.0-55oCVGS = 0 V150oC25oCVSD, Body Diode Forward Voltage [V]IS Reverse Drain Current, [mA]
025507510012515017504080120160200240280 PC[mW], POWER DISSIPATIONTa[oC], AMBIENT TEMPERATURE
2N7002DW — N-Channel Enhancement Mode Field Effect Transistor
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
2N7002DW Rev. A 5
Package DimensionsSC70-6 ( SOT-363 )
2N7002DW N-Channel Enhancement Mode Field Effect Transistor
TRADEMARKS
The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and
is not intended to be an exhaustive list of all such trademarks.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF
THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE
UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF
FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE
PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
ACEx®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
FAST®
FastvCore™
FPS™
FRFET®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
®
PDP-SPM™
Power220®
Power247®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
μSerDes™
UHC®
UniFET™
VCX™
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
Preliminary First Production
This datasheet contains preliminary data; supplementary data will be published
at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.
Obsolete Not In Production
This datasheet contains specifications on a product that has been discontinued
by Fairchild semiconductor. The datasheet is printed for reference information
only.
Rev. I30
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
2N7002DW Rev. A 6
QRE1113, QRE1113GR — Minature Reflective Object Sensor
©2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
QRE1113, QRE1113GR Rev. 1.7.1
August 2011
QRE1113, QRE1113GR
Minature Reflective Object Sensor
Features
■
Phototransistor output
■
No contact surface sensing
■
Miniature package
■
Lead form style: Gull Wing
■
Two leadform options: Through hole (QRE1113)
SMT gullwing (QRE1113GR)
■
Two packaging options: Tube (QRE1113)
Tape and reel (QRE1113GR)
QRE1113GR Package Dimensions
2.90
2.50
3.60
0.94
3.20 1.80
0.60
1.00
C L
C L
0.40
0.94
1.70
1.50
4.80
4.40
1.10
0.90
1 2
4 3
30°
0.40
Notes:
1. Dimensions for all drawings are in millimeters.
2. Tolerance of ±0.15mm on all non-nominal dimensions
0.120
©2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
QRE1113, QRE1113GR Rev. 1.7.1 2
QRE1113, QRE1113GR — Minature Reflective Object Sensor
QRE1113 Package Dimensions
Schematic
2.90
2.50
10.4
0.94
8.4
1.80
0.60
1.00
C L
C L
0.40
0.94
1.70
0~20° 0~20°
1.50
1 2
4 3
4.20
3.80
0.40
3.60
3.20
Notes:
1. Dimensions for all drawings are in millimeters.
2. Tolerance of ±0.15mm on all non-nominal dimensions
1
Pin 1: Anode
Pin 2: Cathode
Pin 3: Collector
Pin 4: Emitter
2 34
©2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
QRE1113, QRE1113GR Rev. 1.7.1 3
QRE1113, QRE1113GR — Minature Reflective Object Sensor
Absolute Maximum Ratings
(T
A
= 25°C unless otherwise specified)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Electrical/Optical Characteristics
(T
A
= 25°C unless otherwise specified)
Notes:
1. Derate power dissipation linearly 1.00mW/°C above 25°C.
2. RMA flux is recommended.
3. Methanol or isopropyl alcohols are recommended as cleaning agents.
4. Soldering iron 1/16" (1.6mm) from housing.
5. Pulse conditions: tp = 100µs; T = 10ms.
6. Measured using an aluminum alloy mirror at d = 1mm.
7. No reflective surface at close proximity.
Symbol Parameter Rating Units
T
OPR
Operating Temperature -40 to +85 °C
T
STG
Storage Temperature -40 to +90 °C
T
SOL-I
Soldering Temperature (Iron)
(2,3,4)
240 for 5 sec °C
T
SOL-F
Soldering Temperature (Flow)
(2,3)
260 for 10 sec °C
EMITTER
I
F
Continuous Forward Current 50 mA
V
R
Reverse Voltage 5 V
I
FP
Peak Forward Current
(5)
1 A
P
D
Power Dissipation
(1)
75 mW
SENSOR
V
CEO
Collector-Emitter Voltage 30 V
V
ECO
Emitter-Collector Voltage 5 V
I
C
Collector Current 20 mA
P
D
Power Dissipation
(1)
50 mW
Symbol Parameter Test Conditions Min. Typ. Max. Units
INPUT DIODE
V
F
Forward Voltage I
F
= 20mA 1.2 1.6 V
I
R
Reverse Leakage Current V
R
= 5V 10 µA
λ
PE
Peak Emission Wavelength I
F
= 20mA 940 nm
OUTPUT TRANSISTOR
I
D
Collector-Emitter Dark Current I
F
= 0mA, V
CE
= 20V 100 nA
COUPLED
I
C(ON)
On-State Collector Current I
F
= 20mA, V
CE
= 5V
(6)
0.10 0.40 mA
I
CX
Cross-Talk Collector Current I
F
= 20mA, V
CE
= 5V
(7)
1 µA
V
CE (SAT)
Saturation Voltage 0.3 V
t
r
Rise Time V
CC
= 5V, I
C(ON)
= 100µA,
R
L
= 1k
Ω
20 µs
t
f
Fall Time 20
©2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
QRE1113, QRE1113GR Rev. 1.7.1 4
QRE1113, QRE1113GR — Minature Reflective Object Sensor
Typical Performance Curves
Fig. 1 Normalized Collector Current vs. Distance
between device and reflector
d-DISTANCE (mm)
012345
IC (ON)
- NORMALIZED
COLLECTOR CURRENT
0.0
0.2
0.4
0.6
0.8
1.0
IF = 10 mA
VCE = 5 V
TA = 25˚C
Mirror
Sensing Object:
White Paper (90% reflective)
d 0
Fig. 2 Collector Current vs. Forward Current
IF - FORWARD CURRENT (mA)
0 4 8 12 16 20
IC (ON) - COLLECTOR CURRENT
(mA)
0.0
0.2
0.4
0.6
0.8
1.0
Fig. 3 Normalized Collector Current vs.
Collector to Emitter Voltage
VCE - COLLECTOR EMITTER VOLTAGE (V)
0.1 1 10 C (ON) I - NORMALIZ
ED COLLECT
OR CURRENT
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
IF = 25mA
IF =20mA
IF =10mA
IF =15mA
IF =5mA
d = 1 mm, 90% reflection
TA = 25˚C
Fig. 4 Collector Emitter Dark Current (Normalized)
vs. Ambient Temperature
TA - Ambient Temperature (˚C)
ICEO
- NORMALIZ
ED DARK CURRENT
25 40 55 70 85
10-2
10-1
100
101
102
Normalized to:
VCE = 10 V
TA = 25˚C
VCE = 10 V
VCE = 5 V
©2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
QRE1113, QRE1113GR Rev. 1.7.1 5
QRE1113, QRE1113GR — Minature Reflective Object Sensor
Typical Performance Curves
(Continued)
Fig. 6 Forward Current vs. Forward Voltage
VF - FORWARD VOLTAGE (V)
VF - FORWARD VOLTAGE (V) IF - FORWARD CURRENT (mA)
1.0 1.1 1.2 1.3 1.4 1.5
0
10
20
30
40
50
TA = 25˚C
Fig. 7 Rise and Fall Time vs. Load Resistance
RL - LOAD RESIST
ANGULAR DISPLACEMENT
ANCE (KΩ)
0.1 1 10
0.6 0.6 0.4 0.2 0 0.2 0.4
R
RELATIVE RADIAN
T INTENSITY
ISE AND FALL TIME (us)
1
10
1.0
0.9
0.8
0.7
100 VCC = 10 V
tpw = 100 us
T=1ms
TA = 25˚C
IC = 0.3 mA
IC = 1 mA
tf
tf
tr
tr
Fig. 8 Forward Voltage vs. Ambient Temperature Fig. 8 Radiation Diagram
0.0
0.5
1.0
1.5
2.0
2.5
3.0
IF = 50 mA
IF = 10 mA
IF = 20 mA
TA - AMBIENT TEMPERATURE (˚C)
-40 -20 0 20 40 60 80
©2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
QRE1113, QRE1113GR Rev. 1.7.1 6
QRE1113, QRE1113GR — Minature Reflective Object Sensor
Recommended Solder Screen Pattern for GR option (for reference only)
Taping Dimensions for GR option
Dimensions in mm
1.0
1.1
2.8
LED (+)
0.8
2.0±0.05 4.0
0.25
5.5±0.05
12.0±0.3
8.0
3.73
4.75
1.98
ø1.5
1.75
Progressive Direction
General tolerance ±0.1
Dimensions in mm
©2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
QRE1113, QRE1113GR Rev. 1.7.1 7
QRE1113, QRE1113GR — Minature Reflective Object Sensor
Reel Dimensions
Reflow Profile
ø13.0 ± 0.5
2.2 ± 0.5
9.0 ± 0.5
12.0 ± 0.15
ø60.0 ± 0.5
ø178.0 ± 1.0
Time (seconds)
Te
mperature (°C)
1°C to 5°C/sec
1°C to 5°C/sec
260°C max. for 10 sec. max.
260°C
120 sec. max.
60 sec. max.
above 220°C
Pre-heating
180°C to 200°C
Note: Reflow soldering should not be done more than twice.
220°C
© Fairchild Semiconductor Corporation www.fairchildsemi.com
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
2Cool
AccuPower
AX-CAP®
*
BitSiC
Build it Now
CorePLUS
CorePOWER
CROSSVOLT
CTL
Current Transfer Logic
DEUXPEED®
Dual Cool™
EcoSPARK®
EfficientMax
ESBC
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series
FACT®
FAST®
FastvCore
FETBench
FPS
F-PFS
FRFET®
Global Power ResourceSM
GreenBridge
Green FPS
Green FPS e-Series
Gmax
GTO
IntelliMAX
ISOPLANAR
Making Small Speakers Sound Louder
and Better™
MegaBuck
MICROCOUPLER
MicroFET
MicroPak
MicroPak2
MillerDrive
MotionMax
mWSaver
OptoHiT
OPTOLOGIC®
OPTOPLANAR®
®
PowerTrench®
PowerXS™
Programmable Active Droop
QFET®
QS
Quiet Series
RapidConfigure
Saving our world, 1mW/W/kW at a time™
SignalWise
SmartMax
SMART START
Solutions for Your Success
SPM®
STEALTH
SuperFET®
SuperSOT-3
SuperSOT-6
SuperSOT-8
SupreMOS®
SyncFET
Sync-Lock™
®*
TinyBoost
TinyBuck
TinyCalc
TinyLogic®
TINYOPTO
TinyPower
TinyPWM
TinyWire
TranSiC
TriFault Detect
TRUECURRENT®
*
SerDes
UHC®
Ultra FRFET
UniFET
VCX
VisualMax
VoltagePlus
XS™
* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN,
WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain
life, and (c) whose failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its
safety or effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com,
under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors
are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical
and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise.
Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global
problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Rev. I64
®
©2007 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
ES1F - ES1J Rev. A
ES1F - ES1J Fast Rectifiers
July 2007
ES1F - ES1J
Fast Rectifiers
Features
•For surface mount applications.
•Glass passivated junction.
•Low profile package.
•Easy pick and place.
•Built-in strain relief.
•Superfast recovery times for high efficiency.
Absolute Maximum Ratings * Ta = 25°C unless otherwise noted
* These ratings are limiting values above which the serviceability of any semiconductor device may by impaired.
Thermal Characteristics
* P. C. B mounted on 0.2’’ x 0.2’’( 5 x 5 mm) copper Pad Area.
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Value
Units
ES1F
ES1G
ES1H
ES1J
VRRM
Maximum Repetitive Reverse Voltage
300
400
500
600
V
IF(AV)
Average Rectified Forward Current
1.0
A
IFSM
Non-repetitive Peak Forward Surge Current
8.3 ms Single Half-Sine-Wave (JEDEC method)
30
A
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature Range
-55 to 150
°C
PD
Power Dissipation
1.47
W
Symbol
Parameter
Value
Units
RθJA
Thermal Resistance, Junction to Ambient *
85
°C/W
RθJL
Thermal Resistance, Junction to Lead *
35
°C/W
Symbol
Parameter
Value
Units
VF
Maximum Forward Voltage @ IF = 1.0 A
1.3
1.7
V
Trr
Maximum Reverse Recovery Time
IF = 0.5 A, IR = 1.0 A, IRR = 0.25 A
35
ns
IR
Maximum Reverse Current @ rated VR TA = 25°C
TA = 100°C
5.0
100
uA
Cj
Typical Junction Capacitance
VR = 4.0 V, f = 1.0 MHz
10.0
8.0
pF
Color Band Denotes CathodeSMA(DO-214AC)
2 www.fairchildsemi.com
ES1F - ES1J Rev. A
ES1F - ES1J Fast Rectifiers
Typical Performance Characteristics
FIG.2- MAXIMUM NON-REPETITIVE PEAK FORWARD
SURGE CURRENT
PEAK FORWARD SURGE CURRENT. (A)
1 10 100
30
20
10
5.0
25
15
NUMBER OF CYCLES AT 60Hz
8.3ms Single Half Sine Wave
(JEDEC Method) at TL=120 C
o
FIG.3- TYPICAL INSTANTANEOUS
FORWARD CHARACTERISTICS
INSTANTANEOUS FORWARD CURRENT. (A)
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0.01
1
10
50
0.1
FORWARD VOLTAGE. (V)
ES1A - D
ES1F - 1G
Tj=25 C
PULSE WIDTH-300 S
1% DUTY CYCLE
0
FIG.1- MAXIMUM FORWARD CURRENT DERATING
CURVE
AVERAGE FORWARD CURRENT. (A)
80 90 100 110 120 130 140 150
0
0.2
0.6
0.8
1.2
1.0
0.4
LEAD TEMPERATURE. ( C) o
RESISTIVE OR
INDUCTIVE LOAD
0.2X0.2"(5.0X5.0mm)
COPPER PAD AREAS
FIG.4- TYPICAL REVERSE CHARACTERISTICS
0 20 40 60 80 100 120 140
10
100
1000
1
0.1
0.01
PERCENT OF RATED PEAK REVERSE VOLTAGE. (%)
Tj=125 C 0
Tj=85 C 0
Tj=25 C 0
0 1
0
10 100
14
10
6.0
4.0
2.0
12
8.0
FIG.5- TYPICAL JUNCTION CAPACITANCE
JUNCTION CAPACITANCE.(pF)
REVERSE VOLTAGE. (V)
ES1 F - G
ES1 H -J
Tj=25 C
f=1.0MHz
Vsig=50mVp-p
0
INSTANTANEOUS REVERSE CURRENT. ( A)
ES1H - 1J
0.01
0.1
1
10
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Tj=25 oC
PULSE WIDTH 300uS
1% DUTY CYCLE
ES1F-1G
ES1H-1J
3 www.fairchildsemi.com
ES1F - ES1J Rev. A
ES1F - ES1J Fast Rectifiers
Package Dimensions
Dimensions in Millimeters SMA / DO - 214AC
TRADEMARKS
The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and
is not intended to be an exhaustive list of all such trademarks.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF
THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE
UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF
FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE
PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
ACEx®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
FAST®
FastvCore™
FPS™
FRFET®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
®
PDP-SPM™
Power220®
Power247®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
μSerDes™
UHC®
UniFET™
VCX™
Datasheet IdentificationProduct StatusDefinition
Advance InformationFormative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
PreliminaryFirst Production
This datasheet contains preliminary data; supplementary data will be pub-
lished at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
No Identification NeededFull Production This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design. ObsoleteNot In Production
This datasheet contains specifications on a product that has been discontin-
ued by Fairchild semiconductor. The datasheet is printed for reference infor-
mation only.
Rev. I30
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 — Small Signal Diode
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 Rev. 1.1.1 1
April 2013
1N/FDLL 914A/B / 916/A/B / 4148 / 4448
Small Signal Diode
Absolute Maximum Ratings(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.
Note:
1. These ratings are limiting values above which the serviceability of the diode may be impaired.
Thermal Characteristics
Symbol Parameter Value Units
VRRM Maximum Repetitive Reverse Voltage 100 V
IO Average Rectified Forward Current 200 mA
IF DC Forward Current 300 mA
If Recurrent Peak Forward Current 400 mA
IFSM Non-repetitive Peak Forward Surge Current
Pulse Width = 1.0 s 1.0 A
Pulse Width = 1.0 μs 4.0 A
TSTG Storage Temperature Range -65 to +200 °C
TJ Operating Junction Temperature 175 °C
Symbol Parameter
Max.
Units
1N/FDLL 914/A/B / 4148 / 4448
PD Power Dissipation 500 mW
RθJA Thermal Resistance, Junction to Ambient 300 °C/W
LL-34
THE PLACEMENT OF THE EXPANSION GAP
HAS NO RELATIONSHIP TO THE LOCATION
OF THE CATHODE TERMINAL
LL-34 COLOR BAND MARKING
DEVICE 1ST BAND
DO-35
FDLL914 BLACK
FDLL914A BLACK
FDLL914B BLACK
Cathode is denoted with a black band
FDLL4148 BLACK
FDLL4448 BLACK
-1st band denotes cathode terminal
and has wider width
SOD80
Cathode Band
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 — Small Signal Diode
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 Rev. 1.1.1 2
Electrical Characteristics(2)
Values are at TA = 25°C unless otherwise noted.
Note:
2. Non-recurrent square wave PW= 8.3 ms.
Symbol Parameter Test Conditions Min. Max. Units
VR Breakdown Voltage
IR= 100 μA 100 V
IR= 5.0 μA 75 V
VF Forward Voltage
1N914B / 4448 IF= 5.0 mA 0.62 0.72 V
1N916B IF= 5.0 mA 0.63 0.73 V
1N914 / 916 / 4148 IF= 10 mA 1.0 V
1N914A / 916A IF= 20 mA 1.0 V
1N916B IF= 20 mA 1.0 V
1N914B / 4448 IF= 100 mA 1.0 V
IR Reverse Leakage
VR= 20 V 0.025 μA
VR= 20 V, TA= 150°C 50 μA
VR= 75 V 5.0 μA
CT Total Capacitance
1N916A/B/4448 VR = 0, f = 1.0 MHz 2.0 pF
1N914A/B/4148 VR = 0, f = 1.0 MHz 4.0 pF
trr Reverse Recovery Time IF = 10 mA, VR = 6.0 V (600 mA)
Irr = 1.0 mA, RL = 100 Ω 4.0 ns
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 — Small Signal Diode
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 Rev. 1.1.1 3
Typical Performance Characteristics
Figure 1. Reverse Voltage vs. Reverse Current
BV - 1.0 to 100 μA
Figure 2. Reverse Current vs. Reverse Voltage
IR - 10 to 100 V
Figure 3. Forward Voltage vs. Forward Current
VF - 1 to 100 μA
Figure 4. Forward Voltage vs. Forward Current
VF - 0.1 to 10 mA
Figure 5. Forward Voltage vs. Forward Current
VF - 10 to 800 mA
Figure 6. Forward Voltage vs. Ambient Temperature
VF - 0.01 - 20 mA (- 40 to +65°C)
110
120
130
140
150
160
Ta=25 oC
1 2 3 5 10 20 30 50 100
Reverse Voltage, V R [V]
Reverse Current, IR [uA]
0
20
40
60
80
100
120
10 20 30 50 70 100
Ta= 25 oC
Reverse Current, I R [nA]
Reverse Voltage, VR [V]
GENERAL RULE: The Reverse Current of a diode will approximately
double for every ten (10) Degree C increase in Temperature
250
300
350
400
450
500
550
1 2 3 5 10 20 30 50 100
Ta= 25 oC
Forward Voltage, V R [mV]
Forward Current, IF [uA]
450
500
550
600
650
700
750
0.1 0.2 0.3 0.5 1 2 3 5 10
Ta= 25 oC
Forward Voltage, V F [mV]
Forward Current, IF [mA]
0.6
0.8
1.0
1.2
1.4
1.6
10 20 30 50 100 200 300 500 800
Ta= 25 oC
Forward Voltage, V F [mV]
Forward Current, IF [mA]
0.01 0.1 1 10
300
400
500
600
700
800
900
0.03 0.3 3
Typical
Ta= -40 oC
Ta= 25 oC
Ta= +65 oC
Forward Voltage, V F [mV]
Forward Current, IF [mA]
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 — Small Signal Diode
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 Rev. 1.1.1 4
Typical Performance Characteristics (Continued)
Figure 7. Total Capacitance Figure 8. Reverse Recovery Time vs
Reverse Recovery Current
Figure 9. Average Rectified Current (IF(AV))
vs Ambient Temperature (TA)
Figure 10. Power Derating Curve
0 2 4 6 8 10 12 14
0.75
0.80
0.85
0.90
TA = 25 oC
Total Capacitance (pF)
REVERSE VOLTAGE (V)
10 20 30 40 50 60
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Ta = 25 oC
Reverse Recovery Time, t rr [ns]
Reverse Recovery Current, Irr [mA]
IF = 10mA , IRR = 1.0 mA , Rloop = 100 Ohms
0 50 100 150
0
100
200
300
400
500
IF(AV) - AVERAGE RECTIFIED CURRENT - mA
Current (mA)
Ambient Temperature ( oC)
0 50 100 150 200
0
100
200
300
400
500
DO-35
SOT-23
Power Dissipation, PD [mW]
Temperature [ oC]
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 — Small Signal Diode
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
1N/FDLL 914A/B / 916/A/B / 4148 / 4448 Rev. 1.1.1 5
Physical Dimensions
Figure 11. 2-TERMINAL, SOD-80, JEDEC DO-213AC, MINI-MELF
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/packaging/tr/SOD80A_tnr.pdf.
1.50
1.30
C R0.30
0.20
0.50 2.64 REF
0.30
3.60
3.30
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC DO-213, VARIATION AC.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C CORNER RADIUS IS OPTIONAL.
D) DRAWING FILE NAME: SOD80A REV01
SOD-80
© Fairchild Semiconductor Corporation www.fairchildsemi.com
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
2Cool
AccuPower
AX-CAP®*
BitSiC
Build it Now
CorePLUS
CorePOWER
CROSSVOLT
CTL
Current Transfer Logic
DEUXPEED®
Dual Cool™
EcoSPARK®
EfficientMax
ESBC
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series
FACT®
FAST®
FastvCore
FETBench
FPS
F-PFS
FRFET®
Global Power ResourceSM
GreenBridge
Green FPS
Green FPS e-Series
Gmax
GTO
IntelliMAX
ISOPLANAR
Making Small Speakers Sound Louder
and Better™
MegaBuck
MICROCOUPLER
MicroFET
MicroPak
MicroPak2
MillerDrive
MotionMax
mWSaver
OptoHiT
OPTOLOGIC®
OPTOPLANAR®
®
PowerTrench®
PowerXS™
Programmable Active Droop
QFET®
QS
Quiet Series
RapidConfigure
Saving our world, 1mW/W/kW at a time™
SignalWise
SmartMax
SMART START
Solutions for Your Success
SPM®
STEALTH
SuperFET®
SuperSOT-3
SuperSOT-6
SuperSOT-8
SupreMOS®
SyncFET
Sync-Lock™
®*
TinyBoost
TinyBuck
TinyCalc
TinyLogic®
TINYOPTO
TinyPower
TinyPWM
TinyWire
TranSiC
TriFault Detect
TRUECURRENT®*
SerDes
UHC®
Ultra FRFET
UniFET
VCX
VisualMax
VoltagePlus
XS™
* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN,
WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain
life, and (c) whose failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its
safety or effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com,
under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors
are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical
and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise.
Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global
problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Rev. I64
®
1N4148WS / 1N4448WS / 1N91
4BWS — Small Signal Diodes
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
1N4148WS / 1N4448WS / 1N914BWS Rev. B0 1
April 2012
1N4148WS / 1N4448WS / 1N914BWS
Small Signal Diodes
Features
• General Purpose Diodes
• Fast Switching Device (TRR < 4.0ns)
• Very Small and Thin SMD Package
• Moisture Level Sensitivity 1
• Pb-free Version and RoHS Compliant
• Matte Tin (Sn) Lead Finish
• Green Mold Compound
Absolute Maximum Ratings* Ta = 25°C unless otherwise noted
* These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
* Device mounted on FR-4 PCB minimum land pad.
Electrical Characteristics Ta = 25°C unless otherwise noted
Symbol Parameter Value Units
VRSM Non-Repetitive Peak Reverse Voltage 100 V
VRRM Repetitive Peak Reverse Voltage 75 V
IFRM Repetitive Peak Forward Current 300 mA
IO Continuous Forward Current 150 mA
TJ Operating Junction Temperature +150 °C
TSTG Storage Temperature Range -55 to +150 °C
Symbol Parameter Value Units
PD Power Dissipation (TC = 25°C) 200 mW
RθJA Thermal Resistance, Junction to Ambient * 500 °C/W
Symbol Parameter Test Conditions Min. Typ. Max. Units
BVR Breakdown Voltage IR = 100 μA
IR = 5 μA
100
75
V
V
IR Reverse Current VR = 20 V
VR = 75 V
25
5
nA
μA
VF Forward Voltage 1N4448WS/914BWS
1N4148WS
1N4448WS/914BWS
IF = 5 mA
IF = 10 mA
IF = 100 mA
0.62 0.72
1
1
V
V
V
CO Diode Capacitance VR = 0, f = 1 MHz 4 pF
TRR Reverse Recovery Time IF = 10 mA, IR = 60 mA,
IRR = 1 mA, RL = 100 Ω
4 ns
Band Indicates Cathode
1. Cathode
ELECTRICAL SYMBOL
2. Anode
SOD-323 Flat Lead
Device Marking Code
Device Type Device Marking
1N4148WS S1
1N4448WS S2
1N914BWS S3
2
11N4148WS / 1N4448WS / 1N91
4BWS — Small Signal Diodes
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
1N4148WS / 1N4448WS / 1N914BWS Rev. B0 2
Typical Performance Characteristics
Figure 1. Total Capacitance Figure 2. Forward Voltage vs. Ambient Temperature
Figure 3. Power Derating Curve Figure 4. Reverse Current vs. Reverse Voltage
Figure 5. Reverse Voltage vs. Reverse Current
Reverse Voltage (V)
0 2 4 6 8 10 12 14
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
TA=25°C
Capacitance [pF]
Forward Current, IF
[mA]
0.01 0.1 1 10 100
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Ta=-40°C
Ta=25°C
Ta=150°C
Typical
VF- Forward Voltage [V]
Temperature [°C]
0 25 50 75 100 125 150 175
0
50
100
150
200
250
PD - Power Dissipation [mW]
Reverse Voltage, VR[V]
10 20 30 40 50 60 70 80 90 100
10-1
100
101
102
103
104
105
Ta=150°C
Ta=25°C
Ta=-40°C
Reverse Current [nA]
VR - Reverse Voltage
Reverse Current, IR[µA]
1 10 100
140
150
160
170
Ta=25°C1N4148WS / 1N4448WS / 1N91
4BWS — Small Signal Diodes
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
1N4148WS / 1N4448WS / 1N914BWS Rev. B0 3
Physical Dimensions
SOD-323F
Dimensions in Millimeters© Fairchild Semiconductor Corporation www.fairchildsemi.com
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Rev. I61
39 ALIMENTATION FIXE A DÉCOUPAGE ALF1210 12 Volts continu 120 watts 10 Ampères - Output ripple < 3mV rms. - Built in power corrector (PFC). - Output voltage adjustable from 10 to 15V. - Short circuit protection. - Temperature controlled fan cooling. - Ausgangswelligkeit < 3mV effektiv. - Eingebaute Leistungsfaktorkorrektur (PFC) - Ausgangsspannung verstellbar zwischen 10 und 15 Volt. - Schutz gegen Kurzschlüsse. - Geregelte Lüftung. Autres caractéristiques • Sécurité : Classe II, double isolation, conforme à la norme EN 61010-1 • CEM : Conforme aux normes EN 50081-1 et 50082-1 • Indice de protection : IP 30 • Alimentation : Secteur 190 à 253 Volts, 50 / 60Hz. • Entrée secteur : cordon 2 pôles double isolation. • Consommation : 170W maxi. • Facteur de puissance : 0,99 (PFC intégré). • Rigidité diélectrique : 3000V entre entrée et sortie. • Présentation : Boîtier métal avec peinture époxy. Caractéristiques techniques Tension • Sorties flottantes sur douilles de sécurité de 4mm. • Tension de sortie : ajustable de 10 à 15V linéairement • Régulation : < 2mV pour une variation de charge de 0 à 100%. < 1mV pour une variation secteur de 190V à 253V. • Ondulation : < 3mV efficace comprenant : < 5mV crête à crête du signal à 100KHz < 5mV crête à crête du signal à 100Hz < 40mV crête à crête des pics de commutations • Temps de maintien : 25ms à 50% de charge et 12ms à 100% (secteur à 190V) • Visualisation : Led verte "alimentation en fonctionnement" Led rouge “status, défaut sur la sortie” Intensité • I maxi : 10,5A au court-circuit 10A de 10 à 15V Puissance • Puissance max. de sortie : 150W. Protections • Contre les courts-circuits par limitation de courant. • Contre les surintensités sur la source, par fusible. • Contre les surtensions en sortie, par limitation de tension à 17V. - Ondulation de sortie < 3mV efficace. - Correcteur du facteur de puissance (PFC) intégré. - Tension de sortie ajustable de 10 à 15 Volts. - Protection contre les courts-circuits. - Ventilation controlée. Other specifications • Safety : Classe II, double insulation, according to EN 61010-1. • EMC : Complies with EN 50081-1 and 50082-1. • Protection level : IP 30. • Input voltage : 190 to 253 Volts, 50 / 60 Hz. • Mains input : double insulation 2 poles cable. • Power consumption : 170 W max. • Power factor : 0.99 (built in PFC). • Dielectric strength : 3000V. • Presentation : metal case with epoxy finish. Specifications Voltage • Floating outputs on 4 mm safety sockets. • Output voltage : adjustable from 10 to 15V linearly. • Regulation : < 1mV for a load change from 0 to 100%. < 1mV for a line change from 190 to 253V. • Ripple : < 3mV rms including: < 5mV peak to peak of the signal at 100 KHz < 5mV peak to peak of the signal at 100 Hz < 40mV peak to peak of switching spikes • Hold-up time : 25 ms at half load and 12 ms at full load (190V line input). • Indicator : green power-on LED indicator. "status, output fault" red LED. Current • Max I : 10,5A in short circuit condition. 10A from 10 to 15V Power • Max output power : 150W. Protection • Short circuit protection, by current regulation. • Transformer primary overcurrent protection, by fuse. • Output overload protection by voltage limiting to 17V. 38 Andere Eigenschaften • Schutz : Klasse II, schutzisoliert, entspricht den Normen EN 61010-1. • EMC : Entspricht den Normen EN 50081-1 und 50082-1. • Schutzart : IP 30. • Versorgung : Netzversorgung 190 bis 253 Volt, 50 / 60 Hz. • Netzversorgungseingang : schutzisoliertes 2-Phasen-Netzkabel. • Leistungsaufnahme : max. 170W. • Leistungsfaktor : 0,99 (PFC integriert). • Durchschlagsfestigkeit : 3000V. • Erscheinungsbild : Metallgehäuse mit Epoxid-Lackierung. Technische Daten Spannung • Ausgänge von Masse getrennt (floating) auf 4-mm-Schutzbuchsen. • Ausgangsspannung : linear verstellbar zwischen 10 und 15 V. • Regelung : < 1mV bei Laständerungen von 0 bis 100%. < 1mV bei Schwankungen der Netzversorgung zwischen 190V und 253V. • Welligkeit : < 3mV effektiv mit: < 3mV Spitze-Spitze des Signals bei 100kHz < 4mV Spitze-Spitze des Signals bei 100Hz < 12mV Spitze-Spitze von Schaltspitzen • Haltezeit : 25ms bei 50% der Last und 12ms bei 100% (Netzversorgung bei 190V). • Anzeige : Grüne LED “Versorgung bei Betrieb”. Rote LED "Status, Fehler auf Ausgang" Stromstärke • I max : 10,5A bei Kurzschluss 10A von 10 bis 15V Liestung • Max. Ausgangsleistung : 150 W. Schutzvorrichtungen • Gegen Kurzschlüsse durch Strombegrenzung. • Gegen Überströme auf dem Primärkreis des Transformators durch Sicherung . • Gegen Überspannungen am Ausgang durch Spannungsbegrenzung auf 17 V. Switching fixed power supply ALF1210 Feste Unterbrechungsfreie Versorgung ALF1210 Séries TDS1000B et TDS2000B Oscilloscope à mémoire numérique Manuel de l’utilisateur Révision B www.tektronix.com 071-1818-00 Copyright © Tektronix. Tous droits réservés. Les produits logiciels sous licence sont la propriété de Tektronix, de ses filiales ou de ses fournisseurs et sont protégés par les lois nationales sur le copyright, ainsi que par des traités internationaux. Les produits Tektronix sont protégés par des brevets américains et étrangers déjà déposés ou en cours d’obtention. Les informations contenues dans le présent document remplacent celles publiées précédemment. Les spécifications et les prix peuvent être soumis à modification. TEKTRONIX et TEK sont des marques déposées de Tektronix, Inc. OpenChoice™ est une marque déposée de Tektronix, Inc. PictBridge™ est une marque déposée de la norme CIPA DC-001-2003 Digital Photo Solutions for Imaging Devices de la Camera & Imaging Products Association. Coordonnées de Tektronix Tektronix, Inc. 14200 SW Karl Braun Drive P.O. Box 500 Beaverton, OR 97077 Etats-Unis Pour obtenir des informations sur le produit, la vente, les services et l’assistance technique : En Amérique du Nord, appelez le 1-800-833-9200. Pour les autres pays, visitez le site www.tektronix.com pour connaître les coordonnées locales. Oscilloscopes TDS1000B et TDS2000B Garantie 18 – Garantie limitée à la durée de vie Tektronix garantit à l’acheteur-utilisateur final d’origine (ci-après dénommé le « premier acheteur ») du produit désigné ci-dessous que ce dernier est exempt de défaut au niveau des matériaux et de la fabrication durant toute la durée de vie du produit. Dans les présentes, la « durée de vie du produit » est définie comme une période de cinq (5) années suivant la fin de la fabrication du produit par Tektronix (comme défini par Tektronix), mais la période de garantie sera d’au moins dix (10) ans à compter de la date d’achat du produit par le premier acheteur à Tektronix ou à un l’un de ses distributeurs agréés. La présente garantie limitée à la durée de vie concerne uniquement le premier acheteur et ne peut être transférée. Si une réclamation concernant la garantie intervient avant la fin de celle-ci, l’acheteur doit fournir une preuve satisfaisante de la date d’achat à Tektronix ou à un distributeur agréé et du fait qu’il est le premier acheteur. En cas de vente ou de transfert du produit par le premier acheteur à un tiers dans les trois (3) ans à compter de la date d’achat du produit par le premier acheteur, la période de garantie sera de trois (3) ans à compter de la date d’achat du produit par le premier acheteur à Tektronix ou à un distributeur agréé. Les sondes, autres accessoires, batteries et fusibles ne sont pas couverts par la garantie. Si l’un des produits Tektronix se révèle défectueux pendant ladite période de garantie, Tektronix peut au choix réparer le produit en question en prenant à sa charge les frais de main-d’oeuvre et de pièces ou bien fournir un produit de remplacement équivalent (comme établi par Tektronix) en échange du produit défectueux. Les pièces, modules et produits de remplacement utilisés par Tektronix pour des travaux sous garantie peuvent être neufs ou reconditionnés pour de nouvelles performances. Tous les produits, modules et pièces de rechange deviennent la propriété de Tektronix. Dans les présentes, le « client » est la personne ou l’entité revendiquant ses droits en vertu de la présente garantie. Pour pouvoir prétendre à la garantie, le client doit signaler le défaut à Tektronix avant l’expiration de la période de garantie applicable et effectuer les démarches correspondantes. Il appartient au client d’emballer et d’expédier le produit défectueux au centre de réparation indiqué par Tektronix, avec les frais d’expédition prépayés et une copie du certificat d’achat du premier acheteur. Tektronix prend à sa charge la réexpédition du produit au client, si le destinataire se trouve dans le pays où le centre de réparation Tektronix est implanté. Tous les frais d’expédition, droits, taxes et autres coûts afférents à la réexpédition du produit dans un autre lieu sont à la charge du client. Cette garantie est caduque en cas de défaillance, de panne ou de dommage provoqué par un accident, l’usure ou des dégradations d’éléments mécaniques, l’utilisation non conforme aux spécifications du produit, un usage impropre ou un défaut de soin ou de maintenance. Tektronix n’est pas contraint d’assurer les réparations sous garantie dans les cas suivants : a) réparations résultant de dommages provoqués par un personnel non mandaté par Tektronix ayant installé, réparé ou entretenu le produit ; b) réparations résultant d’une utilisation impropre ou d’un raccordement à des équipements incompatibles ; c) réparation de dommages ou de dysfonctionnements résultant de l’utilisation de pièces non fournies par Tektronix ; d) entretien d’un produit modifié ou intégré à d’autres produits, rendant ainsi le produit plus difficile à entretenir ou augmentant la périodicité des entretiens. LA PRESENTE GARANTIE DEFINIE PAR TEKTRONIX QUANT AU PRODUIT TIENT LIEU DE TOUTE AUTRE GARANTIE, EXPLICITE OU IMPLICITE. TEKTRONIX ET SES FOURNISSEURS NE DONNENT AUCUNE GARANTIE IMPLICITE QUANT A LA QUALITE MARCHANDE OU A L’ADEQUATION DU PRODUIT A DES USAGES PARTICULIERS. LE SEUL RECOURS DU CLIENT EN CAS DE VIOLATION DE CETTE GARANTIE EST D’EXIGER DE TEKTRONIX QU’IL REPARE OU REMPLACE LE PRODUIT DEFECTUEUX. TEKTRONIX ET SES FOURNISSEURS NE POURRONT PAR CONSEQUENT PAS ETRE TENUS POUR RESPONSABLES DES DOMMAGES INDIRECTS, SPECIAUX OU CONSECUTIFS, MEME S’ILS SONT INFORMES AU PREALABLE DE L’EVENTUALITE DES DOMMAGES EN QUESTION. Sonde P2220 Garantie 2 Tektronix garantit que ce produit est exempt de défaut au niveau des matériaux et de la fabrication, pendant une période de un (1) an à compter de la date d’expédition. Si un produit Tektronix se révèle défectueux pendant sa période de garantie, Tektronix peut soit réparer le produit en question, en prenant à sa charge les frais de main-d’oeuvre et de pièces, soit fournir un produit de remplacement en échange de celui défectueux. Les pièces, modules et produits de remplacement utilisés par Tektronix pour des travaux sous garantie peuvent être neufs ou reconditionnés pour de nouvelles performances. Tous les produits, modules et pièces de rechange deviennent la propriété de Tektronix. Pour pouvoir prétendre à la garantie, le client doit signaler le défaut à Tektronix avant l’expiration de la période de garantie et effectuer les démarches correspondantes. Il appartient au client d’emballer et d’expédier en port payé le produit défectueux au centre de réparation indiqué par Tektronix. Tektronix prend à sa charge la réexpédition du produit au client, si le destinataire se trouve dans le pays où le centre de réparation Tektronix est implanté. Tous les frais d’expédition, droits, taxes et autres coûts afférents à la réexpédition du produit dans un autre lieu sont à la charge du client. Cette garantie est caduque en cas de défaillance, de panne ou de dommage provoqué par un usage impropre ou un défaut de soin ou de maintenance. Tektronix n’est pas contraint d’assurer les réparations sous garantie dans les cas suivants : a) réparations résultant de dommages provoqués par un personnel non mandaté par Tektronix qui a installé, réparé ou entretenu le produit ; b) réparations résultant d’une utilisation impropre ou d’un raccordement à des équipements incompatibles ; c) réparation de dommages ou de dysfonctionnements résultant de l’utilisation de pièces non fournies par Tektronix ; ou d) entretien d’un produit modifié ou intégré à d’autres produits, rendant ainsi le produit plus difficile à entretenir ou augmentant la périodicité des entretiens. LA PRESENTE GARANTIE DEFINIE PAR TEKTRONIX EU EGARD AU PRODUIT TIENT LIEU DE TOUTE AUTRE GARANTIE, EXPLICITE OU IMPLICITE. TEKTRONIX ET SES FOURNISSEURS NE DONNENT AUCUNE GARANTIE IMPLICITE QUANT A LA QUALITE MARCHANDE OU A L’ADEQUATION DU PRODUIT A DES USAGES PARTICULIERS. LE SEUL RECOURS DU CLIENT EN CAS DE VIOLATION DE CETTE GARANTIE EST D’EXIGER DE TEKTRONIX QU’IL REPARE OU REMPLACE LE PRODUIT DEFECTUEUX. TEKTRONIX ET SES FOURNISSEURS NE POURRONT PAR CONSEQUENT PAS ETRE TENUS POUR RESPONSABLES DES DOMMAGES INDIRECTS, SPECIAUX OU CONSECUTIFS, MEME S’ILS SONT INFORMES AU PREALABLE DE L’EVENTUALITE DES DOMMAGES EN QUESTION. Table des matières Consignes générales de sécurité........................................ iv Environnement.......................................................... vii Préface.................................................................... ix Système d’aide ...................................................... x Mises à jour du firmware via Internet ............................ xi Conventions........................................................ xii Démarrage ................................................................ 1 Fonctions générales ................................................. 1 Installation ........................................................... 3 Test de fonctionnement ............................................. 4 Sécurité de la sonde ................................................. 5 Assistant Test de sonde de tension ................................. 5 Compensation manuelle de sonde.................................. 7 Réglage d’atténuation de la sonde ................................. 8 Mise à échelle de la sonde de courant ............................. 9 Calibrage automatique .............................................. 9 Principes de fonctionnement .......................................... 11 Zone d’affichage................................................... 11 Utilisation du système de menus ................................. 15 Réglages verticaux ................................................ 17 Réglages horizontaux ............................................. 18 Commandes de déclenchement .................................. 19 Boutons de menu et de commande............................... 20 Connecteurs d’entrée.............................................. 23 Autres éléments du panneau avant ............................... 24 Compréhension des fonctions de l’oscilloscope ..................... 25 Réglage de l’oscilloscope......................................... 25 Déclenchement .................................................... 27 Acquisition de signaux............................................ 29 Mise à l’échelle et positionnement de signaux.................. 30 Prise de mesures................................................... 35 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B i Table des matières Exemples d’application ................................................ 37 Prise de mesures simples ......................................... 38 Utilisation de la fonction de calibrage automatique (Autorange) pour examiner une série de points de test .................. 44 Mesures par curseur ............................................... 45 Analyse détaillée du signal ....................................... 50 Acquisition d’un signal monocoup .............................. 53 Mesure du retard de propagation................................. 55 Déclenchement sur une largeur d’impulsion spécifique........ 56 Déclenchement sur un signal vidéo.............................. 58 Analyse d’un signal de communication différentiel ............ 64 Affichage des modifications d’impédance sur un réseau....... 66 Fonctions mathématiques FFT ........................................ 69 Réglage du signal temporel....................................... 69 Affichage du spectre FFT......................................... 71 Sélection d’une fenêtre FFT...................................... 73 Agrandissement et positionnement d’un spectre FFT .......... 76 Mesure d’un spectre FFT à l’aide des curseurs ................. 77 Port du lecteur flash USB et port périphérique....................... 79 Port du lecteur flash USB......................................... 79 Conventions de gestion des fichiers.............................. 82 Sauvegarde et rappel de fichiers avec un lecteur flash USB ... 83 Utilisation de la fonction de sauvegarde du bouton PRINT du panneau avant ................................................ 85 Port périphérique USB............................................ 89 Installation du logiciel de communication sur un PC .......... 89 Connexion à un PC................................................ 90 Connexion à un système GPIB................................... 93 Saisie de commande............................................... 93 Connexion à une imprimante..................................... 94 Imprimer une image d’écran ..................................... 95 Référence................................................................ 97 Acquisition......................................................... 97 Calibrage Auto ................................................... 101 Réglage automatique (Autoset) ................................. 103 ii Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Table des matières Curseurs ........................................................... 107 Configuration par défaut ......................................... 109 Affichage.......................................................... 109 Aide ............................................................... 112 Horizontal ......................................................... 112 Fonctions mathématiques........................................ 115 Mesures ........................................................... 116 Imprimer .......................................................... 118 Test de sonde...................................................... 119 Menu Réf.......................................................... 119 Sauvegarder/Rappeler............................................ 120 Commandes de déclenchement ................................. 127 Utilitaire........................................................... 136 Réglages verticaux ............................................... 140 Annexe A : Spécifications ............................................ 145 Spécifications de l’oscilloscope ................................. 145 Homologations et conformité de l’oscilloscope ............... 158 Spécifications relatives à la sonde P2220 ...................... 163 Annexe B : Accessoires ............................................... 167 Annexe C : Nettoyage................................................. 171 Entretien - Généralités ........................................... 171 Nettoyage ......................................................... 171 Annexe D : Configuration par défaut ................................ 173 Annexe E : Licences de police ....................................... 177 Index Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B iii Consignes générales de sécurité Consignes générales de sécurité Veuillez lire avec attention les précautions et consignes de sécurité suivantes, afin d’éviter toute blessure et l’endommagement éventuel de cet appareil et des produits qui lui sont associés. Pour écarter tout danger, utilisez uniquement cet appareil dans les conditions spécifiées. Seul un personnel qualifié doit être autorisé à effectuer les opérations d’entretien. Pour éviter les incendies et les dommages corporels Utilisez le cordon d’alimentation spécifié. Utilisez uniquement le cordon d’alimentation prévu pour cet appareil et conforme aux normes du pays d’utilisation. Procédez aux branchements et débranchements de manière appropriée Branchez la sortie de sonde à l’instrument de mesure avant de brancher la sonde sur le circuit à tester. Branchez le fil de référence de la sonde sur le circuit à tester avant de brancher l’entrée de la sonde. Débranchez l’entrée et le fil de référence de la sonde du circuit testé avant de débrancher la sonde de l’instrument de mesure. Mettez le produit à la terre. Ce produit est raccordé à la terre au moyen du fil de masse du cordon d’alimentation. Pour éviter tout choc électrique, le fil de masse doit être connecté à une prise de terre. Avant de procéder aux branchements des bornes d’entrée et de sortie du produit, veillez à ce que celui-ci soit correctement mis à la terre. Respectez toutes les valeurs nominales des terminaux. Pour éviter tout risque d’incendie ou de choc électrique, respectez les valeurs nominales et les indications figurant sur le produit. Consultez le manuel livré avec le produit où figurent toutes les informations complémentaires avant de procéder au branchement du produit. Branchez le fil de référence de la sonde sur la terre uniquement. N’appliquez à une borne (borne commune incluse) aucun potentiel dépassant la valeur maximale de cette borne. iv Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Consignes générales de sécurité Interrupteur d’alimentation L’interrupteur d’alimentation permet de déconnecter le produit de la source d’alimentation. Consultez les instructions pour connaître l’emplacement de cet interrupteur. Ne bloquez pas l’interrupteur d’alimentation ; il doit rester accessible à tout moment. Ne mettez pas l’appareil en service sans ses capots de protection. Ne mettez pas l’appareil en service si les capots ou panneaux de protection ont été retirés. N’utilisez pas l’appareil en cas de défaillance suspecte. En cas de doute sur le bon état de cet appareil, faites-le inspecter par un technicien qualifié. Evitez tout circuit exposé. Ne touchez à aucun branchement ou composant exposé lorsque l’appareil est sous tension. N’utilisez pas l’appareil dans un environnement humide. N’utilisez pas l’appareil dans un environnement explosif. Maintenez les surfaces du produit propres et sèches. Assurez une ventilation adéquate. Reportez-vous aux instructions d’installation du manuel pour plus de détails sur la mise en place d’une ventilation adéquate du produit. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B v Consignes générales de sécurité Termes apparaissant dans ce manuel. Les mentions suivantes peuvent figurer dans ce manuel : AVERTISSEMENT. Les avertissements identifient des situations ou des opérations pouvant entraîner des blessures graves ou mortelles. ATTENTION. Les mises en garde identifient des situations ou des opérations susceptibles d’endommager le matériel ou d’autres équipements. Symboles et termes relatifs au produit Les mentions suivantes peuvent figurer sur le produit : La mention « DANGER » indique un risque de blessure immédiate à la lecture de l’étiquette. La mention « AVERTISSEMENT » indique un risque de blessure non immédiate à la lecture de l’étiquette. La mention « PRECAUTION » indique un risque de dommage matériel, y compris du produit. Les symboles suivants peuvent figurer sur le produit : vi Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Environnement Cette section contient des informations concernant l’impact du produit sur l’environnement. Recyclage du produit Observez la procédure ci-dessous pour le recyclage d’un instrument ou d’un composant : Recyclage de l’appareil. La fabrication du présent appareil a exigé l’extraction et l’utilisation de ressources naturelles. Il peut contenir des substances potentiellement dangereuses pour l’environnement ou la santé si elles ne sont pas correctement traitées lors de la mise au rebut de l’appareil. Pour éviter la diffusion de telles substances dans l’environnement et réduire l’utilisation des ressources naturelles, nous vous encourageons à recycler ce produit de manière appropriée, afin de garantir que la majorité des matériaux soient correctement réutilisés ou recyclés. Le symbole ci-dessous indique que ce produit respecte les exigences de l’Union européenne, conformément à la directive 2002/96/CE relative aux déchets d’équipements électriques et électroniques (DEEE). Pour plus d’informations sur les solutions de recyclage, reportez-vous à la section Assistance/Maintenance du site Web de Tektronix (www.tektronix.com). Remarque relative au mercure. Ce produit est équipé d’une lampe de rétroéclairage LCD contenant du mercure. Sa mise au rebut est soumise à la réglementation en vigueur concernant l’environnement. Pour connaître les conditions de mise au rebut ou de recyclage, contactez les autorités locales ou, pour les Etats-Unis, l’EIA (Electronics Industries Alliance, www.eiae.org). Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B vii Environnement Restriction concernant les substances dangereuses Cet appareil est considéré comme un appareil de contrôle et de surveillance, non pris en charge par la directive 2002/95/CE relative à la limitation de l’utilisation de certaines substances dangereuses dans les équipements électriques et électroniques. Ce produit contient, de manière avérée, du plomb, du cadmium, du mercure et du chrome hexavalent. viii Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Préface Préface Ce manuel contient des informations relatives au fonctionnement des oscilloscopes à mémoire numérique TDS1000B et TDS2000B. Il se compose des chapitres suivants : Le chapitre Démarrage décrit brièvement les fonctions de l’oscilloscope et fournit des instructions relatives à l’installation. Le chapitre Principes de fonctionnement explique le fonctionnement des oscilloscopes. Le chapitre Compréhension des fonctions de l’oscilloscope décrit les opérations et les fonctions de base d’un oscilloscope : configuration de l’oscilloscope, déclenchement, acquisition de données, mise à l’échelle et positionnement des signaux et prise de mesures. Le chapitre Exemples d’application fournit des exemples de solutions visant à résoudre divers problèmes de mesures. Le chapitre Fonction mathématique FFT explique comment utiliser la fonction mathématique Transformée de Fourier Rapide (FFT) pour convertir un signal temporel en ses composantes de fréquence (spectre). Le chapitre Port du lecteur flash USB et port périphérique décrit l’utilisation du port du lecteur flash USB et le raccordement de l’oscilloscope aux imprimantes et aux ordinateurs via le port périphérique USB. Le chapitre Référence décrit les sélections ou la gamme de valeurs disponibles pour chaque option. L’annexe A : Spécifications contient les spécifications électriques, environnementales et physiques de l’oscilloscope et de la sonde P2220, ainsi que des homologations et des conformités. L’annexe B : Accessoires décrit brièvement les accessoires standard et en option. L’annexe C : Nettoyage décrit comment entretenir l’oscilloscope. L’annexe D : Configuration par défaut contient la liste des menus et des commandes avec leurs configurations (d’usine) par défaut, Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B ix Préface rétablies lorsque vous appuyez sur le bouton CONF. PAR D. du panneau avant. L’annexe E : Licences de police fournit les licences permettant d’utiliser des polices asiatiques spécifiques. Système d’aide L’oscilloscope dispose d’un système d’aide doté de rubriques couvrant toutes les fonctions de l’appareil. Ce système d’aide vous permet d’afficher différents types d’informations : des informations générales portant sur la compréhension et l’utilisation de l’oscilloscope, telles que Utilisation du système de menus ; des informations portant sur les menus et les commandes spécifiques, telles que Commande de position verticale ; des conseils portant sur les problèmes que vous pouvez rencontrer lors de l’utilisation de l’oscilloscope, tels que Réduction du bruit. Le système d’aide met à votre disposition différents moyens de trouver les informations dont vous avez besoin : aide contextuelle, liens hypertexte et index. Aide contextuelle Lorsque vous appuyez sur le bouton AIDE du panneau avant, l’oscilloscope affiche des informations relatives au dernier menu affiché à l’écran. Lorsque vous visualisez les rubriques d’aide, un voyant LED s’allume à côté du bouton multifonctionnel pour indiquer que ce dernier est actif. Si la rubrique s’étend sur plus d’une page, tournez le bouton multifonctionnel pour passer d’une page à l’autre de la rubrique. x Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Préface Liens hypertexte La plupart des rubriques d’aide présentent des phrases dotées de passage entre chevrons, tels que . Il s’agit de liens vers d’autres rubriques. Tournez le bouton multifonctionnel pour sélectionner les différents liens. Appuyez sur le bouton d’option Afficher sujet pour consulter la rubrique correspondant au lien mis en surbrillance. Appuyez sur le bouton d’option Retour pour revenir à la rubrique précédente. Index Appuyez sur le bouton AIDE du panneau avant, puis appuyez sur le bouton d’option Index. Appuyez sur les boutons d’option Page précédente ou Page suivante jusqu’à ce que vous trouviez la page d’index contenant la rubrique que vous souhaitez afficher. Tournez le bouton multifonctionnel pour mettre en surbrillance la rubrique d’aide qui vous intéresse. Appuyez sur le bouton Afficher sujet pour afficher la rubrique. REMARQUE. Appuyez sur le bouton d’option Quitter ou sur un bouton de menu quelconque pour quitter l’écran d’aide affiché et revenir à l’affichage des signaux. Mises à jour du firmware via Internet Si une version plus récente du micrologiciel est disponible, vous pouvez utiliser Internet et un lecteur flash USB pour mettre à jour votre oscilloscope. Si vous ne disposez pas d’un accès à Internet, contactez Tektronix pour obtenir des informations sur les procédures de mise à jour. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B xi Préface Pour mettre à jour le micrologiciel via Internet, procédez comme suit : 1. Appuyez sur UTILITAIRE ► Etat du système et notez le numéro de version du micrologiciel de l’oscilloscope. 2. Depuis votre ordinateur, accédez au site Web www.tektronix.com et vérifiez la disponibilité d’une version plus récente du micrologiciel pour l’oscilloscope. 3. Si une version plus récente est disponible, téléchargez le fichier du micrologiciel à partir de la page Web. Vous devrez peut-être décompresser le fichier téléchargé. 4. Copiez le fichier du micrologiciel TDS1K2KB.TEK dans le dossier racine du lecteur flash USB. 5. Insérez le lecteur flash USB dans le port du lecteur flash USB situé sur le panneau avant de l’oscilloscope. 6. Sur votre oscilloscope, appuyez sur le bouton d’option UTILITAIRE ► Utilitaires Fichiers ► - suite - p. 2 de 2 ► M. à jour Firmware. La mise à jour du micrologiciel prend plusieurs minutes. Lorsque que la mise à jour du microprogramme est terminée, l’oscilloscope vous invite à appuyer sur un bouton. Vous ne devez pas retirer le lecteur flash USB ou mettre l’oscilloscope hors tension avant la fin de la mise à jour du microprogramme. Conventions Ce manuel utilise les conventions suivantes : Les boutons, molettes et connecteurs du panneau avant apparaissent en lettres majuscules. Par exemple : AIDE, PRINT. La première lettre des options de menu est en majuscules. Par exemple : Détect Créte, Zone retardée. xii Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Préface Bouton multifonctionnel Etiquettes des boutons et molettes du panneau avant : tout en majuscules Boutons d’option : première lettre de chaque mot apparaissant à l’écran en majuscules REMARQUE. Les boutons d’options peuvent également être appelés boutons d’écran, boutons du menu latéral, boutons du panneau ou touches programmables. Le délimiteur ► sert à séparer les boutons dans une séquence à réaliser. Par exemple, UTILITAIRE ► Options ► Régler date et heure signifie que vous devez appuyer sur le bouton UTILITAIRE du panneau avant, puis sur le bouton d’option Options, et enfin sur le bouton d’option Régler date et heure. Il est parfois nécessaire d’utiliser plusieurs boutons pour sélectionner l’option souhaitée. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B xiii Préface xiv Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Démarrage Les oscilloscopes à mémoire numérique TDS1000B et TDS2000B sont des oscilloscopes de table compacts et légers, que vous pouvez utiliser pour prendre des mesures référencées au sol. Ce chapitre décrit comment : installer votre produit, effectuer une brève vérification du fonctionnement, effectuer un test de sonde et compenser les sondes, faire correspondre votre facteur d’atténuation de sonde, utiliser le programme de calibrage automatique. REMARQUE. Vous pouvez sélectionner la langue affichée à l’écran lorsque vous mettez l’oscilloscope sous tension. A tout moment, vous pouvez accéder à l’option UTILITAIRE ► Language pour sélectionner la langue souhaitée. Fonctions générales Le tableau et la liste qui suivent décrivent les fonctions générales. Modèle Voies Bande passante Fréquence d’échantillonnageAffichage TDS1001B 2 40 MHz 500 éch./s Monochrome TDS1002B 2 60 MHz 1 G éch./s Monochrome TDS1012B 2 100 MHz 1 G éch./s Monochrome TDS2002B 2 60 MHz 1 G éch./s Couleur TDS2004B 4 60 MHz 1 G éch./s Couleur TDS2012B 2 100 MHz 1 G éch./s Couleur TDS2014B 4 100 MHz 1 G éch./s Couleur TDS2022B 2 200 MHz 2 G éch./s Couleur TDS2024B 4 200 MHz 2 G éch./s Couleur Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 1 Démarrage Aide contextuelle Ecran LCD couleur ou monochrome Limite de bande passante de 20 MHz sélectionnable Longueur d’enregistrement de 2 500 points pour chaque voie Réglage automatique (Autoset) Ajustement automatique Assistant Test de sonde Stockage de la configuration et du signal Port du lecteur flash USB pour stockage des fichiers Impression directe sur imprimante compatible PictBridge Communications avec l’ordinateur via le port périphérique USB doté du logiciel de communication pour PC OpenChoice Connexion à un contrôleur GPIB par un adaptateur TEK-USB-488 en option Curseurs dotés d’un affichage Mesure de la fréquence de déclenchement Onze mesures automatiques Moyenne du signal et Détect Créte Double base de temps Fonctions mathématiques : opérations +, - et × Fonction mathématique Transformée de Fourier Rapide (FFT) Fonctionnalité de déclenchement sur largeur d’impulsion Capacité de déclenchement vidéo avec déclenchement sélectionnable par ligne Déclenchement externe Affichage à persistance variable Interface utilisateur et rubriques d’aide en dix langues 2 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Démarrage Installation Cordon d’alimentation Utilisez uniquement le cordon d’alimentation fourni avec l’oscilloscope. L’Annexe B : Accessoires dresse la liste des accessoires standard et en option. Source d’alimentation Utilisez une source d’alimentation délivrant 90 à 264 V CAeff, de 45 à 66 Hz. Si vous disposez d’une source d’alimentation de 400 Hz, elle doit délivrer 90 à 132 V CAeff, de 360 à 440 Hz. Boucle de sécurité Utilisez un verrou de sécurité standard d’ordinateur portable ou faites passer un câble de sécurité par la voie de câble intégrée afin d’attacher votre oscilloscope. Voie de câble de sécurité Orifice du verrou de sécurité Cordon d’alimentation Ventilation REMARQUE. L’oscilloscope refroidit par convection. Laissez cinq centimètres de chaque côté et au-dessus de l’appareil pour permettre à l’air de circuler. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 3 Démarrage Test de fonctionnement Effectuez le test suivant pour vous assurer du bon fonctionnement de l’oscilloscope. Bouton ON/OFF 1. Mettez l’oscilloscope sous tension. Appuyez sur le bouton CONF. PAR D. Le réglage d’atténuation par défaut de l’option Sonde est 10X. CONF. PAR D., bouton COMP SONDE 2. Réglez le commutateur de la sonde P2220 sur 10X et raccordez la sonde à la voie 1 de l’oscilloscope. Pour ce faire, alignez l’emplacement du connecteur de la sonde avec la touche du connecteur BNC CH 1, appuyez pour effectuer la connexion et tournez la sonde vers la droite pour la verrouiller. Connectez l’extrémité de la sonde et le câble de référence aux bornes COMP SONDE. 3. Appuyez sur le bouton AUTOSET. Au bout de quelques secondes, une onde carrée de 5 V crête à crête à 1 kHz doit s’afficher à l’écran. Appuyez deux fois sur le bouton CH1 MENU du panneau avant pour supprimer la voie 1, appuyez sur le bouton CH2 MENU pour afficher la voie 2 et répétez les étapes 2 et 3. Pour les modèles à 4 voies, répétez la procédure pour les voies 3 et 4. 4 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Démarrage Sécurité de la sonde Vérifiez les valeurs nominales des sondes avant de les utiliser et respectez ces valeurs. Un manchon entourant le corps de la sonde P2220 protège les doigts contre tout choc électrique. Protège-doigts AVERTISSEMENT. Pour éviter tout choc électrique lors de l’utilisation de la sonde, gardez vos doigts derrière le manchon entourant le corps de la sonde. Pour éviter tout choc électrique lors de l’utilisation de la sonde, ne touchez aucune partie métallique de la tête de sonde lorsque celle-ci est branchée sur une source de tension. Raccordez la sonde à l’oscilloscope et la borne de mise à la terre à la masse avant de prendre des mesures. Assistant Test de sonde de tension L’assistant Test de sonde permet de vérifier rapidement le bon fonctionnement d’une sonde de tension. Il ne prend pas en charge les sondes de courant. L’assistant vous permet de régler la compensation des sondes de tension (généralement à l’aide d’un tournevis sur le corps ou un connecteur de la sonde) et de définir le facteur d’atténuation de chaque voie, comme dans l’option CH 1 MENU ► Sonde ► Tension ► Atténuation. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 5 Démarrage Utilisez l’assistant Test de sonde pour chaque raccordement d’une sonde de tension à une voie d’entrée. Pour utiliser l’assistant Test de sonde, appuyez sur le bouton TEST SONDE. Si la sonde de tension est correctement raccordée et compensée et si l’option Atténuation dans le menu VERTICAL de l’oscilloscope correspond bien à la sonde, l’oscilloscope indique alors PASSE en bas de l’écran. Sinon, l’oscilloscope indique la marche à suivre à l’écran pour vous permettre de résoudre ces problèmes. REMARQUE. L’assistant Test de sonde est utile pour les sondes 1X, 10X, 20X, 50X et 100X. Il ne sert pas pour les sondes 500X ou 1000X, ni pour les sondes raccordées au connecteur BNC EXTERNE. REMARQUE. Une fois le processus terminé, l’assistant Test de sonde rétablit les paramètres de l’oscilloscope (autres que l’option Sonde) à la valeur qu’ils avaient avant d’appuyer sur le bouton TEST SONDE. Pour compenser une sonde que vous envisagez d’utiliser avec l’entrée EXTERNE, procédez comme suit : 1. Raccordez la sonde au connecteur BNC d’une voie d’entrée quelconque, par exemple CH 1. 2. Appuyez sur le bouton TEST SONDE et suivez les instructions à l’écran. 3. Après avoir vérifié que la sonde fonctionne et qu’elle est correctement compensée, raccordez-la au connecteur BNC EXTERNE. 6 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Démarrage Compensation manuelle de sonde Il existe une alternative à l’assistant Test de sonde, qui consiste à effectuer manuellement ce réglage afin de faire correspondre votre sonde à la voie d’entrée. COMP SONDE Bouton AUTOSET 1. Appuyez sur CH 1 MENU ► Sonde ► Tension ► Atténuation, puis sélectionnez 10X. Réglez le commutateur de la sonde P2220 sur 10X et raccordez la sonde à la voie 1 de l’oscilloscope. Si vous utilisez un embout en crochet pour la sonde, assurez-vous que la connexion s’effectue correctement en insérant fermement l’embout dans la sonde. 2. Fixez l’extrémité de la sonde à la terminaison COMP SONDE ~5V à 1kHz et le câble de référence à la terminaison COMP SONDE du châssis. Affichez la voie, puis appuyez sur le bouton AUTOSET. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 7 Démarrage Surcompensé Sous-compensé Compensé correctement 3. Vérifiez la forme du signal affiché. 4. Au besoin, ajustez la sonde. L’illustration montre une sonde P2220. Recommencez cette étape si nécessaire. Réglage d’atténuation de la sonde Les sondes sont proposées avec divers facteurs d’atténuation qui affectent l’échelle verticale du signal. L’assistant Test de sonde vérifie que le facteur d’atténuation sélectionné dans l’oscilloscope correspond à la sonde. Au lieu d’utiliser l’assistant Test de sonde, vous pouvez sélectionner manuellement le facteur correspondant à l’atténuation de votre sonde. Par exemple, pour régler l’oscilloscope pour une sonde 10X connectée à CH 1, appuyez sur CH 1 MENU ► Sonde ► Tension ► Atténuation, puis sélectionnez 10X. REMARQUE. Le réglage par défaut de l’option Atténuation est 10X. Si vous changez le commutateur d’atténuation de la sonde P2220, vous devez changer en conséquence l’option Atténuation de l’oscilloscope. Les réglages du commutateur sont 1X et 10X. 8 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Démarrage Commutateur d’atténuation REMARQUE. Lorsque le commutateur d’atténuation est défini sur 1X, la sonde P2220 limite la bande passante de l’oscilloscope à 6 MHz. Pour utiliser toute la bande passante de l’oscilloscope, définissez le commutateur sur 10X. Mise à échelle de la sonde de courant Les sondes de courant fournissent un signal de tension proportionnel au courant. Vous devez régler l’oscilloscope en fonction de l’échelle de votre sonde de courant. L’échelle par défaut est 10 A/V. Par exemple, pour régler l’échelle d’une sonde de courant connectée à CH 1, appuyez sur CH 1 MENU ► Sonde ► Courant ► Echelle, puis sélectionnez une valeur appropriée. Calibrage automatique Le programme de calibrage automatique permet d’optimiser le chemin du signal de l’oscilloscope, afin d’obtenir une précision de mesure maximale. Vous pouvez exécuter ce programme à tout moment, mais il est conseillé de le faire si la température ambiante change de 5 °C (9 °F) ou plus. Ce programme prend environ deux minutes. Pour un calibrage précis, mettez l’oscilloscope sous tension et laissez-le chauffer pendant vingt minutes. Pour compenser le chemin du signal, déconnectez les sondes ou les câbles des connecteurs d’entrée. Ensuite, accédez à l’option UTILITAIRE ► Exécuter Auto-cal et suivez les instructions affichées à l’écran. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 9 Démarrage 10 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Principes de fonctionnement Le panneau avant se compose de plusieurs zones faciles à utiliser. Ce chapitre vous propose une présentation rapide des commandes et informations affichées à l’écran. Modèle à 2 voies Modèle à 4 voies Zone d’affichage Outre l’affichage des signaux, la zone d’affichage contient de nombreuses informations relatives aux réglages du signal et de l’oscilloscope. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 11 Principes de fonctionnement REMARQUE. Pour obtenir des détails sur l’affichage de la fonction FFT, voir (Voir page 71, Affichage du spectre FFT.). 1. L’apparence de l’icône indique le mode d’acquisition. Mode Normale Mode Détect Créte Mode Moyenne 12 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Principes de fonctionnement 2. L’état du déclenchement est indiqué par les icônes ci-dessous : L’oscilloscope est en train d’acquérir des données de pré-déclenchement. Dans cet état, tous les déclenchements sont ignorés. Toutes les données de pré-déclenchement ont été acquises et l’oscilloscope est prêt à accepter un déclenchement. L’oscilloscope a détecté un déclenchement et il est en train d’acquérir les données de post-déclenchement. L’oscilloscope a arrêté l’acquisition des données du signal. L’oscilloscope a terminé l’acquisition d’une séquence unique. L’oscilloscope est en mode automatique et il est en train d’acquérir des signaux en l’absence de déclenchement. L’oscilloscope est en train d’acquérir et d’afficher en continu les données du signal en mode Balayage. 3. Le marqueur indique la position horizontale de déclenchement. Tournez le bouton HORIZONTAL POSITION pour modifier la position du marqueur. 4. L’affichage indique le temps au réticule central. Le temps au déclenchement est zéro. 5. Le marqueur indique le niveau de déclenchement sur front ou sur largeur d’impulsion. 6. Les marqueurs à l’écran indiquent les points de référence de masse des signaux affichés. S’il n’existe aucun marqueur, la voie n’est pas affichée. 7. Une icône en forme de flèche indique que le signal est inversé. 8. Les facteurs d’échelle verticale des voies sont affichés. 9. Une icône BP indique que la bande passante de la voie est limitée. 10. Le réglage de la base de temps principale est affiché. 11. L’affichage indique le réglage de la base de temps de la fenêtre, si celle-ci est utilisée. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 13 Principes de fonctionnement 12. La source utilisée pour le déclenchement est affichée. 13. L’icône indique le type de déclenchement sélectionné comme suit : Déclenchement sur front pour le front montant. Déclenchement sur front pour le front descendant. Déclenchement vidéo pour l’option Synchro de ligne. Déclenchement vidéo pour l’option Synchro de trame. Déclenchement sur largeur d’impulsion, polarité positive. Déclenchement sur largeur d’impulsion, polarité négative. 14. L’affichage indique le niveau de déclenchement sur front ou sur largeur d’impulsion. 15. La zone d’affichage contient des messages utiles, dont certains s’affichent pendant 3 secondes seulement. Si vous rappelez un signal sauvegardé, des informations s’affichent à propos du signal de référence, telles que RefA 1,00 V 500 μs. 16. La date et l’heure sont affichées. 17. L’affichage indique la fréquence du déclenchement. 14 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Principes de fonctionnement Zone de messages L’oscilloscope affiche en bas de l’écran une zone de message (numéro 15 dans la figure précédente) qui propose les types d’informations suivants : Instructions d’accès à un autre menu, par exemple lorsque vous appuyez sur le bouton TRIG MENU. Pour le déclenchement HOLDOFF, aller dans le MENU HORIZONTAL Les étapes que vous pouvez effectuer par la suite, par exemple lorsque vous appuyez sur le bouton MESURES. Appuyez sur un bouton de l’écran pour modifier les mesures Des informations sur l’action effectuée par l’oscilloscope, par exemple lorsque vous appuyez sur le bouton CONF. PAR D. Rappel de la configuration d’usine standard Des informations sur le signal, par exemple lorsque vous appuyez sur le bouton AUTOSET. Onde carrée ou impulsion détectée sur CH1 Utilisation du système de menus L’interface utilisateur des oscilloscopes a été conçue pour faciliter l’accès aux fonctions spécialisées par le biais d’une structure de menus. Lorsque vous appuyez sur un bouton de menu du panneau avant, l’oscilloscope affiche le menu correspondant sur le côté droit de l’écran. Le menu affiche les options disponibles lorsque vous appuyez directement sur les boutons d’option dépourvus d’inscription situés à droite de l’écran. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 15 Principes de fonctionnement L’oscilloscope utilise plusieurs méthodes pour afficher les options de menu : Sélection de la page (sous-menu) : pour certains menus, vous pouvez utiliser le bouton d’option supérieur pour choisir entre deux ou trois sous-menus. Chaque fois que vous appuyez sur le bouton supérieur, les options changent. Par exemple, lorsque vous appuyez sur le bouton supérieur dans le menu TRIGGER, l’oscilloscope passe en revue les sous-menus de déclenchement Front, Vidéo et Largeur d’impulsion. Liste circulaire : l’oscilloscope attribue une valeur différente au paramètre à chaque fois que vous appuyez sur le bouton d’option. Par exemple, vous pouvez appuyer sur le bouton CH 1 MENU, puis sur le bouton d’option supérieur pour passer en revue les options Couplage vertical (voie). Dans certaines listes, vous pouvez utiliser le bouton multifonctionnel pour sélectionner une option. Une ligne de conseil vous indique quand vous pouvez utiliser le bouton multifonctionnel ; un voyant LED à côté de ce même bouton s’allume lorsque celui-ci est actif. (Voir page 20, Boutons de menu et de commande.) Action : l’oscilloscope affiche le type d’action qui se produira dès l’instant où vous appuyez sur un bouton d’option Action. Par exemple, lorsque l’index d’aide est visible et que vous appuyez sur le bouton d’option Page suivante, l’oscilloscope affiche immédiatement la page d’entrées d’index qui suit. Radio : l’oscilloscope utilise un bouton différent pour chaque option. L’option sélectionnée est mise en surbrillance. Par exemple, l’oscilloscope affiche plusieurs options de mode d’acquisition lorsque vous appuyez sur le bouton du menu ACQUISITION. Pour sélectionner une option, appuyez sur le bouton correspondant. 16 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Principes de fonctionnement Sélection de page Liste circulaire Action Radio TRIGGER CH1 AIDE ACQUISITION Type Front Couplage CC Page précédente Normale ou ou Page suivante Détect Créte TRIGGER CH1 Moyennage Type Vidéo Couplage CA ou ou TRIGGER CH1 Type Impulsion Couplage masse Réglages verticaux Tous les modèles (modèle illustré : 4 voies) POSITION (CH 1, CH 2, CH 3 & CH 4). Positionne un signal verticalement. CH 1, CH 2, CH 3 & CH 4 MENU. Permet d’afficher les sélections du menu vertical et d’activer/de désactiver l’affichage du signal de la voie. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 17 Principes de fonctionnement VOLTS/DIV (CH 1, CH 2, CH 3 & CH 4). Permet de sélectionner les facteurs d’échelles verticales. MATH MENU. Permet d’afficher le menu des opérations mathématiques du signal ; permet également d’activer ou de désactiver le signal calculé. Réglages horizontaux Modèle à 2 voies Modèle à 4 voies POSITION. Permet de régler la position horizontale de toutes les voies et de tous les signaux calculés. La résolution de ce réglage varie selon le réglage de la base de temps. (Voir page 114, Zone retardée.) REMARQUE. Pour appliquer un réglage étendu à la position horizontale, tournez la molette SEC/DIV pour définir une valeur supérieure, modifiez la position horizontale, puis tournez de nouveau la molette SEC/DIV pour revenir à la valeur précédente. HORIZ MENU. Permet d’afficher le menu Horizontal. REGLER SUR 0. Permet de régler la position horizontale sur zéro. SEC/DIV. Permet de sélectionner l’unité de temps/la division (facteur d’échelle) de la base de temps principale ou de la base de temps de la fenêtre. Lorsque la Zone retardée est activée, cette commande modifie 18 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Principes de fonctionnement la largeur de la zone retardée en modifiant la base de temps de la fenêtre. (Voir page 114, Zone retardée.) Commandes de déclenchement Modèle à 4 voies Modèle à 2 voies NIVEAU. Lorsque vous utilisez un déclenchement sur front ou sur impulsion, le bouton NIVEAU détermine le niveau d’amplitude que le signal doit traverser pour acquérir un signal. TRIG MENU. Permet d’afficher le menu Déclenchement. NIVEAU A 50%. Le niveau de déclenchement est défini sur le point médian entre les crêtes du signal de déclenchement. FORCE TRIG. Permet de terminer une acquisition quel que soit l’état du signal de déclenchement. Ce bouton est sans effet si l’acquisition est déjà interrompue. TRIG VIEW. Permet d’afficher le signal de déclenchement à la place du signal de voie lorsque vous maintenez le bouton TRIG VIEW enfoncé. Utilisez cette option pour voir comment les paramètres de déclenchement affectent un signal de déclenchement, tel qu’un couplage de déclenchement. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 19 Principes de fonctionnement Boutons de menu et de commande Bouton multifonctionnel Reportez-vous au chapitre Référence pour obtenir des informations détaillées sur les commandes des menus et boutons. Bouton multifonctionnel. La fonction est déterminée par le menu affiché ou l’option de menu sélectionnée. Lorsque la fonction est active, le voyant LED correspondant s’allume. Le tableau suivant énumère les fonctions. Option ou menu actif Fonction du bouton Description Curseurs Curseur 1 ou Curseur 2 Positionne le curseur sélectionné Affichage Contraste Modifie le contraste de l’écran Aide Défilement Sélectionne des entrées dans l’index ; sélectionne des liens dans une rubrique ; affiche la page suivante ou précédente d’une rubrique Horizontal Inhibition Permet de définir la durée avant acceptation d’un autre déclenchement ;(Voir page 135, Inhibition.) Math Position Positionne le signal calculé Echelle verticale Change l’échelle du signal calculé 20 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Principes de fonctionnement Option ou menu actif Fonction du bouton Description Mesures Type Sélectionne le type de mesures automatiques pour chaque source Action Affiche la transaction comme mise en mémoire ou rappel pour les fichiers de configuration, les fichiers de signal et les images d’écran Sauv./Rap Sélection de fichiers Sélectionne les fichiers de configuration, de signal ou image à enregistrer, ou sélectionne les fichiers de configuration ou de signal à rappeler Source Sélectionne la source lorsque l’option Type de déclenchement est réglée sur Front Numéro de ligne vidéo Permet de régler l’oscilloscope sur un numéro de ligne spécifique lorsque l’option Type de déclenchement est définie sur Vidéo et que l’option Synchro de déclenchement est définie sur Numéro de ligne Trigger (Déclenchement) Largeur d’impulsion Détermine la largeur de l’impulsion lorsque l’option Type de déclenchement est définie sur Impulsion Sélection de fichiers Sélectionne des fichiers à renommer ou supprimer ; (Voir page 139, Utilitaires Fichiers pour le lecteur flash USB.) Utilitaire ► Utilitaires Fichiers Saisie du nom Permet de renommer le fichier ou le dossier ; (Voir page 140, Renommer un fichier ou dossier.) Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 21 Principes de fonctionnement Option ou menu actif Fonction du bouton Description Utilitaire ► Options ► Configuration du bus GPIB ► Adresse Saisie de la valeur Définit l’adresse GPIB pour l’adaptateur TEK-USB-488 Utilitaire ► Options ► Régler date et heure Saisie de la valeur Définit la valeur de la date et de l’heure ; (Voir page 138, Réglage de la date et de l’heure.) Vertical ► Sonde ► Tension► Atténuation Saisie de la valeur Pour un menu de voie (comme CH 1 MENU), définit le facteur d’atténuation dans l’oscilloscope Vertical ► Sonde ► Courant ► Echelle Saisie de la valeur Pour un menu de voie (comme CH 1 MENU), définit l’échelle dans l’oscilloscope CALIBRAGE AUTO. Affiche le menu Calibrage Auto et active ou désactive la fonction correspondante. Lorsque la fonction est active, le voyant LED correspondant s’allume. SAUV./RAP. Permet d’afficher le menu Sauvegarde/Rappel des réglages et des signaux. MESURES. Permet d’afficher le menu des mesures automatiques. ACQUISITION. Permet d’afficher le menu Acquisition. MENU REF. Affiche le menu Référence pour afficher et cacher rapidement les signaux de référence stockés dans la mémoire non volatile de l’oscilloscope. UTILITAIRE. Permet d’afficher le menu Utilitaire. CURSEURS. Permet d’afficher le menu Curseurs. Les curseurs restent visibles (sauf si l’option Type est définie sur Désact.) une fois que vous avez quitté le menu Curseurs, mais ils ne sont plus réglables. AFFICHAGE. Permet d’afficher le menu Affichage. 22 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Principes de fonctionnement AIDE. Permet d’afficher le menu Aide. CONF. PAR D. Permet de rétablir la configuration d’usine. AUTOSET. Permet de régler automatiquement les commandes de l’oscilloscope afin d’obtenir un affichage exploitable des signaux d’entrées. SEQ. UNIQUE. Permet d’acquérir un signal unique, puis de s’arrêter. RUN/STOP. Permet d’acquérir des signaux en continu ou d’interrompre l’acquisition. PRINT. Lance l’opération d’impression sur une imprimante compatible PictBridge ou effectue la fonction ENREGISTRER sur le lecteur flash USB. ENREGISTRER. Un voyant LED s’allume lorsque la touche PRINT est configurée pour enregistrer des données sur le lecteur flash USB. Connecteurs d’entrée Modèle à 2 voies Modèle à 4 voies CH 1, CH 2, CH 3 & CH 4. Connecteurs d’entrée pour l’affichage des signaux. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 23 Principes de fonctionnement EXTERNE. Connecteur d’entrée pour une source de déclenchement externe. Le menu Déclenchement permet de sélectionner la source de déclenchement Ext. ou Ext/5. Maintenez le bouton TRIG VIEW enfoncé pour voir comment les paramètres de déclenchement affectent le signal de déclenchement, tel qu’un couplage de déclenchement. Autres éléments du panneau avant port du lecteur flash USB Port du lecteur flash USB. Insérez un lecteur flash USB pour le stockage ou la récupération de données. L’oscilloscope affiche un symbole en forme d’horloge pour indiquer quand le lecteur flash est actif. Après l’enregistrement ou la récupération d’un fichier, l’oscilloscope supprime l’horloge et affiche une ligne de conseil pour vous avertir que l’opération de sauvegarde ou de rappel est terminée. Pour les lecteurs flash dotés d’un voyant LED, celui-ci clignote lors de l’enregistrement de données sur le lecteur ou de la récupération de données depuis le lecteur. Attendez que le voyant LED ne clignote plus pour retirer le lecteur. COMP SONDE. Référence de châssis et de sortie de la compensation de sonde. Permet d’établir une correspondance électrique entre une sonde de tension et le circuit d’entrée de l’oscilloscope. (Voir page 5, Assistant Test de sonde de tension.) (Voir page 7, Compensation manuelle de sonde.) 24 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Compréhension des fonctions de l’oscilloscope Ce chapitre contient des informations générales que vous devez connaître avant d’utiliser un oscilloscope. Pour utiliser votre oscilloscope de manière efficace, vous devez vous familiariser avec les fonctions suivantes : Réglage de l’oscilloscope Déclenchement Acquisition de signaux Mise à l’échelle et positionnement de signaux Mesure de signaux La figure ci-dessous représente un diagramme fonctionnel des différentes fonctions de l’oscilloscope et de leurs relations. Réglage de l’oscilloscope Vous devez vous familiariser avec plusieurs fonctions que vous allez utiliser souvent lors du fonctionnement de l’oscilloscope : le réglage automatique (Autoset), le calibrage automatique (Calibrage Auto), la sauvegarde d’un réglage et le rappel d’un réglage. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 25 Compréhension des fonctions de l’oscilloscope Utilisation de la fonction de réglage automatique (Autoset) Chaque fois que vous appuyez sur le bouton AUTOSET, la fonction de réglage automatique (Autoset) vous donne un affichage de signal stable. Elle permet d’ajuster automatiquement les réglages de l’échelle verticale et horizontale et du déclenchement. Le réglage automatique permet également d’afficher plusieurs mesures automatiques dans la zone du réticule, en fonction du type de signal. Utilisation de la fonction de calibrage automatique (Autorange) Le calibrage automatique est une fonction continue que vous pouvez activer ou désactiver. Cette fonction ajuste la configuration de manière à suivre un signal lorsque celui-ci présente de grandes variations ou lorsque vous déplacez physiquement la sonde. Sauvegarde d’un réglage Le réglage courant est sauvegardé si vous patientez cinq secondes après la dernière modification avant d’éteindre l’oscilloscope. A la prochaine mise sous tension, l’oscilloscope rappelle ce réglage. Le menu SAUV./RAP vous permet d’enregistrer jusqu’à dix réglages différents. Vous pouvez également enregistrer des réglages sur un lecteur flash USB. L’oscilloscope peut recevoir un lecteur flash USB pour le stockage et la récupération de données amovibles. (Voir page 79, Port du lecteur flash USB.) Rappel d’une configuration L’oscilloscope peut rappeler le dernier réglage utilisé avant sa mise hors tension, l’un des réglages que vous avez enregistrés ou le réglage par défaut. (Voir page 120, Sauvegarder/Rappeler.) Configuration par défaut Dans sa configuration définie en usine, l’oscilloscope est réglé en mode de fonctionnement normal. Il s’agit de la configuration par défaut. Pour rappeler cette configuration, appuyez sur le bouton CONF. PAR D. Pour afficher les réglages par défaut, reportez-vous à l’Annexe D : Configuration par défaut. 26 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Compréhension des fonctions de l’oscilloscope Déclenchement Le déclenchement permet de déterminer le moment où l’oscilloscope commence à acquérir des données et à afficher un signal. Lorsque le déclenchement est configuré correctement, l’oscilloscope convertit un signal instable ou des écrans vides en signaux significatifs. Signal déclenché Signaux sans déclenchement Pour obtenir des informations spécifiques sur l’oscilloscope, reportez-vous au chapitre Principes de fonctionnement. (Voir page 19, Commandes de déclenchement.) Reportez-vous également au chapitre Référence. (Voir page 127, Commandes de déclenchement.) Lorsque vous appuyez sur le bouton RUN/STOP ou SEQ. UNIQUE pour démarrer une acquisition, l’oscilloscope effectue les étapes suivantes : 1. Il acquiert suffisamment de données pour remplir la portion de l’enregistrement du signal située sur la gauche du point de déclenchement. Cette opération est appelée pré-déclenchement. 2. Il continue à acquérir des données en attendant le déclenchement. 3. Il détecte le déclenchement. 4. Il continue à acquérir des données jusqu’à ce que l’enregistrement du signal soit complet. 5. Il affiche le signal qui vient d’être acquis. REMARQUE. Pour les déclenchements sur front et sur impulsion, l’oscilloscope évalue la cadence à laquelle se produisent les déclenchements afin de déterminer la fréquence du déclenchement. L’oscilloscope affiche la fréquence dans le coin inférieur droit de l’écran. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 27 Compréhension des fonctions de l’oscilloscope Source Les options de source de déclenchement vous permettent de sélectionner le signal qui sera utilisé par l’oscilloscope comme déclenchement. La source peut être n’importe quel signal connecté à la ligne d’alimentation secteur (disponible uniquement avec les déclenchements sur front), à une voie BNC ou au connecteur BNC EXTERNE. Types L’oscilloscope dispose de trois types de déclenchements : sur front, vidéo et sur largeur d’impulsion. Modes Vous pouvez sélectionner le mode de déclenchement Auto ou Normal pour définir le mode d’acquisition des données par l’oscilloscope lorsque celui-ci ne détecte pas de condition de déclenchement. (Voir page 128, Options des modes.) Pour effectuer une acquisition de type séquence unique, appuyez sur le bouton SEQ. UNIQUE. Couplage Vous pouvez utiliser l’option Couplage déclenchement pour déterminer la partie du signal qui passera dans le circuit de déclenchement. Cela peut vous permettre d’obtenir un affichage du signal stable. Pour utiliser le couplage de déclenchement, appuyez sur le bouton TRIG MENU, sélectionnez un déclenchement sur front ou sur impulsion et sélectionnez une option de couplage. REMARQUE. Le couplage de déclenchement n’affecte que le signal transmis au système de déclenchement. Il n’affecte ni la bande passante, ni le couplage du signal affiché à l’écran. Pour afficher le signal conditionné transmis au circuit de déclenchement, maintenez le bouton TRIG VIEW enfoncé. Position Le réglage de la commande de position horizontale permet de représenter le temps qui s’est écoulé entre le déclenchement et le centre de l’écran. Reportez-vous aux Informations sur l’échelle horizontale 28 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Compréhension des fonctions de l’oscilloscope et la position horizontale et sur le pré-déclenchement pour des informations sur la façon d’utiliser cette commande afin de positionner le déclencheur. (Voir page 31, Informations sur l’échelle horizontale et la position horizontale et sur le pré-déclenchement.) Pente et Niveau Les commandes Pente et Niveau vous permettent de définir le mode de déclenchement. L’option Pente (type de déclenchement sur front uniquement) vous permet de déterminer si l’oscilloscope trouve le point de déclenchement sur le front montant ou descendant du signal. La molette TRIGGER NIVEAU permet de spécifier le point de déclenchement sur le front. Front montant Front descendant Le niveau de déclenchement peut être ajusté verticalement Le déclenchement peut être montant ou descendant Acquisition de signaux Lorsque vous faites l’acquisition d’un signal, l’oscilloscope le convertit au format numérique et affiche sa courbe. Le mode d’acquisition définit la façon dont le signal est numérisé et le réglage de la base de temps affecte la durée temporelle et le niveau de détail de l’acquisition. Modes d’acquisition Il existe trois modes d’acquisition : Normale, Détect Créte et Moyenne. Normale. Dans ce mode d’acquisition, l’oscilloscope échantillonne le signal à intervalles réguliers afin de pouvoir en donner une représentation. Ce mode permet en général de représenter avec précision les signaux. Cependant, ce mode n’acquiert pas les variations rapides qui peuvent se produire dans le signal entre les différents prélèvements d’échantillons. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 29 Compréhension des fonctions de l’oscilloscope Cela risque de provoquer un repliement du spectre ; certaines impulsions étroites risquent d’être oubliées. Si c’est le cas, vous devriez utiliser le mode Détect Créte pour acquérir les données. (Voir page 32, Repliement du spectre temporel.) Détect Créte. Dans ce mode d’acquisition, l’oscilloscope recherche les valeurs les plus élevées et les plus faibles du signal d’entrée sur chaque intervalle d’échantillonnage et les utilise pour afficher la courbe du signal. L’appareil peut ainsi acquérir et afficher les impulsions étroites, qui risqueraient d’être oubliées en mode Normale. Le bruit sera plus élevé dans ce mode. Moyenne. Dans ce mode d’acquisition, l’oscilloscope acquiert plusieurs signaux, il en fait la moyenne et affiche la courbe du signal qui en résulte. Vous pouvez utiliser ce mode pour réduire le bruit aléatoire. Base de temps L’oscilloscope numérise les signaux en faisant l’acquisition de la valeur d’un signal d’entrée à des intervalles discrets. La base de temps vous permet de contrôler la fréquence à laquelle les valeurs sont numérisées. Pour ajuster la base de temps sur une échelle horizontale correspondant à vos besoins, utilisez la molette SEC/DIV. Mise à l’échelle et positionnement de signaux Vous pouvez modifier l’affichage des signaux en ajustant l’échelle et la position. Si vous modifiez l’échelle, la taille de l’affichage du signal va augmenter ou diminuer. Si vous modifiez la position, le signal sera déplacé vers le haut, le bas, la droite ou la gauche. L’indicateur de voie (situé à gauche du réticule) permet d’identifier chacun des signaux affichés. L’indicateur pointe vers le niveau de référence de terre de l’enregistrement du signal. Vous pouvez voir la zone d’affichage et les mesures. (Voir page 11, Zone d’affichage.) Echelle et position verticales Vous pouvez modifier la position verticale des signaux en les déplaçant vers le haut ou le bas de l’affichage. Pour comparer des données, vous 30 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Compréhension des fonctions de l’oscilloscope pouvez aligner un signal sur un autre ou aligner des signaux les uns sur les autres. Vous pouvez modifier l’échelle verticale d’un signal. L’affichage du signal se réduit ou augmente par rapport au niveau de référence de terre. Pour obtenir des informations spécifiques sur l’oscilloscope, reportez-vous au chapitre Principes de fonctionnement. (Voir page 17, Réglages verticaux.) Reportez-vous également au chapitre Référence. (Voir page 140, Réglages verticaux.) Informations sur l’échelle horizontale et la position horizontale et sur le pré-déclenchement Vous pouvez régler la commande HORIZONTAL POSITION pour afficher les données du signal avant le déclenchement, après le déclenchement, ou les deux. Lorsque vous modifiez la position horizontale d’un signal, vous modifiez le temps qui s’écoule entre le déclenchement et le centre de l’écran (cela revient à déplacer le signal vers la droite ou la gauche de l’affichage). Par exemple, si vous souhaitez rechercher la cause d’un parasite dans votre circuit de test, vous pouvez effectuer un déclenchement sur le parasite et allonger la période de pré-déclenchement de façon à capturer les données avant le parasite. Vous pouvez alors analyser les données de pré-déclenchement et peut-être trouver la cause du parasite. Vous pouvez modifier l’échelle horizontale de tous les signaux en actionnant la molette SEC/DIV. Par exemple, vous pouvez avoir besoin de visualiser une seule période de courbe de signal pour mesurer la sur-oscillation sur le front montant. L’oscilloscope affiche l’échelle horizontale en temps par division sur le facteur d’échelle. Comme tous les signaux actifs utilisent la même base de temps, l’oscilloscope affiche uniquement une valeur pour toutes les voies actives, sauf lorsque vous utilisez la Zone retardée. Reportez-vous à la section Zone retardée pour obtenir des informations sur l’utilisation de la fonction fenêtre. (Voir page 114, Zone retardée.) Pour obtenir des informations spécifiques sur l’oscilloscope, reportez-vous au chapitre Principes de fonctionnement. (Voir page 18, POSITION.) Reportez-vous également au chapitre Référence.(Voir page 112, Horizontal.) Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 31 Compréhension des fonctions de l’oscilloscope Repliement du spectre temporel. Un repliement du spectre se produit lorsque l’oscilloscope n’échantillonne pas le signal assez rapidement pour en constituer un enregistrement exact. Lorsque cela se produit, l’oscilloscope affiche un signal dont la fréquence est plus basse que celle du signal d’entrée, ou bien déclenche et affiche un signal instable. Signal de fréquence réelle élevée Signal de fréquence apparente basse en raison du repliement du spectre Points d’échantillonnage L’oscilloscope représente les signaux de façon précise, mais il est limité par la bande passante de la sonde, celle de l’oscilloscope et la fréquence d’échantillonnage. Pour éviter le repliement du spectre, l’oscilloscope doit échantillonner le signal au moins deux fois plus vite que la composante de fréquence la plus élevée de ce signal. La fréquence la plus élevée pouvant être représentée par la fréquence d’échantillonnage de l’oscilloscope est appelée fréquence de Nyquist. La fréquence d’échantillonnage est appelée cadence de Nyquist et elle est égale à deux fois la fréquence de Nyquist. Les fréquences d’échantillonnage maximum de l’oscilloscope sont au moins dix fois supérieures à la bande passante. Ces fréquences d’échantillonnage élevées aident à réduire le risque de repliement du spectre. 32 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Compréhension des fonctions de l’oscilloscope Il existe plusieurs façons de contrôler le repliement du spectre : Tournez la molette SEC/DIV pour modifier l’échelle horizontale. Si la forme du signal change de manière significative, cela signifie que vous observez peut-être un repliement du spectre. Sélectionnez le mode d’acquisition Détect Créte. (Voir page 30, Détect Créte.) Ce mode échantillonne les valeurs les plus élevées et les plus faibles afin que l’oscilloscope puisse détecter les signaux les plus rapides. Si la forme du signal change de manière significative, cela signifie que vous observez peut-être un repliement du spectre. Si la fréquence du déclenchement est plus rapide que les informations affichées à l’écran, cela signifie que vous observez peut-être un repliement du spectre ou un signal qui traverse plusieurs fois le niveau de déclenchement. L’examen du signal permet de déterminer si la forme du signal autorise un déclenchement unique par cycle au niveau du déclenchement sélectionné. Si plusieurs déclenchements se produisent, sélectionnez un niveau de déclenchement ne générant qu’un seul déclenchement par cycle. Si la fréquence du déclenchement demeure plus rapide que l’affichage à l’écran, cela signifie que vous observez peut-être un repliement du spectre. Si la fréquence du déclenchement est plus lente, cela signifie que ce test est inutile. Si le signal que vous visualisez est également la source du déclenchement, utilisez le réticule ou les curseurs pour estimer la fréquence du signal affiché. Comparez ce résultat avec la mesure de la fréquence du déclenchement située dans le coin inférieur droit de l’écran. Si ces deux résultats sont très différents, cela signifie que vous observez peut-être un repliement du spectre. Le tableau suivant dresse la liste des bases de temps que vous pouvez utiliser pour éviter le repliement du spectre sur différentes fréquences, ainsi que les fréquences d’échantillonnage correspondantes. Si le bouton SEC/DIV est réglé sur la position la plus élevée, il ne devrait pas y avoir de repliement du spectre grâce aux limites de bande passante des amplificateurs d’entrée de l’oscilloscope. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 33 Compréhension des fonctions de l’oscilloscope Réglages permettant d’éviter le repliement du spectre en mode Echantillon Base de temps Echantillons par seconde Maximum 2,5 ns 2 G éch./s 200 MHz † de 5 à 250 ns 1 G éch./s ou 2 G éch./s * 200 MHz † 500 ns 500 M éch./s 200 MHz † 1 ms 250 M éch./s 125 MHz † 2,5 ms 100 M éch./s 50 MHz † 5 ms 50 M éch./s 25 MHz † 10 ms 25 M éch./s 12,5 MHz † 25 ms 10 M éch./s 5 MHz 50 ms 5 M éch./s 2,5 MHz 100 ms 2,5 M éch./s 1,25 MHz 250 ms 1 M éch./s 500 kHz 500 ms 500 k éch./s 250 kHz 1 ms 250 k éch./s 125 kHz 2,5 ms 100 k éch./s 50 kHz 5 ms 50 k éch./s 25 kHz 10 ms 25 k éch./s 12,5 kHz 25 ms 10 k éch./s 5 kHz 50 ms 5 k éch./s 2,5 kHz 100 ms 2,5 k éch./s 1,25 kHz 250 ms 1 k éch./s 500 Hz 500 ms 500 éch./s 250 Hz 1 s 250 éch/s 125 Hz 2,5 s 100 éch./s 50 Hz 5 s 50 éch./s 25 Hz 10 s 25 éch./s 12,5 Hz 25 s 10 éch./s 5 Hz 50 s 5 éch./s 2,5 Hz * En fonction du modèle d’oscilloscope. † Bande passante réduite à 6 MHz avec une sonde P2220 réglée sur 1X. 34 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Compréhension des fonctions de l’oscilloscope Prise de mesures L’oscilloscope trace des graphes de la tension par rapport au temps et vous aide à mesurer le signal affiché. Il existe plusieurs façons de prendre des mesures. Vous pouvez utiliser le réticule, les curseurs ou une mesure automatique. Réticule Cette méthode vous permet d’effectuer une estimation visuelle rapide. Vous pouvez par exemple examiner l’amplitude d’un signal et constater qu’elle est légèrement supérieure à 100 mV. Vous pouvez effectuer des mesures simples en comptant les divisions de réticule majeures et mineures concernées et en les multipliant par le facteur d’échelle. Ainsi, si vous comptez cinq divisions de réticule verticales majeures entre les valeurs minimale et maximale d’un signal et si le facteur d’échelle est 100 mV/division, vous pouvez alors calculer la tension crête à crête comme suit : 5 divisions x 100 mV/division = 500 mV Curseur Curseurs Cette méthode vous permet de prendre des mesures en déplaçant les curseurs, qui s’affichent toujours par paires, et en lisant les valeurs numériques correspondantes qui s’affichent à l’écran. Il existe deux types de curseurs : Amplitude et Temps. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 35 Compréhension des fonctions de l’oscilloscope Lorsque vous utilisez les curseurs, assurez-vous de définir la source en fonction du signal affiché à l’écran que vous souhaitez mesurer. Pour utiliser les curseurs, appuyez sur le bouton CURSEURS. Curseurs d’amplitude. Les curseurs d’amplitude s’affichent sous forme de lignes horizontales à l’écran et permettent de mesurer les paramètres verticaux. Les amplitudes sont référencées au niveau de référence. Pour la fonction Math FFT, ces curseurs mesurent l’amplitude. Curseurs de temps. Les curseurs de temps s’affichent sous la forme de lignes verticales à l’écran et permettent de mesurer les paramètres horizontaux et verticaux. Les temps sont référencés au point de déclenchement. Pour la fonction Math FFT, ces curseurs mesurent la fréquence. Les curseurs de temps comprennent également un affichage de l’amplitude du signal au point où celui-ci croise le curseur. Automatique Le menu MESURES peut traiter jusqu’à cinq mesures automatiques. Si vous prenez des mesures automatiques, l’oscilloscope effectue tous les calculs à votre place. Ces mesures utilisent les points qui composent l’enregistrement du signal. Elles sont donc plus précises que les mesures du réticule ou du curseur. Le résultat des mesures automatiques est affiché à l’écran. Ces mesures sont mises à jour périodiquement lorsque l’oscilloscope reçoit de nouvelles données. Pour obtenir des informations sur les mesures, reportez-vous au chapitre Référence. (Voir page 117, Prise de mesures.) 36 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Cette section présente une série d’exemples d’application. Ces exemples simplifiés mettent en évidence les fonctions de l’oscilloscope et vous expliquent comment l’utiliser pour résoudre les problèmes rencontrés lors des tests effectués. Prise de mesures simples Utilisation de la fonction de réglage automatique (Autoset) Utilisation du menu Mesures pour effectuer des mesures automatiques Mesure de deux signaux et calcul du gain Utilisation de la fonction de calibrage automatique (Autorange) pour examiner une série de points de test Prise de mesures par curseur Mesure de la fréquence et de l’amplitude d’anneau Mesure de la largeur d’impulsion Mesure du temps de montée Analyse du détail du signal Examen d’un signal bruyant Utilisation de la fonction de moyenne pour séparer un signal du bruit Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 37 Exemples d’application Acquisition d’un signal monocoup Optimisation de l’acquisition Mesure du retard de propagation Déclenchement sur une largeur d’impulsion Déclenchement sur un signal vidéo Déclenchement sur les trames et les lignes vidéo Utilisation de la fonction fenêtre pour visualiser les détails du signal Analyse d’un signal de communication différentiel avec les fonctions mathématiques Affichage des changements d’impédance dans un réseau en utilisant le mode XY et la persistance Prise de mesures simples Vous devez observer un signal dans un circuit, mais vous ne connaissez ni l’amplitude ni la fréquence de ce signal. Vous souhaitez afficher rapidement le signal et mesurer la fréquence, la période et l’amplitude crête à crête. 38 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Utilisation de la fonction de réglage automatique (Autoset) Pour afficher rapidement un signal, procédez comme suit : 1. Appuyez sur le bouton CH 1 MENU. 2. Appuyez sur Sonde ► Tension ►Atténuation ► 10X. 3. Réglez le commutateur de la sonde P2220 sur 10X. 4. Connectez l’extrémité de la sonde de voie 1 au signal. Raccordez le câble de référence au point de référence du circuit. 5. Appuyez sur le bouton AUTOSET. L’oscilloscope définit automatiquement les réglages verticaux, horizontaux et de déclenchement. Si vous souhaitez optimiser l’affichage du signal, vous pouvez ajuster manuellement ces commandes. REMARQUE. L’oscilloscope affiche les mesures automatiques adéquates dans la zone du signal de l’écran en fonction du type de signal détecté. Pour obtenir des informations spécifiques sur l’oscilloscope, reportez-vous au chapitre Référence. (Voir page 103, Réglage automatique (Autoset).) Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 39 Exemples d’application Mesures automatiques L’oscilloscope peut mesurer automatiquement la plupart des signaux affichés. REMARQUE. Si un point d’interrogation (?) apparaît dans la zone d’affichage Valeur, le signal est en dehors du champ de mesure. Réglez la molette VOLTS/DIV de façon à réduire la sensibilité de la voie appropriée ou changez le réglage de SEC/DIV. Pour mesurer la fréquence du signal, la période, l’amplitude crête à crête, le temps de montée et la largeur positive, procédez comme suit : 1. Appuyez sur le bouton MESURES pour afficher le menu correspondant. 2. Appuyez sur le bouton d’option supérieur ; le menu Mesure 1 s’affiche. 3. Appuyez sur Type ► Fréq. La zone d’affichage Valeur affiche la mesure et les mises à jour. 4. Appuyez sur le bouton d’option Retour. 5. Appuyez sur le deuxième bouton d’option en partant du haut ; le menu Mesure 2 s’affiche. 6. Appuyez sur Type ► Période. La zone d’affichage Valeur affiche la mesure et les mises à jour. 7. Appuyez sur le bouton d’option Retour. 8. Appuyez sur le bouton d’option du milieu ; le menu Mesure 3 s’affiche. 40 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application 9. Appuyez sur Type ► C-C. La zone d’affichage Valeur affiche la mesure et les mises à jour. 10. Appuyez sur le bouton d’option Retour. 11. Appuyez sur le deuxième bouton d’option en partant du bas ; le menu Mesure 4 s’affiche. 12. Appuyez sur Type ► Tps montée. La zone d’affichage Valeur affiche la mesure et les mises à jour. 13. Appuyez sur le bouton d’option Retour. 14. Appuyez sur le bouton d’option inférieur ; le menu Mesure 5 s’affiche. 15. Appuyez sur Type ► Largeur pos. La zone d’affichage Valeur affiche la mesure et les mises à jour. 16. Appuyez sur le bouton d’option Retour. CH1 Fréq. 1 000 kHz CH1 Période 1 000 ms CH1 C-C 5,04 V CH1 Tps montée 2 611 μs ? CH1 Largeur pos. 500 μs Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 41 Exemples d’application Mesure de deux signaux Si vous testez un équipement et devez mesurer le gain de l’amplificateur audio, vous aurez besoin d’un générateur audio capable d’injecter un signal de test à l’entrée de l’amplificateur. Connectez deux voies de l’oscilloscope à l’entrée et à la sortie de l’amplificateur (voir schéma). Mesurez les niveaux des deux signaux et utilisez les mesures pour calculer le gain. CH1 C-C 2,04 V CH2 C-C 206 mV CH1 Aucune CH1 Aucune CH1 Aucune 42 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Pour activer et afficher les signaux connectés aux voies 1 et 2 et sélectionner des mesures pour les deux voies, procédez comme suit : 1. Appuyez sur le bouton AUTOSET. 2. Appuyez sur le bouton MESURES pour afficher le menu correspondant. 3. Appuyez sur le bouton d’option supérieur ; le menu Mesure 1 s’affiche. 4. Appuyez sur Source ► CH1. 5. Appuyez sur Type ► C-C. 6. Appuyez sur le bouton d’option Retour. 7. Appuyez sur le deuxième bouton d’option en partant du haut ; le menu Mesure 2 s’affiche. 8. Appuyez sur Source ► CH2. 9. Appuyez sur Type ► C-C. 10. Appuyez sur le bouton d’option Retour. Lisez les amplitudes crête à crête affichées pour les deux voies. 11. Pour calculer le gain de tension de l’amplificateur, utilisez ces équations : Gain de tension = amplitude de sortie/amplitude d’entrée Gain de tension (dB) = 20 × log (Gain de tension) Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 43 Exemples d’application Utilisation de la fonction de calibrage automatique (Autorange) pour examiner une série de points de test Si votre machine fonctionne mal, vous devrez peut-être trouver la fréquence et la tension efficace de plusieurs points de test et comparer ces valeurs à des valeurs idéales. Vous ne pouvez pas accéder aux commandes du panneau avant car vous avez besoin de vos deux mains pour sonder des points de test difficiles à atteindre physiquement. 1. Appuyez sur le bouton CH 1 MENU. 2. Appuyez sur Sonde ► Tension ► Atténuation et effectuez votre réglage pour que l’atténuation corresponde à celle de la sonde connectée à la voie 1. 3. Appuyez sur le bouton CALIBRAGE AUTO pour activer l’ajustement automatique et sélectionnez l’option Vertical et Horizontal. 4. Appuyez sur le bouton MESURES pour afficher le menu correspondant. 5. Appuyez sur le bouton d’option supérieur ; le menu Mesure 1 s’affiche. 6. Appuyez sur Source ► CH1. 7. Appuyez sur Type ► Fréquence. 8. Appuyez sur le bouton d’option Retour. 9. Appuyez sur le deuxième bouton d’option en partant du haut ; le menu Mesure 2 s’affiche. 10. Appuyez sur Source ► CH1. 11. Appuyez sur Type ► Efficace. 12. Appuyez sur le bouton d’option Retour. 13. Connectez l’extrémité de la sonde et le câble de référence au premier point de test. Lisez la fréquence et la valeur efficace du cycle sur l’écran de l’oscilloscope, puis comparez ces valeurs aux valeurs idéales. 14. Répétez l’étape 13 pour chaque point de test, jusqu’à ce que vous trouviez le composant défaillant. 44 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application REMARQUE. Lorsque la fonction de calibrage automatique (Autorange) est active, chaque fois que vous déplacez la sonde vers un autre point de test, l’oscilloscope réajuste l’échelle horizontale, l’échelle verticale et le niveau de déclenchement pour vous donner un affichage utile. Mesures par curseur Vous pouvez utiliser les curseurs pour prendre rapidement des mesures d’amplitude et de temps sur un affichage. Mesure de l’amplitude et de la fréquence d’anneau Pour mesurer la fréquence d’anneau au front montant d’un signal, procédez comme suit : 1. Appuyez sur le bouton CURSEURS pour afficher le menu correspondant. 2. Appuyez sur Type ► Temps. 3. Appuyez sur Source ► CH1. 4. Appuyez sur le bouton d’option Curseur 1. 5. Tournez le bouton multifonctionnel pour placer un curseur sur la première crête de l’anneau. 6. Appuyez sur le bouton d’option Curseur 2. 7. Tournez le bouton multifonctionnel pour placer un curseur sur la seconde crête de l’anneau. Vous pouvez visualiser le temps Δ (delta) et la fréquence (fréquence d’anneau mesurée) dans le menu Curseurs. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 45 Exemples d’application Type Temps Source CH1 Δt 540 ns 1/Δt 1 852 MHz ΔV 0,44 V Curseur 1 180 ns 1,40 V Curseur 2 720 ns 0,96 V 8. Appuyez sur Type ► Amplitude. 9. Appuyez sur le bouton d’option Curseur 1. 10. Tournez le bouton multifonctionnel pour placer un curseur sur la première crête de l’anneau. 11. Appuyez sur le bouton d’option Curseur 2. 12. Tournez le bouton multifonctionnel pour placer le Curseur 2 sur le point le plus bas de l’anneau. Vous pouvez voir l’amplitude de l’anneau dans le menu Curseurs. Type Amplitude Source CH1 ΔV 640 mV Curseur 1 1,46 V Curseur 2 820 mV 46 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Mesure de la largeur d’impulsion Si vous analysez un affichage d’impulsion et que vous souhaitez connaître la largeur de l’impulsion, procédez comme suit : 1. Appuyez sur le bouton CURSEURS pour afficher le menu correspondant. 2. Appuyez sur Type ► Temps. 3. Appuyez sur Source ► CH1. 4. Appuyez sur le bouton d’option Curseur 1. 5. Tournez le bouton multifonctionnel pour placer un curseur sur le front montant de l’impulsion. 6. Appuyez sur le bouton d’option Curseur 2. 7. Tournez le bouton multifonctionnel pour placer un curseur sur le front descendant de l’impulsion. Vous pouvez accéder aux mesures suivantes dans le menu Curseurs : Le temps au Curseur 1, par rapport au déclenchement. Le temps au Curseur 2, par rapport au déclenchement. Le temps Δ (delta), à savoir la mesure de la largeur d’impulsion. Type Temps Source CH1 Δt 500 μs 1/Δt 2 000 kHz ΔV 1,38 V Curseur 1 0 s 0,98 V Curseur 2 500 μs -1 V Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 47 Exemples d’application REMARQUE. La mesure de largeur positive est exprimée sous forme de mesure automatique dans le menu Mesures. (Voir page 117, Prise de mesures.) REMARQUE. La mesure de largeur positive s’affiche également lorsque vous sélectionnez l’option Carré à simple cycle dans le menu AUTOSET. (Voir page 106, Onde ou impulsion carrée.) 48 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Mesure du temps de montée Après avoir mesuré la largeur d’impulsion, vous décidez de vérifier le temps de montée de l’impulsion. Généralement, vous mesurez le temps de montée entre les niveaux égaux à 10 % et 90 % du signal. Pour mesurer le temps de montée, procédez comme suit : 1. Tournez la molette SEC/DIV pour afficher le front montant du signal. 2. Tournez les molettes VOLTS/DIV et VERTICAL POSITION pour régler l’amplitude du signal sur cinq divisions environ. 3. Appuyez sur le bouton CH 1 MENU. 4. Appuyez sur Volts/div ► Fin. 5. Tournez la molette VOLTS/DIV pour régler l’amplitude du signal sur cinq divisions exactement. 6. Tournez la molette VERTICAL POSITION pour centrer le signal ; positionnez la ligne de base du signal à 2,5 divisions sous le réticule central. 7. Appuyez sur le bouton CURSEURS pour afficher le menu correspondant. 8. Appuyez sur Type ► Temps. 9. Appuyez sur Source ► CH1. 10. Appuyez sur le bouton d’option Curseur 1. 11. Tournez le bouton multifonctionnel pour placer un curseur sur le point de croisement du signal et de la deuxième ligne du réticule située sous le centre de l’écran. Il s’agit du niveau égal à 10 % du signal. 12. Appuyez sur le bouton d’option Curseur 2. 13. Tournez le bouton multifonctionnel pour placer un curseur sur le point de croisement du signal et de la deuxième ligne du réticule située au-dessus du centre de l’écran. Il s’agit du niveau égal à 90 % du signal. L’affichage Δt apparaissant dans le menu Curseurs est le temps de montée du signal. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 49 Exemples d’application 5 divisions Type Temps Source CH1 Δt 140 ns 1/Δt 7 143 MHz ΔV 2,08 V Curseur 1 -80 ns -1,02 V Curseur 2 60 ns 1,06 V REMARQUE. La mesure du temps de montée est exprimée sous forme de mesure automatique dans le menu Mesures. (Voir page 117, Prise de mesures.) REMARQUE. La mesure du temps de montée s’affiche également lorsque vous sélectionnez l’option Front montant dans le menu AUTOSET. (Voir page 106, Onde ou impulsion carrée.) Analyse détaillée du signal Un signal bruyant est affiché sur l’oscilloscope et vous avez besoin d’en connaître le détail. Vous suspectez que le signal contient bien plus de détails que ce qui est affiché. 50 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Examen d’un signal bruyant Le signal paraît bruyant et vous suspectez que ce bruit est à l’origine de problèmes dans votre circuit. Pour mieux analyser le bruit, procédez comme suit : 1. Appuyez sur le bouton ACQUISITION pour afficher le menu correspondant. 2. Appuyez sur le bouton d’option Détect Créte. 3. Si besoin, appuyez sur le bouton AFFICHAGE pour afficher le menu correspondant. Utilisez le bouton d’option Contraste avec le bouton multifonctionnel pour régler l’affichage et voir plus facilement le bruit. La Détect Créte détermine les pointes de bruit et les parasites dans votre signal, notamment lorsque la base de temps est réglée sur un réglage lent. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 51 Exemples d’application Séparation du signal et du bruit Vous souhaitez à présent analyser la forme du signal et ignorer le bruit. Pour réduire le bruit aléatoire dans l’affichage de l’oscilloscope, procédez comme suit : 1. Appuyez sur le bouton ACQUISITION pour afficher le menu correspondant. 2. Appuyez sur le bouton d’option Moyenne. 3. Appuyez sur le bouton d’option Moyennes pour afficher les effets résultant de la variation du nombre de moyennes en cours sur l’affichage du signal. La fonction Moyennes réduit le bruit aléatoire et facilite la visualisation du détail d’un signal. Dans l’exemple ci-dessous, un anneau apparaît sur le front montant et sur le front descendant du signal lorsque le bruit est éliminé. 52 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Acquisition d’un signal monocoup La fiabilité d’un relais à lames souples dans un composant d’équipement laisse à désirer et vous devez rechercher l’origine du problème. Vous suspectez que les contacts du relais produisent un arc lorsque le relais est hors circuit. Comme vous pouvez ouvrir et fermer le relais à la vitesse maximale d’une fois par minute environ, il vous faut capter la tension sur le relais en acquisition monocoup. Pour établir une acquisition monocoup, procédez comme suit : 1. Tournez la molette verticale VOLTS/DIV et la molette horizontale SEC/DIV selon les plages appropriées correspondant au signal que vous souhaitez observer. 2. Appuyez sur le bouton ACQUISITION pour afficher le menu correspondant. 3. Appuyez sur le bouton d’option Détect Créte. 4. Appuyez sur le bouton TRIG MENU pour afficher le menu Déclenchement. 5. Appuyez sur Pente ► Montante. 6. Tournez la molette NIVEAU pour régler le niveau de déclenchement sur la médiane d’une tension entre les tensions ouvertes et fermées du relais. 7. Appuyez sur le bouton SEQ. UNIQUE pour lancer l’acquisition. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 53 Exemples d’application Lorsque le relais s’ouvre, l’oscilloscope se déclenche et capture l’événement. Optimisation de l’acquisition L’acquisition initiale montre que le contact du relais commence à s’ouvrir au point de déclenchement. Cet événement est suivi d’une grande pointe d’impulsion indiquant un rebondissement du contact et une inductance dans le circuit. L’inductance risque de provoquer la formation d’un arc dans le contact et une défaillance prématurée du relais. Vous pouvez utiliser les réglages verticaux, horizontaux et de déclenchement pour optimiser les réglages avant la capture du prochain événement monocoup. Lorsque l’acquisition suivante est capturée avec les nouveaux réglages (après avoir appuyé de nouveau sur le bouton SEQ. UNIQUE), vous pouvez constater que le contact rebondit plusieurs fois lorsqu’il s’ouvre. 54 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Mesure du retard de propagation Vous suspectez que la synchronisation de mémoire du circuit d’un microprocesseur est marginale. Configurez l’oscilloscope pour mesurer le retard de propagation entre le signal de sélection du circuit et la sortie de données du périphérique de mémoire. Type Temps Source CH1 Δt 20 ns 1/Δt 50 MHz ΔV 0,28 V Curseur 1 50 ns -0,20 V Curseur 2 70 ns 0,08 V Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 55 Exemples d’application Pour configurer la mesure du retard de propagation, procédez comme suit : 1. Appuyez sur le bouton AUTOSET pour déclencher un affichage stable. 2. Réglez les commandes horizontales et verticales pour optimiser l’affichage. 3. Appuyez sur le bouton CURSEURS pour afficher le menu correspondant. 4. Appuyez sur Type ► Temps. 5. Appuyez sur Source ► CH1. 6. Appuyez sur le bouton d’option Curseur 1. 7. Tournez le bouton multifonctionnel pour placer le curseur sur le front actif du signal de sélection du circuit. 8. Appuyez sur le bouton d’option Curseur 2. 9. Tournez le bouton multifonctionnel pour placer le deuxième curseur sur la transition de sortie de données. L’affichage Δt apparaissant dans le menu Curseurs est le délai de propagation entre les signaux. La mesure affichée est valide car les deux signaux ont le même réglage SEC/DIV. Déclenchement sur une largeur d’impulsion spécifique Vous testez les largeurs d’impulsion d’un signal dans un circuit. Il est essentiel que toutes les impulsions soient de largeur spécifique et vous devez vous en assurer. Le déclenchement sur front indique que votre signal est tel que spécifié et que la mesure de la largeur d’impulsion correspond aux spécifications. Cependant, vous pensez qu’un problème est susceptible de se produire. 56 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Pour établir un test de détection des aberrations de largeur d’impulsion, procédez comme suit : 1. Appuyez sur le bouton AUTOSET pour déclencher un affichage stable. 2. Dans le menu AUTOSET, appuyez sur le bouton d’option Cycle unique pour afficher un cycle unique du signal et pour prendre rapidement une mesure de la largeur d’impulsion. 3. Appuyez sur le bouton TRIG MENU pour afficher le menu Déclenchement. 4. Appuyez sur Type ► Impulsion. 5. Appuyez sur Source ► CH1. 6. Tournez la molette TRIGGER NIVEAU pour définir le niveau de déclenchement à proximité de la partie inférieure du signal. 7. Appuyez sur Quand ► = (égal). 8. Tournez le bouton multifonctionnel pour régler la largeur d’impulsion sur la valeur rapportée par la mesure de la largeur d’impulsion à l’étape 2. 9. Appuyez sur Suite ► Mode ► Normale. Vous pouvez obtenir un affichage stable présentant un déclenchement de l’oscilloscope sur des impulsions normales. 1. Appuyez sur le bouton d’option Quand pour sélectionner ≠, < ou >. La présence de toute impulsion aberrante satisfaisant à la condition Quand spécifiée provoque le déclenchement de l’oscilloscope. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 57 Exemples d’application REMARQUE. La mesure de la fréquence du déclenchement affiche la fréquence des événements que l’oscilloscope pourrait considérer comme un déclenchement ; elle peut être inférieure à la fréquence du signal d’entrée en mode de déclenchement sur largeur d’impulsion. Déclenchement sur un signal vidéo Vous testez le circuit vidéo d’un composant d’équipement médical et devez afficher le signal de sortie vidéo. La sortie vidéo est un signal NTSC standard. Utilisez le déclenchement vidéo pour obtenir un affichage stable. 58 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application REMARQUE. La plupart des systèmes vidéo utilisent un câblage de 75 ohms. La terminaison des entrées de l’oscilloscope ne correspond pas correctement au câblage à faible impédance. Pour éviter toute imprécision de l’amplitude résultant d’une charge et de réflexions impropres, placez un adaptateur de traversée de 75 ohms (référence Tektronix 011-0055-02 ou équivalent) entre le câble coaxial de 75 ohms à partir du générateur de signal et l’entrée BNC de l’oscilloscope. Déclenchement sur les trames vidéo Automatique. Pour procéder à un déclenchement sur les trames vidéo, procédez comme suit : 1. Appuyez sur le bouton AUTOSET. Une fois le réglage automatique (Autoset) terminé, l’oscilloscope affiche le signal vidéo dont la synchronisation est définie sur Ttes trames. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 59 Exemples d’application L’oscilloscope règle l’option Standard lorsque vous utilisez la fonction de réglage automatique (Autoset). 1. Appuyez sur les boutons d’option Trame imp. ou Trame paire dans le menu AUTOSET pour synchroniser sur les trames impaires ou paires uniquement. Manuel. Le recours à une autre méthode implique davantage d’étapes, mais peut s’avérer nécessaire en fonction du signal vidéo. Pour utiliser la méthode manuelle, procédez comme suit : 1. Appuyez sur le bouton CH 1 MENU. 2. Appuyez sur Couplage ► CA. 3. Appuyez sur le bouton TRIG MENU pour afficher le menu Déclenchement. 4. Appuyez sur le bouton d’option supérieur et sélectionnez Vidéo. 5. Appuyez sur Source ► CH1. 6. Appuyez sur le bouton d’option Synch. et sélectionnez Ttes trames, Trame imp. ou Trame paire. 7. Appuyez sur Standard ► NTSC. 8. Tournez la molette horizontale SEC/DIV pour afficher une trame entière sur tout l’écran. 9. Tournez la molette verticale VOLTS/DIV pour vous assurer que la totalité du signal vidéo est visible à l’écran. 60 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Déclenchement sur les lignes vidéo Automatique. Vous pouvez également examiner les lignes vidéo d’une trame. Pour procéder à un déclenchement sur les lignes vidéo, procédez comme suit : 1. Appuyez sur le bouton AUTOSET. 2. Appuyez sur le bouton d’option supérieur pour sélectionner Ligne afin de synchroniser sur toutes les lignes (le menu AUTOSET inclut les options Ttes lignes et No de ligne). Manuel. Le recours à une autre méthode implique davantage d’étapes, mais peut s’avérer nécessaire en fonction du signal vidéo. Pour utiliser cette méthode, procédez comme suit : 1. Appuyez sur le bouton TRIG MENU pour afficher le menu Déclenchement. 2. Appuyez sur le bouton d’option supérieur et sélectionnez Vidéo. 3. Appuyez sur le bouton d’option Synch., sélectionnez Ttes lignes ou No de ligne et tournez le bouton multifonctionnel pour définir un numéro de ligne spécifique. 4. Appuyez sur Standard ► NTSC. 5. Tournez la molette SEC/DIV pour afficher une ligne vidéo complète à l’écran. 6. Tournez la molette VOLTS/DIV pour vous assurer que la totalité du signal vidéo est visible à l’écran. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 61 Exemples d’application Signal vidéo entrant Utilisation de la fonction fenêtre pour afficher les détails du signal Vous pouvez utiliser la fonction fenêtre (zoom) pour examiner une partie spécifique d’un signal sans modifier l’affichage principal. 62 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Si vous souhaitez afficher la salve couleur du signal précédent de manière plus détaillée sans modifier l’affichage principal, procédez comme suit : 1. Appuyez sur le bouton HORIZ MENU pour afficher le menu Horizontal et sélectionnez l’option Base de temps principale. 2. Appuyez sur le bouton d’option Zone retardée. 3. Tournez la molette SEC/DIV et sélectionnez 500 ns. Il s’agit du réglage SEC/DIV de l’affichage étendu. 4. Tournez la molette HORIZONTAL POSITION pour positionner la fenêtre autour de la portion du signal que vous souhaitez étendre. 1. Appuyez sur le bouton d’option Fenêtre pour afficher la portion étendue du signal. 2. Tournez la molette SEC/DIV pour optimiser l’affichage du signal étendu. Pour passer de l’affichage de type Base de temps principale à l’affichage de type Fenêtre et inversement, appuyez sur le bouton d’option Base de temps principale ou Fenêtre dans le menu Horizontal. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 63 Exemples d’application Analyse d’un signal de communication différentiel Un lien de communication de données série vous pose régulièrement des problèmes en raison, selon vous, d’un signal de mauvaise qualité. Configurez l’oscilloscope pour qu’il affiche une capture instantanée de la chaîne de données série, vous permettant ainsi de vérifier les niveaux des signaux et les temps de transition. Puisqu’il s’agit d’un signal différentiel, vous utilisez la fonction mathématique de l’oscilloscope pour afficher une représentation optimisée du signal. 64 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application REMARQUE. Veillez d’abord à compenser les deux sondes. Les différences de compensation de sonde s’affichent sous forme d’erreurs dans le signal différentiel. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 65 Exemples d’application Pour activer les signaux différentiels connectés aux voies 1 et 2, suivez les étapes ci-dessous : 1. Appuyez sur le bouton CH 1 MENU et réglez l’option Sonde ► Tension► Atténuation sur 10X. 2. Appuyez sur le bouton CH 2 MENU et réglez l’option Sonde ► Tension► Atténuation sur 10X. 3. Réglez les commutateurs des sondes P2220 sur 10X. 4. Appuyez sur le bouton AUTOSET. 5. Appuyez sur le bouton MATH MENU pour afficher le menu Math. 6. Appuyez sur le bouton d’option Opération et sélectionnez -. 7. Appuyez sur le bouton d’option CH1-CH2 pour afficher un nouveau signal correspondant à la différence entre les signaux affichés. 8. Pour régler l’échelle verticale et la position du signal calculé, procédez comme suit : a. N’affichez plus les signaux des voies 1 et 2. b. Tournez les molettes VOLTS/DIV et VERTICAL POSITION de CH 1 et CH 2 pour régler l’échelle verticale et la position du signal calculé. Pour obtenir un affichage plus stable, appuyez sur le bouton SEQ. UNIQUEpour contrôler l’acquisition du signal. Chaque fois que vous appuyez sur le bouton SEQ. UNIQUE, l’oscilloscope acquiert une capture instantanée de la chaîne de données numériques. Vous pouvez utiliser les curseurs ou les mesures automatiques pour analyser le signal ou le stocker en vue d’une analyse ultérieure. Affichage des modifications d’impédance sur un réseau Vous avez conçu un circuit qui doit fonctionner dans une plage de température étendue. Vous devez évaluer la modification d’impédance du circuit puisqu’une variation de la température ambiante a été observée. 66 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Exemples d’application Connectez l’oscilloscope pour contrôler l’entrée et la sortie du circuit et capturez les modifications qui se produisent lorsque vous variez la température. Pour afficher l’entrée et la sortie du circuit au format d’affichage XY, procédez comme suit : 1. Appuyez sur le bouton CH 1 MENU. 2. Appuyez sur Sonde ► Tension ►Atténuation ► 10X. 3. Appuyez sur le bouton CH 2 MENU. 4. Appuyez sur Sonde ► Tension ►Atténuation ► 10X. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 67 Exemples d’application 5. Réglez les commutateurs des sondes P2220 sur 10X. 6. Connectez la sonde de la voie 1 à l’entrée du réseau et connectez la sonde de la voie 2 à la sortie. 7. Appuyez sur le bouton AUTOSET. 8. Tournez les molettes VOLTS/DIV pour afficher des signaux d’amplitude à peu près équivalents sur chaque voie. 9. Appuyez sur le bouton AFFICHAGE pour afficher le menu correspondant. 10. Appuyez sur Format ► XY. L’oscilloscope affiche une figure de Lissajous représentant les caractéristiques d’entrée et de sortie du circuit. 11. Tournez les molettes VOLTS/DIV et VERTICAL POSITION pour optimiser l’affichage. 12. Appuyez sur Persist. ► Infinie. 13. Appuyez sur le bouton d’option Contraste et tournez le bouton multifonctionnel pour modifier l’affichage. Lorsque vous réglez la température ambiante, la persistance de l’écran capture les modifications des caractéristiques du circuit. 68 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Fonctions mathématiques FFT Ce chapitre contient des informations détaillées sur l’utilisation de la fonction mathématique FFT (Transformée de Fourier rapide). Le mode mathématique Transformée de Fourier Rapide (FFT) vous permet de convertir un signal temporel (YT) pour obtenir ses composantes de fréquence (spectre). Le mode mathématique FFT permet les types d’analyses suivants : Analyser les harmoniques dans les lignes électriques Mesurer le contenu harmonique et la distorsion dans les systèmes Caractériser le bruit des alimentations CC Tester la réponse impulsionnelle des filtres et des systèmes Analyser les vibrations Pour utiliser le mode mathématique FFT, vous devez effectuer les tâches suivantes : Définir le signal source (temporel) Afficher le spectre FFT Sélectionner un type de fenêtre FFT Ajuster la cadence d’échantillonnage pour afficher la fréquence fondamentale et les harmoniques sans repliement du spectre Utiliser le zoom pour agrandir le spectre Utiliser les curseurs pour mesurer le spectre Réglage du signal temporel Avant d’utiliser le mode FFT, vous devez définir le signal temporel (YT). Pour ce faire, procédez comme suit : 1. Appuyez sur AUTOSET pour afficher un signal YT. 2. Tournez la molette VERTICAL POSITION pour centrer verticalement le signal YT (aucune division). Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 69 Fonctions mathématiques FFT Cela permet de s’assurer que la fonction FFT affichera une valeur CC correcte. 3. Tournez la molette HORIZONTAL POSITION pour positionner la portion de la courbe du signal YT que vous voulez analyser sur les huit divisions centrales de l’écran. L’oscilloscope calcule le spectre FFT à l’aide des 2 048 points centraux du signal temporel. 4. Tournez la molette VOLTS/DIV pour vous assurer que la totalité du signal s’affiche à l’écran. L’oscilloscope peut afficher des résultats FFT erronés (en ajoutant des composantes de fréquence élevée) si la totalité du signal n’est pas visible. 5. Tournez la molette SEC/DIV pour obtenir la résolution désirée dans le spectre FFT. 6. Si possible, réglez l’oscilloscope pour qu’il affiche plusieurs périodes de signal. Si vous tournez le bouton SEC/DIV afin de sélectionner un réglage plus rapide (moins de cycles), le spectre FFT affiche une plage de fréquences plus étendue et limite les possibilités d’un repliement du spectre. (Voir page 75, Repliement du spectre FFT.) Cependant, l’oscilloscope affiche également une résolution de fréquence inférieure. Pour définir l’affichage FFT, procédez comme suit : 1. Appuyez sur le bouton MATH MENU pour afficher le menu Math. 2. Appuyez sur Opération ► FFT. 3. Sélectionnez la voie Source FFT Math. En général, l’oscilloscope produit un spectre FFT utile même si le signal temporel (YT) n’est pas déclenché, en particulier si votre signal est périodique ou aléatoire (bruyant). REMARQUE. Déclenchez et positionnez tous les signaux transitoires ou de salve aussi précisément que possible au centre de l’écran. 70 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Fonctions mathématiques FFT Fréquence de Nyquist La fréquence la plus élevée pouvant être mesurée sans erreur par un oscilloscope numérique en temps réel équivaut à la moitié de la fréquence d’échantillonnage. Cette fréquence est appelée fréquence de Nyquist. Les informations relatives aux fréquences supérieures à la fréquence de Nyquist sont sous-échantillonnées, ce qui cause le repliement du spectre FFT. (Voir page 75, Repliement du spectre FFT.) La fonction mathématique transforme les 2 048 points centraux du signal temporel en spectre FFT. Le spectre FFT qui en résulte contient 1 024 points allant du CC (0 Hz) à la fréquence de Nyquist. Normalement, l’affichage compresse le spectre FFT horizontalement en 250 points, mais vous pouvez utiliser la fonction FFT Zoom pour le développer et visualiser plus clairement les composantes de fréquence sur chacun des 1 024 points de données du spectre FFT. REMARQUE. La réponse verticale de l’oscilloscope diminue lentement au-dessus de sa bande passante (40 MHz, 60 MHz, 100 MHz ou 200 MHz, en fonction du modèle, ou 20 MHz lorsque l’option Limite de bande passante est activée.) Le spectre FFT peut ainsi afficher des informations valides relatives à des fréquences plus élevées que la bande passante de l’oscilloscope. Cependant, les informations relatives à l’amplitude proches ou supérieures à la bande passante ne seront pas précises. Affichage du spectre FFT Appuyez sur le bouton MATH MENU pour afficher le menu Math. Utilisez les options pour sélectionner la voie source, l’algorithme de fenêtrage et le facteur de zoom FFT. Vous ne pouvez afficher qu’un seul spectre FFT à la fois. Option mathématique FFT Réglages Commentaires Source CH1, CH2, CH3 1, CH4 1 Permet de sélectionner la voie utilisée en tant que source FFT Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 71 Fonctions mathématiques FFT Option mathématique FFT Réglages Commentaires Fenêtre Hanning, Flattop, Rectangular Sélectionne le type de fenêtre FFT ;(Voir page 73, Sélection d’une fenêtre FFT.) Zoom FFT X1, X2, X5, X10 Permet de modifier l’agrandissement horizontal de l’affichage FFT ; (Voir page 76, Agrandissement et positionnement d’un spectre FFT.) 1 Disponible uniquement sur les oscilloscopes à 4 voies. Composante de fréquence fondamentale Composante de fréquence 1. Fréquence au niveau de la ligne centrale du réticule. 2. Echelle verticale, en dB par division (0 dB = 1 Veff). 3. Echelle horizontale, en fréquences par division. 4. Fréquence d’échantillonnage, en nombre d’échantillons par seconde. 5. Type de fenêtre FFT. 72 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Fonctions mathématiques FFT Sélection d’une fenêtre FFT La fonction fenêtre permet de réduire les fuites spectrales dans le spectre FFT. La fonction FFT suppose que le signal temporel (YT) se répète à l’infini. Avec un nombre entier de cycles (1, 2, 3, ...), le signal temporel démarre et se termine à la même amplitude ; il n’y a donc aucune discontinuité dans la forme du signal. Un nombre non entier de cycles dans le signal temporel provoque des points de début et de fin se situant à différentes amplitudes. Les transitions entre les points de début et de fin provoquent des discontinuités dans le signal pouvant introduire des transitoires haute fréquence. L’application d’une fonction fenêtre au signal temporel modifie le signal de façon à ce que les valeurs de début et de fin soient proches l’une de l’autre, réduisant ainsi les discontinuités. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 73 Fonctions mathématiques FFT La fonction mathématique FFT dispose de trois options de fenêtres FFT. Chaque type de fenêtre implique un compromis entre la résolution de fréquence et la précision de l’amplitude. Le choix de la fenêtre à utiliser doit s’effectuer en fonction de la nature de la valeur à mesurer et des caractéristiques du signal source. Fenêtre Mesures Caractéristiques Hanning Signaux périodiques Meilleure précision de la fréquence, moins bonne précision de l’amplitude que Flattop Flattop Signaux périodiques Meilleure précision de l’amplitude, moins bonne précision de la fréquence que Hanning Rectangular Signaux impulsionnels ou transitoires Fenêtre conçue spécifiquement pour les signaux sans discontinuité. Le résultat est essentiellement comparable à l’absence de fenêtre 74 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Fonctions mathématiques FFT Repliement du spectre FFT Ces problèmes surviennent lorsque l’oscilloscope acquiert un signal temporel contenant des composantes de fréquence plus élevée que dans la fréquence de Nyquist. (Voir page 71, Fréquence de Nyquist.) Les composantes de fréquence supérieures à la fréquence de Nyquist sont sous-échantillonnées et apparaissent sous forme de composantes de fréquence inférieure, qui se « replient » autour de la fréquence de Nyquist. Ces composantes incorrectes sont appelées fausses fréquences. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 75 Fonctions mathématiques FFT Elimination des fausses fréquences Pour éliminer les fausses fréquences, essayez les solutions suivantes : Tournez la molette SEC/DIV de façon à régler la fréquence d’échantillonnage sur une valeur plus rapide. Puisque vous augmentez la fréquence de Nyquist en augmentant la fréquence d’échantillonnage, les composants de fausses fréquences apparaissent à la fréquence appropriée. Si trop de composantes de fréquence s’affichent à l’écran, vous pouvez utiliser l’option FFT Zoom pour agrandir le spectre FFT. Si vous n’avez pas besoin d’afficher les composantes de fréquence supérieures à 20 MHz, activez l’option Limite de bande passante. Placez un filtre externe sur le signal source pour limiter la bande passante du signal source aux fréquences inférieures à la fréquence de Nyquist. Identifiez et ignorez les fréquences repliées. Utilisez le zoom et les curseurs pour agrandir et mesurer le spectre FFT. Agrandissement et positionnement d’un spectre FFT Vous pouvez agrandir le spectre FFT et utiliser les curseurs pour le mesurer. L’oscilloscope comprend une option FFT Zoom qui permet d’effectuer des agrandissements horizontalement. Pour agrandir verticalement, vous pouvez utiliser les réglages verticaux. Position et zoom horizontaux L’option FFT Zoom vous permet d’agrandir horizontalement le spectre FFT sans modifier la fréquence d’échantillonnage. Les facteurs de zoom sont X1 (par défaut), X2, X5 et X10. Lorsque le facteur de zoom est X1 et que le signal est centré sur le réticule, la ligne du réticule située le plus à gauche correspond à 0 Hz et celle du réticule le plus à droite à la fréquence de Nyquist. Lorsque vous modifiez le facteur du zoom, le spectre FFT est agrandi à partir de la ligne du réticule central. Autrement dit, c’est la ligne du réticule central qui constitue l’axe d’agrandissement horizontal. 76 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Fonctions mathématiques FFT Tournez la molette HORIZONTAL POSITION dans le sens des aiguilles d’une montre pour déplacer le spectre FFT vers la droite. Appuyez sur le bouton REGLER SUR 0 pour positionner le centre du spectre au centre du réticule. Position et zoom verticaux Lorsque le spectre FFT est affiché, les molettes verticales de la voie permettent de zoomer verticalement et de positionner les voies correspondantes. La molette VOLTS/DIV dispose de facteurs de zoom de X0,5, X1 (par défaut), X2, X5 et X10. Le spectre FFT est agrandi verticalement à partir du marqueur M (point de référence du signal calculé sur le bord gauche de l’écran). Tournez la molette VERTICAL POSITION dans le sens des aiguilles d’une montre pour déplacer le spectre de la voie source vers le haut. Mesure d’un spectre FFT à l’aide des curseurs Vous pouvez prendre deux types de mesure sur les spectres FFT : l’amplitude (en dB) et la fréquence (en Hz). L’amplitude est référencée à 0 dB, où 0 dB équivaut à 1 Veff. Vous pouvez utiliser les curseurs pour prendre des mesures avec n’importe quel facteur de zoom. Pour ce faire, procédez comme suit : 1. Appuyez sur le bouton CURSEURS pour afficher le menu Curseurs. 2. Appuyez sur Source ► MATH. 3. Appuyez sur le bouton d’option Type et sélectionnez Amplitude ou Fréquence. 4. Utilisez le bouton multifonctionnel pour déplacer les curseurs 1 et 2. Utilisez les curseurs horizontaux pour mesurer l’amplitude et les curseurs verticaux pour mesurer la fréquence. Les options permettent d’afficher le delta entre les deux curseurs, la valeur au niveau de la position du curseur 1 et la valeur au niveau de la position du curseur 2. Le delta est la valeur absolue du curseur 1 moins le curseur 2. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 77 Fonctions mathématiques FFT Amplitude, curseurs Fréquence, curseurs Vous pouvez également effectuer une mesure de fréquence sans utiliser les curseurs. Pour ce faire, tournez la molette HORIZONTAL POSITION pour positionner une composante de fréquence sur la ligne du réticule central et lisez la fréquence en haut à droite de l’écran. 78 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique Ce chapitre explique comment utiliser les ports USB (Universal Serial Bus) de l’oscilloscope pour effectuer les tâches suivantes : enregistrer et rappeler des données de signal ou de configuration, ou enregistrer une image d’écran, imprimer une image d’écran, transférer des données de signal, des données de configuration ou une image d’écran vers un PC, contrôler l’oscilloscope grâce à des commandes à distance. Pour utiliser le logiciel de communication pour PC, lancez et reportez-vous à l’aide en ligne du logiciel. Port du lecteur flash USB Le panneau avant de l’oscilloscope dispose d’un port de lecteur flash USB : ceci permet de raccorder un lecteur flash USB afin d’y stocker des fichiers. L’oscilloscope peut enregistrer et récupérer des données sur le lecteur flash. port du lecteur flash USB REMARQUE. L’oscilloscope peut prendre en charge uniquement des lecteurs flash d’une capacité de stockage inférieure ou égale à 2 GBits. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 79 Port du lecteur flash USB et port périphérique Pour brancher un lecteur flash USB, suivez les étapes ci-dessous : 1. Alignez le lecteur flash USB avec le port correspondant sur l’oscilloscope. Les lecteurs flash disposent d’une installation appropriée. 2. Insérez le lecteur flash dans le port jusqu’à son insertion complète. Pour les lecteurs flash équipés d’un voyant LED, celui-ci clignote lorsque l’oscilloscope écrit ou lit des données sur le lecteur. L’oscilloscope affiche également un symbole en forme d’horloge pour indiquer quand le lecteur flash est actif. Après la sauvegarde ou la récupération d’un fichier, le voyant LED sur le lecteur (s’il existe) cesse de clignoter et l’oscilloscope n’affiche plus l’horloge. Une ligne de conseil s’affiche également pour vous indiquer que l’opération de sauvegarde ou de rappel est terminée. Pour retirer un lecteur flash USB, attendez que le voyant LED sur le lecteur (s’il existe) cesse de clignoter ou que la ligne de conseil indiquant la fin de l’opération apparaisse, puis saisissez le bord du lecteur et extrayez-le du port. Temps de lecture initial du lecteur flash L’oscilloscope lit la structure interne d’un lecteur flash USB chaque fois que vous installez un lecteur. Le temps de lecture dépend de la taille du lecteur flash, du formatage du lecteur et du nombre de fichiers stockés sur le lecteur. REMARQUE. Pour réduire sensiblement le temps de lecture initial des lecteurs flash USB de 64 Mo et plus, formatez le lecteur sur votre PC. 80 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique Formatage d’un lecteur flash La fonction Format supprime toutes les données présentes sur le lecteur flash USB. Pour formater un lecteur flash, suivez les étapes ci-dessous : 1. Insérez un lecteur flash USB dans le port du lecteur flash situé sur le panneau avant de l’oscilloscope. 2. Appuyez sur le bouton UTILITAIRE pour afficher le menu Utilitaire. 3. Appuyez sur Utilitaires Fichiers ► Suite ► Format. 4. Sélectionnez Oui pour formater le lecteur flash. Capacités d’un lecteur flash L’oscilloscope peut stocker les types et nombres de fichiers suivants dans 1 Mo de mémoire du lecteur flash USB : 5 opérations Sauveg. tot. ; (Voir page 85, Sauvegarde tout.) (Voir page 121, Sauveg. tot..) 16 fichiers images d’écran (la capacité dépend du format de l’image) ; (Voir page 87, Sauvegarde image.) (Voir page 122, Sauvegarde image.) 250 fichiers de réglage (.SET) de l’oscilloscope ; (Voir page 123, Sauvegarde config..) 18 fichiers de signal (.CSV) ; (Voir page 124, Mise en mémoire.) Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 81 Port du lecteur flash USB et port périphérique Conventions de gestion des fichiers L’oscilloscope utilise les conventions de gestion des fichiers suivantes pour le stockage de données : L’oscilloscope vérifie l’espace disponible sur le lecteur flash USB avant d’écrire les fichiers ; il affiche un message d’avertissement si la mémoire disponible est insuffisante. Le terme « dossier » fait référence à un répertoire sur le lecteur flash USB. L’emplacement de sauvegarde ou de rappel des fichiers par défaut est le dossier courant. Le dossier racine est A:\. L’oscilloscope réinitialise le dossier courant sur A:\ lorsque vous allumez l’oscilloscope ou lorsque vous insérez un lecteur flash USB après la mise sous tension de l’appareil. Les noms de fichier peuvent contenir de un à huit caractères suivis d’un point, puis une extension contenant de un à trois caractères. L’oscilloscope affiche les noms de fichiers longs créés sur les systèmes d’exploitation pour PC sous la forme courte provenant du système d’exploitation. Les noms de fichier ne tiennent pas compte de la casse et sont affichés en majuscules. Le menu Utilitaires Fichiers permet d’effectuer les opérations suivantes : répertorier le contenu du dossier courant sélectionner un fichier ou un dossier accéder à d’autres dossiers créer, renommer et supprimer des fichiers et des dossiers formater le lecteur flash USB. (Voir page 139, Utilitaires Fichiers pour le lecteur flash USB.) 82 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique Sauvegarde et rappel de fichiers avec un lecteur flash USB Il existe deux façons de procéder au stockage de fichiers sur le lecteur flash USB : à partir du menu Sauv./Rap, à partir de la fonction alternative Mise en mémoire de la touche PRINT. Vous pouvez utiliser les options suivantes du menu Sauv./Rap pour écrire ou récupérer des données sur un lecteur flash USB : Sauvegarde image Sauvegarde config. Mise en mémoire Rappel config. Rappel Signal REMARQUE. La touche PRINT peut être utilisée comme bouton ENREGISTRER pour stocker rapidement des fichiers sur un lecteur flash. Pour savoir comment enregistrer plusieurs fichiers en une seule fois ou des images les unes après les autres, reportez-vous à la section Utilisation des fonctions de sauvegarde de la touche PRINT. (Voir page 85, Utilisation de la fonction de sauvegarde du bouton PRINT du panneau avant.) Options Sauvegarde image, Sauvegarde config. et Mise en mémoire Vous pouvez enregistrer une image d’écran, les réglages de l’oscilloscope ou des données de signal dans un fichier sur le lecteur flash USB grâce au menu Sauv./Rap. Chaque option d’enregistrement fonctionne de façon similaire. Par exemple, pour enregistrer un fichier image d’écran sur un lecteur flash, suivez les étapes ci-dessous : 1. Insérez un lecteur flash USB dans le port du lecteur flash USB. 2. Appuyez sur UTILITAIRE ► Options ► Configuration imprimante et configurez les options suivantes : Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 83 Port du lecteur flash USB et port périphérique Economie d’encre Act., Désact. Imprime l’image d’écran sur fond blanc lorsque vous sélectionnez Act. Présentation Portrait, Paysage Orientation de la sortie papier de l’imprimante 3. Accédez à l’écran que vous souhaitez sauvegarder. 4. Appuyez sur le bouton SAUV./RAP du panneau avant. 5. Sélectionnez l’option Action ► Sauvegarde image ► Mise en mémoire. L’oscilloscope enregistre l’image d’écran dans le dossier courant et génère automatiquement le nom du fichier. (Voir page 120, Sauvegarder/Rappeler.) Options Rappel config. et Rappel Signal Vous pouvez rappeler les réglages de l’oscilloscope ou des données de signal à partir d’un fichier sur le lecteur flash USB grâce au menu Sauv./Rap. Chaque option de rappel fonctionne de façon similaire. Par exemple, pour rappeler un fichier de signal à partir d’un lecteur flash USB, suivez les étapes ci-dessous : 1. Insérez le lecteur flash USB contenant le fichier de signal souhaité dans le port du lecteur flash USB situé sur le panneau avant de l’oscilloscope. 2. Appuyez sur le bouton SAUV./RAP du panneau avant. 3. Sélectionnez l’option Action ► Rappel Signal ► Sélection Fichier. Vous pouvez utiliser l’option Modif. Dossier pour accéder à un autre dossier sur le lecteur flash. 4. Tournez le bouton multifonctionnel pour sélectionner le fichier de signal à rappeler. Dans l’option Rappel, le nom du fichier change au cours du défilement. 84 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique 5. Sélectionnez l’option Vers et spécifiez l’emplacement de mémoire de référence pour rappeler le signal vers RéfA ou RéfB. RéfC et RéfD sont disponibles sur les modèles à 4 voies. 6. Appuyez sur le bouton d’option Rappel FnnnnCHx.CSV, où FnnnnCHx.CSV est le nom du fichier de signal. REMARQUE. Pour les dossiers sur le lecteur flash contenant un fichier de signal, sélectionnez l’option SAUV./RAP ► Action ►Rappel Signal ► Vers et spécifiez l’emplacement de mémoire de référence pour rappeler le signal. Le nom du fichier apparaît dans l’option Rappel.(Voir page 120, Sauvegarder/Rappeler.) Utilisation de la fonction de sauvegarde du bouton PRINT du panneau avant Vous pouvez configurer la touche PRINT du panneau avant pour écrire des données sur le lecteur flash USB comme fonction alternative. Pour configurer la fonction de la touche PRINT, accédez à l’une des options suivantes : SAUV./RAP ► Sauveg. tot. ► Touche PRINT UTILITAIRE ►Options ► Configuration imprimante REMARQUE. Un voyant LED à côté de la touche PRINT s’allume pour indiquer la fonction alternative ENREGISTRER, qui écrit des données sur le lecteur flash USB. Sauvegarde tout L’option Sauvegarde tout vous permet de sauvegarder les informations en cours de l’oscilloscope dans des fichiers sur le lecteur flash USB. Une seule action Sauvegarde tout nécessite moins de 700 Ko d’espace sur le lecteur flash. Avant de pouvoir enregistrer des données sur le lecteur flash USB, vous devez appliquer la fonction de sauvegarde alternative à la touche PRINT du panneau avant. Pour ce faire, sélectionnez l’option SAUV./RAP ► Sauveg. tot. ► Touche PRINT ► Sauvegarde tout. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 85 Port du lecteur flash USB et port périphérique Pour enregistrer tous les fichiers de l’oscilloscope sur un lecteur flash USB, suivez les étapes ci-dessous : 1. Insérez un lecteur flash USB dans le port du lecteur flash USB. 2. Pour modifier le dossier désigné comme dossier courant, appuyez sur le bouton d’option Sélection Dossier. L’oscilloscope crée un nouveau dossier dans le dossier courant chaque fois que vous appuyez sur la touche PRINT du panneau avant et il génère automatiquement le nom de dossier. 3. Configurez l’oscilloscope pour capturer vos données. 4. Appuyez sur le bouton PRINT (ENREGISTRER). L’oscilloscope crée un nouveau dossier sur le lecteur flash et enregistre l’image d’écran, les données de signal et les données de configuration dans des fichiers distincts au sein de ce nouveau dossier, en utilisant les réglages courants de l’oscilloscope et de format de fichier. L’oscilloscope nomme ce dossier ALLnnnn. (Voir page 120, Sauvegarder/Rappeler.) Pour afficher la liste des fichiers créés par la fonction Sauvegarde tout, accédez au menu UTILITAIRE ►Utilitaires Fichiers. Source Nom de fichier CH(x) FnnnnCHx.CSV, où nnnn est un nombre généré automatiquement et x correspond au numéro de la voie. MATH FnnnnMTH.CSV Réf(x) FnnnnRFx.CSV, où x correspond à la lettre de la mémoire de référence. Image d’écran FnnnnTEK.???, où ??? représente le format de fichier courant. Réglages FnnnnTEK.SET 86 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique Type de fichier Contenu et usages .CSV Contient des chaînes de texte ASCII donnant les valeurs de temps (par rapport au déclenchement) et d’amplitude pour chacun des 2 500 points de données du signal ; vous pouvez importer des fichiers .CSV dans de nombreux tableurs et applications d’analyse mathématique. .SET Contient une chaîne de texte ASCII énumérant les réglages de l’oscilloscope ; reportez-vous au Manuel de programmation des oscilloscopes à mémoire numérique TDS200, TDS1000/2000, TDS1000B/2000B et TPS2000 pour décoder cette chaîne. Images d’écran Fichiers à importer dans des tableurs et applications de traitement de texte ; le type de fichier image dépend de l’application. REMARQUE. L’oscilloscope conserve les réglages jusqu’à leur modification, même si vous appuyez sur le bouton CONF. PAR D. Sauvegarde image Cette option vous permet de sauvegarder l’image d’écran de l’oscilloscope dans un fichier nommé TEKnnnn.???, où .??? représente le format en cours de la fonction Sauvegarde image. Le tableau suivant énumère les formats de fichier. Format de fichier Extension Commentaires BMP BMP Ce format bitmap utilise un algorithme de compression sans perte et il est compatible avec la plupart des programmes de traitement de texte et tableurs ; il s’agit du format par défaut. EPSIMAGE EPS Format Postscript Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 87 Port du lecteur flash USB et port périphérique Format de fichier Extension Commentaires JPEG JPG Ce format bitmap utilise un algorithme de compression à perte et il est généralement utilisé par les appareils photo numériques et d’autres applications pour la photo numérique. PCX PCX Format Paintbrush DOS RLE RLE Run-Length Encoding ; ce format utilise un algorithme de compression sans perte. TIFF TIF Tagged Image File Format (Format de fichier graphique) Avant de pouvoir enregistrer des données sur le lecteur flash USB, vous devez appliquer la fonction de sauvegarde alternative à la touche PRINT. Pour ce faire, sélectionnez l’option SAUV./RAP ► Sauveg. tot. ► Touche PRINT ► Sauvegarde image. Le voyant LED ENREGISTRER adjacent à la touche PRINT s’allume pour indiquer la fonction alternative. Pour enregistrer une image d’écran sur un lecteur flash USB, suivez les étapes ci-dessous : 1. Insérez un lecteur flash USB dans le port du lecteur flash USB. 2. Pour modifier le dossier désigné comme dossier courant, appuyez sur le bouton d’option Sélection Dossier. 3. Accédez à l’écran que vous souhaitez sauvegarder. 4. Appuyez sur le bouton PRINT (ENREGISTRER). L’oscilloscope enregistre l’image d’écran et génère automatiquement le nom de fichier. Pour afficher la liste des fichiers créés par la fonction Sauvegarde image, vous pouvez accéder au menu UTILITAIRE ► Utilitaires Fichiers. 88 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique Port périphérique USB Vous pouvez utiliser un câble USB pour raccorder l’oscilloscope à un PC ou à une imprimante compatible PictBridge. Le port périphérique USB se trouve à l’arrière de l’oscilloscope. Port périphérique USB Installation du logiciel de communication sur un PC Avant de raccorder l’oscilloscope à un PC, vous devez installer le logiciel de communication pour PC à partir du CD fourni avec l’appareil. ATTENTION. Si vous raccordez l’oscilloscope à votre PC avant d’installer le logiciel, le PC ne reconnaîtra pas l’oscilloscope. Le PC considèrera alors l’oscilloscope comme un périphérique inconnu et ne communiquera pas avec celui-ci. Pour éviter ce problème, installez le logiciel sur votre PC avant de raccorder l’oscilloscope à votre PC. REMARQUE. Assurez-vous d’avoir installé la même version du logiciel de communication pour PC que celle fournie avec l’oscilloscope ou bien une version supérieure. Le logiciel conçu pour l’oscilloscope est également disponible sur le site Web de Tektronix, à la section de recherche de logiciels. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 89 Port du lecteur flash USB et port périphérique Pour installer le logiciel de communication pour PC, suivez les étapes ci-dessous : 1. Insérez le CD-ROM fourni avec l’oscilloscope dans le lecteur de CD de votre PC. L’assistant d’installation InstallShield apparaît à l’écran. 2. Suivez ensuite les instructions affichées à l’écran. 3. Quittez l’assistant d’installation InstallShield. Connexion à un PC Après avoir installé le logiciel sur votre PC, vous pouvez raccorder l’oscilloscope au PC. REMARQUE. Vous devez installer le logiciel avant de raccorder l’oscilloscope au PC. (Voir page 89, Installation du logiciel de communication sur un PC.) Pour raccorder l’oscilloscope au PC, suivez les étapes ci-dessous : 1. Mettez l’oscilloscope sous tension. 2. Insérez l’une des extrémités d’un câble USB dans le port périphérique USB, à l’arrière de l’oscilloscope. 3. Mettez l’ordinateur sous tension. 4. Insérez l’autre extrémité du câble dans le port USB souhaité sur le PC. 5. Si un message similaire à « Nouveau matériel » s’affiche, suivez les instructions affichées à l’écran dans l’assistant Matériel détecté. NE cherchez PAS le matériel à installer sur le Web. 6. Pour les systèmes Windows XP, suivez les étapes ci-dessous : a. Si la boîte de dialogue du périphérique PictBridge de Tektronix apparaît, cliquez sur Annuler. b. A l’invite, sélectionnez l’option demandant à Windows de NE PAS se connecter à Windows Update, puis cliquez sur Suivant. 90 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique c. La fenêtre suivante devrait vous indiquer que vous êtes en train d’installer un logiciel pour un périphérique USB de test et de mesures. Si vous ne voyez pas le logiciel pour périphérique USB de test et de mesures, le logiciel fourni avec l’oscilloscope n’est pas correctement installé. d. Sélectionnez l’option qui installe automatiquement le logiciel (option recommandée) et cliquez sur Suivant. Windows installe le pilote pour votre oscilloscope. e. Si vous ne voyez pas le périphérique USB de test et de mesures lors de l’étape c ou si Windows ne parvient pas à trouver le pilote du logiciel, le logiciel fourni avec l’oscilloscope n’est pas installé correctement. Dans ces situations, cliquez sur Annuler pour quitter l’assistant Matériel détecté. NE laissez PAS l’assistant aller à son terme. Débranchez le câble USB de votre oscilloscope et installez le logiciel du CD fourni avec l’oscilloscope. Rebranchez votre oscilloscope au PC et suivez les étapes 6a, 6b, 6c, et 6d. f. Cliquez sur Terminer. g. Si une boîte de dialogue nommée Périphérique USB de test et de mesures apparaît, choisissez l’opération que Windows doit effectuer, puis cliquez sur OK. 7. Pour les systèmes Windows 2000 : a. A l’invite, sélectionnez l’option demandant à Windows d’afficher une liste des pilotes connus et cliquez sur Suivant. b. Dans la fenêtre suivante, sélectionnez Périphérique USB de test et de mesures. Si vous ne voyez pas de sélection Périphérique USB de test et de mesures, le logiciel fourni avec l’oscilloscope n’est pas correctement installé. c. Dans la fenêtre suivante, cliquez sur Suivant pour permettre à Windows d’installer le pilote pour votre oscilloscope. Windows installe le pilote pour votre oscilloscope. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 91 Port du lecteur flash USB et port périphérique d. Si vous ne voyez pas le périphérique USB de test et de mesures lors de l’étape b ou si Windows ne parvient pas à trouver le pilote du logiciel, le logiciel fourni avec l’oscilloscope n’est pas installé correctement. Dans ces situations, cliquez sur Annuler pour quitter l’assistant Ajout de nouveau matériel détecté. NE laissez PAS l’assistant aller à son terme. Débranchez le câble USB de votre oscilloscope et installez le logiciel du CD fourni avec l’oscilloscope. Rebranchez votre oscilloscope au PC et suivez les étapes 7a, 7b et 7c. 8. A l’invite, cliquez sur Terminer. 9. Si Windows vous demande d’insérer un CD, cliquez sur Annuler. 10. Exécutez le logiciel de communication pour PC sur votre PC. 11. Si l’oscilloscope et le PC ne communiquent pas, reportez-vous à l’aide et à la documentation en ligne de communication pour PC. 92 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique Connexion à un système GPIB Si vous souhaitez établir une communication entre l’oscilloscope et un système GPIB, utilisez un adaptateur TEK-USB-488 et suivez les étapes ci-dessous : 1. Raccordez l’oscilloscope à un adaptateur TEK-USB-488 avec un câble USB. L’annexe Accessoires dispose d’informations concernant la commande d’un adaptateur. (Voir page 167, Accessoires.) 2. Raccordez l’adaptateur TEK-USB-488 à votre système GPIB à l’aide d’un câble GPIB. 3. Appuyez sur le bouton d’option UTILITAIRE ► Option ► Configuration du bus GPIB ► Adresse pour sélectionner l’adresse appropriée pour l’adaptateur ou utilisez le bouton multifonctionnel. L’adresse GPIB par défaut est 1. 4. Exécutez le logiciel GPIB sur votre système GPIB. 5. Si l’oscilloscope et votre système GPIB ne communiquent pas, reportez-vous aux informations concernant le logiciel de votre système GPIB et au manuel de l’utilisateur de l’adaptateur TEK-USB-488 pour résoudre le problème. Saisie de commande REMARQUE. Pour des informations détaillées sur les commandes, reportez-vous au Manuel de programmation des oscilloscopes numériques TDS200, TDS1000/2000, TDS1000B/2000B et TPS2000 (071-1075-XX). Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 93 Port du lecteur flash USB et port périphérique Connexion à une imprimante Lorsque vous connectez l’oscilloscope à une imprimante compatible PictBridge, l’oscilloscope et l’imprimante peuvent être mis sous ou hors tension. Pour raccorder l’oscilloscope à une imprimante compatible PictBridge, suivez les étapes ci-dessous : 1. Insérez l’une des extrémités d’un câble USB dans le port périphérique USB de l’oscilloscope. 2. Insérez l’autre extrémité du câble dans le port PictBridge d’une imprimante compatible PictBridge. Reportez-vous à la documentation produit de votre imprimante pour localiser ce port. 3. Pour tester la connexion, configurez l’oscilloscope pour imprimer, comme indiqué dans la procédure suivante. REMARQUE. L’imprimante reconnaît l’oscilloscope uniquement lorsqu’elle est mise sous tension. Si l’oscilloscope vous demande de le raccorder à une imprimante et que celle-ci est raccordée, vous devez mettre l’imprimante sous tension. 94 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Port du lecteur flash USB et port périphérique Imprimer une image d’écran Pour configurer une imprimante compatible PictBridge, suivez les étapes ci-dessous : 1. Mettez l’oscilloscope et l’imprimante sous tension. 2. Appuyez sur UTILITAIRE ► Options ► Configuration imprimante ► Touche PRINT et sélectionnez l’option Imprime. 3. Configurez l’option Economie d’encre sur Act., le réglage par défaut. 4. Appuyez sur les boutons d’option - suite - page 2 de 3 et - suite - page 3 de 3 pour configurer l’imprimante. L’oscilloscope interroge l’imprimante et n’affiche que les options et les valeurs prises en charge par l’imprimante. Si vous n’êtes pas sûr du réglage à choisir, sélectionnez Par défaut pour chaque option. 5. Pour imprimer une image d’écran, appuyez sur la touche PRINT du panneau avant. L’oscilloscope prend quelques secondes pour capturer l’image d’écran. Les réglages de votre imprimante et la vitesse d’impression déterminent le temps d’impression des données. Selon le format sélectionné, cela peut prendre plus de temps que prévu. REMARQUE. Vous pouvez continuer à utiliser l’oscilloscope lors de l’impression. 6. Si l’impression échoue, vérifiez que le câble USB est connecté au port PictBridge de l’imprimante, puis réessayez. REMARQUE. L’oscilloscope conserve les réglages jusqu’à leur modification, même si vous appuyez sur le bouton CONF. PAR D. ou si vous mettez l’oscilloscope hors tension. REMARQUE. Pour arrêter l’envoi de l’image d’écran à l’imprimante, appuyez sur Suspendre impression. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 95 Port du lecteur flash USB et port périphérique 96 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Ce chapitre décrit les menus et les détails du fonctionnement associés à chaque bouton ou commande des menus du panneau avant. Acquisition Appuyez sur le bouton ACQUISITION pour régler les paramètres d’acquisition. Options Réglages Commentaires Normale Acquiert et affiche avec précision la plupart des signaux ; il s’agit du mode par défaut Détect Créte Détecte les parasites et réduit les risques de repliement du spectre Moyenne Réduit le bruit aléatoire et sans corrélation avec le signal affiché ; vous pouvez sélectionner le nombre de moyennes Moyennes 4, 16, 64, 128 Sélectionne le nombre de moyennes Informations importantes Si vous sondez un signal carré bruyant contenant des parasites étroits et intermittents, le signal affiché va varier en fonction du mode d’acquisition choisi. Normale Détect Créte Moyenne Normale. Utilisez le mode d’acquisition Echantillon pour acquérir 2 500 points et les afficher dans le réglage SEC/DIV. Le mode Normale est le mode par défaut. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 97 Référence Intervalles d’acquisition en mode Normale (2 500) • Points d’échantillonnage Le mode Normale acquiert un seul et unique point d’échantillonnage dans chaque intervalle. L’oscilloscope échantillonne selon les fréquences suivantes : 500 M éch./s minimum pour les modèles de 40 MHz 1 G éch./s maximum pour les modèles de 60 MHz ou 100 MHz 2 G éch./s maximum pour les modèles de 200 MHz A 100 ns et avec des réglages plus rapides, cette fréquence d’échantillonnage n’est pas suffisante pour acquérir 2 500 points. Dans ce cas, un processeur numérique de signaux interpole les points entre les points d’échantillonnage, afin de créer un enregistrement du signal comportant 2 500 points. Détect Créte. Utilisez le mode d’acquisition Détect Créte pour détecter les parasites d’une largeur de 10 ns et pour réduire les risques de repliement du spectre. Ce mode est effectif lorsque le bouton SEC/DIV est réglé sur 5 ms/div ou plus lent. 98 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Intervalles d’acquisition en mode Détect Créte (1 250) • Points d’échantillonnage affichés Le mode Détect Créte affiche la tension la plus élevée et la moins élevée acquise dans chaque intervalle. REMARQUE. Si vous réglez le bouton SEC/DIV sur 2,5 ms/div ou sur une valeur plus rapide, le mode d’acquisition passe en mode Normale car la cadence d’échantillonnage est suffisamment rapide et vous n’avez donc pas besoin d’utiliser Détect Créte. L’oscilloscope n’affiche aucun message indiquant que le mode est passé en Normale. Lorsque le bruit du signal est suffisamment important, une zone d’affichage de Détect Créte type affiche alors de grandes zones sombres. Pour un meilleur affichage, les oscilloscopes remplissent cette zone de lignes diagonales. Zone d’affichage de Détect Créte type Zone d’affichage de Détect Créte TDS1000B/TDS2000B Moyenne. Utilisez le mode d’acquisition Moyenne pour réduire le bruit aléatoire ou sans corrélation avec le signal à afficher. Les données sont acquises en mode échantillon, l’oscilloscope fait ensuite la moyenne de plusieurs signaux. Sélectionnez le nombre d’acquisitions (4, 16, 64 ou 128) pour effectuer la moyenne du signal. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 99 Référence Bouton RUN/STOP. Appuyez sur le bouton RUN/STOP pour que l’oscilloscope acquière les signaux en continu. Appuyez à nouveau sur le bouton pour interrompre l’acquisition. Bouton SEQ. UNIQUE. Appuyez sur le bouton SEQ. UNIQUE pour que l’oscilloscope acquière un signal unique, puis s’arrête. Chaque fois que vous appuyez sur le bouton SEQ. UNIQUE, l’oscilloscope commence l’acquisition d’un autre signal. Une fois que l’oscilloscope a détecté un déclenchement, il termine l’acquisition en cours et s’arrête. Mode d’acquisition SEQ. UNIQUE, bouton Normale, Détect Créte La séquence est terminée une fois l’acquisition effectuée Moyenne La séquence est terminée une fois le nombre d’acquisitions défini atteint ; (Voir page 97, Acquisition.) Affichage en mode Balayage. Le mode d’acquisition Balayage horizontal (également appelé mode Défilement) vous permet de surveiller en permanence les signaux qui connaissent des modifications lentes. L’oscilloscope affiche les mises à jour de signaux en allant de gauche à droite sur l’écran et supprime les anciens points au fur et à mesure de l’affichage des nouveaux points. Une section en mouvement vide d’une largeur égale à une division sépare les nouveaux échantillons des anciens. L’oscilloscope passe en mode d’acquisition Balayage si vous tournez la molette SEC/DIV jusqu’à obtenir un réglage de 100 ms/div ou plus lent, lorsque l’option Mode Auto est sélectionnée dans le menu TRIGGER. Pour désactiver le mode Balayage, appuyez sur le bouton TRIG MENU et définissez l’option Mode sur Normal. Interruption de l’acquisition. Lorsque l’acquisition est en cours, l’affichage du signal est actif. Si vous stoppez l’acquisition (en appuyant sur le bouton RUN/STOP), l’affichage est alors figé. Dans tous les modes, vous pouvez mettre à l’échelle ou positionner l’affichage du signal à l’aide des réglages horizontaux et verticaux. 100 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Calibrage Auto Lorsque vous appuyez sur le bouton CALIBRAGE AUTO, l’oscilloscope active ou désactive la fonction correspondante. Un voyant LED s’allume à côté du bouton CALIBRAGE AUTO pour indiquer que la fonction est active. Cette fonction ajuste automatiquement la configuration pour suivre un signal. Si le signal change, la configuration continue à suivre le signal. Lorsque vous mettez l’oscilloscope sous tension, la fonction d’ajustement automatique est toujours désactivée. Options Commentaires Ajustement automatique Active ou désactive la fonction d’ajustement automatique (Autorange) ; lorsque cette fonction est active, le voyant LED correspondant s’allume Vertical et Horizontal Suit et ajuste les deux axes Vertical Uniquement Suit et ajuste l’échelle Verticale ; les réglages horizontaux ne changent pas Horizontal Uniquement Suit et ajuste l’échelle Horizontale ; les réglages verticaux ne changent pas Undo Autoranging Annule la configuration actuelle de l’oscilloscope et rétablit la précédente La fonction d’ajustement automatique (Autorange) intervient dans les conditions suivantes : trop ou trop peu de périodes de signal pour avoir un affichage clair de la source de déclenchement (à l’exception du mode Vertical Uniquement) ; l’amplitude du signal est trop grande ou trop petite (à l’exception du mode Horizontal Uniquement). Changement de niveau de déclenchement idéal Lorsque vous appuyez sur le bouton CALIBRAGE AUTO, l’oscilloscope ajuste les commandes de façon à obtenir un affichage exploitable du signal d’entrée. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 101 Référence Fonction Réglage Mode d’acquisition Normale Format d’affichage Y(t) Afficher persist. Désact. HORIZONTAL POSITION Ajusté Vue horizontale Principale RUN/STOP RUN SEC/DIV Ajusté Couplage du déclenchement CC Inhibition du déclenchement Minimum Niveau de déclenchement Ajusté Mode de déclenchement Front Bande passante verticale Totale Limite de bande passante verticale Désact. Couplage vertical CC Inversion verticale Désact. VOLTS/DIV Ajusté Les modifications suivantes apportées à la configuration de l’oscilloscope désactivent la fonction d’ajustement automatique (Autorange) : VOLTS/DIV désactive la fonction d’ajustement automatique vertical. SEC/DIV désactive la fonction d’ajustement automatique horizontal. Afficher ou supprimer un signal de voie Réglages de déclenchement Mode d’acquisition SEQ. UNIQUE Rappel d’une configuration Mode d’affichage XY Persistance 102 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence La fonction d’ajustement automatique (Autorange) est généralement plus utile que le réglage automatique (Autoset) dans les situations suivantes : Analyse d’un signal qui change de manière dynamique. Comparaison rapide d’une séquence de plusieurs signaux sans ajustement de l’oscilloscope. Cela est très utile si vous devez utiliser deux sondes à la fois ou utiliser une sonde dans une main et tenir un autre objet dans l’autre. Contrôle des réglages ajustés automatiquement par l’oscilloscope. Si vos signaux varient en fréquence, mais ont des amplitudes similaires, vous pouvez utiliser l’option Horizontal Uniquement. L’oscilloscope ajustera les réglages horizontaux sans modifier les réglages verticaux. De cette façon, vous pouvez évaluer visuellement l’amplitude du signal sans vous préoccuper de modifier l’échelle verticale. L’option Vertical Uniquement fonctionne de la même manière, en ajustant les paramètres verticaux sans modifier les réglages horizontaux. Réglage automatique (Autoset) Lorsque vous appuyez sur le bouton AUTOSET, l’oscilloscope identifie le type de signal et ajuste les commandes de façon à obtenir un affichage du signal d’entrée exploitable. Fonction Réglage Mode d’acquisition Ajusté en mode Normale ou Détect Créte Curseurs Désact. Mode d’affichage Défini sur Y(t) Type d’affichage Défini sur Points pour un signal vidéo, sur Vecteurs pour un spectre FFT ; inchangé sinon HORIZONTAL POSITION Ajusté SEC/DIV Ajusté Couplage du déclenchement Ajusté sur CC, rejet bruit ou rejet HF Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 103 Référence Fonction Réglage Inhibition du déclenchement Minimum Niveau de déclenchement Niveau à 50 % Mode de déclenchement Auto Source de déclenchement Ajusté ; se reporter aux informations qui suivent ce tableau ; impossible d’utiliser la fonction de réglage automatique (Autoset) sur le signal EXTERNE Pente de déclenchement Ajusté Type de déclenchement Front ou vidéo Polarité de déclenchement vidéo Normal Synch. de déclenchement vidéo Ajusté Standard de déclenchement vidéo Ajusté Bande passante verticale Totale Couplage vertical CC (si Masse a été sélectionnée précédemment) ; CA pour un signal vidéo ; inchangé sinon VOLTS/DIV Ajusté La fonction de réglage automatique (Autoset) inspecte toutes les voies à la recherche de signaux et affiche les signaux correspondants. Le réglage automatique (Autoset) permet également de déterminer la source de déclenchement en fonction des conditions suivantes : Si plusieurs voies ont des signaux, l’oscilloscope affiche la voie avec la fréquence du signal la plus faible. Si aucun signal n’est trouvé, l’oscilloscope affiche alors la voie avec le plus petit numéro lorsque le réglage automatique (Autoset) a été choisi. Si aucun signal n’est trouvé et qu’aucune voie ne s’affiche, l’oscilloscope affiche et utilise la voie 1. 104 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Lorsque vous utilisez la fonction de réglage automatique (Autoset) et que l’oscilloscope ne peut pas déterminer le type de signal, il ajuste alors les échelles horizontale et verticale, puis prend les mesures automatiques Moyenne et C-C. Le réglage automatique (Autoset) est généralement plus utile que l’ajustement automatique (Autorange) dans les situations suivantes : dépannage d’un signal stable ; affichage automatique des mesures de votre signal ; changement aisé de la présentation du signal. Par exemple, affichage d’un seul cycle du signal ou du front montant du signal ; affichage de signaux vidéo ou FFT. Onde sinusoïdale Lorsque vous utilisez la fonction de réglage automatique (Autoset) et que l’oscilloscope détermine que le signal est semblable à une onde sinusoïdale, il affiche alors les options suivantes : Onde sinusoïdale Détails Sinusoïdale multicycles Affiche plusieurs cycles avec les échelles verticale et horizontale adéquates ; l’oscilloscope affiche alors les mesures automatiques de la valeur efficace du cycle, de la fréquence, de la période et de la valeur crête à crête. Sinusoïdale à simple cycle Règle l’échelle horizontale afin d’afficher environ un cycle du signal ; l’oscilloscope affiche alors les mesures automatiques de la moyenne et de la valeur crête à crête FFT Convertit le signal d’entrée temporel en ses composantes de fréquence et affiche le résultat sous la forme d’un graphe de la fréquence par rapport à l’amplitude (spectre) ; comme il s’agit d’un calcul mathématique, reportez-vous au chapitre Fonctions mathématiques FFT pour plus d’informations. Annuler Config. auto. Annule la configuration actuelle de l’oscilloscope et rétablit la précédente Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 105 Référence Onde ou impulsion carrée Lorsque vous utilisez la fonction de réglage automatique (Autoset) et que l’oscilloscope détermine que le signal est semblable à une onde ou une impulsion carrée, il affiche les options suivantes : Options onde Détails Carrée multicycles Affiche plusieurs cycles avec les échelles verticale et horizontale adéquates ; l’oscilloscope affiche alors les mesures automatiques de la valeur C-C, Moyenne, Période et Fréquence. Carrée à simple cycle Règle l’échelle horizontale afin d’afficher environ un cycle du signal ; l’oscilloscope affiche alors les mesures automatiques Min, Max, Moyenne et Largeur positive Front montant Affiche le front et les mesures automatiques du temps de montée et de la valeur crête à crête Front descendant Affiche le front et les mesures automatiques du temps de descente et de la valeur crête à crête Annuler Config. auto. Annule la configuration actuelle de l’oscilloscope et rétablit la précédente Signal vidéo Lorsque vous utilisez la fonction de réglage automatique (Autoset) et que l’oscilloscope détermine que le signal est un signal vidéo, il affiche alors les options suivantes : Options du signal vidéo Détails Trames ►Ttes trames Affiche plusieurs trames et l’oscilloscope se déclenche sur n’importe quelle trame Lignes ►Ttes lignes Affiche une ligne entière comprenant des parties de la ligne précédente et de la ligne suivante ; l’oscilloscope se déclenche sur n’importe quelle ligne 106 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Options du signal vidéo Détails Lignes ►Numéro Affiche une ligne entière comprenant des parties de la ligne précédente et de la ligne suivante ; utilisez le bouton multifonctionnel pour sélectionner un numéro de ligne spécifique que l’oscilloscope utilisera comme déclenchement Trames impaires Affiche plusieurs trames et l’oscilloscope se déclenche uniquement sur les trames impaires Trames paires Affiche plusieurs trames et l’oscilloscope se déclenche uniquement sur les trames paires Annuler Config. auto. Annule la configuration actuelle de l’oscilloscope et rétablit la précédente REMARQUE. La fonction de réglage vidéo automatique définit l’option Type d’affichage sur le Mode point. Curseurs Appuyez sur le bouton CURSEURS pour afficher les curseurs de mesure et le menu Curseurs, puis utilisez le bouton multifonctionnel pour modifier la position d’un curseur. Options Réglages Commentaires Type 1 Temps, Amplitude, Désact. Permet de sélectionner et d’afficher les curseurs de mesure ; Temps mesure le temps, la fréquence et l’amplitude ; Amplitude mesure l’amplitude, comme le courant ou la tension Source CH1, CH2, CH3 2, CH4 2, MATH, REFA, REFB, REFC 2, REFD 2 Permet de sélectionner le signal sur lequel prendre des mesures à l’aide du curseur Les mesures du curseur apparaissent dans l’affichage Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 107 Référence Options Réglages Commentaires Δ Affiche la valeur absolue de la différence (delta) entre les curseurs Curseur 1 Curseur 2 Affiche l’emplacement du curseur sélectionné (le temps est référencé au point de déclenchement et l’amplitude au niveau de référence) 1 Pour une source mathématique FFT, mesure la fréquence et l’amplitude 2 Disponible uniquement sur les oscilloscopes à 4 voies. Les valeurs delta (Δ) varient selon le type de curseur : Les curseurs de temps affichent Δt, 1/ Δt et ΔV (ou ΔI, ΔVV, etc.). Les curseurs d’amplitude (source mathématique FFT) affichent ΔV, ΔI, ΔVV, etc. Les curseurs de fréquence (source mathématique FFT) affichent 1/ΔHz et ΔdB. REMARQUE. L’oscilloscope affiche obligatoirement un signal pour les curseurs et les affichages de curseur qui doivent s’afficher. REMARQUE. L’oscilloscope affiche les valeurs de temps et d’amplitude pour chaque signal lorsque vous utilisez les curseurs de temps. Informations importantes Mouvement des curseurs. Utilisez le bouton multifonctionnel pour déplacer les curseurs 1 ou 2. Vous pouvez déplacer les curseurs uniquement si le menu Curseurs est affiché. Le curseur actif est représenté par une ligne continue. 108 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Amplitude, curseurs Curseurs de temps Configuration par défaut Le bouton CONF. PAR D. vous permet de rappeler la plupart des options et des réglages d’usine, mais pas tous. L’annexe D répertorie les paramètres par défaut qui seront rappelés. Affichage Appuyez sur le bouton AFFICHAGE pour choisir la présentation des signaux et modifier l’apparence de tout l’affichage. Options Réglages Commentaires Type Vecteurs, Points Le mode Vecteurs permet de remplir l’espace entre les points d’échantillonnage adjacents dans l’affichage Le mode Points permet d’afficher uniquement les points d’échantillonnage Persist. Aucune, 1 s, 2 s, 5 s, Infinie Permet de définir la durée pendant laquelle chaque point d’échantillonnage demeure affiché Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 109 Référence Options Réglages Commentaires Mode Y(t), XY Le mode Y(t) permet d’afficher la tension verticale par rapport au temps (échelle horizontale) Le mode XY permet d’afficher un point à chaque acquisition d’un échantillon sur la voie 1 et la voie 2 La tension ou le courant sur la voie 1 détermine la coordonnée X du point (horizontale) et la tension ou le courant sur la voie 2 détermine la coordonnée Y (verticale) Contraste 1 Permet de faciliter la distinction entre un signal de voie et une persistance 1 Utilisez le bouton multifonctionnel pour changer le réglage. En fonction de leur type, les signaux vont s’afficher dans trois styles différents : uniforme, estompé et en pointillé. 1. Un signal uniforme indique un affichage de signal de voie (active). Une fois l’acquisition interrompue, le signal reste uniforme si aucun réglage rendant la précision de l’affichage aléatoire n’a été modifié. Vous êtes autorisé à modifier les réglages horizontaux et verticaux une fois les acquisitions interrompues. 2. Pour les modèles TDS1000B (écran monochrome), les signaux de référence ou les signaux persistants apparaissent comme estompés. 110 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Pour les modèles TDS2000B (écran couleur), les signaux de référence s’affichent en blanc et les signaux persistants s’affichent dans la même couleur que le signal principal, mais avec moins d’intensité. 3. Une ligne en pointillés indique que l’affichage du signal ne correspond plus aux réglages. Cela se produit lorsque vous interrompez l’acquisition et que vous modifiez le paramètre d’un réglage que l’oscilloscope ne peut pas appliquer au signal affiché. Par exemple, si vous modifiez les réglages du déclenchement sur une acquisition interrompue, vous obtiendrez un signal en pointillés. Informations importantes Persistance. L’oscilloscope affiche les données de persistance avec moins d’intensité que les données de signal actives. Si le mode Persistance est défini sur Infinie, les points d’enregistrement s’accumulent jusqu’à la modification du réglage. Option Commentaires Aucune Efface les signaux par défaut ou les anciens signaux chaque fois que de nouveaux signaux s’affichent Limite de temps Affiche les nouveaux signaux avec une intensité normale et les anciens signaux avec une intensité moins importante ; efface les anciens signaux lorsque la limite de temps est atteinte Infinie Les anciens signaux deviennent moins brillants, mais restent toujours visibles ; utilisez la persistance infinie pour rechercher les événements rares et mesurer le bruit crête-à-crête à long terme Mode XY. Le mode d’affichage XY vous permet d’analyser les différences de phase, telles que celles représentées par les figures de Lissajous. Ce mode trace le signal de tension de la voie 1 en fonction de celle de la voie 2, la voie 1 représentant l’axe horizontal et la voie 2 l’axe vertical. L’oscilloscope utilise le mode d’acquisition Normale sans déclenchement et affiche les données sous forme de points. La fréquence d’échantillonnage est établie à 1 M éch./s. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 111 Référence REMARQUE. L’oscilloscope peut capturer un signal en mode Y(t) normal à n’importe quelle fréquence d’échantillonnage. Vous pouvez afficher le même signal en mode XY. Pour ce faire, interrompez l’acquisition et modifiez le mode d’affichage sur XY. Dans le mode XY, les réglages fonctionnent comme suit : Le réglage des boutons VOLTS/DIV et VERTICAL POSITION de la voie 1 définissent l’échelle et la position horizontales. Le réglage des boutons VOLTS/DIV et VERTICAL POSITION de la voie 2 définissent l’échelle et la position verticales. Les fonctions suivantes ne fonctionnent pas en mode d’affichage XY : Réglage automatique (Autoset ; rétablit le mode d’affichage sur Y(t)) Calibrage Auto Mesures automatiques Curseurs Signaux de référence ou calculés SAUV./RAP ► Sauveg. tot. Réglages de la base de temps Réglages du déclenchement Aide Appuyez sur le bouton AIDE pour afficher le menu d’aide. Les rubriques traitent toutes les options et les commandes de menu de l’oscilloscope. (Voir page x, Système d’aide.) Horizontal Les réglages horizontaux vous permettent de configurer deux affichages pour un même signal, chacun ayant sa propre échelle horizontale et sa propre position horizontale. La position horizontale illustre le temps 112 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence représenté au centre de l’écran, en utilisant le temps de déclenchement comme point de départ. Lorsque vous modifiez l’échelle horizontale, le signal se développe ou se réduit autour du centre de l’écran. Options Commentaires Principale Le réglage de la base de temps principale sert à afficher le signal Zone retardée Cette zone est définie par deux curseurs Ces curseurs permettent d’ajuster la Zone retardée à l’aide des commandes HORIZONTAL POSITION et SEC/DIV Base de temps retardée Permet de modifier l’affichage pour visualiser le segment du signal (étendu en fonction de la largeur de l’écran) dans la zone retardée Définir validat. de déclenchem. Affiche la valeur d’inhibition ; appuyez sur le bouton d’option et utilisez le bouton multifonctionnel pour effectuer le réglage REMARQUE. Si vous souhaitez afficher un signal en entier ou afficher une partie agrandie de celui-ci, appuyez sur les boutons d’options horizontaux. Vous pouvez suivre la position horizontale courante en secondes en haut à droite de l’écran, où elle est affichée. L’affichage de la lettre M signale la Base de temps principale, et la lettre W la Base de temps retardée. L’oscilloscope affiche également la position horizontale sous la forme d’une icône de flèche placée en haut du réticule. Molettes et boutons Molette HORIZONTAL POSITION. Permet de contrôler la position du déclenchement par rapport au centre de l’écran. Vous pouvez définir le point de déclenchement à gauche ou à droite du centre de l’écran. Le nombre maximal de divisions à gauche varie en fonction du réglage (base de temps) de l’échelle horizontale. Pour la plupart des échelles, le maximum s’élève au moins à 100 divisions. On qualifie de Balayage retardé le fait de placer le point de déclenchement en dehors de l’écran, du côté gauche. Bouton REGLER SUR 0. Permet de régler la position horizontale sur zéro. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 113 Référence Molette SEC/DIV (échelle horizontale). Permet de modifier l’échelle de temps horizontale de façon à agrandir ou réduire le signal. Informations importantes SEC/DIV. Si l’acquisition d’un signal est interrompue (à l’aide du bouton RUN/STOP ou SEQ. UNIQUE), la commande SEC/DIV agrandit ou réduit le signal. Utilisez cette fonction pour agrandir un détail du signal. Affichage en mode Balayage (mode Défilement). Si la commande SEC/DIV est définie sur 100 ms/div ou plus lent et que le mode de déclenchement est défini sur Auto, l’oscilloscope passe en mode d’acquisition Balayage. Dans ce mode, les mises à jour d’affichage des signaux s’effectuent de gauche à droite. Il n’y a ni déclenchement, ni réglage de la position horizontale des signaux lorsque le mode Balayage est actif. (Voir page 100, Affichage en mode Balayage.) Zone retardée. Utilisez l’option Zone retardée pour définir le segment d’un signal et ainsi afficher plus de détails (zoom). La Base de temps retardée ne peut pas avoir un réglage plus lent que celui de la Base de temps principale. Les barres verticales définissent la Zone retardée. Affichage de la Base de temps principale Affichage de la Zone retardée Base de temps retardée. Permet d’étendre la Zone retardée de façon à occuper tout l’écran. Permet de basculer entre deux bases de temps. REMARQUE. Si vous basculez entre les affichages de type Base de temps principale, Zone retardée et Base de temps retardée, l’oscilloscope efface alors tous les signaux enregistrés à l’écran via la persistance. La persistance est annulée par les modifications dans le menu Horizontal. 114 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Inhibition. Utilisez l’inhibition pour vous permettre de stabiliser l’affichage de signaux complexes. (Voir page 135, Inhibition.) Fonctions mathématiques Appuyez sur le bouton MATH MENU pour afficher les opérations mathématiques du signal. Appuyez à nouveau sur le bouton MATH MENU pour effacer les signaux calculés. (Voir page 140, Réglages verticaux.) Options Commentaires +, -, ×, FFT Opérations mathématiques ; voir le tableau suivant Sources Sources utilisées pour les opérations ; voir le tableau suivant Position Utilisez le bouton multifonctionnel pour régler la position verticale du signal calculé résultant Echelle verticale Utilisez le bouton multifonctionnel pour régler l’échelle verticale du signal calculé résultant Le menu Math contient des options Sources pour chaque opération. Opération option Sources Commentaires CH1 + CH2 Les voies 1 et 2 sont additionnées + (addition) CH3 + CH4 1 Les voies 3 et 4 sont additionnées CH1 - CH2 Le signal de la voie 2 est soustrait de celui de la voie 1 CH2 - CH1 Le signal de la voie 1 est soustrait de celui de la voie 2 CH3 - CH4 1 Le signal de la voie 4 est soustrait de celui de la voie 3 - (soustraction) CH4 - CH3 1 Le signal de la voie 3 est soustrait de celui de la voie 4 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 115 Référence Opération option Sources Commentaires CH1×CH2 Les voies 1 et 2 sont multipliées × (multiplication) CH3×CH4 1 Les voies 3 et 4 sont multipliées FFT (Voir page 69.) 1 Disponible uniquement sur les oscilloscopes à 4 voies. Informations importantes Unités des signaux. La combinaison des unités des signaux sources détermine les unités résultantes du signal calculé. Unité du signal Unité du signal Opération Unité calculée résultante V V + ou - V A A + ou - A V A + ou - ? V V × VV A A × AA V A × VA Mesures Appuyez sur le bouton MESURES pour accéder aux mesures automatiques. Il existe onze types de mesures disponibles. Vous pouvez en afficher au maximum cinq à la fois. Appuyez sur le bouton d’option supérieur pour afficher le menu Mesure 1. Vous pouvez sélectionner la voie sur laquelle prendre la mesure dans l’option Source. Vous pouvez sélectionner le type de mesure dans l’option Type. Appuyez sur le bouton d’option Retour pour revenir au menu MESURES et afficher les mesures sélectionnées. 116 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Informations importantes Prise de mesures. Vous pouvez afficher au maximum cinq mesures automatiques à la fois. La voie du signal doit être activée (affichée) pour prendre les mesures. Il est impossible de prendre desmesures automatiques sur les signaux de référence ou lorsque le mode Balayage ou XY est activé. Les mesures sont mises à jour environ deux fois par seconde. Type de mesure Définition Fréq. Permet de calculer la fréquence du signal en mesurant le premier cycle Période Permet de calculer la durée du premier cycle Moyenne Permet de calculer la moyenne arithmétique de l’amplitude sur la totalité de l’enregistrement C-C Permet de calculer la différence absolue entre les crêtes maximales et minimales de la totalité du signal Efficace Permet de calculer une mesure efficace correcte du premier cycle complet du signal Min Permet d’examiner les 2 500 points composant l’enregistrement du signal et d’en afficher la valeur minimale Max Permet d’examiner les 2 500 points composant l’enregistrement du signal et d’en afficher la valeur maximale Tps montée Permet de mesurer le temps entre 10 % et 90 % de l’avancement du premier front montant du signal Tps descente Permet de mesurer le temps entre 90 % et 10 % de l’avancement du premier front descendant du signal Largeur pos. Permet de mesurer le temps écoulé entre le premier front montant et le front descendant suivant à 50 % de l’avancement du signal Largeur nég. Permet de mesurer le temps écoulé entre le premier front descendant et le front montant suivant à 50 % de l’avancement du signal Aucune Ne prend aucune mesure Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 117 Référence Imprimer Lorsque l’option Sauveg. tot. ► Touche PRINT est définie sur Imprime, vous pouvez appuyer sur la touche PRINT pour envoyer l’image d’écran à une imprimante. Vous pouvez configurer l’oscilloscope pour envoyer une image d’écran à votre imprimante via le menu UTILITAIRE ► Options ► Configuration imprimante. Option Réglage Commentaires Economie d’encre Act., Désact. Imprime l’image d’écran sur fond blanc lorsque vous sélectionnez Act. Présentation 1 Portrait, Paysage Orientation de la sortie papier de l’imprimante Suspendre impression Interrompt l’envoi de l’image d’écran à l’imprimante Format papier 2 Par défaut, L, 2L, Hagaki Postcard, Card Size, 10x15 cm, 4"x6", 8"x10", Letter, 11"x17", A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, Roll 89 mm (L), Roll 127 mm (2L), Roll 100 mm (4"), Roll 210 mm (A4) Affiche les réglages disponibles pour votre imprimante compatible PictBridge Format image 2 Par défaut, 2,5"x3,25", L (3,5"x5"), 4"x6", 2L (5"x7"), 8"x10", 4L (7"x10"), E, Card, Hagaki card, 6x8 cm, 7x10 cm, 9x13 cm, 10x15 cm, 13x18 cm, 15x21 cm, 18x24 cm, A4, Letter Type papier 2 Par défaut, Normal, Photo, Photo rapide Qualité impr. 2 Par défaut, Normale, Brouillon, Précision Date impr. 2 Par défaut, Désactivé, Activé ID impr. 2 Par défaut, Désactivé, Activé 1 ll se peut que l’imprimante annule votre sélection pour un résultat optimal. 2 Si votre sélection n’est pas prise en charge par l’imprimante, l’oscilloscope utilise les paramètres par défaut. 118 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence La fonction alternative de la touche PRINT consiste à sauvegarder des données vers un lecteur flash USB. (Voir page 79, Port du lecteur flash USB et port périphérique.) L’oscilloscope peut imprimer sur n’importe quelle imprimante compatible PictBridge. Reportez-vous à la documentation produit de votre imprimante pour déterminer si l’imprimante est compatible PictBridge. Test de sonde L’assistant Test de sonde vous permet de vérifier rapidement le bon fonctionnement de votre sonde de tension. (Voir page 5, Assistant Test de sonde de tension.) Menu Réf Le menu Réf peut activer ou désactiver l’affichage des signaux de mémoire de référence. Les signaux sont stockés dans la mémoire non volatile de l’oscilloscope et affichent les désignations suivantes : RéfA, RéfB, RéfC et RéfD (RéfC et RéfD sont disponibles uniquement sur les oscilloscopes à 4 voies). Pour afficher (rappeler) ou masquer un signal de référence, suivez les étapes ci-dessous : 1. Appuyez sur le bouton MENU REF du panneau avant. 2. Appuyez sur le bouton d’option Option Réf pour sélectionner un signal de référence à afficher ou à masquer. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 119 Référence Les signaux de référence ont les caractéristiques suivantes : sur les modèles couleur, les signaux de référence s’affichent en blanc ; sur les modèles monochrome, les signaux de référence s’affichent avec une intensité moins importante que celle des signaux de voie actifs ; deux signaux de référence peuvent être affichés en même temps ; les échelles verticales et horizontales s’affichent au bas de l’écran ; les signaux de référence ne peuvent pas faire l’objet de zoom ou de panorama. Vous pouvez afficher un ou deux signaux de référence en même temps que les signaux de voie actifs. Si vous affichez deux signaux de référence, vous devez masquer un signal avant de pouvoir afficher un autre signal. Reportez-vous à la section Mise en mémoire pour obtenir des informations sur l’enregistrement de signaux de référence. (Voir page 124, Mise en mémoire.) Sauvegarder/Rappeler Appuyez sur le bouton SAUV./RAP pour sauvegarder les configurations, les images d’écran ou les signaux de l’oscilloscope, ou pour rappeler les configurations ou les signaux de l’appareil. Le menu Sauv./Rap comporte plusieurs sous-menus auxquels vous pouvez accéder via une option Action. Chaque option Action affiche un menu qui permet de configurer plus précisément la fonction de sauvegarde ou de rappel. Options Action Commentaires Sauveg. tot. Contient l’option permettant de configurer la touche PRINT pour envoyer les données vers une imprimante ou de sauvegarder les données sur un lecteur flash USB Sauvegarde image Sauvegarde une image d’écran dans un fichier au format spécifié 120 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Options Action Commentaires Sauvegarde config. Sauvegarde les réglages courants de l’oscilloscope vers un fichier dans un dossier spécifié ou dans la mémoire de réglage non volatile Mise en mémoire Sauvegarde le signal spécifié dans un fichier ou la mémoire de référence Rappel config. Rappelle un fichier de configuration d’oscilloscope d’un lecteur flash USB ou d’un emplacement dans la mémoire de réglage non volatile Rappel Signal Rappelle un fichier de signal depuis le lecteur flash USB vers la mémoire de référence Sauveg. tot. L’action Sauveg. tot. configure la touche PRINT pour sauvegarder des données sur un lecteur flash USB ou envoyer des données vers une imprimante. Options Réglages ou sous-menus Commentaires Sauvegarde tout 1 (Voir page 85.) Sauvegarde image 1 (Voir page 87.) Touche PRINT Imprime (Voir page 95.) Répertorie le contenu du dossier courant du lecteur flash USB Modif. Dossier Nouv. Dossier (Voir page 82, Conventions de gestion des fichiers.) (Voir page 139, Utilitaires Fichiers pour le lecteur flash USB.) Sélection Dossier Retour Revient au menu Sauveg. tot. A propos de Sauvegarde totale Permet d’afficher la rubrique d’aide 1 Un voyant LED à côté de la touche PRINT s’allume pour indiquer la fonction alternative de sauvegarde qui envoie des données à un lecteur flash USB. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 121 Référence Sauvegarde image L’action Sauvegarde image enregistre une image d’écran dans un fichier au format spécifié. Options Réglages ou sous-menus Commentaires Format de fichier BMP, PCX, TIFF, RLE, EPSIMAGE, JPEG Définit le format du fichier graphique de l’image à l’écran A propos de Sauvegarde Images Permet d’afficher la rubrique d’aide Répertorie le contenu du dossier courant du lecteur flash USB et affiche les options du dossier Modif. Dossier Nouv. Dossier (Voir page 82, Conventions de gestion des fichiers.) (Voir page 139, Utilitaires Fichiers pour le lecteur flash USB.) Présentation 1, Portrait, Paysage Permet de sélectionner une présentation d’image de type portrait ou paysage Sélection Dossier Economie d’encre 1, Act., Désact. Active ou désactive le mode Economie d’encre Mise en mémoire nom du fichier (par ex. TEK0000.TIF) Sauvegarde l’image d’écran dans le fichier (dont le nom est généré automatiquement) dans le dossier courant du lecteur flash USB 1 (Voir page 118, Imprimer.) Lorsque l’option de la touche PRINT est réglée sur Sauvegarde image, l’oscilloscope sauvegarde les images d’écran sur un lecteur flash USB lorsque vous appuyez sur le bouton ENREGISTRER. (Voir page 87, Sauvegarde image.) 122 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Sauvegarde config. L’action Sauvegarde config. enregistre les réglages actuels de l’oscilloscope dans un fichier TEKnnnn.SET, stocké dans le dossier indiqué ou dans la mémoire de réglage non volatile. Un fichier de configuration contient une chaîne de texte ASCII indiquant les réglages de l’oscilloscope. Options Réglages ou sous-menus Commentaires Config Sauvegarde les réglages actuels de l’oscilloscope dans un emplacement de la mémoire de réglage non volatile Sauv. vers Fichier Sauvegarde les réglages actuels de l’oscilloscope dans un fichier sur le lecteur flash USB Mém. Conf. 1 à 10 Indique l’emplacement de mémoire de réglage non volatile à utiliser pour la sauvegarde Répertorie le contenu du dossier courant du lecteur flash USB Modif. Dossier Sélection Dossier Nouv. Dossier (Voir page 82, Conventions de gestion des fichiers.) (Voir page 139, Utilitaires Fichiers pour le lecteur flash USB.) Mise en mémoire nom du fichier (par ex. TEK0000.SET) Sauvegarde les réglages dans le fichier (dont le nom est généré automatiquement) dans le dossier courant du lecteur flash USB Lorsque l’option de la touche PRINT est réglée sur Sauvegarde tout, l’oscilloscope sauvegarde les fichiers de configuration sur un lecteur flash USB lorsque vous appuyez sur le bouton ENREGISTRER. (Voir page 85, Sauvegarde tout.) Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 123 Référence Mise en mémoire L’action Mise en mémoire sauvegarde le signal défini dans un fichier TEKnnnn.CSV ou dans la mémoire de référence. L’oscilloscope sauvegarde les données de signal dans des fichiers au format CSV (valeurs séparées par des virgules), qui correspondent à des chaînes de texte ASCII indiquant le temps (par rapport au déclenchement) et les valeurs d’amplitude de chacun des 2 500 points de données de signal. Vous pouvez importer les fichiers .CSV dans un grand nombre de tableurs et d’applications d’analyse mathématique. Options Réglages ou sous-menus Commentaires Fichier Indique que les données du signal source doivent être sauvegardées dans un fichier sur un lecteur flash USB Sauv. vers Réf Indique que les données du signal source doivent être sauvegardées dans la mémoire de référence Source 1 CH(x), Réf(x), MATH Indique le signal source à sauvegarder Vers Réf(x) Indique l’emplacement de mémoire de référence dans lequel le signal source doit être sauvegardé Répertorie le contenu du dossier courant du lecteur flash USB Modif. Dossier Sélection Dossier Nouv. Dossier (Voir page 82, Conventions de gestion des fichiers.) (Voir page 139, Utilitaires Fichiers pour le lecteur flash USB.) Mise en mémoire nom du fichier (par ex. TEK0000.CSV) Sauvegarde les données de signal dans le fichier (dont le nom est généré automatiquement) dans le dossier courant du lecteur flash USB 1 Un signal doit être affiché pour être enregistré en tant que signal de référence. 124 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Rappel config. L’action Rappel config. rappelle un fichier de configuration d’oscilloscope d’un lecteur flash USB ou d’un emplacement dans la mémoire de réglage non volatile. Options Réglages ou sous-menus Commentaires Config Indique que la configuration doit être rappelée à partir de la mémoire non volatile. Rappel de Fichier Indique qu’un fichier de configuration doit être rappelé à partir du lecteur flash USB Config 1 à 10 Indique à partir de quel emplacement de mémoire de réglage non volatile la configuration doit être rappelée Répertorie le contenu du dossier courant du lecteur flash USB où sélectionner un fichier Sélection fichier Modif. Dossier (Voir page 82, Conventions de gestion des fichiers.) (Voir page 139, Utilitaires Fichiers pour le lecteur flash USB.) Rappelle les réglages de l’emplacement de mémoire non volatile spécifié Rappel nom du fichier (par ex. TEK0000.SET) Rappelle les réglages de l’oscilloscope à partir du fichier du lecteur flash USB spécifié Rappel Signal L’action Rappel Signal rappelle un fichier de signal d’un lecteur flash USB et le charge dans un emplacement de la mémoire de référence. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 125 Référence Options Réglages ou sous-menus Commentaires Vers Réf(x) Indique l’emplacement de mémoire de référence où charger le signal Du fichier Rappelle le fichier à partir du lecteur flash USB Répertorie le contenu du dossier courant du lecteur flash USB et affiche l’option de dossier suivante Modif. Dossier (Voir page 82, Conventions de gestion des fichiers.) (Voir page 139, Utilitaires Fichiers pour le lecteur flash USB.) Sélection fichier Vers Indique l’emplacement de mémoire de référence où rappeler le signal Rappel nom du fichier (par ex. TEK0000.CSV) Charge le signal depuis le fichier spécifié dans l’emplacement de mémoire de référence et affiche le signal Informations importantes Sauvegarde et rappel de configurations. La totalité de la configuration est enregistrée dans une mémoire non volatile. Lorsque vous rappelez cette configuration, l’oscilloscope passe alors en mode actif au moment de l’enregistrement de la configuration. Le réglage courant est sauvegardé si vous patientez trois secondes après la dernière modification avant d’éteindre l’oscilloscope. A la prochaine mise sous tension, l’oscilloscope rappelle ce réglage. Rappel de la configuration par défaut. Le bouton CONF. PAR D. vous permet d’obtenir une configuration familière lors de l’initialisation de l’oscilloscope. Pour connaître les paramètres d’options et de commandes qui sont rappelés par l’oscilloscope lorsque vous appuyez sur ce bouton, reportez-vous à l’Annexe D : Configuration par défaut. 126 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Sauvegarde et rappel des signaux. L’oscilloscope doit pouvoir afficher tous les signaux que vous souhaitez afficher. Les oscilloscopes dotés de deux voies peuvent enregistrer deux signaux de référence dans une mémoire non volatile interne. Les oscilloscopes dotés de quatre voies peuvent en enregistrer quatre, mais en afficher uniquement deux à la fois. L’oscilloscope peut afficher à la fois les signaux de référence et les acquisitions de signal de voie. Vous ne pouvez pas régler les signaux de référence ; en revanche l’oscilloscope affiche les échelles horizontale et verticale en bas de l’écran. Commandes de déclenchement Vous pouvez définir le déclenchement par l’intermédiaire du menu Déclenchement et des commandes du panneau avant. Types de déclenchement Il existe trois types de déclenchement : sur front, vidéo et sur largeur d’impulsion. Un ensemble d’options s’affiche pour chaque type de déclenchement : Option Détails Front (par défaut) Permet de déclencher l’oscilloscope sur front montant ou descendant du signal d’entrée lorsqu’il traverse le niveau de déclenchement (seuil). Vidéo Affiche les signaux vidéo composites standard NTSC ou PAL/SECAM ; vous pouvez déclencher sur des trames ou des lignes de signaux vidéo. (Voir page 131, Déclenchement vidéo.) Impulsion Permet d’effectuer des déclenchements sur des impulsions aberrantes. (Voir page 132, Déclenchement sur largeur d’impulsion.) Déclenchement sur front Utilisez le Déclenchement sur front pour procéder à un déclenchement sur le front montant ou descendant du signal d’entrée de l’oscilloscope, au seuil de déclenchement. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 127 Référence Options Réglages Commentaires Front Lorsque l’option Front est sélectionnée, le front montant ou descendant du signal d’entrée est utilisé pour le déclenchement. Source CH1, CH2, CH3 1, CH4 1 , Ext., Ext/5, Secteur Sélectionnez la source d’entrée utilisée comme signal de déclenchement (Voir page 129.) Pente Montante, Descend. Sélectionnez le déclenchement sur le front montant ou descendant du signal. Mode Auto, Normal Sélectionnez le type de déclenchement (Voir page 128.) Couplage CA, CC, rejet bruit, rejet HF, rejet BF Permet de sélectionner les composantes du signal de déclenchement qui s’appliquent au circuit de déclenchement (Voir page 130.) 1 Disponible uniquement sur les oscilloscopes à 4 voies. Mesure de la fréquence du déclenchement L’oscilloscope mesure la cadence à laquelle se produisent les événements déclenchables pour déterminer la fréquence du déclenchement, puis il affiche cette dernière dans le coin inférieur droit de l’écran. REMARQUE. La mesure de la fréquence du déclenchement affiche la fréquence des événements que l’oscilloscope pourrait considérer comme un déclenchement ; elle peut être inférieure à la fréquence du signal d’entrée en mode de déclenchement sur largeur d’impulsion. Informations importantes Options des modes. Le mode Auto (par défaut) force l’oscilloscope à se déclencher lorsqu’il ne détecte pas d’événement de déclenchement 128 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence pendant une certaine période, définie dans le réglage SEC/DIV. Ce mode est utilisable dans bon nombre de situations, telles que le contrôle de la sortie d’une alimentation. Utilisez le mode Auto pour laisser l’acquisition s’effectuer librement en l’absence de déclenchement valide. Ce mode permet d’effectuer un balayage de signal sans déclenchement avec un réglage de la base de temps à 100 ms/div ou plus lent. Le mode Normal permet de mettre à jour les signaux affichés uniquement lorsque l’oscilloscope détecte un déclenchement valide. L’oscilloscope affiche les anciens signaux jusqu’à ce qu’il les remplace par de nouveaux. Utilisez ce mode lorsque vous ne souhaitez visualiser que les signaux déclenchés. Lorsque vous utilisez ce mode, l’oscilloscope affiche un signal uniquement après le premier déclenchement. Pour effectuer une acquisition de type séquence unique, appuyez sur le bouton SEQ. UNIQUE. Options de source. Option de source Détails CH1, CH2, CH3 1, CH4 1 Cette option permet de déclencher sur une voie, que le signal soit affiché ou non Ext. Cette option n’affiche pas le signal de déclenchement ; l’option Ext. utilise le signal connecté au connecteur BNC EXTERNE du panneau avant et autorise une plage de niveaux de déclenchement s’étendant de +1,6 V à -1,6 V. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 129 Référence Option de source Détails Ext/5 Identique à l’option Ext., mais divise le signal par cinq et autorise une plage de niveaux de déclenchement allant de +8 V à -8 V, ce qui permet d’étendre la plage de niveaux de déclenchement. Secteur 2 Utilise un signal dérivé de la ligne d’alimentation comme source de déclenchement ; le couplage de déclenchement est défini sur CC et le niveau de déclenchement sur 0 volt. Vous pouvez utiliser l’option Secteur lorsque vous devez analyser des signaux associés à la fréquence de la ligne d’alimentation, tels que les dispositifs d’éclairage et les systèmes d’alimentation ; l’oscilloscope génère le déclenchement, puis règle le couplage de déclenchement sur CC et le niveau de déclenchement sur zéro volt. 1 Disponible uniquement sur les oscilloscopes à 4 voies. 2 Disponible uniquement lorsque vous sélectionnez le type Déclenchement sur front. REMARQUE. Pour afficher un signal de déclenchement Ext., Ext/5 ou Secteur, maintenez le bouton TRIG VIEW enfoncé. Couplage. Le couplage vous permet de filtrer le signal de déclenchement utilisé pour déclencher une acquisition. Option Détails CC Cette option permet de faire passer toutes les composantes du signal Rejet bruit Cette option permet d’ajouter de l’hystérésis au circuit de déclenchement ; on peut ainsi réduire la sensibilité et donc la probabilité de faux déclenchement en fonction du bruit. Rejet HF Permet de réduire les composantes de fréquence élevée supérieure à 80 kHz Rejet BF Bloque la composante CC et réduit les composantes de basse fréquence au-dessous de 300 kHz. CA Bloque les composantes CC et réduit les signaux de fréquence inférieure à 10 Hz 130 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence REMARQUE. Le couplage de déclenchement n’affecte que le signal transmis au système de déclenchement. Il n’affecte ni la bande passante, ni le couplage du signal affiché à l’écran. Pré-déclenchement. La position du déclenchement est généralement définie à l’horizontale, au centre de l’écran. Vous pouvez alors afficher cinq divisions d’informations de pré-déclenchement. En réglant la position horizontale du signal, vous augmentez ou diminuez la quantité d’informations de pré-déclenchement affichées à l’écran. Déclenchement vidéo Options Réglages Commentaires Vidéo Si l’option Vidéo est sélectionnée, le déclenchement s’effectue sur un signal vidéo standard de type NTSC, PAL ou SECAM. Le couplage de déclenchement est prédéfini sur CA. Source CH1, CH2, CH3 1, CH4 1, Ext., Ext/5 Sélectionne la source d’entrée utilisée comme signal de déclenchement ; les sélections Ext. et Ext/5 utilisent le signal appliqué au connecteur EXTERNE Polarité Normale, Inversée Le type Normale permet d’effectuer le déclenchement sur le front négatif de l’impulsion de synchronisation, et le type Inversée, sur le front positif de cette impulsion. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 131 Référence Options Réglages Commentaires Synch. Ttes lignes, No de ligne, Trame imp., Trame paire, Ttes trames Sélectionnez une synchronisation vidéo appropriée. Si vous sélectionnez l’option No de ligne en tant qu’option Synch., tournez le bouton multifonctionnel pour spécifier un numéro de ligne. Standard NTSC, PAL/SECAM Sélectionnez le standard vidéo désiré pour la synchronisation et le comptage du nombre de lignes. 1 Disponible uniquement sur les oscilloscopes à 4 voies. Informations importantes Impulsions synch. Quand vous choisissez une Polarité Normale, le déclenchement se produit toujours sur des impulsions synch. sur front descendant. Si votre signal vidéo possède des impulsions synch. sur front ascendant, sélectionnez une Polarité Inversée. Déclenchement sur largeur d’impulsion Utilisez le Déclenchement sur largeur d’impulsion pour obtenir des déclenchements sur des impulsions normales ou aberrantes. Options Réglages Commentaires Impulsion Si l’option Impulsion est sélectionnée, le déclenchement s’effectue sur les impulsions conformes aux conditions de déclenchement définies par les options Source, Quand et Régler largeur d’impulsion. Source CH1, CH2, CH3 1, CH 4 1, Ext., Ext/5 Sélectionnez la source d’entrée utilisée comme signal de déclenchement. 132 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Options Réglages Commentaires Quand =, ≠, <, > Sélectionnez le mode de comparaison de l’impulsion de déclenchement par rapport à la valeur sélectionnée dans l’option Largeur d’impulsion. Largeur d’impulsion 33 ns à 10 s Utilisez le bouton multifonctionnel pour définir une largeur. Polarité Positif, Négatif Sélectionnez cette option pour effectuer un déclenchement sur des impulsions positives ou négatives. Mode Auto, Normal Sélectionnez cette option pour définir le type de déclenchement ; le mode Normal est le mieux adapté à la plupart des applications de déclenchement sur largeur d’impulsion. Couplage CA, CC, rejet bruit, rejet HF, rejet BF Permet de sélectionner les composantes du signal de déclenchement qui s’appliquent au circuit de déclenchement ;(Voir page 127, Déclenchement sur front.) suite Permet de parcourir les pages des sous-menus 1 Disponible uniquement sur les oscilloscopes à 4 voies. Mesure de la fréquence du déclenchement L’oscilloscope mesure la cadence à laquelle se produisent les déclenchements afin de déterminer la fréquence du déclenchement et affiche ensuite cette fréquence dans le coin inférieur droit de l’écran. Informations importantes Déclenchement Quand. La largeur d’impulsion de la source doit être ≥5 ns pour que l’oscilloscope puisse détecter l’impulsion. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 133 Référence Options Quand Détails = ≠ Déclenche l’oscilloscope quand la largeur d’impulsion du signal égale ou diffère de l’impulsion spécifiée dans une tolérance de ±5 %. < > Déclenche l’oscilloscope lorsque la largeur d’impulsion du signal source est inférieure ou supérieure à la largeur d’impulsion spécifiée Reportez-vous au chapitre Exemples d’applications pour avoir un exemple de déclenchement sur des impulsions aberrantes. (Voir page 56, Déclenchement sur une largeur d’impulsion spécifique.) Molettes et boutons Bouton NIVEAU. Permet de contrôler le Niveau de déclenchement. Bouton NIVEAU A 50 %. Le bouton NIVEAU A 50 % vous permet de stabiliser rapidement un signal. L’oscilloscope règle automatiquement le Niveau de déclenchement approximativement à mi-chemin entre les niveaux de tension maximum et minimum. Ce réglage est utile lorsque 134 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence vous connectez un signal au BNC EXTERNE et définissez la source de déclenchement sur Ext. ou Ext/5. Bouton FORCE TRIG. Le bouton FORCE TRIG vous permet de terminer l’acquisition du signal en cours, que l’oscilloscope détecte ou non un déclenchement. Ce bouton est utile pour les acquisitions SEQ. UNIQUE et le mode de déclenchement Normal (en mode de déclenchement Auto, l’oscilloscope procède à un déclenchement forcé s’il ne détecte pas de déclenchement pendant un certain laps de temps). Bouton TRIG VIEW. Le mode Trigger View permet d’afficher le signal de déclenchement conditionné sur l’oscilloscope. Vous pouvez utiliser ce mode pour afficher les types d’informations suivants : Effets de l’option Couplage déclenchement Source de déclenchement Secteur (Déclenchement sur front uniquement) Signal connecté au BNC EXTERNE REMARQUE. Il s’agit du seul bouton que vous devez maintenir enfoncé pendant l’utilisation. Lorsque vous maintenez le bouton TRIG VIEW enfoncé, le seul autre bouton utilisable est la touche PRINT. L’oscilloscope désactive tous les autres boutons du panneau avant. Cependant, les molettes restent actives. Inhibition. La fonction Inhibition du déclenchement permet d’obtenir un affichage stable de signaux complexes, tels que des trains d’impulsion. L’inhibition représente le temps séparant le moment où l’oscilloscope détecte un déclenchement de celui où il est prêt à détecter le suivant. L’oscilloscope ne se déclenche pas pendant la période d’inhibition. En ce qui concerne les trains d’impulsion, vous pouvez régler la période d’inhibition afin que l’oscilloscope ne se déclenche qu’à la première impulsion du train. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 135 Référence Pour utiliser la fonction Inhibition du déclenchement, appuyez sur le bouton d’option HORIZ MENU ► Définir validat. de déclenchem. et utilisez le bouton multifonctionnel pour ajuster l’inhibition. La résolution de l’inhibition de déclenchement varie en fonction du réglage SEC/DIV horizontal. Utilitaire Appuyez sur le bouton UTILITAIRE pour afficher le menu Utilitaire. Options Réglages Commentaires Résumé des paramètres de l’oscilloscope Etat du système Divers Affiche le modèle, le numéro de série du fabricant, les adaptateurs connectés, l’adresse de configuration du bus GPIB, la version du micrologiciel et d’autres informations 136 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Options Réglages Commentaires Style d’affichage 1 Définit les données de l’écran en noir sur fond blanc ou en blanc sur fond noir Configuration imprimante Modifie la configuration de l’imprimante(Voir page 95.) Configuration du bus GPIB ► Adresse Définit l’adresse GPIB pour l’adaptateur TEK-USB-488 (Voir page 93.) Régler date et heure Règle la date et l’heure (Voir page 138.) Options Historique des erreurs Affiche une liste de toutes les erreurs enregistrées ainsi que le comptage des cycles d’alimentation Cet historique est utile lorsque vous contactez un Centre d’entretien Tektronix pour obtenir de l’aide. Exécuter Auto-cal Permet d’effectuer un ajustement automatique Utilitaires Fichiers Affiche les options de dossier, de fichier et de lecteur flash USB (Voir page 139.) Language Anglais, Français, Allemand, Italien, Espagnol, Japonais, Portugais, Chinois simplifié, Chinois traditionnel, Coréen Permet de sélectionner la langue de l’oscilloscope 1 Modèles monochromes uniquement. Informations importantes Etat du système. En sélectionnant l’état du système dans le menu Utilitaire, vous pouvez afficher les menus permettant d’obtenir la liste des paramètres de commande correspondant aux différents groupes de commandes de l’oscilloscope. Appuyez sur n’importe quel bouton du panneau avant pour supprimer l’écran d’état. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 137 Référence Options Commentaires Bases de temps Liste les paramètres horizontaux Vertical Liste les paramètres verticaux des voies Déclenche Liste les paramètres de déclenchement Divers Affiche le modèle de l’oscilloscope, le numéro de version du logiciel et le numéro de série Indique les valeurs des paramètres de communication Réglage de la date et de l’heure. Vous pouvez utiliser le menu Régler date et heure pour régler la date et l’heure de l’horloge. L’oscilloscope affiche ces informations et les utilise également pour horodater les fichiers écrits sur un lecteur flash USB. L’oscilloscope contient une batterie intégrée non remplaçable qui permet de conserver les réglages de l’horloge. L’horloge ne s’ajuste pas automatiquement en fonction des changements d’heure saisonniers. Le calendrier s’ajuste pour les années bissextiles. Options Commentaires ↑ ↓ Déplace la mise en surbrillance de sélection du champ vers le haut ou vers le bas dans la liste. Utilisez le bouton multifonctionnel pour modifier la valeur du champ sélectionné. Régler date et heure Met à jour l’oscilloscope avec la date et l’heure spécifiées Annuler Ferme le menu et revient au menu précédent sans sauvegarder les modifications Calibrage automatique. Le programme de calibrage automatique optimise la précision de l’oscilloscope pour la température ambiante. Pour une précision optimale, effectuez un calibrage automatique chaque fois que la température ambiante varie de 5 °C (9 °F) ou plus. Pour un calibrage précis, mettez l’oscilloscope sous tension et laissez-le chauffer pendant vingt minutes. Suivez ensuite les instructions qui s’affichent à l’écran. La fonction Calibrage usine utilise les tensions générées en externe et requiert un équipement spécial. Il est recommandé de l’effectuer tous les ans. Reportez-vous à la section Coordonnées de Tektronix à la 138 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence page du copyright pour obtenir des informations sur la réalisation d’un Calibrage usine de votre oscilloscope par Tektronix. Utilitaires Fichiers pour le lecteur flash USB Un dossier est toujours désigné comme le dossier courant. Le dossier courant est l’emplacement par défaut pour la sauvegarde et le rappel des fichiers. Le menu Utilitaires Fichiers permet d’effectuer les opérations suivantes : répertorier le contenu du dossier courant sélectionner un fichier ou un dossier accéder à d’autres dossiers créer, renommer et supprimer des fichiers et des dossiers Formater un lecteur flash USB Options Commentaires Accède au dossier du lecteur flash USB sélectionné. Utilisez le bouton multifonctionnel pour sélectionner un fichier ou un dossier, puis sélectionnez l’option de menu Modif. Dossier. Modif. Dossier Pour revenir au dossier précédent, sélectionnez l’option de dossier ↑Précédent et appuyez sur l’option de menu Modif. Dossier. Nouv. Dossier Crée un nouveau dossier intitulé NEW_FOL dans le dossier courant et affiche le menu Renommer pour changer le nom de dossier par défaut. Renommer (nom de fichier ou dossier) Affiche l’écran Renommer pour renommer un dossier ou un fichier, comme décrit ci-après. Supprimer (nom de fichier ou dossier) Supprime le nom de fichier ou le dossier sélectionné ; le dossier doit être vide pour pouvoir le supprimer. Confirmer Suppression S’affiche après avoir appuyé sur Supprimer afin de confirmer l’action de suppression d’un fichier. Si vous appuyez sur un bouton autre que Confirmer Suppression, l’action de suppression du fichier sera annulée. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 139 Référence Options Commentaires Format Formate le lecteur flash USB ; cela supprime toutes les données se trouvant sur le lecteur flash USB. M. à jour Firmware Suivez les instructions à l’écran pour la configuration et appuyez sur le bouton d’option M. à jour Firmware pour lancer la mise à jour du micrologiciel. Renommer un fichier ou dossier. Vous pouvez modifier le nom des fichiers et des dossiers sur un lecteur flash USB. Option Réglages Commentaires Permet de saisir le caractère alphanumérique mis en surbrillance au niveau de la position du curseur dans le champ Nom courant A - Z, 0 - 9, _, . Utilisez le bouton multifonctionnel pour sélectionner un caractère alphanumérique ou utilisez les fonctions Retour arr., Supprimer caract. ou Effacer nom. Retour arr. Modifie l’option du bouton de menu 1 en lui affectant la fonction Retour arr. Supprime le caractère situé à gauche du caractère mis en surbrillance dans le champ Nom Supprimer caract. Modifie l’option du bouton de menu 1 en lui affectant la fonction Supprimer caractère. Supprime du champ Nom le caractère mis en surbrillance Entrer caractère Effacer nom Modifie l’option du bouton de menu 1 en lui affectant la fonction Effacer nom. Supprime tous les caractères du champ Nom Réglages verticaux Vous pouvez utiliser les réglages verticaux pour afficher et effacer des signaux, pour ajuster l’échelle et la position verticales, pour régler les paramètres d’entrée et pour les opérations mathématiques verticales. (Voir page 115, Fonctions mathématiques.) 140 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Menus Verticaux des voies Il existe un menu vertical distinct pour chaque voie. Chaque option est définie individuellement pour chaque voie. Options Réglages Commentaires Couplage CC, CA, masse CC transmet les composantes CA et CC du signal d’entrée CA permet de bloquer les composantes CC et de réduire les signaux de fréquence inférieurs à 10 Hz Masse déconnecte le signal d’entrée Options Réglages Commentaires Limite Bande 20 MHz 1, Aucune Permet de limiter la bande passante pour réduire le bruit d’affichage ; filtre le signal pour réduire le bruit et toute composante haute fréquence non souhaitée Volts/Div Gros, Fin Permet de sélectionner la résolution de la molette Volts/Div Gros définit une séquence 1-2-5. Fin permet d’obtenir une résolution incluant des échelons de petite taille entre les réglages du mode Gros Sonde Voir le tableau suivant Appuyez pour régler les options Sonde Inverser Act., Désact. Inverse (renverse) le signal par rapport au niveau de référence 1 La bande passante effective est de 6 MHz avec une sonde P2220 réglée sur 1X. L’option est différente pour les sondes de tension et de courant : Atténuation ou Echelle. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 141 Référence Options de sonde Réglages Commentaires Sonde ►Tension ►Atténuation 1X, 10X, 20X, 50X, 100X, 500X, 1000X Permet de correspondre au facteur d’atténuation de la sonde de tension afin de garantir des affichages verticaux corrects Sonde ►Courant ► Echelle 5 V/A, 1 V/A, 500 mV/A, 200 mV/A, 100 mV/A, 20 mV/A, 10 mV/A, 1 mV/A Permet de correspondre à l’échelle de la sonde de courant afin de garantir des affichages verticaux corrects Retour Permet de revenir au menu précédent Molettes Molettes VERTICAL POSITION. Tournez les molettes VERTICAL POSITION pour déplacer les signaux de la voie vers le haut ou le bas de l’écran. Molettes VOLTS/DIV. Les molettes VOLTS/DIV vous permettent de contrôler la manière dont l’oscilloscope amplifie ou atténue le signal source des signaux des voies. Lorsque vous tournez un bouton VOLTS/DIV, l’oscilloscope augmente ou réduit la taille verticale du signal à l’écran. Dépassement de la mesure verticale (écrêtage). Les signaux qui dépassent l’écran (dépassement) et présentent un ? dans l’affichage de mesure indiquent une valeur non valide. Réglez l’échelle verticale pour vous assurer que la mesure est valide. Informations importantes Couplage masse. Utilisez le couplage masse pour afficher un signal de zéro volt. En interne, l’entrée de la voie est connectée à un niveau de référence de zéro volt. 142 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Référence Résolution fine. L’échelle verticale affiche la valeur réelle du paramètre Volts/Div en mode résolution fine. Le passage en grosse résolution ne modifie pas l’échelle verticale tant que le bouton de commande VOLTS/DIV n’est pas ajusté. Supprimer un signal. Pour supprimer un signal de l’écran, appuyez sur un bouton de menu de la voie sur le panneau avant. Par exemple, appuyez sur le bouton CH 1 MENU pour afficher ou supprimer le signal de la voie 1. REMARQUE. Vous n’avez pas besoin d’afficher un signal de voie pour l’utiliser comme source de déclenchement ou dans le cadre d’opérations mathématiques. REMARQUE. Vous devez afficher un signal de voie pour prendre des mesures ou utiliser des curseurs sur ce signal, ou pour l’enregistrer comme signal de référence ou dans un fichier. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 143 Référence 144 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Toutes les spécifications s’appliquent aux modèles TDS1000B et TDS2000B. Reportez-vous à la fin de ce chapitre pour obtenir les spécifications relatives à la sonde P2220. Avant de vérifier la conformité de l’oscilloscope aux spécifications en vigueur, celui-ci doit d’abord satisfaire aux conditions suivantes : L’oscilloscope doit avoir fonctionné en continu pendant vingt minutes dans un environnement conforme à la température de fonctionnement spécifiée. Vous devez effectuer l’opération Exécuter Auto-cal, accessible via le menu Utilitaire, si la température de fonctionnement change de plus de 5 °C (9 °F). L’oscilloscope doit être dans l’intervalle du calibrage usine. Toutes les spécifications sont garanties, à l’exception de celles désignées comme « types ». Spécifications de l’oscilloscope Tableau 1 : Spécifications d’acquisition Caractéristique Description Modes d’acquisition Normale, Détect Créte et Moyenne Fréquence d’acquisition, type Jusqu’à 180 signaux par seconde, par voie (mode d’acquisition Normale, pas de mesure) Mode d’acquisition L’acquisition s’interrompt après Normale, Détect Créte Acquisition unique, toutes les voies simultanément Séquence unique Moyenne Acquisitions N, toutes les voies simultanément, N peut avoir la valeur 4, 16, 64 ou 128 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 145 Annexe A : Spécifications Tableau 2 : Spécifications d’entrée Caractéristique Description Couplage d’entrée CC, CA ou masse Impédance d’entrée, Couplée en CC 1 MΩ ± 2 % en parallèle à 20 pF ± 3 pF Atténuation de la sonde P2220 1X, 10X Facteurs d’atténuation de la sonde de tension prise en charge 1X, 10X, 20X, 50X, 100X, 500X, 1000X Echelles de sonde de courant prises en charge 5 V/A, 1 V/A, 500 mV/A, 200 mV/A, 100 mV/A, 20 mV/A, 10 mV/A, 1 mV/A Catégorie de surtension Tension maximum CAT I et CAT II 300 Veff CAT III 150 Veff Tension maximale entre le signal et la référence au connecteur d’entrée BNC Catégorie d’installation II ; dérive à 20 dB/décade au-dessus de 100 kHz à la tension de crête de 13 V CA à 3 MHz 1 et plus. Pour les ondes non sinusoïdales, la valeur de la crête doit être inférieure à 450 V. La durée d’une course supérieure à 300 V doit être inférieure à 100 ms et le rapport cyclique est limité à ≤ 44 %. Le niveau de signal efficace, y compris les éventuelles composantes CC supprimées via couplage CA, doit être limité à 300 V. En cas de dépassement de ces valeurs, cela risque d’endommager l’instrument. Reportez-vous à la description de la Catégorie de surtension ci-dessus. 146 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Tableau 2 : Spécifications d’entrée, (suite) Caractéristique Description TDS1001B TDS1002B, 2002B, 2004B TDS1012B, 2012B, 2014B, 2022B, 2024B 100:1 à 60 Hz, 20:1 à 20 MHz1 2 100:1 à 60 Hz, 20:1 à 30 MHz 1. 2 100:1 à 60 Hz, 10:1 à 50 MHz1. 2 Réjection type en mode commun entre voies Mesurée sur le signal calculé Ch1 - Ch2, avec application du signal de test entre le signal et la masse des deux voies, et avec des réglages VOLTS/DIV et de couplage identiques sur chaque voie. Mesurée sur le signal calculé Ch3 - Ch4 pour les modèles à 4 voies TDS1001B TDS1002B, 2002B, 2004B TDS1012B, 2012B, 2014B TDS2022B, 2024B ≥ 100:1 à 20 MHz 1. 2 ≥ 100:1 à 30 MHz 1. 2 ≥ 100:1 à 50 MHz 1. 2 ≥ 100:1 à 100 MHz 1. 2 Diaphonie de voie à voie Mesurée sur une voie, avec application du signal de test entre le signal et la masse de l’autre voie et avec des réglages VOLTS/DIV et de couplage identiques sur chaque voie 1 Bande passante réduite à 6 MHz avec une sonde 1X. 2 Ne fait pas apparaître les impacts liés à la sonde. Tableau 3 : Spécifications verticales 1 Caractéristique Description Numériseurs Résolution à 8 bits (sauf lorsqu’ils sont définis sur 2 mV/div) ; chaque voie est échantillonnée simultanément Plage VOLTS/DIV 2 mV/div à 5 V/div au BNC d’entrée Plage de positions 2°mV/div à 200mV/div ±2°V > 200 mV/div à 5 V/div, ±50 V Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 147 Annexe A : Spécifications Tableau 3 : Spécifications verticales 1 , (suite) Caractéristique Description TDS1001B TDS1002B, 2002B, 2004B TDS1012B, 2012B, 2014B TDS2022B, 2024B 40 MHz2 3 60 MHz2 3 100 MHz2 3 200 MHz2 3 0 °C à + 40 °C (32 °F à 104 °F) 160 MHz2 3 0 °C à + 50 °C (32 °F à 122 °F) Bande passante analogique en modes Echantillon et Moyenne au BNC ou avec la sonde P2220 réglée à 10X, Couplée en CC 20 MHz 2 (lorsque l’échelle verticale est réglée sur < 5 mV) TDS1001B TDS1002B, 2002B, 2004B TDS1012B, 2012B, 2014B, 2022B, 2024B 30 MHz2 3 50 MHz2 3 75 MHz2 3 Bande passante analogique en mode Détect Créte (50 s/div à 5 μs/div 4), type 20 MHz 2 (lorsque l’échelle verticale est réglée sur < 5 mV) Limite de bande passante analogique sélectionnable, type 20 MHz 2 Limite de fréquence inférieure, Couplée en CA ≤ 10 Hz à BNC ≤ 1°Hz avec une sonde passive 10X TDS1001B TDS1002B, 2002B, 2004B TDS1012B, 2012B, 2014B TDS2022B, 2024B Temps de montée au BNC, type < 8,4 ns < 5,8 ns < 3,5 ns < 2,1 ns 148 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Tableau 3 : Spécifications verticales 1 , (suite) Caractéristique Description Réponse à la Détect Créte 4 Capture 50 % ou plus de l’amplitude des impulsions d’une largeur ≥ 12 ns (50s/div à 5ms/div) dans les 8 divisions verticales centrales ± 3 % pour le mode d’acquisition Normale ou Moyenne, 5 V/div à 10 mV/div Précision du gain CC ± 4 % pour le mode d’acquisition Normale ou Moyenne, 5 mV/div à 2 mV/div Type de mesure Précision Moyenne ≥ 16 signaux, la position verticale étant définie sur zéro ± (3 % × lecture + 0,1 div + 1 mV) lorsque la valeur 10 mV/div ou supérieure est sélectionnée Précision de mesure CC, Mode d’acquisition Moyenne Moyenne ≥ 16 signaux en position verticale et échelle verticale réglée sur 2 mV/div à 200°m/div et –1.8 V < position verticale < 1.8 V ±[3% × (lecture + position verticale) + 1% de la position verticale + 0,2 div + 7 mV] Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 149 Annexe A : Spécifications Tableau 3 : Spécifications verticales 1 , (suite) Caractéristique Description Moyenne ≥ 16 signaux en position verticale et échelle verticale réglée sur > 200 mV/div and –45 V < Position Verticale < 45 V ± [3% × (lecture + position verticale) + 1% de la position verticale + 0,2 div + 175 mV] Répétabilité de mesure en volts, Mode d’acquisition Moyenne Ecart en volts entre deux moyennes basses sur ≥16 signaux capturés dans les mêmes conditions ambiantes et de configuration ± (3 % × lecture + 0,05 div) 1 Les spécifications sont définies sur 1X pour l’option Sonde ►Tension ►Atténuation. 2 Bande passante réduite à 6 MHz avec une sonde 1X. 3 Lorsque l’échelle verticale est définie sur > 5 mV. 4 L’oscilloscope repasse en mode Echantillon lorsque le réglage SEC/DIV (échelle horizontale) est compris entre 2,5 ms/div et 5 ns/div sur les modèles à 1 G éch./s ou entre 2,5 ms/div et 2,5 ns/div sur les modèles à 2 G éch./s. Le mode Echantillon peut toujours capturer des parasites d’une largeur de 10 ns. 150 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Tableau 4 : Spécifications horizontales Caractéristique Description TDS1001B, 1002B, 1012B, 2002B, 2004B, 2012B, 2014B Plage de la TDS2022B, 2024B fréquence d’échantillonnage 5 éch./s à 1 G éch./s 5 éch./s à 2 G éch./s Interpolation du signal (sinus x)/x Longueur d’enregistrement 2 500 échantillons pour chaque voie TDS1001B, 1002B, 1012B, 2002B, 2004B, 2012B, 2014B Plage TDS2022B, 2024B SEC/DIV 5 ns/div à 50 s/div, dans une séquence 1, 2,5, 5 2,5 ns/div à 50 s/div, dans une séquence 1, 2,5, 5 Précision de la fréquence d’échantillonnage et temps de retard ± 50 ppm au-dessus de tout intervalle de temps ≥ 1 ms Conditions Précision Monocoup, mode Echantillon ± (1 intervalle d’échantillonnage + 100 ppm × lecture + 0,6 ns) > 16 moyennes ± (1 intervalle d’échantillonnage + 100 ppm × lecture + 0,4 ns) Précision de la mesure de temps Delta (Totalité de la bande passante) Intervalle d’échantillonnage = s/div ÷ 250 TDS1001B, 1002B, 1012B, 2002B, 2004B, 2012B, 2014B 2022B, 2024B 5 ns/div à 10 ns/div (- 4 div × s/div) à 20 ms 25 ns/div à 100 μs/div (- 4 div × s/div) à 50 ms 250 ms/div à 50 s/div (- 4 div × s/div) à 50 s TDS2022B, 2024B Plage de positions 2.5°ns/div (- 4 div × s/div) à 20 ms Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 151 Annexe A : Spécifications Tableau 5 : Spécifications de déclenchement Caractéristique Description Couplage Sensibilité TDS1001B, 1002B, 1012B, 2002B, 2004B, 2012B, 2014B TDS2022B, 2024B EXT. 200 mV de CC à 100 MHz 1 200 mV de CC à 100 MHz 1 350 mV de 100 MHz à 200 MHz 1 EXT/5 1 V de CC à 100 MHz 1 1 V de CC à 100 MHz 1 1,75 V de 100 MHz à 200 MHz 1 Sensibilité de déclenchement, Type Déclenchement sur front, affichage stable d’un événement de déclenchement CC CH1, CH2, CH3 2, CH42 1 div de CC à 10 MHz 1 1,5 div de 10 MHz à pleine puissance 1,5 div de 10 MHz à 100 MHz 2 div de 100 MHz à pleine puissance 152 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Tableau 5 : Spécifications de déclenchement, (suite) Caractéristique Description Couplage Sensibilité TDS1001B, 1002B, 1012B, 2002B, 2004B, 2012B, 2014B TDS2022B, 2024B EXT 300 mV de CC à 100 MHz 1 300 mV de CC à 100 MHz 1 500 mV de 100 MHz à 200 MHz 1 EXT/5 1.5 V de CC à 100 MHz 1 1.5 V de CC à 100 MHz 1 3 V de 100 MHz à 200 MHz 1 Sensibilité de déclenchement, Type Déclenchement sur front, Compteur de fréquences, type CC CH1, CH2, CH3 2, CH42 1,5 div de CC à 10 MHz 1 3 div de 10 MHz à pleine puissance Couplage Sensibilité CA Identique à CC à 50 Hz et plus REJECTION DU BRUIT Réduit la sensibilité de déclenchement couplée CC de moitié pour > 10 mv/div à 5 V/div HF REJ Identique à la limite couplée CC de CC à 7 kHz, réduit les signaux supérieurs à 80 kHz Sensibilité de déclenchement, Type Déclenchement sur front, type LF REJ Identique aux limites couplées CC pour les fréquences supérieures à 300 kHz, réduit les signaux inférieurs à 300 kHz Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 153 Annexe A : Spécifications Tableau 5 : Spécifications de déclenchement, (suite) Caractéristique Description Source Plage CH1, CH2, CH3 2, CH42 ± 8 divisions à partir du centre de l’écran EXT. ± 1,6 V EXT/5 ± 8 V Plage de niveau de déclenchement, type Secteur Impossible à définir Les précisions s’appliquent aux signaux ayant des temps de montée et de descente ≥ 20 ns. Source Précision Interne ±0,2 div × volts/div dans ±4 divisions à partir du centre de l’écran EXT. ± (6 % du réglage + 40 mV) Précision du niveau de déclenchement, type EXT/5 ± (6% du réglage + 200 mV) NIVEAU A 50 %, type Fonctionne avec des signaux d’entrée ≥ 50 Hz Réglages par défaut, Déclenchement vidéo Le couplage est défini sur CA et Auto sauf pour une acquisition de type séquence unique Signal vidéo composite Source Plage Interne Amplitude C-C de 2 divisions EXT. 400 mV Sensibilité, Type Déclenchement vidéo, type EXT/5 2 V Formats du signal et fréquences de la trame, Type Déclenchement vidéo Prend en charge les systèmes de diffusion NTSC, PAL et SECAM pour toute trame ou toute ligne 154 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Tableau 5 : Spécifications de déclenchement, (suite) Caractéristique Description Plage d’inhibition 500 ns à 10 s Modes Déclenchement sur largeur d’impulsion Déclenchement lorsque < (Inférieur à), > (Supérieur à ), = (Egal à) ou ≠ (Différent) ; Impulsion positive ou Impulsion négative Point de déclenchement sur largeur d’impulsion Egal : l’oscilloscope se déclenche lorsque le front descendant de l’impulsion croise le niveau de déclenchement. Différent : si l’impulsion est plus étroite que la largeur spécifiée, le point de déclenchement est représenté par le front descendant. Sinon, l’oscilloscope se déclenche lorsqu’une impulsion dure plus longtemps que la durée spécifiée dans l’option Largeur d’impulsion. Inférieur à : le point de déclenchement est représenté par le front descendant. Supérieur à (également appelé Déclenchement sur temporisation) : l’oscilloscope se déclenche lorsqu’une impulsion dure plus longtemps que la durée spécifiée dans l’option Largeur d’impulsion. Plage de largeur d’impulsion Sélectionnable entre 33 ns et 10 s Résolution de largeur d’impulsion 16,5 ns ou 1 partie par millier, quelle que soit la valeur la plus élevée Bande de garde égale t > 330 ns : ± 5 %≤ bande de guarde < ± (5,1 % + 16,5 ns) t ≤ 330 ns : bande de garde = + 16,5 ns Bande de garde différente t > 330 ns : ± 5 %≤ bande de guarde < ± (5,1 % + 16,5 ns) 165 ns < t ≤ 330 ns : bande de garde = - 16,5 ns/+ 33 ns t ≤ 165 ns : bande de garde = + 16,5 ns Compteur de fréquence de déclenchement Résolution d’affichage 6 chiffres Précision (typique) + 51 ppm y compris toutes les erreurs de fréquence de référence et ± 1 erreur de comptage Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 155 Annexe A : Spécifications Tableau 5 : Spécifications de déclenchement, (suite) Caractéristique Description Plage de fréquences Couplée CA, 10 Hz au minimum jusqu’à la bande passante indiquée Signal source Modes Déclenchement sur largeur d’impulsion ou Déclenchement sur front : toutes les sources de déclenchement disponibles Le compteur de fréquences permet à tout moment de mesurer la source de déclenchement dans les modes Largeur d’impulsion ou Front, y compris lorsque l’acquisition est interrompue sur l’oscilloscope en raison de modifications du mode d’exécution ou lorsque l’acquisition d’un événement monocoup est terminée. Mode Déclenchement sur largeur d’impulsion : l’oscilloscope compte les impulsions considérées comme événements de déclenchement et ayant une amplitude significative dans la fenêtre de mesure de 250 ms, telles que les impulsions étroites dans un train d’impulsion MLI s’il est défini sur le mode < et si la largeur est définie sur une durée relativement courte. Mode Déclenchement sur front : l’oscilloscope compte tous les fronts ayant une amplitude suffisante et une polarité correcte. Mode Déclenchement vidéo : le compteur de fréquences n’intervient pas. 1 Bande passante réduite à 6 MHz avec une sonde 1X. 2 Disponible uniquement sur les oscilloscopes à 4 voies. Tableau 6 : Spécifications de mesures Caractéristique Description Curseurs Différence d’amplitude entre les curseurs ( ΔV, ΔA ou ΔVA) Différence de temps entre les curseurs (Δt) Inverse de Δt en hertz (1/ Δt) Mesures automatiques Fréquence, Période, Moyenne, C-C, Valeur efficace du cycle, Min, Max, Tps montée, Tps descente, Largeur pos., Largeur nég. 156 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Tableau 7 : Spécifications générales Caractéristique Description Affichage Type d’affichage à cristaux liquides diagonaux de 5,7 pouces (145 mm) Résolution d’affichage 320 pixels à l’horizontale sur 240 à la verticale Contraste de l’écran Réglable, à compensation thermique Intensité de rétro-éclairage, type 1 65 cd/m2 Sortie du compensateur de la sonde Tension de sortie, type 5 V dans une charge ≥ 1 MΩ Fréquence, type 1 kHz Source d’alimentation Tension de source 100 - 240 VACeff (± 10 %) 50/60 Hz 115 VACeff (± 10 %) 400 Hz (± 10 %) Consommation électrique Inférieure à 30 W Fusible 2 A, protection thermique-magnétique, 250 V Environnement Degré de pollution Degré de pollution 2 2. Utilisation en intérieur uniquement. N’utilisez pas cet appareil dans un environnement susceptible d’abriter des polluants conducteurs. En fonctionnement 32 °F à 122 °F (0 °C à + 50 °C) Température A l’arrêt - 40 °F à 159,8 °F (- 40 °C à +71 °C) Méthode de refroidissement Convection + 104 °F ou moins (+ 40 °C ou moins) Humidité Humidité relative ≤ 85 % 106 °F à 122 °F (+ 41 °C à + 50 °C) Humidité relative ≤ 45 % Altitude 3 000 m (environ 10 000 pieds) Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 157 Annexe A : Spécifications Tableau 7 : Spécifications générales, (suite) Caractéristique Description En fonctionnement 0,31 geff de 5 Hz à 500 Hz, 10 minutes sur chaque axe Vibration aléatoire A l’arrêt 2,46 geff de 5 Hz à 500 Hz, 10 minutes sur chaque axe Choc mécanique En fonctionnement 50 g, 11 ms, semi-sinusoïdal Mécanique Hauteur 158 mm (6,22 pouces) Largeur 326,3 mm (12,845 pouces) Dimension Profondeur 124,1 mm (4,885 pouces) Poids (approximatif) Appareil uniquement 2 kg (4,375 livres) Intervalle de réglage (Calibrage usine) Il est recommandé de l’effectuer tous les ans. 1 Réglable via le menu Affichage. 2 Tel que défini par la norme IEC 61010-1:2001. Homologations et conformité de l’oscilloscope Déclaration de conformité électromagnétique CE Conforme aux objectifs de la Directive 89/336/CEE pour la compatibilité électromagnétique. La conformité aux spécifications suivantes a été démontrée telles qu’établies au Journal officiel de la Communauté européenne : EN 61326. Règles de compatibilité électromagnétique relatives aux équipements électriques de classe A utilisés pour les mesures, le contrôle et l’utilisation en laboratoire 158 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications IEC 61000-4-2. Immunité des décharges électrostatiques (Critère de performance B) IEC 61000-4-3. Immunité du champ électromagnétique RF (Critère de performance A) IEC 61000-4-4. Electrique transitoire rapide/immunité de salve (Critère de performance B) IEC 61000-4-5. Immunité contre les surtensions de la ligne d’alimentation (Critère de performance B) IEC 61000-4-6. Immunité RF transmise par conduction (Critère de performance A) IEC 61000-4-11. Insensibilité aux chutes de tension & interruptions (Critère de performance B) EN 61000-3-2. Emissions d’harmoniques de la ligne d’alimentation secteur 1 EN 61000-3-3. Changements de tension, fluctuations et scintillement 1 Des émissions qui dépassent les niveaux requis par cette norme peuvent se produire lorsque cet instrument est connecté à un objet de test. Déclaration de conformité électromagnétique Australie/Nouvelle-Zélande Conforme aux dispositions du Radiocommunications Act en matière de compatibilité électromagnétique, par le biais de la ou des norme(s) suivante(s) : AS/NZS 2064.1/2. Equipement industriel, scientifique et médical : 1992 Conformité CEM Conforme aux objectifs de la directive 89/336/CEE pour la conformité de compatibilité électromagnétique en cas d’utilisation avec le ou les produit(s) mentionné(s) dans le tableau des spécifications. Reportez-vous à la spécification CEM publiée pour les produits mentionnés. Non-conformité possible aux objectifs de la directive en cas d’utilisation avec d’autres produits. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 159 Annexe A : Spécifications Conformité FCC Emissions conformes au Code américain de réglementation fédérale FCC 47, article 15, alinéa B, pour les appareils de Classe A. Fédération de Russie Ce produit a été homologué par le Ministère GOST russe comme étant conforme à toutes les réglementations applicables en matière de compatibilité électromagnétique. Déclaration de conformité basse tension CE La conformité aux spécifications suivantes telles qu’énoncées au Journal officiel de la Communauté européenne a été démontrée : Directive basse tension 73/23/CEE telle que modifiée par la directive 93/68/CEE : EN 61010-1:2001. Règles de sécurité relatives aux appareils électriques utilisés pour les mesures, le contrôle et l’utilisation en laboratoire. EN 61010-2-031:2002. Conditions spécifiques relatives aux systèmes de sonde à main destinés aux appareils électriques de mesure et de test. Liste des laboratoires de test agréés aux Etats-Unis UL 61010B-1:2004, 2ème édition. Norme relative aux appareils électriques de mesure et de test. UL 61010B-2-031:2003. Conditions spécifiques relatives aux systèmes de sonde à main destinés aux appareils électriques de mesure et de test. 160 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Homologation Canada CAN/CSA C22.2 N° 61010-1-04. Règles de sécurité relatives aux équipements électriques utilisés pour les mesures, le contrôle et l’utilisation en laboratoire. Partie 1. CAN/CSA C22.2 N° 61010-2-031:1994. Conditions spécifiques relatives aux systèmes de sonde à main destinés aux appareils électriques de mesure et de test. Autres normes IEC 61010-1:2001. Règles de sécurité relatives aux appareils électriques utilisés pour les mesures, le contrôle et l’utilisation en laboratoire. IEC 61010-031:2002. Conditions spécifiques relatives aux systèmes de sonde à main destinés aux appareils électriques de mesure et de test. Type d’équipement Equipement de mesure et de test. Classe de sécurité Classe 1 - produits mis à la terre Descriptions du degré de pollution Mesure des contaminants pouvant être diffusés dans l’environnement autour et au sein du produit. L’environnement interne d’un produit est généralement considéré comme identique à l’environnement externe. Les produits doivent être utilisés uniquement dans l’environnement pour lequel ils ont été conçus. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 161 Annexe A : Spécifications Degré de pollution 1. Pas de pollution ou uniquement une pollution sèche, non conductrice. Les produits de cette catégorie sont généralement placés dans une enveloppe hermétique ou dans des salles blanches. Degré de pollution 2. Pollution sèche non conductrice uniquement. Une conductivité temporaire, due à la condensation, peut avoir lieu. Ces produits sont généralement destinés aux environnements domestiques/de bureau. Une condensation temporaire peut se former lorsque le produit est hors service. Degré de pollution 3. Pollution conductrice ou pollution sèche non conductrice devenant conductrice en cas de condensation. Ces produits sont destinés à des environnements abrités, où la température et l’humidité ne sont pas contrôlées. La zone est protégée des rayons directs du soleil, de la pluie ou du vent. Degré de pollution 4. Pollution générant une conductivité continue due à la conductivité de la poussière, de la pluie ou de la neige. Ces produits sont généralement utilisés en extérieur. Descriptions des catégories d’installation (surtension) Il est possible que les bornes de ce produit appartiennent à plusieurs catégories d’installation (surtension). Les différentes catégories d’installation sont les suivantes : Catégorie de mesure II (CAT II). Pour les mesures effectuées sur les circuits directement connectés à l’installation basse tension (secteur). Catégorie de mesure I (CAT I). Pour les mesures effectuées sur les circuits non connectés directement au secteur. 162 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications Spécifications relatives à la sonde P2220 Spécifications relatives à la sonde P2220 Caractéristiques électriques. Position 10X Bande passante CC à 200 MHz Rapport d’atténuation 10:1 ± 2% Plage de compensation 15 pF-25 pF Résistance d’entrée 10 MΩ ± 3 % à CC Capacité d’entrée 13 pF-17 pF Temps de montée, typique < 2,2 ns Tension d’entrée maximale 1 entre l’extrémité (signal) et le câble de référence Position 10X Position 1X 300 Veff CAT II ou 300 V CC CAT II 150 Veff CAT III ou 150 V CC CAT III Tension de crête 420 V, <50 % rapport cyclique, <1 s LI Tension de crête 670 V, <20 % rapport cyclique, <1 s LI 150 Veff CAT II ou 150 V CC CAT II 100 Veff CAT III ou 100 V CC CAT III Tension de crête 210 V, <50 % rapport cyclique, <1 s LI Tension de crête 330 V, <20 % rapport cyclique, <1 s LI Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 163 Annexe A : Spécifications Spécifications relatives à la sonde P2220 300 Veff ; dérive à 20 dB/décade au-dessus de 900 kHz à une tension de crête de 13 V CA à 3 MHz et plus. Pour les ondes non sinusoïdales, la valeur de la crête doit être inférieure à 450 V. La durée d’une course supérieure à 300 V doit être inférieure à 100 ms. Le niveau de signal efficace, y compris les éventuelles composantes CC supprimées via couplage CA, doit être limité à 300 V. Si cette valeur est dépassée, cela risque d’endommager l’instrument. Reportez-vous à la Catégorie de surtension, plus bas dans ce tableau. Tension d’entrée maximale 1 entre l’extrémité (signal) et la prise de terre Position 10X Position 1X 300 Veff CAT II ou 300 V CC CAT II 150 Veff CAT III ou 150 V CC CAT III Tension de crête 420 V, <50 % rapport cyclique, <1 s LI Tension de crête 670 V, <20 % rapport cyclique, <1 s LI 150 Veff CAT II ou 150 V CC CAT II 100 Veff CAT III ou 100 V CC CAT III Tension de crête 210 V, <50 % rapport cyclique, <1 s LI Tension de crête 330 V, <20 % rapport cyclique, <1 s LI 1 Tel que défini par la norme IEC61010-1 : 2001. Homologations et conformités relatives à la sonde P2220 Tension maximale entre le câble de référence et la prise de terre 30 V 1 164 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe A : Spécifications La conformité aux spécifications suivantes telles qu’énoncées au Journal officiel de la Communauté européenne a été démontrée : Directive basse tension 73/23/CEE telle que modifiée par la directive 93/68/CEE : Déclaration de conformité CE EN 61010-1 2001 EN 61010-2-031 2003 Règles de sécurité relatives aux équipements électriques utilisés pour les mesures, le contrôle et l’utilisation en laboratoire Recommandations particulières concernant les ensembles de sonde portative pour les mesures et les tests électriques Catégorie Exemples de produits appartenant à cette catégorie Catégorie de surtension CAT III CAT II CAT I Réseaux de distribution, installations fixes Réseaux d’alimentation terminale, appareils, équipements portatifs Niveaux des signaux sur un équipement ou composant d’équipement spécifique, de télécommunication, électronique Degré de pollution Degré de pollution 2 2. Utilisation en intérieur uniquement. N’utilisez pas cet appareil dans un environnement susceptible d’abriter des polluants conducteurs. Sécurité UL61010-1, 2004 & UL61010B-2-031, 2003 CAN/CSA 22.22 N° 61010.1:2004 CAN/CSA 22.22 N° 61010-2-031: IEC61010-031: 2001 EN61010-031: 2001 Caractéristiques environnementales En fonctionnement 0 °C à 50 °C (32 °F à 122 °F) Température A l’arrêt - 40 °C à 71 °C (- 40 °F à + 159,8 °F) Méthode de refroidissement Convection Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 165 Annexe A : Spécifications 104 °F (40 °C) ou moins Humidité Humidité relative ≤ 90 % 105 °F - 122 °F (41 °C à + 50 °C) Humidité relative ≤ 60 % En fonctionnement Altitude 3 000 m (environ 10 000 pieds) A l’arrêt 15 000 m (40 000 pieds) 1 Tel que défini par la norme IEC 61010-1:2001. 2 Tel que défini par la norme IEC 60529. 2001. 166 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe B : Accessoires Tous les accessoires (standard et en option) sont disponibles auprès de votre bureau local Tektronix. Accessoires standard Sonde de tension passive 1X, 10X P2220. Les sondes P2220 disposent d’une bande passante de 6 MHz avec une puissance nominale de 150 Veff CAT II lorsque le commutateur est en position 1X, et d’une bande passante de 200 MHz avec une puissance nominale de 300 Veff CAT II lorsque le commutateur est en position 10X. Le manuel d’utilisation de la sonde est disponible en anglais uniquement. Manuel de l’utilisateur des oscilloscopes TDS1000B et TDS2000B.Un seul manuel de l’utilisateur est inclus. Pour savoir dans quelles langues ce manuel est disponible, reportez-vous aux accessoires en option. CD-ROM de communication pour PC. Le logiciel de communication pour PC permet de transférer facilement les données de l’oscilloscope au PC. Accessoires en option Sonde de tension passive P6101B 1X. La sonde P6101B a une bande passante de 15 MHz d’une puissance de 300 VRMS CAT II. Kit d’installation en baie RM2000B Le Kit d’installation en baie RM2000B vous permet d’installer un oscilloscope TDS1000B ou TDS2000B dans une baie de 19 pouces conforme aux normes de l’industrie. Le kit d’installation en baie nécessite un espace vertical de sept pouces dans la baie. Vous pouvez allumer ou éteindre l’oscilloscope à partir de l’avant du kit d’installation en baie. Le kit d’installation en baie n’est pas mobile. Instructions pour la sonde 1X/10X P2220 Le manuel de la sonde P2220 (071-1464-XX, en anglais) fournit des informations sur la sonde et ses accessoires. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 167 Annexe B : Accessoires Manuel de programmation des oscilloscopes numériques TDS200, TDS1000/2000, TDS1000B/2000B et TPS2000. Le manuel de programmation (071-1075-XX, en anglais) fournit des informations relatives aux commandes et à la syntaxe. Manuel d’entretien des oscilloscopes à mémoire numérique TDS1000B et TDS2000B. Le manuel d’entretien (071-1828-XX, en anglais) fournit des informations relatives aux réparations au niveau du module. Manuels de l’utilisateur des oscilloscopes à mémoire numérique TDS1000B et TDS2000B. Le manuel de l’utilisateur est disponible dans les langues suivantes : Anglais, 071-1817-XX Français, 071-1818-XX Italien, 071-1819-XX Allemand, 071-1820-XX Espagnol, 071-1821-XX Japonais, 071-1822-XX Portugais, 071-1823-XX Chinois simplifié, 071-1824-XX Chinois traditionnel, 071-1825-XX Coréen, 071-1826-XX Russe, 071-1827-XX Cordons d’alimentation internationaux. Outre le cordon d’alimentation livré avec votre oscilloscope, vous pouvez vous procurer les cordons suivants : Option A0, Amérique du Nord 120 V, 60 Hz, 161-0066-00 Option A1, Europe 230 V, 50 Hz, 161-0066-09 Option A2, Royaume-Uni 230 V, 50 Hz, 161-0066-10 Option A3, Australie 240 V, 50 Hz, 161-0066-11 Option A5, Suisse 230 V, 50 Hz, 161-0154-00 Option A10, Chine 220 V, 50 Hz, 161-0304-00 Option A11, Inde 230 V, 50 Hz, 161-4000-00 168 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe B : Accessoires Adaptateur TEK-USB-488. L’adaptateur GPIB vous permet de raccorder votre oscilloscope à un contrôleur GPIB. Etui souple. L’étui souple (AC2100) protège l’oscilloscope des chocs et permet de ranger les sondes, le cordon d’alimentation et les manuels. Valise de transport. La valise de transport (HCTEK4321) protège l’oscilloscope des coups, des vibrations, des chocs et de l’humidité lors des déplacements. L’étui souple s’insère dans la valise de transport. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 169 Annexe B : Accessoires 170 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe C : Nettoyage Entretien - Généralités N’entreposez pas ou ne laissez pas l’oscilloscope longtemps dans un endroit où l’écran plat à cristaux liquides est exposé à la lumière directe du soleil. ATTENTION. Pour éviter d’endommager l’oscilloscope ou les sondes, ne les exposez à aucun vaporisateur, liquide ou solvant. Nettoyage Inspectez l’oscilloscope et les sondes aussi souvent que les conditions d’utilisation l’exigent. Procédez comme suit pour le nettoyage de la surface extérieure : 1. Retirez la poussière sur l’extérieur de l’oscilloscope et des sondes avec un chiffon non pelucheux. Procédez avec précaution pour éviter de rayer le filtre transparent de l’écran en verre. 2. Utilisez un chiffon doux imbibé d’eau pour nettoyer l’oscilloscope. Pour obtenir un nettoyage plus efficace, utilisez une solution aqueuse à base de 75 % d’isopropanol. ATTENTION. Pour éviter d’endommager la surface de l’oscilloscope ou des sondes, n’utilisez pas de produit de nettoyage abrasif ou chimique. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 171 Annexe C : Nettoyage 172 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe D : Configuration par défaut Cette annexe décrit les options, les boutons et les commandes qui sont modifiés lorsque vous appuyez sur le bouton CONF. PAR D. La dernière page de cette annexe répertorie les réglages qui ne changent pas. REMARQUE. Lorsque vous appuyez sur le bouton CONF. PAR D., l’oscilloscope affiche le signal CH1 et supprime tous les autres signaux. Menu ou système Option, bouton ou molette Paramètre par défaut (options composées de trois modes) Normale Moyennes 16 ACQUISITION RUN/STOP RUN CALIBRAGE AUTO Calibrage Auto Aucune Mode Vertical et Horizontal Type Aucune Source CH1 Horizontal (amplitude) +/- 3,2 div CURSEURS Vertical (temps) +/- 4 div Type Vecteurs Persist. Aucune AFFICHAGE Mode Y(t) Base de temps principale Principale Déclenche. Niveau POSITION 0 s SEC/DIV 500 ms HORIZONTAL Zone retardée 50 ms Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 173 Annexe D : Configuration par défaut Menu ou système Option, bouton ou molette Paramètre par défaut Opération - Sources CH1 - CH2 Position 0 div Echelle Verticale 2 V MATH Opération FFT : Source Fenêtre FFT Zoom CH1 Hanning X1 MESURES (Toutes) Source CH1 Type Aucune TRIGGER Type Front (commun) Source CH1 Pente Montante Mode Auto Couplage CC TRIGGER (Front) NIVEAU 0 V Polarité Normale Synch. Ttes lignes TRIGGER (Vidéo) Standard NTSC Quand = Régler largeur d’impulsion 1 ms Polarité Positif Mode Auto TRIGGER (Impulsion) Couplage CC 174 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe D : Configuration par défaut Menu ou système Option, bouton ou molette Paramètre par défaut Couplage CC Limite Bande Aucune Volts/Div Gros Sonde Tension Atténuation de la sonde de tension 10X Echelle de la sonde de courant 10 A/V Inverser Désact. POSITION 0 div (0 V) Système vertical, toutes les voies VOLTS/DIV 1 V Le bouton CONF. PAR D. ne modifie pas les réglages suivants : option Langue Configurations sauvegardées Signaux de référence sauvegardés Contraste de l’écran Données de calibrage Configuration imprimante Configuration du bus GPIB Configuration de la sonde (type et facteur d’atténuation) Date et heure Dossier courant sur le lecteur flash USB Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 175 Annexe D : Configuration par défaut 176 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe E : Licences de police Les accords de licence suivants couvrent les polices asiatiques utilisées pour les oscilloscopes TDS1000B et TDS2000B. Copyright © 1988 The Institute of Software, Academia Sinica. Adresse postale : P.O. Box 8718, Beijing, Chine 100080. Le présent avis autorise l’utilisation, la copie, la modification et la distribution du présent logiciel et sa documentation à toutes fins utiles et sans contrepartie financière, sous réserve que le copyright susmentionné apparaisse dans toutes les copies, que l’autorisation et le copyright susmentionnés apparaissent dans la documentation d’assistance, et que le nom « the Institute of Software, Academia Sinica » ne soit pas utilisé à des fins de publicité relative à la distribution du présent logiciel sans autorisation écrite spécifique et préalable. The Institute of Software, Academia Sinica ne garantit aucunement l’adéquation du présent logiciel aux objectifs visés. Il est fourni « tel quel », sans garantie expresse ou implicite. THE INSTITUTE OF SOFTWARE, ACADEMIA SINICA NE GARANTIT EN AUCUN CAS LE PRESENT LOGICIEL, Y COMPRIS TOUTES LES GARANTIES IMPLICITES DE QUALITE MARCHANDE ET D’ADEQUATION DU PROUIT ; EN AUCUN CAS THE INSTITUTE OF SOFTWARE, ACADEMIA SINICA NE POURRA ETRE TENU POUR RESPONSABLE DE DOMMAGES SPECIAUX, INDIRECTS OU CONSECUTIFS, OU DE DOMMAGES QUELS QU’ILS SOIENT, RESULTANT DE LA PERTE D’UTILISATION, DE DONNEES OU DE BENEFICES, QU’IL S’AGISSE D’UN CONTRAT, D’UNE NEGLIGENCE OU DE TOUTE AUTRE ACTION COMPLEXE, EMANANT DE OU FAISANT SUITE A L’UTILISATION DES PERFORMANCES DE CE LOGICIEL. © Copyright 1986-2000, Hwan Design Inc. Le présent avis vous octroie l’autorisation, selon l’ensemble des droits de propriété Hwan Design, d’utiliser, de copier, de modifier, d’accorder une sous-licence, de vendre et de redistribuer les 4 polices truetype outline Baekmuk à toutes fins utiles et sans restriction, sous réserve que le présent avis figure dans son intégralité sur toutes les copies desdites polices et que la marque commerciale de Hwan Design Int. soit Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 177 Annexe E : Licences de police reconnaissable (telle qu’illustrée ci-dessous) sur l’ensemble des copies des 4 polices Baekmuk truetype. BAEKMUK BATANG est une marque déposée de Hwan Design Inc. BAEKMUK GULIM est une marque déposée de Hwan Design Inc. BAEKMUK DOTUM est une marque déposée de Hwan Design Inc. BAEKMUK HEADLINE est une marque déposée de Hwan Design Inc. © Copyright 2000-2001 /efont/ The Electronic Font Open Laboratory. Tous droits réservés. La redistribution et l’utilisation sous forme source et binaire, avec ou sans modification, sont autorisées, sous réserve que les conditions suivantes soient remplies : La redistribution du code source doit contenir l’avis de copyright ci-dessus, cette liste de conditions et la clause de non-responsabilité suivante. La redistribution sous forme binaire doit reproduire l’avis de copyright ci-dessus, cette liste de conditions et la clause de non-responsabilité dans la documentation et/ou les autres matériaux fournis avec la distribution. Ni le nom de l’équipe, ni celui des collaborateurs la composant ne peuvent être utilisés pour faire de la publicité ou promouvoir des produits dérivés de cette police sans autorisation écrite spécifique et préalable. CETTE POLICE EST FOURNIE « TELLE QUELLE » PAR L’EQUIPE ET LES COLLABORATEURS LA COMPOSANT ET TOUTE GARANTIE EXPRESSE OU IMPLICITE, INCLUANT, MAIS SANS S’Y LIMITER, LES GARANTIES IMPLICITES QUANT A LA QUALITE MARCHANDE OU A L’ADEQUATION DU PRODUIT A DES USAGES PARTICULIERS, EST REJETEE. EN AUCUN CAS L’EQUIPE OU LES COLLABORATEURS LA COMPOSANT NE POURRONT ETRE TENUS POUR RESPONSABLES DE DOMMAGES DIRECTS, INDIRECTS, FORTUITS, SPECIAUX, EXEMPLAIRES OU CONSECUTIFS (INCLUANT, MAIS SANS S’Y LIMITER, L’OBTENTION DE BIENS OU SERVICES DE SUBSTITUTION, LA PERTE D’UTILISATION, DE DONNEES OU DE BENEFICES, OU L’INTERRUPTION COMMERCIALE), CAUSES DE QUELQUE MANIERE QUE CE SOIT, ET SELON TOUTE THEORIE DE RESPONSABILITE, QUE CE SOIT DANS LE 178 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Annexe E : Licences de police CADRE D’UN CONTRAT, DE LA STRICTE RESPONSABILITE OU DU TORT (Y COMPRIS LA NEGLIGENCE OU NON) EMANANT DE QUELQUE FACON QUE CE SOIT DE L’UTILISATION DE CETTE POLICE, MEME EN CAS DE CONNAISSANCE DE L’EVENTUALITE DE TELS DOMMAGES. Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 179 Annexe E : Licences de police 180 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Index AA ccessoires, 167 Acquisition de signaux, concepts de base, 29 Acquisition, affichage actif, 100 arrêt, 100 exemple monocoup, 53 ACQUISITION, bouton, 22, 97 Acquisition, menu, 97 Adaptateur GPIB, commande, 169 Adaptateur TEK-USB-488, commande, 169 connexion, 93 Affichage de signaux, 140 référence, 119 Affichage du pré-déclenchement, 131 Affichage, contraste, 109 intensité, 109 menu, 109 mesures, 11 mode XY, 110 mode Y(t), 110 persistance, 109 style (Inverser), 141 style des signaux, 110 type : vecteurs ou points, 109 AFFICHAGE, bouton, 22, 109 Agrandissement horizontal, fenêtre, 112 Ajouter des signaux, Math menu, 115 Alimentation, 3 spécifications, 157 Amplitude, curseurs, 36, 107 spectre FFT, 77 Assistant Test de sonde, sondes de tension, 5 Atténuation, sonde de tension, 5, 8, 142 Auto, mode de déclenchement, 128 AUTOSET, bouton, 23 Autoset, menu, 103 B Balayage de signaux, 114 Balayage retardé, 113 Balayage, échelle horizontale, 113 retardé, 113 Base de temps de la Fenêtre, 18 Base de temps principale, 18, 113 Base de temps retardée, 113 affichage, 13 Base de temps, 30 affichage, 13 Fenêtre, 18, 113 Principale, 18, 113 BMP, format de fichier, 87 Boucle de sécurité, 3 Bouton multifonctionnel, 20 Bouton TEST SONDE, 6 Boutons d’écran, xii Boutons d’option, xii Boutons du menu latéral, xii Boutons du panneau, xii Bruit crête-à-crête, 111 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 181 Index C Calendrier, 138 CALIBRAGE AUTO, bouton, 22 Calibrage Auto, menu, 101 Calibrage automatique, 9 Calibrage usine, 138 Calibrage, 137 programme automatique, 9 CH 1, CH2, CH 3 ou CH 4, boutons MENU, 17 connecteurs, 23 Commande VOLTS/DIV, 17 Communication, installation du logiciel OpenChoice, 89 Commutateur d’atténuation, 8 COMP SONDE, connexions, 24 Compensation, assistant Test de sonde de tension, 5 COMP SONDE, connecteur, 23 manuelle de sonde de tension, 7 Comptage de cycles d’alimentation, 137 CONF. PAR D., bouton, paramètres d’option conservés, 175 paramètres d’options et de commandes, 173 Configuration d’usine, 173 rappel, 126 Configuration par défaut, Déclenchement d’impulsions, 174 Déclenchement sur front, 174 Déclenchement vidéo, 174 rappel, 126 Connecteurs, CH 1, CH2, CH 3 et CH 4, 23 COMP SONDE, 23 EXTERNE, 23 port du lecteur flash USB, 79 Port périphérique USB, 89 Consignes de sécurité, iv Contraste, 110 Contrôle à distance à l’aide d’une interface GPIB, 93 Conventions utilisées dans ce manuel, xii Cordons d’alimentation, 3 commande, 168 Couplage CA, déclenchement, 128 vertical, 141 Couplage CC, déclenchement, 128 vertical, 141 Couplage masse, 141 Couplage, déclenchement, 28, 130 vertical, 141–142 Crête-à-crête, mesures, 117 CSV, format de fichier, 124 Curseurs de temps, 36, 107 Curseurs, Amplitude pour FFT, 107 Amplitude, 36, 107 concepts de base, 35 Fréquence pour FFT, 107 mesure d’un spectre FFT, 77 mesures, exemples, 45 réglage, 107 Temps, 36, 107 utilisation, 107 CURSEURS, bouton, 22, 107 Curseurs, menu, 107 182 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Index DD ate et heure, affichage, 14 Date, 138 Déclenchement sur front, 127 Déclenchement sur largeur d’impulsion, 132 Déclenchement sur temporisation, 155 Déclenchement vidéo, 131 exemple d’application, 58 Déclenchement, affichage de la fréquence, 14, 128, 133 affichage de la position, 13 affichage du niveau, 14 affichage, 19, 135 couplage, 28, 128, 130 définition, 27 état, 137 forcé, 135 front, 128 indicateur du type, 14 indicateurs d’état, 13 informations de pré-déclenchement, 131 inhibition, 19, 115, 135 marqueur de niveau, 13 marqueur de position, 13 menu, 127 modes : Auto, 128 modes : Normal, 128 modes, 28 niveau, 19, 29, 127 pente, 29, 128 polarité, 133 position, 28 source, 14, 28, 128, 132 synch., 132 types, 28 vidéo, 131–132 Delta, affichage dans le menu Curseurs, 108 Description, général, 1 Différences de phase, 111 Dossier courant, 82, 139 Dossiers, création, 139 renommer, 140 suppression, 134, 139 Double base de temps, 18, 113 E Echelle, horizontale, 31 sonde de courant, 9, 142 verticale, 30 EPSIMAGE, format de fichier, 87 Etat, divers, 137 système, 136 Etui souple, commande, 169 Evénements rares, persistance infinie, 111 Exemples d’application, acquisition d’un signal monocoup, 53 affichage des modifications d’impédance sur un réseau, 66 analyse d’un signal de communication différentiel, 64 analyse du détail du signal, 50 calcul du gain de l’amplificateur, 43 curseurs, utilisation, 45 déclenchement sur les lignes vidéo, 61 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 183 Index déclenchement sur les trames vidéo, 59 déclenchement sur un signal vidéo, 58 déclenchement sur une largeur d’impulsion spécifique, 56 Détect Créte, utilisation, 51 examen d’un signal bruyant, 51 fonction d’ajustement automatique pour examiner des points de test, 44 fonction de réglage automatique, utilisation, 39 mesure de deux signaux, 42 mesure de l’amplitude d’anneau, 45 mesure de la fréquence d’anneau, 45 mesure de la largeur d’impulsion, 47 mesure du retard de propagation, 55 mesure du temps de montée, 49 mesures automatiques, 38 moyenne, utilisation, 52 optimisation de l’acquisition, 54 prise de mesures automatiques, 40 prise de mesures par curseur, 45 réduction du bruit, 52 utilisation de la fonction de calibrage automatique (Autorange) pour examiner des points de test, 44 utilisation de la fonction fenêtre, 62 utilisation de la persistance, 68 utilisation du mode XY, 68 EXTERNE, connecteur, 23 compensation de sonde, 6 F Fenêtre FFT, Flattop, 74 Hanning, 74 Rectangular, 74 Fenêtre Flattop, 74 Fenêtre Hanning, 74 Fenêtre Rectangular, 74 Fenêtres, spectre FFT, 73 FFT zoom, horizontal, 72 vertical, 71 Figure de Lissajous, mode XY, 111 Fonctionnement normal, rappel de la configuration par défaut, 26 Fonctions d’ajustement automatique (Autorange), 26 désactivation, 102 présentation générale, 101 Fonctions de réglage automatique (Autoset), 26 Annuler, 105 bruit, 105 FFT, 105 impulsion carrée, 106 Niveau CC, 103 onde carrée, 106 ondes sinusoïdales, 105 présentation générale, 103 signal vidéo, 106 utilisation, 105 Fonctions mathématiques, FFT, 69, 71 fonctions, 115 menu, 115 Fonctions, présentation générale, 1 184 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Index FORCE TRIG, bouton, 19 Format, fichier d’image, 87 Lecteur flash USB, 81 Formats de fichier pour les images, 87 Formats des fichiers image, 87 Fréquence d’échantillonnage, maximum, 98 Fréquence, affichage de la fréquence de déclenchement, 14 affichage du déclenchement, 128 Fréquence, curseurs, 36 spectre FFT, 77 Fréquence, mesures, 117 à l’aide des curseurs, 45 Curseurs FFT, 77 HH istorique des erreurs, 137 HORIZ MENU, bouton, 18 Horizontal, état, 137 marqueur de position, 13 menu, 112 Mode Balayage, 100, 114 repliement du spectre, temporel, 31 Horizontale, échelle, 31 position, 31 Horloge, régler date et heure, 138 I Icônes, affichage de la base de temps de la fenêtre, 13 affichage de la date et de l’heure, 14 affichage de signal inversé, 13 affichage des signaux de référence, 14 base de temps, 13 déclenchement, affichage de la position, 13 déclenchement, affichage du niveau, 14 déclenchement, marqueur de niveau, 13 déclenchement, mesure de la fréquence, 14 déclenchement, source, 14 échelle de voies, 13 échelle verticale, 13 état du déclenchement, Acq. terminée, 13 état du déclenchement, Armé, 13 état du déclenchement, Arrêt, 13 état du déclenchement, Déclenché, 13 état du déclenchement, mode Auto, 13 état du déclenchement, mode Balayage, 13 état du déclenchement, Prêt, 13 Limite de bande passante, 13 marqueur de position de déclenchement, 13 marqueur de position horizontale, 13 Marqueur de référence, 13 modes d’acquisition, Détect Créte, 12 modes d’acquisition, Moyenne, 12 modes d’acquisition, Normale, 12 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 185 Index type de déclenchement, Front, 14 type de déclenchement, Largeur d’impulsion, 14 type de déclenchement, Vidéo, 14 Image d’écran, enregistrement dans un fichier, 87 envoi à une imprimante, 95 Impression, données de l’écran, 118 image d’écran, 95 suspendre, 95, 118 Imprimante, Compatible PictBridge, 94 configuration, 95 connexion, 94 Impulsion carrée, Fonction de réglage automatique (Autoset), 106 Impulsion de synch., 132 Index des rubriques d’aide, xi Indicateurs, 12 Inhibition, 115, 135 INHIBITION, commande, 19 Installation, Logiciel OpenChoice sur un PC, 89 Intensité, 109 Interpolation, 98 J JPG, format de fichier, 87 L Langues, 137 Largeur négative, mesures, 117 Largeur positive, mesures, 117 Lecteur flash USB, capacité de stockage, 81 emplacement du port, 24 formatage, 81 gestion des fichiers, 82 indicateur d’opération de sauvegarde, 80 installation, 80 PRINT, touche, 85 Sauv./Rap, menu, 83 sauvegarde de fichiers, configurations, 85 sauvegarde de fichiers, images, 87 sauvegarde de fichiers, signaux, 85 sauvegarde de fichiers, tous, 85 Utilitaires Fichiers, 139 Liens hypertexte dans les rubriques d’aide, xi Ligne, déclenchement vidéo, 131 Lignes diagonales dans le signal, Détect Créte, 99 Limite Bande verticale, 141 Limite de bande passante, affichage, 13 déclenchement, 128 vertical, 141 Logiciel, OpenChoice, 167 M M, indicateur de base de temps principale, 113 Manuel d’entretien, commande, 168 Manuel de programmation, commande, 168 Manuels de la sonde, commande, Sonde passive P2220 1X/10X, 167 186 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Index Manuels, commande, 168 MATH MENU, bouton, 18 Maximum, mesures, 117 Mémoire non volatile, fichiers de configuration, 121 fichiers de signal de référence, 121 Mémoire, configurations, 120 images d’écran, 120 Lecteur flash USB, 79 signaux, 120 Menu Réf, 119 Menus, Acquisition, 97 Affichage, 109 Aide, 112 Calibrage Auto, 101 Curseurs, 107 Déclenchement, 127 Fonctions mathématiques FFT, 71 Fonctions mathématiques, 115 Horizontal, 112 Imprimer, 118 Mesures, 116 Réf, 119 Réglage automatique (Autoset), 103 Sauv./Rap, 120 Utilitaire, 136 Vertical, 140 Messages utiles, 14 Messages, 14–15 Mesures automatiques, 116 concepts de base, 36 Mesures d’amplitude, à l’aide des curseurs, 45 Mesures de la largeur d’impulsion, à l’aide des curseurs, 47 Mesures efficaces du cycle, 117 Mesures efficaces, 117 Mesures, automatiques, 36, 116 concepts de base, 35 crête-à-crête, 117 curseur, 35, 45 FFT (fonctions mathématiques), 72 fréquence, 117 général, 11 largeur négative, 117 largeur positive, 117 maximum, 117 minimum, 117 moyenne, 117 période, 117 réticule, 35 spectre FFT, 77 temps de descente, 117 temps de montée, 117 types, 117 valeur efficace du cycle, 117 MESURES, bouton, 22 Mesures, menu, 116 Minimum, mesures, 117 Mise à jour du firmware, Internet, xi Mise à l’échelle de signaux, concepts de base, 30 Mise en mémoire, paramètres de configuration, 26 Mise en mémoire, menu, 124 Mises à jour du micrologiciel, 140 Mode Balayage, 100, 114 Mode d’acquisition Détect Créte, 30, 98 Mode d’acquisition Moyenne, 30, 99 Mode d’acquisition Normale, 29, 97 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 187 Index Mode Défilement, Voir Mode Balayage Mode Détect Créte, 97 icône, 12 Mode Moyenne, icône, 12 Mode Normale, icône, 12 Mode, affichage, 110 Modes d’acquisition, 29, 97 Détect Créte, 30, 98 indicateurs, 12 Moyenne, 30, 99 Normale, 29, 97 Moyenne, mode d’acquisition, 97 Moyenne, mesure, 117 Multiplier des signaux, Math menu, 115 N Navigation, système de fichiers, 139 Nettoyage, 171 NIVEAU A 50%, bouton, 19 Niveau, 19, 29 NIVEAU, commande, 19 Noms des boutons, xii Normal, mode de déclenchement, 128 NTSC, standard vidéo, 131 Nyquist, fréquence, 71 O Onde carrée, Fonction de réglage automatique (Autoset), 106 Ondes sinusoïdales, Fonction de réglage automatique (Autoset), 105 OpenChoice, logiciel, 167 installation, 89 Option de la touche PRINT, 121 sauvegarde vers un lecteur flash USB, 85 Option Exécuter Auto-cal, 9 Oscilloscope, compréhension des fonctions, 25 connexion à un PC, 90 connexion à un système GPIB, 93 connexion à une imprimante, 94 panneaux avant, 11 régler date et heure, 138 spécifications, 145 P PAL, standard vidéo, 131 Panning, horizontale, 31 verticale, 30 PC, connexion à un oscilloscope, 90 PCX, format de fichier, 87 Pente, 29 Période, mesures, 117 Persistance, 109, 111 Points, type d’affichage, 109 Polarité, déclenchement sur largeur d’impulsion, 133 Synch. déclenchement vidéo, 131 port du lecteur flash USB, 79 Port périphérique USB, 89 Ports, Lecteur flash USB, 79 188 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Index Position, déclenchement, 131 horizontal, 112 horizontale, 31 vertical, 140 POSITION, commande, horizontal, 18 verticale, 17 Pré-déclenchement, 27 PRINT, touche, 23, 118 R Rappel config., menu, 125 Rappel signal, menu, 125 Rappel, configurations, 126 paramètres de configuration, 26 signaux, 126 Rappeler, configuration d’usine (par défaut), 26 Réduction du bruit, couplage déclenchement, 128 limite de bande passante verticale, 141 Mode Moyenne, 97 Soustraction mathématique, 115 REF, bouton, 22 Référence, borne de la sonde, 5 borne, 24 câble de masse de la sonde, 5 marqueur, 13 Refroidissement par convection, 3 Réglages, concepts de base, 25 sauvegarde et rappel, 120 Régler date et heure, 138 REGLER SUR 0, bouton, 18 Renommer des fichiers ou dossiers, 140 Répertoires, suppression, 134, 139 Repliement du spectre FFT, 75 solutions, 76 Repliement du spectre, contrôle, 33 FFT, 75 temporel, 31 Résolution approximative, 141 Résolution précise, 141 Résolution, fine, 142 Réticule, 35, 109 RLE, format de fichier, 87 Rubriques de l’aide contextuelle, x RUN/STOP, bouton, 23, 99 étapes effectuées par l’oscilloscope lorsque vous appuyez sur ce bouton, 27 S SAUV. vers un lecteur flash USB, 80 SAUV./RAP, bouton, 22 Sauv./Rap, menu, 120 sauvegarde vers un lecteur flash USB, 83 Sauveg. tot., menu, 121 Sauvegarde config., menu, 123 Sauvegarde image, menu, 122 Sauvegarde, configurations, 126 fichiers image vers un lecteur flash USB, 87 signaux, 126 tous les fichiers vers un lecteur flash USB, 85 SEC/DIV, commande, 18, 114 SECAM, standard vidéo, 131 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 189 Index SEQ. UNIQUE, bouton, 100 étapes effectuées par l’oscilloscope lorsque vous appuyez sur ce bouton, 27 Service, historique des erreurs comme référence, 137 signal calculé, unités autorisées, 116 Signal inversé, affichage, 13 Signal monocoup, exemple d’application, 53 Signal vidéo, Fonction de réglage automatique (Autoset), 106 Signaux de référence, affichage et suppression, 119 affichage, 14 sauvegarde et rappel, 126 Signaux, acquisition de données, 29 balayage, 100 compression, 114 échelle, 30 expansion, 114 numérisé, 29 position, 30 prendre des mesures, 35 signification du style d’affichage, 110 supprimer de l’écran, 143 temporel, 69 Sonde, option, correspondre à l’atténuation de la sonde, 8 correspondre à l’échelle de la sonde de courant, 9 Sondes de courant, réglage de l’échelle, 9, 142 Sondes, assistant Test de sonde de tension, 5 Commutateur d’atténuation, 8 compensation manuelle d’une sonde de tension, 7 compensation, 24 courant et échelle, 9 sécurité, 5 spécifications, 163 tension et atténuation, 142 Source, déclenchement, 28, 128, 131–132 Ext., 129 Ext/5, 130 Secteur, 131 Soustraire des signaux, Math menu, 115 Spécifications relatives à la sonde P2220, 163 Spécifications, oscilloscope, 145 Sonde P2200, 163 spectre FFT, affichage, 71 agrandissement, 76 applications, 69 Fenêtre, 73 Fréquence de Nyquist, 71 mesure de l’amplitude et de la fréquence à l’aide des curseurs, 77 mesures, 72 processus, 69 Stockage amovible de fichiers, Lecteur flash USB, 79 Suppression de fichiers ou dossiers, 134 190 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B Index Suppression de signaux de référence, 119 Suppression de signaux, 140 Suppression, fichiers ou dossiers, 139 Suspendre impression, 95, 118 Synch., déclenchement vidéo ligne ou trame, 132 polarité vidéo, 131 Système d’aide, x Système de menus, utilisation, 15 Système GPIB, connexion à un oscilloscope, 93 T Temporel, signal, 69 Temps de descente, mesures, 117 Temps de montée, mesures, à l’aide des curseurs, 49 automatiques, 117 Test de fonctionnement, 4 TIFF, format de fichier, 87 Touches programmables, xii Trame, déclenchement vidéo, 132 TRIG MENU, bouton, 19 TRIG VIEW, bouton, 19 Types d’options, Action, 16 Liste circulaire, 16 Radio, 16 Sélection de page, 16 UU TILITAIRE, bouton, 22 Utilitaire, menus, 136 Utilitaires Fichiers, 139 Contenu du lecteur flash USB, 139 création de fichiers ou dossiers, 139 navigation dans la structure de répertoires, 139 renommer des fichiers ou dossiers, 140 sélection de fichiers ou dossiers, 139 suppression de fichiers ou dossiers, 134, 139 V Valise de transport, commande, 169 Vecteurs, 109 Ventilation, 3 Vertical, bouton de position, 17 état, 137 menu, 140 Verticale, échelle, 31 position, 30 Voie, couplage, 141 échelle, 13 menu, 141 Volts/Div, Fin, 141 Gros, 141 Voyant LED Liste aide, x W W, indicateur de base de temps retardée, 113 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B 191 Index X XY, exemple d’application, 67 mode d’affichage, 110–111 Y Y(t), mode d’affichage, 110 ZZ one retardée, 113–114 Zoom, 62 FFT, 76 HORIZ menu, 112 Zone retardée, 112–114 192 Manuel de l’utilisateur de l’oscilloscope TDS1000B/2000B http://www.farnell.com/datasheets/43798.pdf http://www.farnell.com/datasheets/43798.pdf 2010 Microchip Technology Inc. DS41302D PIC12F609/615/617 PIC12HV609/615 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. DS41302D-page 2 2010 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. DS41302D-page 3 PIC12F609/615/617/12HV609/615 High-Performance RISC CPU: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes Special Microcontroller Features: • Precision Internal Oscillator: - Factory calibrated to ±1%, typical - Software selectable frequency: 4 MHz or 8 MHz • Power-Saving Sleep mode • Voltage Range: - PIC12F609/615/617: 2.0V to 5.5V - PIC12HV609/615: 2.0V to user defined maximum (see note) • Industrial and Extended Temperature Range • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Brown-out Reset (BOR) • Watchdog Timer (WDT) with independent Oscillator for Reliable Operation • Multiplexed Master Clear with Pull-up/Input Pin • Programmable Code Protection • High Endurance Flash: - 100,000 write Flash endurance - Flash retention: > 40 years • Self Read/ Write Program Memory (PIC12F617 only) Low-Power Features: • Standby Current: - 50 nA @ 2.0V, typical • Operating Current: - 11A @ 32 kHz, 2.0V, typical - 260A @ 4 MHz, 2.0V, typical • Watchdog Timer Current: - 1A @ 2.0V, typical Note: Voltage across the shunt regulator should not exceed 5V. Peripheral Features: • Shunt Voltage Regulator (PIC12HV609/615 only): - 5 volt regulation - 4 mA to 50 mA shunt range • 5 I/O Pins and 1 Input Only • High Current Source/Sink for Direct LED Drive - Interrupt-on-pin change or pins - Individually programmable weak pull-ups • Analog Comparator module with: - One analog comparator - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and output externally accessible - Built-In Hysteresis (software selectable) • Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Timer1 Gate (count enable) - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected - Option to use system clock as Timer1 • In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins PIC12F615/617/HV615 ONLY: • Enhanced Capture, Compare, PWM module: - 16-bit Capture, max. resolution 12.5 ns - Compare, max. resolution 200 ns - 10-bit PWM with 1 or 2 output channels, 1 output channel programmable “dead time,” max. frequency 20 kHz, auto-shutdown • A/D Converter: - 10-bit resolution and 4 channels, samples internal voltage references • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers PIC12F609/615/617/12HV609/615 DS41302D-page 4 2010 Microchip Technology Inc. 8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN) TABLE 1: PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, MSOP, DFN) Device Program Memory Data Memory Self Read/ Self Write I/O 10-bit A/D (ch) Comparators ECCP Timers 8/16-bit Voltage Range Flash (words) SRAM (bytes) PIC12F609 1024 64 — 5 0 1 — 1/1 2.0V-5.5V PIC12HV609 1024 64 — 5 0 1 — 1/1 2.0V-user defined PIC12F615 1024 64 — 5 4 1 YES 2/1 2.0V-5.5V PIC12HV615 1024 64 — 5 4 1 YES 2/1 2.0V-user defined PIC12F617 2048 128 YES 5 4 1 YES 2/1 2.0V-5.5V I/O Pin Comparators Timer Interrupts Pull-ups Basic GP0 7 CIN+ — IOC Y ICSPDAT GP1 6 CIN0- — IOC Y ICSPCLK GP2 5 COUT T0CKI INT/IOC Y — GP3(1) 4 — — IOC Y(2) MCLR/VPP GP4 3 CIN1- T1G IOC Y OSC2/CLKOUT GP5 2 — T1CKI IOC Y OSC1/CLKIN — 1 — — — — VDD — 8 — — — — VSS Note 1: Input only. 2: Only when pin is configured for external MCLR. 1 2 3 4 5 6 7 8 PIC12F609/ HV609 VSS GP0/CIN+/ICSPDAT GP1/CIN0-/ICSPCLK GP2/T0CKI/INT/COUT VDD GP5/T1CKI/OSC1/CLKIN GP4/CIN1-/T1G/OSC2/CLKOUT GP3/MCLR/VPP 2010 Microchip Technology Inc. DS41302D-page 5 PIC12F609/615/617/12HV609/615 8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN) TABLE 2: PIC12F615/617/HV615 PIN SUMMARY (PDIP, SOIC, MSOP, DFN) I/O Pin Analog Comparator s Timer CCP Interrupts Pull-ups Basic GP0 7 AN0 CIN+ — P1B IOC Y ICSPDAT GP1 6 AN1 CIN0- — — IOC Y ICSPCLK/VREF GP2 5 AN2 COUT T0CKI CCP1/P1A INT/IOC Y — GP3(1) 4 — — T1G* — IOC Y(2) MCLR/VPP GP4 3 AN3 CIN1- T1G P1B* IOC Y OSC2/CLKOUT GP5 2 — — T1CKI P1A* IOC Y OSC1/CLKIN — 1 — — — — — — VDD — 8 — — — — — — VSS * Alternate pin function. Note 1: Input only. 2: Only when pin is configured for external MCLR. 1 2 3 4 5 6 7 8 PIC12F615/ 617/HV615 VSS GP0/AN0/CIN+/P1B/ICSPDAT GP1/AN1/CIN0-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/P1A VDD GP5/T1CKI/P1A*/OSC1/CLKIN GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT GP3/T1G*/MCLR/VPP * Alternate pin function. PIC12F609/615/617/12HV609/615 DS41302D-page 6 2010 Microchip Technology Inc. Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................ 11 3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only).................................................................................. 27 4.0 Oscillator Module ....................................................................................................................................................................... 37 5.0 I/O Port ...................................................................................................................................................................................... 43 6.0 Timer0 Module .......................................................................................................................................................................... 53 7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57 8.0 Timer2 Module (PIC12F615/617/HV615 only) .......................................................................................................................... 65 9.0 Comparator Module ................................................................................................................................................................... 67 10.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/617/HV615 only) ............................................................................... 79 11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) ............... 89 12.0 Special Features of the CPU ................................................................................................................................................... 107 13.0 Voltage Regulator .................................................................................................................................................................... 127 14.0 Instruction Set Summary ........................................................................................................................................................ 129 15.0 Development Support ............................................................................................................................................................. 139 16.0 Electrical Specifications ........................................................................................................................................................... 143 17.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 171 18.0 Packaging Information ............................................................................................................................................................ 195 Appendix A: Data Sheet Revision History ......................................................................................................................................... 203 Appendix B: Migrating from other PIC® Devices ............................................................................................................................... 203 Index ................................................................................................................................................................................................. 205 The Microchip Web Site .................................................................................................................................................................... 209 Customer Change Notification Service ............................................................................................................................................. 209 Customer Support ............................................................................................................................................................................. 209 Reader Response ............................................................................................................................................................................. 210 Product Identification System ............................................................................................................................................................ 211 Worldwide Sales and Service ........................................................................................................................................................... 212 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. DS41302D-page 7 PIC12F609/615/617/12HV609/615 1.0 DEVICE OVERVIEW The PIC12F609/615/617/12HV609/615 devices are covered by this data sheet. They are available in 8-pin PDIP, SOIC, MSOP and DFN packages. Block Diagrams and pinout descriptions of the devices are as follows: • PIC12F609/HV609 (Figure 1-1, Table 1-1) • PIC12F615/617/HV615 (Figure 1-2, Table 1-2) FIGURE 1-1: PIC12F609/HV609 BLOCK DIAGRAM Flash Program Memory 13 Data Bus 8 Program 14 Bus Instruction Reg Program Counter RAM File Registers Direct Addr 7 RAM Addr 9 Addr MUX Indirect Addr FSR Reg STATUS Reg MUX ALU W Reg Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT GPIO 8 8 8 3 8-Level Stack 64 Bytes 1K X 14 (13-Bit) Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer MCLR VSS Brown-out Reset Timer0 Timer1 GP0 GP1 GP2 GP3 GP4 GP5 Analog Comparator T0CKI INT T1CKI Configuration Internal Oscillator and Reference T1G VDD Block CIN+ CIN0- CIN1- COUT Comparator Voltage Reference Absolute Voltage Reference Shunt Regulator (PIC12HV609 only) PIC12F609/615/617/12HV609/615 DS41302D-page 8 2010 Microchip Technology Inc. FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM Flash Program Memory 13 Data Bus 8 Program 14 Bus Instruction Reg Program Counter RAM File Registers Direct Addr 7 RAM Addr 9 Addr MUX Indirect Addr FSR Reg STATUS Reg MUX ALU W Reg Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT GPIO 8 8 8 3 8-Level Stack 64 Bytes and 1K X 14 (13-Bit) Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer MCLR VSS Brown-out Reset Timer0 Timer1 GP0 GP1 GP2 GP3 GP4 GP5 Analog Comparator T0CKI INT T1CKI Configuration Internal Oscillator VREF and Reference T1G VDD Timer2 Block Shunt Regulator (PIC12HV615 only) Analog-To-Digital Converter AN0 AN1 AN2 AN3 CIN+ CIN0- CIN1- COUT ECCP CCP1/P1A P1B P1A* P1B* Comparator Voltage Reference Absolute Voltage Reference * Alternate pin function. ** For the PIC12F617 only. T1G* 2K X 14** and 128 Bytes** 2010 Microchip Technology Inc. DS41302D-page 9 PIC12F609/615/617/12HV609/615 TABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION Name Function Input Type Output Type Description GP0/CIN+/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change CIN+ AN — Comparator non-inverting input ICSPDAT ST CMOS Serial Programming Data I/O GP1/CIN0-/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change CIN0- AN — Comparator inverting input ICSPCLK ST — Serial Programming Clock GP2/T0CKI/INT/COUT GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-change T0CKI ST — Timer0 clock input INT ST — External Interrupt COUT — CMOS Comparator output GP3/MCLR/VPP GP3 TTL — General purpose input with interrupt-on-change MCLR ST — Master Clear w/internal pull-up VPP HV — Programming voltage GP4/CIN1-/T1G/OSC2/ CLKOUT GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change CIN1- AN — Comparator inverting input T1G ST — Timer1 gate (count enable) OSC2 — XTAL Crystal/Resonator CLKOUT — CMOS FOSC/4 output GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change T1CKI ST — Timer1 clock input OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection VDD VDD Power — Positive supply VSS VSS Power — Ground reference Legend: AN=Analog input or output CMOS= CMOS compatible input or output HV= High Voltage ST=Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL=Crystal PIC12F609/615/617/12HV609/615 DS41302D-page 10 2010 Microchip Technology Inc. TABLE 1-2: PIC12F615/617/HV615 PINOUT DESCRIPTION Name Function Input Type Output Type Description GP0/AN0/CIN+/P1B/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-onchange AN0 AN — A/D Channel 0 input CIN+ AN — Comparator non-inverting input P1B — CMOS PWM output ICSPDAT ST CMOS Serial Programming Data I/O GP1/AN1/CIN0-/VREF/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and interrupt-onchange AN1 AN — A/D Channel 1 input CIN0- AN — Comparator inverting input VREF AN — External Voltage Reference for A/D ICSPCLK ST — Serial Programming Clock GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-onchange AN2 AN — A/D Channel 2 input T0CKI ST — Timer0 clock input INT ST — External Interrupt COUT — CMOS Comparator output CCP1 ST CMOS Capture input/Compare input/PWM output P1A — CMOS PWM output GP3/T1G*/MCLR/VPP GP3 TTL — General purpose input with interrupt-on-change T1G* ST — Timer1 gate (count enable), alternate pin MCLR ST — Master Clear w/internal pull-up VPP HV — Programming voltage GP4/AN3/CIN1-/T1G/P1B*/OSC2/ CLKOUT GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-onchange AN3 AN — A/D Channel 3 input CIN1- AN — Comparator inverting input T1G ST — Timer1 gate (count enable) P1B* — CMOS PWM output, alternate pin OSC2 — XTAL Crystal/Resonator CLKOUT — CMOS FOSC/4 output GP5/T1CKI/P1A*/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-onchange T1CKI ST — Timer1 clock input P1A* — CMOS PWM output, alternate pin OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection VDD VDD Power — Positive supply VSS VSS Power — Ground reference * Alternate pin function. Legend: AN=Analog input or output CMOS=CMOS compatible input or output HV= High Voltage ST=Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL=Crystal 2010 Microchip Technology Inc. DS41302D-page 11 PIC12F609/615/617/12HV609/615 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC12F609/615/617/12HV609/615 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h- 03FFh) for the PIC12F609/615/12HV609/615 is physically implemented. For the PIC12F617, the first 2K x 14 (0000h-07FFh) is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space for PIC12F609/615/12HV609/615 devices, and within the first 2K x 14 space for the PIC12F617 device. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC12F609/615/12HV609/615 FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR THE PIC12F617 2.2 Data Memory Organization The data memory (see Figure 2-3) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM. For the PIC12F617, the register locations 20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general purpose registers implemented as Static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. The RP0 bit of the STATUS register is the bank select bit. RP0 0 Bank 0 is selected 1 Bank 1 is selected PC<12:0> 13 0000h 0004h 0005h 03FFh 0400h 1FFFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory CALL, RETURN RETFIE, RETLW Stack Level 2 Wraps to 0000h-03FFh Note: The IRP and RP1 bits of the STATUS register are reserved and should always be maintained as ‘0’s. PC<12:0> 13 0000h 0004h 0005h 07FFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector CALL, RETURN RETFIE, RETLW Stack Level 2 Page 0 On-Chip Program Memory Wraps to 0000h-07FFh 0800h 1FFFh PIC12F609/615/617/12HV609/615 DS41302D-page 12 2010 Microchip Technology Inc. 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the PIC12F609/615/12HV609/615, and as 128 x 8 in the PIC12F617. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. FIGURE 2-3: DATA MEMORY MAP OF THE PIC12F609/HV609 Indirect Addr.(1) TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. General File Address File Address WPU IOC Indirect Addr.(1) OPTION_REG PCL STATUS FSR TRISIO PCLATH INTCON PIE1 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h FFh Bank 1 ANSEL Accesses 70h-7Fh F0h VRCON CMCON0 OSCTUNE 40h 3Fh CMCON1 EFh T1CON Purpose Registers 64 Bytes Accesses 70h-7Fh 6Fh 70h 2010 Microchip Technology Inc. DS41302D-page 13 PIC12F609/615/617/12HV609/615 FIGURE 2-4: DATA MEMORY MAP OF THE PIC12F615/617/HV615 Indirect Addr.(1) TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H T1CON 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. 2: Used for the PIC12F617 only. File Address File Address WPU IOC Indirect Addr.(1) OPTION_REG PCL STATUS FSR TRISIO PCLATH INTCON PIE1 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h FFh Bank 1 ADRESH ADCON0 ADRESL ANSEL Accesses 70h-7Fh F0h TMR2 T2CON CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS VRCON CMCON0 OSCTUNE PR2 40h 3Fh CMCON1 EFh APFCON General Purpose Registers 64 Bytes Accesses 70h-7Fh 6Fh 70h PMCON1 (2) PMCON2 (2) PMADRL (2) PMADRH (2) PMDATL (2) PMDATH (2) General Purpose Registers 96 Bytes from 20h-7Fh(2) Unimplemented for PIC12F615/HV615 General Purpose Registers 32 Bytes(2) Unimplemented for PIC12F615/HV615 BFh C0h PIC12F609/615/617/12HV609/615 DS41302D-page 14 2010 Microchip Technology Inc. TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 115 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 115 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 115 03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 18, 115 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 115 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 115 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 115 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 20, 115 0Ch PIR1 — — — — CMIF — — TMR1IF ---- 0--0 22, 115 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 62, 115 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h VRCON CMVREN — VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116 1Ah CMCON0 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -0-0 72, 116 1Bh — — — — — 1Ch CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 73, 116 1Dh — Unimplemented — — 1Eh — Unimplemented — — 1Fh — Unimplemented — — Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: Read only register. 2010 Microchip Technology Inc. DS41302D-page 15 PIC12F609/615/617/12HV609/615 TABLE 2-2: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 116 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116 03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 18, 116 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 116 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 20, 116 0Ch PIR1 — ADIF CCP1IF — CMIF — TMR2IF TMR1IF -00- 0-00 22, 116 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 116 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 116 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 62, 116 11h TMR2(3) Timer2 Module Register 0000 0000 65, 116 12h T2CON(3) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 66, 116 13h CCPR1L(3) Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 90, 116 14h CCPR1H(3) Capture/Compare/PWM Register 1 High Byte XXXX XXXX 90, 116 15h CCP1CON(3) P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 89, 116 16h PWM1CON(3) PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 105, 116 17h ECCPAS(3) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 102, 116 18h — Unimplemented — — 19h VRCON CMVREN — VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116 1Ah CMCON0 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -0-0 72, 116 1Bh — — — — — 1Ch CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 73, 116 1Dh — Unimplemented — — 1Eh ADRESH(2, 3) Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 85, 116 1Fh ADCON0(3) ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 84, 116 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: Read only register. 3: PIC12F615/617/HV615 only. PIC12F609/615/617/12HV609/615 DS41302D-page 16 2010 Microchip Technology Inc. TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 81h OPTION_RE G GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19, 116 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116 83h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 18, 116 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF(3) 0000 0000 20, 116 8Ch PIE1 — — — — CMIE — — TMR1IE ---- 0--0 21, 116 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --qq 23, 116 8Fh — Unimplemented — — 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU(2) — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 46, 116 96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ANSEL — — — — ANS3 — ANS1 ANS0 ---- 1-11 45, 117 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. 4: TRISIO3 always reads as ‘1’ since it is an input only pin. 2010 Microchip Technology Inc. DS41302D-page 17 PIC12F609/615/617/12HV609/615 TABLE 2-4: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19, 116 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116 83h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 18, 116 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF(3) 0000 0000 20, 116 8Ch PIE1 — ADIE CCP1IE — CMIE — TMR2IE TMR1IE -00- 0-00 21, 116 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --qq 23, 116 8Fh — Unimplemented — — 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116 91h — Unimplemented — — 92h PR2 Timer2 Module Period Register 1111 1111 65, 116 93h APFCON — — — T1GSEL — — P1BSEL P1ASEL ---0 --00 21, 116 94h — Unimplemented — — 95h WPU(2) — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 46, 116 96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116 97h — Unimplemented — — 98h PMCON1(7) — — — — — WREN WR RD ---- -000 29 99h PMCON2(7) Program Memory Control Register 2 (not a physical register). ---- ---- — 9Ah PMADRL(7) PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 28 9Bh PMADRH(7) — — — — — PMADRH2 PMADRH1 PMADRH0 ---- -000 28 9Ch PMDATL(7) PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 28 9Dh PMDATH(7) — — Program Memory Data Register High Byte. --00 0000 28 9Eh ADRESL(5, 6) Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 85, 117 9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 45, 117 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. 4: TRISIO3 always reads as ‘1’ since it is an input only pin. 5: Read only register. 6: PIC12F615/617/HV615 only. 7: PIC12F617 only. PIC12F609/615/617/12HV609/615 DS41302D-page 18 2010 Microchip Technology Inc. 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (RAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the Section 14.0 “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC12F609/615/617/ 12HV609/615 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. REGISTER 2-1: STATUS: STATUS REGISTER Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h – FFh) 0 = Bank 0 (00h – 7Fh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2010 Microchip Technology Inc. DS41302D-page 19 PIC12F609/615/617/12HV609/615 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • Timer0/WDT prescaler • External GP2/INT interrupt • Timer0 • Weak pull-ups on GPIO Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 6.1.3 “Software Programmable Prescaler”. REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 BIT VALUE TIMER0 RATE WDT RATE PIC12F609/615/617/12HV609/615 DS41302D-page 20 2010 Microchip Technology Inc. 2.2.2.3 INTCON Register The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO change and external GP2/INT pin interrupts. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GIE PEIE T0IE INTE GPIE T0IF INTF GPIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt bit 3 GPIE: GPIO Change Interrupt Enable bit(1) 1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow bit 1 INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur bit 0 GPIF: GPIO Change Interrupt Flag bit 1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software) 0 = None of the GPIO <5:0> pins have changed state Note 1: IOC register must also be enabled. 2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. 2010 Microchip Technology Inc. DS41302D-page 21 PIC12F609/615/617/12HV609/615 2.2.2.4 PIE1 Register The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 2-4. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit(1) 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 CCP1IE: CCP1 Interrupt Enable bit(1) 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 4 Unimplemented: Read as ‘0’ bit 3 CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1) 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’. PIC12F609/615/617/12HV609/615 DS41302D-page 22 2010 Microchip Technology Inc. 2.2.2.5 PIR1 Register The PIR1 register contains the Peripheral Interrupt flag bits, as shown in Register 2-5. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Interrupt Flag bit(1) 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started bit 5 CCP1IF: CCP1 Interrupt Flag bit(1) Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit 1 = Comparator output has changed (must be cleared in software) 0 = Comparator output has not changed bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1) 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’. 2010 Microchip Technology Inc. DS41302D-page 23 PIC12F609/615/617/12HV609/615 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-6. REGISTER 2-6: PCON: POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0(1) — — — — — — POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled. PIC12F609/615/617/12HV609/615 DS41302D-page 24 2010 Microchip Technology Inc. 2.2.2.7 APFCON Register (PIC12F615/617/HV615 only) The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. For this device, the P1A, P1B and Timer1 Gate functions can be moved between different pins. The APFCON register bits are shown in Register 2-7. REGISTER 2-7: APFCON:ALTERNATE PIN FUNCTION REGISTER(1) U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — — T1GSEL — — P1BSEL P1ASEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1GSEL: TMR1 Input Pin Select bit 1 = T1G function is on GP3/T1G(2)/MCLR/VPP 0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT bit 3-2 Unimplemented: Read as ‘0’ bit 1 P1BSEL: P1B Output Pin Select bit 1 = P1B function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT 0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT bit 0 P1ASEL: P1A Output Pin Select bit 1 = P1A function is on GP5/T1CKI/P1A(2)/OSC1/CLKIN 0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A Note 1: PIC12F615/617/HV615 only. 2: Alternate pin function. 2010 Microchip Technology Inc. DS41302D-page 25 PIC12F609/615/617/12HV609/615 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). FIGURE 2-5: LOADING OF PC IN DIFFERENT SITUATIONS 2.3.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556). 2.3.2 STACK The PIC12F609/615/617/12HV609/615 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 2.4 Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-6. A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 2-1. EXAMPLE 2-1: INDIRECT ADDRESSING PC 12 8 7 0 5 PCLATH<4:0> PCLATH Instruction with ALU Result GOTO, CALL OPCODE <10:0> 8 PC 12 11 10 0 PCLATH<4:3> 11 PCH PCL 8 7 2 PCLATH PCH PCL PCL as Destination Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. MOVLW 0x40 ;initialize pointer MOVWF FSR ;to RAM NEXT CLRF INDF ;clear INDF register INCF FSR ;inc pointer BTFSS FSR,7 ;all done? GOTO NEXT ;no clear next CONTINUE ;yes continue PIC12F609/615/617/12HV609/615 DS41302D-page 26 2010 Microchip Technology Inc. FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615 Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in this area are mirrored back into Bank 0 and Bank 1. Data Memory Direct Addressing Indirect Addressing Bank Select Location Select RP1(1) RP0 6 From Opcode 0 IRP(1) 7 File Select Register 0 Bank Select Location Select 00 01 10 11 180h 1FFh 00h 7Fh Bank 0 Bank 1 Bank 2 Bank 3 NOT USED(2) For memory map detail, see Figure 2-3. 2010 Microchip Technology Inc. DS41302D-page 27 PIC12F609/615/617/12HV609/615 3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY) The Flash program memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5). There are six SFRs used to read and write this memory: • PMCON1 • PMCON2 • PMDATL • PMDATH • PMADRL • PMADRH When interfacing the program memory block, the PMDATL and PMDATH registers form a two-byte word which holds the 14-bit data for read/write, and the PMADRL and PMADRH registers form a two-byte word which holds the 13-bit address of the Flash location being accessed. These devices have 2K words of program Flash with an address range from 0000h to 07FFh. The program memory allows single word read and a by four word write. A four word write automatically erases the row of the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. When the device is code-protected, the CPU may continue to read and write the Flash program memory. Depending on the settings of the Flash Program Memory Enable (WRT<1:0>) bits, the device may or may not be able to write certain blocks of the program memory, however, reads of the program memory are allowed. When the Flash program memory Code Protection (CP) bit in the Configuration Word register is enabled, the program memory is code-protected, and the device programmer (ICSP™) cannot access data or program memory. 3.1 PMADRH and PMADRL Registers The PMADRH and PMADRL registers can address up to a maximum of 8K words of program memory. When selecting a program address value, the Most Significant Byte (MSB) of the address is written to the PMADRH register and the Least Significant Byte (LSB) is written to the PMADRL register. 3.2 PMCON1 and PMCON2 Registers PMCON1 is the control register for the data program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. PMCON2 is not a physical register. Reading PMCON2 will read all ‘0’s. The PMCON2 register is used exclusively in the Flash memory write sequence. PIC12F609/615/617/12HV609/615 DS41302D-page 28 2010 Microchip Technology Inc. REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA REGISTER REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS REGISTER REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PMDATL<7:0>: 8 Least Significant Address bits to Write or Read from Program Memory R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDATH<5:0>: 6 Most Significant Data bits from Program Memory U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PMADRH2 PMADRH1 PMADRH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 3 Unimplemented: Read as ‘0’ bit 2-0 PMADRH<2:0>: Specifies the 3 Most Significant Address bits or high bits for program memory reads. 2010 Microchip Technology Inc. DS41302D-page 29 PIC12F609/615/617/12HV609/615 REGISTER 3-5: PMCON1 – PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h) U-1 U-0 U-0 U-0 U-0 R/W-0 R/S-0 R/S-0 — — — — — WREN WR RD bit 7 bit 0 bit 7 Unimplemented: Read as ‘1’ bit 6-3 Unimplemented: Read as ‘0’ bit 2 WREN: Program Memory Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle to program memory. (The bit is cleared by hardware when write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the Flash memory is complete bit 0 RD: Read Control bit 1 = Initiates a program memory read (The read takes one cycle. The RD is cleared in hardware; the RD bit can only be set (not cleared) in software). 0 = Does not initiate a Flash memory read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown PIC12F609/615/617/12HV609/615 DS41302D-page 30 2010 Microchip Technology Inc. 3.3 Reading the Flash Program Memory To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored. The data is available in the very next cycle in the PMDATL and PMDATH registers; it can be read as two bytes in the following instructions. PMDATL and PMDATH registers will hold this value until another read or until it is written to by the user (during a write operation). EXAMPLE 3-1: FLASH PROGRAM READ BANKSEL PM_ADR ; Change STATUS bits RP1:0 to select bank with PMADRL MOVLW MS_PROG_PM_ADDR ; MOVWF PMADRH ; MS Byte of Program Address to read MOVLW LS_PROG_PM_ADDR ; MOVWF PMADRL ; LS Byte of Program Address to read BANKSEL PMCON1 ; Bank to containing PMCON1 BSF PMCON1, RD ; PM Read NOP ; First instruction after BSF PMCON1,RD executes normally NOP ; Any instructions here are ignored as program ; memory is read in second cycle after BSF PMCON1,RD ; BANKSEL PMDATL ; Bank to containing PMADRL MOVF PMDATL, W ; W = LS Byte of Program PMDATL MOVF PMDATH, W ; W = MS Byte of Program PMDATL 2010 Microchip Technology Inc. DS41302D-page 31 PIC12F609/615/617/12HV609/615 FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 BSF PMCON1,RD Executed here INSTR (PC + 1) Executed here NOP Executed here Flash ADDR PC PC + 1 PMADRH,PMADRL PC+3 PC + 5 RD bit INSTR (PC) PMDATH,PMDATL INSTR (PC + 3) PC + 3 PC + 4 INSTR (PC + 1) INSTR (PC + 4) INSTR (PC - 1) Executed here INSTR (PC + 3) Executed here INSTR (PC + 4) Executed here Flash DATA PMDATH PMDATL Register PMRHLT PIC12F609/615/617/12HV609/615 DS41302D-page 32 2010 Microchip Technology Inc. 3.4 Writing the Flash Program Memory A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory. Flash program memory must be written in four-word blocks. See Figure 3-2 and Figure 3-3 for more details. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where PMADRL<1:0> = 00. All block writes to program memory are done as 16-word erase by fourword write operations. The write operation is edgealigned and cannot occur across boundaries. To write program data, it must first be loaded into the buffer registers (see Figure 3-2). This is accomplished by first writing the destination address to PMADRL and PMADRH and then writing the data to PMDATL and PMDATH. After the address and data have been set up, then the following sequence of events must be executed: 1. Write 55h, then AAh, to PMCON2 (Flash programming sequence). 2. Set the WR control bit of the PMCON1 register. All four buffer register locations should be written to with correct data. If less than four words are being written to in the block of four words, then a read from the program memory location(s) not being written to must be performed. This takes the data from the program location(s) not being written and loads it into the PMDATL and PMDATH registers. Then the sequence of events to transfer data to the buffer registers must be executed. To transfer data from the buffer registers to the program memory, the PMADRL and PMADRH must point to the last location in the four-word block (PMADRL<1:0> = 11). Then the following sequence of events must be executed: 1. Write 55h, then AAh, to PMCON2 (Flash programming sequence). 2. Set control bit WR of the PMCON1 register to begin the write operation. The user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence (000, 001, 010, 011). When the write is performed on the last word (PMADRL<1:0> = 11), a block of sixteen words is automatically erased and the content of the four-word buffer registers are written into the program memory. After the “BSF PMCON1,WR” instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. Since data is being written to buffer registers, the writing of the first three words of the block appears to occur immediately. The processor will halt internal operations for the typical 4 ms, only during the cycle in which the erase takes place (i.e., the last word of the sixteen-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run. After the four-word write cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. The above sequence must be repeated for the higher 12 words. 3.5 Protection Against Spurious Write There are conditions when the device should not write to the program memory. To protect against spurious writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents program memory writes. The write initiate sequence and the WREN bit help prevent an accidental write during brown-out, power glitch or software malfunction. 3.6 Operation During Code-Protect When the device is code-protected, the CPU is able to read and write unscrambled data to the program memory. The test mode access is disabled. 3.7 Operation During Write Protect When the program memory is write-protected, the CPU can read and execute from the program memory. The portions of program memory that are write protected can be modified by the CPU using the PMCON registers, but the protected program memory cannot be modified using ICSP mode. 2010 Microchip Technology Inc. DS41302D-page 33 PIC12F609/615/617/12HV609/615 FIGURE 3-2: BLOCK WRITES TO 2K FLASH PROGRAM MEMORY FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION 14 14 14 14 Program Memory Buffer Register PMADRL<1:0> = 00 Buffer Register PMADRL<1:0> = 01 Buffer Register PMADRL<1:0> = 10 Buffer Register PMADRL<1:0> = 11 PMDATH PMDATL 7 5 0 7 0 6 8 First word of block to be written If at a new row to Flash automatically after this word is written are transferred Flash are erased, then four buffers sixteen words of Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 BSF PMCON1,WR Executed here INSTR (PC + 1) Executed here Flash PC + 1 INSTR INSTR PMDATH,PMDATL INSTR (PC+3) NOP Executed here Flash Flash PMWHLT WR bit Processor halted PM Write Time PMADRH,PMADRL PC + 3 PC + 4 INSTR (PC + 3) Executed here ADDR DATA Memory Location ignored read PC + 2 INSTR (PC+2) (INSTR (PC + 2) NOP Executed here (PC) (PC + 1) PIC12F609/615/617/12HV609/615 DS41302D-page 34 2010 Microchip Technology Inc. An example of the complete four-word write sequence is shown in Example 3-2. The initial address is loaded into the PMADRH and PMADRL register pair; the eight words of data are loaded using indirect addressing. EXAMPLE 3-2: WRITING TO FLASH PROGRAM MEMORY ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; This write routine assumes the following: ; A valid starting address (the least significant bits = '00') ; is loaded in ADDRH:ADDRL ; ADDRH, ADDRL and DATADDR are all located in data memory ; BANKSEL PMADRH MOVF ADDRH,W ; Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVF DATAADDR,W ; Load initial data address MOVWF FSR ; LOOP MOVF INDF,W ; Load first data byte into lower MOVWF PMDATL ; INCF FSR,F ; Next byte MOVF INDF,W ; Load second data byte into upper MOVWF PMDATH ; INCF FSR,F ; BANKSEL PMCON1 BSF PMCON1,WREN ; Enable writes BCF INTCON,GIE ; Disable interrupts (if using) BTFSC INTCON,GIE ; See AN576 GOTO $-2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Required Sequence MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write 0AAh BSF PMCON1,WR ; Set WR bit to begin write NOP ; Required to transfer data to the buffer NOP ; registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts (comment out if not using interrupts) BANKSEL PMADRL MOVF PMADRL, W INCF PMADRL,F ; Increment address ANDLW 0x03 ; Indicates when sixteen words have been programmed SUBLW 0x03 ; 0x0F = 16 words ; 0x0B = 12 words ; 0x07 = 8 words ; 0x03 = 4 words BTFSS STATUS,Z ; Exit on a match, GOTO LOOP ; Continue if more data needs to be written 2010 Microchip Technology Inc. DS41302D-page 35 PIC12F609/615/617/12HV609/615 TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PMCON1 — — — — — WREN WR RD ---- -000 ---- -000 PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ---- PMADRL PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 0000 0000 PMADRH — — — — — PMADRH2 PMADRH1 PMADRH0 ---- -000 ---- -000 PMDATL PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 0000 0000 PMDATH — — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by Program Memory module. PIC12F609/615/617/12HV609/615 DS41302D-page 36 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 37 PIC12F609/615/617/12HV609/615 4.0 OSCILLATOR MODULE 4.1 Overview The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured with a choice of two selectable speeds: internal or external system clock source. The Oscillator module can be configured in one of eight clock modes. 3. EC – External clock with I/O on OSC2/CLKOUT. 4. LP – 32 kHz Low-Power Crystal mode. 5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode. 6. HS – High Gain Crystal or Ceramic Resonator mode. 7. RC – External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. 8. RCIO – External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT. 9. INTOSC – Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. 10. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The Internal Oscillator module provides a selectable system clock mode of either 4 MHz (Postscaler) or 8 MHz (INTOSC). FIGURE 4-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM (CPU and Peripherals) OSC1 OSC2 Sleep External Oscillator LP, XT, HS, RC, RCIO, EC System Clock MUX FOSC<2:0> (Configuration Word Register) Internal Oscillator INTOSC 8 MHz Postscaler 4 MHz INTOSC IOSCFS<7> PIC12F609/615/617/12HV609/615 DS41302D-page 38 2010 Microchip Technology Inc. 4.2 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. • Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two selectable clock frequencies: 4 MHz and 8 MHz The system clock can be selected between external or internal clock sources via the FOSC<2:0> bits of the Configuration Word register. 4.3 External Clock Modes 4.3.1 OSCILLATOR START-UP TIMER (OST) If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 4-1. TABLE 4-1: OSCILLATOR DELAY EXAMPLES 4.3.2 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 4-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 4-2: EXTERNAL CLOCK (EC) MODE OPERATION Switch From Switch To Frequency Oscillator Delay Sleep/POR INTOSC 125 kHz to 8 MHz Oscillator Warm-Up Delay (TWARM) Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST) OSC1/CLKIN I/O OSC2/CLKOUT(1) Clock from Ext. System PIC® MCU Note 1: Alternate pin functions are listed in the Section 1.0 “Device Overview”. 2010 Microchip Technology Inc. DS41302D-page 39 PIC12F609/615/617/12HV609/615 4.3.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 4-3 and Figure 4-4 show typical circuits for quartz crystal and ceramic resonators, respectively. FIGURE 4-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 4-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. C1 C2 Quartz RS(1) OSC1/CLKIN RF(2) Sleep To Internal Logic PIC® MCU Crystal OSC2/CLKOUT Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. C1 C2 Ceramic RS(1) OSC1/CLKIN RF(2) Sleep To Internal Logic PIC® MCU RP(3) Resonator OSC2/CLKOUT PIC12F609/615/617/12HV609/615 DS41302D-page 40 2010 Microchip Technology Inc. 4.3.4 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 4-5 shows the external RC mode connections. FIGURE 4-5: EXTERNAL RC MODES In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. 4.4 Internal Clock Modes The Oscillator module provides a selectable system clock source of either 4 MHz or 8 MHz. The selectable frequency is configured through the IOSCFS bit of the Configuration Word. The frequency of the internal oscillator can be trimmed with a calibration value in the OSCTUNE register. 4.4.1 INTOSC AND INTOSCIO MODES The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 12.0 “Special Features of the CPU” for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. OSC2/CLKOUT(1) CEXT REXT PIC® MCU OSC1/CLKIN FOSC/4 or Internal Clock VDD VSS Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: Alternate pin functions are listed in Section 1.0 “Device Overview”. 2: Output depends upon RC or RCIO Clock mode. I/O(2) 2010 Microchip Technology Inc. DS41302D-page 41 PIC12F609/615/617/12HV609/615 4.4.1.1 OSCTUNE Register The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-1). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES REGISTER 4-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = ••• 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = ••• 10000 = Minimum frequency Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets(1) CONFIG(2) IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 12-1) for operation of all register bits. PIC12F609/615/617/12HV609/615 DS41302D-page 42 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 43 PIC12F609/615/617/12HV609/615 5.0 I/O PORT There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 5.1 GPIO and the TRISIO Registers GPIO is a 6-bit wide port with 5 bidirectional and 1 inputonly pin. The corresponding data direction register is TRISIO (Register 5-2). Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., disable the output driver). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is GP3, which is input only and its TRIS bit will always read as ‘1’. Example 5- 1 shows how to initialize GPIO. Reading the GPIO register (Register 5-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. GP3 reads ‘0’ when MCLRE = 1. The TRISIO register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISIO register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. EXAMPLE 5-1: INITIALIZING GPIO Note: GPIO = PORTA TRISIO = TRISA Note: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. BANKSEL GPIO ; CLRF GPIO ;Init GPIO BANKSEL ANSEL ; CLRF ANSEL ;digital I/O, ADC clock ;setting ‘don’t care’ MOVLW 0Ch ;Set GP<3:2> as inputs MOVWF TRISIO ;and set GP<5:4,1:0> ;as outputs REGISTER 5-1: GPIO: GPIO REGISTER U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-x R/W-x — — GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GP<5:0>: GPIO I/O Pin bit 1 = GPIO pin is > VIH 0 = GPIO pin is < VIL PIC12F609/615/617/12HV609/615 DS41302D-page 44 2010 Microchip Technology Inc. 5.2 Additional Pin Functions Every GPIO pin on the PIC12F609/615/617/12HV609/ 615 has an interrupt-on-change option and a weak pullup option. The next three sections describe these functions. 5.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. 5.2.2 WEAK PULL-UPS Each of the GPIO pins, except GP3, has an individually configurable internal weak pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 5-5. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU bit of the OPTION register). A weak pull-up is automatically enabled for GP3 when configured as MCLR and disabled when GP3 is an I/O. There is no software control of the MCLR pull-up. 5.2.3 INTERRUPT-ON-CHANGE Each GPIO pin is individually configurable as an interrupt-on-change pin. Control bits IOCx enable or disable the interrupt function for each pin. Refer to Register 5-6. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of GPIO. The ‘mismatch’ outputs of the last read are OR’d together to set the GPIO Change Interrupt Flag bit (GPIF) in the INTCON register (Register 2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) Any read of GPIO AND Clear flag bit GPIF. This will end the mismatch condition; OR b) Any write of GPIO AND Clear flag bit GPIF will end the mismatch condition; A mismatch condition will continue to set flag bit GPIF. Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOR Reset. After these resets, the GPIF flag will continue to be set if a mismatch is present. REGISTER 5-2: TRISIO: GPIO TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISIO<5:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output Note 1: TRISIO<3> always reads ‘1’. 2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. 2010 Microchip Technology Inc. DS41302D-page 45 PIC12F609/615/617/12HV609/615 REGISTER 5-3: ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609) U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 — — — — ANS3 — ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 ANS3: Analog Select Between Analog or Digital Function on Pin GP4 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. bit 2 Unimplemented: Read as ‘0’ bit 1 ANS1: Analog Select Between Analog or Digital Function on Pin GP1 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O. Pin is assigned to port or special function. bit 0 ANS0: Analog Select Between Analog or Digital Function on Pin GP0 0 = Digital I/O. Pin is assigned to port or special function. 1 = Analog input. Pin is assigned as analog input.(1) Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-onchange if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 5-4: ANSEL: ANALOG SELECT REGISTER (PIC12F615/617/HV615) U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 bit 3-0 ANS<3:0>: Analog Select Between Analog or Digital Function on Pins GP4, GP2, GP1, GP0, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-onchange if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. PIC12F609/615/617/12HV609/615 DS41302D-page 46 2010 Microchip Technology Inc. REGISTER 5-5: WPU: WEAK PULL-UP GPIO REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPU5 WPU4 — WPU2 WPU1 WPU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 WPU<3>: Weak Pull-up Register bit(3) bit 2-0 WPU<2:0>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global GPPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). 3: The GP3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled as an input and reads as ‘0’. 4: WPU<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. REGISTER 5-6: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOC<5:0>: Interrupt-on-change GPIO Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOC<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. 2010 Microchip Technology Inc. DS41302D-page 47 PIC12F609/615/617/12HV609/615 5.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. 5.2.4.1 GP0/AN0(1)/CIN+/P1B(1)/ICSPDAT Figure 5-1 shows the diagram for this pin. The GP0 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC(1) • an analog non-inverting input to the comparator • a PWM output(1) • In-Circuit Serial Programming data 5.2.4.2 GP1/AN1(1)/CIN0-/VREF(1)/ICSPCLK Figure 5-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC(1) • an analog inverting input to the comparator • a voltage reference input for the ADC(1) • In-Circuit Serial Programming clock FIGURE 5-1: BLOCK DIAGRAM OF GP<1:0> Note 1: PIC12F615/617/HV615 only. VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak RD GPIO RD WR WR RD WR IOC RD IOC Interrupt-on- To Comparator Analog(1) Input Mode GPPU Analog(1) Input Mode Change Q1 WR RD WPU Data Bus WPU GPIO TRISIO TRISIO GPIO Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC12F615/617/HV615 only. To A/D Converter(3) I/O Pin S(2) R Q From other GP<5:0> pins (GP0) Write ‘0’ to GBIF GP<5:2, 0> pins (GP1) PIC12F609/615/617/12HV609/615 DS41302D-page 48 2010 Microchip Technology Inc. 5.2.4.3 GP2/AN2(1)/T0CKI/INT/COUT/ CCP1(1)/P1A(1) Figure 5-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC(1) • the clock input for TMR0 • an external edge triggered interrupt • a digital output from Comparator • a Capture input/Compare input/PWM output(1) • a PWM output(1) FIGURE 5-2: BLOCK DIAGRAM OF GP2 Note 1: PIC12F615/617/HV615 only. VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak RD GPIO RD WR WR RD WR IOC RD IOC Interrupt-on- To INT Analog(1) Input Mode GPPU Analog(1) Input Mode Change Q1 WR RD WPU Data Bus WPU GPIO TRISIO TRISIO GPIO Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC12F615/617/HV615 only. To A/D Converter(3) I/O Pin S(2) R Q From other GP<5:3, 1:0> pins Write ‘0’ to GBIF 0 C1OE 1 C1OE Enable To Timer0 2010 Microchip Technology Inc. DS41302D-page 49 PIC12F609/615/617/12HV609/615 5.2.4.4 GP3/T1G(1, 2)/MCLR/VPP Figure 5-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • a Timer1 gate (count enable), alternate pin(1, 2) • as Master Clear Reset with weak pull-up FIGURE 5-3: BLOCK DIAGRAM OF GP3 Note 1: Alternate pin function. 2: PIC12F615/617/HV615 only. VSS D CK Q Q D EN Q Data Bus RD GPIO RD GPIO WR IOC RD IOC Reset MCLRE RD TRISIO VSS D EN Q MCLRE VDD MCLRE Weak Q1 Input Pin Interrupt-on- Change S(1) R Q From other Write ‘0’ to GBIF Note 1: Set has priority over Reset GP<5:4, 2:0> pins PIC12F609/615/617/12HV609/615 DS41302D-page 50 2010 Microchip Technology Inc. 5.2.4.5 GP4/AN3(2)/CIN1-/T1G/ P1B(1, 2)/OSC2/CLKOUT Figure 5-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC(2) • Comparator inverting input • a Timer1 gate (count enable) • PWM output, alternate pin(1, 2) • a crystal/resonator connection • a clock output FIGURE 5-4: BLOCK DIAGRAM OF GP4 Note 1: Alternate pin function. 2: PIC12F615/617/HV615 only. VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak Analog Input Mode Data Bus WR WPU RD WPU RD GPIO WR GPIO WR TRISIO RD TRISIO WR IOC RD IOC FOSC/4 To A/D Converter(5) Oscillator Circuit OSC1 CLKOUT 0 1 CLKOUT Enable Enable Analog(3) Input Mode GPPU RD GPIO To T1G INTOSC/ RC/EC(2) CLK(1) Modes CLKOUT Enable Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC12F615/617/HV615 only. Q1 I/O Pin Interrupt-on- Change S(4) R Q From other Write ‘0’ to GBIF GP<5, 3:0> pins 2010 Microchip Technology Inc. DS41302D-page 51 PIC12F609/615/617/12HV609/615 5.2.4.6 GP5/T1CKI/P1A(1, 2)/OSC1/CLKIN Figure 5-5 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input • PWM output, alternate pin(1, 2) • a crystal/resonator connection • a clock input FIGURE 5-5: BLOCK DIAGRAM OF GP5 Note 1: Alternate pin function. 2: PIC12F615/617/HV615 only. VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak Data Bus WR WPU RD WPU RD GPIO WR GPIO WR TRISIO RD TRISIO WR IOC RD IOC To Timer1 INTOSC Mode RD GPIO INTOSC Mode GPPU OSC2 Note 1: Timer1 LP Oscillator enabled. 2: Set has priority over Reset. TMR1LPEN(1) Oscillator Circuit Q1 I/O Pin Interrupt-on- Change S(2) R Q From other GP<4:0> pins Write ‘0’ to GBIF PIC12F609/615/617/12HV609/615 DS41302D-page 52 2010 Microchip Technology Inc. TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL — ADCS2(1) ADCS1(1) ADCS0(1) ANS3 ANS2(1) ANS1 ANS0 -000 1111 -000 1111 CMCON0 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -0-0 0000 -0-0 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --u0 u000 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 WPU — — WPU5 WPU4 WPU3 WPU2 WPU1 WPU0 --11 1111 --11 -111 T1CON T1GINV TMR1GE TICKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu CCP1CON(1) P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000 APFCON(1) — — — T1GSEL — — P1BSEL P1ASEL ---0 --00 ---0 --00 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO. Note 1: PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. DS41302D-page 53 PIC12F609/615/617/12HV609/615 6.0 TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • 8-bit timer/counter register (TMR0) • 8-bit prescaler (shared with Watchdog Timer) • Programmable internal or external clock source • Programmable external clock edge selection • Interrupt on overflow Figure 6-1 is a block diagram of the Timer0 module. 6.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 6.1.1 8-BIT TIMER MODE When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to ‘0’. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. 6.1.2 8-BIT COUNTER MODE When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. T0CKI T0SE pin TMR0 Watchdog Timer WDT Time-out PS<2:0> WDTE Data Bus Set Flag bit T0IF on Overflow T0CS Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. 0 1 0 1 0 1 8 8 8-bit Prescaler 0 1 FOSC/4 PSA PSA PSA Sync 2 TCY PIC12F609/615/617/12HV609/615 DS41302D-page 54 2010 Microchip Technology Inc. 6.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. 6.1.3.1 Switching Prescaler Between Timer0 and WDT Modules As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 6-1, must be executed. EXAMPLE 6-1: CHANGING PRESCALER (TIMER0 WDT) When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 6-2). EXAMPLE 6-2: CHANGING PRESCALER (WDT TIMER0) 6.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. 6.1.5 USING TIMER0 WITH AN EXTERNAL CLOCK When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 16.0 “Electrical Specifications”. BANKSEL TMR0 ; CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and ;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ; ; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32 Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. CLRWDT ;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b’00000011’ ;Set prescale to 1:16 MOVWF OPTION_REG ; 2010 Microchip Technology Inc. DS41302D-page 55 PIC12F609/615/617/12HV609/615 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 REGISTER 6-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 BIT VALUE TMR0 RATE WDT RATE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. PIC12F609/615/617/12HV609/615 DS41302D-page 56 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 57 PIC12F609/615/617/12HV609/615 7.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with ECCP) • Comparator output synchronization to Timer1 clock Figure 7-1 is a block diagram of the Timer1 module. 7.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. 7.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally. Clock Source TMR1CS T1ACS FOSC/4 0 0 FOSC 0 1 T1CKI pin 1 x PIC12F609/615/617/12HV609/615 DS41302D-page 58 2010 Microchip Technology Inc. FIGURE 7-1: TIMER1 BLOCK DIAGRAM TMR1H TMR1L Oscillator T1SYNC T1CKPS<1:0> FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 1 0 0 1 Synchronized clock input 2 Set flag bit TMR1IF on Overflow TMR1(2) TMR1GE TMR1ON T1OSCEN 1 COUT 0 T1GSS T1GINV To Comparator Module Timer1 Clock TMR1CS OSC2/T1G OSC1/T1CKI Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: Alternate pin function. 5: PIC12F615/617/HV615 only. (1) EN INTOSC Without CLKOUT 1 0 T1ACS FOSC 0 1 T1GSEL(2) GP3/T1G(4, 5) Synchronize(3) det 2010 Microchip Technology Inc. DS41302D-page 59 PIC12F609/615/617/12HV609/615 7.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 7.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. If an external clock oscillator is needed (and the microcontroller is using the INTOSC without CLKOUT), Timer1 can use the LP oscillator as a clock source. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after one or more of the following conditions: • Timer1 is enabled after POR or BOR Reset • A write to TMR1H or TMR1L • T1CKI is high when Timer1 is disabled and when Timer1 is re-enabled T1CKI is low. See Figure 7-2. 7.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 7.4 Timer1 Oscillator A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when in LP oscillator mode. The user must provide a software time delay to ensure proper oscillator start-up. TRISIO5 and TRISIO4 bits are set when the Timer1 oscillator is enabled. GP5 and GP4 bits read as ‘0’ and TRISIO5 and TRISIO4 bits read as ‘1’. 7.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 7.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). 7.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TTMR1L register pair. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce a single spurious increment. Note: In asynchronous counter mode or when using the internal oscillator and T1ACS=1, Timer1 can not be used as a time base for the capture or compare modes of the ECCP module (for PIC12F615/617/ HV615 only). PIC12F609/615/617/12HV609/615 DS41302D-page 60 2010 Microchip Technology Inc. 7.6 Timer1 Gate Timer1 gate source is software configurable to be the T1G pin (or the alternate T1G pin) or the output of the Comparator. This allows the device to directly time external events using T1G or analog events using the Comparator. See the CMCON1 Register (Register 9-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or the Comparator output. This configures Timer1 to measure either the active-high or active-low time between events. 7.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • PEIE bit of the INTCON register • GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. 7.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • TMR1ON bit of the T1CON register must be set • TMR1IE bit of the PIE1 register must be set • PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). 7.9 ECCP Capture/Compare Time Base (PIC12F615/617/HV615 only) The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 11.0 “Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)”. Note: TMR1GE bit of the T1CON register must be set to use either T1G or COUT as the Timer1 gate source. See Register 9-2 for more information on selecting the Timer1 gate source. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. 2010 Microchip Technology Inc. DS41302D-page 61 PIC12F609/615/617/12HV609/615 7.10 ECCP Special Event Trigger (PIC12F615/617/HV615 only) If a ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to generate a ECCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1. Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the ECCP, the write will take precedence. For more information, see Section 11.0 “Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)”. 7.11 Comparator Synchronization The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module. When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. For more information, see Section 9.0 “Comparator Module”. FIGURE 7-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. PIC12F609/615/617/12HV609/615 DS41302D-page 62 2010 Microchip Technology Inc. 7.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 7-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 7-1: T1CON: TIMER 1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 6 TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is active 0 = Timer1 is on bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off For all other system clock modes: This bit is ignored. LP oscillator is disabled. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) or system clock (FOSC)(3) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register, as a Timer1 gate source. 3: See T1ACS bit in CMCON1 register. 2010 Microchip Technology Inc. DS41302D-page 63 PIC12F609/615/617/12HV609/615 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets APFCON(1) — — — T1GSEL — — P1BSEL P1ASEL ---0 --00 ---0 --00 CMCON0 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -0-0 0000 -0-0 CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 ---0 0-10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x PIE1 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: PIC12F615/617/HV615 only. PIC12F609/615/617/12HV609/615 DS41302D-page 64 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 65 PIC12F609/615/617/12HV609/615 8.0 TIMER2 MODULE (PIC12F615/617/HV615 ONLY) The Timer2 module is an 8-bit timer with the following features: • 8-bit timer register (TMR2) • 8-bit period register (PR2) • Interrupt on TMR2 match with PR2 • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) See Figure 8-1 for a block diagram of Timer2. 8.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle. • The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: • A write to TMR2 occurs. • A write to T2CON occurs. • Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). FIGURE 8-1: TIMER2 BLOCK DIAGRAM Note: TMR2 is not cleared when T2CON is written. Comparator TMR2 Sets Flag TMR2 Output Reset Postscaler Prescaler PR2 2 FOSC/4 1:1 to 1:16 1:1, 1:4, 1:16 EQ 4 bit TMR2IF TOUTPS<3:0> T2CKPS<1:0> PIC12F609/615/617/12HV609/615 DS41302D-page 66 2010 Microchip Technology Inc. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 REGISTER 8-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 PR2(1) Timer2 Module Period Register 1111 1111 1111 1111 TMR2(1) Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 T2CON(1) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. Note 1: For PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. DS41302D-page 67 PIC12F609/615/617/12HV609/615 9.0 COMPARATOR MODULE The comparator can be used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparator is a very useful mixed signal building block because it provides analog functionality independent of the program execution. The Analog Comparator module includes the following features: • Programmable input section • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change • Wake-up from Sleep • PWM shutdown • Timer1 gate (count enable) • Output synchronization to Timer1 clock input • Programmable voltage reference • User-enable Comparator Hysteresis 9.1 Comparator Overview The comparator is shown in Figure 9-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. FIGURE 9-1:SINGLE COMPARATOR FIGURE 9-2: COMPARATOR SIMPLIFIED BLOCK DIAGRAM – VIN+ + VINOutput Output VIN+ VINNote: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. CMOE MUX CMPOL 0 1 CMON(1) CMCH From Timer1 Clock Note 1: When CMON = 0, the comparator will produce a ‘0’ output to the XOR Gate. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. 4: Output shown for reference only. See I/O port pin diagram for more details. D Q EN D Q EN CL D Q RD_CMCON0 Q3*RD_CMCON0 Q1 Set CMIF To Reset CMVINCMVIN+ GP1/CIN0- GP4/CIN1- 0 1 CMSYNC CMPOL Data Bus MUX COUT(4) To PWM Auto-Shutdown To Timer1 Gate 0 1 CMR MUX GP0/CIN+ 0 1 MUX CVREF CMVREN FixedRef CMVREF SYNCCMOUT PIC12F609/615/617/12HV609/615 DS41302D-page 68 2010 Microchip Technology Inc. 9.2 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 9-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. FIGURE 9-3: ANALOG INPUT MODEL Note 1: When reading a GPIO register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. VA RS < 10K CPIN 5 pF VDD VT 0.6V VT 0.6V RIC ILEAKAGE ±500 nA VSS AIN Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage To Comparator 2010 Microchip Technology Inc. DS41302D-page 69 PIC12F609/615/617/12HV609/615 9.3 Comparator Control The comparator has two control and Configuration registers: CMCON0 and CMCON1. The CMCON1 register is used for controlling the interaction with Timer1 and simultaneously reading the comparator output. The CMCON0 register (Register 9-1) contain the control and Status bits for the following: • Enable • Input selection • Reference selection • Output selection • Output polarity 9.3.1 COMPARATOR ENABLE Setting the CMON bit of the CMCON0 register enables the comparator for operation. Clearing the CMON bit disables the comparator for minimum current consumption. 9.3.2 COMPARATOR INPUT SELECTION The CMCH bit of the CMCON0 register directs one of four analog input pins to the comparator inverting input. 9.3.3 COMPARATOR REFERENCE SELECTION Setting the CMR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. See Section 9.10 “Comparator Voltage Reference” for more information on the internal voltage reference module. 9.3.4 COMPARATOR OUTPUT SELECTION The output of the comparator can be monitored by reading either the COUT bit of the CMCON0 register. In order to make the output available for an external connection, the following conditions must be true: • CMOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CMON bit of the CMCON0 register must be set. 9.3.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CMPOL bit of the CMCON0 register. Clearing CMPOL results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 9-1. TABLE 9-1: OUTPUT STATE VS. INPUT CONDITIONS 9.4 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See Section 16.0 “Electrical Specifications” for more details. Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. Note 1: The CMOE bit overrides the PORT data latch. Setting the CMON has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. Input Conditions CMPOL COUT CMVIN- > CMVIN+ 0 0 CMVIN- < CMVIN+ 0 1 CMVIN- > CMVIN+ 1 1 CMVIN- < CMVIN+ 1 0 Note: COUT refers to both the register bit and output pin. PIC12F609/615/617/12HV609/615 DS41302D-page 70 2010 Microchip Technology Inc. 9.5 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 9-4 and Figure 9-5). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset. The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch condition will occur when a comparator output change is clocked through the second latch on the Q1 clock cycle. At this point the two mismatch latches have opposite output levels which is detected by the exclusive-or gate and fed to the interrupt circuitry. The mismatch condition persists until either the CMCON0 register is read or the comparator output returns to the previous state. The comparator interrupt is set by the mismatch edge and not the mismatch level. This means that the interrupt flag can be reset without the additional step of reading or writing the CMCON0 register to clear the mismatch registers. When the mismatch registers are cleared, an interrupt will occur upon the comparator’s return to the previous state, otherwise no interrupt will be generated. Software will need to maintain information about the status of the comparator output, as read from the CMCON1 register, to determine the actual change that has occurred. The CMIF bit of the PIR1 register is the Comparator Interrupt flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to write a '1' to this register, an interrupt can be generated. The CMIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CMIF bit of the PIR1 register will still be set if an interrupt condition occurs. FIGURE 9-4: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ FIGURE 9-5: COMPARATOR INTERRUPT TIMING WITH CMCON0 READ Note 1: A write operation to the CMCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle. 2: Comparator interrupts will operate correctly regardless of the state of CMOE. Note 1: If a change in the CMCON0 register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF of the PIR1 register interrupt flag may not get set. 2: When a comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. Q1 Q3 CIN+ COUT Set CMIF (edge) CMIF TRT reset by software Q1 Q3 CIN+ COUT Set CMIF (edge) CMIF TRT cleared by CMCON0 read reset by software 2010 Microchip Technology Inc. DS41302D-page 71 PIC12F609/615/617/12HV609/615 9.6 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 16.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by clearing the CMON bit of the CMCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CMIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the SLEEP instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. 9.7 Effects of a Reset A device Reset forces the CMCON1 register to its Reset state. This sets the comparator and the voltage reference to the OFF state. PIC12F609/615/617/12HV609/615 DS41302D-page 72 2010 Microchip Technology Inc. REGISTER 9-1: CMCON0: COMPARATOR CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 CMON COUT CMOE CMPOL — CMR — CMCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CMON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COUT: Comparator Output bit If C1POL = 1 (inverted polarity): COUT = 0 when CMVIN+ > CMVINCOUT = 1 when CMVIN+ < CMVINIf C1POL = 0 (non-inverted polarity): COUT = 1 when CMVIN+ > CMVINCOUT = 0 when CMVIN+ < CMVINbit 5 CMOE: Comparator Output Enable bit 1 = COUT is present on the COUT pin(1) 0 = COUT is internal only bit 4 CMPOL: Comparator Output Polarity Select bit 1 = COUT logic is inverted 0 = COUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CMR: Comparator Reference Select bit (non-inverting input) 1 = CMVIN+ connects to CMVREF output 0 = CMVIN+ connects to CIN+ pin bit 1 Unimplemented: Read as ‘0’ bit 0 CMCH: Comparator C1 Channel Select bit 0 = CMVIN- pin of the Comparator connects to CIN0- 1 = CMVIN- pin of the Comparator connects to CIN1- Note 1: Comparator output requires the following three conditions: CMOE = 1, CMON = 1 and corresponding port TRIS bit = 0. 2010 Microchip Technology Inc. DS41302D-page 73 PIC12F609/615/617/12HV609/615 9.8 Comparator Gating Timer1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator. This requires that Timer1 is on and gating is enabled. See Section 7.0 “Timer1 Module with Gate Control” for details. It is recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment. 9.9 Synchronizing Comparator Output to Timer1 The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 9- 2) and the Timer1 Block Diagram (Figure 7-1) for more information. REGISTER 9-2: CMCON1: COMPARATOR CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-0 — — — T1ACS CMHYS — T1GSS CMSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1ACS: Timer1 Alternate Clock Select bit 1 = Timer 1 Clock Source is System Clock (FOSC) 0 = Timer 1 Clock Source is Instruction Clock (FOSC\4) bit 3 CMHYS: Comparator Hysteresis Select bit 1 = Comparator Hysteresis enabled 0 = Comparator Hysteresis disabled bit 2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Timer 1 Gate Source is comparator output bit 0 CMSYNC: Comparator Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section 7.6 “Timer1 Gate”. 2: Refer to Figure 9-2. PIC12F609/615/617/12HV609/615 DS41302D-page 74 2010 Microchip Technology Inc. 9.10 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: • Independent from Comparator operation • 16-level voltage range • Output clamped to VSS • Ratiometric with VDD • Fixed Reference (0.6) The VRCON register (Register 9-3) controls the Voltage Reference module shown in Register 9-6. 9.10.1 INDEPENDENT OPERATION The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference. 9.10.2 OUTPUT VOLTAGE SELECTION The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register. The CVREF output voltage is determined by the following equations: EQUATION 9-1: CVREF OUTPUT VOLTAGE The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 9-6. 9.10.3 OUTPUT CLAMPED TO VSS The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: • FVREN = 0 This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current. 9.10.4 OUTPUT RATIOMETRIC TO VDD The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 16.0 “Electrical Specifications”. 9.10.5 FIXED VOLTAGE REFERENCE The fixed voltage reference is independent of VDD, with a nominal output voltage of 0.6V. This reference can be enabled by setting the FVREN bit of the VRCON register to ‘1’. This reference is always enabled when the HFINTOSC oscillator is active. 9.10.6 FIXED VOLTAGE REFERENCE STABILIZATION PERIOD When the Fixed Voltage Reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See Section 16.0 “Electrical Specifications” for the minimum delay requirement. 9.10.7 VOLTAGE REFERENCE SELECTION Multiplexers on the output of the Voltage Reference module enable selection of either the CVREF or fixed voltage reference for use by the comparators. Setting the CMVREN bit of the VRCON register enables current to flow in the CVREF voltage divider and selects the CVREF voltage for use by the Comparator. Clearing the CMVREN bit selects the fixed voltage for use by the Comparator. When the CMVREN bit is cleared, current flow in the CVREF voltage divider is disabled minimizing the power drain of the voltage reference peripheral. VRR = 1 (low range): VRR = 0 (high range): CVREF = (VDD/4) + CVREF = (VR<3:0>/24) VDD (VR<3:0> VDD/32) 2010 Microchip Technology Inc. DS41302D-page 75 PIC12F609/615/617/12HV609/615 FIGURE 9-6: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 8R VRR VR<3:0>(1) Analog 8R R R R R 16 Stages VDD MUX Fixed Voltage CMVREN CVREF(1) Reference EN FVREN Sleep HFINTOSC enable FixedRef 0.6V To Comparators and ADC Module To Comparators and ADC Module Note 1: Care should be taken to ensure CVREF remains within the comparator common mode input range. See Section 16.0 “Electrical Specifications” for more detail. 15 0 4 PIC12F609/615/617/12HV609/615 DS41302D-page 76 2010 Microchip Technology Inc. REGISTER 9-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMVREN — VRR FVREN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CMVREN: Comparator Voltage Reference Enable bit(1, 2) 1 = CVREF circuit powered on and routed to CVREF input of the Comparator 0 = 0.6 Volt constant reference routed to CVREF input of the Comparator bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 FVREN: 0.6V Reference Enable bit(2) 1 = Enabled 0 = Disabled bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0 VR<3:0> 15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD Note 1: When CMVREN is low, the CVREF circuit is powered down and does not contribute to IDD current. 2: When CMVREN is low and the FVREN bit is low, the CVREF signal should provide Vss to the comparator. 2010 Microchip Technology Inc. DS41302D-page 77 PIC12F609/615/617/12HV609/615 9.11 Comparator Hysteresis Each comparator has built-in hysteresis that is user enabled by setting the CMHYS bit of the CMCON1 register. The hysteresis feature can help filter noise and reduce multiple comparator output transitions when the output is changing state. Figure 9-7 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis. The output of the comparator changes from a low state to a high state only when the analog voltage at VIN+ rises above the upper hysteresis threshold (VH+). The output of the comparator changes from a high state to a low state only when the analog voltage at VIN+ falls below the lower hysteresis threshold (VH-). FIGURE 9-7: COMPARATOR HYSTERESIS – VIN+ + VINOutput Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time. VHVH+ VINV+ VIN+ Output (Without Hysteresis) Output (With Hysteresis) PIC12F609/615/617/12HV609/615 DS41302D-page 78 2010 Microchip Technology Inc. TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL — ADCS2(1) ADCS1(1) ADCS0(1) ANS3 ANS2(1) ANS1 ANS0 -000 1111 -000 1111 CMCON0 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -000 0000 -000 CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC 0000 0000 0000 0000 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x PIE1 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 VRCON CMVREN — VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 0-00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator. Note 1: For PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. DS41302D-page 79 PIC12F609/615/617/12HV609/615 10.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC12F615/617/HV615 ONLY) The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure 10-1 shows the block diagram of the ADC. FIGURE 10-1: ADC BLOCK DIAGRAM Note: The ADRESL and ADRESH registers are Read Only. GP0/AN0 A/D GP1/AN1/VREF GP2/AN2 CVREF VDD VREF ADON GO/DONE VCFG = 1 VCFG = 0 CHS VSS 0.6V Reference 1.2V Reference GP4/AN3 ADRESH ADRESL 10 10 ADFM 0 = Left Justify 1 = Right Justify 000 001 010 011 100 101 110 PIC12F609/615/617/12HV609/615 DS41302D-page 80 2010 Microchip Technology Inc. 10.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 10.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding port section for more information. 10.1.2 CHANNEL SELECTION The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 10.2 “ADC Operation” for more information. 10.1.3 ADC VOLTAGE REFERENCE The VCFG bit of the ADCON0 register provides control of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage source. The negative voltage reference is always connected to the ground reference. 10.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ANSEL register. There are seven possible clock options: • FOSC/2 • FOSC/4 • FOSC/8 • FOSC/16 • FOSC/32 • FOSC/64 • FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 10-3. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 16.0 “Electrical Specifications” for more information. Table 10-1 gives examples of appropriate ADC clock selections. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. 2010 Microchip Technology Inc. DS41302D-page 81 PIC12F609/615/617/12HV609/615 TABLE 10-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) FIGURE 10-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES 10.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 10.1.5 “Interrupts” for more information. ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 200 ns(2) 500 ns(2) 1.0 s(2) 4.0 s FOSC/8 001 400 ns(2) 1.0 s(2) 2.0 s 8.0 s(3) FOSC/16 101 800 ns(2) 2.0 s 4.0 s 16.0 s(3) FOSC/32 010 1.6 s 4.0 s 8.0 s(3) 32.0 s(3) FOSC/64 110 3.2 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 Set GO/DONE bit Holding Capacitor is Disconnected from Analog Input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 TAD10 TAD11 b1 b0 TCY to TAD Conversion Starts ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. PIC12F609/615/617/12HV609/615 DS41302D-page 82 2010 Microchip Technology Inc. 10.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 10-4 shows the two output formats. FIGURE 10-3: 10-BIT A/D CONVERSION RESULT FORMAT 10.2 ADC Operation 10.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. 10.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result 10.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel. 10.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 10.2.5 SPECIAL EVENT TRIGGER The ECCP Special Event Trigger allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. See Section 11.0 “Enhanced Capture/Compare/ PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)” for more information. ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 10.2.6 “A/D Conversion Procedure”. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2010 Microchip Technology Inc. DS41302D-page 83 PIC12F609/615/617/12HV609/615 10.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: • Disable pin output driver (See TRIS register) • Configure pin as analog 2. Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Select result format • Turn on ADC module 3. Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) 4. Wait the required acquisition time(2). 5. Start conversion by setting the GO/DONE bit. 6. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 10-1: A/D CONVERSION Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 10.3 “A/D Acquisition Requirements”. ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL TRISIO ; BSF TRISIO,0 ;Set GP0 to input BANKSEL ANSEL ; MOVLW B’01110001’ ;ADC Frc clock, IORWF ANSEL ; and GP0 as analog BANKSEL ADCON0 ; MOVLW B’10000001’ ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;Store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space PIC12F609/615/617/12HV609/615 DS41302D-page 84 2010 Microchip Technology Inc. 10.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 10-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5 Unimplemented: Read as ‘0’ bit 4-2 CHS<2:0>: Analog Channel Select bits 000 = Channel 00 (AN0) 001 = Channel 01 (AN1) 010 = Channel 02 (AN2) 011 = Channel 03 (AN3) 100 = CVREF 101 = 0.6V Reference 110 = 1.2V Reference 111 = Reserved. Do not use. bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: When the CHS<2:0> bits change to select the 1.2V or 0.6V reference, the reference output voltage will have a transient. If the Comparator module uses this 0.6V reference voltage, the comparator output may momentarily change state due to the transient. 2010 Microchip Technology Inc. DS41302D-page 85 PIC12F609/615/617/12HV609/615 REGISTER 10-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 10-3: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY) R-x R-x U-0 U-0 U-0 U-0 U-0 U-0 ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Unimplemented: Read as ‘0’ REGISTER 10-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY) U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 10-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result PIC12F609/615/617/12HV609/615 DS41302D-page 86 2010 Microchip Technology Inc. 10.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 10-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 10-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 10-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. EQUATION 10-1: ACQUISITION TIME EXAMPLE TACQ Amplifier Settling Time Hold Capacitor Charging = + Time + Temperature Coefficient = TAMP + TC + TCOFF = 2μs + TC + Temperature - 25°C0.05μs/°C TC = –CHOLDRIC + RSS + RS ln(1/2047) = –10pF1k + 7k + 10k ln(0.0004885) = 1.37μs TACQ = 2μs + 1.37μs + 50°C- 25°C0.05μs/°C = 4.67μs VAPPLIED 1 e –Tc -R----C---- – VAPPLIED 1 1 – -2---0---4---7- = VAPPLIED 1 1 – -2---0---4---7- = VCHOLD VAPPLIED 1 e –TC --R----C--- – = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb ;[2] VCHOLD charge response to VAPPLIED ;combining [1] and [2] The value for TC can be approximated with the following equations: Solving for TC: Therefore: Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2010 Microchip Technology Inc. DS41302D-page 87 PIC12F609/615/617/12HV609/615 FIGURE 10-4: ANALOG INPUT MODEL FIGURE 10-5: ADC TRANSFER FUNCTION VA CPIN Rs ANx 5 pF VDD VT = 0.6V VT = 0.6V I LEAKAGE RIC 1k Sampling Switch SS Rss CHOLD = 10 pF VSS/VREF- 6V Sampling Switch 5V 4V 3V 2V 5 6 7 8 91011 (k) VDD ± 500 nA Legend: CPIN VT I LEAKAGE RIC SS CHOLD = Input Capacitance = Threshold Voltage = Leakage current at the pin due to = Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance various junctions RSS 3FFh 3FEh ADC Output Code 3FDh 3FCh 004h 003h 002h 001h 000h Full-Scale 3FBh 1 LSB ideal VSS/VREF- Zero-Scale Transition VDD/VREF+ Transition 1 LSB ideal Full-Scale Range Analog Input Voltage PIC12F609/615/617/12HV609/615 DS41302D-page 88 2010 Microchip Technology Inc. TABLE 10-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCON0(1) ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000 ANSEL — ADCS2(1) ADCS1(1) ADCS0(1) ANS3 ANS2(1) ANS1 ANS0 -000 1111 -000 1111 ADRESH(1,2) A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL(1,2) A/D Result Register Low Byte xxxx xxxx uuuu uuuu GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 --x0 x000 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Note 1: For PIC12F615/617/HV615 only. 2: Read Only Register. 2010 Microchip Technology Inc. DS41302D-page 89 PIC12F609/615/617/12HV609/615 11.0 ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTOSHUTDOWN AND DEAD BAND) MODULE (PIC12F615/617/ HV615 ONLY) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event.The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. Table 11-1 shows the timer resources required by the ECCP module. TABLE 11-1: ECCP MODE – TIMER RESOURCES REQUIRED ECCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 REGISTER 11-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 P1M: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: x = P1A assigned as Capture/Compare input; P1B assigned as port pins If CCP1M<3:2> = 11: 0 = Single output; P1A modulated; P1B assigned as port pins 1 = Half-Bridge output; P1A, P1B modulated with dead-band control bit 6 Unimplemented: Read as ‘0’ bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP Mode Select bits 0000 =Capture/Compare/PWM off (resets ECCP module) 0001 =Unused (reserved) 0010 =Compare mode, toggle output on match (CCP1IF bit is set) 0011 =Unused (reserved) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCP1IF bit is set) 1001 =Compare mode, clear output on match (CCP1IF bit is set) 1010 =Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 =Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2 and starts an A/D conversion, if the ADC module is enabled) 1100 =PWM mode; P1A active-high; P1B active-high 1101 =PWM mode; P1A active-high; P1B active-low 1110 =PWM mode; P1A active-low; P1B active-high 1111 =PWM mode; P1A active-low; P1B active-low PIC12F609/615/617/12HV609/615 DS41302D-page 90 2010 Microchip Technology Inc. 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value (see Figure 11-1). 11.1.1 CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. FIGURE 11-1: CAPTURE MODE OPERATION BLOCK DIAGRAM 11.1.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 11.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode. 11.1.4 CCP PRESCALER There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler (see Example 11-1). EXAMPLE 11-1: CHANGING BETWEEN CAPTURE PRESCALERS Note: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition. CCPR1H CCPR1L TMR1H TMR1L Set Flag bit CCP1IF (PIR1 register) Capture Enable CCP1CON<3:0> Prescaler 1, 4, 16 and Edge Detect pin CCP1 System Clock (FOSC) BANKSEL CCP1CON ;Set Bank bits to point ;to CCP1CON CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this ; value 2010 Microchip Technology Inc. DS41302D-page 91 PIC12F609/615/617/12HV609/615 TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CCP1CON P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture. Note 1: For PIC12F615/617/HV615 only. PIC12F609/615/617/12HV609/615 DS41302D-page 92 2010 Microchip Technology Inc. 11.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • Toggle the CCP1 output. • Set the CCP1 output. • Clear the CCP1 output. • Generate a Special Event Trigger. • Generate a Software Interrupt. The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. All Compare modes can generate an interrupt. FIGURE 11-2: COMPARE MODE OPERATION BLOCK DIAGRAM 11.2.1 CCP1 PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. 11.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. 11.2.3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register). 11.2.4 SPECIAL EVENT TRIGGER When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following: • Resets Timer1 • Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch. CCPR1H CCPR1L TMR1H TMR1L Comparator Q S R Output Logic Special Event Trigger Set CCP1IF Interrupt Flag (PIR1) Match TRIS CCP1CON<3:0> Mode Select Output Enable Pin Special Event Trigger will: • Clear TMR1H and TMR1L registers. • NOT set interrupt flag bit TMR1IF of the PIR1 register. • Set the GO/DONE bit to start the ADC conversion. CCP1 4 Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMRxIF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. 2010 Microchip Technology Inc. DS41302D-page 93 PIC12F609/615/617/12HV609/615 TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CCP1CON P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR2 Timer2 Module Register 0000 0000 0000 0000 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Compare. Note 1: For PIC12F615/617/HV615 only. PIC12F609/615/617/12HV609/615 DS41302D-page 94 2010 Microchip Technology Inc. 11.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPR1L • CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCP1 pin output driver. Figure 11-3 shows a simplified block diagram of PWM operation. Figure 11-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 11.3.7 “Setup for PWM Operation”. FIGURE 11-3: SIMPLIFIED PWM BLOCK DIAGRAM The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 11-4: CCP PWM OUTPUT Note: Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin. CCPR1L CCPR1H(2) (Slave) Comparator TMR2 PR2 (1) R Q S Duty Cycle Registers CCP1CON<5:4> Clear Timer2, toggle CCP1 pin and latch duty cycle Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. 2: In PWM mode, CCPR1H is a read-only register. TRIS CCP1 Comparator Period Pulse Width TMR2 = 0 TMR2 = CCPRxL:CCPxCON<5:4> TMR2 = PR2 2010 Microchip Technology Inc. DS41302D-page 95 PIC12F609/615/617/12HV609/615 11.3.1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 11-1. EQUATION 11-1: PWM PERIOD When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPR1L into CCPR1H. 11.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 11-2 is used to calculate the PWM pulse width. Equation 11-3 is used to calculate the PWM duty cycle ratio. EQUATION 11-2: PULSE WIDTH EQUATION 11-3: DUTY CYCLE RATIO The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure 11- 3). 11.3.3 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 11-4. EQUATION 11-4: PWM RESOLUTION TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) TABLE 11-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) Note: The Timer2 postscaler (see Section 8.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. PWM Period = PR2 + 1 4 TOSC (TMR2 Prescale Value) Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. Pulse Width = CCPR1L:CCP1CON<5:4> TOSC (TMR2 Prescale Value) Duty Cycle Ratio CCPR1L:CCP1CON<5:4> 4PR2 + 1 = ----------------------------------------------------------------------- Resolution log4PR2 + 1 log2 = ------------------------------------------ bits PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 PIC12F609/615/617/12HV609/615 DS41302D-page 96 2010 Microchip Technology Inc. 11.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 11.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 4.0 “Oscillator Module” for additional details. 11.3.6 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 11.3.7 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Disable the PWM pin (CCP1) output drivers by setting the associated TRIS bit. 2. Set the PWM period by loading the PR2 register. 3. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. 4. Set the PWM duty cycle by loading the CCPR1L register and DC1B bits of the CCP1CON register. 5. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. • Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register. • Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output driver by clearing the associated TRIS bit. 2010 Microchip Technology Inc. DS41302D-page 97 PIC12F609/615/617/12HV609/615 11.4 PWM (Enhanced Mode) The Enhanced PWM Mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: • Single PWM • Half-Bridge PWM To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately. The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. Table 11-6 shows the pin assignments for each Enhanced PWM mode. Figure 11-5 shows an example of a simplified block diagram of the Enhanced PWM module. FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE TABLE 11-6: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES Note: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. CCPR1L CCPR1H (Slave) Comparator TMR2 Comparator PR2 (1) R Q S Duty Cycle Registers CCP1<1:0> Clear Timer2, toggle PWM pin and latch duty cycle * Alternate pin function. Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. TRISIO2 CCP1/P1A Output Controller P1M<1:0> 2 CCP1M<3:0> 4 PWM1CON CCP1/P1A P1B 0 1 TRISIO5 CCP1/P1A* P1ASEL (APFCON<0>) TRISIO0 0 P1B 1 TRISIO4 P1B* P1BSEL (APFCON<1>) Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions. ECCP Mode P1M<1:0> CCP1/P1A P1B Single 00 Yes(1) Yes(1) Half-Bridge 10 Yes Yes PIC12F609/615/617/12HV609/615 DS41302D-page 98 2010 Microchip Technology Inc. FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 Period 00 10 Signal PR2+1 P1M<1:0> P1A Modulated P1A Modulated P1B Modulated P1A Active P1B Inactive P1C Inactive P1D Modulated Pulse Width (Single Output) (Half-Bridge) Delay(1) Delay(1) Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay mode”). 0 Period 00 10 Signal PR2+1 P1M<1:0> P1A Modulated P1A Modulated P1B Modulated P1A Active P1B Inactive P1C Inactive P1D Modulated Pulse Width (Single Output) (Half-Bridge) Delay(1) Delay(1) Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay mode”). 2010 Microchip Technology Inc. DS41302D-page 99 PIC12F609/615/617/12HV609/615 11.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 11-8). This mode can be used for Half-Bridge applications, as shown in Figure 11-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in Half- Bridge power devices. The value of the PDC<6:0> bits of the PWM1CON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 11.4.6 “Programmable Dead-Band Delay mode” for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. FIGURE 11-8: EXAMPLE OF HALFBRIDGE PWM OUTPUT FIGURE 11-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Period Pulse Width td td (1) P1A(2) P1B(2) td = Dead-Band Delay Period (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. P1A P1B FET Driver FET Driver Load + - + - FET Driver FET Driver V+ Load FET Driver FET Driver P1A P1B Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit PIC12F609/615/617/12HV609/615 DS41302D-page 100 2010 Microchip Technology Inc. 11.4.2 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each PWM output pin (P1A and P1B). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A and P1B output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before configuring the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. 11.4.3 OPERATION DURING SLEEP When the device is placed in sleep, the allocated timer will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. Note: When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). 2010 Microchip Technology Inc. DS41302D-page 101 PIC12F609/615/617/12HV609/615 11.4.4 ENHANCED PWM AUTOSHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPASx bits of the ECCPAS register. A shutdown event may be generated by: • A logic ‘0’ on the INT pin • Comparator • Setting the ECCPASE bit in firmware A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. Refer to Figure 1. When a shutdown event occurs, two things happen: The ECCPASE bit is set to ‘1’. The ECCPASE will remain set until cleared in firmware or an auto-restart occurs (see Section 11.4.5 “Auto-Restart Mode”). The enabled PWM pins are asynchronously placed in their shutdown states. The state of P1A is determined by the PSSAC bit. The state of P1B is determined by the PSSBD bit. The PSSAC and PSSBD bits are located in the ECCPAS register. Each pin may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) FIGURE 11-10: AUTO-SHUTDOWN BLOCK DIAGRAM PSSAC<1> TRISx P1A 0 1 P1A_DRV PSSAC<0> PSSBD<1> TRISx P1B 0 PSSBD<0> 1 P1B_DRV 000 001 010 011 100 101 110 111 From Comparator ECCPAS<2:0> R D Q S From Data Bus ECCPASE Write to ECCPASE PRSEN INT PIC12F609/615/617/12HV609/615 DS41302D-page 102 2010 Microchip Technology Inc. REGISTER 11-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits 000 =Auto-Shutdown is disabled 001 =Comparator output change 010 =Auto-Shutdown is disabled 011 =Comparator output change(1) 100 =VIL on INT pin 101 =VIL on INT pin or Comparator change 110 =VIL on INT pin(1) 111 =VIL on INT pin or Comparator change bit 3-2 PSSAC<1:0>: Pin P1A Shutdown State Control bits 00 = Drive pin P1A to ‘0’ 01 = Drive pin P1A to ‘1’ 1x = Pin P1A tri-state bit 1-0 PSSBD<1:0>: Pin P1B Shutdown State Control bits 00 = Drive pin P1B to ‘0’ 01 = Drive pin P1B to ‘1’ 1x = Pin P1B tri-state Note 1: If CMSYNC is enabled, the shutdown will be delayed by Timer1. Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period. 2010 Microchip Technology Inc. DS41302D-page 103 PIC12F609/615/617/12HV609/615 FIGURE 11-11: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) 11.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 11-12: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) Shutdown PWM ECCPASE bit Activity Event Shutdown Event Occurs Shutdown Event Clears PWM Resumes PWM Period Start of PWM Period ECCPASE Cleared by Firmware Shutdown PWM ECCPASE bit Activity Event Shutdown Event Occurs Shutdown Event Clears PWM Resumes PWM Period Start of PWM Period PIC12F609/615/617/12HV609/615 DS41302D-page 104 2010 Microchip Technology Inc. 11.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 11-13 for illustration. The lower seven bits of the associated PWMxCON register (Register 11-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 11-13: EXAMPLE OF HALFBRIDGE PWM OUTPUT FIGURE 11-14: EXAMPLE OF HALF-BRIDGE APPLICATIONS Period Pulse Width td td (1) P1A(2) P1B(2) td = Dead-Band Delay Period (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. P1A P1B FET Driver FET Driver V+ VLoad + V- + VStandard Half-Bridge Circuit (“Push-Pull”) 2010 Microchip Technology Inc. DS41302D-page 105 PIC12F609/615/617/12HV609/615 TABLE 11-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn =Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets APFCON — — — T1GSEL — — P1BSEL P1ASEL ---0 --00 ---0 --00 CCP1CON(1) P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H(1) Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu CMCON0 CMON COUT CMOE CMPOL — CMR — CMCH 0000 -0-0 0000 -0-0 CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 ---0 0-10 ECCPAS(1) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00 PIR1 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00 T2CON(1) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TMR2(1) Timer2 Module Register 0000 0000 0000 0000 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. Note 1: For PIC12F615/617/HV615 only. PIC12F609/615/617/12HV609/615 DS41302D-page 106 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 107 PIC12F609/615/617/12HV609/615 12.0 SPECIAL FEATURES OF THE CPU The PIC12F609/615/617/12HV609/615 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Oscillator selection • Sleep • Code protection • ID Locations • In-Circuit Serial Programming The PIC12F609/615/617/12HV609/615 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Powerup Timer to provide at least a 64 ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through: • External Reset • Watchdog Timer Wake-up • An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1). 12.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h- 3FFFh), which can be accessed only during programming. See Memory Programming Specification (DS41204) for more information. PIC12F609/615/617/12HV609/615 DS41302D-page 108 2010 Microchip Technology Inc. REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER (ADDRESS: 2007h) FOR PIC12F609/615/HV609/615 ONLY U-1 U-1 U-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BOREN1(1) BOREN0(1) IOSCFS CP(2) MCLRE(3) PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 13 bit 0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set P = Programmable ‘0’ = Bit is cleared U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 13-10 Unimplemented: Read as ‘1’ bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 0x = BOR disabled bit 7 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz 0 = 4 MHz bit 6 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: MCLR Pin Function Select bit(3) 1 = MCLR pin function is MCLR 0 = MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 =RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 110 =RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 101 =INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 011 =EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN 010 =HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire program memory will be erased when the code protection is turned off. 3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. 2010 Microchip Technology Inc. DS41302D-page 109 PIC12F609/615/617/12HV609/615 REGISTER 12-2: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) FOR PIC12F617 ONLY U-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — WRT1 WRT0 BOREN1 BOREN0 IOSCFS CP MCLRE PWRTE WDTE FOSC2 F0SC1 F0SC0 bit 13 bit 0 bit 13-12 Unimplemented: Read as ‘1’ bit 11-10 WRT<1:0>: Flash Program Memory Self Write Enable bits 11 =Write protection off 10 = 000h to 1FFh write protected, 200h to 7FFh may be modified by PMCON1 control 01 = 000h to 3FFh write protected, 400h to 7FFh may be modified by PMCON1 control 00 = 000h to 7FFh write protected, entire program memory is write protected. bit 9-8 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR disabled during Sleep and enabled during operation 0X = BOR disabled bit 7 IOSCFS: Internal Oscillator Frequency Select 1 = 8 MHz 0 = 4 MHz bit 6 CP: Code Protection 1 = Program memory is not code protected 0 = Program memory is external read and write protected bit 5 MCLRE: MCLR Pin Function Select 1 = MCLR pin is MCLR function and weak internal pull-up is enabled 0 = MCLR pin is alternate function, MCLR function is internally disabled bit 4 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 000 =LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT 001 =XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT 010 =HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT 011 =EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN 100 =INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN 101 =INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/ CLKIN 110 =EXTRCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN 111 =EXTRC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN Note 1:Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’ P = Programmable -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown PIC12F609/615/617/12HV609/615 DS41302D-page 110 2010 Microchip Technology Inc. 12.2 Calibration Bits The 8 MHz internal oscillator is factory calibrated. These calibration values are stored in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the Memory Programming Specification (DS41204) and thus, does not require reprogramming. 12.3 Reset The PIC12F609/615/617/12HV609/615 device differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • Power-on Reset • MCLR Reset • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (BOR) WDT wake-up does not cause register resets in the same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-2. Software can use these bits to determine the nature of the Reset. See Table 12-5 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 16.0 “Electrical Specifications” for pulse-width specifications. FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT S R Q External Reset MCLR/VPP pin VDD OSC1/ WDT Module VDD Rise Detect OST/PWRT On-Chip WDT Time-out Power-on Reset OST 10-bit Ripple Counter PWRT Chip_Reset 11-bit Ripple Counter Reset Enable OST Enable PWRT Sleep Brown-out(1) Reset BOREN CLKIN pin Note 1: Refer to the Configuration Word register (Register 12-1). RC OSC 2010 Microchip Technology Inc. DS41302D-page 111 PIC12F609/615/617/12HV609/615 12.3.1 POWER-ON RESET (POR) The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 16.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 12.3.4 “Brown-out Reset (BOR)”). When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC12F609/615/617/12HV609/615 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Voltages applied to the MCLR pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 12-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the GP3/MCLR pin becomes an external Reset input. In this mode, the GP3/MCLR pin has a weak pull-up to VDD. FIGURE 12-2: RECOMMENDED MCLR CIRCUIT 12.3.3 POWER-UP TIMER (PWRT) The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from an internal RC oscillator. For more information, see Section 4.4 “Internal Clock Modes”. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip due to: • VDD variation • Temperature variation • Process variation See DC parameters for details (Section 16.0 “Electrical Specifications”). Note: The POR circuit does not produce an internal Reset when VDD declines. To reenable the POR, VDD must reach Vss for a minimum of 100 s. Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. VDD PIC® MCLR R1 1 kor greater) C1 0.1 F (optional, not critical) R2 100 SW1 needed with capacitor) (optional) MCU PIC12F609/615/617/12HV609/615 DS41302D-page 112 2010 Microchip Technology Inc. 12.3.4 BROWN-OUT RESET (BOR) The BOREN0 and BOREN1 bits in the Configuration Word register select one of three BOR modes. One mode has been added to allow control of the BOR enable for lower current during Sleep. By selecting BOREN<1:0> = 10, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. See Register 12-1 for the Configuration Word definition. A brown-out occurs when VDD falls below VBOR for greater than parameter TBOR (see Section 16.0 “Electrical Specifications”). The brown-out condition will reset the device. This will occur regardless of VDD slew rate. A Brown-out Reset may not occur if VDD falls below VBOR for less than parameter TBOR. On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 12-3). If enabled, the Powerup Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset. FIGURE 12-3: BROWN-OUT SITUATIONS Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register. 64 ms(1) VBOR VDD Internal Reset VBOR VDD Internal Reset 64 ms < 64 ms (1) 64 ms(1) VBOR VDD Internal Reset Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’. 2010 Microchip Technology Inc. DS41302D-page 113 PIC12F609/615/617/12HV609/615 12.3.5 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: • PWRT time-out is invoked after POR has expired. • OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F609/615/617/ 12HV609/615 device operating in parallel. Table 12-6 shows the Reset conditions for some special registers, while Table 12-5 shows the Reset conditions for all the registers. 12.3.6 POWER CONTROL (PCON) REGISTER The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred last. Bit 0 is BOR (Brown-out). BOR is unknown on Poweron Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR is ‘0’, it will indicate that a Poweron Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 12.3.4 “Brown-out Reset (BOR)”. TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Oscillator Configuration Power-up Brown-out Reset Wake-up from PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 Sleep XT, HS, LP TPWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC RC, EC, INTOSC TPWRT — TPWRT — — POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets(1) PCON — — — — — — POR BOR ---- --qq ---- --uu STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. PIC12F609/615/617/12HV609/615 DS41302D-page 114 2010 Microchip Technology Inc. FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) TPWRT TOST VDD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset VDD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset TPWRT TOST TOST VDD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset TPWRT 2010 Microchip Technology Inc. DS41302D-page 115 PIC12F609/615/617/12HV609/615 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (PIC12F609/HV609) Register Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu GPIO 05h --x0 x000 --u0 u000 --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2) PIR1 0Ch ----- 0--0 ---- 0--0 ---- u--u(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu VRCON 19h 0-00 0000 0-00 0000 u-uu uuuu CMCON0 1Ah 0000 -0-0 0000 -0-0 uuuu -u-u CMCON1 1Ch ---0 0-10 ---0 0-10 ---u u-qu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISIO 85h --11 1111 --11 1111 --uu uuuu PIE1 8Ch ----- 0--0 ---- 0--0 ---- u--u PCON 8Eh ---- --0x ---- --uu(1, 5) ---- --uu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu WPU 95h --11 -111 --11 -111 --uu -uuu IOC 96h --00 0000 --00 0000 --uu uuuu ANSEL 9Fh ---- 1-11 ---- 1-11 ---- q-qq Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 12-6 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. PIC12F609/615/617/12HV609/615 DS41302D-page 116 2010 Microchip Technology Inc. TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (PIC12F615/617/HV615) Register Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu GPIO 05h --x0 x000 --u0 u000 --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2) PIR1 0Ch -000 0-00 -000 0-00 -uuu u-uu(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu TMR2(1) 11h 0000 0000 0000 0000 uuuu uuuu T2CON(1) 12h -000 0000 -000 0000 -uuu uuuu CCPR1L(1) 13h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H(1) 14h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON(1) 15h 0-00 0000 0-00 0000 u-uu uuuu PWM1CON(1) 16h 0000 0000 0000 0000 uuuu uuuu ECCPAS(1) 17h 0000 0000 0000 0000 uuuu uuuu VRCON 19h 0-00 0000 0-00 0000 u-uu uuuu CMCON0 1Ah 0000 -0-0 0000 -0-0 uuuu -u-u CMCON1 1Ch ---0 0-10 ---0 0-10 ---u u-qu ADRESH(1) 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0(1) 1Fh 00-0 0000 00-0 0000 uu-u uuuu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISIO 85h --11 1111 --11 1111 --uu uuuu PIE1 8Ch -00- 0-00 -00- 0-00 -uu- u-uu PCON 8Eh ---- --0x ---- --uu(1, 5) ---- --uu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu PR2 92h 1111 1111 1111 1111 1111 1111 APFCON 93h ---0 --00 ---0 --00 ---u --uu WPU 95h --11 -111 --11 -111 --uu -uuu IOC 96h --00 0000 --00 0000 --uu uuuu PMCON1(6) 98h ---- -000 ---- -000 ---- -uuu PMCON2(6) 99h ---- ---- ---- ---- ---- ---- PMADRL(6) 9Ah 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 12-6 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: For PIC12F617 only. 2010 Microchip Technology Inc. DS41302D-page 117 PIC12F609/615/617/12HV609/615 TABLE 12-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS PMADRH(6) 9Bh ---- -000 ---- -000 ---- -uuu PMDATL(6) 9Ch 0000 0000 0000 0000 uuuu uuuu PMDATH(6) 9Dh --00 0000 --00 0000 --uu uuuu ADRESL(1) 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ANSEL 9Fh -000 1111 -000 1111 -uuu qqqq Condition Program Counter Status Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --10 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)(PIC12F615/617/HV615) Register Address Power-on Reset MCLR Reset WDT Reset (Continued) Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 12-6 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: For PIC12F617 only. PIC12F609/615/617/12HV609/615 DS41302D-page 118 2010 Microchip Technology Inc. 12.4 Interrupts The PIC12F609/615/617/12HV609/615 has 8 sources of interrupt: • External Interrupt GP2/INT • Timer0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt (PIC12F615/617/HV615 only) • Timer1 Overflow Interrupt • Timer2 Match Interrupt (PIC12F615/617/HV615 only) • Enhanced CCP Interrupt (PIC12F615/617/HV615 only) • Flash Memory Self Write (PIC12F617 only) The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. The Global Interrupt Enable bit, GIE of the INTCON register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. When an interrupt is serviced, the following actions occur automatically: • The GIE is cleared to disable any further interrupt. • The return address is pushed onto the stack. • The PC is loaded with 0004h. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: • INT Pin Interrupt • GPIO Change Interrupt • Timer0 Overflow Interrupt The peripheral interrupt flags are contained in the special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1. The following interrupt flags are contained in the PIR1 register: • A/D Interrupt • Comparator Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • Enhanced CCP Interrupt For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 12-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. For additional information on Timer1, Timer2, comparators, ADC, Enhanced CCP modules, refer to the respective peripheral section. 12.4.1 GP2/INT INTERRUPT The external interrupt on the GP2/INT pin is edgetriggered; either on the rising edge if the INTEDG bit of the OPTION register is set, or the falling edge, if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must be cleared by software in the Interrupt Service Routine before re-enabling this interrupt. The GP2/INT interrupt can wake-up the processor from Sleep, if the INTE bit was set prior to going into Sleep. See Section 12.7 “Power-Down Mode (Sleep)” for details on Sleep and Figure 12-9 for timing of wake-up from Sleep through GP2/INT interrupt. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. Note: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. 2010 Microchip Technology Inc. DS41302D-page 119 PIC12F609/615/617/12HV609/615 12.4.2 TIMER0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 6.0 “Timer0 Module” for operation of the Timer0 module. 12.4.3 GPIO INTERRUPT-ON-CHANGE An input change on GPIO sets the GPIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the GPIE bit of the INTCON register. Plus, individual pins can be configured through the IOC register. FIGURE 12-7: INTERRUPT LOGIC Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. TMR1IF TMR1IE CMIF CMIE T0IF T0IE INTF INTE GPIF GPIE GIE PEIE Wake-up (If in Sleep mode)(1) Interrupt to CPU ADIF ADIE IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR2IF TMR2IE CCP1IF CCP1IE Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”. (615/617 (615/617 only) (615/617 only) only) PIC12F609/615/617/12HV609/615 DS41302D-page 120 2010 Microchip Technology Inc. FIGURE 12-8: INT PIN INTERRUPT TIMING TABLE 12-7: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 PIR1 — ADIF(1) CCP1IF(1) — CMIF — TMR2IF(1) TMR1IF -00- 0-00 -000 0-00 PIE1 — ADIE(1) CCP1IE(1) — CMIE — TMR2IE(1) TMR1IE -00- 0-00 -000 0-00 Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC12F615/617/HV615 only. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Interrupt Latency PC PC + 1 PC + 1 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (PC) Inst (PC + 1) Inst (PC – 1) Inst (PC) Dummy Cycle Inst (0004h) — Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 16.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. (1) (2) (3) (4) (1) (5) 2010 Microchip Technology Inc. DS41302D-page 121 PIC12F609/615/617/12HV609/615 12.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure 2-3). These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler. The code shown in Example 12-1 can be used to: • Store the W register • Store the STATUS register • Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register EXAMPLE 12-1: SAVING STATUS AND W REGISTERS IN RAM 12.6 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator, which requires no external components. This RC oscillator is separate from the external RC oscillator of the CLKIN pin and INTOSC. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example, by execution of a SLEEP instruction). During normal operation, a WDT time out generates a device Reset. If the device is in Sleep mode, a WDT time out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the Configuration bit, WDTE, as clear (Section 12.1 “Configuration Bits”). 12.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out. Note: The PIC12F609/615/617/12HV609/615 does not require saving the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR. MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W PIC12F609/615/617/12HV609/615 DS41302D-page 122 2010 Microchip Technology Inc. 12.6.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worstcase conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT time out occurs. FIGURE 12-2: WATCHDOG TIMER BLOCK DIAGRAM TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER TABLE 12-8: WDT STATUS Conditions WDT WDTE = 0 Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 CONFIG IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits. T0CKI T0SE pin CLKOUT TMR0 Watchdog Timer WDT Time-Out PS<2:0> WDTE Data Bus Set Flag bit T0IF on Overflow T0CS Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 0 1 0 1 0 1 SYNC 2 Cycles 8 8 8-bit Prescaler 0 1 (= FOSC/4) PSA PSA PSA 3 2010 Microchip Technology Inc. DS41302D-page 123 PIC12F609/615/617/12HV609/615 12.7 Power-Down Mode (Sleep) The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • WDT will be cleared but keeps running. • PD bit in the STATUS register is cleared. • TO bit is set. • Oscillator driver is turned off. • I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are highimpedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pullups on GPIO should be considered. The MCLR pin must be at a logic high level. 12.7.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin. 2. Watchdog Timer wake-up (if WDT was enabled). 3. Interrupt from GP2/INT pin, GPIO change or a peripheral interrupt. The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. Timer1 interrupt. Timer1 must be operating as an asynchronous counter. 2. ECCP Capture mode interrupt. 3. A/D conversion (when A/D clock source is RC). 4. Comparator output changes state. 5. Interrupt-on-change. 6. External Interrupt from INT pin. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. 12.7.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will Immediately wake-up from Sleep. The SLEEP instruction is executed. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 12-9 for more details. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low. Note: If the global interrupts are disabled (GIE is cleared) and any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. PIC12F609/615/617/12HV609/615 DS41302D-page 124 2010 Microchip Technology Inc. FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT 12.8 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. 12.9 ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC – 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(3) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) PC + 2 0004h 0005h Dummy Cycle TOST(2) PC + 2 Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes. 3: GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. Note: The entire Flash program memory will be erased when the code protection is turned off. See the MemoryProgramming Specification (DS41204) for more information. 2010 Microchip Technology Inc. DS41302D-page 125 PIC12F609/615/617/12HV609/615 12.10 In-Circuit Serial Programming™ ThePIC12F609/615/617/12HV609/615 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five connections for: • clock • data • power • ground • programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the GP0 and GP1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the Memory Programming Specification (DS41284) for more information. GP0 becomes the programming data and GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Trigger inputs in Program/Verify mode. A typical In-Circuit Serial Programming connection is shown in Figure 12-10. FIGURE 12-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION 12.11 In-Circuit Debugger Since in-circuit debugging requires access to three pins, MPLAB® ICD 2 development with an 14-pin device is not practical. A special 28-pin PIC12F609/615/617/ 12HV609/615 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. A special debugging adapter allows the ICD device to be used in place of a PIC12F609/615/617/12HV609/ 615 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC12F609/615/617/ 12HV609/615 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 12-10 shows which features are consumed by the background debugger. TABLE 12-10: DEBUGGER RESOURCES For more information, see “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com). FIGURE 12-11: 28 PIN ICD PINOUT Note: To erase the device VDD must be above the Bulk Erase VDD minimum given in the Memory Programming Specification (DS41284) External Connector Signals To Normal Connections To Normal Connections PIC12F615/12HV615 VDD VSS MCLR/VPP/GP3/RA3 GP1 GP0 +5V 0V VPP CLK Data I/O * * * * * Isolation devices (as required) PIC12F609/12HV609 PIC12F617/ Resource Description I/O pins ICDCLK, ICDDATA Stack 1 level Program Memory Address 0h must be NOP 700h-7FFh 28-Pin PDIP In-Circuit Debug Device VDD CS0 CS1 CS2 RA5 RA4 GND RA0 RA1 SHUNTEN RC3 NC RA2 RC0 RA3 RC5 RC4 RC1 RC2 NC 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 ICDDATA ICD NC ICDCLK ICDMCLR NC NC NC 11 12 13 14 18 17 16 15 PIC16F616-ICD PIC12F609/615/617/12HV609/615 DS41302D-page 126 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 127 PIC12F609/615/617/12HV609/615 13.0 VOLTAGE REGULATOR The PIC12HV609/HV615 devices include a permanent internal 5 volt (nominal) shunt regulator in parallel with the VDD pin. This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All external devices connected directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). 13.1 Regulator Operation A shunt regulator generates a specific supply voltage by creating a voltage drop across a pass resistor RSER. The voltage at the VDD pin of the microcontroller is monitored and compared to an internal voltage reference. The current through the resistor is then adjusted, based on the result of the comparison, to produce a voltage drop equal to the difference between the supply voltage VUNREG and the VDD of the microcontroller. See Figure 13-1 for voltage regulator schematic. FIGURE 13-1: VOLTAGE REGULATOR An external current limiting resistor, RSER, located between the unregulated supply, VUNREG, and the VDD pin, drops the difference in voltage between VUNREG and VDD. RSER must be between RMAX and RMIN as defined by Equation 13-1. EQUATION 13-1: RSER LIMITING RESISTOR 13.2 Regulator Considerations The supply voltage VUNREG and load current are not constant. Therefore, the current range of the regulator is limited. Selecting a value for RSER must take these three factors into consideration. Since the regulator uses the band gap voltage as the regulated voltage reference, this voltage reference is permanently enabled in the PIC12HV609/HV615 devices. The shunt regulator will still consume current when below operating voltage range for the shunt regulator. 13.3 Design Considerations For more information on using the shunt regulator and managing current load, see Application Note AN1035, “Designing with HV Microcontrollers” (DS01035). Feedback VDD VSS CBYPASS RSER VUNREG ISUPPLY ISHUNT ILOAD Device RMAX = (VUMIN - 5V) 1.05 • (4 MA + ILOAD) RMIN = (VUMAX - 5V) 0.95 • (50 MA) Where: RMAX = maximum value of RSER (ohms) RMIN = minimum value of RSER (ohms) VUMIN = minimum value of VUNREG VUMAX= maximum value of VUNREG VDD = regulated voltage (5V nominal) ILOAD = maximum expected load current in mA including I/O pin currents and external circuits connected to VDD. 1.05 = compensation for +5% tolerance of RSER 0.95 = compensation for -5% tolerance of RSER PIC12F609/615/617/12HV609/615 DS41302D-page 128 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 129 PIC12F609/615/617/12HV609/615 14.0 INSTRUCTION SET SUMMARY The PIC12F609/615/617/12HV609/615 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 14-1, while the various opcode fields are summarized in Table 14-1. Table 14-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the W register. If ‘d’ is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which the bit is located. For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. 14.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (RMW) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended consequence of clearing the condition that set the GPIF flag. TABLE 14-1: OPCODE FIELD DESCRIPTIONS FIGURE 14-1: GENERAL FORMAT FOR INSTRUCTIONS Field Description f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit Byte-oriented file register operations 13 8 7 6 0 d = 0 for destination W OPCODE d f (FILE #) d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value General CALL and GOTO instructions only PIC12F609/615/617/12HV609/615 DS41302D-page 130 2010 Microchip Technology Inc. TABLE 14-2: PIC12F609/615/617/12HV609/615 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode Status Affected Notes MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f– f, d f, d f, d f, d f, d f, d f, d f– f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 111111 1(2) 1 1(2) 111111111 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C, DC, Z ZZZZZ Z ZZ CC C, DC, Z Z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 11 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1, 2 1, 2 33 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW kkk–kkk–k––kk Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1121211222111 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C, DC, Z Z TO, PD Z TO, PD C, DC, Z Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2010 Microchip Technology Inc. DS41302D-page 131 PIC12F609/615/617/12HV609/615 14.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW k Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. ADDWF Add W and f Syntax: [ label ] ADDWF f,d Operands: 0 f 127 d 0,1 Operation: (W) + (f) (destination) Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W Syntax: [ label ] ANDLW k Operands: 0 k 255 Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0 f 127 d 0,1 Operation: (W) .AND. (f) (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. BCF Bit Clear f Syntax: [ label ] BCF f,b Operands: 0 f 127 0 b 7 Operation: 0 (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0 f 127 0 b 7 Operation: 1 (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b Operands: 0 f 127 0 b 7 Operation: skip if (f) = 0 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction. PIC12F609/615/617/12HV609/615 DS41302D-page 132 2010 Microchip Technology Inc. BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands: 0 f 127 0 b < 7 Operation: skip if (f) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. CALL Call Subroutine Syntax: [ label ] CALL k Operands: 0 k 2047 Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Status Affected: None Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF f Operands: 0 f 127 Operation: 00h (f) 1 Z Status Affected: Z Description: The contents of register ‘f’ are cleared and the Z bit is set. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h (W) 1 Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. COMF Complement f Syntax: [ label ] COMF f,d Operands: 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DECF Decrement f Syntax: [ label ] DECF f,d Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2010 Microchip Technology Inc. DS41302D-page 133 PIC12F609/615/617/12HV609/615 DECFSZ Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making it a two-cycle instruction. GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 k 2047 Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: None Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f Syntax: [ label ] INCF f,d Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Status Affected: Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, a NOP is executed instead, making it a two-cycle instruction. IORLW Inclusive OR literal with W Syntax: [ label ] IORLW k Operands: 0 k 255 Operation: (W) .OR. k (W) Status Affected: Z Description: The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d Operands: 0 f 127 d [0,1] Operation: (W) .OR. (f) (destination) Status Affected: Z Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. PIC12F609/615/617/12HV609/615 DS41302D-page 134 2010 Microchip Technology Inc. MOVF Move f Syntax: [ label ] MOVF f,d Operands: 0 f 127 d [0,1] Operation: (f) (dest) Status Affected: Z Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself. d = 1 is useful to test a file register since Status flag Z is affected. Words: 1 Cycles: 1 Example: MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W Syntax: [ label ] MOVLW k Operands: 0 k 255 Operation: k (W) Status Affected: None Description: The eight-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘0’s. Words: 1 Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A MOVWF Move W to f Syntax: [ label ] MOVWF f Operands: 0 f 127 Operation: (W) (f) Status Affected: None Description: Move data from W register to register ‘f’. Words: 1 Cycles: 1 Example: MOVW F OPTION Before Instruction OPTION= 0xFF W = 0x4F After Instruction OPTION= 0x4F W = 0x4F NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Description: No operation. Words: 1 Cycles: 1 Example: NOP 2010 Microchip Technology Inc. DS41302D-page 135 PIC12F609/615/617/12HV609/615 RETFIE Return from Interrupt Syntax: [ label ] RETFIE Operands: None Operation: TOS PC, 1 GIE Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON< 7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W Syntax: [ label ] RETLW k Operands: 0 k 255 Operation: k (W); TOS PC Status Affected: None Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: TABLE DONE CALL TABLE;W contains ;table offset ;value GOTO DONE • • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ;End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. PIC12F609/615/617/12HV609/615 DS41302D-page 136 2010 Microchip Technology Inc. RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 Cycles: 1 Example: RLF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. C Register f C Register f SLEEP Enter Sleep mode Syntax: [ label ] SLEEP Operands: None Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. SUBLW Subtract W from literal Syntax: [ label ] SUBLW k Operands: 0 k 255 Operation: k - (W) W) Status Affected: C, DC, Z Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. Result Condition C = 0 W k C = 1 W k DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> 2010 Microchip Technology Inc. DS41302D-page 137 PIC12F609/615/617/12HV609/615 SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Status Affected: C, DC, Z Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0 f 127 d [0,1] Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. C = 0 W f C = 1 W f DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> XORWF Exclusive OR W with f Syntax: [ label ] XORWF f,d Operands: 0 f 127 d [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. PIC12F609/615/617/12HV609/615 DS41302D-page 138 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 139 PIC12F609/615/617/12HV609/615 15.0 DEVELOPMENT SUPPORT The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 15.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. PIC12F609/615/617/12HV609/615 DS41302D-page 140 2010 Microchip Technology Inc. 15.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 15.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 15.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process 15.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 15.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • Support for the entire device instruction set • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility 2010 Microchip Technology Inc. DS41302D-page 141 PIC12F609/615/617/12HV609/615 15.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 15.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 15.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto- use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 15.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming ™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. PIC12F609/615/617/12HV609/615 DS41302D-page 142 2010 Microchip Technology Inc. 15.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 15.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. 15.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/ development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2010 Microchip Technology Inc. DS41302D-page 143 PIC12F609/615/617/12HV609/615 16.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ...............................................................................................................................800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by GPIO...................................................................................................................... 90 mA Maximum current sourced GPIO...................................................................................................................... 90 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. PIC12F609/615/617/12HV609/615 DS41302D-page 144 2010 Microchip Technology Inc. FIGURE 16-1: PIC12F609/615/617 VOLTAGE-FREQUENCY GRAPH, -40°C TA +125°C FIGURE 16-2: PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH, -40°C TA +125°C 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 Frequency (MHz) VDD (V) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 8 10 20 5.5 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 Frequency (MHz) VDD (V) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 8 10 20 2010 Microchip Technology Inc. DS41302D-page 145 PIC12F609/615/617/12HV609/615 16.1 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions VDD Supply Voltage D001 PIC12F609/615/617 2.0 — 5.5 V FOSC < = 4 MHz D001 PIC12HV609/615 2.0 — —(2) V FOSC < = 4 MHz D001B PIC12F609/615/617 2.0 — 5.5 V FOSC < = 8 MHz D001B PIC12HV609/615 2.0 — —(2) V FOSC < = 8 MHz D001C PIC12F609/615/617 3.0 — 5.5 V FOSC < = 10 MHz D001C PIC12HV609/615 3.0 — —(2) V FOSC < = 10 MHz D001D PIC12F609/615/617 4.5 — 5.5 V FOSC < = 20 MHz D001D PIC12HV609/615 4.5 — —(2) V FOSC < = 20 MHz D002* VDR RAM Data Retention Voltage(1) 1.5 — — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal — VSS — V See Section 12.3.1 “Power-on Reset (POR)” for details. D004* SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 — — V/ms See Section 12.3.1 “Power-on Reset (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: User defined. Voltage across the shunt regulator should not exceed 5V. PIC12F609/615/617/12HV609/615 DS41302D-page 146 2010 Microchip Technology Inc. 16.2 DC Characteristics: PIC12F609/615/617-I (Industrial) PIC12F609/615/617-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D010 Supply Current (IDD)(1, 2) — 13 25 A 2.0 FOSC = 32 kHz PIC12F609/615/617 — 19 29 A 3.0 LP Oscillator mode — 32 51 A 5.0 D011* — 135 225 A 2.0 FOSC = 1 MHz — 185 285 A 3.0 XT Oscillator mode — 300 405 A 5.0 D012 — 240 360 A 2.0 FOSC = 4 MHz — 360 505 A 3.0 XT Oscillator mode — 0.66 1.0 mA 5.0 D013* — 75 110 A 2.0 FOSC = 1 MHz — 155 255 A 3.0 EC Oscillator mode — 345 530 A 5.0 D014 — 185 255 A 2.0 FOSC = 4 MHz — 325 475 A 3.0 EC Oscillator mode — 0.665 1.0 mA 5.0 D016* — 245 340 A 2.0 FOSC = 4 MHz — 360 485 A 3.0 INTOSC mode — 0.620 0.845 mA 5.0 D017 — 395 550 A 2.0 FOSC = 8 MHz — 0.620 0.850 mA 3.0 INTOSC mode — 1.2 1.6 mA 5.0 D018 — 175 235 A 2.0 FOSC = 4 MHz EXTRC mode(3) — 285 390 A 3.0 — 530 750 A 5.0 D019 — 2.2 3.1 mA 4.5 FOSC = 20 MHz HS Oscillator mode — 2.8 3.35 mA 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-torail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in KOhms (K 2010 Microchip Technology Inc. DS41302D-page 147 PIC12F609/615/617/12HV609/615 16.3 DC Characteristics: PIC12HV609/615-I (Industrial) PIC12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D010 Supply Current (IDD)(1, 2) — 160 230 A 2.0 FOSC = 32 kHz PIC12HV609/615 — 240 310 A 3.0 LP Oscillator mode — 280 400 A 4.5 D011* — 270 380 A 2.0 FOSC = 1 MHz — 400 560 A 3.0 XT Oscillator mode — 520 780 A 4.5 D012 — 380 540 A 2.0 FOSC = 4 MHz — 575 810 A 3.0 XT Oscillator mode — 0.875 1.3 mA 4.5 D013* — 215 310 A 2.0 FOSC = 1 MHz — 375 565 A 3.0 EC Oscillator mode — 570 870 A 4.5 D014 — 330 475 A 2.0 FOSC = 4 MHz — 550 800 A 3.0 EC Oscillator mode — 0.85 1.2 mA 4.5 D016* — 310 435 A 2.0 FOSC = 4 MHz — 500 700 A 3.0 INTOSC mode — 0.74 1.1 mA 4.5 D017 — 460 650 A 2.0 FOSC = 8 MHz — 0.75 1.1 mA 3.0 INTOSC mode — 1.2 1.6 mA 4.5 D018 — 320 465 A 2.0 FOSC = 4 MHz EXTRC mode(3) — 510 750 A 3.0 — 0.770 1.0 mA 4.5 D019 — 2.5 3.4 mA 4.5 FOSC = 20 MHz HS Oscillator mode * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k PIC12F609/615/617/12HV609/615 DS41302D-page 148 2010 Microchip Technology Inc. 16.4 DC Characteristics: PIC12F609/615/617 - I (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D020 Power-down Base Current (IPD)(2) — 0.05 0.9 A 2.0 WDT, BOR, Comparator, VREF and T1OSC disabled — 0.15 1.2 A 3.0 PIC12F609/615/617 — 0.35 1.5 A 5.0 150 500 nA 3.0 -40°C TA +25°C for industrial D021 — 0.5 1.5 A 2.0 WDT Current(1) — 2.5 4.0 A 3.0 — 9.5 17 A 5.0 D022 — 5.0 9 A 3.0 BOR Current(1) — 6.0 12 A 5.0 D023 — 50 60 A 2.0 Comparator Current(1), single — 55 65 A 3.0 comparator enabled — 60 75 A 5.0 D024 — 30 40 A 2.0 CVREF Current(1) (high range) — 45 60 A 3.0 — 75 105 A 5.0 D025* — 39 50 A 2.0 CVREF Current(1) (low range) — 59 80 A 3.0 — 98 130 A 5.0 D026 — 5.5 10 A 2.0 T1OSC Current(1), 32.768 kHz — 7.0 12 A 3.0 — 8.5 14 A 5.0 D027 — 0.2 1.6 A 3.0 A/D Current(1), no conversion in — 0.36 1.9 A 5.0 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 2010 Microchip Technology Inc. DS41302D-page 149 PIC12F609/615/617/12HV609/615 16.5 DC Characteristics: PIC12F609/615/617 - E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C for extended Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D020E Power-down Base Current (IPD)(2) PIC12F609/615/617 — 0.05 4.0 A 2.0 WDT, BOR, Comparator, VREF and — 0.15 5.0 A 3.0 T1OSC disabled — 0.35 8.5 A 5.0 D021E — 0.5 5.0 A 2.0 WDT Current(1) — 2.5 8.0 A 3.0 — 9.5 19 A 5.0 D022E — 5.0 15 A 3.0 BOR Current(1) — 6.0 19 A 5.0 D023E — 50 70 A 2.0 Comparator Current(1), single — 55 75 A 3.0 comparator enabled — 60 80 A 5.0 D024E — 30 40 A 2.0 CVREF Current(1) (high range) — 45 60 A 3.0 — 75 105 A 5.0 D025E* — 39 50 A 2.0 CVREF Current(1) (low range) — 59 80 A 3.0 — 98 130 A 5.0 D026E — 5.5 16 A 2.0 T1OSC Current(1), 32.768 kHz — 7.0 18 A 3.0 — 8.5 22 A 5.0 D027E — 0.2 6.5 A 3.0 A/D Current(1), no conversion in — 0.36 10 A 5.0 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. PIC12F609/615/617/12HV609/615 DS41302D-page 150 2010 Microchip Technology Inc. 16.6 DC Characteristics: PIC12HV609/615 - I (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D020 Power-down Base Current (IPD)(2,3) — 135 200 A 2.0 WDT, BOR, Comparator, VREF and T1OSC disabled — 210 280 A 3.0 PIC12HV609/615 — 260 350 A 4.5 D021 — 135 200 A 2.0 WDT Current(1) — 210 285 A 3.0 — 265 360 A 4.5 D022 — 215 285 A 3.0 BOR Current(1) — 265 360 A 4.5 D023 — 185 270 A 2.0 Comparator Current(1), single — 265 350 A 3.0 comparator enabled — 320 430 A 4.5 D024 — 165 235 A 2.0 CVREF Current(1) (high range) — 255 330 A 3.0 — 330 430 A 4.5 D025* — 175 245 A 2.0 CVREF Current(1) (low range) — 275 350 A 3.0 — 355 450 A 4.5 D026 — 140 205 A 2.0 T1OSC Current(1), 32.768 kHz — 220 290 A 3.0 — 270 360 A 4.5 D027 — 210 280 A 3.0 A/D Current(1), no conversion in — 260 350 A 4.5 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Shunt regulator is always on and always draws operating current. 2010 Microchip Technology Inc. DS41302D-page 151 PIC12F609/615/617/12HV609/615 16.7 DC Characteristics: PIC12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C for extended Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D020E Power-down Base Current (IPD)(2,3) PIC12HV609/615 — 135 200 A 2.0 WDT, BOR, Comparator, VREF and — 210 280 A 3.0 T1OSC disabled — 260 350 A 4.5 D021E — 135 200 A 2.0 WDT Current(1) — 210 285 A 3.0 — 265 360 A 4.5 D022E — 215 285 A 3.0 BOR Current(1) — 265 360 A 4.5 D023E — 185 280 A 2.0 Comparator Current(1), single — 265 360 A 3.0 comparator enabled — 320 430 A 4.5 D024E — 165 235 A 2.0 CVREF Current(1) (high range) — 255 330 A 3.0 — 330 430 A 4.5 D025E* — 175 245 A 2.0 CVREF Current(1) (low range) — 275 350 A 3.0 — 355 450 A 4.5 D026E — 140 205 A 2.0 T1OSC Current(1), 32.768 kHz — 220 290 A 3.0 — 270 360 A 4.5 D027E — 210 280 A 3.0 A/D Current(1), no conversion in — 260 350 A 4.5 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Shunt regulator is always on and always draws operating current. PIC12F609/615/617/12HV609/615 DS41302D-page 152 2010 Microchip Technology Inc. 16.8 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions VIL Input Low Voltage I/O port: D030 with TTL buffer Vss — 0.8 V 4.5V VDD 5.5V D030A Vss — 0.15 VDD V 2.0V VDD 4.5V D031 with Schmitt Trigger buffer Vss — 0.2 VDD V 2.0V VDD 5.5V D032 MCLR, OSC1 (RC mode) VSS — 0.2 VDD V (NOTE 1) D033 OSC1 (XT and LP modes) VSS — 0.3 V D033A OSC1 (HS mode) VSS — 0.3 VDD V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V VDD 5.5V D040A 0.25 VDD + 0.8 — VDD V 2.0V VDD 4.5V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V 2.0V VDD 5.5V D042 MCLR 0.8 VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V D043A OSC1 (HS mode) 0.7 VDD — VDD V D043B OSC1 (RC mode) 0.9 VDD — VDD V (NOTE 1) IIL Input Leakage Current(2,3) D060 I/O ports — 0.1 1 A VSS VPIN VDD, Pin at high-impedance D061 GP3/MCLR(3,4) — 0.7 5 A VSS VPIN VDD D063 OSC1 — 0.1 5 A VSS VPIN VDD, XT, HS and LP oscillator configuration D070* IPUR GPIO Weak Pull-up Current(5) 50 250 400 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C VOH Output High Voltage VDD – 0.7 — — V IOH = -2.5mA, VDD = 4.5V, -40°C to +125°C D090 I/O ports(2) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: This specification applies to GP3/MCLR configured as GP3 with the internal weak pull-up disabled. 5: This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. 6: Applies to PIC12F617 only. 2010 Microchip Technology Inc. DS41302D-page 153 PIC12F609/615/617/12HV609/615 D101* COSC2 Capacitive Loading Specs on Output Pins OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C TA +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C TA +125°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Bulk Erase/Write 4.5 — 5.5 V D132A VPEW VDD for Row Erase/Write(6) VMIN — 5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated 16.8 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) (Continued) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: This specification applies to GP3/MCLR configured as GP3 with the internal weak pull-up disabled. 5: This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. 6: Applies to PIC12F617 only. PIC12F609/615/617/12HV609/615 DS41302D-page 154 2010 Microchip Technology Inc. 16.9 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym Characteristic Typ Units Conditions TH01 JA Thermal Resistance Junction to Ambient 84.6* C/W 8-pin PDIP package 149.5* C/W 8-pin SOIC package 211* C/W 8-pin MSOP package 60* C/W 8-pin DFN 3x3mm package 44* C/W 8-pin DFN 4x4mm package TH02 JC Thermal Resistance Junction to Case 41.2* C/W 8-pin PDIP package 39.9* C/W 8-pin SOIC package 39* C/W 8-pin MSOP package 9* C/W 8-pin DFN 3x3mm package 3.0* C/W 8-pin DFN 4x4mm package TH03 TDIE Die Temperature 150* C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD (NOTE 1) TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TDIE - TA)/JA (NOTE 2) * These parameters are characterized but not tested. Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient temperature. 2010 Microchip Technology Inc. DS41302D-page 155 PIC12F609/615/617/12HV609/615 16.10 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: FIGURE 16-3: LOAD CONDITIONS 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O Port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance VSS CL Legend: CL=50 pF for all pins 15 pF for OSC2 output Load Condition Pin PIC12F609/615/617/12HV609/615 DS41302D-page 156 2010 Microchip Technology Inc. 16.11 AC Characteristics: PIC12F609/615/617/12HV609/615 (Industrial, Extended) FIGURE 16-4: CLOCK TIMING TABLE 16-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode DC — 4 MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator mode 250 — ns XT Oscillator mode 50 — ns HS Oscillator mode 50 — ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TOSH, TOSL External CLKIN High, External CLKIN Low 2 — — s LP oscillator 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TOSR, TOSF External CLKIN Rise, External CLKIN Fall 0 — ns LP oscillator 0 — ns XT oscillator 0 — ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. OSC1/CLKIN OSC2/CLKOUT Q4 Q1 Q2 Q3 Q4 Q1 OS02 OS03 OS04 OS04 OSC2/CLKOUT (LP,XT,HS Modes) (CLKOUT Mode) 2010 Microchip Technology Inc. DS41302D-page 157 PIC12F609/615/617/12HV609/615 TABLE 16-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic Freq. Tolerance Min Typ† Max Units Conditions OS06 TWARM Internal Oscillator Switch when running(3) — — — 2 TOSC Slowest clock OS07 INTOSC Internal Calibrated INTOSC Frequency(2) (4MHz) 1% 3.96 4.0 4.04 MHz VDD = 3.5V, TA = 25°C 2% 3.92 4.0 4.08 MHz 2.5V VDD 5.5V, 0°C TA +85°C 5% 3.80 4.0 4.2 MHz 2.0V VDD 5.5V, -40°C TA +85°C (Ind.), -40°C TA +125°C (Ext.) OS08 INTOSC Internal Calibrated INTOSC Frequency(2) (8MHz) 1% 7.92 8.0 8.08 MHz VDD = 3.5V, TA = 25°C 2% 7.84 8.0 8.16 MHz 2.5V VDD 5.5V, 0°C TA +85°C 5% 7.60 8.0 8.40 MHz 2.0V VDD 5.5V, -40°C TA +85°C (Ind.), -40°C TA +125°C (Ext.) OS10* TIOSC ST INTOSC Oscillator Wakeup from Sleep Start-up Time — 5.5 12 24 s VDD = 2.0V, -40°C to +85°C — 3.5 7 14 s VDD = 3.0V, -40°C to +85°C — 3 6 11 s VDD = 5.0V, -40°C to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design. PIC12F609/615/617/12HV609/615 DS41302D-page 158 2010 Microchip Technology Inc. FIGURE 16-5: CLKOUT AND I/O TIMING FOSC CLKOUT I/O pin (Input) I/O pin (Output) Q4 Q1 Q2 Q3 OS11 OS19 OS13 OS15 OS18, OS19 OS20 OS21 OS17 OS16 OS14 OS12 OS18 Old Value New Value Cycle Write Fetch Read Execute TABLE 16-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions OS11 TOSH2CKL FOSC to CLKOUT (1) — — 70 ns VDD = 5.0V OS12 TOSH2CKH FOSC to CLKOUT (1) — — 72 ns VDD = 5.0V OS13 TCKL2IOV CLKOUT to Port out valid(1) — — 20 ns OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15 TOSH2IOV FOSC (Q1 cycle) to Port out valid — 50 70* ns VDD = 5.0V OS16 TOSH2IOI FOSC (Q2 cycle) to Port input invalid (I/O in hold time) 50 — — ns VDD = 5.0V OS17 TIOV2OSH Port input valid to FOSC(Q2 cycle) (I/O in setup time) 20 — — ns OS18 TIOR Port output rise time(2) —— 15 40 72 32 ns VDD = 2.0V VDD = 5.0V OS19 TIOF Port output fall time(2) —— 28 15 55 30 ns VDD = 2.0V VDD = 5.0V OS20* TINP INT pin input high or low time 25 — — ns OS21* TRAP GPIO interrupt-on-change new input level time TCY — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. 2010 Microchip Technology Inc. DS41302D-page 159 PIC12F609/615/617/12HV609/615 FIGURE 16-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING FIGURE 16-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD MCLR Internal POR PWRT Time-out OSC Start-Up Time Internal Reset(1) Watchdog Timer 33 32 30 31 34 I/O pins 34 Note 1: Asserted low. Reset(1) VBOR VDD (Device in Brown-out Reset) (Device not in Brown-out Reset) 33* 37 * 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. Reset (due to BOR) VBOR + VHYST PIC12F609/615/617/12HV609/615 DS41302D-page 160 2010 Microchip Technology Inc. TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 —— —— s s VDD = 5V, -40°C to +85°C VDD = 5V, -40°C to +125°C 31* TWDT Watchdog Timer Time-out Period (No Prescaler) 10 10 20 20 30 35 ms ms VDD = 5V, -40°C to +85°C VDD = 5V, -40°C to +125°C 32 TOST Oscillation Start-up Timer Period(1, 2) — 1024 — TOSC (NOTE 3) 33* TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O High-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 s 35 VBOR Brown-out Reset Voltage 2.0 2.15 2.3 V (NOTE 4) 36* VHYST Brown-out Reset Hysteresis — 100 — mV 37* TBOR Brown-out Reset Minimum Detection Period 100 — — s VDD VBOR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2010 Microchip Technology Inc. DS41302D-page 161 PIC12F609/615/617/12HV609/615 FIGURE 16-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: 20 or TCY + 40 N — — ns N = prescale value (2, 4, ..., 256) 45* TT1H T1CKI High Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 46* TT1L T1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Period Synchronous Greater of: 30 or TCY + 40 N — — ns N = prescale value (1, 2, 4, 8) Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) — 32.768 — kHz 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment 2 TOSC — 7 TOSC — Timers in Sync mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. T0CKI T1CKI 40 41 42 45 46 47 49 TMR0 or TMR1 PIC12F609/615/617/12HV609/615 DS41302D-page 162 2010 Microchip Technology Inc. FIGURE 16-9: PIC12F615/617/HV615 CAPTURE/COMPARE/PWM TIMINGS (ECCP) TABLE 16-6: PIC12F615/617/HV615 CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) TABLE 16-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP1 Input Period 3TCY + 40 N — — ns N = prescale value (1, 4 or 16) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristics Min Typ† Max Units Comments CM01 VOS Input Offset Voltage(2) — 5.0 10 mV CM02 VCM Input Common Mode Voltage 0 — VDD – 1.5 V CM03* CMRR Common Mode Rejection Ratio +55 — — dB CM04* TRT Response Time(1) Falling — 150 600 ns Rising — 200 1000 ns CM05* TMC2COV Comparator Mode Change to Output Valid — — 10 s CM06* VHYS Input Hysteresis Voltage — 45 60 mV * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20mV. The other input is at (VDD -1.5)/2. 2: Input offset voltage is measured with one comparator input at (VDD - 1.5V)/2. Note: Refer to Figure 16-3 for load conditions. (Capture mode) CC01 CC02 CC03 CCP1 2010 Microchip Technology Inc. DS41302D-page 163 PIC12F609/615/617/12HV609/615 TABLE 16-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS TABLE 16-9: VOLTAGE REFERENCE SPECIFICATIONS TABLE 16-10: SHUNT REGULATOR SPECIFICATIONS (PIC12HV609/615 only) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym Characteristics Min Typ† Max Units Comments CV01* CLSB Step Size(2) —— VDD/24 VDD/32 —— VV Low Range (VRR = 1) High Range (VRR = 0) CV02* CACC Absolute Accuracy(3) —— —— 1/2 1/2 LSb LSb Low Range (VRR = 1) High Range (VRR = 0) CV03* CR Unit Resistor Value (R) — 2k — CV04* CST Settling Time(1) — — 10 s * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section 9.10 “Comparator Voltage Reference” for more information. 3: Absolute Accuracy when CVREF output is (VDD -1.5). VR Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Symbol Characteristics Min Typ Max Units Comments VR01 VP6OUT VP6 voltage output 0.5 0.6 0.7 V VR02 V1P2OUT V1P2 voltage output 1.05 1.20 1.35 V VR03* TSTABLE Settling Time — 10 — s * These parameters are characterized but not tested. SHUNT REGULATOR CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Symbol Characteristics Min Typ Max Units Comments SR01 VSHUNT Shunt Voltage 4.75 5 5.4 V SR02 ISHUNT Shunt Current 4 — 50 mA SR03* TSETTLE Settling Time — — 150 ns To 1% of final value SR04 CLOAD Load Capacitance 0.01 — 10 F Bypass capacitor on VDD pin SR05 ISNT Regulator operating current — 180 — A Includes band gap reference current * These parameters are characterized but not tested. PIC12F609/615/617/12HV609/615 DS41302D-page 164 2010 Microchip Technology Inc. TABLE 16-11: PIC12F615/617/HV615 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions AD01 NR Resolution — — 10 bits bit AD02 EIL Integral Error — — 1 LSb VREF = 5.12V(5) AD03 EDL Differential Error — — 1 LSb No missing codes to 10 bits VREF = 5.12V(5) AD04 EOFF Offset Error — +1.5 +2.0 LSb VREF = 5.12V(5) AD07 EGN Gain Error — — 1 LSb VREF = 5.12V(5) AD06 AD06A VREF Reference Voltage(3) 2.2 2.5 — — VDD V Absolute minimum to ensure 1 LSb accuracy AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of Analog Voltage Source — — 10 k AD09* IREF VREF Input Current(3) 10 — 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN. — — 50 A During A/D conversion cycle. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. 5: VREF = 5V for PIC12HV615. 2010 Microchip Technology Inc. DS41302D-page 165 PIC12F609/615/617/12HV609/615 TABLE 16-12: PIC12F615/617/HV615 A/D CONVERSION REQUIREMENTS FIGURE 16-10: PIC12F615/617/HV615 A/D CONVERSION TIMING (NORMAL MODE) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions AD130* TAD A/D Clock Period 1.6 — 9.0 s TOSC-based, VREF 3.0V 3.0 — 9.0 s TOSC-based, VREF full range(3) A/D Internal RC Oscillator Period 3.0 6.0 9.0 s ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.6 4.0 6.0 s At VDD = 5.0V AD131 TCNV Conversion Time (not including Acquisition Time)(1) — 11 — TAD Set GO/DONE bit to new data in A/D Result register AD132* TACQ Acquisition Time 11.5 — s AD133* TAMP Amplifier Settling Time — — 5 s AD134 TGO Q4 to A/D Clock Start — — TOSC/2 TOSC/2 + TCY — — — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section 10.3 “A/D Acquisition Requirements” for minimum conditions. 3: Full range for PIC12HV609/HV615 powered by the shunt regulator is the 5V regulated voltage. AD131 AD130 BSF ADCON0, GO Q4 A/D CLK A/D Data ADRES ADIF GO Sample OLD_DATA Sampling Stopped DONE NEW_DATA 9 8 7 3 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1 TCY 6 AD134 (TOSC/2(1)) 1 TCY AD132 PIC12F609/615/617/12HV609/615 DS41302D-page 166 2010 Microchip Technology Inc. FIGURE 16-11: PIC12F615/617/HV615 A/D CONVERSION TIMING (SLEEP MODE) AD132 AD131 AD130 BSF ADCON0, GO Q4 A/D CLK A/D Data ADRES ADIF GO Sample OLD_DATA Sampling Stopped DONE NEW_DATA 9 7 3 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. AD134 8 6 (TOSC/2 + TCY(1)) 1 TCY 1 TCY 2010 Microchip Technology Inc. DS41302D-page 167 PIC12F609/615/617/12HV609/615 16.12 High Temperature Operation This section outlines the specifications for the PIC12F615 device operating in a temperature range between -40°C and 150°C.(4) The specifications between -40°C and 150°C(4) are identical to those shown in DS41288 and DS80329. TABLE 16-13: ABSOLUTE MAXIMUM RATINGS Note 1: Writes are not allowed for Flash Program Memory above 125°C. 2: All AC timing specifications are increased by 30%. This derating factor will include parameters such as TPWRT. 3: The temperature range indicator in the part number is “H” for -40°C to 150°C.(4) Example: PIC12F615T-H/ST indicates the device is shipped in a TAPE and reel configuration, in the MSOP package, and is rated for operation from -40°C to 150°C.(4) 4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. Parameter Source/Sink Value Units Max. Current: VDD Source 20 mA Max. Current: VSS Sink 50 mA Max. Current: PIN Source 5 mA Max. Current: PIN Sink 10 mA Pin Current: at VOH Source 3 mA Pin Current: at VOL Sink 8.5 mA Port Current: GPIO Source 20 mA Port Current: GPIO Sink 50 mA Maximum Junction Temperature 155 °C Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. PIC12F609/615/617/12HV609/615 DS41302D-page 168 2010 Microchip Technology Inc. TABLE 16-14: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC12F615-H (High Temp.) Param No. Device Characteristics Units Min Typ Max Condition VDD Note D010 Supply Current (IDD) A — 13 58 2.0 — 19 67 3.0 IDD LP OSC (32 kHz) — 32 92 5.0 D011 A — 135 316 2.0 — 185 400 3.0 IDD XT OSC (1 MHz) — 300 537 5.0 D012 A — 240 495 2.0 — 360 680 3.0 IDD XT OSC (4 MHz) mA — 0.660 1.20 5.0 D013 A — 75 158 2.0 — 155 338 3.0 IDD EC OSC (1 MHz) — 345 792 5.0 D014 A — 185 357 2.0 — 325 625 3.0 IDD EC OSC (4 MHz) mA — 0.665 1.30 5.0 D016 A — 245 476 2.0 — 360 672 3.0 IDD INTOSC (4 MHz) — 620 1.10 5.0 D017 A — 395 757 2.0 mA — 0.620 1.20 3.0 IDD INTOSC (8 MHz) — 1.20 2.20 5.0 D018 A — 175 332 2.0 — 285 518 3.0 IDD EXTRC (4 MHz) — 530 972 5.0 D019 mA — 2.20 4.10 4.5 IDD HS OSC (20 MHz) — 2.80 4.80 5.0 2010 Microchip Technology Inc. DS41302D-page 169 PIC12F609/615/617/12HV609/615 TABLE 16-15: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC12F615-H (High Temp.) TABLE 16-16: WATCHDOG TIMER SPECIFICATIONS FOR PIC12F615-H (High Temp.) TABLE 16-17: LEAKAGE CURRENT SPECIFICATIONS FOR PIC12F615-H (High Temp.) Param No. Device Characteristics Units Min Typ Max Condition VDD Note D020E Power Down Base Current A — 0.05 12 2.0 — 0.15 13 3.0 IPD Base — 0.35 14 5.0 D021E A — 0.5 20 2.0 — 2.5 25 3.0 WDT Current — 9.5 36 5.0 D022E A — 5.0 28 3.0 BOR Current — 6.0 36 5.0 D023E A — 105 195 2.0 IPD Current (Both Comparators Enabled) — 110 210 3.0 — 116 220 5.0 A — 50 105 2.0 IPD Current (One Comparator — 55 110 3.0 Enabled) — 60 125 5.0 D024E A — 30 58 2.0 — 45 85 3.0 IPD (CVREF, High Range) — 75 142 5.0 D025E A — 39 76 2.0 — 59 114 3.0 IPD (CVREF, Low Range) — 98 190 5.0 D026E A — 5.5 30 2.0 — 7.0 35 3.0 IPD (T1 OSC, 32 kHz) — 8.5 45 5.0 D027E A — 0.2 12 3.0 IPD (A2D on, not converting) — 0.3 15 5.0 Param No. Sym Characteristic Units Min Typ Max Conditions 31 TWDT Watchdog Timer Time-out Period (No Prescaler) ms 6 20 70 150°C Temperature Param No. Sym Characteristic Units Min Typ Max Conditions D061 IIL Input Leakage Current(1) (GP3/RA3/MCLR) μA — ±0.5 ±5.0 VSS VPIN VDD D062 IIL Input Leakage Current(2) (GP3/RA3/MCLR) μA 50 250 400 VDD = 5.0V Note 1: This specification applies when GP3/RA3/MCLR is configured as an input with the pull-up disabled. The leakage current for the GP3/RA3/MCLR pin is higher than for the standard I/O port pins. 2: This specification applies when GP3/RA3/MCLR is configured as the MCLR reset pin function with the weak pull-up enabled. PIC12F609/615/617/12HV609/615 DS41302D-page 170 2010 Microchip Technology Inc. TABLE 16-18: OSCILLATOR PARAMETERS FOR PIC12F615-H (High Temp.) TABLE 16-19: COMPARATOR SPECIFICATIONS FOR PIC12F615-H (High Temp.) Param No. Sym Characteristic Frequency Tolerance Units Min Typ Max Conditions OS08 INTOSC Int. Calibrated INTOSC Freq.(1) ±10% MHz 7.2 8.0 8.8 2.0V VDD 5.5V -40°C TA 150°C Note 1: To ensure these oscillator frequency tolerances, Vdd and Vss must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. Param No. Sym Characteristic Units Min Typ Max Conditions CM01 VOS Input Offset Voltage mV — ±5 ±20 (VDD - 1.5)/2 2010 Microchip Technology Inc. DS41302D-page 171 PIC12F609/615/617/12HV609/615 17.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean - 3) respectively, where s is a standard deviation, over each temperature range. FIGURE 17-1: PIC12F609/615/617 IDD LP (32 kHz) vs. VDD FIGURE 17-2: PIC12F609/615/617 IDD EC (1 MHz) vs. VDD Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0 10 20 30 40 50 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) IDD LP (μA) Maximum VDD (V) Typical 1 2 3 4 5 6 0 100 200 300 400 500 600 1 2 3 4 5 6 Typical Maximum VDD (V) IDD EC (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) PIC12F609/615/617/12HV609/615 DS41302D-page 172 2010 Microchip Technology Inc. FIGURE 17-3: PIC12F609/615/617 IDD EC (4 MHz) vs. VDD FIGURE 17-4: PIC12F609/615/617 IDD XT (1 MHz) vs. VDD FIGURE 17-5: PIC12F609/615/617 IDD XT (4 MHz) vs. VDD 0 200 400 600 800 1000 1200 Typical VDD (V) IDD EC (μA) Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1 2 3 4 5 6 0 200 400 600 800 1000 1200 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1 2 3 4 5 6 Typical Maximum VDD (V) IDD XT (μA) 0 200 400 600 800 1000 1200 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1 2 3 4 5 6 Typical Maximum VDD (V) IDD XT ( μA) 2010 Microchip Technology Inc. DS41302D-page 173 PIC12F609/615/617/12HV609/615 FIGURE 17-6: PIC12F609/615/617 IDD INTOSC (4 MHz) vs. VDD FIGURE 17-7: PIC12F609/615/617 IDD INTOSC (8 MHz) vs. VDD 0 100 200 300 400 500 600 700 800 900 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1 2 3 4 5 6 Typical Maximum VDD (V) IDD INTOSC (μA) 0 200 400 600 800 1000 1200 1400 1600 1800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1 2 3 4 5 6 Typical Maximum VDD (V) IDD INTOSC (μA) PIC12F609/615/617/12HV609/615 DS41302D-page 174 2010 Microchip Technology Inc. FIGURE 17-8: PIC12F609/615617 IDD EXTRC (4 MHz) vs. VDD FIGURE 17-9: PIC12F609/615/617 IDD HS (20 MHz) vs. VDD 0 100 200 300 400 500 600 700 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1 2 3 4 5 6 Typical Maximum VDD (V) IDD EXTRC (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 1 2 3 4 VDD (V) IDD HS (mA) 4 5 6 Maximum Typical 2010 Microchip Technology Inc. DS41302D-page 175 PIC12F609/615/617/12HV609/615 FIGURE 17-10: PIC12F609/615/617 IPD BASE vs. VDD FIGURE 17-11: PIC12F609/615/617 IPD COMPARATOR (SINGLE ON) vs. VDD 0 1 2 3 4 5 6 7 8 9 IPD BASE (μA) Typical: Statistical Mean @25°C Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1 2 3 4 5 6 Industrial Typical Extended VDD (V) Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) 30 40 50 60 70 80 90 VDD (V) IPD CMP (μA) 1 2 3 4 5 6 Industrial Typical Extended Typical: Statistical Mean @25°C Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) PIC12F609/615/617/12HV609/615 DS41302D-page 176 2010 Microchip Technology Inc. FIGURE 17-12: PIC12F609/615/617 IPD WDT vs. VDD FIGURE 17-13: PIC12F609/615/617 IPD BOR vs. VDD 0 2 4 6 8 10 12 14 16 18 20 VDD (V) IPD WDT (μA) 1 2 3 4 5 6 Industrial Typical Extended Typical: Statistical Mean @25°C Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) 0 2 4 6 8 10 12 14 16 18 20 VDD (V) IPD BOR (μA) 1 2 3 4 5 6 Industrial Typical Typical: Statistical Mean @25°C Extended Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) 2010 Microchip Technology Inc. DS41302D-page 177 PIC12F609/615/617/12HV609/615 FIGURE 17-14: PIC12F609/615/617 IPD CVREF (LOW RANGE) vs. VDD FIGURE 17-15: PIC12F609/615/617 IPD CVREF (HI RANGE) vs. VDD 0 20 40 60 80 100 120 140 VDD (V) IPD CVREF (μA) 1 2 3 4 5 6 Maximum Typical Typical: Statistical Mean @25°C Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) 0 20 40 60 80 100 120 1 3 5 VDD (V) IPD CVREF (μA) 2 4 6 Maximum Typical Typical: Statistical Mean @25°C Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) PIC12F609/615/617/12HV609/615 DS41302D-page 178 2010 Microchip Technology Inc. FIGURE 17-16: PIC12F609/615/617 IPD T1OSC vs. VDD FIGURE 17-17: PIC12F615/617 IPD A/D vs. VDD 0 5 10 15 20 25 VDD (V) IPD T1OSC (μA) Industrial Typical Extended 1 2 3 4 5 6 Typical: Statistical Mean @25°C Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) 0 2 4 6 8 10 12 14 VDD (V) IPD A2D (μA) Industrial Typical Extended 1 2 3 4 5 6 Typical: Statistical Mean @25°C Extended: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Industrial: Mean (Worst-Case Temp) + 3 (-40°C to 85°C) 2010 Microchip Technology Inc. DS41302D-page 179 PIC12F609/615/617/12HV609/615 FIGURE 17-18: PIC12HV609/615 IDD LP (32 kHz) vs. VDD FIGURE 17-19: PIC12HV609/615 IDD EC (1 MHz) vs. VDD FIGURE 17-20: PIC12HV609/615 IDD EC (4 MHz) vs. VDD 0 50 100 150 200 250 300 350 400 450 VDD (V) IDD LP (μA) 1 2 3 4 5 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 100 200 300 400 500 600 700 800 900 1000 VDD (V) IDD EC (μA) 1 2 3 4 5 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 200 400 600 800 1000 1200 1400 VDD (V) IDD EC (μA) 5 1 3 4 2 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) PIC12F609/615/617/12HV609/615 DS41302D-page 180 2010 Microchip Technology Inc. FIGURE 17-21: PIC12HV609/615 IDD XT (1 MHz) vs. VDD FIGURE 17-22: PIC12HV609/615 IDD XT (4 MHz) vs. VDD FIGURE 17-23: PIC12HV609/615 IDD INTOSC (4 MHz) vs. VDD 0 100 200 300 400 500 600 700 800 900 VDD (V) IDD XT (μA) 1 2 3 4 5 Typical Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 200 400 600 800 1000 1200 1400 VDD (V) IDD XT (μA) 1 2 3 4 5 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 200 400 600 800 1000 1200 VDD (V) IDD INTOSC ( μA) 1 2 3 4 5 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 2010 Microchip Technology Inc. DS41302D-page 181 PIC12F609/615/617/12HV609/615 FIGURE 17-24: PIC12HV609/615 IDD INTOSC (8 MHz) vs. VDD FIGURE 17-25: PIC12HV609/615 IDD EXTRC (4 MHz) vs. VDD FIGURE 17-26: PIC12HV609/615 IPD BASE vs. VDD 0 500 1000 1500 2000 VDD (V) IDD INTOSC (μA) 1 2 3 4 5 Typical Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 200 400 600 800 1000 1200 VDD (V) IDD EXTRC (μA) 1 2 3 4 5 Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typical 0 50 100 150 200 250 300 350 400 VDD (V) IPD BASE (μA) 1 2 3 4 5 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) PIC12F609/615/617/12HV609/615 DS41302D-page 182 2010 Microchip Technology Inc. FIGURE 17-27: PIC12HV609/615 IPD COMPARATOR (SINGLE ON) vs. VDD FIGURE 17-28: PIC12HV609/615 IPD WDT vs. VDD FIGURE 17-29: PIC12HV609/615 IPD BOR vs. VDD 0 100 200 300 400 500 VDD (V) IPD CMP (μA) 1 2 3 4 5 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 50 100 150 200 250 300 350 400 VDD (V) IPD WDT (μA) 1 2 3 4 5 Typical Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 100 150 200 250 300 350 400 VDD (V) IPD BOR (μA) 2 3 4 5 Typical Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 2010 Microchip Technology Inc. DS41302D-page 183 PIC12F609/615/617/12HV609/615 FIGURE 17-30: PIC12HV609/615 IPD CVREF (LOW RANGE) vs. VDD FIGURE 17-31: PIC12HV609/615 IPD CVREF (HI RANGE) vs. VDD FIGURE 17-32: PIC12HV609/615 IPD T1OSC vs. VDD 0 100 200 300 400 500 VDD (V) IPD CVREF (μA) 1 2 3 4 5 Typical Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) VDD (V) IPD CVREF (μA) 0 100 200 300 400 500 1 2 3 4 5 Typical Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 50 100 150 200 250 300 350 400 VDD (V) IPD T1OSC (μA) 1 2 3 4 5 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) PIC12F609/615/617/12HV609/615 DS41302D-page 184 2010 Microchip Technology Inc. FIGURE 17-33: PIC12HV615 IPD A/D vs. VDD FIGURE 17-34: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) 0 50 100 150 200 250 300 350 400 VDD (V) IPD A2D (μA) 2 3 4 5 Typical Maximum Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) VOL (V) Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C Min. -40°C Max. 85°C Typical 25°C 2010 Microchip Technology Inc. DS41302D-page 185 PIC12F609/615/617/12HV609/615 FIGURE 17-35: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) FIGURE 17-36: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) VOL (V) Max. 85°C Typ. 25°C Min. -40°C Max. 125°C 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) VOH (V) Typ. 25°C Max. -40°C Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) PIC12F609/615/617/12HV609/615 DS41302D-page 186 2010 Microchip Technology Inc. FIGURE 17-37: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) FIGURE 17-38: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.0 3.5 4.0 4.5 5.0 5.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) VOH (V) Max. -40°C Typ. 25°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Min. 125°C 0.5 0.7 0.9 1.1 1.3 1.5 1.7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) VIN (V) Typ. 25°C Max. -40°C Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 2010 Microchip Technology Inc. DS41302D-page 187 PIC12F609/615/617/12HV609/615 FIGURE 17-39: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE FIGURE 17-40: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) VIN (V) VIH Max. 125°C VIH Min. -40°C VIL Min. 125°C VIL Max. -40°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 2 4 6 8 10 12 14 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Time (μs) 85°C 25°C -40°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) PIC12F609/615/617/12HV609/615 DS41302D-page 188 2010 Microchip Technology Inc. FIGURE 17-41: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE FIGURE 17-42: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 0 5 10 15 20 25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Time (μs) -40°C 85°C 25°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Time (s) -40°C 25°C 85°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 2010 Microchip Technology Inc. DS41302D-page 189 PIC12F609/615/617/12HV609/615 FIGURE 17-43: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) FIGURE 17-44: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (85°C) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Change from Calibration (%) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Change from Calibration (%) PIC12F609/615/617/12HV609/615 DS41302D-page 190 2010 Microchip Technology Inc. FIGURE 17-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) FIGURE 17-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Change from Calibration (%) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Change from Calibration (%) 2010 Microchip Technology Inc. DS41302D-page 191 PIC12F609/615/617/12HV609/615 FIGURE 17-47: 0.6V REFERENCE VOLTAGE vs. TEMP (TYPICAL) FIGURE 17-48: 1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL) FIGURE 17-49: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 0.56 0.57 0.58 0.59 0.6 0.61 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) Reference Voltage (V) 2.5V 4V 5V 5.5V 3V 1.2 1.21 1.22 1.23 1.24 1.25 1.26 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) Reference Voltage (V) 2.5V 3V 4V 5V 5.5V 4.96 4.98 5 5.02 5.04 5.06 5.08 5.1 5.12 5.14 5.16 0 10 20 30 40 50 60 Input Current (mA) Shunt Regulator Voltage (V) 25°C 85°C 125°C -40°C PIC12F609/615/617/12HV609/615 DS41302D-page 192 2010 Microchip Technology Inc. FIGURE 17-50: SHUNT REGULATOR VOLTAGE vs. TEMP (TYPICAL) FIGURE 17-51: COMPARATOR RESPONSE TIME (RISING EDGE) 4.96 4.98 5 5.02 5.04 5.06 5.08 5.1 5.12 5.14 5.16 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) Shunt Regulator Voltage (V) 50 mA 40 mA 20 mA 15 mA 10 mA 4 mA 0 100 200 300 400 500 600 700 800 900 1000 2.0 2.5 4.0 5.5 VDD (V) Response Time (nS) Note: V- input = Transition from VCM + 100mV to VCM - 20mV V+ input = VCM VCM = (VDD - 1.5V)/2 Min. -40°C Typ. 25°C Max. 85°C Max. 125°C 2010 Microchip Technology Inc. DS41302D-page 193 PIC12F609/615/617/12HV609/615 FIGURE 17-52: COMPARATOR RESPONSE TIME (FALLING EDGE) FIGURE 17-53: WDT TIME-OUT PERIOD vs. VDD OVER TEMPERATURE 0 100 200 300 400 500 600 700 800 900 1000 2.0 2.5 4.0 5.5 VDD (V) Response Time (nS) Max. 85°C Typ. 25°C Min. -40°C Max. 125°C Note: V- input = Transition from VCM - 100mV to VCM + 20MV V+ input = VCM VCM = (VDD - 1.5V)/2 5 10 15 20 25 30 35 40 45 50 55 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) Time (ms) -40°C 25°C 85°C 125°C PIC12F609/615/617/12HV609/615 DS41302D-page 194 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 195 PIC12F609/615/617/12HV609/615 18.0 PACKAGING INFORMATION 18.1 Package Marking Information * Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e3 e3 XXXXXNNN 8-Lead PDIP (.300”) XXXXXXXX YYWW 017 Example XXFXXX/P 0610 8-Lead SOIC (.150”) XXXXXXXX XXXXYYWW NNN Example PICXXCXX /SN0610 017 XXXXXX 8-Lead DFN (4x4 mm) (for PIC12F609/615/HV609/615 YYWW NNN Example XXXXXX XXXXXX 0610 017 XXXX e3 e3 e3 8-Lead MSOP XXXXXX YWWNNN Example 602/MS 610017 XXXX 8-Lead DFN (3x3 mm) YYWW NNN Example 0610 017 XXXX devices only) PIC12F609/615/617/12HV609/615 DS41302D-page 196 2010 Microchip Technology Inc. 18.2 Package Details The following sections give the technical details of the packages. !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# / !# '! #& .0 1,21 !'! & $ & "! **& "&& ! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 7,8. '! 9'&! 7 7: ; 7"') % ! 7 < & 1, & & = = ## 4 4!! - 1 !& & = = "# & "# >#& . - - ## 4 >#& . < : 9& -< -? & & 9 - 9 # 4!! < 6 9 #>#& ) ? 9 * 9 #>#& ) < : * + 1 = = - N E1 NOTE 1 D 1 2 3 A A1 A2 L b1 b e E eB c * , <1 2010 Microchip Technology Inc. DS41302D-page 197 PIC12F609/615/617/12HV609/615 ! ""#$%& !' !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99.. '! 9'&! 7 7: ; 7"') % ! 7 < & 1, : 8 & = = ## 4 4!! = = & # %%+ = : >#& . ?1, ## 4 >#& . -1, : 9& 1, , '% @ & A = 3 &9& 9 = 3 & & 9 .3 3 & B = #& ) - = # %& B = B # %&1 && ' B = B D N e E E1 NOTE 1 1 2 3 b A A1 A2 L L1 c h h φ β α * , 1 PIC12F609/615/617/12HV609/615 DS41302D-page 198 2010 Microchip Technology Inc. ! ""#$%& !' 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 2010 Microchip Technology Inc. DS41302D-page 199 PIC12F609/615/617/12HV609/615 (" ! )*( ( ! !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99.. '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & = = ## 4 4!! < & # %% = : >#& . 1, ## 4 >#& . -1, : 9& -1, 3 &9& 9 ? < 3 & & 9 .3 3 & B = #& ) = D N E E1 NOTE 1 1 2 e b A A1 A2 c L1 L φ * , 1 PIC12F609/615/617/12HV609/615 DS41302D-page 200 2010 Microchip Technology Inc. + $ )*(+,,%& + !" #$% &" ' ()"&'"!&) &#*& & & # 4 ' ' $ !#&) ! &#! - 4 !! *!" &# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99.. '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & < & # %% , & & 4!! - .3 : 9& -1, .$ !# #>#& . = ? : >#& . -1, .$ !# #9& = , & &>#& ) - - , & &9& 9 - , & && .$ !# # C = = TOP VIEW BOTTOM VIEW D N E NOTE 1 1 2 EXPOSED PAD b e N L E2 K NOTE 1 D2 2 1 NOTE 2 A A3 A1 * ,?1 2010 Microchip Technology Inc. DS41302D-page 201 PIC12F609/615/617/12HV609/615 + $ )*(-,-,%& + !" #$% &" ' ()"&'"!&) &#*& & & # 4 ' ' $ !#&) ! &#! - 4 !! *!" &# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99.. '! 9'&! 7 7: ; 7"') % ! 7 < & <1, : 8 & < & # %% , & & 4!! - .3 : 9& 1, .$ !# #>#& . < : >#& . 1, .$ !# #9& - -? , & &>#& ) - - , & &9& 9 - , & && .$ !# # C = = D N E NOTE 1 1 2 A3 A A1 NOTE 2 NOTE 1 D2 2 1 E2 L N e b K EXPOSED PAD TOP VIEW BOTTOM VIEW * , - PIC12F609/615/617/12HV609/615 DS41302D-page 202 2010 Microchip Technology Inc. + $ )*(D-,-,%& + 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 2010 Microchip Technology Inc. DS41302D-page 203 PIC12F609/615/617/12HV609/615 APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. Revision B (05/2008) Added Graphs. Revised 28-Pin ICD Pinout, Electrical Specifications Section, Package Details. Revision C (09/2009) Updated adding the PIC12F617 device throughout the entire data sheet; Added Figure 2-2 to Memory Organization section; Added section 3 ”FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY)”; Updated Register 12-1; Updated Table12-5 adding PMCON1, PMCON2, PMADRL, PMADRH, PMDATL, PMDATH; Added section 16-12 in the Electrical Specification section; Other minor edits. Revision D (01/2010) Updated Figure 17-50; Revised 16.8 DC Characteristics; Removed Preliminary Status. APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX Family of devices. B.1 PIC12F675 to PIC12F609/615/ 12HV609/615 TABLE B-1: FEATURE COMPARISON Feature PIC12F675 PIC12F609/ 615/ 12HV609/615 Max Operating Speed 20 MHz 20 MHz Max Program Memory (Words) 1024 1024 SRAM (bytes) 64 64 A/D Resolution 10-bit 10-bit (615 only) Timers (8/16-bit) 1/1 2/1 (615) 1/1 (609) Oscillator Modes 8 8 Brown-out Reset Y Y Internal Pull-ups RA0/1/2/4/5 GP0/1/2/4/5, MCLR Interrupt-on-change RA0/1/2/3/4/5 GP0/1/2/3/4/5 Comparator 1 1 ECCP N Y (615) INTOSC Frequencies 4 MHz 4/8 MHz Internal Shunt Regulator N Y (PIC12HV609/ 615) Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. PIC12F609/615/617/12HV609/615 DS41302D-page 204 2010 Microchip Technology Inc. NOTES: 2010 Microchip Technology Inc. DS41302D-page 205 PIC12F609/615/617/12HV609/615 INDEX A A/D Specifications.................................................... 164, 165 Absolute Maximum Ratings .............................................. 143 AC Characteristics Industrial and Extended ............................................ 156 Load Conditions ........................................................ 155 ADC Acquisition Requirements ........................................... 86 Associated registers.................................................... 88 Block Diagram............................................................. 79 Calculating Acquisition Time....................................... 86 Channel Selection....................................................... 80 Configuration............................................................... 80 Configuring Interrupt ................................................... 83 Conversion Clock........................................................ 80 Conversion Procedure ................................................ 83 Internal Sampling Switch (RSS) Impedance................ 86 Interrupts..................................................................... 81 Operation .................................................................... 82 Operation During Sleep .............................................. 82 Port Configuration....................................................... 80 Reference Voltage (VREF)........................................... 80 Result Formatting........................................................ 82 Source Impedance...................................................... 86 Special Event Trigger.................................................. 82 Starting an A/D Conversion ........................................ 82 ADC (PIC12F615/617/HV615 Only) ................................... 79 ADCON0 Register............................................................... 84 ADRESH Register (ADFM = 0) ........................................... 85 ADRESH Register (ADFM = 1) ........................................... 85 ADRESL Register (ADFM = 0)............................................ 85 ADRESL Register (ADFM = 1)............................................ 85 Analog Input Connection Considerations............................ 68 Analog-to-Digital Converter. See ADC ANSEL Register (PIC12F609/HV609) ................................ 45 ANSEL Register (PIC12F615/617/HV615) ......................... 45 APFCON Register............................................................... 24 Assembler MPASM Assembler................................................... 140 B Block Diagrams (CCP) Capture Mode Operation ................................. 90 ADC ............................................................................ 79 ADC Transfer Function ............................................... 87 Analog Input Model ............................................... 68, 87 Auto-Shutdown ......................................................... 101 CCP PWM................................................................... 94 Clock Source............................................................... 37 Comparator ................................................................. 67 Compare ..................................................................... 92 Crystal Operation........................................................ 39 External RC Mode....................................................... 40 GP0 and GP1 Pins...................................................... 47 GP2 Pins..................................................................... 48 GP3 Pin....................................................................... 49 GP4 Pin....................................................................... 50 GP5 Pin....................................................................... 51 In-Circuit Serial Programming Connections.............. 125 Interrupt Logic ........................................................... 119 MCLR Circuit............................................................. 111 On-Chip Reset Circuit ............................................... 110 PIC12F609/12HV609 ................................................... 7 PIC12F615/617/12HV615 ............................................ 8 PWM (Enhanced) ....................................................... 97 Resonator Operation .................................................. 39 Timer1 .................................................................. 57, 58 Timer2 ........................................................................ 65 TMR0/WDT Prescaler ................................................ 53 Watchdog Timer ....................................................... 122 Brown-out Reset (BOR).................................................... 112 Associated Registers................................................ 113 Specifications ........................................................... 160 Timing and Characteristics ....................................... 159 C C Compilers MPLAB C18.............................................................. 140 MPLAB C30.............................................................. 140 Calibration Bits.................................................................. 109 Capture Module. See Enhanced Capture/Compare/ PWM (ECCP) Capture/Compare/PWM (CCP) Associated registers w/ Capture................................. 91 Associated registers w/ Compare............................... 93 Associated registers w/ PWM................................... 105 Capture Mode............................................................. 90 CCP1 Pin Configuration ............................................. 90 Compare Mode........................................................... 92 CCP1 Pin Configuration ..................................... 92 Software Interrupt Mode............................... 90, 92 Special Event Trigger ......................................... 92 Timer1 Mode Selection................................. 90, 92 Prescaler .................................................................... 90 PWM Mode................................................................. 94 Duty Cycle .......................................................... 95 Effects of Reset .................................................. 96 Example PWM Frequencies and Resolutions, 20 MHZ.................................. 95 Example PWM Frequencies and Resolutions, 8 MHz .................................... 95 Operation in Sleep Mode.................................... 96 Setup for Operation ............................................ 96 System Clock Frequency Changes .................... 96 PWM Period ............................................................... 95 Setup for PWM Operation .......................................... 96 CCP1CON (Enhanced) Register ........................................ 89 Clock Sources External Modes........................................................... 38 EC ...................................................................... 38 HS ...................................................................... 39 LP....................................................................... 39 OST .................................................................... 38 RC ...................................................................... 40 XT....................................................................... 39 Internal Modes............................................................ 40 INTOSC.............................................................. 40 INTOSCIO.......................................................... 40 CMCON0 Register.............................................................. 72 CMCON1 Register.............................................................. 73 Code Examples A/D Conversion .......................................................... 83 Assigning Prescaler to Timer0.................................... 54 Assigning Prescaler to WDT....................................... 54 Changing Between Capture Prescalers ..................... 90 Indirect Addressing..................................................... 25 PIC12F609/615/617/12HV609/615 DS41302D-page 206 2010 Microchip Technology Inc. Initializing GPIO .......................................................... 43 Saving Status and W Registers in RAM ................... 121 Writing to Flash Program Memory ..............................34 Code Protection ................................................................ 124 Comparator ......................................................................... 67 Associated registers.................................................... 78 Control ........................................................................69 Gating Timer1 ............................................................. 73 Operation During Sleep .............................................. 71 Overview..................................................................... 67 Response Time........................................................... 69 Synchronizing COUT w/Timer1 .................................. 73 Comparator Hysteresis ....................................................... 77 Comparator Voltage Reference (CVREF) ............................74 Effects of a Reset........................................................ 71 Comparator Voltage Reference (CVREF) Response Time........................................................... 69 Comparator Voltage Reference (CVREF) Specifications............................................................ 163 Comparators C2OUT as T1 Gate .....................................................60 Effects of a Reset........................................................ 71 Specifications............................................................ 162 Compare Module. See Enhanced Capture/Compare/ PWM (ECCP) (PIC12F615/617/HV615 only) CONFIG Register.............................................................. 108 Configuration Bits.............................................................. 107 CPU Features ................................................................... 107 Customer Change Notification Service ............................. 209 Customer Notification Service........................................... 209 Customer Support ............................................................. 209 D Data EEPROM Memory Associated Registers .................................................. 35 Data Memory....................................................................... 11 DC and AC Characteristics Graphs and Tables ...................................................171 DC Characteristics Extended and Industrial ............................................ 152 Industrial and Extended ............................................ 145 Development Support ....................................................... 139 Device Overview ................................................................... 7 E ECCP. See Enhanced Capture/Compare/PWM ECCPAS Register ............................................................. 102 EEDAT Register.................................................................. 28 EEDATH Register ............................................................... 28 Effects of Reset PWM mode ................................................................. 96 Electrical Specifications .................................................... 143 Enhanced Capture/Compare/PWM (ECCP) Enhanced PWM Mode ................................................ 97 Auto-Restart...................................................... 103 Auto-shutdown.................................................. 101 Half-Bridge Application ....................................... 99 Half-Bridge Application Examples..................... 104 Half-Bridge Mode ................................................ 99 Output Relationships (Active-High and Active-Low) .................................................98 Output Relationships Diagram............................98 Programmable Dead Band Delay ..................... 104 Shoot-through Current ...................................... 104 Start-up Considerations .................................... 100 Specifications............................................................ 162 Timer Resources ........................................................ 89 Enhanced Capture/Compare/PWM (PIC12F615/617/HV615 Only).................................... 89 Errata .................................................................................... 6 F Firmware Instructions ....................................................... 129 Flash Program Memory Self Read/Self Write Control (For PIC12F617 only)..................................... 27 Fuses. See Configuration Bits G General Purpose Register File ........................................... 12 GPIO................................................................................... 43 Additional Pin Functions ............................................. 44 ANSEL Register ................................................. 44 Interrupt-on-Change ........................................... 44 Weak Pull-Ups.................................................... 44 Associated registers ................................................... 52 GP0 ............................................................................ 47 GP1 ............................................................................ 47 GP2 ............................................................................ 48 GP3 ............................................................................ 49 GP4 ............................................................................ 50 GP5 ............................................................................ 51 Pin Descriptions and Diagrams .................................. 47 Specifications ........................................................... 158 GPIO Register .................................................................... 43 H High Temperature Operation............................................ 167 I ID Locations...................................................................... 124 In-Circuit Debugger........................................................... 125 In-Circuit Serial Programming (ICSP)............................... 125 Indirect Addressing, INDF and FSR registers..................... 25 Instruction Format............................................................. 129 Instruction Set................................................................... 129 ADDLW..................................................................... 131 ADDWF..................................................................... 131 ANDLW..................................................................... 131 ANDWF..................................................................... 131 MOVF ....................................................................... 134 BCF .......................................................................... 131 BSF........................................................................... 131 BTFSC...................................................................... 131 BTFSS ...................................................................... 132 CALL......................................................................... 132 CLRF ........................................................................ 132 CLRW....................................................................... 132 CLRWDT .................................................................. 132 COMF ....................................................................... 132 DECF........................................................................ 132 DECFSZ ................................................................... 133 GOTO....................................................................... 133 INCF ......................................................................... 133 INCFSZ..................................................................... 133 IORLW...................................................................... 133 IORWF...................................................................... 133 MOVLW.................................................................... 134 MOVWF.................................................................... 134 NOP.......................................................................... 134 RETFIE..................................................................... 135 RETLW..................................................................... 135 RETURN................................................................... 135 2010 Microchip Technology Inc. DS41302D-page 207 PIC12F609/615/617/12HV609/615 RLF ........................................................................... 136 RRF........................................................................... 136 SLEEP ...................................................................... 136 SUBLW..................................................................... 136 SUBWF..................................................................... 137 SWAPF ..................................................................... 137 XORLW..................................................................... 137 XORWF..................................................................... 137 Summary Table......................................................... 130 INTCON Register................................................................ 20 Internal Oscillator Block INTOSC Specifications............................................ 157, 158 Internal Sampling Switch (RSS) Impedance........................ 86 Internet Address................................................................ 209 Interrupts........................................................................... 118 ADC ............................................................................ 83 Associated Registers ................................................ 120 Context Saving.......................................................... 121 GP2/INT.................................................................... 118 GPIO Interrupt-on-Change........................................ 119 Interrupt-on-Change.................................................... 44 Timer0....................................................................... 119 TMR1 .......................................................................... 60 INTOSC Specifications ............................................. 157, 158 IOC Register ....................................................................... 46 L Load Conditions ................................................................ 155 M MCLR................................................................................ 111 Internal ...................................................................... 111 Memory Organization.......................................................... 11 Data ............................................................................ 11 Program...................................................................... 11 Microchip Internet Web Site.............................................. 209 Migrating from other PICmicro Devices ............................ 203 MPLAB ASM30 Assembler, Linker, Librarian ................... 140 MPLAB ICD 2 In-Circuit Debugger ................................... 141 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 141 MPLAB Integrated Development Environment Software .. 139 MPLAB PM3 Device Programmer .................................... 141 MPLAB REAL ICE In-Circuit Emulator System................. 141 MPLINK Object Linker/MPLIB Object Librarian ................ 140 O OPCODE Field Descriptions............................................. 129 Operation During Code Protect........................................... 32 Operation During Write Protect ........................................... 32 Operational Amplifier (OPA) Module AC Specifications...................................................... 163 OPTION Register................................................................ 19 OPTION_REG Register ...................................................... 55 Oscillator Associated registers.............................................. 41, 63 Oscillator Module .......................................................... 27, 37 EC............................................................................... 37 HS............................................................................... 37 INTOSC ...................................................................... 37 INTOSCIO................................................................... 37 LP................................................................................ 37 RC............................................................................... 37 RCIO........................................................................... 37 XT ............................................................................... 37 Oscillator Parameters ....................................................... 157 Oscillator Specifications.................................................... 156 Oscillator Start-up Timer (OST) Specifications ........................................................... 160 OSCTUNE Register............................................................ 41 P P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/ PWM (ECCP) ............................................................. 97 Packaging......................................................................... 195 Marking..................................................................... 195 PDIP Details ............................................................. 196 PCL and PCLATH............................................................... 25 Stack........................................................................... 25 PCON Register ........................................................... 23, 113 PICSTART Plus Development Programmer..................... 142 PIE1 Register ..................................................................... 21 Pin Diagram PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)........... 4 PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN).... 5 Pinout Descriptions PIC12F609/12HV609 ................................................... 9 PIC12F615/617/12HV615 .......................................... 10 PIR1 Register ..................................................................... 22 PMADRH and PMADRL Registers ..................................... 27 PMCON1 and PMCON2 Registers..................................... 27 Power-Down Mode (Sleep)............................................... 123 Power-on Reset (POR)..................................................... 111 Power-up Timer (PWRT) .................................................. 111 Specifications ........................................................... 160 Precision Internal Oscillator Parameters .......................... 158 Prescaler Shared WDT/Timer0................................................... 54 Switching Prescaler Assignment ................................ 54 Program Memory................................................................ 11 Map and Stack............................................................ 11 Programming, Device Instructions.................................... 129 Protection Against Spurious Write...................................... 32 PWM Mode. See Enhanced Capture/Compare/PWM........ 97 PWM1CON Register......................................................... 105 R Reader Response............................................................. 210 Reading the Flash Program Memory.................................. 30 Read-Modify-Write Operations ......................................... 129 Registers ADCON0 (ADC Control 0) .......................................... 84 ADRESH (ADC Result High) with ADFM = 0) ............ 85 ADRESH (ADC Result High) with ADFM = 1) ............ 85 ADRESL (ADC Result Low) with ADFM = 0).............. 85 ADRESL (ADC Result Low) with ADFM = 1).............. 85 ANSEL (Analog Select) .............................................. 45 APFCON (Alternate Pin Function Register) ............... 24 CCP1CON (Enhanced CCP1 Control) ....................... 89 CMCON0 (Comparator Control 0) .............................. 72 CMCON1 (Comparator Control 1) .............................. 73 CONFIG (Configuration Word) ................................. 108 Data Memory Map (PIC12F609/HV609) .................... 12 Data Memory Map (PIC12F615/617/HV615) ............. 13 ECCPAS (Enhanced CCP Auto-shutdown Control) . 102 EEDAT (EEPROM Data) ............................................ 28 EEDATH (EEPROM Data) ......................................... 28 GPIO........................................................................... 43 INTCON (Interrupt Control) ........................................ 20 IOC (Interrupt-on-Change GPIO) ............................... 46 OPTION_REG (OPTION)........................................... 19 PIC12F609/615/617/12HV609/615 DS41302D-page 208 2010 Microchip Technology Inc. OPTION_REG (Option) .............................................. 55 OSCTUNE (Oscillator Tuning) .................................... 41 PCON (Power Control Register) ................................. 23 PCON (Power Control) ............................................. 113 PIE1 (Peripheral Interrupt Enable 1)........................... 21 PIR1 (Peripheral Interrupt Register 1) ........................ 22 PWM1CON (Enhanced PWM Control) ..................... 105 Reset Values (PIC12F609/HV609) ........................... 115 Reset Values (PIC12F615/617/HV615) .................... 116 Reset Values (special registers) ............................... 117 Special Function Registers ......................................... 12 Special Register Summary (PIC12F609/HV609).. 14, 16 Special Register Summary (PIC12F615/617/HV615) .............................. 15, 17 STATUS......................................................................18 T1CON........................................................................62 T2CON........................................................................66 TRISIO (Tri-State GPIO) ............................................. 44 VRCON (Voltage Reference Control) ......................... 76 WPU (Weak Pull-Up GPIO) ........................................ 46 Reset................................................................................. 110 Revision History ................................................................ 203 S Shoot-through Current ...................................................... 104 Sleep Power-Down Mode ...................................................123 Wake-up....................................................................123 Wake-up using Interrupts.......................................... 123 Software Simulator (MPLAB SIM)..................................... 140 Special Event Trigger.......................................................... 82 Special Function Registers .................................................12 STATUS Register................................................................ 18 T T1CON Register.................................................................. 62 T2CON Register.................................................................. 66 Thermal Considerations .................................................... 154 Time-out Sequence........................................................... 113 Timer0................................................................................. 53 Associated Registers .................................................. 55 External Clock............................................................. 54 Interrupt....................................................................... 55 Operation .............................................................. 53, 57 Specifications............................................................ 161 T0CKI ..........................................................................54 Timer1................................................................................. 57 Associated registers.................................................... 63 Asynchronous Counter Mode ..................................... 59 Reading and Writing ........................................... 59 Comparator Synchronization ...................................... 61 ECCP Special Event Trigger (PIC12F615/617/HV615 Only) ............................61 ECCP Time Base (PIC12F615/617/HV615 Only) .......60 Interrupt....................................................................... 60 Modes of Operation .................................................... 57 Operation During Sleep .............................................. 60 Oscillator ..................................................................... 59 Prescaler..................................................................... 59 Specifications............................................................ 161 Timer1 Gate Inverting Gate .....................................................60 Selecting Source........................................... 60, 73 Synchronizing COUT w/Timer1 .......................... 73 TMR1H Register ......................................................... 57 TMR1L Register.......................................................... 57 Timer2 (PIC12F615/617/HV615 Only) Associated registers ................................................... 66 Timers Timer1 T1CON ............................................................... 62 Timer2 T2CON ............................................................... 66 Timing Diagrams A/D Conversion......................................................... 165 A/D Conversion (Sleep Mode).................................. 166 Brown-out Reset (BOR)............................................ 159 Brown-out Reset Situations ...................................... 112 CLKOUT and I/O ...................................................... 158 Clock Timing............................................................. 156 Comparator Output ..................................................... 67 Enhanced Capture/Compare/PWM (ECCP)............. 162 Half-Bridge PWM Output .................................... 99, 104 INT Pin Interrupt ....................................................... 120 PWM Auto-shutdown Auto-restart Enabled......................................... 103 Firmware Restart .............................................. 103 PWM Output (Active-High) ......................................... 98 PWM Output (Active-Low) .......................................... 98 Reset, WDT, OST and Power-up Timer ................... 159 Time-out Sequence Case 1 .............................................................. 114 Case 2 .............................................................. 114 Case 3 .............................................................. 114 Timer0 and Timer1 External Clock ........................... 161 Timer1 Incrementing Edge ......................................... 61 Wake-up from Interrupt............................................. 124 Timing Parameter Symbology .......................................... 155 TRISIO................................................................................ 43 TRISIO Register ................................................................. 44 V Voltage Reference (VR) Specifications ........................................................... 163 Voltage Reference. See Comparator Voltage Reference (CVREF) Voltage References Associated registers ................................................... 78 VP6 Stabilization ........................................................ 74 VREF. SEE ADC Reference Voltage W Wake-up Using Interrupts ................................................. 123 Watchdog Timer (WDT).................................................... 121 Associated registers ................................................. 122 Specifications ........................................................... 160 WPU Register ..................................................................... 46 Writing the Flash Program Memory .................................... 32 WWW Address ................................................................. 209 WWW, On-Line Support ....................................................... 6 2010 Microchip Technology Inc. DS41302D-page 209 PIC12F609/615/617/12HV609/615 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support • Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC12F609/615/617/12HV609/615 DS41302D-page 210 2010 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: FAX: (______) _________ - _________ PIC12F609/615/617/12HV609/615 DS41302D 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 2010 Microchip Technology Inc. DS41302D-page 211 PIC12F609/615/617/12HV609/615 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Temperature Package Pattern Range Device Device: PIC12F609, PIC12F609T(1), PIC12HV609, PIC12HV609T(1), PIC12F615, PIC12F615T(1), PIC12HV615, PIC12HV615T(1), PIC12F617, PIC12F617T(1) Temperature Range: H = -40C to +150C (High Temp)(3) I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package: P = Plastic DIP (PDIP) SN = 8-lead Small Outline (150 mil) (SOIC) MS = Micro Small Outline (MSOP) MF = 8-lead Plastic Dual Flat, No Lead (3x3) (DFN) MD = 8-lead Plastic Dual Flat, No Lead (4x4)(DFN)(1,2) Pattern: QTP, SQTP or ROM Code; Special Requirements (blank otherwise) Examples: a) PIC12F615-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC12F615-I/SN = Industrial Temp., SOIC package, 20 MHz c) PIC12F615T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz d) PIC12F609T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz e) PIC12HV615T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz f) PIC12HV609T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz g) PIC12F617T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz h) PIC12F617-I/P = Industrial Temp., PDIP package, 20 MHz i) PIC12F615-H/SN = High Temp., SOIC package, 20 MHz Note 1: T = in tape and reel for MSOP, SOIC and DFN packages only. 2: Not available for PIC12F617. 3: High Temp. available for PIC12F615 only. DS41302D-page 212 2010 Microchip Technology Inc. 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Designed for use with Tektronix MDO3000, MDO4000B, MSO/DPO4000B and MSO/ DPO5000B Series oscilloscopes, these probes provide up to 1 GHz of analog bandwidth with less than 3.9 pF of capacitive loading. Key performance specs 1 GHz, 500 MHz and 250 MHz probe bandwidth models <4 pF input capacitance 10X and 2X attenuation factor 300 V CAT II input voltage Designed for use with the MDO3000, MDO4000B, MSO/DPO4000B and MSO/DPO5000B series oscilloscopes Key features Compact probe head for probing small-geometry circuit elements Small probe body for enhanced visibility to the device-under-test Rigid tip for secure device-under-test connectivity Replaceable probe tip cartridges Large accessory set for versatile connectivity Connectivity Integrated oscilloscope and probe measurement system provides intelligent communication that automatically scales and adjusts units on the oscilloscope display to match the probe attenuation Built-in AC compensation optimizes signal path across the entire frequency range Applications Low-power devices Service Manufacturing engineering test Research and development Accurate high-speed passive probing The extremely low capacitive loading limits adverse affects on your circuits and is more forgiving of longer ground leads. And with the probe's wide bandwidth, you can see the high-frequency components in your signal which is critical for high-speed applications. The TPP1000, TPP0500B and TPP0250 passive voltage probes offer all the benefits of general-purpose probes like high dynamic range, flexible connection options, and robust mechanical design, while providing the performance of active probes. Accurate low voltage The TPP0502 offers the industry's highest bandwidth (500 MHz) and lowest attenuation factor (2X) for making low-voltage measurements such as ripple, a common measurement on the output of power supplies. The low capacitive loading of the TPP0502 means long ground leads can also be used on this probe with minimal impact on measurement quality, providing today's engineer with the flexibility to move around their design without worrying about ground lead length. www.tektronix.com 1 Specifications All specifications apply to all models unless noted otherwise. Model overview TPP1000 TPP0500B TPP0502 TPP0250 Attenuation 10X 10X 2X 10X Dynamic range 300 V Cat II 300 V Cat II 300 V Cat II 300 V Cat II Bandwidth 1 GHz 500 MHz 500 MHz 250 MHz Input impedance at the probe tip 10 MΩ, <4 pF 10 MΩ, <4 pF 2 MΩ, 12.7 pF 10 MΩ, <4 pF Cable length 1.3 m 1.3 m 1.3 m 1.3 m Ordering information Models TPP1000 1 GHz, 10X attenuation passive probe with TekVPI™ interface. TPP0500B 500 MHz, 10X attenuation passive probe with TekVPI™ interface. TPP0502 500 MHz, 2X attenuation passive probe with TekVPI™ interface. TPP0250 250 MHz, 10X attenuation passive probe with TekVPI™ interface. Standard accessories Description Quantity included Reorder part number Rigid tip 3.8 mm 1 206-0610-00 Flex ground spring SHORT 3.8 mm 2 016-2034-00 Long ground spring 2 016-2028-00 Alligator ground (6 in.) 1 196-3521-00 Hook tip (regular) 1 013-0362-00 Hook tip (micro) 1 013-0363-00 IC cap (universal) 3.8 mm 1 013-0366-00 Datasheet 2 www.tektronix.com Recommended accessories Description Quantity included Reorder part number Alligator ground (12 in.) 1 196-3512-00 6 in. clip-on ground lead (with 0.025 in. pin receptacle) 1 196-3198-01 Microcircuit test tip 1 206-0569-00 Wire, 32 AWG (spool) 1 020-3045-00 BNC to probe tip adapter 1 013-0367-00 PCB to probe tip adapter, pack of 10 1 016-2016-00 Compact probe tip chassis mount test jack 1 131-4210-00 Color bands (set of 4 color-coded bands) 1 016-0633-00 Tweaker tool 1 003-1433-02 Options Service options Opt. SILV100 Standard warranty extended to 5 years Opt. SILV200 Standard warranty extended to 5 years Probes and accessories are not covered by the oscilloscope warranty and Service Offerings. Refer to the datasheet of each probe and accessory model for its unique warranty and calibration terms. Tektronix is registered to ISO 9001 and ISO 14001 by SRI Quality System Registrar. Product(s) complies with IEEE Standard 488.1-1987, RS-232-C, and with Tektronix Standard Codes and Formats. TPP1000, TPP0500B, TPP0502, TPP0250 Passive Voltage Probes www.tektronix.com 3 Datasheet ASEAN / Australasia (65) 6356 3900 Austria 00800 2255 4835* Balkans, Israel, South Africa and other ISE Countries +41 52 675 3777 Belgium 00800 2255 4835* Brazil +55 (11) 3759 7627 Canada 1 800 833 9200 Central East Europe and the Baltics +41 52 675 3777 Central Europe & Greece +41 52 675 3777 Denmark +45 80 88 1401 Finland +41 52 675 3777 France 00800 2255 4835* Germany 00800 2255 4835* Hong Kong 400 820 5835 India 000 800 650 1835 Italy 00800 2255 4835* Japan 81 (3) 6714 3010 Luxembourg +41 52 675 3777 Mexico, Central/South America & Caribbean 52 (55) 56 04 50 90 Middle East, Asia, and North Africa +41 52 675 3777 The Netherlands 00800 2255 4835* Norway 800 16098 People's Republic of China 400 820 5835 Poland +41 52 675 3777 Portugal 80 08 12370 Republic of Korea 001 800 8255 2835 Russia & CIS +7 (495) 6647564 South Africa +41 52 675 3777 Spain 00800 2255 4835* Sweden 00800 2255 4835* Switzerland 00800 2255 4835* Taiwan 886 (2) 2722 9622 United Kingdom & Ireland 00800 2255 4835* USA 1 800 833 9200 * European toll-free number. If not accessible, call: +41 52 675 3777 Updated 10 April 2013 For Further Information. Tektronix maintains a comprehensive, constantly expanding collection of application notes, technical briefs and other resources to help engineers working on the cutting edge of technology. Please visit www.tektronix.com. Copyright © Tektronix, Inc. All rights reserved. Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Specification and price change privileges reserved. TEKTRONIX and TEK are registered trademarks of Tektronix, Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies. 10 Feb 2014 51W-26151-5 www.tektronix.com http://www.farnell.com/datasheets/1807245.pdf AVR172: Sensorless Commutation of Brushless DC Motor (BLDC) using ATmega32M1 and ATAVRMC320 Features • Robust sensorless commutation control • Ramp-up sequence References [1] ATmega32M1 Data sheet [2] AVR194: Brushless DC Motor Control using ATmega32M1 [3] AVR430: MC300 Hardware User Guide [4] AVR470: MC310 User Guide [5] AVR471: MC320 Getting Started Guide [6] AVR928: Sensorless methods to drive BLDC motors 1 Introduction This application note describes how to implement a sensorless commutation of BLDC motors with the ATAVRMC320 development kit. The ATmega32M1 is equipped with integrated peripherals that reduce the number of external components required in a BLDC application. The ATmega32M1 is suitable for sensorless commutation and for commutation with Hall sensors as well, but this application note focuses on the sensorless commutation. The AVR928 Application Note describes the theory of the sensorless control method and must be carefully read first. 8-bit Microcontrollers Application Note Rev. 8306B-AVR-05/10 2 AVR172 8306B-AVR-05/10 2 Hardware The hardware includes the ATAVRMC310 and ATAVRMC300 boards which are the two parts of the ATAVRMC320 Starter kit. Please refer to the ATAVRMC300 and ATAVRMC310 user guides : - AVR430: MC300 Hardware User Guide - AVR470: MC310 Hardware User Guide 2.1 MC310 jumpers setting The AVR172 firmware has been developed with the following jumper settings: Table 2-1.ATAVRMC310 jumpers setting for sensorless control Designator Setting Function J5 Vm connect PB4 to Vm’ (motor voltage measurement if necessary) J6 PFC OC Connect to overcurrent signal J7 none used by CAN applications J8 ShCo connect PC5 to ShCo for current measurement J9 GNDm connect PC4 to GNDm for current measurement J12 TxD connect PD3 to the RS232 driver MOSI A Connect PD3 to ISP connector (for ISP use) RxDUSB Connect PD3 to RxD1 (for USB interface use) J13 RxD connect PD4 to the RS232 driver SCK Connect PD3 to ISP connector (for ISP use) TxDUSB Connect PD3 to RxD1 (for USB interface use) J15 none used by CAN application to add a termination resistor J21 Cmp- connect ACMP0- to V+W bemf conditioning J22 Cmp+ connect ACMP0+ to U bemf conditioning J23 Cmp- connect ACMP1- to U+W bemf conditioning J24 Cmp+ connect ACMP1+ to V bemf conditioning J25 Cmp- connect ACMP2- to U+V bemf conditioning J26 Cmp+ connect ACMP2+ to W bemf conditioning J28 VCC supply the on board USB dongle from the board power supply See also following picture of MC310 Jumpers configurations : AVR172 3 8306B-AVR-05/10 Figure 1. MC310 Jumpers configuration 2.2 MC300 jumper settings Table 2-1. ATAVRMC300 jumpers setting for sensorless control Designator Setting Function J2 none provide +5V to supply the ATAVRMC310 board On ATAVRMC300, Vm and Vin connectors can be supplied from the same +12V/7A power supply. Nevertheless a separate +12V/1A can also be used to supply the Vin (processor supply voltage). 2.3 Power-supply This firmware example has been configured according to a power-supply Vm=12V. This power-supply must be able to provide up to 4A output current. 2.4 Motor The BLDC motor provided inside MC320 and MC300 Motor Control Kit has the following characteristics: Manufacturer : TECMOTION Number of phases : 3 Number of poles : 8 (4 pairs) Rated voltage : 24V Rated speed : 4000 rpm Rated torque : 62.5 Nm Torque constant : 35 Nm/A = k_tau 4 AVR172 8306B-AVR-05/10 Line to Line Resistance : 1.8 ohm = R Back EMF : 3.66 V/Krpm = k_e Peak current : 5.4A As Vm=12V, the rated speed will be 2000 rpm. 2.5 ATmega32M1 Configuration ATmega32M1 must be programmed to run at 16MHz using PLL (set corresponding Fuse bits). The CKDIV8 fuse must be disabled. Extended/High/Low Fuses configurations are : FF/DF/F3 2.6 Technical Advices 2.6.1 Disconnecting the BLDC Motor The BLDC motor must not be disconnected while it is running or while its coils carry current. It is allowed to disconnect a BLDC motor if the PWM duty cycle is 0% and the rotor is at rest so that no current is driven through the coils. Be careful, when stopping the power supply or PWM, a BLDC motor with a high moment of inertia is able to run for a relatively long time. 2.6.2 Ground and Power Wirings One design its own board has to take care of the ground wiring and power wiring. The power supply of the processor and additional signal conditioning components (e.g. additional fast comparators, operational amplifiers, …) has to be decoupled from the motor power supply. The ground connection has to be of low resistance and low inductance to prevent against voltage drop and noise due to high currents. A ground plane within a multi layer PCB is recommended for proper operation. 3 Firmware The example firmware is based on the Sensorless method described in AVR928 Application Note. It is operating in sensorless mode using the ATmega32M1 internal comparators. Hall sensor wires of the BLDC motor of the kit can remain unconnected. The source file directory embeds an html documentation which can be opened through the readme.html file. The theory of the different tasks has been detailed in AVR928. The application to ATmega32M1 is detailed in following sections. 3.1 Main Flow chart The firmware main flowchart is described below : AVR172 5 8306B-AVR-05/10 Figure 2. Main flow chart The tasks are scheduled thanks to the g_tick produced each 1.024ms with Timer0. 6 AVR172 8306B-AVR-05/10 3.2 MS_ALIGN phase The ALIGN phase forces the motor at a specific position. The time of this phase is controlled with ALIGN_TIME constant which is the ru_period_counter initial value (200 for MC310 motor). 3.3 RAMP_UP phase The ramp-up charateristics (duty-cycles and times) are stored in two tables: • ramp_up_duty_table[] : which provides the duty_cycle of the step • ramp_up_time_table[] : which provides the length of the step (ru_step_length) These two tables are specific to the motor and the application. The scanning of the step sequences and the monitoring of the step length are achieved thanks to three independant counters : - ru_step_length_cntr : which counts the commutation time (up to ru_step_length variable) - ru_period_counter : which counts the step length (up to RAMP_UP_PERIOD constant) - ramp_up_index : which counts the step numbers (up to RAMP_UP_INDEX_MAX constant) The figure below provides a waveform of steps timing : Figure 3. Steps timing AVR172 7 8306B-AVR-05/10 3.3.1 Time of steps The step time is RAMP_UP_PERIOD = 50ms. 3.3.2 Number of steps The parameter : RAMP_UP_INDEX_MAX = 9, defines 10 steps ramp up. 3.3.3 Parameters tables In firmware example, the tables have been defined according to the characteristics of the motor provided in the kit (see parameters in 2.4 Motor section) : ramp_up_time_table[] = {26,23,20,17,14,11,8,5,3,2,2}; ramp_up_duty_table[] = {122,124,126,129,131,133,135,137,140,143,145}; 3.3.4 Sp1/pwm1 The usual parameters described in AVR928 Application Note are: • Pwm1 = 50% • Sp1 = Sp_max/60 The parameters defined with MC310 Tecmotion motor are: • Pwm1 = 48% (= 122/256) • Sp1 : Sp1 is defined thanks to the initialization value of ru_step_length : ru_step_length = RAMP_UP_STEP_MAX = 40 This variable determines one commutation each 40ms. So an electrical rotation time is 120ms. As the motor has 4 pairs of poles, the mechanical rotation time is 480ms. So the rotation speed is 60/0.48 = 125 rpm. So Sp1 = Sp_max/32. The second value of ru_step_length is 26 in the time table. It defines the following commutation time. 3.3.5 Sp2/pwm2 The theorical parameters described in AVR928 Application Note are: • Pwm2 = 60% • Sp2 = Sp_max/6 = Sp1 / 10 The parameters defined with Tecmotion motor are: • Pwm2 = 57% (= 145/256) • Sp2 : Sp2 is defined thanks to the last value of ru_step_length : 2 This variable determines one commutation each 4ms. So an electrical rotation time is 12ms. As the motor has 4 pairs of poles, the mechanical rotation time is 48ms. So the rotation speed is 60/0.048 = 1250 rpm. So Sp2 = Sp_max/3.2. 8 AVR172 8306B-AVR-05/10 This confirms also the usual ratio = 10 between Sp1 and Sp2 which is defined in AVR498 Application Note. 3.4 LAST_RAMP_UP phase To avoid a shorten last step, this phase monitors the last ramp-up step to guarantee it is ended properly before running in closed loop. 3.5 RUNNING Phase 3.5.1 Closed-loop block diagram The Running phase is a sensorless closed loop which block diagram is following : Figure 4. Closed-loop block diagram AVR172 9 8306B-AVR-05/10 3.5.2 Running flowchart The flowchart is following : Figure 5. Closed-loop flowchart • Motor_state is kept equal to MS_RUNNING mci_set_ref_speed() function updates the speed setpoint according to the potentiometer adjustment or the speed command received on serial transmission. In mc_regulation_loop() function, duty_cycle_reference is the duty_cycle variable which controls the PWM generator. This variable is the result of following functions : • In OPEN_LOOP: mci_set_ref_speed() function • In SPEED_LOOP: 10 AVR172 8306B-AVR-05/10 mc_control_speed(2*mci_get_ref_speed()) duty-cycle_reference is calculated from ref_speed and from monitored mci_get_measured_speed() measured_speed = (KSPEED * 4) / mci_measured_period with mci_measured_period calculated in the Interrupt vector of Analog Comparator 1. This interrupt uses Timer 0 to compute the period. • In CURRENT_LOOP : mc_control_current(mc_get_potentiometer_value() 3.5.3 Sensorless Detection and Commutation Management The analog comparators 0, 1 and 2 are used to detect the zero crossing of the U, V and W phases. The timer 1 is used to monitor the time between two consecutive zero crossings. This time corresponds to one sector of the electrical rotation of the motor. It equals 60° of the entire electrical period of the motor. When a zero crossing event occurs, the timer 1 value is stored. Then this value is divided by 2 (providing the 30° time) and loaded into the Compare A register of timer 1. Then this value is added to the half of itself to provide the 45° time and loaded into the Compare B register of timer 1. The timer 1 compare A event occurs 30° after the zero crossing. It activates the next commutation state and masks the zero crossing to avoid the discharge of the inductance (demagnetization) pulse generated at the end of a step when the active switches are released. Due to the inductance of the motor coils, a voltage equals to -Ldi/dt is generated, the demagnetization is done through the diodes of the power bridge. The timer 1 compare B event releases the zero crossing mask : enables the comparator n interrupt according to the motor_step variable. This Timer1 interrupt provides the demagnetization mask delay. AVR172 11 8306B-AVR-05/10 4 RS232 Communication with firmware 4.1 Connecting ATAVRMC310 to use the RS232 interface Connect PC com port to the ATAVRMC310 RS232 connector through a direct cable. The serial configuration is: • 38400 bauds, • 8 bit data bit, • 1 stop bit, • no handshake, 4.2 PC applications User can communicate with firmware through RS232 with usual PC serial communication applications (i.e. Hyperterminal) or the Atmel “Motor Control Center” application which can be downloaded from Atmel web at url : http://www.atmel.com 4.2.1 PC Terminal : RS232 Messages and Commands At power up the following welcome message is received on terminal : “ATMEL Motor Control Interface”. The following commands can be sent to the firmware: Table 2-1. List of commands Command Action ru Run motor st Stop Motor help Gives help fw Set direction to Forward bw Set direction to Backward ss Set Speed (followed with speed value) gi Get ID g0 Get Status 0 g1 Get Status 1 4.2.2 Motor Control Center The User Guide is available in Install directory at URL : C:\Program Files\Atmel\Motor Control Center\help\Overview.htm The AVR172 Target must be selected first to get the right configuration : To select a target, execute the File > Select Target command or click the button in the toolbar. The following dialog pops up: 12 AVR172 8306B-AVR-05/10 Figure 6. Motor Control Center Interface 5 USB communication Communication can be achieved from PC to USB connector of MC310 board. The AVR470, MC310 Hardware User Guide details the configuration to be achieved. Communication port becomes a Virtual Com port. Same tools as described in section 4 (RS232 Communication with firmware), can be used through this Virtual Com port. 8306B-AVR-05/10 Disclaimer Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Product Contact Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en- Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Web Site http://www.atmel.com/ Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Request www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR®, AVR® logo and others, are the registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. http://www.farnell.com/datasheets/1734386.pdf 1. Product profile 1.1 General description NPN/NPN general-purpose transistor pair in a small SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package. 1.2 Features ■ Low collector capacitance ■ Low collector-emitter saturation voltage ■ Closely matched current gain ■ Reduces number of components and board space ■ No mutual interference between the transistors ■ AEC-Q101 qualified 1.3 Applications ■ General-purpose switching and amplification 1.4 Quick reference data BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor Rev. 01 — 25 August 2009 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per transistor VCEO collector-emitter voltage open base - - 45 V IC collector current - - 100 mA hFE DC current gain VCE = 5 V; IC = 2 mA 200 300 450BC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 2 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 emitter TR1 2 base TR1 3 collector TR2 4 emitter TR2 5 base TR2 6 collector TR1 1 3 2 6 5 4 sym020 1 2 3 6 5 TR1 TR2 4 Table 3. Ordering information Type number Package Name Description Version BC847DS SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 Table 4. Marking codes Type number Marking code BC847DS ZL Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 45 V VEBO emitter-base voltage open collector - 6 V IC collector current - 100 mA ICM peak collector current single pulse; tp ≤ 1 ms - 200 mA IBM peak base current single pulse; tp ≤ 1 ms - 200 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW Per device Ptot total power dissipation Tamb ≤ 25 °C [1] - 380 mWBC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 3 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. Tj junction temperature - 150 °C Tamb ambient temperature −55 +150 °C Tstg storage temperature −65 +150 °C FR4 PCB, standard footprint Fig 1. Per device: Power derating curve SOT457 (SC-74) Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tamb (°C) −75 175 −25 25 75 125 006aab621 200 300 100 400 500 Ptot (mW) 0 Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Per transistor Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 500 K/W Rth(j-sp) thermal resistance from junction to solder point - - 250 K/W Per device Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 328 K/WBC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 4 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor 7. Characteristics FR4 PCB, standard footprint Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aab622 10−5 10 10 −2 10−4 102 10−1 tp (s) 10−3 103 1 102 10 103 Zth(j-a) (K/W) 1 δ = 1 0.75 0.50 0.33 0.10 0.05 0.02 0.01 0 0.20 Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per transistor ICBO collector-base cut-off current VCB = 30 V; IE = 0 A - - 15 nA VCB = 30 V; IE = 0 A; Tj = 150 °C --5 µA IEBO emitter-base cut-off current VEB = 6 V; IC = 0 A - - 100 nA hFE DC current gain VCE =5V IC = 10 µA - 280 - IC = 2 mA 200 300 450 VCEsat collector-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - 55 100 mV IC = 100 mA; IB = 5 mA - 200 300 mV VBEsat base-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - 755 850 mV IC = 100 mA; IB = 5 mA - 1000 - mV VBE base-emitter voltage VCE =5V IC = 2 mA 580 650 700 mV IC = 10 mA - - 770 mVBC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 5 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz - 1.9 - pF Ce emitter capacitance VEB = 0.5 V; IC = ic = 0 A; f = 1 MHz - 11 - pF fT transition frequency VCE = 5 V; IC = 10 mA; f = 100 MHz 100 - - MHz NF noise figure VCE = 5 V; IC = 0.2 mA; RS =2kΩ; f = 10 Hz to 15.7 kHz - 1.9 - dB VCE = 5 V; IC = 0.2 mA; RS =2kΩ; f = 1 kHz; B = 200 Hz - 3.1 - dB Table 7. Characteristics …continued Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCE =5V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Tamb = 25 °C Fig 3. Per transistor: DC current gain as a function of collector current; typical values Fig 4. Per transistor: Collector current as a function of collector-emitter voltage; typical values 006aaa533 200 400 600 hFE 0 IC (mA) 10−2 103 102 10−1 1 10 (3) (1) (2) 006aaa532 VCE (V) 0 10 2 4 6 8 0.08 0.12 0.04 0.16 0.20 IC (A) 0 IB (mA) = 4.50 2.70 3.15 4.05 3.60 0.45 0.90 1.35 1.80 2.25BC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 6 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor VCE = 5 V; Tamb = 25 °C IC/IB = 20 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Fig 5. Per transistor: Base-emitter voltage as a function of collector current; typical values Fig 6. Per transistor: Base-emitter saturation voltage as a function of collector current; typical values IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C VCE = 5 V; Tamb = 25 °C Fig 7. Per transistor: Collector-emitter saturation voltage as a function of collector current; typical values Fig 8. Per transistor: Transition frequency as a function of collector current; typical values 006aaa536 0.6 0.8 1 VBE (V) 0.4 IC (mA) 10−1 103 102 1 10 006aaa534 IC (mA) 10−1 103 102 1 10 0.5 0.9 1.3 0.3 0.7 1.1 VBEsat (V) 0.1 (1) (2) (3) 006aaa535 1 10−1 10 VCEsat (V) 10−2 IC (mA) 10−1 103 102 1 10 (1) (2) (3) 006aaa537 IC (mA) 1 102 10 102 103 fT (MHz) 10BC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 7 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor f = 1 MHz; Tamb = 25 °C f = 1 MHz; Tamb = 25 °C Fig 9. Per transistor: Collector capacitance as a function of collector-base voltage; typical values Fig 10. Per transistor: Emitter capacitance as a function of emitter-base voltage; typical values VCB (V) 0 10 2 4 6 8 006aab620 2 4 6 Cc (pF) 0 006aaa539 VEB (V) 0 6 2 4 9 11 7 13 15 Ce (pF) 5BC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 8 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. [2] T1: normal taping [3] T2: reverse taping Fig 11. Package outline SOT457 (SC-74) Dimensions in mm 04-11-08 3.0 2.5 1.7 1.3 3.1 2.7 pin 1 index 1.9 0.26 0.10 0.40 0.25 0.95 1.1 0.9 0.6 0.2 1 3 2 6 5 4 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 BC847DS SOT457 4 mm pitch, 8 mm tape and reel; T1 [2] -115 -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 -165BC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 9 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor 11. Soldering Fig 12. Reflow soldering footprint SOT457 (SC-74) Fig 13. Wave soldering footprint SOT457 (SC-74) solder lands solder resist occupied area solder paste sot457_fr 3.45 1.95 3.3 2.825 0.45 (6×) 0.55 (6×) 0.7 (6×) 0.8 (6×) 2.4 0.95 0.95 Dimensions in mm sot457_fw 5.3 5.05 1.45 (6×) 0.45 (2×) 1.5 (4×) 2.85 1.475 1.475 solder lands solder resist occupied area preferred transport direction during soldering Dimensions in mmBC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 10 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes BC847DS_1 20090825 Product data sheet - -BC847DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 25 August 2009 11 of 12 NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.NXP Semiconductors BC847DS 45 V, 100 mA NPN/NPN general-purpose transistor © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 August 2009 Document identifier: BC847DS_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 8 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 Packing information. . . . . . . . . . . . . . . . . . . . . . 8 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 Contact information. . . . . . . . . . . . . . . . . . . . . 11 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 http://www.farnell.com/datasheets/480916.pdf Plug and Play Wireless CPU® Fastrack Supreme User Guide Revision: 003 Date: November
http://www.farnell.com/datasheets/1793262.pdf
