NE5532 - Texas Instruments - Farnell Element 14 - Revenir à l'accueil
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Farnell-2-GBPS-Diffe..> 28-Jul-2014 17:42 2.7M
Farnell-LMT88-2.4V-1..> 28-Jul-2014 17:42 2.8M
Farnell-Octal-Genera..> 28-Jul-2014 17:42 2.8M
Farnell-Dual-MOSFET-..> 28-Jul-2014 17:41 2.8M
Farnell-TLV320AIC325..> 28-Jul-2014 17:41 2.9M
Farnell-SN54LV4053A-..> 28-Jul-2014 17:20 5.9M
Farnell-TAS1020B-USB..> 28-Jul-2014 17:19 6.2M
Farnell-TPS40060-Wid..> 28-Jul-2014 17:19 6.3M
Farnell-TL082-Wide-B..> 28-Jul-2014 17:16 6.3M
Farnell-RF-short-tra..> 28-Jul-2014 17:16 6.3M
Farnell-maxim-integr..> 28-Jul-2014 17:14 6.4M
Farnell-TSV6390-TSV6..> 28-Jul-2014 17:14 6.4M
Farnell-Fast-Charge-..> 28-Jul-2014 17:12 6.4M
Farnell-NVE-datashee..> 28-Jul-2014 17:12 6.5M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-REF102-10V-P..> 28-Jul-2014 17:09 2.4M
Farnell-TMS320F28055..> 28-Jul-2014 17:09 2.7M
Farnell-MULTICOMP-Ra..> 22-Jul-2014 12:35 5.9M
Farnell-RASPBERRY-PI..> 22-Jul-2014 12:35 5.9M
Farnell-Dremel-Exper..> 22-Jul-2014 12:34 1.6M
Farnell-STM32F103x8-..> 22-Jul-2014 12:33 1.6M
Farnell-BD6xxx-PDF.htm 22-Jul-2014 12:33 1.6M
Farnell-L78S-STMicro..> 22-Jul-2014 12:32 1.6M
Farnell-RaspiCam-Doc..> 22-Jul-2014 12:32 1.6M
Farnell-SB520-SB5100..> 22-Jul-2014 12:32 1.6M
Farnell-iServer-Micr..> 22-Jul-2014 12:32 1.6M
Farnell-LUMINARY-MIC..> 22-Jul-2014 12:31 3.6M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:31 2.4M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:30 4.6M
Farnell-CLASS 1-or-2..> 22-Jul-2014 12:30 4.7M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:29 4.8M
Farnell-Evaluating-t..> 22-Jul-2014 12:28 4.9M
Farnell-LM3S6952-Mic..> 22-Jul-2014 12:27 5.9M
Farnell-Keyboard-Mou..> 22-Jul-2014 12:27 5.9M
Farnell-Full-Datashe..> 15-Jul-2014 17:08 951K
Farnell-pmbta13_pmbt..> 15-Jul-2014 17:06 959K
Farnell-EE-SPX303N-4..> 15-Jul-2014 17:06 969K
Farnell-Datasheet-NX..> 15-Jul-2014 17:06 1.0M
Farnell-Datasheet-Fa..> 15-Jul-2014 17:05 1.0M
Farnell-MIDAS-un-tra..> 15-Jul-2014 17:05 1.0M
Farnell-SERIAL-TFT-M..> 15-Jul-2014 17:05 1.0M
Farnell-MCOC1-Farnel..> 15-Jul-2014 17:05 1.0M
Farnell-TMR-2-series..> 15-Jul-2014 16:48 787K
Farnell-DC-DC-Conver..> 15-Jul-2014 16:48 781K
Farnell-Full-Datashe..> 15-Jul-2014 16:47 803K
Farnell-TMLM-Series-..> 15-Jul-2014 16:47 810K
Farnell-TEL-5-Series..> 15-Jul-2014 16:47 814K
Farnell-TXL-series-t..> 15-Jul-2014 16:47 829K
Farnell-TEP-150WI-Se..> 15-Jul-2014 16:47 837K
Farnell-AC-DC-Power-..> 15-Jul-2014 16:47 845K
Farnell-TIS-Instruct..> 15-Jul-2014 16:47 845K
Farnell-TOS-tracopow..> 15-Jul-2014 16:47 852K
Farnell-TCL-DC-traco..> 15-Jul-2014 16:46 858K
Farnell-TIS-series-t..> 15-Jul-2014 16:46 875K
Farnell-TMR-2-Series..> 15-Jul-2014 16:46 897K
Farnell-TMR-3-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-TEN-8-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-Full-Datashe..> 15-Jul-2014 16:46 947K
Farnell-HIP4081A-Int..> 07-Jul-2014 19:47 1.0M
Farnell-ISL6251-ISL6..> 07-Jul-2014 19:47 1.1M
Farnell-DG411-DG412-..> 07-Jul-2014 19:47 1.0M
Farnell-3367-ARALDIT..> 07-Jul-2014 19:46 1.2M
Farnell-ICM7228-Inte..> 07-Jul-2014 19:46 1.1M
Farnell-Data-Sheet-K..> 07-Jul-2014 19:46 1.2M
Farnell-Silica-Gel-M..> 07-Jul-2014 19:46 1.2M
Farnell-TKC2-Dusters..> 07-Jul-2014 19:46 1.2M
Farnell-CRC-HANDCLEA..> 07-Jul-2014 19:46 1.2M
Farnell-760G-French-..> 07-Jul-2014 19:45 1.2M
Farnell-Decapant-KF-..> 07-Jul-2014 19:45 1.2M
Farnell-1734-ARALDIT..> 07-Jul-2014 19:45 1.2M
Farnell-Araldite-Fus..> 07-Jul-2014 19:45 1.2M
Farnell-fiche-de-don..> 07-Jul-2014 19:44 1.4M
Farnell-safety-data-..> 07-Jul-2014 19:44 1.4M
Farnell-A-4-Hardener..> 07-Jul-2014 19:44 1.4M
Farnell-CC-Debugger-..> 07-Jul-2014 19:44 1.5M
Farnell-MSP430-Hardw..> 07-Jul-2014 19:43 1.8M
Farnell-SmartRF06-Ev..> 07-Jul-2014 19:43 1.6M
Farnell-CC2531-USB-H..> 07-Jul-2014 19:43 1.8M
Farnell-Alimentation..> 07-Jul-2014 19:43 1.8M
Farnell-BK889B-PONT-..> 07-Jul-2014 19:42 1.8M
Farnell-User-Guide-M..> 07-Jul-2014 19:41 2.0M
Farnell-T672-3000-Se..> 07-Jul-2014 19:41 2.0M
Farnell-0050375063-D..> 18-Jul-2014 17:03 2.5M
Farnell-Mini-Fit-Jr-..> 18-Jul-2014 17:03 2.5M
Farnell-43031-0002-M..> 18-Jul-2014 17:03 2.5M
Farnell-0433751001-D..> 18-Jul-2014 17:02 2.5M
Farnell-Cube-3D-Prin..> 18-Jul-2014 17:02 2.5M
Farnell-MTX-Compact-..> 18-Jul-2014 17:01 2.5M
Farnell-MTX-3250-MTX..> 18-Jul-2014 17:01 2.5M
Farnell-ATtiny26-L-A..> 18-Jul-2014 17:00 2.6M
Farnell-MCP3421-Micr..> 18-Jul-2014 17:00 1.2M
Farnell-LM19-Texas-I..> 18-Jul-2014 17:00 1.2M
Farnell-Data-Sheet-S..> 18-Jul-2014 17:00 1.2M
Farnell-LMH6518-Texa..> 18-Jul-2014 16:59 1.3M
Farnell-AD7719-Low-V..> 18-Jul-2014 16:59 1.4M
Farnell-DAC8143-Data..> 18-Jul-2014 16:59 1.5M
Farnell-BGA7124-400-..> 18-Jul-2014 16:59 1.5M
Farnell-SICK-OPTIC-E..> 18-Jul-2014 16:58 1.5M
Farnell-LT3757-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-LT1961-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-PIC18F2420-2..> 18-Jul-2014 16:57 2.5M
Farnell-DS3231-DS-PD..> 18-Jul-2014 16:57 2.5M
Farnell-RDS-80-PDF.htm 18-Jul-2014 16:57 1.3M
Farnell-AD8300-Data-..> 18-Jul-2014 16:56 1.3M
Farnell-LT6233-Linea..> 18-Jul-2014 16:56 1.3M
Farnell-MAX1365-MAX1..> 18-Jul-2014 16:56 1.4M
Farnell-XPSAF5130-PD..> 18-Jul-2014 16:56 1.4M
Farnell-DP83846A-DsP..> 18-Jul-2014 16:55 1.5M
Farnell-Dremel-Exper..> 18-Jul-2014 16:55 1.6M
Farnell-MCOC1-Farnel..> 16-Jul-2014 09:04 1.0M
Farnell-SL3S1203_121..> 16-Jul-2014 09:04 1.1M
Farnell-PN512-Full-N..> 16-Jul-2014 09:03 1.4M
Farnell-SL3S4011_402..> 16-Jul-2014 09:03 1.1M
Farnell-LPC408x-7x 3..> 16-Jul-2014 09:03 1.6M
Farnell-PCF8574-PCF8..> 16-Jul-2014 09:03 1.7M
Farnell-LPC81xM-32-b..> 16-Jul-2014 09:02 2.0M
Farnell-LPC1769-68-6..> 16-Jul-2014 09:02 1.9M
Farnell-Download-dat..> 16-Jul-2014 09:02 2.2M
Farnell-LPC3220-30-4..> 16-Jul-2014 09:02 2.2M
Farnell-LPC11U3x-32-..> 16-Jul-2014 09:01 2.4M
Farnell-SL3ICS1002-1..> 16-Jul-2014 09:01 2.5M
Farnell-T672-3000-Se..> 08-Jul-2014 18:59 2.0M
Farnell-tesa®pack63..> 08-Jul-2014 18:56 2.0M
Farnell-Encodeur-USB..> 08-Jul-2014 18:56 2.0M
Farnell-CC2530ZDK-Us..> 08-Jul-2014 18:55 2.1M
Farnell-2020-Manuel-..> 08-Jul-2014 18:55 2.1M
Farnell-Synchronous-..> 08-Jul-2014 18:54 2.1M
Farnell-Arithmetic-L..> 08-Jul-2014 18:54 2.1M
Farnell-NA555-NE555-..> 08-Jul-2014 18:53 2.2M
Farnell-4-Bit-Magnit..> 08-Jul-2014 18:53 2.2M
Farnell-LM555-Timer-..> 08-Jul-2014 18:53 2.2M
Farnell-L293d-Texas-..> 08-Jul-2014 18:53 2.2M
Farnell-SN54HC244-SN..> 08-Jul-2014 18:52 2.3M
Farnell-MAX232-MAX23..> 08-Jul-2014 18:52 2.3M
Farnell-High-precisi..> 08-Jul-2014 18:51 2.3M
Farnell-SMU-Instrume..> 08-Jul-2014 18:51 2.3M
Farnell-900-Series-B..> 08-Jul-2014 18:50 2.3M
Farnell-BA-Series-Oh..> 08-Jul-2014 18:50 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.5M
Farnell-270-Series-O..> 08-Jul-2014 18:49 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.8M
Farnell-Tiva-C-Serie..> 08-Jul-2014 18:49 2.6M
Farnell-UTO-Souriau-..> 08-Jul-2014 18:48 2.8M
Farnell-Clipper-Seri..> 08-Jul-2014 18:48 2.8M
Farnell-SOURIAU-Cont..> 08-Jul-2014 18:47 3.0M
Farnell-851-Series-P..> 08-Jul-2014 18:47 3.0M
Farnell-SL59830-Inte..> 06-Jul-2014 10:07 1.0M
Farnell-ALF1210-PDF.htm 06-Jul-2014 10:06 4.0M
Farnell-AD7171-16-Bi..> 06-Jul-2014 10:06 1.0M
Farnell-Low-Noise-24..> 06-Jul-2014 10:05 1.0M
Farnell-ESCON-Featur..> 06-Jul-2014 10:05 938K
Farnell-74LCX573-Fai..> 06-Jul-2014 10:05 1.9M
Farnell-1N4148WS-Fai..> 06-Jul-2014 10:04 1.9M
Farnell-FAN6756-Fair..> 06-Jul-2014 10:04 850K
Farnell-Datasheet-Fa..> 06-Jul-2014 10:04 861K
Farnell-ES1F-ES1J-fi..> 06-Jul-2014 10:04 867K
Farnell-QRE1113-Fair..> 06-Jul-2014 10:03 879K
Farnell-2N7002DW-Fai..> 06-Jul-2014 10:03 886K
Farnell-FDC2512-Fair..> 06-Jul-2014 10:03 886K
Farnell-FDV301N-Digi..> 06-Jul-2014 10:03 886K
Farnell-S1A-Fairchil..> 06-Jul-2014 10:03 896K
Farnell-BAV99-Fairch..> 06-Jul-2014 10:03 896K
Farnell-74AC00-74ACT..> 06-Jul-2014 10:03 911K
Farnell-NaPiOn-Panas..> 06-Jul-2014 10:02 911K
Farnell-LQ-RELAYS-AL..> 06-Jul-2014 10:02 924K
Farnell-ev-relays-ae..> 06-Jul-2014 10:02 926K
Farnell-ESCON-Featur..> 06-Jul-2014 10:02 931K
Farnell-Amplifier-In..> 06-Jul-2014 10:02 940K
Farnell-Serial-File-..> 06-Jul-2014 10:02 941K
Farnell-Both-the-Del..> 06-Jul-2014 10:01 948K
Farnell-Videk-PDF.htm 06-Jul-2014 10:01 948K
Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-Sensorless-C..> 04-Jul-2014 10:42 3.3M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-PIC12F609-61..> 04-Jul-2014 10:41 3.7M
Farnell-PADO-semi-au..> 04-Jul-2014 10:41 3.7M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-Series-TDS10..> 04-Jul-2014 10:39 4.0M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-0430300011-D..> 14-Jun-2014 18:13 2.0M
Farnell-06-6544-8-PD..> 26-Mar-2014 17:56 2.7M
Farnell-3M-Polyimide..> 21-Mar-2014 08:09 3.9M
Farnell-3M-VolitionT..> 25-Mar-2014 08:18 3.3M
Farnell-10BQ060-PDF.htm 14-Jun-2014 09:50 2.4M
Farnell-10TPB47M-End..> 14-Jun-2014 18:16 3.4M
Farnell-12mm-Size-In..> 14-Jun-2014 09:50 2.4M
Farnell-24AA024-24LC..> 23-Jun-2014 10:26 3.1M
Farnell-50A-High-Pow..> 20-Mar-2014 17:31 2.9M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-1907-2006-PD..> 26-Mar-2014 17:56 2.7M
Farnell-5910-PDF.htm 25-Mar-2014 08:15 3.0M
Farnell-6517b-Electr..> 29-Mar-2014 11:12 3.3M
Farnell-A-True-Syste..> 29-Mar-2014 11:13 3.3M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-AD524-PDF.htm 20-Mar-2014 17:33 2.8M
Farnell-ADL6507-PDF.htm 14-Jun-2014 18:19 3.4M
Farnell-ADSP-21362-A..> 20-Mar-2014 17:34 2.8M
Farnell-ALF1210-PDF.htm 04-Jul-2014 10:39 4.0M
Farnell-ALF1225-12-V..> 01-Apr-2014 07:40 3.4M
Farnell-ALF2412-24-V..> 01-Apr-2014 07:39 3.4M
Farnell-AN10361-Phil..> 23-Jun-2014 10:29 2.1M
Farnell-ARADUR-HY-13..> 26-Mar-2014 17:55 2.8M
Farnell-ARALDITE-201..> 21-Mar-2014 08:12 3.7M
Farnell-ARALDITE-CW-..> 26-Mar-2014 17:56 2.7M
Farnell-ATMEL-8-bit-..> 19-Mar-2014 18:04 2.1M
Farnell-ATMEL-8-bit-..> 11-Mar-2014 07:55 2.1M
Farnell-ATmega640-VA..> 14-Jun-2014 09:49 2.5M
Farnell-ATtiny20-PDF..> 25-Mar-2014 08:19 3.6M
Farnell-ATtiny26-L-A..> 13-Jun-2014 18:40 1.8M
Farnell-Alimentation..> 14-Jun-2014 18:24 2.5M
Farnell-Alimentation..> 01-Apr-2014 07:42 3.4M
Farnell-Amplificateu..> 29-Mar-2014 11:11 3.3M
Farnell-An-Improved-..> 14-Jun-2014 09:49 2.5M
Farnell-Atmel-ATmega..> 19-Mar-2014 18:03 2.2M
Farnell-Avvertenze-e..> 14-Jun-2014 18:20 3.3M
Farnell-BC846DS-NXP-..> 13-Jun-2014 18:42 1.6M
Farnell-BC847DS-NXP-..> 23-Jun-2014 10:24 3.3M
Farnell-BF545A-BF545..> 23-Jun-2014 10:28 2.1M
Farnell-BK2650A-BK26..> 29-Mar-2014 11:10 3.3M
Farnell-BT151-650R-N..> 13-Jun-2014 18:40 1.7M
Farnell-BTA204-800C-..> 13-Jun-2014 18:42 1.6M
Farnell-BUJD203AX-NX..> 13-Jun-2014 18:41 1.7M
Farnell-BYV29F-600-N..> 13-Jun-2014 18:42 1.6M
Farnell-BYV79E-serie..> 10-Mar-2014 16:19 1.6M
Farnell-BZX384-serie..> 23-Jun-2014 10:29 2.1M
Farnell-Battery-GBA-..> 14-Jun-2014 18:13 2.0M
Farnell-C.A-6150-C.A..> 14-Jun-2014 18:24 2.5M
Farnell-C.A 8332B-C...> 01-Apr-2014 07:40 3.4M
Farnell-CC2560-Bluet..> 29-Mar-2014 11:14 2.8M
Farnell-CD4536B-Type..> 14-Jun-2014 18:13 2.0M
Farnell-CIRRUS-LOGIC..> 10-Mar-2014 17:20 2.1M
Farnell-CS5532-34-BS..> 01-Apr-2014 07:39 3.5M
Farnell-Cannon-ZD-PD..> 11-Mar-2014 08:13 2.8M
Farnell-Ceramic-tran..> 14-Jun-2014 18:19 3.4M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Cles-electro..> 21-Mar-2014 08:13 3.9M
Farnell-Conception-d..> 11-Mar-2014 07:49 2.4M
Farnell-Connectors-N..> 14-Jun-2014 18:12 2.1M
Farnell-Construction..> 14-Jun-2014 18:25 2.5M
Farnell-Controle-de-..> 11-Mar-2014 08:16 2.8M
Farnell-Cordless-dri..> 14-Jun-2014 18:13 2.0M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:48 2.5M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:51 1.8M
Farnell-Davum-TMC-PD..> 14-Jun-2014 18:27 2.4M
Farnell-De-la-puissa..> 29-Mar-2014 11:10 3.3M
Farnell-Directive-re..> 25-Mar-2014 08:16 3.0M
Farnell-Documentatio..> 14-Jun-2014 18:26 2.5M
Farnell-Download-dat..> 13-Jun-2014 18:40 1.8M
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Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-EPCOS-Sample..> 11-Mar-2014 07:53 2.2M
Farnell-ES2333-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-Ed.081002-DA..> 19-Mar-2014 18:02 2.5M
Farnell-F28069-Picco..> 14-Jun-2014 18:14 2.0M
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Farnell-FDS-ITW-Spra..> 14-Jun-2014 18:22 3.3M
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Farnell-Fiche-de-don..> 14-Jun-2014 09:47 2.5M
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Farnell-Fluke-1730-E..> 14-Jun-2014 18:23 2.5M
Farnell-GALVA-A-FROI..> 26-Mar-2014 17:56 2.7M
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Farnell-GN-RELAYS-AG..> 20-Mar-2014 08:11 2.6M
Farnell-HC49-4H-Crys..> 14-Jun-2014 18:20 3.3M
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Farnell-HI-70300-Sol..> 14-Jun-2014 18:27 2.4M
Farnell-HUNTSMAN-Adv..> 10-Mar-2014 16:17 1.7M
Farnell-Haute-vitess..> 11-Mar-2014 08:17 2.4M
Farnell-IP4252CZ16-8..> 13-Jun-2014 18:41 1.7M
Farnell-Instructions..> 19-Mar-2014 18:01 2.5M
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Farnell-Loctite3455-..> 25-Mar-2014 08:16 3.0M
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Farnell-Lubrifiant-a..> 26-Mar-2014 18:00 2.7M
Farnell-MC3510-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-MC21605-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-MCF532x-7x-E..> 29-Mar-2014 11:14 2.8M
Farnell-MICREL-KSZ88..> 11-Mar-2014 07:54 2.2M
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Farnell-MOLEX-39-00-..> 10-Mar-2014 17:19 1.9M
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Farnell-MX670-MX675-..> 14-Jun-2014 09:46 2.5M
Farnell-Microchip-MC..> 13-Jun-2014 18:27 1.8M
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Farnell-Molex-83421-..> 14-Jun-2014 18:17 3.4M
Farnell-Molex-COMMER..> 14-Jun-2014 18:16 3.4M
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Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46 464K1FEATURES 1 2 3 4 5 6 7 8 2IN+ 2IN– 2OUT V CC+ V CC– 1IN+ 1IN– 1OUT NE5532, NE5532A . . . D, P, OR PS PACKAGE SA5532, SA5532A . . . D OR P PACKAGE (TOP VIEW) DESCRIPTION/ORDERING INFORMATION NE5532, NE5532A SA5532, SA5532A www.ti.com................................................................................................................................................... SLOS075I–NOVEMBER 1979–REVISED APRIL 2009 DUAL LOW-NOISE OPERATIONAL AMPLIFIERS · Equivalent Input Noise Voltage: 5 nV/√Hz Typ at 1 kHz · Unity-Gain Bandwidth: 10 MHz Typ · Common-Mode Rejection Ratio: 100 dB Typ · High DC Voltage Gain: 100 V/mV Typ · Peak-to-Peak Output Voltage Swing 26 V Typ With VCC± = ±15 V and RL = 600 Ω · High Slew Rate: 9 V/ms Typ The NE5532, NE5532A, SA5532, and SA5532A are high-performance operational amplifiers combining excellent dc and ac characteristics. They feature very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, high slew rate, input-protection diodes, and output short-circuit protection. These operational amplifiers are compensated internally for unity-gain operation. These devices have specified maximum limits for equivalent input noise voltage. ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING NE5532P NE5532P PDIP – P Tube of 50 NE5532AP NE5532AP Tube of 75 NE5532D N5532 Reel of 2500 NE5532DR 0°C to 70°C SOIC – D Tube of 75 NE5532AD N5532A Reel of 2500 NE5532ADR NE5532PSR N5532 SOP – PS Reel of 2000 NE5532APSR N5532A SA5532P SA5532P PDIP – P Tube of 50 SA5532AP SA5532AP Tube of 75 SA5532D –40°C to 85°C SA5532 Reel of 2500 SA5532DR SOIC – D Tube of 75 SA5532AD SA5532A Reel of 2500 SA5532ADR (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1979–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. OUT VCC– VCC+ 36 pF 37 pF 14 pF 7 pF 15 W 460 W 15 W IN+ IN– Component values shown are nominal. ABSOLUTE MAXIMUM RATINGS(1) NE5532, NE5532A SA5532, SA5532A SLOS075I–NOVEMBER 1979–REVISED APRIL 2009................................................................................................................................................... www.ti.com SCHEMATIC (EACH AMPLIFIER) over operating free-air temperature range (unless otherwise noted) VCC+ 22 V VCC Supply voltage(2) VCC– –22 V Input voltage, either input(2) (3) VCC± Input current(4) ±10 mA Duration of output short circuit(5) Unlimited D package 97°C/W qJA Package thermal impedance(6) (7) P package 85°C/W PS package 95°C/W TJ Operating virtual-junction temperature 150°C Tstg Storage temperature range –65°C to 150°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. (3) The magnitude of the input voltage must never exceed the magnitude of the supply voltage. (4) Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless some limiting resistance is used. (5) The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the maximum dissipation rating is not exceeded. (6) The package thermal impedance is calculated in accordance with JESD 51-7. (7) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 2 Submit Documentation Feedback Copyright © 1979–2009, Texas Instruments Incorporated Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS NE5532, NE5532A SA5532, SA5532A www.ti.com................................................................................................................................................... SLOS075I–NOVEMBER 1979–REVISED APRIL 2009 MIN MAX UNIT VCC+ Supply voltage 5 15 V VCC– Supply voltage –5 –15 V NE5532, NE5532A 0 70 TA Operating free-air temperature °C SA5532, SA5532A –40 85 VCC± = ±15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT TA = 25°C 0.5 4 VIO Input offset voltage VO = 0 mV TA = Full range(2) 5 TA = 25°C 10 150 IIO Input offset current nA TA = Full range(2) 200 TA = 25°C 200 800 IIB Input bias current nA TA = Full range(2) 1000 VICR Common-mode input-voltage range ±12 ±13 V V Maximum peak-to-peak output-voltage OPP swing RL ≥ 600 Ω, VCC± = ±15 V 24 26 V TA = 25°C 15 50 RL ≥ 600 Ω, VO = ±10 V Large-signal differential-voltage TA = Full range(2) 10 AVD amplification V/mV TA = 25°C 25 100 RL ≥ 2 kΩ, VO±10 V TA = Full range(2) 15 A Small-signal differential-voltage vd amplification f = 10 kHz 2.2 V/mV BOM Maximum output-swing bandwidth RL = 600 Ω, VO = ±10 V 140 kHz B1 Unity-gain bandwidth RL = 600 Ω, CL = 100 pF 10 MHz ri Input resistance 30 300 kΩ zo Output impedance AVD = 30 dB, RL = 600 Ω, f = 10 kHz 0.3 Ω CMRR Common-mode rejection ratio VIC = VICR min 70 100 dB k Supply-voltage rejection ratio SVR (ΔV VCC± = ±9 V to ±15 V, VO = 0 80 100 dB CC±/ΔVIO) IOS Output short-circuit current 10 38 60 mA ICC Total supply curent VO = 0, No load 8 16 mA Crosstalk attenuation (VO1/VO2) V01 = 10 V peak, f = 1 kHz 110 dB (1) All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. (2) Full temperature ranges are: –40°C to 85°C for the SA5532 and SA5532A, and 0°C to 70°C for the NE5532 and NE5532A. Copyright © 1979–2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A OPERATING CHARACTERISTICS NE5532, NE5532A SA5532, SA5532A SLOS075I–NOVEMBER 1979–REVISED APRIL 2009................................................................................................................................................... www.ti.com VCC± = ±15 V, TA = 25°C (unless otherwise noted) NE5532, SA5532 NE5532A, SA5532A PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX SR Slew rate at unity gain 9 9 V/ms Overshoot factor VI = 100 mV, RL = 600 Ω, 10 10 % AVD = 1, CL = 100 pF f = 30 Hz 8 8 10 Vn Equivalent input noise voltage nV/√Hz f = 1 kHz 5 5 6 f = 30 Hz 2.7 2.7 In Equivalent input noise current pA/√Hz f = 1 kHz 0.7 0.7 4 Submit Documentation Feedback Copyright © 1979–2009, Texas Instruments Incorporated Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples NE5532AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADG4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70 NE5532ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532AIP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85 NE5532AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532AP NE5532APE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532AP NE5532APSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532APSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532APSRG4 ACTIVE SO PS 8 TBD Call TI Call TI 0 to 70 NE5532D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DE4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70 NE5532DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 N5532 NE5532DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples NE5532IP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85 NE5532P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532P NE5532PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532P NE5532PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 SA5532AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADRE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532AP SA5532APE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532AP SA5532D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532DE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532DG4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532DRE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SA5532DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532P SA5532PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 4 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant NE5532ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532APSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 NE5532DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 NE5532DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SA5532ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SA5532DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NE5532ADR SOIC D 8 2500 340.5 338.1 20.6 NE5532APSR SO PS 8 2000 367.0 367.0 38.0 NE5532DR SOIC D 8 2500 364.0 364.0 27.0 NE5532DR SOIC D 8 2500 340.5 338.1 20.6 NE5532DRG4 SOIC D 8 2500 340.5 338.1 20.6 NE5532PSR SO PS 8 2000 367.0 367.0 38.0 SA5532ADR SOIC D 8 2500 340.5 338.1 20.6 SA5532DR SOIC D 8 2500 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated LM386 LM386 Low Voltage Audio Power Amplifier Literature Number: SNAS545A LM386 Low Voltage Audio Power Amplifier General Description The LM386 is a power amplifier designed for use in low voltage consumer applications. The gain is internally set to 20 to keep external part count low, but the addition of an external resistor and capacitor between pins 1 and 8 will increase the gain to any value from 20 to 200. The inputs are ground referenced while the output automatically biases to one-half the supply voltage. The quiescent power drain is only 24 milliwatts when operating from a 6 volt supply, making the LM386 ideal for battery operation. Features n Battery operation n Minimum external parts n Wide supply voltage range: 4V–12V or 5V–18V n Low quiescent current drain: 4mA n Voltage gains from 20 to 200 n Ground referenced input n Self-centering output quiescent voltage n Low distortion: 0.2% (AV = 20, VS = 6V, RL = 8W, PO = 125mW, f = 1kHz) n Available in 8 pin MSOP package Applications n AM-FM radio amplifiers n Portable tape player amplifiers n Intercoms n TV sound systems n Line drivers n Ultrasonic drivers n Small servo drivers n Power converters Equivalent Schematic and Connection Diagrams DS006976-1 Small Outline, Molded Mini Small Outline, and Dual-In-Line Packages DS006976-2 Top View Order Number LM386M-1, LM386MM-1, LM386N-1, LM386N-3 or LM386N-4 See NS Package Number M08A, MUA08A or N08E August 2000 LM386 Low Voltage Audio Power Amplifier © 2000 National Semiconductor Corporation DS006976 www.national.com Absolute Maximum Ratings (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (LM386N-1, -3, LM386M-1) 15V Supply Voltage (LM386N-4) 22V Package Dissipation (Note 3) (LM386N) 1.25W (LM386M) 0.73W (LM386MM-1) 0.595W Input Voltage ±0.4V Storage Temperature −65°C to +150°C Operating Temperature 0°C to +70°C Junction Temperature +150°C Soldering Information Dual-In-Line Package Soldering (10 sec) +260°C Small Outline Package (SOIC and MSOP) Vapor Phase (60 sec) +215°C Infrared (15 sec) +220°C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. Thermal Resistance qJC (DIP) 37°C/W qJA (DIP) 107°C/W qJC (SO Package) 35°C/W qJA (SO Package) 172°C/W qJA (MSOP) 210°C/W qJC (MSOP) 56°C/W Electrical Characteristics (Notes 1, 2) TA = 25°C Parameter Conditions Min Typ Max Units Operating Supply Voltage (VS) LM386N-1, -3, LM386M-1, LM386MM-1 4 12 V LM386N-4 5 18 V Quiescent Current (IQ) VS = 6V, VIN = 0 4 8 mA Output Power (POUT) LM386N-1, LM386M-1, LM386MM-1 VS = 6V, RL = 8W, THD = 10% 250 325 mW LM386N-3 VS = 9V, RL = 8W, THD = 10% 500 700 mW LM386N-4 VS = 16V, RL = 32W, THD = 10% 700 1000 mW Voltage Gain (AV) VS = 6V, f = 1 kHz 26 dB 10 μF from Pin 1 to 8 46 dB Bandwidth (BW) VS = 6V, Pins 1 and 8 Open 300 kHz Total Harmonic Distortion (THD) VS = 6V, RL = 8W, POUT = 125 mW 0.2 % f = 1 kHz, Pins 1 and 8 Open Power Supply Rejection Ratio (PSRR) VS = 6V, f = 1 kHz, CBYPASS = 10 μF 50 dB Pins 1 and 8 Open, Referred to Output Input Resistance (RIN) 50 kW Input Bias Current (IBIAS) VS = 6V, Pins 2 and 3 Open 250 nA Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and 1) a thermal resistance of 107°C/W junction to ambient for the dual-in-line package and 2) a thermal resistance of 170°C/W for the small outline package. LM386 www.national.com 2 Application Hints GAIN CONTROL To make the LM386 a more versatile amplifier, two pins (1 and 8) are provided for gain control. With pins 1 and 8 open the 1.35 kW resistor sets the gain at 20 (26 dB). If a capacitor is put from pin 1 to 8, bypassing the 1.35 kW resistor, the gain will go up to 200 (46 dB). If a resistor is placed in series with the capacitor, the gain can be set to any value from 20 to 200. Gain control can also be done by capacitively coupling a resistor (or FET) from pin 1 to ground. Additional external components can be placed in parallel with the internal feedback resistors to tailor the gain and frequency response for individual applications. For example, we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 1 to 5 (paralleling the internal 15 kW resistor). For 6 dB effective bass boost: R . 15 kW, the lowest value for good stable operation is R = 10 kW if pin 8 is open. If pins 1 and 8 are bypassed then R as low as 2 kW can be used. This restriction is because the amplifier is only compensated for closed-loop gains greater than 9. INPUT BIASING The schematic shows that both inputs are biased to ground with a 50 kW resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV when left open. If the dc source resistance driving the LM386 is higher than 250 kW it will contribute very little additional offset (about 2.5 mV at the input, 50 mV at the output). If the dc source resistance is less than 10 kW, then shorting the unused input to ground will keep the offset low (about 2.5 mV at the input, 50 mV at the output). For dc source resistances between these values we can eliminate excess offset by putting a resistor from the unused input to ground, equal in value to the dc source resistance. Of course all offset problems are eliminated if the input is capacitively coupled. When using the LM386 with higher gains (bypassing the 1.35 kW resistor between pins 1 and 8) it is necessary to bypass the unused input, preventing degradation of gain and possible instabilities. This is done with a 0.1 μF capacitor or a short to ground depending on the dc source resistance on the driven input. LM386 3 www.national.com Typical Performance Characteristics Quiescent Supply Current vs Supply Voltage DS006976-5 Power Supply Rejection Ratio (Referred to the Output) vs Frequency DS006976-12 Peak-to-Peak Output Voltage Swing vs Supply Voltage DS006976-13 Voltage Gain vs Frequency DS006976-14 Distortion vs Frequency DS006976-15 Distortion vs Output Power DS006976-16 Device Dissipation vs Output Power—4W Load DS006976-17 Device Dissipation vs Output Power—8W Load DS006976-18 Device Dissipation vs Output Power—16W Load DS006976-19 LM386 www.national.com 4 Typical Applications Amplifier with Gain = 20 Minimum Parts DS006976-3 Amplifier with Gain = 200 DS006976-4 Amplifier with Gain = 50 DS006976-6 Low Distortion Power Wienbridge Oscillator DS006976-7 Amplifier with Bass Boost DS006976-8 Square Wave Oscillator DS006976-9 LM386 5 www.national.com Typical Applications (Continued) Note 4: Twist Supply lead and supply ground very tightly. Note 5: Twist speaker lead and ground very tightly. Note 6: Ferrite bead in Ferroxcube K5-001-001/3B with 3 turns of wire. Note 7: R1C1 band limits input signals. Note 8: All components must be spaced very closely to IC. Frequency Response with Bass Boost DS006976-10 AM Radio Power Amplifier DS006976-11 LM386 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted SO Package (M) Order Number LM386M-1 NS Package Number M08A LM386 7 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead (0.118” Wide) Molded Mini Small Outline Package Order Number LM386MM-1 NS Package Number MUA08A LM386 www.national.com 8 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Dual-In-Line Package (N) Order Number LM386N-1, LM386N-3 or LM386N-4 NS Package Number N08E LM386 Low Voltage Audio Power Amplifier National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 2-kV ESD Protection for: − LM224K, LM224KA − LM324K, LM324KA − LM2902K, LM2902KV, LM2902KAV Wide Supply Ranges − Single Supply . . . 3 V to 32 V (26 V for LM2902) − Dual Supplies . . . 1.5 V to 16 V (13 V for LM2902) Low Supply-Current Drain Independent of Supply Voltage . . . 0.8 mA Typ Common-Mode Input Voltage Range Includes Ground, Allowing Direct Sensing Near Ground Low Input Bias and Offset Parameters − Input Offset Voltage . . . 3 mV Typ A Versions . . . 2 mV Typ − Input Offset Current . . . 2 nA Typ − Input Bias Current . . . 20 nA Typ A Versions . . . 15 nA Typ Differential Input Voltage Range Equal to Maximum-Rated Supply Voltage . . . 32 V (26 V for LM2902) Open-Loop Differential Voltage Amplification . . . 100 V/mV Typ Internal Frequency Compensation description/ordering information These devices consist of four independent high-gain frequency-compensated operational amplifiers that are designed specifically to operate from a single supply over a wide range of voltages. Operation from split supplies also is possible if the difference between the two supplies is 3 V to 32 V (3 V to 26 V for the LM2902), and VCC is at least 1.5 V more positive than the input common-mode voltage. The low supply-current drain is independent of the magnitude of the supply voltage. Applications include transducer amplifiers, dc amplification blocks, and all the conventional operational-amplifier circuits that now can be more easily implemented in single-supply-voltage systems. For example, the LM124 can be operated directly from the standard 5-V supply that is used in digital systems and provides the required interface electronics, without requiring additional ±15-V supplies. PRODUCTION DATA information is current as of publication date. Copyright 2010, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1OUT 1IN− 1IN+ VCC 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT LM124 . . . D, J, OR W PACKAGE LM124A . . . J OR W PACKAGE LM224, LM224A, LM224K, LM224KA . . . D OR N PACKAGE LM324, LM324K . . . D, N, NS, OR PW PACKAGE LM324A . . . D, DB, N, NS, OR PW PACKAGE LM324KA . . . D, N, NS, OR PW PACKAGE LM2902 . . . D, N, NS, OR PW PACKAGE LM2902K . . . D, DB, N, NS, OR PW PACKAGE LM2902KV, LM2902KAV . . . D OR PW PACKAGE (TOP VIEW) 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 4IN+ NC GND NC 3IN+ 1IN+ NC VCC NC 2IN+ LM124, LM124A . . . FK PACKAGE (TOP VIEW) 1IN− 1OUT NC 3IN− 4IN− 2IN− 2OUT NC NC − No internal connection 3OUT 4OUT On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ORDERING INFORMATION TA VIOmax AT 25°C MAX TESTED VCC PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (N) Tube of 25 LM324N LM324N LM324KN LM324KN Tube of 50 LM324D Reel of 2500 LM324DR LM324 SOIC (D) Reel of 2500 LM324DRG3 Tube of 50 LM324KD LM324K 7 mV 30 V Reel of 2500 LM324KDR Reel of 2000 LM324NSR LM324 SOP (NS) Tube of 50 LM324KNS LM324K Reel of 2000 LM324KNSR Tube of 90 LM324PW L324 TSSOP (PW) Reel of 2000 LM324PWR Tube of 90 LM324KPW L324K 0°C to 70°C Reel of 2000 LM324KPWR PDIP (N) Tube of 25 LM324AN LM324AN Tube of 25 LM324KAN LM324KAN Tube of 50 LM324AD LM324A SOIC (D) Reel of 2500 LM324ADR Tube of 50 LM324KAD LM324KA Reel of 2500 LM324KADR 3 mV 30 V Reel of 2000 LM324ANSR LM324A SOP (NS) Tube of 50 LM324KANS LM324KA Reel of 2000 LM324KANSR SSOP (DB) Reel of 2000 LM324ADBR LM324A Tube of 90 LM324APW L324A TSSOP (PW) Reel of 2000 LM324APWR Tube of 90 LM324KAPW L324KA Reel of 2000 LM324KAPWR PDIP (N) Tube of 25 LM224N LM224N LM224KN LM224KN 5 mV 30 V Tube of 50 LM224D LM224 SOIC (D) Reel of 2500 LM224DR Tube of 50 LM224KD LM224K 25°C to 85°C Reel of 2500 LM224KDR −PDIP (N) Tube of 25 LM224AN LM224AN Tube of 25 LM224KAN LM224KAN 3 mV 30 V Tube of 50 LM224AD LM224A SOIC (D) Reel of 2500 LM224ADR Tube of 50 LM224KAD LM224KA Reel of 2500 LM224KADR † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 ORDERING INFORMATION (CONTINUED) TA VIOmax AT 25°C MAX TESTED VCC PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (N) Tube of 25 LM2902N LM2902N Tube of 25 LM2902KN LM2902KN Tube of 50 LM2902D LM2902 SOIC (D) Reel of 2500 LM2902DR Tube of 50 LM2902KD LM2902K Reel of 2500 LM2902KDR Reel of 2000 LM2902NSR LM2902 26 V SOP (NS) Tube of 50 LM2902KNS LM2902K 7 mV Reel of 2000 LM2902KNSR −40°C to 125°C SSOP (DB) Tube of 80 LM2902KDB L2902K 40 125 Reel of 2000 LM2902KDBR Tube of 90 LM2902PW L2902 TSSOP (PW) Reel of 2000 LM2902PWR Tube of 90 LM2902KPW L2902K Reel of 2000 LM2902KPWR 32 V SOIC (D) Reel of 2500 LM2902KVQDR L2902KV TSSOP (PW) Reel of 2000 LM2902KVQPWR L2902KV 2 mV 32 V SOIC (D) Reel of 2500 LM2902KAVQDR L2902KA TSSOP (PW) Reel of 2000 LM2902KAVQPWR L2902KA CDIP (J) Tube of 25 LM124J LM124J CFP (W) Tube of 25 LM124W LM124W 5 mV 30 V LCCC (FK) Tube of 55 LM124FK LM124FK 55°C to 125°C SOIC (D) Tube of 50 LM124D −LM124 Reel of 2500 LM124DR CDIP (J) Tube of 25 LM124AJ LM124AJ 2 mV 30 V CFP (W) Tube of 25 LM124AW LM124AW LCCC (FK) Tube of 55 LM124AFK LM124AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. symbol (each amplifier) − + IN− IN+ OUT LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematic (each amplifier) To Other Amplifiers ≈6-μA Current Regulator VCC OUT GND IN− IN+ ≈100-μA Current Regulator ≈50-μA Current Regulator COMPONENT COUNT (total device) Epi-FET Transistors Diodes Resistors Capacitors 1 95 4 11 4 ≈6-μA Current Regulator † ESD protection cells - available on LM324K and LM324KA only † † LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† LM2902 ALL OTHER DEVICES UNIT Supply voltage, VCC (see Note 1) ±13 or 26 ±16 or 32 V Differential input voltage, VID (see Note 2) ±26 ±32 V Input voltage, VI (either input) −0.3 to 26 −0.3 to 32 V Duration of output short circuit (one amplifier) to ground at (or below) TA = 25°C, VCC ≤ 15 V (see Note 3) Unlimited Unlimited D package 86 86 DB package 96 96 Package thermal impedance, θJA (see Notes 4 and 5) N package 80 80 °C/W NS package 76 76 PW package 113 113 FK package 5.61 Package thermal impedance, JC (see Notes 6 and 7) J package 15.05 °C/W W package 14.65 Operating virtual junction temperature, TJ 150 150 °C Case temperature for 60 seconds FK package 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J or W package 300 300 °C Storage temperature range, Tstg −65 to 150 −65 to 150 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND. 2. Differential voltages are at IN+, with respect to IN−. 3. Short circuits from outputs to VCC can cause excessive heating and eventual destruction. 4. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/JA. Operating at the absolute maximum TJ of 150°C can affect reliability. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) − TC)/JC. Operating at the absolute maximum TJ of 150°C can affect reliability. 7. The package thermal impedance is calculated in accordance with MIL-STD-883. ESD protection TEST CONDITIONS TYP UNIT Human-Body Model LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV ±2 kV LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† TA LM124 LM224 LM324 LM324K UNIT ‡ MIN TYP§ MAX MIN TYP§ MAX V Input offset voltage VCC = 5 V to MAX, 25°C 3 5 3 7 VIO mV VIC = VICRmin, VO = 1.4 V Full range 7 9 I Input offset current V 1 4 V 25°C 2 30 2 50 IIO VO = 1.4 nA Full range 100 150 I Input bias current V 1 4 V 25°C −20 −150 −20 −250 IIB VO = 1.4 nA Full range −300 −500 25°C 0 to 0 to V Common-mode V 5 V to MAX VCC − 1.5 VCC − 1.5 VICR V input voltage range VCC = Full range 0 to 0 to VCC − 2 VCC − 2 RL = 2 kΩ 25°C VCC − 1.5 VCC − 1.5 V High-level RL = 10 kΩ 25°C VOH V output voltage V MAX RL = 2 kΩ Full range 26 26 p g VCC = RL ≥ 10 kΩ Full range 27 28 27 28 VOL Low-level output voltage RL ≤ 10 kΩ Full range 5 20 5 20 mV A Large-signal differential voltage VCC = 15 V, VO = 1 V to 11 V, 25°C 50 100 25 100 AVD V/mV amplification RL ≥ 2 kΩ Full range 25 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 70 80 65 80 dB k Supply-voltage kSVR rejection ratio 25°C 65 100 65 100 dB (ΔVCC /ΔVIO) VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 dB VCC = 15 V, V 1 V Source CC 25°C −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Full range −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 20 10 20 O p CC VID = −V, VO = 15 V Full range 5 5 VID = −1 V, VO = 200 mV 25°C 12 30 12 30 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V VO = 0, 25°C ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = MAX, VO = 0.5 VCC, No load Full range 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. MAX VCC for testing purposes is 26 V for LM2902 and 30 V for the others. ‡ Full range is −55°C to 125°C for LM124, −25°C to 85°C for LM224, and 0°C to 70°C for LM324. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† T ‡ LM2902 LM2902V TA UNIT MIN TYP§ MAX MIN TYP§ MAX V 5 V t Non-A-suffix 25°C 3 7 3 7 V Input offset voltage VCC = to devices Full range 10 10 VIO MAX, mV VIC = VICRmin, V 1 4 V A-suffix 25°C 1 2 IC ICR VO = 1.4 devices Full range 4 ΔVIO/ΔT Input offset voltage temperature drift RS = 0 Ω Full range 7 μV/°C I Input offset current V 1 4 V 25°C 2 50 2 50 IIO VO = 1.4 nA Full range 300 150 ΔIIO/ΔT Input offset current temperature drift Full range 10 pA/°C I Input bias current V 1 4 V 25°C −20 −250 −20 −250 IIB VO = 1.4 nA Full range −500 −500 25°C 0 to 0 to V Common-mode V 5 V to MAX VCC − 1.5 VCC − 1.5 VICR V input voltage range VCC = Full range 0 to 0 to VCC − 2 VCC − 2 RL = 2 kΩ 25°C V High-level RL = 10 kΩ 25°C VCC − 1.5 VCC − 1.5 VOH V output voltage V MAX RL = 2 kΩ Full range 22 26 p g VCC = RL ≥ 10 kΩ Full range 23 24 27 VOL Low-level output voltage RL ≤ 10 kΩ Full range 5 20 5 20 mV A Large-signal differential voltage VCC = 15 V, VO = 1 V to 11 V, 25°C 25 100 25 100 AVD V/mV amplification RL ≥ 2 kΩ Full range 15 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 50 80 60 80 dB k Supply-voltage kSVR rejection ratio 25°C 50 100 60 100 dB (ΔVCC /ΔVIO) VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 dB VCC = 15 V, V 1 V S CC 25°C −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Source Full range −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 20 10 20 CC VID = −V, VO = 15 V Full range 5 5 VID = −1 V, VO = 200 mV 25°C 30 12 40 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V VO = 0, 25°C ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = MAX, VO = 0.5 VCC, No load Full range 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. MAX VCC for testing purposes is 26 V for LM2902 and 32 V for LM2902V. ‡ Full range is −40°C to 125°C for LM2902. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − MARCH 2010 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† TA ‡ LM124A LM224A LM324A, T LM324KA UNIT A MIN TYP§ MAX MIN TYP§ MAX MIN TYP § MAX V Input offset voltage VCC = 5 V to 30 V, 25°C 2 2 3 2 3 VIO mV VIC = VICRmin, VO = 1.4 V Full range 4 4 5 I Input offset current V 1 4 V 25°C 10 2 15 2 30 IIO VO = 1.4 nA Full range 30 30 75 I Input bias current V 1 4 V 25°C −50 −15 −80 −15 −100 IIB VO = 1.4 nA Full range −100 −100 −200 V Common-mode input V 30 V 25°C 0 to VCC − 1.5 0 to VCC − 1.5 0 to VCC − 1.5 VICR V voltage range VCC = Full range 0 to VCC − 2 0 to VCC − 2 0 to VCC − 2 RL = 2 kΩ 25°C VCC − 1.5 VCC − 1.5 VCC − 1.5 VOH High-level output voltage V 30 V High RL = 2 kΩ Full range 26 26 26 V VCC = RL ≥ 10 kΩ Full range 27 27 28 27 28 VOL Low-level output voltage RL ≤ 10 kΩ Full range 20 5 20 5 20 mV A Large-signal differential VCC = 15 V, VO = 1 V to 11 V, 25°C 50 100 50 100 25 100 AVD V/mV voltage amplification RL ≥ 2 kΩ Full range 25 25 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 70 70 80 65 80 dB kSVR Supply-voltage rejection ratio (ΔVCC /ΔVIO) 25°C 65 65 100 65 100 dB VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 120 dB VCC = 15 V, V 1 V Source 25°C −20 −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Full range −10 −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 10 20 10 20 VID = −V, VO = 15 V Full range 5 5 5 VID = −1 V, VO = 200 mV 25°C 12 12 30 12 30 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V, VO = 0 25°C ±40 ±60 ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = 30 V, VO = 15 V, No load Full range 1.4 3 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. ‡ Full range is −55°C to 125°C for LM124A, −25°C to 85°C for LM224A, and 0°C to 70°C for LM324A. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 operating conditions, VCC = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT SR Slew rate at unity gain RL = 1 MΩ, CL = 30 pF, VI = ±10 V (see Figure 1) 0.5 V/μs B1 Unity-gain bandwidth RL = 1 MΩ, CL = 20 pF (see Figure 1) 1.2 MHz Vn Equivalent input noise voltage RS = 100 Ω, VI = 0 V, f = 1 kHz (see Figure 2) 35 nV/√Hz VO − + RL CL VI VCC+ VCC− Figure 1. Unity-Gain Amplifier VO − + 100 Ω VCC+ VCC− RS 900 Ω VI = 0 V Figure 2. Noise-Test Circuit PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-7704301VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7704301VC A LM124JQMLV 5962-9950403V9B ACTIVE XCEPT KGD 0 100 TBD Call TI N / A for Pkg Type -55 to 125 5962-9950403VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9950403VC A LM124AJQMLV 77043012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043012A LM124FKB 7704301CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301CA LM124JB 7704301DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301DA LM124WB 77043022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043022A LM124AFKB 7704302CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302CA LM124AJB 7704302DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302DA LM124AWB JM38510/11005BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /11005BCA LM124ADR OBSOLETE SOIC D 14 TBD Call TI Call TI -55 to 125 LM124AFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043022A LM124AFKB LM124AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124AJ LM124AJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302CA LM124AJB LM124AWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302DA LM124AWB LM124D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM124DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043012A LM124FKB LM124J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124J LM124JB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301CA LM124JB LM124N OBSOLETE PDIP N 14 TBD Call TI Call TI -55 to 125 LM124W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124W LM124WB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301DA LM124WB LM224AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -25 to 85 LM224A LM224ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224AN LM224ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224AN LM224D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM224DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -25 to 85 LM224 LM224DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -25 to 85 LM224 LM224DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224KAD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KAN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KAN LM224KANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KAN LM224KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KN LM224KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KN LM224N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224N PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM224NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224N LM2902D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902KAVQDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDB ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDBE4 ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDBG4 ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 5 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM2902KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902KN LM2902KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902KN LM2902KNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KVQDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 6 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM2902N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902N LM2902NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902N LM2902NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 125 LM2902PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRE4 ACTIVE TSSOP PW 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902QN OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 125 LM324AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI LM324ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 7 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM324A LM324ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324AN LM324ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324AN LM324ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI LM324APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 L324A LM324APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 8 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM324 LM324DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LM324 LM324DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324KAD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KAN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KAN LM324KANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KAN LM324KANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KAPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 9 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324KAPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KN LM324KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KN LM324KNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 10 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324KPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 LM324N LM324NE3 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU SN N / A for Pkg Type 0 to 70 LM324N LM324NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324N LM324NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI 0 to 70 LM324PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 L324 LM324PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 L324 LM324PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324Y OBSOLETE DIESALE Y 0 TBD Call TI Call TI M38510/11005BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /11005BCA PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 11 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM124, LM124-SP, LM124M, LM2902 : • Catalog: LM124, LM124 • Automotive: LM2902-Q1 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 12 • Enhanced Product: LM2902-EP • Military: LM124M, LM124M • Space: LM124-SP, LM124-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LM124DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM224ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM224KADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM2902DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902KAVQPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KAVQPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902KNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM2902KPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 1 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LM2902KVQPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KVQPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM2902PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902PWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM2902PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 LM324ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM324APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324DR SOIC D 14 2500 330.0 16.4 6.55 9.05 2.1 8.0 16.0 Q1 LM324DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324KAPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324KPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324PWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM324PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM124DR SOIC D 14 2500 367.0 367.0 38.0 LM224ADR SOIC D 14 2500 364.0 364.0 27.0 LM224ADR SOIC D 14 2500 333.2 345.9 28.6 LM224ADRG4 SOIC D 14 2500 333.2 345.9 28.6 LM224ADRG4 SOIC D 14 2500 367.0 367.0 38.0 LM224DR SOIC D 14 2500 367.0 367.0 38.0 LM224DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM224KADR SOIC D 14 2500 367.0 367.0 38.0 LM224KDR SOIC D 14 2500 367.0 367.0 38.0 LM2902DR SOIC D 14 2500 333.2 345.9 28.6 LM2902DR SOIC D 14 2500 367.0 367.0 38.0 LM2902DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM2902DRG4 SOIC D 14 2500 333.2 345.9 28.6 LM2902KAVQPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KAVQPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KDR SOIC D 14 2500 367.0 367.0 38.0 LM2902KNSR SO NS 14 2000 367.0 367.0 38.0 LM2902KPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KVQPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KVQPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 3 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM2902NSR SO NS 14 2000 367.0 367.0 38.0 LM2902PWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902PWRG3 TSSOP PW 14 2000 364.0 364.0 27.0 LM2902PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM324ADBR SSOP DB 14 2000 367.0 367.0 38.0 LM324ADR SOIC D 14 2500 364.0 364.0 27.0 LM324ADR SOIC D 14 2500 367.0 367.0 38.0 LM324ADRG4 SOIC D 14 2500 367.0 367.0 38.0 LM324ANSR SO NS 14 2000 367.0 367.0 38.0 LM324APWR TSSOP PW 14 2000 364.0 364.0 27.0 LM324APWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM324DR SOIC D 14 2500 385.0 388.0 194.0 LM324DR SOIC D 14 2500 364.0 364.0 27.0 LM324DR SOIC D 14 2500 333.2 345.9 28.6 LM324DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM324DRG4 SOIC D 14 2500 333.2 345.9 28.6 LM324KADR SOIC D 14 2500 367.0 367.0 38.0 LM324KANSR SO NS 14 2000 367.0 367.0 38.0 LM324KAPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324KDR SOIC D 14 2500 367.0 367.0 38.0 LM324KNSR SO NS 14 2000 367.0 367.0 38.0 LM324KPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324PWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324PWRG3 TSSOP PW 14 2000 364.0 364.0 27.0 LM324PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 4 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated User's Guide SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U This User’s Guide describes the operation, use, features and characteristics of the TLV320AIC3254EVMU. This small form factor evaluation module (EVM) is a programmable USB audio device that features the TLV320AIC3254 Audio Codec with miniDSP. Figure 1. TLV321AIC3254EVM-U Angle View The following related documents are available through the Texas Instruments Web site at www.ti.com. EVM-Compatible Device Data Sheets Device Literature Number TLV320AIC3254 SLAS549 TAS1020B SLES025 Contents 1 EVM Overview ............................................................................................................... 3 2 EVM Description and Basics .............................................................................................. 4 3 AIC3254EVM-U Control Software ........................................................................................ 7 Appendix A TLV320AIC3254EVM Schematic ............................................................................... 15 Appendix B TLV320AIC3254EVM Bill of Materials ......................................................................... 16 Appendix C Writing Scripts ..................................................................................................... 18 List of Figures 1 TLV321AIC3254EVM-U Angle View ..................................................................................... 1 2 Bottom and Top Views ..................................................................................................... 4 3 Default Input and Output Signals ......................................................................................... 5 4 Sounds and Audio Devices Properties................................................................................... 6 5 Main Panel Window ........................................................................................................ 8 6 Compatibility Tab............................................................................................................ 9 7 Playback Configurations and Controls.................................................................................. 10 8 Associated Script and Description ...................................................................................... 10 9 Tip Strip Example.......................................................................................................... 11 10 Status Flags Panel ........................................................................................................ 12 11 Register Tables Panel .................................................................................................... 13 SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 1 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com 12 Command Line interface Panel.......................................................................................... 14 List of Tables 1 TLV320AIC3254EVM Bill of Materials .................................................................................. 16 2 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com EVM Overview 1 EVM Overview 1.1 Features • Small USB Stick form factor EVM for the TLV320AIC3254 Audio Codec. • USB connection to the PC provides power, control and streaming audio for easy evaluation. • Pre-programmed EEPROM boots the TLV320AIC3254 as a fully functional USB Audio Device when connected to a PC. • Easy to use AIC3254 Control Software (CS) configures and controls the TLV320AIC3254. The TLV320AIC3254EVM-U is a universal serial bus (USB)-based audio device for use with a personal computer running the Microsoft Windows™ XP operating system 1.2 Introduction The TLV320AIC3254EVM-U is a USB Audio Device with programmable inputs and outputs, effects and extensive routing capabilities. It is a simple platform to evaluate the TLV320AIC3254 miniDSP Audio Codec. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 3 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVM Description and Basics www.ti.com 2 EVM Description and Basics This section provides information on the analog input and output, digital control, power, and general connection of the TLV320AIC3254EVM-U. 2.1 TLV320AIC3254EVM-U Hardware Description The TLV320AIC3254EVM-U has 2 stereo analog input connectors (Line-in and Mic-in) and 2 stereo analog output connectors (Line-Out and Headphone-Out) that are routed to the TLV320AIC3254. Digital audio as well as control data communicated between the PC and the EVM are interpreted by the TAS1020B USB Streaming Controller. Control data is communicated to the TLV320AIC3254 via the I2C protocol; audio data is communicated via the I2S protocol. An on-board 32KB EEPROM is capable of storing TLV320AIC3254 commands (scripts) as well as the TAS1020B firmware. A push button is provided to cycle between scripts along with an LED that provides the user feedback regarding the script that is currently loaded. The EEPROM Manager in the AIC3254 CS is used to write new scripts into the EEPROM. Figure 2. Bottom and Top Views 4 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com EVM Description and Basics The table below summarizes the audio jacks available to connect analog inputs and outputs to the TLV320AIC3254, as well as a switch. Designator Label Associated Pin Description J1 L IN (LINE IN) IN2_L / IN2_R Line Input. External electric microphone input. J2 MIC IN (MIC IN) IN3_L / IN3_R MICBIAS is connected to both tip and ring through resistors. Line output. Only high impedance loads should J3 L OUT (LINE OUT) LOL / LOR be connected to this output (e.g. external Class-D amplifier). J4 HP OUT (HEADPHONE) HPL / HPR Headphone output. Cycles through scripts SW1 SW1 N/A loaded in the on-board EEPROM. 2.2 Getting Started Evaluation can start right out of the box. Simply connect the TLV320AIC3254EVM-U to an available USB port, connect stereo headphones to HP OUT and start playing audio with any media player. By default, when the TLV320AIC3254EVM-U is connected, the TLV320AIC3254 is automatically configured to play and record stereo audio through all four jacks, as shown below. Figure 3. Default Input and Output Signals To adjust playback volume, open “Sounds and Audio Devices” in the “Control Panel” and click the “Volume” button of the “Sound playback” section of the “Audio” tab. Ensure USB-miniEVM is selected as the default playback and recording device. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 5 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVM Description and Basics www.ti.com Figure 4. Sounds and Audio Devices Properties Pressing SW1 on the EVM once will set a flat response at the outputs (LED D1 blinks once). Pressing SW1 again will switch to bass and treble boost (LED D1 blinks twice). The following section explains the software installation procedure which allows programming of the audio device. 6 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software 3 AIC3254EVM-U Control Software The AIC3254 Control Software (CS) is an intuitive, easy-to-use, powerful tool to learn, evaluate, and control the TLV320AIC3254. This tool was specifically designed to make learning the TLV320AIC3254 software easy. The following sections describe the operation and installation of this software NOTE: For configuration of the codec, the TLV320AIC3254 block diagram located in SLAS549 is a good reference to help determine the signal routing. 3.1 AIC3254EVM-U CS Setup This section provides setup instructions for the AIC3254EVM-U CS. To install the AIC3254EVM-U software: 1. Download the latest version of the AIC3254EVM-U Control Software (CS) located in the TLV320AIC3254EVM-U Product Folder. 2. Open the self-extracting installation file. 3. Extract the software to a known folder. 4. Install the EVM software by double-clicking the Setup executable, and follow the directions. The user may be prompted to restart their computer. This installs all the AIC3254EVM-U software and required drivers onto the PC. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 7 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2 AIC3254EVM-U CS Usage The following sections describe the AIC3254EVM-U CS usage. 3.2.1 Main Panel Window The Firmware Name and Version boxes provide The Main Panel window, shown in the figure below, information about the firmware loaded into the EVM's provides easy access to all the features of the EEPROM. AIC3254 CS. The USB-MODEVM Interface drop-down menu allows the user to select which communication protocol the TAS1020B USB Controller uses to communicate with the TLV320AIC3254. The TLV320AIC3254 supports I2C Standard, I2C Fast, and 8-bit register SPI. However, this EVM only supports I2C. The USB Interface selection is global to all panels, including the Command-Line Interface. The Panel Selection Tree provides access to typical configurations, features, and other panels that allow the user to control the TLV320AIC3254. The tree is divided into several categories which contain items that pop up panels. A panel can be opened by double-clicking any item inside a category in the Panel Selection Tree. Below the Panel Selection Tree are three buttons that pop up the following: • Status Flags - Allows the user to monitor the TLV320AIC3254 status flags. • Register Tables - A tool to monitor register pages. • Command-Line Interface - A tool to execute/generate scripts and monitor register activity. The USB LED indicates if the EVM is recognized by the software and the ACTIVITY LED illuminates every time a command request is sent. The dialog box at the bottom of the Main Panel provides feedback of the current status of the software. Figure 5. Main Panel Window 8 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software If running the software in Windows Vista or Windows 7, right-click the AIC3254EVM-U CS shortcut and select Properties. Configure the Compatibility tab as shown in Figure 6 Figure 6. Compatibility Tab 3.2.2 Typical Configurations This category can help users to quickly become familiar with the TLV320AIC3254. Each of the panels that can be accessed through this menu have controls relevant to the selected configuration; a tab shows the script that will be loaded for that particular configuration. Each script includes a brief description of the selected configuration. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 9 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com Figure 7. Playback Configurations and Controls Figure 8. Associated Script and Description 3.2.3 Control Categories The Digital Settings, Analog Settings, and Signal Processing categories provide control of many registers and other features of the TLV320AIC3254 . These categories are intended for the advanced user. Hovering the mouse cursor on top of a control displays a tip strip that contains page, register, and bit information. As an example, hovering on top of IN1_R of the Audio Inputs panel, as shown in Figure 9 displays p1_r55_b7-6 which means that this control writes to Page 1/Register 55/Bits D7 to D6. 10 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software Figure 9. Tip Strip Example Before changing a control, see the data sheet to ensure that a particular control is compatible with the current state of the codec. As an example, some controls in the Analog Setup panel must be modified in a particular order as described in the data sheet. Other controls must only be modified with a specific hardware setup, such as powering up the AVDD LDO. All controls update their status with respect to the register contents in the following conditions: • A panel is opened. • The Execute Command Buffer button in the Command-Line Interface is pressed (if enabled). • The Refresh button at the bottom right of a panel is pressed SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 11 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2.4 Status Flags Panel The TLV320AIC3254 status flags can monitored in the Status Flags panel (Figure 10) which is located below in the Panel Selection Tree . Pressing the POLL button continuously reads all the registers relevant to each flag and updates those flags accordingly. The rate at which the registers are read can be modified by changing the value in the Polling Interval numeric control. Note that a smaller interval reduces responsiveness of other controls, especially volume sliders, due to bandwidth limitations. By default, the polling interval is 200 ms and can be set to a minimum of 20 ms. The Sticky Flags tab contains indicators whose corresponding register contents clear every time a read is performed to that register. To read all the sticky flags, click the Read Sticky Flags button. Figure 10. Status Flags Panel 12 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software 3.2.5 Register Tables Panel The contents of configuration and coefficient pages of the TLV320AIC3254 can be accessed through the Register Tables panel (Figure 11). The Page Number control changes to the page to be displayed in the register table. The register table contains page information such as the register name, reset value, current value, and a bitmap of the current value. The contents of the selected page can be exported into a spreadsheet by clicking the Dump to Spreadsheet button. Figure 11. Register Tables Panel SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 13 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2.6 Command-line Interface Panel The Command-Line Interface panel provides a means to communicate with the TLV320AIC3254 using a simple scripting language (described in Appendix C). The TAS1020B USB Controller handles all communication between the PC and the TLV320AIC3254. A script is loaded into the command buffer, either by loading a script file using the File menu or by pasting text from the clipboard using the Ctrl-V key combination (Figure 12). When the command buffer is executed, the return data packets which result from each individual command are displayed in the Command History control. This control is an array (with a maximum size of 100 elements) that contains information about each command as well as status. The Interface box displays the interface used for a particular command in the Command History array. The Command box displays the type of command executed (i.e., write, read) for a particular interface. The Flag Retries box displays the number of read iterations performed by a Wait for Flag command (see Appendix C for details). The Register Data array displays the register number and data bytes that correspond to a particular command. The Information tab provides additional information related to the Command History as well as additional settings. The Syntax and Examples tabs provide useful information related to the scripting language. The File menu provides some options for working with scripts. The first option, Open Script File..., loads a command file script into the command buffer. This script can then be executed by pressing the Execute Command Buffer button. The contents of the Command Buffer can be saved using the Save Script File... option. Both the Command Buffer and Command History can be cleared by clicking their corresponding Clear buttons Figure 12. Command Line interface Panel 14 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix A TLV320AIC3254EVM Schematic The schematic diagram for the TLV320AIC3254EVM is provided as a reference. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM Schematic 15 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated DOUT DIN WCLK BCLK MCLK SCLK SDA SCL RESET~ DESIGN LEAD: EDGE #: DATE: FILENAME: SCH REV: PCB REV: SHEET: OF: LEAD # DRAWN BY: PAGE INFO: TI FILENAME DATE OF BY SHEET REV REV C12 0402 0.1ufd/6.3V C16 0603 10ufd/6.3V GND TLV320AIC3254RHB U1 QFN32-RHB 25 26 27 28 29 30 31 32 6 8 4 1 2 3 5 7 16 15 14 13 12 11 10 9 21 24 22 23 19 20 18 17 C15 0805 22ufd/6.3V C11 0402 0.1ufd/6.3V GND GND GND C5 0603 0.47ufd/16V C6 0603 0.47ufd/16V GND C13 0603 .047ufd/25V C9 0603 1.0ufd/16V C14 0603 .047ufd/25V C8 0603 1.0ufd/16V GND GND GND C10 0805 22ufd/6.3V C7 0402 0.1ufd/6.3V GND GND GND C1 0603 0.47ufd/16V C2 0603 0.47ufd/16V C3 0603 10ufd/6.3V GND R4 0603 4.7K +3.3V +3.3V +3.3V J1 LEFT RIGHT Shield 2 4 1 3 6 5 J2 LEFT RIGHT Shield 2 4 1 3 6 5 J3 LEFT RIGHT Shield 2 4 1 3 6 5 J4 LEFT RIGHT Shield 2 4 1 3 6 5 C17 1210 100ufd/6.3V C18 1210 100ufd/6.3V R1 0603 1.2K R2 0603 1.2K C4 0402 0.1ufd/6.3V TLV320AIC3254RHB U1 41 40 39 38 37 36 35 34 33 QFN32-RHB GND GND GND GND GND GND GND GND GND GND C35 0603 10ufd/6.3V R3 100 0603 R5 100 0603 TLV320AIC3254_RHB_USB_EVM TLV320AIC3254_RHB_USB_EVM STEVE LEGGIO JULY 09, 2009 B B 1 4 TLV320AIC3254_RHB_USB_EVM SL LINE IN MIC IN LINE OUT HEADPHONE 6508852 SDA SCL DOUT WCLK BCLK DIN MCLK SCLK RESET~ LEAD # TI FILENAME DATE OF DRAWN BY SHEET PCB REV SCH REV BY: SHEET: OF: REV: REV: FILENAME: DATE: DESIGN LEAD: EDGE #: PAGE INFO: U2 13 14 15 17 18 19 20 22 31 30 29 27 26 25 23 24 32 34 35 36 40 39 38 37 21 8 4 28 16 33 42 41 12 11 10 9 7 6 5 45 44 43 2 1 48 3 47 46 R9 0603 1.50K C26 0603 47pfd/50v C27 0603 47pfd/50v C22 0603 1000pfd/50V 1 2 3 4 5 6 7 8 J5 TYPEA_SMT-RA NC NC CASE CASE Data+ GND +5V Data- R12 0603 100K C30 0603 1.0ufd/16V C28 0402 0.1ufd/6.3V C25 0402 0.1ufd/6.3V C29 0402 0.1ufd/6.3V C24 0402 0.1ufd/6.3V D1 0805 Yellow C23 0805 100pfd/50V C19 0402 0.1ufd/6.3V +3.3V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +5V +5V +3.3V GND GND GND GND C33 0603 0.1ufd/50V C34 0805 10ufd/16V C32 0805 10ufd/16V 1 2 3 4 Y1 SMT-8002 6MHz/3.3V Vcc OUT OE GND GND +3.3V 1 2 SW1 GND C31 0603 0.1ufd/50V R14 0603 10K +3.3V GND +5V VR1 5 3 2 1 SOT230DBV5 3.3V/400mA 4 1 2 3 4 5 6 7 8 U3 MSOP8-DGK R13 0603 649 R8 0603 30.9K R10 0603 27.4 R11 0603 27.4 R6 0603 2.7K/5% R7 0603 2.7K/5% EEPROM USB INPUT +5.0V USB INPUT +3.3V OUTPUT POWER SUPPLY TLV320AIC3254_RHB_USB_EVM SL 2 4 B B JULY 09, 2009 STEVE LEGGIO TLV320AIC3254_RHB_USB_EVM TLV320AIC3254_RHB_USB_EVM GPIO 6508852 www.ti.com Appendix B TLV320AIC3254EVM Bill of Materials The complete bill of materials for the TLV320AIC3254EVM is provided as a reference. Table 1. TLV320AIC3254EVM Bill of Materials PCB Qty Value Ref Des Description Vendor Part number 1 U1 ULTRA LO PWR ST AUDIO CODEC Texas TLV320AIC3254 W/EMBEDDED MINI DSP QFN32- Instruments RHB RHB ROHS RESISTORS Qty Value Ref Des Description Vendor Part number 1 1.5k R9 RESISTOR SMD0603 1.50K OHM DIGI-KEY P1.50KHCT 1% THICK FILM 1/10W ROHS 3 100k R3,R5,R12 RESISTOR SMD0603 100K OHM 1% DIGI-KEY P100KHCT THICK FILM 1/10W ROHS 1 1.7k R4 RESISTOR SMD0603 4.7K OHMS DIGI-KEY P4.7KGCT 1% 1/10W ROHS 1 10k R14 RESISTOR SMD0603 10K 5% 1/10W DIGI-KEY P10KGCT ROHS 2 1.2k R1,R2 RESISTOR SMD0603 1.2K OHMS DIGI-KEY P1.2KGCT 5% 1/10W ROHS 1 649 R13 RESISTOR SMD0603 THICK FILM DIGI-KEY 311-649HRCT 649 OHMS 1% 1/10W ROHS 1 30.9k R8 RESISTOR SMD0603 30.9K OHMS 541-30.9KHCT 1% 1/10W ROHS 2 27.4k R10,R11 RESISTOR SMD0603 27.4 OHMS DIGI-KEY P27.4HCT 1% 1/10W ROHS 2 2.7k R6,R7 RESISTOR SMD0603 2.7K OHMS DIGI-KEY P2.7KGCT 5% 1/10W ROHS 2 100 R3,R5 RESISTOR SMD0603 100 OHM DIGI-KEY 541-100HCT 1/10W 1% ROHS CAPACITORS Qty Value Ref Des Description Vendor Part number 9 0.1μF C4,C7,C11,C12,C19,C24,C25,C28,C29 CAP SMD0402 CERM 0.1UFD 6.3V DIGI-KEY 445-1266-1 10% X5R ROHS 3 10μF C3,C16, C35 CAP SMD0603 CERM 10UFD 6.3V DIGI-KEY PCC2395CT 20% X5R ROHS 2 22μF C10,C15 CAP SMD0805 CERM 22UFD 6.3V DIGI-KEY 445-1422-1 20% X5R ROHS 2 47pF C26,C27 CAP SMD0603 CERM 47PFD 50V DIGI-KEY PCC470ACVCT 5% NPO ROHS 1 1000pF C22 CAP SMD0603 CERM 1000PFD 50V DIGI-KEY 445-1293-1 5% COG ROHS 1 1μF C30 CAP SMD0603 CERM 1.0UFD 16V DIGI-KEY 445-1604-1 5% X7R ROHS 4 0.47μF C1,C2,C5,C6 CAP SMD0603 CERM 0.47UFD 16V DIGI-KEY 478-1248-1 10% X5R ROHS 2 0.47μF C13,C14 CAP SMD0603 CERM 0.47UFD 25V DIGI-KEY PCC1771CT 10% X7R ROHS 2 1μF C8,C9 CAP SMD0603 CERM 1.0UFD 16V DIGI-KEY PCC2224CT 10% X5R ROHS 1 100pF C23 CAP SMD0805 CERM 100PFD 50V DIGI-KEY 490-1615-1 5% C0G ROHS 2 0.1μF C31,C33 CAP SMD0603 CERM 0.1UFD 50V DIGI-KEY 445-1314-1 10% X7R ROHS 16 TLV320AIC3254EVM Bill of Materials SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix B Table 1. TLV320AIC3254EVM Bill of Materials (continued) 2 10μF C32,C34 CAP SMD0805 CERM 10UFD 16V DIGI-KEY 490-3886-1 10% X5R ROHS 2 100μF C17,C18 CAP SMD1210 CERM 100UFD 6.3V DIGI-KEY 490-3390-1 20% X5R ROHS INTEGRATED CIRCUITS Qty Value Ref Des Description Vendor Part number 1 U2 USB STREAMING CONTROLLER DIGI-KEY 296-13041-5 TQFP48-PFB ROHS 1 VR1 VOLT REG 3.3V 400MA LDO CAP- DIGI-KEY 296-15819-1 FREE NMOS SOT23-DBV5 ROHS 1 U3 256K I2C SERIAL EEPROM,MSOP-8 DIGI-KEY 24AA256-I/MSND 1 D1 LED, YELLOW 2.0V SMD0805 DIGI-KEY 67-1554-1 ROHS 1 Y1 OSCILLATOR SMT 6MHz 3.3V OUT- DIGI-KEY 788- ENABLE ROHS 8002AI133E- 6.0T MISCELLANEOUS ITEMS Qty Value Ref Des Description Vendor Part number 1 J5 JACK-USB MALE TYPEA SMT-RA DIGI-KEY WM17118 4PIN ROHS J 4 J1,J2,J3,J4 ACK AUDIO MINI(3.5MM ,4-COND DIGI-KEY CP-43516SJCT PCB-RA ROHS 1 SW1 SWITCH, MOM, 160G SMT 4X3MM DIGI-KEY EG4344CT ROHS ATTENTION: All components must be Rhos compliant. Some part numbers may be either leaded or Rhos. Verify that purchased components are Rhos compliant. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM Bill of Materials 17 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix C Writing Scripts A script is simply a text file that contains data to send to the serial control buses. Each line in a script file is one command. No provision is made for extending lines beyond one line, except for the > command. A line is terminated by a carriage return. The first character of a line is the command. Commands are: I Set interface bus to use r Read from the serial control bus w Write to the serial control bus > Extend repeated write commands to lines below a w # Comment b Break d Delay f Wait for Flag The first command, I, sets the interface to use for the commands to follow. This command must be followed by one of the following parameters: i2cstd Standard mode I2C bus i2cfast Fast mode I2C bus spi8 SPI bus with 8-bit register addressing spi16 SPI bus with 16-bit register addressing For example, if a fast mode I2C bus is to be used, the script begins with: I i2cfast A double quoted string of characters following the b command can be added to provide information to the user about each breakpoint. When the script is executed, the software's command handler halts as soon as a breakpoint is detected and displays the string of characters within the double quotes. The Wait for Flag command, f, reads a specified register and verifies if the bitmap provided with the command matches the data being read. If the data does not match, the command handler retries for up to 200 times. This feature is useful when switching buffers in parts that support the adaptive filtering mode. The command f syntax follows: f [i2c address] [register] [D7][D6][D5][D4][D3][D2][D1][D0] where 'i2c address' and 'register' are in hexadecimal format and 'D7' through 'D0' are in binary format with values of 0, 1 or X for don't care. Anything following a comment command # is ignored by the parser, provided that it is on the same line. The delay command d allows the user to specify a time, in milliseconds, that the script pauses before proceeding. The delay time is entered in decimal format. A series of byte values follows either a read or write command. Each byte value is expressed in hexadecimal, and each byte must be separated by a space. Commands are interpreted and sent to the TAS1020B by the program. The first byte following an r (read) or w (write) command is the I2C slave address of the device (if I2C is used) or the first data byte to write (if SPI is usednote that SPI interfaces are not standardized on protocols, so the meaning of this byte varies with the device being addressed on the SPI bus). The second byte is the starting register address that data will be written to (again, with I2C; SPI varies. Following these two bytes are data, if writing; if reading, the third byte value is the number of bytes to read, (expressed in hexadecimal). 18 Writing Scripts SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix C For example, to write the values 0xAA 0x55 to an I2C device with a slave address of 0x30, starting at a register address of 0x03, the user writes: #example script I i2cfast w 30 03 AA 55 r 30 03 02 This script begins with a comment, specifies that a fast I2C bus will be used, then writes 0xAA 0x55 to the I2C slave device at address 0x30, writing the values into registers 0x03 and 0x04. The script then reads back two bytes from the same device starting at register address 0x03. Note that the slave device value does not change. It is unnecessary to set the R/W bit for I2C devices in the script; the read or write commands does that. If extensive repeated write commands are sent and commenting is desired for a group of bytes, the > command can be used to extend the bytes to other lines that follow. A usage example for the > command follows: #example script for '>' command I i2cfast # Write AA and BB to registers 3 and 4, respectively w 30 03 AA BB # Write CC, DD, EE and FF to registers 5, 6, 7 and 8, respectively > CC DD EE FF # Place a commented breakpoint b "AA BB CC DD EE FF was written, starting at register 3" # Read back all six registers, starting at register 3 r 30 03 06 The following example demonstrates usage of the Wait for Flag command, f: #example script for 'wait for flag' command I i2cfast # Switch to Page 44 w 30 00 2C # Switch buffers w 30 01 05 # Wait for bit D0 to clear. 'x' denotes a don't care. f 30 01 xxxxxxx0 Any text editor can be used to write these scripts; Jedit is an editor that is highly recommended for general usage. For more information, go to: http://www.jedit.org. Once the script is written, it can be used in the command window by running the program, and then selecting Open Script File... from the File menu. Locate the script and open it. The script is then displayed in the command buffer. The user can also edit the script once it is in the buffer and save it by selecting Save Script File... from the File menu. SLAU295A–September 2009–Revised October 2012 Writing Scripts 19 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Appendix C www.ti.com Once the script is in the command buffer, it can be executed by pressing the Execute Command Buffer button. If there are breakpoints in the script, the script executes to that point, and the user is presented with a dialog box with a button to press to continue executing the script. When ready to proceed, push that button and the script continues. 20 Writing Scripts SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated SLLS025A − JULY 1986 Copyright 1986, Texas Instruments Incorporated Revision Information POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 • Dual Circuits Capable of Driving High-Capacitance Loads at High Speeds • Output Supply Voltage Range up to 24 V • Low Standby Power Dissipation description The SN75372 is a dual NAND gate interface circuit designed to drive power MOSFETs from TTL inputs. It provides high current and voltage levels necessary to drive large capacitive loads at high speeds. The device operates from a VCC1 of 5 V and a VCC2 of up to 24 V. The SN75372 is characterized for operation from 0°C to 70°C. schematic (each driver) VCC1 VCC2 To Other Driver To Other Driver Output Y GND Input A Enable E 1Y 7 2Y 6 E 2 EN 1A 1 2A 3 logic symbol† TTL/MOS 1 2 3 4 8 7 6 5 1A E 2A GND VCC1 1Y 2Y VCC2 D OR P PACKAGE (TOP VIEW) † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. !"# $"%&! ' #( '"! ! $#!! $# )# # #* " # ' ' + ,( '"! $!# - '# #!# &, !&"'# # - && $ # # ( SLLS025A − JULY 1986 3−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 25 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Peak output current, VO (tw < 10 ms, duty cycle < 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to network GND. DISSIPATION RATING TABLE PACKAGE TA = 25°C DERATING FACTOR TA = 70°C 25 POWER RATING ABOVE TA = 25°C 70 POWER RATING D 725 mW 5.8 mW/°C 464 mW P 1000 mW 8.0 mW/°C 640 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC1 4.75 5 5.25 V Supply voltage, VCC2 4.75 20 24 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High-level output current, IOH −10 mA Low-level output current, IOL 40 mA Operating free-air temperature, TA 0 70 °C SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of VCC1, VCC2, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = − 12 mA −1.5 V VOH High-level output voltage VIL = 0.8 V, IOH = −50 μA VCC2−1.3 VCC2−0.8 V VIL = 0.8 V, IOH = − 10 mA VCC2−2.5 VCC2−1.8 VIH = 2 V, IOL = 10 mA 0.15 0.3 VOL Low-level output voltage VCC2 = 15 V to 24 V, IOL = 40 mA VIH = 2 V, 0.25 0.5 V VF Output clamp-diode forward voltage VI = 0, IF = 20 mA 1.5 V II Input current at maximum input VI = 5.5 V 1 mA voltage IIH High-level input current Any A VI = 2.4 V 40 A Any E 80 μA IIL Low-level input current Any A VI = 0.4 V −1 −1.6 mA Any E −2 −3.2 ICC1(H) Supply current from VCC1, both outputs high 2 4 mA ICC2(H) Supply current from VCC2, both outputs high VCC1 = 5.25 V, All inputs at 0 V, VCC2 = 24 V, No load 0.5 mA ICC1(L) Supply current from VCC1, both outputs low 16 24 mA ICC2(L) Supply current from VCC2, both outputs low VCC1 = 5.25 V, All inputs at 5 V, VCC2 = 24 V, No load 7 13 mA ICC2(S) Supply current from VCC2, standby condition VCC1 = 0, All inputs at 5 V, VCC2 = 24 V, No load 0.5 mA † All typical values are at VCC1 = 5 V, VCC2 = 20 V, and TA = 25°C. switching characteristics, VCC1 = 5 V, VCC2 = 20 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDLH Delay time, low-to-high-level output 20 35 ns tDHL Delay time, high-to-low-level output 10 20 ns tTLH Transition time, low-to-high-level output CL = 390 pF, RD = 10 Ω, See Figure 1 20 30 ns tTHL Transition time, high-to-low-level output 20 30 ns tPLH Propagation delay time, low-to-high-level output 10 40 65 ns tPHL Propagation delay time, high-to-low-level output 10 30 50 ns SLLS025A − JULY 1986 3−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION 10% 5 V 2.4 V VCC1 TEST CIRCUIT Input GND VCC2 Pulse Generator (see Note A) Output CL = 390 pF (see Note B) 20 V RD Input Output VOLTAGE WAVEFORMS ≤ 10 ns 90% 1.5 V 0.5 μs tDHL tTLH VCC2−3 V 2 V 0 V VOH ≤ 10 ns 90% 1.5 V 10% tPHL tPHL tDLH tTHL VCC2−3 V 2 V VOL 3 V NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms, Each Driver TYPICAL CHARACTERISTICS −1 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT −10 −100 0.3 0.2 0.1 0 0 20 40 60 0.4 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.5 80 100 VCC2−0.5 VCC2−1 VCC2−1.5 VCC2−2 VCC2−2.5 VCC2−3 VCC1 = 5 V VCC2 = 20 V VI = 0.8 V TA = 25°C TA = 70°C TA = 0°C VVO0HH − High-Level Output Voltage − V IOL − Low-Level Output Current − mA VCC1 = 5 V VCC2 = 20 V VI = 2 V TA = 70°C TA = 0°C VVOOLL − Low-Level Output Voltage − V IOH − High-Level Output Current − mA VCC2 − 0.01 − 0.1 Figure 2 Figure 3 SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS 10 20 40 100 400 1000 f − Frequency − kHz POWER DISSIPATION (BOTH DRIVERS) vs FREQUENCY 200 400 200 0 800 1000 1200 12 600 8 4 0 0 0.5 1 1.5 16 20 VOLTAGE TRANSFER CHARACTERISTICS 24 2 2.5 VI − Input Voltage − V VVO) − Output Voltage − V VCC1 = 5 V VCC2 = 20 V No Load TA = 25°C VCC1 = 5 V VCC2 = 20 V Input: 3-V Square Wave 50% Duty Cycle TA = 25°C CL = 600 pF CL = 1000 pF CL = 2000 pF CL = 4000 pF CL = 400 pF PPDT − Power Dissipation − mW Allowable in P Package Only Figure 4 Figure 5 PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs FREE-AIR TEMPERATURE PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs FREE-AIR TEMPERATURE 100 80 20 0 0 10 20 30 40 50 60 High-to-Low-Level Output − ns 140 180 200 70 80 60 160 120 40 TA − Free-Air Temperature − °C tkPSLVHR − Propagation Delay Time, Low-to-High-Level Output − ns ktSPVHRL − Propagation Delay Time, TA − Free-Air Temperature − °C 100 80 20 0 140 180 200 60 160 120 40 0 10 20 30 40 50 60 70 80 CL = 50 pF CL = 200 pF CL = 1000 pF CL = 2000 pF CL = 4000 pF VCC1 = 5 V VCC2 = 20 V RD = 10 Ω See Figure 1 CL = 4000 pF CL = 2000 pF CL = 1000 pF VCC1 = 5 V VCC2 = 20 V RD = 10 Ω See Figure 1 CL = 200 pF CL = 390 pF CL = 50 pF CL = 390 pF Figure 6 Figure 7 SLLS025A − JULY 1986 3−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS 0 5 10 15 PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs VCC2 SUPPLY VOLTAGE 20 25 100 80 20 0 140 180 200 60 160 120 40 Low-to-High-Level Output − ns VCC2 − Supply Voltage − V PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs VCC2 SUPPLY VOLTAGE 100 80 20 0 140 180 200 60 160 120 40 0 5 10 15 20 25 VCC2 − Supply Voltage − V tPLH − Propagation Delay Time, VCC1 = 5 V RD = 10 Ω TA = 25°C See Figure 1 CL = 2000 pF CL = 1000 pF CL = 200 pF CL = 390 pF CL = 50 pF VCC1 = 5 V RD = 10 Ω TA = 25°C See Figure 1 CL = 4000 pF CL = 2000 pF CL = 1000 pF CL = 390 pF CL = 200 pF CL = 50 pF CL = 4000 pF High-to-Low-Level Output − ns tPLH − Propagation Delay Time, Figure 8 Figure 9 0 1000 2000 3000 4000 VCC1 = 5 V VCC2 = 20 V TA = 25°C See Figure 1 Low-to-High-Level Output − ns 100 80 20 0 140 180 200 60 160 120 40 PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs LOAD CAPACITANCE CL − Load Capacitance − pF RD = 10 Ω RD = 0 RD = 24 Ω 100 80 20 0 140 180 200 60 160 120 40 0 1000 2000 3000 4000 CL − Load Capacitance − pF VCC1 = 5 V VCC2 = 20 V TA = 25°C See Figure 1 RD = 24 Ω RD = 10 Ω PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs LOAD CAPACITANCE RD = 0 ktSPVLRH − Propagation Delay Time, High-to-Low-Level Output − ns ktSPVLRH − Propagation Delay Time, Figure 10 Figure 11 NOTE: For RD = 0, operation with CL > 2000 pF violates absolute maximum current rating. SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 THERMAL INFORMATION power dissipation precautions Significant power may be dissipated in the SN75372 driver when charging and discharging high-capacitance loads over a wide voltage range at high frequencies. Figure 5 shows the power dissipated in a typical SN75372 as a function of load capacitance and frequency. Average power dissipated by this driver is derived from the equation PT(AV) = PDC(AV) + PC(AV) = PS(AV) where PDC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power level during charging or discharging of the load capacitance, and PS(AV) is the power dissipation during switching between the low and high levels. None of these include energy transferred to the load, and all are averaged over a full cycle. The power components per driver channel are PC(AV) C V2 C f tHL tLH tH tL T = 1/f where the times are as defined in Figure 14. Figure 12. Output Voltage Waveform PDC(AV) = PHtH + PLtL T PS(AV) = PLHtLH + PHLtHL T PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance. VC is the voltage across the load capacitance during the charge cycle shown by the equation VC = VOH − VOL PS(AV) may be ignored for power calculations at low frequencies. In the following power calculation, both channels are operating under identical conditions: VOH =19.2 V and VOL = 0.15 V with VCC1 = 5 V, VCC2 = 20 V, VC = 19.05 V, C = 1000 pF, and the duty cycle = 60%. At 0.5 MHz, PS(AV) is negligible and can be ignored. When the output voltage is high, ICC2 is negligible and can be ignored. On a per-channel basis using data sheet values, PDC(AV) (5 V) 2 mA 2 (20 V) 0 mA 2 (0.6)(5 V) 16 mA 2 (20 V) 7 mA 2 (0.4) PDC(AV) = 47 mW per channel Power during the charging time of the load capacitance is PC(AV) = (1000 pF) (19.05 V)2 (0.5 MHz) = 182 mW per channel Total power for each driver is PT(AV) = 47 mW + 182 mW = 229 mW and total package power is PT(AV) = (229) (2) = 458 mW. SLLS025A − JULY 1986 3−8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 APPLICATION INFORMATION driving power MOSFETs The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The input impedance of a FET consists of a reverse biased PN junction that can be described as a large capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver with a pullup resistor is not satisfactory for high-speed applications. In Figure 12(a), an IRF151 power MOSFET switching an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input capacitance (Ciss) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time due to the combination of Ciss and the pullup resistor is shown in Figure 12(b). 5 V 7 4 8 3 5 2 1 6 VVO0HH − − Gate Voltage − V TLC555P 1/2 SN75447 470 Ω 48 V M VOL t − Time − μs (b) (a) IRF151 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 Figure 13. Power MOSFET Drive Using SN75447 SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 APPLICATION INFORMATION A faster, more efficient drive circuit uses an active pullup as well as an active pulldown output configuration, referred to as a totem-pole output. The SN75372 driver provides the high speed, totem-pole drive desired in an application of this type, see Figure 13(a). The resulting faster switching speeds are shown in Figure 13(b). 5 V TLC555P 1/2 SN75372 M t − Time − μs (b) (a) IRF151 48 V 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 VVO0HH − VVOOLL − Gate Voltage − V 7 4 8 3 5 2 1 6 Figure 14. Power MOSFET Drive Using SN75372 Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as shown by the equation Ipk VC tr where C is the capacitive load, and tr is the desired drive time. V is the voltage that the capacitance is charged to. In the circuit shown in Figure 13(a), V is found by the equation V = VOH − VOL Peak current required to maintain a rise time of 100 ns in the circuit of Figure 13(a) is IPK (30)4(109) 100(109) 120 mA Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151. With a VCC of 5 V, and assuming worst-cast conditions, the gate drive voltage is 3 V. For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, the SN75374 quad MOSFET driver should be used. PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN75372D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office SN75372PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office SN75372PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2010 Addendum-Page 2 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN75372DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN75372PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75372DR SOIC D 8 2500 340.5 338.1 20.6 SN75372PSR SO PS 8 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 Meets IEEE Standard 488-1978 (GPIB) 8-Channel Bidirectional Transceivers Power-Up/Power-Down Protection (Glitch Free) Designed to Implement Control Bus Interface SN75161B Designed for Single Controller SN75162B Designed for Multiple Controllers High-Speed, Low-Power Schottky Circuitry Low Power Dissipation . . . 72 mW Max Per Channel Fast Propagation Times . . . 22 ns Max High-Impedance pnp Inputs Receiver Hysteresis . . . 650 mV Typ Bus-Terminating Resistors Provided on Driver Outputs No Loading of Bus When Device Is Powered Down (VCC = 0) description The SN75161B and SN75162B eight-channel, general-purpose interface bus transceivers are monolithic, high-speed, low-power Schottky devices designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a single- or multiple-controller instrumentation system. When combined with the SN75160B octal bus transceiver, the SN75161B or SN75162B provides the complete 16-wire interface for the IEEE-488 bus. The SN75161B and SN75162B feature eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. A powerup/- down disable circuit is included on all bus and receiver outputs. This provides glitch-free operation during VCC power up and power down. PRODUCTION DATA information is current as of publication date. Copyright W 1995, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SC TE REN IFC NDAC NRFD DAV EOI ATN SRQ NC GND 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC NC REN IFC NDAC NRFD DAV EOI ATN SRQ NC DC (TOP VIEW) TE REN IFC NDAC NRFD DAV EOI ATN SRQ GND VCC REN IFC NDAC NRFD DAV EOI ATN SRQ DC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GPIB I/O Ports Terminal I/O Ports (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SC TE REN IFC NDAC NRFD DAV EOI ATN SRQ GND VCC NC REN IFC NDAC NRFD DAV EOI ATN SRQ DC (TOP VIEW) NC–No internal connection SN75161B . . . DW OR N PACKAGE SN75162B . . . DW PACKAGE SN75162B . . . N PACKAGE GPIB I/O Ports Terminal I/O Ports GPIB I/O Ports Terminal I/O Ports SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC (on SN75162B) enable signals. The SC input on the SN75162B allows the REN and IFC transceivers to be controlled independently. The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage VCC is 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal when disabled. The SN75161B and SN75162B are characterized for operation from 0°C to 70°C. Function Tables SN75161B RECEIVE/TRANSMIT CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS DC TE ATN† ATN† SRQ REN IFC EOI DAV NDAC NRFD (Controlled by DC) (Controlled by TE) H H H R T R R T T R R H H L R L L H T R T T R R T T L L L T H L X R T R R R R T T L H X T R T T T T R R H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. † ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. SN75162B RECEIVE/TRANSMIT CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS SC DC TE ATN† ATN† SRQ REN IFC EOI DAV NDAC NRFD (Controlled by DC) (Controlled by SC) (Controlled by TE) H H H R T T T R R H H L R L L H T R R R T T L L L T H L X R T R R T T L H X T R T T R R H T T L R R H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. † ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CHANNEL-IDENTIFICATION TABLE NAME IDENTITY CLASS DC Direction Control TE Talk Enable Control SC System Control (SN75162B only) ATN Attention SRQ Service Request REN Remote Enable Bus IFC Interface Clear Management EOI End of Identity DAV Data Valid NDAC Not Data Accepted Data NRFD Not Ready for Data Transfer SN75161B logic symbol† EN3 1 ATN 8 1 ATN 13 1 1 EOI 7 3 EOI 14 1 3 SRQ 1 SRQ 12 1 1 REN 2 1 REN 19 1 1 IFC 3 1 IFC 18 1 1 DAV 6 2 DAV 15 1 2 NDAC 4 2 NDAC 17 1 2 2 1 16 NRFD 2 EN1/G4 EN2/G5 5 4 5 NRFD TE 1 DC 11 This symbol is in accordance with IEEE Std 91-1984 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs 9 SN75161B logic diagram (positive logic) NRFD 5 NRFD 16 NDAC 4 NDAC 17 DAV 6 DAV 15 IFC 3 IFC 18 REN 2 REN 19 SRQ 9 SRQ 12 EOI 7 EOI 14 11 DC 1 TE 13 ATN 8 ATN SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75162B logic symbol† EN3 . 1 ATN 1 ATN 14 1 1 EOI 6 EOI 1 6 SRQ 1 SRQ 1 1 REN REN 1 3 IFC IFC 1 DAV 2 DAV 1 2 NDAC 2 NDAC 1 2 2 1 NRFD 2 EN1/G4 EN2/G5 5 4 NRFD TE DC This symbol is in accordance with IEEE Std 91-1984 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs EN3 12 2 1 15 SC 13 20 19 16 18 17 9 8 10 3 4 7 5 6 3 3 3 Pin numbers shown are for the N package. SN75162B logic diagram (positive logic) NRFD NRFD NDAC NDAC DAV DAV IFC IFC REN REN SRQ SRQ EOI EOI DC TE ATN ATN 12 2 1 14 15 13 20 19 16 18 17 9 8 10 3 4 7 5 6 SC SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 schematics of inputs and outputs NOM 4 kW R(eq) 1.7 kW NOM 10 kW NOM VCC GND Input/Output Port Input/Output Port GND VCC NOM 10 kW NOM 4 kW NOM 1.7 kW NOM 9 kW GND Input VCC NOM 4 kW EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT Circuit inside dashed lines is on the driver outputs only. TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC, AND NRFD GPIB I/O PORTS Driver output R(eq) = 30 W NOM Receiver output R(eq) = 110 W NOM Circuit inside dashed lines is on the driver outputs only. R(eq) = equivalent resistor absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Low-level driver output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DISSIPATION RATING TABLE PACKAGE TA 3 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING DW (20 pin) 1125 mW 9.0 mW/°C 720 mW DW (24 pin) 1350 mW 10.8 mW/°C 864 mW N (20 pin) 1150 mW 9.2 mW/°C 736 mW N (22 pin) 1700 mW 13.6 mW/°C 1088 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High level output current IOH Bus ports with 3-state outputs –5.2 mA High-current, Terminal ports –800 mA Low level output current IOL Bus ports 48 Low-current, mA Terminal ports 16 Operating free-air temperature, TA 0 70 °C SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = – 18 mA –0.8 –1.5 V Vhys Hysteresis voltage (VIT+ – VIT–) Bus See Figure 7 0.4 0.65 V VOH‡ High level output voltage Terminal IOH = – 800 mA 2.7 3.5 High-V Bus IOH = – 5.2 mA 2.5 3.3 VOL Low level output voltage Terminal IOL = 16 mA 0.3 0.5 Low-V Bus IOL = 48 mA 0.35 0.5 II Input current at maximum Terminal VI = 5 5 V 0 2 100 mA input voltage 5.5 0.2 IIH High-level input current Terminal and VI = 2.7 V 0.1 20 mA IIL Low-level input current control inputs VI = 0.5 V –10 –100 mA VI/O(b ) Voltage at bus port Driver disabled II(bus) = 0 2.5 3.0 3.7 bus) V II(bus) = – 12 mA –1.5 VI(bus) = – 1.5 V to 0.4 V –1.3 VI(bus) = 0.4 V to 2.5 V 0 –3.2 Power on Driver disabled VI(b ) = 2 5 V to 3 7 V 2.5 mA II/O(bus) Current into bus port bus) 2.5 3.7 –3.2 ( ) VI(bus) = 3.7 V to 5 V 0 2.5 VI(bus) = 5 V to 5.5 V 0.7 2.5 Power off VCC = 0, VI(bus) = 0 V to 2.5 V –40 mA IOS Short circuit output current Terminal –15 –35 –75 Short-mA Bus –25 –50 –125 ICC Supply current No load, TE, DE, and SC low 110 mA CI/O(b ) Bus port capacitance VCC = 5 V to 0, bus) Bus-CC 16 pF VI/O = 0 to 2 V, f = 1 MHz † All typical values are at VCC = 5 V, TA = 25°C. ‡ VOH applies for 3-state outputs only. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output Terminal Bus CL = 30 pF, 14 20 ns tPHL Propagation delay time, high- to low-level output L See Figure 1 14 20 tPLH Propagation delay time, low- to high-level output Terminal Bus (SRQ,NDAC, NRFD) CL = 30 pF, See Figure 1 29 35 ns tPLH Propagation delay time, low- to high-level output Bus Terminal CL = 30 pF, 10 20 ns tPHL Propagation delay time, high- to low-level output L See Figure 2 15 22 tPZH Output enable time to high level Bus (ATN 60 tPHZ Output disable time from high level TE,DC, ATN, EOI, REN, See Figure 3 45 ns tPZL Output enable time to low level or SC , , IFC, and 60 tPLZ Output disable time from low level DAV) 55 tPZH Output enable time to high level 55 tPHZ Output disable time from high level TE,DC, Terminal See Figure 4 50 ns tPZL Output enable time to low level or SC 45 tPLZ Output disable time from low level 55 SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION VOLTAGE WAVEFORMS LOAD CIRCUIT 480 W 200 W (see Note A) CL = 30 pF Test Point 5 V Output Bus Input Terminal See Note B VOH VOH 0 V 3 V tPHL 2.2 V 1.0 V 1.5 V tPLH 1.5 V From (Bus) Output Under Test NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms See Note B 1.5 V tPLH 1.5 V 1.5 V 1.5 V tPHL 3 V 0 V VOH VOL Bus Input Output From (Terminal) Output Under Test 4.3 V Test Point CL = 30 pF (see Note A) 240 W 3 kW LOAD CIRCUIT VOLTAGE WAVEFORMS Terminal NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. S1 Open tPHZ 1.5 V 3 V 0 V S1 Closed 1 V 3.5 V VOL Input Control See Note B 1.5 V tPZH S1 VOLTAGE WAVEFORMS 2 V tPZL 90% 0.5 V tPLZ VOH 0 V Bus Output Bus Output 5 V Test Point CL = 15 pF (see Note A) 200 W 480 W LOAD CIRCUIT From (Bus) Output Under Test Figure 3. Bus Enable and Disable Times Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PARAMETER MEASUREMENT INFORMATION Output 90% Terminal S1 Open S1 Closed Terminal tPHZ VOLTAGE WAVEFORMS Output 0 V VOH tPLZ 0.7 V tPZL 1.5 V tPZH 1.5 V See Note B Control Input VOL 4 V 1 V 0 V 3 V 1.5 V LOAD CIRCUIT 3 kW 240 W Test Point S1 4.3 V CL = 15 pF (see Note A) From (Terminal) Output Under Test NOTES: A. CL includes probe and jig capacitance. B. The Input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 4. Terminal Enable and Disable Times Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS VOH – High-Level Output Voltage – V TERMINAL I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 3 2.5 2 1.5 1 0.5 –5 –10 –15 –20 –25 –30 –35 0 –40 4 0 TA = 25°C VCC = 5 V IOH – High-Level Output Current – mA Figure 5 IOL – Low-Level Output Current – mA – Low-Level Output Voltage – V TERMINAL I/O PORTS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 0 60 0.6 0 VOL Figure 6 2 – Output Voltage – V TERMINAL I/O PORTS OUTPUT VOLTAGE vs BUS INPUT VOLTAGE VIT– TA = 25°C No Load VCC = 5 V 3.5 3 2.5 2 1.5 1 0.5 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 4 VI – Bus Input Voltage – V 0 VO VIT+ Figure 7 SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TYPICAL CHARACTERISTICS IOH – High-Level Output Current – mA – High-Level Output Voltage – V GPIB I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 3 2 1 –10 –20 –40 –30 –50 0 –60 0 0 VOH Figure 8 IOL – Low-Level Output Current – mA – Low-Level Output Voltage – V GPIB I/O PORTS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 60 70 80 90 0 100 0.6 0 VOL Figure 9 Figure 10 VI – Input Voltage – V VO – Output Voltage – V GPIB I/O PORTS OUTPUT VOLTAGE vs THERMAL INPUT VOLTAGE TA = 25°C No Load VCC = 5 V 3 2 1 1 1.1 1.2 1.3 1.4 1.5 1.6 0 4 0.9 1.7 – Current – mA GPIB I/O PORTS CURRENT vs VOLTAGE 2 1 0 –1 –2 –3 –6 –1 0 1 2 3 4 5 –7 6 VI/O – Voltage – V –2 TA = 25°C VCC = 5 V ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ The Unshaded Area Conforms to Paragraph 3.5.3 of IEEE Standard 488-1978 II/O –5 –4 Figure 11 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) SN75161BDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75161BNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75162BDW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BN OBSOLETE PDIP N 22 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 2 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN75161BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN75161BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1 SN75162BDWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2011 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75161BDWR SOIC DW 20 2000 346.0 346.0 41.0 SN75161BDWR SOIC DW 20 2000 346.0 346.0 41.0 SN75162BDWR SOIC DW 24 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2011 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated 6 O 6 (1.8639 V 2.1962 10 3.88 10 ) T 1481.96 u u GND NC V+ VO LMT88 LMT88 www.ti.com SNIS175 –MARCH 2013 LMT88 2.4V, 10μA, SC70, DSBGA Temperature Sensor Check for Samples: LMT88 1FEATURES DESCRIPTION The LMT88 is a precision analog output CMOS 2• Cost-Effective Alternative to Thermistors integrated-circuit temperature sensor that operates • Rated for full −55°C to +130°C range over a −55°C to 130°C temperature range. The • Available in an SC70 Package power supply operating range is 2.4 V to 5.5 V. The • Predictable Curvature Error transfer function of LMT88 is predominately linear, yet • Suitable for Remote Applications has a slight predictable parabolic curvature. The accuracy of the LMT88 when specified to a parabolic transfer function is ±1.5°C at an ambient temperature APPLICATIONS of 30°C. The temperature error increases linearly and • Industrial reaches a maximum of ±2.5°C at the temperature • HVAC range extremes. The temperature range is affected by the power supply voltage. At a power supply • Disk Drives voltage of 2.7 V to 5.5 V the temperature range • Automotive extremes are 130°C and −55°C. Decreasing the • Portable Medical Instruments power supply voltage to 2.4 V changes the negative extreme to −30°C, while the positive remains at • Computers 130°C. • Battery Management The LMT88 quiescent current is less than 10 μA. • Printers Therefore, self-heating is less than 0.02°C in still air. • Power Supply Modules Shutdown capability for the LMT88 is intrinsic • FAX Machines because its inherent low power consumption allows it to be powered directly from the output of many logic • Mobile Phones gates or does not necessitate shutdown at all. • Automotive The LMT88 is a cost-competitive alternative to thermistors. TYPICAL APPLICATION Full-Range Celsius (Centigrade) Temperature Sensor (−55°C TO 130°C) Operating From a Single LI-Ion Battery Cell space space VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 space where: T is temperature, and VO is the measured output voltage of the LMT88. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LMT88 GND NC V+ VO 1 4 3 5 GND 2 LMT88 SNIS175 –MARCH 2013 www.ti.com Figure 1. Output Voltage vs Temperature Table 1. Output Voltage vs Temperature TEMPERATURE (T) TYPICAL VO 130°C 303 mV 100°C 675 mV 80°C 919 mV 30°C 1515 mV 25°C 1574 mV 0°C 1863.9 mV –30°C 2205 mV −40°C 2318 mV −55°C 2485 mV CONNECTION DIAGRAMS GND (pin 2) may be grounded or left floating. For optimum thermal conductivity to the pc board ground plane, pin 2 must be grounded. NC (pin 1) must be left floating or grounded. Other signal traces must not be connected to this pin. Figure 2. SC70-5 Top View 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 LMT88 www.ti.com SNIS175 –MARCH 2013 ABSOLUTE MAXIMUM RATINGS(1) VALUES Supply Voltage 6.5V to −0.2V Output Voltage (V+ + 0.6 V) to −0.6 V Output Current 10 mA Input Current at any pin (2) 5 mA Storage Temperature −65°C to 150°C Maximum Junction Temperature (TJMAX) 150°C Human Body Model 2500 V ESD Susceptibility (3) Machine Model 250 V Soldering process must comply with the Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(4) (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For specified specifications and test conditions, see the ELECTRICAL CHARACTERISTICS. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V+), the current at that pin should be limited to 5 mA. (3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. (4) Reflow temperature profiles are different for lead-free and non-lead-free packages. OPERATION RATINGS Specified Temperature Range: TMIN ≤ TA ≤ TMAX LMT88 with 2.4 V ≤ V+≤ 2.7 V −30°C ≤ TA ≤ 130°C LMT88 with 2.7 V ≤ V+≤ 5.5 V −55°C ≤ TA ≤ 130°C Supply Voltage Range (V+) 2.4 V to 5.5 V Thermal Resistance, θJA (1) SC70 415°C/W (1) The junction to ambient thermal resistance (θJA) is specified without a heat sink in still air using the printed circuit board layout shown in PCB Layouts Used For Thermal Measurements. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMT88 LMT88 SNIS175 –MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise noted, these specifications apply for V+ = +2.7 VDC. Boldface limits apply for TA = TJ = TMIN to TMAX ; all other limits TA = TJ = 25°C; Unless otherwise noted. PARAMETER CONDITIONS TYPICAL(1) MAX(2) UNIT (Limit) TA = 25°C to 30°C ±1.5 ±4.0 °C (max) TA = 130°C ±5.0 °C (max) TA = 125°C ±5.0 °C (max) TA = 100°C ±4.7 °C (max) Temperature to Voltage Error TA = 85°C ±4.6 °C (max) VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639V(3) TA = 80°C ±4.5 °C (max) TA = 0°C ±4.4 °C (max) TA = –30°C ±4.7 °C (min) TA = –40°C ±4.8 °C (max) TA = –55°C ±5.0 °C (max) Output Voltage at 0°C 1.8639 V Variance from Curve ±1.0 °C Non-Linearity (4) –20°C ≤ TA ≤ 80°C ±0.4% Sensor Gain (Temperature Sensitivity or Average Slope) –30°C ≤ T −11.0 mV/°C (min) to equation: V A ≤ 100°C −11.77 O=−11.77 mV/ °C×T+1.860V −12.6 mV/°C (max) Output Impedance 0 μA ≤ IL ≤ 16 μA (5) (6) 160 Ω (max) Load Regulation(7) 0 μA ≤ IL ≤ 16 μA (5) (6) −2.5 mV (max) 2.4 V ≤ V+ ≤ 5.0V 3.7 mV/V (max) Line Regulation(8) 5.0 V ≤ V+ ≤ 5.5 V 11 mV (max) 2.4V ≤ V+ ≤ 5.0V 4.5 7 μA (max) Quiescent Current 5.0V ≤ V+ ≤ 5.5V 4.5 9 μA (max) 2.4V ≤ V+ ≤ 5.0V 4.5 10 μA (max) Change of Quiescent Current 2.4 V ≤ V+ ≤ 5.5V 0.7 μA Temperature Coefficient of Quiescent Current −11 nA/°C Shutdown Current V+ ≤ 0.8 V 0.02 μA (1) Typicals are at TJ = TA = 25°C and represent most likely parametric norm. (2) Limits are specified to TI's AOQL (Average Outgoing Quality Level). (3) Accuracy is defined as the error between the measured and calculated output voltage at the specified conditions of voltage, current, and temperature (expressed in°C). (4) Non-Linearity is defined as the deviation of the calculated output-voltage-versus-temperature curve from the best-fit straight line, over the temperature range specified. (5) Negative currents are flowing into the LMT88. Positive currents are flowing out of the LMT88. Using this convention the LMT88 can at most sink −1 μA and source 16 μA. (6) Load regulation or output impedance specifications apply over the supply voltage range of 2.4V to 5.5V. (7) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output due to heating effects can be computed by multiplying the internal dissipation by the thermal resistance. (8) Line regulation is calculated by subtracting the output voltage at the highest supply input voltage from the output voltage at the lowest supply input voltage. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 6 O 6 (1.8639 V 2.1962 10 3.88 10 T 1481.96 u u LMT88 www.ti.com SNIS175 –MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS PCB Layouts Used For Thermal Measurements Figure 4. Layout Used For No Heat Sink Measurements Figure 5. Layout Used For Measurements With Small Heat Sink LMT88 TRANSFER FUNCTION The LMT88 transfer function can be described in different ways with varying levels of precision. A simple linear transfer function, with good accuracy near 25°C, is VO = −11.69 mV/°C × T + 1.8663 V (1) Over the full operating temperature range of −55°C to 130°C, best accuracy can be obtained by using the parabolic transfer function. VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 (2) solving for T: (3) A linear transfer function can be used over a limited temperature range by calculating a slope and offset that give best results over that range. A linear transfer function can be calculated from the parabolic transfer function of the LMT88. The slope of the linear transfer function can be calculated using the following equation: m = −7.76 × 10−6× T − 0.0115, (4) where T is the middle of the temperature range of interest and m is in V/°C. For example for the temperature range of TMIN = −30 to TMAX = +100°C: T = 35°C (5) and m = −11.77 mV/°C (6) The offset of the linear transfer function can be calculated using the following equation: b = (VOP(TMAX) + VOP(T) − m × (TMAX+T))/2 (7) where: VOP(TMAX) is the calculated output voltage at TMAX using the parabolic transfer function for VO VOP(T) is the calculated output voltage at T using the parabolic transfer function for VO. Using this procedure the best fit linear transfer function for many popular temperature ranges was calculated in Table 2. As shown in Table 2 the error that is introduced by the linear transfer function increases with wider temperature ranges. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMT88 LMT88 SNIS175 –MARCH 2013 www.ti.com Table 2. First Order Equations Optimized for Different Temperature Ranges TEMPERATURE RANGE MAXIMUM DEVIATION OF LINEAR EQUATION LINEAR EQUATION Tmin (°C) Tmax (°C) FROM PARABOLIC EQUATION (°C) −55 130 VO = −11.79 mV/°C × T + 1.8528 V ±1.41 −40 110 VO = −11.77 mV/°C × T + 1.8577 V ±0.93 −30 100 VO = −11.77 mV/°C × T + 1.8605 V ±0.70 -40 85 VO = −11.67 mV/°C × T + 1.8583 V ±0.65 −10 65 VO = −11.71 mV/°C × T + 1.8641 V ±0.23 35 45 VO = −11.81 mV/°C × T + 1.8701 V ±0.004 20 30 VO = –11.69 mV/°C × T + 1.8663 V ±0.004 MOUNTING The LMT88 can be applied easily in the same way as other integrated-circuit temperature sensors. It can be glued or cemented to a surface. The temperature that the LMT88 is sensing will be within about +0.02°C of the surface temperature to which the LMT88's leads are attached to. This presumes that the ambient air temperature is almost the same as the surface temperature; if the air temperature were much higher or lower than the surface temperature, the actual temperature measured would be at an intermediate temperature between the surface temperature and the air temperature. To ensure good thermal conductivity the backside of the LMT88 die is directly attached to the pin 2 GND pin. The tempertures of the lands and traces to the other leads of the LMT88 will also affect the temperature that is being sensed. Alternatively, the LMT88 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or screwed into a threaded hole in a tank. As with any IC, the LMT88 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold temperatures where condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often used to ensure that moisture cannot corrode the LMT88 or its connections. The thermal resistance junction to ambient (θJA) is the parameter used to calculate the rise of a device junction temperature due to its power dissipation. For the LMT88 the equation used to calculate the rise in the die temperature is as follows: TJ = TA + θJA [(V+ IQ) + (V+ − VO) IL] where IQ is the quiescent current and ILis the load current on the output. Since the LMT88's junction temperature is the actual temperature being measured care should be taken to minimize the load current that the LMT88 is required to drive. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d R C OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d R C 0.1 μF Bypass Optional 0.1 μF Bypass Optional OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d To A High-Impedance Load LMT88 www.ti.com SNIS175 –MARCH 2013 The tables shown in Table 3 summarize the rise in die temperature of the LMT88 without any loading, and the thermal resistance for different conditions. Table 3. Temperature Rise of LMT88 Due to Self-Heating and Thermal Resistance (θJA)(1) SC70-5 SC70-5 NO HEAT SINK SMALL HEAT SINK θJA TJ − TA θJA TJ − TA (°C/W) (°C) (°C/W) (°C) Still air 412 0.2 350 0.19 Moving air 312 0.17 266 0.15 (1) See PCB Layouts Used For Thermal Measurements for PCB layout samples. CAPACITIVE LOADS The LMT88 handles capacitive loading well. Without any precautions, the LMT88 can drive any capacitive load less than 300 pF as shown in Figure 6. Over the specified temperature range the LMT88 has a maximum output impedance of 160 Ω. In an extremely noisy environment it may be necessary to add some filtering to minimize noise pickup. It is recommended that 0.1 μF be added from V+ to GND to bypass the power supply voltage, as shown in . In a noisy environment it may even be necessary to add a capacitor from the output to ground with a series resistor as shown in . A 1 μF output capacitor with the 160 Ω maximum output impedance and a 200 Ω series resistor will form a 442 Hz lowpass filter. Since the thermal time constant of the LMT88 is much slower, the overall response time of the LMT88 will not be significantly affected. Figure 6. LMT88 No Decoupling Required for Capacitive Loads Less Than 300 pF R (Ω) C (μF) 200 1 470 0.1 680 0.01 1 k 0.001 spacer between the table and graphic Figure 7. LMT88 with Filter for Noisy Environment and Capacitive Loading Greater Than 300 pF Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMT88 GND 0.1 PF V+ VO LMT88 GND NC 0.1 PF V+ (+5.0V) 1 k ADCV0831 LM4040BIM3-4.1 GND VIN V+ 6 5 4 1 3 2 3 2 1 4 5 CS DO CLK 470 LMT88 SHUTDOWN +VS VO Any logic device output 4.1V R1 R3 R2 LM4040 U3 0.1 PF R4 VOUT V+ VT VTemp + - U1 V+ LMT88 U2 (High = overtemp alarm) VT1 VT2 VTEMP VOUT VT1 = R1 + R2||R3 (4.1)R2 VT2 = R2 + R1||R3 (4.1)R2||R3 LM7211 LMT88 SNIS175 –MARCH 2013 www.ti.com NOTE Either placement of resistor as shown above is just as effective. APPLICATION CIRCUITS Figure 8. Centigrade Thermostat Figure 9. Conserving Power Dissipation with Shutdown Figure 10. Suggested Connection to a Sampling Analog to Digital Converter Input Stage Most CMOS ADCs found in ASICs have a sampled data comparator input structure that is notorious for causing grief to analog output devices such as the LMT88 and many op amps. The cause of this grief is the requirement of instantaneous charge of the input sampling capacitor in the ADC. This requirement is easily accommodated by the addition of a capacitor. Since not all ADCs have identical input stages, the charge requirements will vary necessitating a different value of compensating capacitor. This ADC is shown as an example only. If a digital output temperature is required please refer to devices such as the LM74. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LMT88DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 130 T9C LMT88DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 130 T9C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LMT88DCKR SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMT88DCKT SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMT88DCKR SC70 DCK 5 3000 210.0 185.0 35.0 LMT88DCKT SC70 DCK 5 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 125°C. The EVM is designed to operate properly with certain components above 125°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated Information About Cautions and Warnings v Preface Read This First About This Manual This EVM user’s guide provides information about the 2-GBPS differential repeater evaluation module. How to Use This Manual This document contains the following chapters: Chapter 1 — Introduction Chapter2 — Setup and Equipment Required Chapter 3 — EVM Construction Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments vi Related Documentation From Texas Instruments To obtain a copy of any of the following TI document, call the Texas Instruments Literature Response Center at (800) 477-8924 or the Product Information Center (PIC) at (972) 644-5580. When ordering, identify this booklet by its title and literature number. Updated documents can also be obtained through our website at www.ti.com. Data Sheet: Literature Number: SN65LVDS100/101 SLLS516 SN65CML100 SLLS547 FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Contents vii Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 Setup and Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 3 EVM Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 Board Layer Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Figures 1-1 EVM With SN65LVDS100 Installed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2 Schematic of EVM Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2-1 TIA/EIA-644-A LVDS Driver Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-2 EVM Power Connections for SN65LVDS100 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-3 External Termination for Differential CML or LVPECL Inputs to EVM . . . . . . . . . . . . . . . . . 2-4 2-4 External Termination for Single-Ended LVPECL Inputs to EVM . . . . . . . . . . . . . . . . . . . . . . 2-5 2-5 Typical Output From SN65LVDS100 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Tables 1-1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Contents viii Introduction 1-1 Introduction The 2-GBPS differential repeater evaluation module (EVM) allows evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential repeaters/ translators. This user’s guide gives a brief overview of the EVM, setup and operation instructions, and typical test results that can be expected. Topic Page 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Chapter 1 Overview 1-2 1.1 Overview The 2-GBPS differential repeater evaluation module (EVM) is designed for evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential repeaters/ translators. The SN65LVDS100 and SN65LVDS101 devices both incorporate wide common-mode range receivers, allowing receipt of LVDS, LVPECL, or CML input signals. The SN65LVDS100 provides an LVDS output, the SN65LVDS101 incorporates an LVPECL output driver, and the SN65CML100 delivers a CML output. Both devices provide a VBB reference voltage to support receiving of single-ended LVPECL input signals, or biasing of ac-coupled inputs. The EVM can be ordered with the SN65LVDS100, SN65LVDS101, or SN65CML100 installed. Orderable EVM part numbers are shown in Table 1-1. Table 1-1. Ordering Information EVM Part Number Installed Device SN65LVDS100EVM SN65LVDS100DGK SN65LVDS101EVM SN65LVDS101DGK SN65CML100EVM SN65CML100DGK Detailed information relating to the SN65LVDS100, SN65LVDS101, and SN65CML100 can be found in the device data sheet, a copy of which is shipped as part of the EVM or available from www.ti.com. A picture of the EVM, with an SN65LVDS100 device installed, is shown in Figure 1-1. Figure 1-1. EVM With SN65LVDS100 Installed Signal Paths Introduction 1-3 1.2 Signal Paths A partial schematic of the EVM is shown in Figure 1-2 and a full schematic is in chapter 3. Edge-mount SMA connectors (J4, J5, J6, and J7) are provided for data input and output connections. Three power jacks (J1, J2, and J3) are used to provide power to and a ground reference, for the EVM. The use of these power jacks is addressed later. Chapter 3 also provides a parts list for the EVM, as well as an indication of which components are installed when shipped. Figure 1-2. Schematic of EVM Signal Path NC A B Vbb VCC Y Z GND R5 Uninstalled JMP2 1 2 C12 .010 μF DUT_MSOP8 DUT1 VCC01 VCC C11 .010 μF R2 Uninstalled J6 GND J7 GND R4 Uninstalled R3 Uninstalled J4 R1 100 Ω GND J5 GND 1 1 1 2 3 4 8 7 6 5 1 1 1-4 Setup and Equipment Required 2-1 Setup and Equipment Required This chapter examines the setup and use of the evaluation module and the results of operation. Topic Page 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Chapter 2 Overview 2-2 2.1 Overview LVDS driver output characteristics are specified in the TIA/EIA-644 standard. LVDS drivers nominally provide a 350-mV differential signal, with a 1.25-V offset from ground. These levels are attained when driving a 100-Ω differential line-termination test load (see Figure 2-1). In real applications, there may be a ground potential between a driver and receiver(s). The driver must drive the common-mode load presented by the receiver inputs and the differential load. A TIA/EIA-644-A compliant LVDS driver is required to maintain its differential output with up to 32 standard receivers. The receiver load is represented by the 3.74-kΩ resistors shown in Figure 2-1. Figure 2-1. TIA/EIA-644-A LVDS Driver Test Load _ + A B VOD 100 Ω 3.74 kΩ 3.74 kΩ 0 V ≤ Vtest ≤ 2.4 V D LVPECL drivers are generally loaded with 50-Ω resistors to a termination bias voltage, VT. VT is usually 2-V below the supply voltage of the driver circuit. When the driver operates from a 3.3-V supply, VT is set to approximately 1.3 V. CML drivers are generally loaded with 50-Ω resistors to a termination voltage, VTT. VTT can either be equivalent to the supply voltage of the driver circuit (equal to VCC) or set to 2.5 V or 1.8 V, irrelevant to the supply voltage. If desired, the SN65CML100 can be configured to drive a dual 50-Ω load. In this configuration one 50-Ω resistor (tied to the termination voltage VTT) is placed near the output of the SN65CML100 and a second 50-Ω resistor (also tied to VTT) is placed near the end of the transmission line. The EVM has been designed to support the SN65LVDS100 LVDS-output device, the SN65LVDS101 LVPECL-output device, and the SN65CML100 CML-output device. By using the three power jacks (J1, J2, and J3), as well as installing termination resistors (R2, R3, and R4), different methods of termination and probing can be used to evaluate the device output characteristics. The typical setup for the SN65LVDS100 is shown in Figure 2-2. Applying an Input Setup and Equipment Required 2-3 Figure 2-2. EVM Power Connections for SN65LVDS100 Evaluation Pattern Generator Oscilloscope EVM Power Supply 1 + - Power Supply 2 + - EVM VCC GND DUT GND 1.22V 3.3V Matched Cables SMA to SMA Matched Cables SMA to SMA J2 J7 J6 J5 J4 J3 J1 100 Ω 50 Ω 50 Ω Warning Power jacks J1, J2, and J3 are not insulated on the backside of the EVM. Place on a nonconductive surface. 2.2 Applying an Input LVDS inputs should be applied to SMA connectors J4 and J5, while keeping R1 installed. The EVM comes with a 100-Ω termination resistor (R1) installed across the differential inputs. This 100-Ω resistor represents an LVDS termination. When using a general-purpose signal generator with 50-Ω output impedance, make sure that the signal levels are between 0 V to 4 V with respect to J3. A signal generator such as the Advantest D3186 can simulate LVDS, LVPECL, or CML inputs. When using LVPECL or CML drivers for the input signal, termination external to the EVM must be provided (see Figure 2-3). LVPECL drivers should be terminated with 50-Ω pulldowns to VT, while CML drivers should be terminated Applying an Input 2-4 with 50-Ω pullups to VTT. When using external terminations, the onboard termination resistor R1 should be removed from the EVM. It should be noted that the signal quality at the receiver input may be degraded when external terminations are used, as a significant stub exists from the external termination network to the receiver input. The user needs to verify that the transition time of the input signal, coupled with the stub length, does not lead to reflection problems. These concerns would be addressed in a real application where the terminations are placed close to the receiver input. Figure 2-3. External Termination for Differential CML or LVPECL Inputs to EVM Select VT for LVPECL or Select VTT for CML Select VT for LVPECL or Select VTT for CML 50 Ω 50 Ω OUT OUT Signal Source EVM BOARD NOTES: A. Locate 50-Ω resistors as close to the EVM as possible B. Remove R1 A B Y Z Finally, as mentioned above, the SN65LVDS100, SN65LVDS101, and SN65CML100 devices provide a VBB reference voltage output. This output can be used with an externally terminated, single-ended, LVPECL input to convert from a single-ended input to a differential output. The same cautions that are mentioned above concerning signal quality and reflections apply. When using VBB as a single-ended reference, R1 should be removed while R5 and JMP2 should be installed. The single-ended input signal is applied to J4. This setup directly connects the VBB output to the DUT receiver B input via a 0-Ω connection (see Figure 2-4). Observing an Output Setup and Equipment Required 2-5 Figure 2-4. External Termination for Single-Ended LVPECL Inputs to EVM 50 Ω OUT Signal Source EVM BOARD NOTES: A. Add jumper Jmp2 and 0-Ω R5 B. Remove R1 A B Y Z 2.3 Observing an Output Direct connection to an oscilloscope with 50-Ω internal terminations to ground is accomplished without R2, R3, and R41. The outputs are available at J6 and J7 for direct connection to oscilloscope inputs. Matched length cables must be used when connecting the EVM to a scope to avoid inducing skew between the noninverting (+) and inverting (-) outputs. The three power jacks (J1, J2, and J3) are used to provide power and a ground reference for the EVM. The power connections to the EVM determine the common-mode load to the device. As mentioned earlier, LVDS drivers have limited common-mode driver capability. When connecting the EVM outputs directly to oscilloscope inputs, setting of the oscilloscope common-mode offset voltage is required, as the oscilloscope presents low common-mode load impedance to the device. Returning to Figure 2-2, power supply 1 is used to provide the required 3.3 V to the EVM. Power supply 2 is used to offset the EVM ground relative to the DUT ground. The EVM ground is connected to the oscilloscope ground through the returns on SMA connectors J6 and J7. With power applied as shown in Figure 2-2, the common-mode voltage seen by the SN65LVDS100 is approximately equal to the reference voltage being used inside the device preventing significant common-mode current to flow. Optimum device setup can be confirmed by adjusting the voltage on power supply 2 until its current is minimized. It is important to note that use of the dual supplies and offsetting the EVM ground relative to the DUT ground are simply steps needed for the test and evaluation of devices. Actual designs would include high-impedance receivers, which would not require the setup steps outlined above. 1 As delivered R2, R3, and R4 are not installed Typical Test Results 2-6 LVPECL drivers need a 50-Ω termination to VT. A modification of Figure 2-2 and the above instructions are used when evaluating an SN65LVDS101 with a direct connection to a 50-Ω oscilloscope. With power supply 1 in Figure 2-2 set to 3.3 V, power supply 2 should be set to 1.3 V (2 V below VCC) to provide the correct termination voltage. CML drivers need a 50-Ω termination to VTT (VTT is either VCC, 2.5 V, or 1.8 V). A modification of Figure 2-2 and the instructions for the SN65LVDS100 are used when evaluating a SN65CML100 with direct connection to a 50-Ω oscilloscope. With power supply 1 in Figure 2-2 set to 3.3 V, power supply 2 should be set to either VCC (3.3 V), 2.5 V, or 1.8 V to provide the correct termination voltage. Dual termination of the output can be achieved by placing 49.9-Ω resistors at R2 and R3 and connecting to an oscilloscope as described above. If the EVM outputs are to be evaluated with a high-impedance probe, direct probing on the EVM is supported via installation of R2, R3, and R4. LVDS outputs can be observed by installing R4, a 100-Ω resistor. LVPECL outputs can be observed by installing R2 and R3 (49.9-Ω resistors), and setting power supply 2 to 1.3 V. CML outputs can be observed by setting power supply 2 to VTT and installing 49.9-Ω resistors at R2 and R3 for single termination, or 24.9-Ω resistors at R2 and R3 for dual termination (Note that power supply 2 must be able to sink current.) 2.4 Typical Test Results Figure 2-5 shows a typical test result obtained with the EVM. Figure 2-5 shows the output of an SN65LVDS100 being driven directly into a 50-Ω oscilloscope. For this figure, the SN65LVDS100 was stimulated with an HP 3-GBPS BERT. The input data was pseudorandom data at 2 GBPS and with a random record length of 223-1. The BERT drove two electrically matched one-meter cables with an electrical length of 3.667 ns. These cables were then connected to the EVM inputs. The EVM outputs were connected through another set of electrically matched one-meter cables and terminated by a TDS8000 oscilloscope’s 50-Ω resistors to ground. Typical Test Results Setup and Equipment Required 2-7 Figure 2-5. Typical Output From SN65LVDS100 EVM 2-8 EVM Construction 3-1 EVM Construction This chapter lists the EVM components and examines the construction of the evaluation module. Topic Page 3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 Board Layer Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Chapter 3 Schematic 3-2 3.1 Schematic NC A B Vbb VCC Y Z GND R5 Uninstalled JMP2 1 2 C12 .010 μF DUT_MSOP8 DUT1 VCC01 VCC C11 .010 μF R2 Uninstalled J6 GND J7 GND R4 Uninstalled R3 Uninstalled J4 R1 100 Ω GND J5 GND 1 1 1 2 3 4 8 7 6 5 1 1 VCC VCC01 + + + + C1 10 μF C6 10 μF C2 68 μF C7 68 μF C3 1 μF C8 1 μF C4 0.1 μF C9 0.1 μF C5 0.001 μF 109 0.001 μF J1 -1 J2 -1 J3 -1 MNTH1 MNTH2 MNTH3 MNTH4 Bill of Materials EVM Construction 3-3 3.2 Bill of Materials ITEM QTY MFG MFG PART NO. REF. DES. DESCRIPTION VALUE OR FUNCTION NOT INSTALLED 1 2 Sprague 293D106X0035D2W C1,C6 Capacitor, SMT, TANT 35 V, 10%, 10 μF 2 2 AVX 12063G105ZATRA C3,C8 Capacitor, SMT1206 25 V, 80 -20%, 1.0 μF 3 2 AVX 12065C104JATMA C4,C9 Capacitor, SMT1206 50 V, 5%, 0.1 μF 4 2 Sprague 592D686X0010R2T C2,C7 Capacitor, SMT, TANT 10 V, 20%, 68 μF, Low ESR 5 2 Murata GRM39X7R103K50V C11, C12 Capacitor, SMT0603 50 V,±10%, 0.010 μF 6 2 AVX 06033G102JATMA C5,C10 Capacitor, SMT0603 25 V, 5%, 0.001 μF 7 3 ITT-Pomona 3267 J1, J2, J3 Connector, banana jack Bannana jack 8 4 EF Johnson 142-0701-801 J4, J5, J6, J7 Connector SMA Jack, end launch, 0.062 9 1 Dale CRCW0603100F R1 Resistor, SMT,0603 100 Ω 10 2 R2, R3 Resistor, SMT, 0603 49.9 Ω R2, R3 11 1 R4 Resistor, SMT, 0603 100 Ω R4 12 1 R5 Resistor, SMT, 0603 0 Ω R5 13 1 AMP 4-103239-0x2 JMP2 Header Male, 2 pin, 0.100 CC 14 1 TI SN65LVDS100† SN65LVDS101† DUT1 IC, SMT, 8P 2-GBPS differential repeater/translator 15 3 Screws 16 3 Nuts 17 1 User’s manual 18 1 Data sheet † Only one is installed Board Stackup 3-4 3.3 Board Stackup 9 Copper Foil CH A1 Copper Foil CH A1 .0062 PREPREG .0062 PREPREG CORE .015 C1/0 A1 .0122 PREPREG CORE .015 C0/1 A1 SECTION A - A NO SCALE TOP SIDE-SIGNAL/GND FILL (LAYER 1) INT1-GND PLANE (LAYER 2) INT2-VCC SPLIT PLANE (LAYER 3) 9 BOTTOM SIDE-GND PLANE (LAYER 4) Symbol Diameter (in) 0.0160 0.0320 0.0400 0.0500 0.1250 0.2720 Plated Yes Yes Yes Yes Yes Yes Quantity 49 82343 Through Holes 3.000 A A 3.000 DATUM 0,0 TOP SIDE SHOWN DRILL 0.250 0.250 NN THIS IS AN IMPEDANCE CONTROLLED BOARD. GENERAL NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL FABRICATION ITEMS MUST MEET OR EXCEED BEST INDUSTRY PRACTICE. IPC-A 600C ( Commercial Std.) 2.LAMINATE MATERIAL: NELCO N4000-13 (DO NOT USE - 13SI) 3. COOPER WEIGHT:1 OZ. START INTERNAL AND 1/2 OZ. START EXTERNAL 4. FINISHED BOARD THICKNESS: .062 ±10% 5. MAXIMUM WARP AND TWIST TO BE .005 INCH PER INCH 6 MINIMUM COPPER WALL THICKNESS OF PLATED-THRU HOLES TO BE .001 INCH 7 MINIMUM ANNULAR RING OF PLATED-THRU HOLES TO BE .002 INCH 8. MINIMUM ALLOWABLE LINE REDUCTION TO BE 20% OR .002 WHICHEVER IS GREATER 9. 0.013 INCH SIGNAL LINES ON LAYER 1 TO BE IMPEDANCE CONTROLLED 50 OHMS TO GND ±10% 0.010 INCH SIGNAL LINES ON LAYER 1 TO BE IMPEDANCE CONTROLLED 100 OHMS TO EACH OTHER ±10% 10. DIELECTRIC CONSTANTS ARE: CORE: 3.2 PREPREG:3.2 PROCESS NOTES: 1. CIRCUITRY ON OUTER LAYERS TO BE PLATED WITH TIN LEAD 2. SOLDERMASK BOTH SIDES PER ARTWORK: GREEN LPI 3. SILKSCREEN BOTH SIDE PER ARTWORK: COLOR=WHITE 4 N 6434666A PWA, BENCH, EVALUATION BOARD, SN65LVDS100/101D, EVM 10/31/01 Board Layer Patterns EVM Construction 3-5 3.4 Board Layer Patterns (Not to Scale) Layer 1 - Signal/GND Fill (Top Side) Layer 2 - GND Plane (INT1) Board Layer Patterns 3-6 Layer 3 - VCC Split Plane (INT2) Layer 4 - GND Plane (Bottom Side) ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Piccolo Microcontrollers Check for Samples: TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 1 TMS320F2805x ( Piccolo™) MCUs 1.1 Features 123 • Highlights • Programmable Control Law Accelerator (CLA) – High-Efficiency 32-Bit CPU ( TMS320C28x™) – 32-Bit Floating-Point Math Accelerator – 60-MHz Device – Executes Code Independently of the Main – Single 3.3-V Supply CPU – Integrated Power-on and Brown-out Resets • Low Device and System Cost: – Two Internal Zero-pin Oscillators – Single 3.3-V Supply – Up to 42 Multiplexed GPIO Pins – No Power Sequencing Requirement – Three 32-Bit CPU Timers – Integrated Power-on Reset and Brown-out – On-Chip Flash, SARAM, Message RAM, OTP, Reset CLA Data ROM, Boot ROM, Secure ROM – Low Power Memory – No Analog Support Pins – Dual-Zone Security Module • Clocking: – Serial Port Peripherals (SCI/SPI/I2C/eCAN) – Two Internal Zero-pin Oscillators – Enhanced Control Peripherals – On-Chip Crystal Oscillator/External Clock • Enhanced Pulse Width Modulator (ePWM) Input • Enhanced Capture (eCAP) – Dynamic PLL Ratio Changes Supported • Enhanced Quadrature Encoder Pulse – Watchdog Timer Module (eQEP) – Missing Clock Detection Circuitry – Analog Peripherals • Up to 42 Individually Programmable, • One 12-Bit Analog-to-Digital Converter Multiplexed GPIO Pins With Input Filtering (ADC) • Peripheral Interrupt Expansion (PIE) Block That • One On-Chip Temperature Sensor Supports All Peripheral Interrupts • Up to Seven Comparators With up to • Three 32-Bit CPU Timers Three Integrated Digital-to-Analog • Independent 16-Bit Timer in Each ePWM Converters (DACs) Module • One Buffered Reference DAC • On-Chip Memory • Up to Four Programmable Gain – Flash, SARAM, Message RAM, OTP, CLA Amplifiers (PGAs) Data ROM, Boot ROM, Secure ROM Available • Up to Four Digital Filters • 128-Bit Security Key and Lock – 80-Pin Package – Protects Secure Memory Blocks • High-Efficiency 32-Bit CPU ( TMS320C28x™) – Prevents Firmware Reverse Engineering – 60 MHz (16.67-ns Cycle Time) • Serial Port Peripherals – 16 x 16 and 32 x 32 MAC Operations – Three SCI (UART) Modules – 16 x 16 Dual MAC – One SPI Module – Harvard Bus Architecture – One Inter-Integrated-Circuit (I2C) Bus – Atomic Operations – One Enhanced Controller Area Network – Fast Interrupt Response and Processing (eCAN) Bus – Unified Memory Programming Model • Advanced Emulation Features – Code-Efficient (in C/C++ and Assembly) – Analysis and Breakpoint Functions • Endianness: Little Endian – Real-Time Debug via Hardware • 80-Pin PN Low-Profile Quad Flatpack (LQFP) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510, XDS560 are trademarks of Texas Instruments. 3All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling or preproduction Copyright © 2012, Texas Instruments Incorporated phase of development. Characteristic data and other specifications are subject to change without notice. ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 1.2 Description The F2805x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, as well as providing a high level of analog integration. An internal voltage regulator allows for single rail operation. Analog comparators with internal 6-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead/latency. The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to- Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers (PGAs), and up to four digital filters. The Programmable Gain Amplifiers (PGAs) are capable of amplifying the input signal in three discrete gain modes. The actual gain itself depends on the resistors defined by the user at the bipolar input end. The actual number of AFE peripherals will depend upon the 2805x device number. See Table 2-1 for more details. 2 TMS320F2805x ( Piccolo™) MCUs Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 SARAM 1Kx16 (0-wait) 16-bit Peripheral Bus M1 SARAM 1Kx16 (0-wait) SCI-A, B C (4L FIFO) SCI- , SCI- SPISIMOA SPISOMIA SPICLKA SPISTEA ePWM1–ePWM7 SPI-A (4L FIFO) I2C-A (4L FIFO) 32-Bit Peripheral Bus GPIO MUX C28x CPU (60 MHz) PIE (up to 96 interrupts) CPU Timer 0 CPU Timer 1 CPU Timer 2 TRST TCK TDI TMS TDO OSC1, OSC2, Ext, PLL, LPM, WD X2 32-bit Peripheral Bus (CLA-accessible) EPWMxA EPWMxB SDAx SCLx SCIRXDx GPIO Mux LPM Wakeup CLA + Message RAMs ADC 0-wait Result Regs Boot ROM 12Kx16 (0-wait) Non-Secure L0 SARAM (2Kx16) (0-wait, Secure) CLA Data RAM2 COMP + Digital COMPAn Filter COMPBn 32-bit Peripheral Bus (CLA-accessible) eCAN-A (32-mbox) eCAP ECAPx CANTXx CANRXx eQEP EQEPxA EQEPxB EQEPxI EQEPxS SCITXDx X1 GPIO MUX Program- mable Gain Amps VREG POR/ BOR Memory Bus Memory Bus TZx Secure ROM (A) 2Kx16 (0-wait) Secure L1 DPSARAM (1Kx16) (0-wait, Secure) CLA Data RAM0 L2 DPSARAM (1Kx16) (0-wait, Secure) CLA Data RAM1 L3 DPSARAM (4Kx16) (0-wait, Secure) CLA Program RAM CLA Data ROM (4Kx16) CTRIPnOUT ADC 3.75 MSPS 32-bit Peripheral Bus (CLA-accessible) CLA Bus XRS GPIO Mux XCLKIN 3 External Interrupts Memory Bus EPWMSYNCI EPWMSYNCO PSWD Dual- Zone Security Module + ECSL OTP/Flash Wrapper Z1/Z2 User OTP Secure PUMP FLASH 28055, 28054: 64K x 16, 10 Sectors 28053, 28052, 28051: 32K x 16, 5 Sectors 28050: 16K x 16, 3 Sectors Secure TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 1.3 Functional Block Diagram A. Stores Secure Copy Code Functions on all devices. B. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram Copyright © 2012, Texas Instruments Incorporated TMS320F2805x ( Piccolo™) MCUs 3 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 1 TMS320F2805x ( Piccolo™) MCUs .................. 1 5.1 Power Sequencing ................................. 58 1.1 Features ............................................. 1 5.2 Clocking ............................................ 60 1.2 Description ........................................... 2 5.3 Interrupts ............................................ 63 1.3 Functional Block Diagram ........................... 3 6 Peripheral Information and Timings ............... 68 2 Device Overview ........................................ 5 6.1 Parameter Information .............................. 68 2.1 Device Characteristics ............................... 5 6.2 Control Law Accelerator (CLA) ..................... 69 2.2 Memory Maps ........................................ 8 6.3 Analog Block ........................................ 72 2.3 Brief Descriptions ................................... 15 6.4 Serial Peripheral Interface (SPI) .................... 91 2.4 Register Map ....................................... 26 6.5 Serial Communications Interface (SCI) ........... 100 2.5 Device Emulation Registers ........................ 28 6.6 Enhanced Controller Area Network (eCAN) ...... 103 2.6 VREG, BOR, POR .................................. 30 6.7 Inter-Integrated Circuit (I2C) ...................... 107 2.7 System Control ..................................... 32 6.8 Enhanced Pulse Width Modulator (ePWM) ....... 110 2.8 Low-power Modes Block ........................... 40 6.9 Enhanced Capture Module (eCAP) ............... 118 2.9 Thermal Design Considerations .................... 40 6.10 Enhanced Quadrature Encoder Pulse (eQEP) .... 120 3 Device Pins ............................................. 41 6.11 JTAG Port ......................................... 123 3.1 Pin Assignments .................................... 41 6.12 General-Purpose Input/Output (GPIO) ............ 125 3.2 Terminal Functions ................................. 42 7 Device and Documentation Support ............. 136 4 Device Operating Conditions ....................... 50 7.1 Device Support .................................... 136 4.1 Absolute Maximum Ratings ........................ 50 7.2 Documentation Support ........................... 138 4.2 Recommended Operating Conditions .............. 50 7.3 Community Resources ............................ 138 4.3 Electrical Characteristics Over Recommended 8 Mechanical Packaging and Orderable Operating Conditions (Unless Otherwise Noted) ... 51 Information ............................................ 139 4.4 Current Consumption ............................... 52 8.1 Thermal Data for Package ........................ 139 4.5 Flash Timing ........................................ 56 8.2 Packaging Information ............................ 139 5 Power, Reset, Clocking, and Interrupts ........... 58 4 Contents Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2 Device Overview 2.1 Device Characteristics Table 2-1 lists the features of the TMS320F2805x devices. Copyright © 2012, Texas Instruments Incorporated Device Overview 5 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 2-1. TMS320F2805x Hardware Features FEATURE 28055 28054 28053 28052 28051 28050 (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) Package Type 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN LQFP LQFP LQFP LQFP LQFP LQFP Instruction cycle 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns Control Law Accelerator (CLA) Yes No Yes No No No On-chip flash (16-bit word) 64K 64K 32K 32K 32K 16K On-chip SARAM (16-bit word) 10K 10K 10K 10K 8K 6K Dual-zone security for on-chip Flash, SARAM, OTP, Yes Yes Yes Yes Yes Yes and Secure ROM blocks Boot ROM (12K x 16) Yes Yes Yes Yes Yes Yes One-time programmable (OTP) ROM 1K 1K 1K 1K 1K 1K (16-bit word) ePWM outputs 14 14 14 14 14 14 eCAP inputs 1 1 1 1 1 1 eQEP modules 1 1 1 1 1 1 Watchdog timer Yes Yes Yes Yes Yes Yes MSPS 3.75 3.75 3.75 3.75 2 2 Conversion Time 267 ns 267 ns 267 ns 267 ns 500 ns 500 ns 12-Bit ADC Channels 16 16 16 16 16 16 Temperature Sensor Yes Yes Yes Yes Yes Yes Dual Yes Yes Yes Yes Yes Yes Sample-and-Hold Programmable Gain Amplifier (PGA) 4 4 4 4 4 3 (Gains = ~3, ~6, ~11) Fixed Gain Amplifier 3 3 3 3 3 4 (Gain = ~3) Comparators 7 7 7 7 7 6 Internal Comparator Reference DACs 3 3 3 3 3 2 Buffered Reference DAC 1 1 1 1 1 1 32-Bit CPU timers 3 3 3 3 3 3 Inter-integrated circuit (I2C) 1 1 1 1 1 1 Enhanced Controller Area Network (eCAN) 1 1 1 1 1 1 Serial Peripheral Interface (SPI) 1 1 1 1 1 1 Serial Communications Interface (SCI) 3 3 3 3 3 3 0-pin Oscillators 2 2 2 2 2 2 I/O pins (shared) GPIO 42 42 42 42 42 42 External interrupts 3 3 3 3 3 3 Supply voltage (nominal) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 6 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-1. TMS320F2805x Hardware Features (continued) FEATURE 28055 28054 28053 28052 28051 28050 (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) T: –40ºC to 105ºC Yes Yes Yes Yes Yes Yes Temperature options S: –40ºC to 125ºC Yes Yes Yes Yes Yes Yes Product status(1) TMX TMX TMX TMX TMX TMX (1) See Section 7.1.2, Device and Development Support Tool Nomenclature, for descriptions of device stages. The "TMX" product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications. Copyright © 2012, Texas Instruments Incorporated Device Overview 7 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.2 Memory Maps In Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space. • Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order. • Certain memory ranges are EALLOW protected against spurious writes after configuration. 8 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) 0x00 0000 0x00 0040 0x00 0400 M1 SARAM (1K x 16, 0-Wait) Data Space Prog Space Reserved 0x00 2000 Reserved Peripheral Frame 1 (1K x 16, Protected) 0x00 6000 Peripheral Frame 3 (1.5K x 16, Protected) 0x00 6400 Peripheral Frame 1 (1.5K x 16, Protected) 0x00 6A00 Peripheral Frame 2 (4K x 16, Protected) 0x00 7000 Reserved 0x00 0800 Peripheral Frame 0 0x00 1580 Peripheral Frame 0 0x00 0D00 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) 0x00 1400 0x00 0E00 0x00 1500 0x00 1480 CPU-to-CLA Message RAM CLA-to-CPU Message RAM CLA Registers Peripheral Frame 0 0x00 8000 L0 DPSARAM (2K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2) 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1) 0x00 9000 L3 DPSARAM (4K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM) 0x3D 7800 User OTP, Zone 2 Passwords (512 x 16) 0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16) 0x00 F000 CLA Data ROM (4K x 16) 0x00 A000 Reserved 0x01 0000 Reserved 0x3D 7C00 Reserved 0x3D 7E00 Calibration Data FLASH (64K x 16, 10 Sectors, Dual Secure Zone + ECSL) (Z1/Z2 User-Selectable Security Zone Per Sector) 0x3E 8000 0x3F 7FFF Zone 1 Secure Copy Code ROM (1K x 16) 0x3F 8000 Zone 2 Secure Copy Code ROM (1K x 16) 0x3F 8400 0x3D 7FCB Configuration Data 0x3F FFC0 0x3F D000 Vector (32 Vectors, Enabled if VMAP = 1) Boot ROM (12K x 16, 0-Wait) 0x3D 7FF0 Reserved 0x3F 8800 Reserved TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. CLA-specific registers and RAM apply to the 28055 device only. Figure 2-1. 28055 and 28054 Memory Map Copyright © 2012, Texas Instruments Incorporated Device Overview 9 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) 0x00 0000 0x00 0040 0x00 0400 M1 SARAM (1K x 16, 0-Wait) Data Space Prog Space Reserved 0x00 2000 Reserved Peripheral Frame 1 (1K x 16, Protected) 0x00 6000 Peripheral Frame 3 (1.5K x 16, Protected) 0x00 6400 Peripheral Frame 1 (1.5K x 16, Protected) 0x00 6A00 Peripheral Frame 2 (4K x 16, Protected) 0x00 7000 Reserved 0x00 0800 Peripheral Frame 0 0x00 1580 Peripheral Frame 0 0x00 0D00 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) 0x00 1400 0x00 0E00 0x00 1500 0x00 1480 CPU-to-CLA Message RAM CLA-to-CPU Message RAM CLA Registers Peripheral Frame 0 0x00 8000 L0 DPSARAM (2K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2) 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1) 0x00 9000 L3 DPSARAM (4K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM) 0x3D 7800 User OTP, Zone 2 Passwords (512 x 16) 0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16) 0x00 F000 CLA Data ROM (4K x 16) 0x00 A000 Reserved 0x01 0000 Reserved 0x3D 7C00 Reserved 0x3D 7E00 Calibration Data FLASH (32K x 16, 5 Sectors, Dual Secure Zone + ECSL) (Z1/Z2 User-Selectable Security Zone Per Sector) 0x3F 0000 0x3F 7FFF Zone 1 Secure Copy Code ROM (1K x 16) 0x3F 8000 Zone 2 Secure Copy Code ROM (1K x 16) 0x3F 8400 0x3D 7FCB Configuration Data 0x3F FFC0 0x3F D000 Vector (32 Vectors, Enabled if VMAP = 1) Boot ROM (12K x 16, 0-Wait) 0x3D 7FF0 Reserved 0x3F 8800 Reserved TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. CLA-specific registers and RAM apply to the 28053 device only. Figure 2-2. 28053 and 28052 Memory Map 10 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) 0x00 0000 0x00 0040 0x00 0400 M1 SARAM (1K x 16, 0-Wait) Data Space Prog Space Reserved 0x00 2000 Reserved Peripheral Frame 1 (1K x 16, Protected) 0x00 6000 Peripheral Frame 3 (1.5K x 16, Protected) 0x00 6400 Peripheral Frame 1 (1.5K x 16, Protected) 0x00 6A00 Peripheral Frame 2 (4K x 16, Protected) 0x00 7000 Reserved 0x00 0800 Peripheral Frame 0 0x00 1580 Peripheral Frame 0 0x00 0D00 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) 0x00 1400 0x00 0E00 0x00 1500 0x00 1480 CPU-to-CLA Message RAM CLA-to-CPU Message RAM CLA Registers Peripheral Frame 0 0x00 8000 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1) 0x00 9000 L3 DPSARAM (4K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM) 0x3D 7800 User OTP, Zone 2 Passwords (512 x 16) 0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16) 0x00 F000 CLA Data ROM (4K x 16) 0x00 A000 Reserved 0x01 0000 Reserved 0x3D 7C00 Reserved 0x3D 7E00 Calibration Data FLASH (32K x 16, 5 Sectors, Dual Secure Zone + ECSL) (Z1/Z2 User-Selectable Security Zone Per Sector) 0x3F 0000 0x3F 7FFF Zone 1 Secure Copy Code ROM (1K x 16) 0x3F 8000 Zone 2 Secure Copy Code ROM (1K x 16) 0x3F 8400 0x3D 7FCB Configuration Data 0x3F FFC0 0x3F D000 Vector (32 Vectors, Enabled if VMAP = 1) Boot ROM (12K x 16, 0-Wait) 0x3D 7FF0 Reserved 0x3F 8800 Reserved Reserved TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 2-3. 28051 Memory Map Copyright © 2012, Texas Instruments Incorporated Device Overview 11 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) 0x00 0000 0x00 0040 0x00 0400 M1 SARAM (1K x 16, 0-Wait) Data Space Prog Space Reserved 0x00 2000 Reserved Peripheral Frame 1 (1K x 16, Protected) 0x00 6000 Peripheral Frame 3 (1.5K x 16, Protected) 0x00 6400 Peripheral Frame 1 (1.5K x 16, Protected) 0x00 6A00 Peripheral Frame 2 (4K x 16, Protected) 0x00 7000 Reserved 0x00 0800 Peripheral Frame 0 0x00 1580 Peripheral Frame 0 0x00 0D00 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) 0x00 1400 0x00 0E00 Peripheral Frame 0 0x00 8000 L0 DPSARAM (2K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL) 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL) 0x00 9000 0x3D 7800 User OTP, Zone 2 Passwords (512 x 16) 0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16) 0x00 F000 0x00 A000 Reserved 0x01 0000 Reserved 0x3D 7C00 Reserved 0x3D 7E00 Calibration Data FLASH (16K x 16, 3 Sectors, Dual Secure Zone + ECSL) (Z1/Z2 User-Selectable Security Zone Per Sector) 0x3F 4000 0x3F 7FFF Zone 1 Secure Copy Code ROM (1K x 16) 0x3F 8000 Zone 2 Secure Copy Code ROM (1K x 16) 0x3F 8400 0x3D 7FCB Configuration Data 0x3F FFC0 0x3F D000 Vector (32 Vectors, Enabled if VMAP = 1) Boot ROM (12K x 16, 0-Wait) 0x3D 7FF0 Reserved 0x3F 8800 Reserved Reserved Reserved Reserved TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 2-4. 28050 Memory Map 12 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-2. Addresses of Flash Sectors in F28055 and F28054 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3E 8000 – 0x3E 8FFF Sector J (4K x 16) 0x3E 9000 – 0x3E 9FFF Sector I (4K x 16) 0x3E A000 – 0x3E BFFF Sector H (8K x 16) 0x3E C000 – 0x3E DFFF Sector G (8K x 16) 0x3E E000 – 0x3E FFFF Sector F (8K x 16) 0x3F 0000 – 0x3F 1FFF Sector E (8K x 16) 0x3F 2000 – 0x3F 3FFF Sector D (8K x 16) 0x3F 4000 – 0x3F 5FFF Sector C (8K x 16) 0x3F 6000 – 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 – 0x3F 7FFF Sector A (4K x 16) Table 2-3. Addresses of Flash Sectors in F28053, F28052, and F28051 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 0000 – 0x3F 1FFF Sector E (8K x 16) 0x3F 2000 – 0x3F 3FFF Sector D (8K x 16) 0x3F 4000 – 0x3F 5FFF Sector C (8K x 16) 0x3F 6000 – 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 – 0x3F 7FFF Sector A (4K x 16) Table 2-4. Addresses of Flash Sectors in F28050 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 4000 – 0x3F 5FFF Sector C (8K x 16) 0x3F 6000 – 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 – 0x3F 7FFF Sector A (4K x 16) Copyright © 2012, Texas Instruments Incorporated Device Overview 13 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations will appear in reverse order on the memory bus of the CPU. This action can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The CPU supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable, and by default, it protects the selected zones. The wait-states for the various spaces in the memory map area are listed in Table 2-5. Table 2-5. Wait-States AREA WAIT-STATES (CPU) COMMENTS M0 and M1 SARAMs 0-wait Fixed Peripheral Frame 0 0-wait Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready. 2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur a 1-cycle stall (1-cycle delay). Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral. 2-wait (reads) Peripheral Frame 3 0-wait (writes) Assumes no conflict between CPU and CLA. 2-wait (reads) Cycles can be extended by peripheral-generated ready. L0 SARAM 0-wait data and program Assumes no CPU conflicts L1 SARAM 0-wait data and program Assumes no CPU conflicts L2 SARAM 0-wait data and program Assumes no CPU conflicts L3 SARAM 0-wait data and program Assumes no CPU conflicts OTP Programmable Programmed via the Flash registers. 1-wait minimum 1-wait is minimum number of wait states allowed. FLASH Programmable Programmed via the Flash registers. 0-wait Paged min 1-wait Random min Random ≥ Paged FLASH Password 16-wait fixed Wait states of password locations are fixed. Boot-ROM 0-wait 14 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.3 Brief Descriptions 2.3.1 CPU The 2805x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28xbased controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. Each C28x-based controller, including the 2805x device, is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language, but also enabling development of math algorithms using C/C++. The device is as efficient at MCU math tasks as it is at system control tasks. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this feature the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-leveldeep protected pipeline with pipelined memory accesses. This pipelining enables the device to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. 2.3.2 Control Law Accelerator (CLA) The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started by software or a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to completion. When a task completes the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP, and the Comparator and DAC registers. Dedicated message RAMs provide a method to pass additional data between the main CPU and the CLA. 2.3.3 Memory Bus (Harvard Bus Architecture) As with many MCU-type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows: Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.) Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.) Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.) Copyright © 2012, Texas Instruments Incorporated Device Overview 15 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.3.4 Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports CLA access and both 16- and 32-bit accesses (called peripheral frame 3). 2.3.5 Real-Time JTAG and Analysis The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug. Additionally, the devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations while the processor is running and executing code and servicing interrupts. The user can also single step through non-time-critical code while enabling timecritical interrupts to be serviced without interference. The device implements the real-time mode in hardware within the CPU. This feature is unique to the 28x family of devices, and requires no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable break events when a match occurs. These devices do not support boundary scan; however, IDCODE and BYPASS features are available if the following considerations are taken into account. The IDCODE does not come by default. The user needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For BYPASS instruction, the first shifted DR value would be 1. 2.3.6 Flash The F28055 and F28054 devices contain 64K x 16 of embedded flash memory, segregated into six 8K x 16 sectors and four 4K x 16 sectors. The F28053, F28052, and F28051 devices contain 32K x 16 of embedded flash memory, segregated into three 8K x 16 sectors and two 4K x 16 sectors. The F28050 device contains 16K x 16 of embedded flash memory, segregated into one 8K x 16 sector and two 4K x 16 sectors. The devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase or program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, the flash/OTP can be used to execute code or store data information. NOTE The Flash and OTP wait-states can be configured by the application. This feature allows applications running at slower frequencies to configure the flash to use fewer wait-states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5). (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture 16 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.3.7 M0, M1 SARAMs All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer, which makes for easier programming in high-level languages. 2.3.8 L0 SARAM, and L1, L2, and L3 DPSARAMs The device contains up to 8K x 16 of single-access RAM. To ascertain the exact size for a given device, see the device-specific memory map figures in Section 2.2. This block is mapped to both program and data space. Block L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2 are both 1K in size, and together with L0, are shared with the CLA which can ultilize these blocks for its data space. Block L3 is 4K in size and is shared with the CLA which can ultilize this block for its program space. DPSARAM refers to the dual-port configuration of these blocks. 2.3.9 Boot ROM The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 2-6. Boot Mode Selection MODE GPIO37/TDO GPIO34/COMP2OUT/ TRST MODE COMP3OUT 3 1 1 0 GetMode 2 1 0 0 Wait (see Section 2.3.10 for description) 1 0 1 0 SCI 0 0 0 0 Parallel IO EMU x x 1 Emulation Boot 2.3.9.1 Emulation Boot When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid, then the Wait boot option is used. All boot mode options can be accessed in emulation boot. 2.3.9.2 GetMode The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP. Copyright © 2012, Texas Instruments Incorporated Device Overview 17 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.3.9.3 Peripheral Pins Used by the Bootloader Table 2-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if these conflict with any of the peripherals you would like to use in your application. Table 2-7. Peripheral Bootload Pins BOOTLOADER PERIPHERAL LOADER PINS SCI SCIRXDA (GPIO28) SCITXDA (GPIO29) Parallel Boot Data (GPIO31,30,5:0) 28x Control (GPIO26) Host Control (GPIO27) SPI SPISIMOA (GPIO16) SPISOMIA (GPIO17) SPICLKA (GPIO18) SPISTEA (GPIO19) I2C SDAA (GPIO28) SCLA (GPIO29) CAN CANRXA (GPIO30) CANTXA (GPIO31) 2.3.10 Security The TMS320F2805x device supports high levels of security with a dual-zone (Z1/Z2) feature to protect user's firmware from being reverse-engineered. The dual-zone feature enables the user to co-develop application software with a third-party or sub-contractor by preventing visibility into each other's software IP. The security features a 128-bit password (hardcoded for 16 wait states) for each zone, which the user programs into the USER-OTP. Each zone has its own dedicated USER-OTP, which needs to be programmed by the user with the required security settings, including the 128-bit password. Since OTP cannot be erased, in order to provide the user with the flexibility of changing security-related settings and passwords multiple times, a 32-bit link pointer is stored at the beginning of each USER-OTP. Considering the fact that user can only flip a ‘1’ in USER-OTP to ‘0’, the most significant bit position in the link pointer, programmed as 0, defines the USER-OTP region (zone-select) for each zone in which security-related settings and passwords are stored. Table 2-8. Location of Zone-Select Block Based on Link Pointer Zx LINK POINTER VALUE ADDRESS OFFSET FOR ZONE-SELECT 32’bxx111111111111111111111111111111 0x10 32’bxx111111111111111111111111111110 0x20 32’bxx11111111111111111111111111110x 0x30 32’bxx1111111111111111111111111110xx 0x40 32’bxx111111111111111111111111110xxx 0x50 32’bxx11111111111111111111111110xxxx 0x60 32’bxx1111111111111111111111110xxxxx 0x70 32’bxx111111111111111111111110xxxxxx 0x80 32’bxx11111111111111111111110xxxxxxx 0x90 32’bxx1111111111111111111110xxxxxxxx 0xa0 32’bxx111111111111111111110xxxxxxxxx 0xb0 32’bxx11111111111111111110xxxxxxxxxx 0xc0 32’bxx1111111111111111110xxxxxxxxxxx 0xd0 32’bxx111111111111111110xxxxxxxxxxxx 0xe0 32’bxx11111111111111110xxxxxxxxxxxxx 0xf0 18 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-8. Location of Zone-Select Block Based on Link Pointer (continued) Zx LINK POINTER VALUE ADDRESS OFFSET FOR ZONE-SELECT 32’bxx1111111111111110xxxxxxxxxxxxxx 0x100 32’bxx111111111111110xxxxxxxxxxxxxxx 0x110 32’bxx11111111111110xxxxxxxxxxxxxxxx 0x120 32’bxx1111111111110xxxxxxxxxxxxxxxxx 0x130 32’bxx111111111110xxxxxxxxxxxxxxxxxx 0x140 32’bxx11111111110xxxxxxxxxxxxxxxxxxx 0x150 32’bxx1111111110xxxxxxxxxxxxxxxxxxxx 0x160 32’bxx111111110xxxxxxxxxxxxxxxxxxxxx 0x170 32’bxx11111110xxxxxxxxxxxxxxxxxxxxxx 0x180 32’bxx1111110xxxxxxxxxxxxxxxxxxxxxxx 0x190 32’bxx111110xxxxxxxxxxxxxxxxxxxxxxxx 0x1a0 32’bxx11110xxxxxxxxxxxxxxxxxxxxxxxxx 0x1b0 32’bxx1110xxxxxxxxxxxxxxxxxxxxxxxxxx 0x1c0 32’bxx110xxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1d0 32’bxx10xxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1e0 32’bxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1f0 Table 2-9. Zone-Select Block Organization in USER-OTP 16-BIT ADDRESS OFFSET (WITH RESPECT TO OFFSET OF ZONE-SELECT) CONTENT 0x0 Zx-EXEONLYRAM 0x1 0x2 Zx-EXEONLYSECT 0x3 0x4 Zx-GRABRAM 0x5 0x6 Zx-GRABSECT 0x7 0x8 Zx-CSMPSWD0 0x9 0xa Zx-CSMPSWD1 0xb 0xc Zx-CSMPSWD2 0xd 0xe Zx-CSMPSWD3 0xf The Dual Code Security Module (DCSM) is used to protect the Flash/OTP/Lx SARAM blocks/CLA/Secure ROM content. Individual flash sectors and SARAM blocks can be attached to any of the secure zone at start-up time. Secure ROM and the CLA are always attached to Z1. Resources attached to (owned by) one zone do not have any access to code running in the other zone when it is secured. Individual flash sectors, as well as SARAM blocks, can be further protected by enabling the EXEONLY protection. EXEONLY flash sectors or SARAM blocks do not have READ/WRITE access. Only code execution is allowed from such memory blocks. Copyright © 2012, Texas Instruments Incorporated Device Overview 19 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com The security feature prevents unauthorized users from examining memory contents via the JTAG port, executing code from external memory, or trying to boot load an undesirable software that would export the secure memory contents. To enable access to the secure blocks of a particular zone, the user must write a 128-bit value in the zone’s CSMKEY registers that matches the values stored in the password locations in USER-OTP. If the 128 bits of the password locations in USER-OTP of a particular zone are all ones (un-programmed), then the security for that zone gets UNLOCKED as soon as a dummy read is done to the password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case). In addition to the DCSM, the Emulation Code Security Logic (ECSL) has been implemented for each zone to prevent unauthorized users from stepping through secure code. A halt inside secure code will trip the ECSL and break the emulation connection. To allow emulation of secure code while maintaining DCSM protection against secure memory reads, the user must write the lower 64 bits of the USER-OTP password into the zone's CSMKEY register to disable the ECSL. Note that dummy reads of all 128 bits of the password for that particular zone in USER-OTP must still be performed. If the lower 64 bits of the password locations of a particular zone are all zeros, then the ECSL for that zone gets disabled as soon as a dummy read is done to the password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case). When initially debugging a device with the password locations in OTP (that is, secured), the CPU will start running and may execute an instruction that performs an access to ECSL-protected area. If the CPU execution is halted when the program counter belongs to the secure code region, the ECSL will trip and cause the emulator connection to be cut. The solution is to use the Wait boot option. The Wait boot option will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. The user can then exit this mode once the emulator is connected by using one of the emulation boot options as described in the Boot ROM chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5). 2805x devices do not support hardware wait-in-reset mode. To prevent reverse-engineering of the code in secure zone, unauthorized users are prevented from looking at the CPU registers in the CCS Expressions Window. The values in the Expressions Window for all of these registers, except for PC and some status bits, display false values when code is running from a secure zone. This feature gets disabled if the zone is unlocked. NOTE • The USER-OTP contains security-related settings for their respective zone. Execution is not allowed from the USER-OTP; therefore, the user should not keep any code/data in this region. • The 128-bit password must not be programmed to zeros. Doing so would permanently lock the device. • The user must try not to write into the CPU registers through the debugger watch window when code is running/halted from/inside secure zone. This may corrupt the execution of the actual program. 20 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Disclaimer Dual Code Security Module Disclaimer THE DUAL CODE SECURITY MODULE (DCSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE DCSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE DCSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE DCSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 2.3.11 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F2805x devices, 54 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE block. Copyright © 2012, Texas Instruments Incorporated Device Overview 21 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.3.12 External Interrupts (XINT1–XINT3) The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled or disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0–GPIO31 pins. 2.3.13 Internal Zero-Pin Oscillators, Oscillator, and PLL The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to Section 5.2 for timing details. The PLL block can be set in bypass mode. 2.3.14 Watchdog Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either generate an interrupt or a device reset. 2.3.15 Peripheral Clocking The clocks to each individual peripheral can be enabled or disabled to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to the CPU clock. 2.3.16 Low-power Modes The devices are full-static CMOS devices. Three low-power modes are provided: IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode. STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event HALT: This mode basically shuts down the device and places the device in the lowest possible power consumption mode. If the internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is used as the clock source, the crystal oscillator is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPUwatchdog can wake the device from this mode. The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put the device into HALT or STANDBY. 22 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.3.17 Peripheral Frames 0, 1, 2, 3 (PFn) The device segregates peripherals into four sections. The mapping of peripherals is as follows: PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: Flash Waitstate Registers Timers: CPU-Timers 0, 1, 2 Registers DCSM: Dual Zone Security Module Registers ADC: ADC Result Registers CLA Control Law Accelrator Registers and Message RAMs PF1: GPIO: GPIO MUX Configuration and Control Registers eCAN: Enhanced Control Area Network Configuration and Control Registers eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers PF2: SYS: System Control Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Configuration Registers I2C: Inter-Integrated Circuit Module and Registers XINT: External Interrupt Registers PF3: ePWM: Enhanced Pulse Width Modulator Module and Registers Comparators and Comparator Modules Digital Filters: eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers ADC: ADC Status, Control, and Configuration Registers ADC: ADC Result Registers DAC: DAC Control Registers 2.3.18 General-Purpose Input/Output (GPIO) Multiplexer Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This muxing enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This selection is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes. Copyright © 2012, Texas Instruments Incorporated Device Overview 23 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.3.19 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, the counter is automatically reloaded with a 32-bit period value. CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. CPU-Timer 2 is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 2 can be clocked by any one of the following: • SYSCLKOUT (default) • Internal zero-pin oscillator 1 (INTOSC1) • Internal zero-pin oscillator 2 (INTSOC2) • External clock source 2.3.20 Control Peripherals The devices support the following peripherals that are used for embedded control and communication: ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. The type 1 module found on 2805x devices also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced triggering including trip functions based on comparator outputs. eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal. eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals. ADC: The ADC block is a 12-bit converter. The ADC has up to 16 single-ended channels pinned out, depending on the device. The ADC also contains two sample-and-hold units for simultaneous sampling. Comparator and Each comparator block consists of one analog comparator along with an Digital Filter internal 6-bit reference for supplying one input of the comparator. The Subsystems: comparator output signal filtering is achieved using the Digital Filter present on each input line and qualifies the output of the COMP/DAC subsystem. The filtered or unfiltered output of the COMP/DAC subsystem can be configured to be an input to the Digital Compare submodule of the ePWM peripheral. There is also a configurable option to bring the output of the COMP/DAC subsystem onto the GPIO’s. 24 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.3.21 Serial Port Peripherals The devices support the following serial communication peripherals: SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The SPI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. The SCI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. I2C: The inter-integrated circuit (I2C) module provides an interface between an MCU and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive up to 8-bit data to and from the MCU through the I2C module. The I2C contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. eCAN: The eCAN is the enhanced version of the CAN peripheral. The eCAN supports 32 mailboxes, time stamping of messages, and is CAN 2.0B-compliant. Copyright © 2012, Texas Instruments Incorporated Device Overview 25 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.4 Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 2-10. Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 2-11. Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 2-12. Peripheral Frame 3: These are peripherals that are mapped to CLA in addition to their respective Peripheral Frame. See Table 2-13. Table 2-10. Peripheral Frame 0 Registers(1) NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED(2) Device Emulation Registers 0x00 0880 – 0x00 0984 261 Yes System Power Control Registers 0x00 0985 – 0x00 0987 3 Yes FLASH Registers(3) 0x00 0A80 – 0x00 0ADF 96 Yes ADC registers (0 wait read only) 0x00 0B00 – 0x00 0B0F 16 No DCSM Zone 1 Registers 0x00 0B80 – 0x00 0BBF 64 Yes DCSM Zone 2 Registers 0x00 0BC0 – 0x00 0BEF 48 Yes CPU-TIMER0, CPU-TIMER1, CPU-TIMER2 0x00 0C00 – 0x00 0C3F 64 No Registers PIE Registers 0x00 0CE0 – 0x00 0CFF 32 No PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 No CLA Registers 0x00 1400 – 0x00 147F 128 Yes CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 – 0x00 14FF 128 NA CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 – 0x00 157F 128 NA (1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents. (3) The Flash Registers are also protected by the Dual Code Security Module (DCSM). Table 2-11. Peripheral Frame 1 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED eCAN-A Registers 0x00 6000 – 0x00 61FF 512 (1) eCAP1 Registers 0x00 6A00 – 0x00 6A1F 32 No eQEP1 Registers 0x00 6B00 – 0x00 6B3F 64 (1) GPIO Registers 0x00 6F80 – 0x00 6FFF 128 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. 26 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-12. Peripheral Frame 2 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED System Control Registers 0x00 7010 – 0x00 702F 32 Yes SPI-A Registers 0x00 7040 – 0x00 704F 16 No SCI-A Registers 0x00 7050 – 0x00 705F 16 No NMI Watchdog Interrupt Registers 0x00 7060 – 0x00 706F 16 Yes External Interrupt Registers 0x00 7070 – 0x00 707F 16 Yes ADC Registers 0x00 7100 – 0x00 717F 128 (1) I2C-A Registers 0x00 7900 – 0x00 793F 64 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. Table 2-13. Peripheral Frame 3 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED ADC registers 0x00 0B00 – 0x00 0B0F 16 No (0 wait read only) DAC Control Registers 0x00 6400 – 0x00 640F 16 Yes DAC, PGA, Comparator, and Filter Enable 0x00 6410 – 0x00 641F 16 Yes Registers SWITCH Registers 0x00 6420 – 0x00 642F 16 Yes Digital Filter and Comparator Control Registers 0x00 6430 – 0x00 647F 80 Yes LOCK Registers 0x00 64F0 – 0x00 64FF 16 Yes ePWM1 registers 0x00 6800 – 0x00 683F 64 (1) ePWM2 registers 0x00 6840 – 0x00 687F 64 (1) ePWM3 registers 0x00 6880 – 0x00 68BF 64 (1) ePWM4 registers 0x00 68C0 – 0x00 68FF 64 (1) ePWM5 registers 0x00 6900 – 0x00 693F 64 (1) ePWM6 registers 0x00 6940 – 0x00 697F 64 (1) ePWM7 registers 0x00 6980 – 0x00 69BF 64 (1) eCAP1 Registers 0x00 6A00 – 0x00 6A1F 32 No eQEP1 Registers 0x00 6B00 – 0x00 6B3F 64 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. Copyright © 2012, Texas Instruments Incorporated Device Overview 27 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.5 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 2-14. Table 2-14. Device Emulation Registers NAME ADDRESS SIZE (x16) DESCRIPTION EALLOW RANGE PROTECTED DEVICECNF 0x0880 – 2 Device Configuration Register Yes 0x0881 PARTID 0x0882 1 PARTID Register TMS320F28055 0x0105 TMS320F28054 0x0104 TMS320F28053 0x0103 No TMS320F28052 0x0102 TMS320F28051 0x0101 TMS320F28050 0x0100 REVID 0x0883 1 Revision ID 0x0000 - Silicon Rev. 0 - TMX No Register DC1 0x0886 – 2 Device Capability Register 1. 0x0887 The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this register, the module is not present. See Table 2-15. DC2 0x0888 – 2 Device Capability Register 2. 0x0889 The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this register, the module is not present. See Table 2-16. DC3 0x088A – 2 Device Capability Register 3. 0x088B The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this register, the module is not present. See Table 2-17. Table 2-15. Device Capability Register 1 (DC1) Field Descriptions(1) BIT FIELD TYPE DESCRIPTION 31–30 RSVD R = 0 Reserved 29–22 PARTNO R These 8 bits set the PARTNO field value in the PARTID register for the device. They are readable in the PARTID[7:0] register bits. 21–14 RSVD R = 0 Reserved 13 CLA R CLA is present when this bit is set. 12–7 RSVD R = 0 Reserved 6 L3 R L3 is present when this bit is set. 5 L2 R L2 is present when this bit is set. 4 L1 R L1 is present when this bit is set. 3 L0 R L0 is present when this bit is set. 2 RSVD R = 0 Reserved 1–0 RSVD R = 0 Reserved (1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same value that is read back from the reserved bits. These bits are reserved for future enhancements. 28 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-16. Device Capability Register 2 (DC2) Field Descriptions(1) BIT FIELD TYPE DESCRIPTION 31–28 RSVD R = 0 Reserved 27 eCAN-A R eCAN-A is present when this bit is set. 26–17 RSVD R = 0 Reserved 16 EQEP-1 R eQEP-1 is present when this bit is set. 15–13 RSVD R = 0 Reserved 12 ECAP-1 R eCAP-1 is present when this bit is set. 11–9 RSVD R = 0 Reserved 8 I2C-A R I2C-A is present when this bit is set. 7–5 RSVD R = 0 Reserved 4 SPI-A R SPI-A is present when this bit is set. 3 RSVD R = 0 Reserved 2 SCI-C R SCI-C is present when this bit is set. 1 SCI-B R SCI-B is present when this bit is set. 0 SCI-A R SCI-A is present when this bit is set. (1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same value that is read back from the reserved bits. These bits are reserved for future enhancements. Table 2-17. Device Capability Register 3 (DC3) Field Descriptions(1) BIT FIELD TYPE DESCRIPTION 31–20 RSVD R = 0 Reserved 19 CTRIPFIL7 R CTRIPFIL7(B7) is present when this bit is set. 18 CTRIPFIL6 R CTRIPFIL6(B6) is present when this bit is set. 17 CTRIPFIL5 R CTRIPFIL5(B4) is present when this bit is set. 16 CTRIPFIL4 R CTRIPFIL4(A6) is present when this bit is set. 15 CTRIPFIL3 R CTRIPFIL3(B1) is present when this bit is set. 14 CTRIPFIL2 R CTRIPFIL2(A3) is present when this bit is set. 13 CTRIPFIL1 R CTRIPFIL1(A1) is present when this bit is set. 12–8 RSVD R = 0 Reserved 7 RSVD R = 0 Reserved 6 ePWM7 R ePWM7 is present when this bit is set. 5 ePWM6 R ePWM6 is present when this bit is set. 4 ePWM5 R ePWM5 is present when this bit is set. 3 ePWM4 R ePWM4 is present when this bit is set. 2 ePWM3 R ePWM3 is present when this bit is set. 1 ePWM2 R ePWM2 is present when this bit is set. 0 ePWM1 R ePWM1 is present when this bit is set. (1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same value that is read back from the reserved bits. These bits are reserved for future enhancements. Copyright © 2012, Texas Instruments Incorporated Device Overview 29 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.6 VREG, BOR, POR Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This feature eliminates the cost and space of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode. 2.6.1 On-chip Voltage Regulator (VREG) A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the application. 2.6.1.1 Using the On-chip VREG To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum) capacitance for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. 2.6.1.2 Disabling the On-chip VREG To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high. 30 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION I/O Pin In Out DIR (0 = Input, 1 = Output) (Force Hi-Z When High) SYSRS C28x Core Sync RS XRS PLL + Clocking Logic MCLKRS VREGHALT Deglitch Filter On-Chip Voltage Regulator (VREG) VREGENZ POR/BOR Generating Module XRS Pin SYSCLKOUT WDRST (A) JTAG TCK Detect Logic PBRS (B) Internal Weak PU TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.6.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled (VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 4.3 for the various trip points as well as the delay time for the device to release the XRS pin after the undervoltage or over-voltage condition is removed. Figure 2-5 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO BOR functions, a bit is provided in the BORCFG register. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for details. A. WDRST is the reset signal from the CPU-watchdog. B. PBRS is the reset signal from the POR/BOR module. Figure 2-5. VREG + POR + BOR + Reset Signal Connectivity Copyright © 2012, Texas Instruments Incorporated Device Overview 31 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.7 System Control This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. Table 2-18. PLL, Clocking, Watchdog, and Low-Power Mode Registers NAME ADDRESS SIZE (x16) DESCRIPTION(1) BORCFG 0x00 0985 1 BOR Configuration Register XCLK 0x00 7010 1 XCLKOUT Control PLLSTS 0x00 7011 1 PLL Status Register CLKCTL 0x00 7012 1 Clock Control Register PLLLOCKPRD 0x00 7013 1 PLL Lock Period INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register PCLKCR4 0x00 7024 1 Peripheral Clock Control Register 4 WDKEY 0x00 7025 1 Watchdog Reset Key Register WDCR 0x00 7029 1 Watchdog Control Register (1) All registers in this table are EALLOW protected. 32 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION PCLKCR0/1/3/4 (System Ctrl Regs) LOSPCP (System Ctrl Regs) I/O Clock Enables LSPCLK Peripheral Registers SPI-A, SCI-A, SCI-B, SCI-C SYSCLKOUT Clock Enables Peripheral Registers I/O eCAP1, eQEP1 Clock Enables Peripheral Registers ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7 I/O Clock Enables Peripheral Registers I/O I2C-A Clock Enables ADC 9 Ch 12-Bit ADC Registers Clock Enables AFE AFE Registers 7 Ch GPIO Mux Analog C28x Core CLKIN Peripheral I/O eCAN-A Registers /2 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 2-6 shows the various clock domains that are discussed. Figure 2-7 shows the various clock sources (both internal and external) that can provide a clock for device operation. A. CLKIN is the clock into the CPU. CLKIN is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT). Figure 2-6. Clock and Reset Domains Copyright © 2012, Texas Instruments Incorporated Device Overview 33 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION INTOSC1TRIM Reg (A) Internal OSC 1 (10 MHz) OSCE CLKCTL[INTOSC1OFF] WAKEOSC CLKCTL[INTOSC1HALT] INTOSC2TRIM Reg (A) Internal OSC 2 (10 MHz) OSCE CLKCTL[INTOSC2OFF] CLKCTL[INTOSC2HALT] 1 = Turn OSC Off 1 = Ignore HALT 1 = Turn OSC Off 1 = Ignore HALT XCLK[XCLKINSEL] 0 = GPIO38 1 = GPIO19 GPIO19 or GPIO38 CLKCTL[XCLKINOFF] 0 0 1 (Crystal) OSC XCLKIN X1 X2 CLKCTL[XTALOSCOFF] 0 = OSC on (default on reset) 1 = Turn OSC off 0 1 0 1 OSC1CLK OSCCLKSRC1 WDCLK OSC2CLK 0 1 CLKCTL[WDCLKSRCSEL] (OSC1CLK on XRS reset) CLKCTL[OSCCLKSRCSEL] CLKCTL[TRM2CLKPRESCALE] CLKCTL[TMR2CLKSRCSEL] OSCCLKSRC2 11 Prescale /1, /2, /4, /8, /16 00 01, 10, 11 CPUTMR2CLK SYNC Edge Detect 10 01 CLKCTL[OSCCLKSRC2SEL] SYSCLKOUT WAKEOSC (Oscillators enabled when this signal is high) EXTCLK XTAL XCLKIN (OSC1CLK on XRS reset) OSCCLK PLL Missing-Clock-Detect Circuit (B) CPU-Watchdog TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. Register loaded from TI OTP-based calibration function. B. See Section 2.7.4 for details on missing clock detection. Figure 2-7. Clock Tree 34 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION External Clock Signal (Toggling 0−VDDIO) XCLKIN/GPIO19/38 X2 NC X1 X1 X2 Crystal XCLKIN/GPIO19/38 Turn off XCLKIN path in CLKCTL register Rd CL1 CL2 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.7.1 Internal Zero-Pin Oscillators The F2805x devices contain two independent internal zero-pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user. The center frequency of these oscillators is determined by their respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See Section 5.2.1 for more information on these oscillators. 2.7.2 Crystal Oscillator Option The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table 2-19. Furthermore, ESR range = 30 to 150 Ω. Table 2-19. Typical Specifications for External Quartz Crystal(1) FREQUENCY (MHz) Rd (Ω) CL1 (pF) CL2 (pF) 5 2200 18 18 10 470 15 15 15 0 15 15 20 0 12 12 (1) Cshunt should be less than or equal to 5 pF. Figure 2-8. Using the On-chip Crystal Oscillator NOTE 1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and crystal. The value is usually approximately twice the value of the crystal's load capacitance. 2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers. 3. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range. Figure 2-9. Using a 3.3-V External Oscillator Copyright © 2012, Texas Instruments Incorporated Device Overview 35 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.7.3 PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. The watchdog module can be re-enabled (if need be) after the PLL module has stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is at least 50 MHz. Table 2-20. PLL Settings SYSCLKOUT (CLKIN) PLLCR[DIV] VALUE(1) (2) PLLSTS[DIVSEL] = 0 or 1(3) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3 0000 (PLL bypass) OSCCLK/4 (Default)(1) OSCCLK/2 OSCCLK 0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1 0010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 (OSCCLK * 2)/1 0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 (OSCCLK * 3)/1 0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 (OSCCLK * 4)/1 0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 (OSCCLK * 5)/1 0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 (OSCCLK * 6)/1 0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 (OSCCLK * 7)/1 1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 (OSCCLK * 8)/1 1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 (OSCCLK * 9)/1 1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 (OSCCLK * 10)/1 1011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 (OSCCLK * 11)/1 1100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 (OSCCLK * 12)/1 (1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic has no effect. (2) This register is EALLOW protected. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for more information. (3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes the PLLSTS[DIVSEL] configuration to /1.) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. Table 2-21. CLKIN Divide Options PLLSTS [DIVSEL] CLKIN DIVIDE 0 /4 1 /4 2 /2 3 /1 36 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 The PLL-based clock module provides four modes of operation: • INTOSC1 (Internal Zero-pin Oscillator 1): INTOSC1 is the on-chip internal oscillator 1. INTOSC1 can provide the clock for the Watchdog block, core and CPU-Timer 2. • INTOSC2 (Internal Zero-pin Oscillator 2): INTOSC2 is the on-chip internal oscillator 2. INTOSC2 can provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen for the Watchdog block, core and CPU-Timer 2. • Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 3-1 for details. • External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows the on-chip (crystal) oscillator to be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input (forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable at boot time. Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock source must be disabled (using the CLKCTL register) before switching clocks. Table 2-22. Possible PLL Configuration Modes PLL MODE REMARKS PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block is disabled in this mode. The PLL block being disabled can be useful in reducing 0, 1 OSCCLK/4 PLL Off system noise and for low-power operation. The PLLCR register must first be set to 2 OSCCLK/2 0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is 3 OSCCLK/1 derived directly from the input clock on either X1/X2, X1 or XCLKIN. PLL Bypass is the default PLL configuration upon power-up or after an external 0, 1 OSCCLK/4 PLL Bypass reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or 2 OSCCLK/2 while the PLL locks to a new frequency after the PLLCR register has been 3 OSCCLK/1 modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the 0, 1 OSCCLK * n/4 PLL Enable PLLCR the device will switch to PLL Bypass mode until the PLL locks. 2 OSCCLK * n/2 3 OSCCLK * n/1 2.7.4 Loss of Input Clock (NMI Watchdog Function) The 2805x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1 or INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limpmode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz. When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt. Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or the NMI watchdog counter can issue a reset when the counter overflows. In addition to this action, the Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a shut-down procedure for the system. If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a preprogrammed time interval. Figure 2-10 shows the interrupt mechanisms involved. Copyright © 2012, Texas Instruments Incorporated Device Overview 37 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION NMIFLG[NMINT] 1 0 Generate Interrupt Pulse When Input = 1 NMINT Latch Clear Set Clear NMIFLGCLR[NMINT] XRS 0 NMICFG[CLOCKFAIL] Latch Clear Clear Set XRS NMIFLG[CLOCKFAIL] NMI Watchdog SYSCLKOUT SYSRS NMIRS NMIWDPRD[15:0] NMIWDCNT[15:0] NMIFLGCLR[CLOCKFAIL] SYNC? NMIFLGFRC[CLOCKFAIL] SYSCLKOUT See System Control Section CLOCKFAIL TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 2-10. NMI-watchdog 2.7.5 CPU-Watchdog Module The CPU-watchdog module on the 2805x device is similar to the one used on the 281x, 280x, and 283xx devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this occurrence, the user must disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter. Figure 2-11 shows the various functional blocks within the watchdog module. Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPUwatchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock). NOTE The CPU-watchdog is different from the NMI watchdog. The CPU-watchdog is the legacy watchdog that is present in all 28x devices. NOTE Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent the capacitor from getting fully charged. Such a circuit would also help in detecting failure of the flash memory. 38 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION /512 WDCLK WDCR (WDPS[2:0]) WDCLK WDCNTR(7:0) WDKEY(7:0) Good Key 1 0 1 WDCR (WDCHK[2:0]) Bad WDCHK Key WDCR (WDDIS) Clear Counter SCSR (WDENINT) Watchdog Prescaler Generate Output Pulse (512 OSCCLKs) 8-Bit Watchdog Counter CLR WDRST WDINT Watchdog 55 + AA Key Detector XRS Core-reset WDRST(A) Internal Pullup TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. The WDRST signal is driven low for 512 OSCCLK cycles. Figure 2-11. CPU-watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that the signal can wake the device from STANDBY (if enabled). See Section 2.8, Low-power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset. Copyright © 2012, Texas Instruments Incorporated Device Overview 39 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.8 Low-power Modes Block Table 2-23 summarizes the various modes. Table 2-23. Low-power Modes MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT(1) IDLE 00 On On On XRS, CPU-watchdog interrupt, any enabled interrupt STANDBY 01 On Off Off XRS, CPU-watchdog interrupt, GPIO (CPU-watchdog still running) Port A signal, debugger(2) Off (on-chip crystal oscillator and XRS, GPIO Port A signal, debugger(2), HALT(3) 1X PLL turned off, zero-pin oscillator Off Off CPU-watchdog and CPU-watchdog state dependent on user code.) (1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power mode will not be exited and the device will go back into the indicated low power mode. (2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off. (3) The WDCLK must be active for the device to go into HALT mode. The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signals will wake the device in the GPIOLPMSEL register. The selected signals are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register. NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for more details. 2.9 Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number SPRA963) help to understand the thermal metrics and definitions. 40 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 41 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 21 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 80 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 VSSA VSS VDDIO GPIO26/SCIRXDC TEST2 GPIO9/EPWM5B/SCITXDB GPIO30/CANRXA/SCIRXDB/EPWM7A GPIO31/CANTXA/SCITXDB/EPWM7B GPIO27/SCITXDC PFCGND ADCINB7 (op-amp) ADCINB0 ADCINB6 (op-amp) ADCINB5 M2GND ADCINB4 (op-amp) ADCINB3 ADCINA7 ADCINA6 (op-amp) VREFLO GPIO23/EQEP1I/SCIRXDB GPIO11/EPWM6B/SCIRXDB GPIO5/EPWM3B/SPISIMOA/ECAP1 GPIO4/EPWM3A GPIO40/EPWM7A GPIO10/EPWM6A/ADCSOCBO GPIO3/EPWM2B/SPISOMIA/CTRIPM2OUT (COMP2OUT) GPIO2/EPWM2A GPIO1/EPWM1B/CTRIPM1OUT (COMP1OUT) GPIO0/EPWM1A VDDIO VREGENZ VSS VDD GPIO34/CTRIPM2OUT (COMP2OUT)/CTRIPPFCOUT (COMP3OUT) GPIO15/TZ1/CTRIPM1OUT/SCIRXDB GPIO13/TZ2/CTRIPM2OUT GPIO14/TZ3/CTRIPPFCOUT/SCITXDB GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT (COMP1OUT) GPIO21/EQEP1B/EPWM7B/CTRIPM2OUT (COMP2OUT) VDDA GPIO22/EQEP1S/SCITXDB XRS GPIO32/SDAA/EPWMSYNCI/EQEP1S GPIO33/SCLA/EPWMSYNCO/EQEP1I GPIO24/ECAP1/EPWM7A GPIO42/EPWM7B/SCITXDC/CTRIPM1OUT (COMP1OUT) VDD VSS TRST ADCBGOUT/ADCINA4 ADCINA5 ADCINA3 (op-amp) ADCINA2 ADCINA1 (op-amp) M1GND ADCINB2 ADCINB1 (op-amp) ADCINA0/VREFOUT VREFHI GPIO29/SCITXDA/SCLA/ /CTRIPPFCOUTTZ3 GPIO36/TMS GPIO35/TDI GPIO37/TDO GPIO38/TCK/XCLKIN GPIO39/SCIRXDC/CTRIPPFCOUT GPIO19/XCLKIN/ /SCIRXDB/ECAP1SPISTEA VDD VSS X1 X2 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA GPIO16/SPISIMOA/EQEP1S/ /CTRIPM2OUTTZ2 GPIO12/ /CTRIPM1OUT/SCITXDATZ1 GPIO25 GPIO8/EPWM5A/ADCSOCAO GPIO17/SPISOMIA/EQEP1I/ /CTRIPPFCOUTTZ3 GPIO18/SPICLKA/SCITXDB/XCLKOUT GPIO28/SCIRXDA/SDAA/TZ2/CTRIPM2OUT TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 3 Device Pins 3.1 Pin Assignments Figure 3-1 shows the 80-pin PN Low-Profile Quad Flatpack (LQFP) pin assignments. Figure 3-1. 2805x 80-Pin PN LQFP (Top View) Copyright © 2012, Texas Instruments Incorporated Device Pins 41 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 3.2 Terminal Functions Table 3-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins could glitch during power up. If this behavior is unacceptable in an application, 1.8 V could be supplied externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V. Table 3-1. Terminal Functions(1) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. JTAG JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. TRST 9 I An external pull-down resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. (↓) TCK See I See GPIO38. JTAG test clock with internal pullup. (↑) GPIO38 TMS See I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is GPIO36 clocked into the TAP controller on the rising edge of TCK.. (↑) TDI See I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected GPIO35 register (instruction or data) on a rising edge of TCK. (↑) TDO See O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register GPIO37 (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive) FLASH TEST2 39 I/O Test Pin. Reserved for TI. Must be left unconnected. (1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown 42 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. CLOCK See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same See frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT GPIO18 O/Z XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to See GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a XCLKIN GPIO19 I crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. and NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal GPIO38 device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This action is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device. On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator X1 52 I must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, this pin must be tied to GND. (I) X2 51 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, X2 must be left unconnected. (O) RESET Device Reset (in) and Watchdog Reset (out). The device has a built-in power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the device. See Section 4.3, Electrical Characteristics, for thresholds of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS XRS 8 I/O pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, TI recommends that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. (I/OD) Copyright © 2012, Texas Instruments Incorporated Device Pins 43 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. ADC, COMPARATOR, ANALOG I/O ADCINA7 24 I ADC Group A, Channel 7 input ADCINA6 23 I ADC Group A, Channel 6 input (op-amp) ADCINA5 10 I ADC Group A, Channel 5 input ADCBGOUT 11 O ADCINA4 I ADC Group A, Channel 4 input ADCINA3 12 I ADC Group A, Channel 3 input (op-amp) ADCINA2 13 I ADC Group A, Channel 2 input ADCINA1 14 I ADC Group A, Channel 1 input (op-amp) ADCINA0 18 I ADC Group A, Channel 0 input VREFOUT Voltage Reference out from buffered DAC V ADC External Reference – used when in ADC external reference mode and used as VREFOUT REFHI 19 I reference ADCINB7 31 I ADC Group B, Channel 7 input (op-amp) ADCINB6 29 I ADC Group B, Channel 6 input (op-amp) ADCINB5 28 I ADC Group B, Channel 5 input ADCINB4 26 I ADC Group B, Channel 4 input (op-amp) ADCINB3 25 I ADC Group B, Channel 3 input ADCINB2 16 I ADC Group B, Channel 2 input ADCINB1 17 I ADC Group B, Channel 1 input (op-amp) ADCINB0 30 I ADC Group B, Channel 0 input VREFLO 22 I ADC Low Reference (always tied to ground) 44 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. CPU AND I/O POWER VDDA 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin. VSSA 21 Analog Ground Pin VDD 6 CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie VDD 54 with 1.2 μF (minimum) ceramic capacitor (10% tolerance) to ground when using internal V VREG. Higher value capacitors may be used, but could impact supply-rail ramp-up time. DD 73 VDDIO 38 Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled VDDIO 70 VSS 7 VSS 37 Digital Ground Pins VSS 53 VSS 72 M1GND 15 Ground pin for M1 channel M2GND 27 Ground pin for M2 channel PFCGND 32 Ground pin for PFC channel VOLTAGE REGULATOR CONTROL SIGNAL VREGENZ 71 I Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG GPIO AND PERIPHERAL SIGNALS (1) GPIO0 69 I/O/Z General-purpose input/output 0 EPWM1A O Enhanced PWM1 Output A GPIO1 68 I/O/Z General-purpose input/output 1 EPWM1B O Enhanced PWM1 Output B CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1) GPIO2 67 I/O/Z General-purpose input/output 2 EPWM2A O Enhanced PWM2 Output A GPIO3 66 I/O/Z General-purpose input/output 3 EPWM2B O Enhanced PWM2 Output B SPISOMIA I/O SPI-A slave out, master in CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2) GPIO4 63 I/O/Z General-purpose input/output 4 EPWM3A O Enhanced PWM3 output A GPIO5 62 I/O/Z General-purpose input/output 5 EPWM3B O Enhanced PWM3 output B SPISIMOA I/O SPI-A slave in, master out ECAP1 I/O Enhanced Capture input/output 1 (1) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for details. Copyright © 2012, Texas Instruments Incorporated Device Pins 45 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. GPIO6 50 I/O/Z General-purpose input/output 6 EPWM4A O Enhanced PWM4 output A EPWMSYNCI I External ePWM sync pulse input EPWMSYNCO O External ePWM sync pulse output GPIO7 49 I/O/Z General-purpose input/output 7 EPWM4B O Enhanced PWM4 output B SCIRXDA I SCI-A receive data GPIO8 45 I/O/Z General-purpose input/output 8 EPWM5A O Enhanced PWM5 output A ADCSOCAO O ADC start-of-conversion A GPIO9 36 I/O/Z General-purpose input/output 9 EPWM5B O Enhanced PWM5 output B SCITXDB O SCI-B transmit data GPIO10 65 I/O/Z General-purpose input/output 10 EPWM6A O Enhanced PWM6 output A ADCSOCBO O ADC start-of-conversion B GPIO11 61 I/O/Z General-purpose input/output 11 EPWM6B O Enhanced PWM6 output B SCIRXDB I SCI-B receive data GPIO12 48 I/O/Z General-purpose input/output 12 TZ1 I Trip Zone input 1 CTRIPM1OUT O CTRIPM1 CTRIPxx output SCITXDA O SCI-A transmit data GPIO13 76 I/O/Z General-purpose input/output 13 TZ2 I Trip zone input 2 CTRIPM2OUT O CTRIPM2 CTRIPxx output GPIO14 77 I/O/Z General-purpose input/output 14 TZ3 I Trip zone input 3 CTRIPPFCOUT O CTRIPPFC output SCITXDB O SCI-B transmit data GPIO15 75 I/O/Z General-purpose input/output 15 TZ1 I Trip zone input 1 CTRIPM1OUT O CTRIPM1 CTRIPxx output SCIRXDB I SCI-B receive data GPIO16 47 I/O/Z General-purpose input/output 16 SPISIMOA I/O SPI-A slave in, master out EQEP1S I/O Enhanced QEP1 strobe TZ2 I Trip Zone input 2 CTRIPM2OUT O CTRIPM2 CTRIPxx output GPIO17 44 I/O/Z General-purpose input/output 17 SPISOMIA I/O SPI-A slave out, master in EQEP1I I/O Enhanced QEP1 index TZ3 I Trip zone input 3 CTRIPPFCOUT O CTRIPPFC output 46 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. GPIO18 43 I/O/Z General-purpose input/output 18 SPICLKA I/O SPI-A clock input/output SCITXDB O SCI-B transmit data XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. GPIO19 55 I/O/Z General-purpose input/output 19 XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if this path is being used for the other periperhal functions SPISTEA I/O SPI-A slave transmit enable input/output SCIRXDB I SCI-B receive data ECAP1 I/O Enhanced Capture input/output 1 GPIO20 78 I/O/Z General-purpose input/output 20 EQEP1A I Enhanced QEP1 input A EPWM7A O Enhanced PWM7 output A CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1) GPIO21 79 I/O/Z General-purpose input/output 21 EQEP1B I Enhanced QEP1 input B EPWM7B O Enhanced PWM7 output B CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2) GPIO22 1 I/O/Z General-purpose input/output 22 EQEP1S I/O Enhanced QEP1 strobe SCITXDB O SCI-B transmit data GPIO23 80 I/O/Z General-purpose input/output 23 EQEP1I I/O Enhanced QEP1 index SCIRXDB I SCI-B receive data GPIO24 4 I/O/Z General-purpose input/output 24 ECAP1 I/O Enhanced Capture input/output 1 EPWM7A O Enhanced PWM7 output A GPIO25 46 I/O/Z General-purpose input/output 25 GPIO26 40 I/O/Z General-purpose input/output 26 SCIRXDC I SCI-C receive data GPIO27 33 I/O/Z General-purpose input/output 27 SCITXDC O SCI-C transmit data GPIO28 42 I/O/Z General-purpose input/output 28 SCIRXDA I SCI-A receive data SDAA I/OD I2C data open-drain bidirectional port TZ2 I Trip zone input 2 CTRIPM2OUT O CTRIPM2 CTRIPxx output Copyright © 2012, Texas Instruments Incorporated Device Pins 47 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. GPIO29 41 I/O/Z General-purpose input/output 29 SCITXDA O SCI-A transmit data SCLA I/OD I2C clock open-drain bidirectional port TZ3 I Trip zone input 3 CTRIPPFCOUT O CTRIPPFC output GPIO30 35 I/O/Z General-purpose input/output 30 CANRXA I CAN receive SCIRXDB I SCI-B receive data EPWM7A O Enhanced PWM7 output A GPIO31 34 I/O/Z General-purpose input/output 31 CANTXA O CAN transmit SCITXDB O SCI-B transmit data EPWM7B O Enhanced PWM7 output B GPIO32 2 I/O/Z General-purpose input/output 32 SDAA I/OD I2C data open-drain bidirectional port EPWMSYNCI I Enhanced PWM external sync pulse input EQEP1S I/O Enhanced QEP1 strobe GPIO33 3 I/O/Z General-Purpose Input/Output 33 SCLA I/OD I2C clock open-drain bidirectional port EPWMSYNCO O Enhanced PWM external synch pulse output EQEP1I I/O Enhanced QEP1 index GPIO34 74 I/O/Z General-Purpose Input/Output 34 CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2) CTRIPPFCOUT O CTRIPPFC output (COMP3OUT) (Direct output of Comparator 3) GPIO35 59 I/O/Z General-Purpose Input/Output 35 TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK GPIO36 60 I/O/Z General-Purpose Input/Output 36 TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. GPIO37 58 I/O/Z General-Purpose Input/Output 37 TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive) GPIO38 57 I/O/Z General-Purpose Input/Output 38 TCK I JTAG test clock with internal pullup XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if this path is being used for the other functions. 48 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. GPIO39 56 I/O/Z General-Purpose Input/Output 39 SCIRXDC I SCI-C receive data CTRIPPFCOUT O CTRIPPFC output GPIO40 64 I/O/Z General-Purpose Input/Output 40 EPWM7A O Enhanced PWM7 output A GPIO42 5 I/O/Z General-Purpose Input/Output 42 EPWM7B O Enhanced PWM7 output B SCITXDC O SCI-C transmit data CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1) Copyright © 2012, Texas Instruments Incorporated Device Pins 49 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 4 Device Operating Conditions 4.1 Absolute Maximum Ratings(1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V Output voltage range, VO –0.3 V to 4.6 V Input clamp current, IIK (VIN < 0 or VIN > VDDIO)(3) ±20 mA Output clamp current, IOK (VO < 0 or VO > VDDIO) ±20 mA Junction temperature range, TJ (4) –40°C to 150°C Storage temperature range, Tstg (4) –65°C to 150°C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Continuous clamp current per pin is ± 2 mA. (4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). 4.2 Recommended Operating Conditions MIN NOM MAX UNIT Device supply voltage, I/O, VDDIO (1) 2.97 3.3 3.63 V Device supply voltage CPU, VDD (When internal 1.71 1.8 1.995 VREG is disabled and 1.8 V is supplied externally) V Supply ground, VSS 0 V Analog supply voltage, VDDA (1) 2.97 3.3 3.63 V Analog ground, VSSA 0 V Device clock frequency (system clock) 2 60 MHz High-level input voltage, VIH (3.3 V) 2 VDDIO + 0.3 V Low-level input voltage, VIL (3.3 V) VSS – 0.3 0.8 V High-level output source current, VOH = VOH(MIN) , IOH All GPIO pins –4 mA Group 2(2) –8 mA Low-level output sink current, VOL = VOL(MAX), IOL All GPIO pins 4 mA Group 2(2) 8 mA Junction temperature, TJ T version –40 105 °C S version –40 125 (1) VDDIO and VDDA should be maintained within approximately 0.3 V of each other. (2) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO28, GPIO29, GPIO30, GPIO31, GPIO36, GPIO37 50 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 4.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH = IOH MAX 2.4 VOH High-level output voltage V IOH = 50 μA VDDIO – 0.2 VOL Low-level output voltage IOL = IOL MAX 0.4 V Pin with pullup All GPIO pins –80 –140 –205 enabled VDDIO = 3.3 V, VIN = 0 V I Input current XRS pin –230 –300 –375 IL (low level) μA Pin with pulldown VDDIO = 3.3 V, VIN = 0 V ±2 enabled Pin with pullup VDDIO = 3.3 V, VIN = VDDIO ±2 Input current enabled IIH (high level) μA Pin with pulldown VDDIO = 3.3 V, VIN = VDDIO 28 50 80 enabled I Output current, pullup or OZ pulldown disabled VO = VDDIO or 0 V ±2 μA CI Input capacitance 2 pF VDDIO BOR trip point Falling VDDIO 2.78 V VDDIO BOR hysteresis 35 mV Supervisor reset release delay Time after BOR/POR/OVR event is removed to XRS 400 800 μs time release VREG VDD output Internal VREG on 1.9 V (1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage (VDD) go out of range. Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 51 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 4.4 Current Consumption Table 4-1. TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT VREG ENABLED VREG DISABLED MODE TEST CONDITIONS IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2) TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX The following peripheral clocks are enabled: • ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7 • eCAP1 • eQEP1 • eCAN-A • CLA • SCI-A, SCI-B, SCI-C • SPI-A Operational • ADC 100 mA(6) 40 mA 90 mA(6) 17 mA 40 mA (Flash) • I2C-A • COMPA1, COMPA3, COMPB1, COMPA6, COMPB4, COMPB5, COMPB7 • CPU-TIMER0, CPU-TIMER1, CPU-TIMER2 All PWM pins are toggled at 60 kHz. All I/O pins are left unconnected.(4)(5) Code is running out of flash with 2 wait-states. XCLKOUT is turned off. Flash is powered down. IDLE XCLKOUT is turned off. 13 mA 15 μA 13 mA 300 μA 15 μA All peripheral clocks are turned off. Flash is powered down. STANDBY 4 mA 15 μA 4 mA 300 μA 15 μA Peripheral clocks are off. Flash is powered down. HALT Peripheral clocks are off. 30 μA 15 μA 15 μA 150 μA 15 μA Input clock is disabled.(7) (1) IDDIO current is dependent on the electrical loading on the I/O pins. (2) In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. (3) The TYP numbers are applicable over room temperature and nominal voltage. (4) The following is done in a loop: • Data is continuously transmitted out of SPI-A, SCI-A, SCI-B, SCI-C, eCAN-A, and I2C-A ports. • The hardware multiplier is exercised. • Watchdog is reset. • ADC is performing continuous conversion. • GPIO17 is toggled. (5) CLA is continuously performing polynomial calculations. (6) For F2805x devices that do not have CLA, subtract the IDD current number for CLA (see Table 4-2) from the IDD (VREG disabled)/IDDIO (VREG enabled) current numbers shown in Table 4-1 for operational mode. (7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator. NOTE The peripheral-I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If the clocks to all the peripherals are turned on at the same time, the current drawn by the device will be more than the numbers specified in the current consumption tables. 52 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 4.4.1 Reducing Current Consumption The 2805x devices incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 4-2 indicates the typical reduction in current consumption achieved by turning off the clocks. Table 4-2. Typical Current Consumption by Various Peripherals (at 60 MHz)(1) PERIPHERAL IDD CURRENT MODULE(2) REDUCTION (mA) ADC 2(3) I2C 3 ePWM 2 eCAP 2 eQEP 2 SCI 2 SPI 2 COMP/DAC 1 PGA 2 CPU-TIMER 1 Internal zero-pin oscillator 0.5 CAN 2.5 CLA 20 (1) All peripheral clocks (except CPU Timer clock) are disabled upon reset. Writing to or reading from peripheral registers is possible only after the peripheral clocks are turned on. (2) For peripherals with multiple instances, the current quoted is per module. For example, the 2 mA value quoted for ePWM is for one ePWM module. (3) This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (IDDA) as well. NOTE IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off. NOTE The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDD current. Following are other methods to reduce power consumption further: • The flash module may be powered down if code is run off SARAM. This method results in a current reduction of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail. • Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function. Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 53 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Operational Power vs Frequency 200 250 300 350 400 450 500 0 10 20 30 40 50 60 70 SYSCLKOUT (MHz) Operational Power (mW) Operational Current vs Frequency 0 20 40 60 80 100 120 140 0 10 20 30 40 50 60 70 SYSCLKOUT (MHz) Operational Current (mA) IDDIO IDDA TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 4.4.2 Current Consumption Graphs (VREG Enabled) Figure 4-1. Typical Operational Current Versus Frequency (F2805x) Figure 4-2. Typical Operational Power Versus Frequency (F2805x) 54 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Typical CLA operational current vs SYSCLKOUT 0 5 10 15 20 25 10 15 20 25 30 35 40 45 50 55 60 SYSCLKOUT (MHz) CLA operational IDDIO current (mA) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 4-3. Typical CLA Operational Current Versus SYSCLKOUT Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 55 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 4.5 Flash Timing Table 4-3. Flash/OTP Endurance for T Temperature Material(1) ERASE/PROGRAM TEMPERATURE MIN TYP MAX UNIT Nf Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 4-4. Flash/OTP Endurance for S Temperature Material(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE Nf Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 4-5. Flash Parameters at 60-MHz SYSCLKOUT PARAMETER TEST MIN TYP MAX UNIT CONDITIONS Program Time 16-Bit Word 50 μs 8K Sector 250 ms 4K Sector 125 ms Erase Time(1) 8K Sector 2 s 4K Sector 2 s IDDP (2) VDD current consumption during Erase/Program cycle VREG disabled 80 mA IDDIOP (2) VDDIO current consumption during Erase/Program cycle 60 IDDIOP (2) VDDIO current consumption during Erase/Program cycle VREG enabled 120 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. Table 4-6. Flash/OTP Access Timing PARAMETER MIN MAX UNIT ta(fp) Paged Flash access time 40 ns ta(fr) Random Flash access time 40 ns ta(OTP) OTP access time 60 ns Table 4-7. Flash Data Retention Duration PARAMETER TEST CONDITIONS MIN MAX UNIT tretention Data retention duration TJ = 55°C 15 years 56 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION OTP Wait State 1 round up to the next highest integer, or 1, whichever is larger ú ú û ù ê ê ë é - ÷ ÷ ø ö ç ç è æ = t t c(SCO) a(OTP) FlashRandom Wait State 1 round up to the next highest integer, or 1, whichever is larger ú ú û ù ê ê ë é - ÷ ÷ ø ö ç ç è æ = × t t c(SCO) a(f r) FlashPage Wait State 1 round up to the next highest integer ( ) ( ) ú ú û ù ê ê ë é - ÷ ÷ ø ö ç ç è æ = · t t c SCO a f p TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 4-8. Minimum Required Flash/OTP Wait-States at Different Frequencies SYSCLKOUT SYSCLKOUT PAGE RANDOM OTP (MHz) (ns) WAIT-STATE(1) WAIT-STATE(1) WAIT-STATE 60 16.67 2 2 3 55 18.18 2 2 3 50 20 1 1 2 45 22.22 1 1 2 40 25 1 1 2 35 28.57 1 1 2 30 33.33 1 1 1 (1) Page and random wait-state must be ≥ 1. The equations to compute the Flash page wait-state and random wait-state in Table 4-8 are as follows: The equation to compute the OTP wait-state in Table 4-8 is as follows: Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 57 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION tw(RSL1) th(boot-mode) (C) V V (3.3 V) DDIO, DDA INTOSC1 X1/X2 XRS (D) Boot-Mode Pins V (1.8 V) DD XCLKOUT I/O Pins User-code dependent User-code dependent Boot-ROM execution starts Peripheral/GPIO function Based on boot code GPIO pins as input GPIO pins as input (state depends on internal PU/PD) (E) tOSCST User-code dependent Address/Data/ Control (Internal) Address/data valid, internal boot-ROM code execution phase td(EX) User-code execution phase tINTOSCST (A) (B) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 5 Power, Reset, Clocking, and Interrupts 5.1 Power Sequencing There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up or power down (GPIO19, GPIO34–38 do not have glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this value is 0.7 V above VDDA) prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. A. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before SYSCLKOUT appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase. B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that XCLKOUT will not be visible at the pin until explicitly configured by user code. C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry. E. The internal pullup or pulldown will take effect when BOR is driven high. Figure 5-1. Power-on Reset 58 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION th(boot-mode) (A) tw(RSL2) INTOSC1 X1/X2 XRS Boot-Mode Pins XCLKOUT I/O Pins Address/Data/ Control (Internal) Boot-ROM Execution Starts User-Code Execution Starts User-Code Dependent User-Code Execution Phase User-Code Dependent User-Code Execution Peripheral/GPIO Function User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) GPIO Pins as Input Peripheral/GPIO Function td(EX) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 5-1. Reset (XRS) Timing Requirements MIN MAX UNIT th(boot-mode) Hold time for boot-mode pins 1000tc(SCO) cycles tw(RSL2) Pulse duration, XRS low on warm reset 32tc(OSCCLK) cycles Table 5-2. Reset (XRS) Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tw(RSL1) Pulse duration, XRS driven by device 600 μs tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles tINTOSCST Start up time, internal zero-pin oscillator 3 μs tOSCST (1) On-chip crystal-oscillator start-up time 1 10 ms (1) Dependent on crystal/resonator and board design. A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Figure 5-2. Warm Reset Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 59 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION OSCCLK SYSCLKOUT Write to PLLCR OSCCLK * 2 (Current CPU Frequency) OSCCLK/2 (CPU frequency while PLL is stabilizing with the desired frequency. This period (PLL lock-up time t ) is 1 ms long.) p OSCCLK * 4 (Changed CPU frequency) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 5-3 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4. Figure 5-3. Example of Effect of Writing Into PLLCR Register 5.2 Clocking 5.2.1 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 2805x MCUs. Table 5-3 lists the cycle times of various clocks. Table 5-3. 2805x Clock Table and Nomenclature (60-MHz Devices) MIN NOM MAX UNIT tc(SCO), Cycle time 16.67 500 ns SYSCLKOUT Frequency 2 60 MHz tc(LCO), Cycle time 16.67 66.67(2) ns LSPCLK(1) Frequency 15(2) 60 MHz tc(ADCCLK), Cycle time 16.67 ns ADC clock Frequency 60 MHz (1) Lower LSPCLK will reduce device power consumption. (2) This value is the default reset value if SYSCLKOUT = 60 MHz. Table 5-4. Device Clocking Requirements/Characteristics MIN NOM MAX UNIT On-chip oscillator (X1/X2 pins) tc(OSC), Cycle time 50 200 ns (Crystal/Resonator) Frequency 5 20 MHz External oscillator/clock source tc(CI), Cycle time (C8) 33.3 200 ns (XCLKIN pin) — PLL Enabled Frequency 5 30 MHz External oscillator/clock source tc(CI), Cycle time (C8) 33.33 250 ns (XCLKIN pin) — PLL Disabled Frequency 4 30 MHz Limp mode SYSCLKOUT Frequency range 1 to 5 MHz (with /2 enabled) tc(XCO), Cycle time (C1) 66.67 2000 ns XCLKOUT Frequency 0.5 15 MHz PLL lock time(1) tp 1 ms (1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum). 60 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Zero-Pin Oscillator Frequency Movement With Temperature 9.6 9.7 9.8 9.9 10 10.1 10.2 10.3 10.4 10.5 10.6 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) Output Frequency (MHz) Typical Max TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 5-5. Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics PARAMETER MIN TYP MAX UNIT Internal zero-pin oscillator 1 (INTOSC1) at 30°C(1) (2) Frequency 10.000 MHz Internal zero-pin oscillator 2 (INTOSC2) at 30°C(1) (2) Frequency 10.000 MHz Step size (coarse trim) 55 kHz Step size (fine trim) 14 kHz Temperature drift(3) 3.03 4.85 kHz/°C Voltage (VDD) drift(3) 175 Hz/mV (1) In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, see the Oscillator Compensation Guide Application Report (literature number SPRAB84). Refer to Figure 5-4 for TYP and MAX values. (2) Frequency range ensured only when VREG is enabled, VREGENZ = VSS. (3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For example: • Increase in temperature will cause the output frequency to increase per the temperature coefficient. • Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient. Figure 5-4. Zero-Pin Oscillator Frequency Movement With Temperature Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 61 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION C4 C3 XCLKOUT(B) XCLKIN(A) C5 C9 C10 C1 C8 C6 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 5.2.2 Clock Requirements and Characteristics Table 5-6. XCLKIN Timing Requirements - PLL Enabled NO. MIN MAX UNIT C9 tf(CI) Fall time, XCLKIN 6 ns C10 tr(CI) Rise time, XCLKIN 6 ns C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % Table 5-7. XCLKIN Timing Requirements - PLL Disabled NO. MIN MAX UNIT C9 tf(CI) Fall time, XCLKIN Up to 20 MHz 6 ns 20 MHz to 30 MHz 2 C10 tr(CI) Rise time, XCLKIN Up to 20 MHz 6 ns 20 MHz to 30 MHz 2 C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % The possible configuration modes are shown in Table 2-22. Table 5-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2) over recommended operating conditions (unless otherwise noted) NO. PARAMETER MIN MAX UNIT C3 tf(XCO) Fall time, XCLKOUT 5 ns C4 tr(XCO) Rise time, XCLKOUT 5 ns C5 tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns C6 tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns (1) A load of 40 pF is assumed for these parameters. (2) H = 0.5tc(XCO) A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. B. XCLKOUT configured to reflect SYSCLKOUT. Figure 5-5. Clock Timing 62 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION CPU TIMER 2 CPU TIMER 0 Watchdog Peripherals (SPI, SCI, ePWM, I2C, eCAP, ADC, eQEP, CLA, eCAN) TINT0 XINT1 Interrupt Control XINT1 XINT1CR(15:0) Interrupt Control XINT2 XINT2CR(15:0) GPIO MUX WDINT INT1 to INT12 NMI XINT2CTR(15:0) XINT3CTR(15:0) CPU TIMER 1 TINT2 Low Power Modes LPMINT WAKEINT Sync SYSCLKOUT MUX XINT2 XINT3 ADC XINT2SOC GPIOXINT1SEL(4:0) GPIOXINT2SEL(4:0) GPIOXINT3SEL(4:0) Interrupt Control XINT3 XINT3CR(15:0) XINT3CTR(15:0) NMI interrupt with watchdog function (See the NMI Watchdog section.) NMIRS System Control (See the System Control section.) INT14 INT13 GPIO0.int GPIO31.int CLOCKFAIL CPUTMR2CLK C28 Core MUX MUX TINT1 PIE Up to 96 Interrupts TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 5.3 Interrupts Figure 5-6 shows how the various interrupt sources are multiplexed. Figure 5-6. External and PIE Interrupt Sources Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 63 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION INT12 MUX INT11 INT2 INT1 CPU (Flag) (Enable) INTx INTx.8 PIEIERx[8:1] PIEIFRx[8:1] MUX INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 From Peripherals or External Interrupts (Enable) (Flag) IFR[12:1] IER[12:1] Global Enable INTM 1 0 PIEACKx (Enable/Flag) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 5-9 shows the interrupts used by 2805x devices. The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior. When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth. Figure 5-7. Multiplexing of Interrupts Using the PIE Block 64 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 5-9. PIE MUXed Peripheral Interrupt Vector Table(1) INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1 (LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC) 0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40 INT2.y Reserved EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT – (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50 INT3.y Reserved EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT – (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60 INT4.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAP1_INT – – – – – – – (eCAP1) 0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70 INT5.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved EQEP1_INT – – – – – – – (eQEP1) 0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80 INT6.y Reserved Reserved Reserved Reserved Reserved Reserved SPITXINTA SPIRXINTA – – – – – – (SPI-A) (SPI-A) 0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90 INT7.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved – – – – – – – – 0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0 INT8.y Reserved Reserved SCITXINTC SCIRXINTC Reserved Reserved I2CINT2A I2CINT1A – – (SCI-C) (SCI-C) – – (I2C-A) (I2C-A) 0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0 INT9.y Reserved Reserved ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA – – (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A) 0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0 INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ePWM16) (ePWM15) (ePWM14) (ePWM13) (ePWM12) (ePWM11) (ePWM10) (ePWM9) 0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0 INT11.y CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1 (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (ePWM16) (ePWM15) (ePWM14) (ePWM13) (ePWM12) (ePWM11) (ePWM10) (ePWM9) 0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0 INT12.y LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3 (CLA) (CLA) – – – – – Ext. Int. 3 0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0 (1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: • No peripheral within the group is asserting interrupts. • No peripheral interrupts are assigned to the group (for example, PIE group 7). Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 65 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 5-10. PIE Configuration and Control Registers NAME ADDRESS SIZE (x16) DESCRIPTION(1) PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA – 6 Reserved 0x0CFF (1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. 66 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION XINT1, XINT2, XINT3 tw(INT) Interrupt Vector td(INT) Address bus (internal) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 5.3.1 External Interrupts Table 5-11. External Interrupt Registers NAME ADDRESS SIZE (x16) DESCRIPTION XINT1CR 0x00 7070 1 XINT1 configuration register XINT2CR 0x00 7071 1 XINT2 configuration register XINT3CR 0x00 7072 1 XINT3 configuration register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register XINT3CTR 0x00 707A 1 XINT3 counter register Each external interrupt can be enabled, disabled, or qualified using positive, negative, or both positive and negative edge. For more information, see the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5). 5.3.1.1 External Interrupt Electrical Data/Timing Table 5-12. External Interrupt Timing Requirements(1) TEST CONDITIONS MIN MAX UNIT tw(INT) (2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. (2) This timing is applicable to any GPIO pin configured for ADCSOC functionality. Table 5-13. External Interrupt Switching Characteristics(1) over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. Figure 5-8. External Interrupt Timing Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 67 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Transmission Line 4.0 pF 1.85 pF Z0 = 50 W (A) Tester Pin Electronics Data Sheet Timing Reference Point Output Under Test 42 W 3.5 nH Device Pin (B) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6 Peripheral Information and Timings 6.1 Parameter Information 6.1.1 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their Letters and symbols and their meanings: meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) 6.1.1.1 General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.1.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 6-1. 3.3-V Test Load Circuit 68 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.2 Control Law Accelerator (CLA) 6.2.1 Control Law Accelerator Device-Specific Information The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Timecritical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the main CPU to perform other system and communication functions concurently. The following is a list of major features of the CLA. • Clocked at the same rate as the main CPU (SYSCLKOUT). • An independent architecture allowing CLA algorithm execution independent of the main C28x CPU. – Complete bus architecture: • Program address bus and program data bus • Data address bus, data read bus, and data write bus – Independent eight-stage pipeline. – 12-bit program counter (MPC) – Four 32-bit result registers (MR0–MR3) – Two 16-bit auxillary registers (MAR0, MAR1) – Status register (MSTF) • Instruction set includes: – IEEE single-precision (32-bit) floating-point math operations – Floating-point math with parallel load or store – Floating-point multiply with parallel add or subtract – 1/X and 1/sqrt(X) estimations – Data type conversions. – Conditional branch and call – Data load and store operations • The CLA program code can consist of up to eight tasks or interrupt service routines. – The start address of each task is specified by the MVECT registers. – No limit on task size as long as the tasks fit within the CLA program memory space. – One task is serviced at a time through to completion. There is no nesting of tasks. – Upon task completion, a task-specific interrupt is flagged within the PIE. – When a task finishes, the next highest-priority pending task is automatically started. • Task trigger mechanisms: – C28x CPU via the IACK instruction – Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example: • Task1: ADCINT1 or EPWM1_INT • Task2: ADCINT2 or EPWM2_INT • Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT • Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT – Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT • Memory and Shared Peripherals: – Two dedicated message RAMs for communication between the CLA and the main CPU. – The C28x CPU can map CLA program and data memory to the main CPU space or CLA space. – The CLA has direct access to the CLA Data ROM that stores the math tables required by the routines in the CLA Math Library. – The CLA has direct access to the ADC Result registers, comparator and DAC registers, eCAP, eQEP, and ePWM registers. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 69 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION CLA_INT1 to CLA_INT8 MVECT1 MIFR MIER MIFRC MVECT2 MIRUN MPERINT1 to MPERINT8 PIE Main 28x CPU CLA Program Memory MMEMCFG MIOVF MICLR MCTL MICLROVF MPISRCSEL1 MVECT3 MVECT4 MVECT5 MVECT6 MVECT7 MVECT8 PU BUS INT11 INT12 Peripheral Interrupts ADCINT1 to ADCINT8 EPWM1_INT to EPWM7_INT ECAP1_INT EQEP1_INT CPU Timer 0 Map to CLA or CPU Space Main CPU Read/Write Data Bus CLA Program Address Bus CLA Program Data Bus Map to CLA or CPU Space CLA Data Memory CLA Data ROM Comparator + DAC Registers ePWM Registers eCAP Registers eQEP Registers ADC Result Registers CLA Shared Message RAMs Main CPU Bus MR0(32) MPC(12) MR1(32) MR3(32) MAR0(32) MSTF(32) MR2(32) MAR1(32) CLA Data Read Address Bus CLA Data Write Data Bus CLA Data Write Address Bus CLA Data Read Data Bus MEALLOW Main CPU Read Data Bus CLA Execution Registers CLA Control Registers SYSCLKOUT CLAENCLK SYSRS LVF LUF IACK CLA Data Bus TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-2. CLA Block Diagram 70 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.2.2 Control Law Accelerator Register Descriptions Table 6-1. CLA Control Registers REGISTER NAME CLA1 SIZE (x16) EALLOW DESCRIPTION(1) ADDRESS PROTECTED MVECT1 0x1400 1 Yes CLA Interrupt/Task 1 Start Address MVECT2 0x1401 1 Yes CLA Interrupt/Task 2 Start Address MVECT3 0x1402 1 Yes CLA Interrupt/Task 3 Start Address MVECT4 0x1403 1 Yes CLA Interrupt/Task 4 Start Address MVECT5 0x1404 1 Yes CLA Interrupt/Task 5 Start Address MVECT6 0x1405 1 Yes CLA Interrupt/Task 6 Start Address MVECT7 0x1406 1 Yes CLA Interrupt/Task 7 Start Address MVECT8 0x1407 1 Yes CLA Interrupt/Task 8 Start Address MCTL 0x1410 1 Yes CLA Control Register MMEMCFG 0x1411 1 Yes CLA Memory Configure Register MPISRCSEL1 0x1414 2 Yes Peripheral Interrupt Source Select Register 1 MIFR 0x1420 1 Yes Interrupt Flag Register MIOVF 0x1421 1 Yes Interrupt Overflow Register MIFRC 0x1422 1 Yes Interrupt Force Register MICLR 0x1423 1 Yes Interrupt Clear Register MICLROVF 0x1424 1 Yes Interrupt Overflow Clear Register MIER 0x1425 1 Yes Interrupt Enable Register MIRUN 0x1426 1 Yes Interrupt RUN Register MPC(2) 0x1428 1 – CLA Program Counter MAR0(2) 0x142A 1 – CLA Aux Register 0 MAR1(2) 0x142B 1 – CLA Aux Register 1 MSTF(2) 0x142E 2 – CLA STF Register MR0(2) 0x1430 2 – CLA R0H Register MR1(2) 0x1434 2 – CLA R1H Register MR2(2) 0x1438 2 – CLA R2H Register MR3(2) 0x143C 2 – CLA R3H Register (1) All registers in this table are DCSM protected (2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes to this register. Table 6-2. CLA Message RAM ADDRESS RANGE SIZE (x16) DESCRIPTION 0x1480 – 0x14FF 128 CLA to CPU Message RAM 0x1500 – 0x157F 128 CPU to CLA Message RAM Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 71 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Digital Value = 0, when input £ 0 V V V Input Analog Voltage V Digital Value 4096 REFHI REFLO REFLO - - = ´ when 0 V input VREFHI < < Digital Value = 4095, when input VREFHI ³ Digital Value = 0, when input £ 0 V 3.3 Input Analog Voltage V Digital Value 4096 REFLO - = ´ when 0 V < input < 3.3 V Digital Value = 4095, when input ³ 3.3 V TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.3 Analog Block 6.3.1 Analog-to-Digital Converter (ADC) 6.3.1.1 Analog-to-Digital Converter Device-Specific Information The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sampleand- hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog input channels. The converter can be configured to run with an internal bandgap reference to create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometric-based conversions. Contrary to previous ADC types, this ADC is not sequencer-based. The user can easily create a series of conversions from a single trigger. However, the basic principle of operation is centered around the configurations of individual conversions, called SOCs, or Start-Of-Conversions. Functions of the ADC module include: • 12-bit ADC core with built-in dual sample-and-hold (S/H) • Simultaneous sampling or sequential sampling modes • Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog voltage is derived by: – Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external reference modes.) – External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when using either internal or external reference modes.) • Runs at full system clock, no prescaling required • Up to 16-channel, multiplexed inputs • 16 SOCs, configurable for trigger, sample window, and channel • 16 result registers (individually addressable) to store conversion values • Multiple trigger sources – S/W – software immediate start – ePWM 1–7 – GPIO XINT2 – CPU Timer 0, CPU Timer 1, CPU Timer 2 – ADCINT1, ADCINT2 • 9 flexible PIE interrupts, can configure interrupt request after any conversion 72 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 6-3. ADC Configuration and Control Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED ADCCTL1 0x7100 1 Yes Control 1 Register ADCCTL2 0x7101 1 Yes Control 2 Register ADCINTFLG 0x7104 1 No Interrupt Flag Register ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register ADCINTOVF 0x7106 1 No Interrupt Overflow Register ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register INTSEL1N2 0x7108 1 Yes Interrupt 1 and 2 Selection Register INTSEL3N4 0x7109 1 Yes Interrupt 3 and 4 Selection Register INTSEL5N6 0x710A 1 Yes Interrupt 5 and 6 Selection Register INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection) SOCPRICTL 0x7110 1 Yes SOC Priority Control Register ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels) ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels) ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels) ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels) ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels) ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels) ADCSOC0CTL to 0x7120 – 1 Yes SOC0 Control Register to SOC15 Control Register ADCSOC15CTL 0x712F ADCREFTRIM 0x7140 1 Yes Reference Trim Register ADCOFFTRIM 0x7141 1 Yes Offset Trim Register COMPHYSTCTL 0x714C 1 Yes Comparator Hysteresis Control Register ADCREV 0x714F 1 No Revision Register Table 6-4. ADC Result Registers (Mapped to PF0) REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED ADCRESULT0 to 0xB00 – 1 No ADC Result 0 Register to ADC Result 15 Register ADCRESULT15 0xB0F Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 73 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION PF0 (CPU) PF2 (CPU) SYSCLKOUT ADCENCLK ADC Channels ADC Core 12-Bit 0-Wait Result Registers ADCINT 1 ADCINT 9 ADCTRIG 1 TINT 0 PIE CPUTIMER 0 ADCTRIG 2 TINT 1 CPUTIMER 1 ADCTRIG 3 TINT 2 CPUTIMER 2 ADCTRIG 4 XINT 2SOC XINT 2 ADCTRIG 5 SOCA 1 EPWM 1 ADCTRIG 6 SOCB 1 ADCTRIG 7 SOCA 2 EPWM 2 ADCTRIG 8 SOCB 2 ADCTRIG 9 SOCA 3 EPWM 3 ADCTRIG 10 SOCB 3 ADCTRIG 11 SOCA 4 EPWM 4 ADCTRIG 12 SOCB 4 ADCTRIG 13 SOCA 5 EPWM 5 ADCTRIG 14 SOCB 5 ADCTRIG 15 SOCA 6 EPWM 6 ADCTRIG 16 SOCB 6 ADCTRIG 17 SOCA 7 EPWM 7 ADCTRIG 18 SOCB 7 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-3. ADC Connections ADC Connections if the ADC is Not Used TI recommends that the connections for the analog power pins be kept, even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application: • VDDA – Connect to VDDIO • VSSA – Connect to VSS • VREFLO – Connect to VSS • ADCINAn, ADCINBn, VREFHI – Connect to VSSA When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (VSSA). When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings. 74 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.1.2 Analog-to-Digital Converter Electrical Data/Timing Table 6-5. ADC Electrical Characteristics PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS Resolution 12 Bits ADC clock 0.5 60 MHz Sample Window (see Table 6-6) 28055, 28054, 28053, 10 63 ADC 28052 Clocks 28051, 28050 24 63 ACCURACY INL (Integral nonlinearity)(1) –4 4 LSB DNL (Differential nonlinearity), no missing codes –1 1.5 LSB Offset error (2) Executing a single self- –20 0 20 LSB recalibration(3) Executing periodic self- –4 0 4 recalibration(4) Overall gain error with internal reference –60 60 LSB Overall gain error with external reference –40 40 LSB Channel-to-channel offset variation –4 4 LSB Channel-to-channel gain variation –4 4 LSB ADC temperature coefficient with internal reference –50 ppm/°C ADC temperature coefficient with external reference –20 ppm/°C VREFLO –100 μA VREFHI 100 μA ANALOG INPUT Analog input voltage with internal reference 0 3.3 V Analog input voltage with external reference VREFLO VREFHI V VREFLO input voltage VSSA 0.66 V VREFHI input voltage(5) 2.64 VDDA V with VREFLO = VSSA 1.98 VDDA Input capacitance 5 pF Input leakage current ±2 μA (1) INL will degrade when the ADC input voltage goes above VDDA. (2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external reference. (3) For more details, see the TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 Piccolo MCU Silicon Errata (literature number SPRZ362). (4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration" section in the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5). (5) VREFHI must not exceed VDDA when using either internal or external reference modes. Table 6-6. ACQPS Values(1) OVERLAP MODE NONOVERLAP MODE Non-PGA {9, 10, 23, 36, 49, 62} {15, 16, 28, 29, 41, 42, 54, 55} PGA {23, 36, 49, 62} {15, 16, 28, 29, 41, 42, 54, 55} (1) ACQPS = 6 can be used for the first sample if it is thrown away. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 75 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ADCSOCAO ADCSOCBO or tw(ADCSOCL) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-7. ADC Power Modes ADC OPERATING MODE CONDITIONS IDDA UNITS Mode A – Operating Mode ADC Clock Enabled 13 mA Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 1) ADC Powered Up (ADCPWDN = 1) Mode B – Quick Wake Mode ADC Clock Enabled 4 mA Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 1) ADC Powered Up (ADCPWDN = 0) Mode C – Comparator-Only Mode ADC Clock Enabled 1.5 mA Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 0) ADC Powered Up (ADCPWDN = 0) Mode D – Off Mode ADC Clock Enabled 0.075 mA Bandgap On (ADCBGPWD = 0) Reference On (ADCREFPWD = 0) ADC Powered Up (ADCPWDN = 0) 6.3.1.2.1 External ADC Start-of-Conversion Electrical Data/Timing Table 6-8. External ADC Start-of-Conversion Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO ) cycles Figure 6-4. ADCSOCAO or ADCSOCBO Timing 6.3.1.2.2 Internal Temperature Sensor Table 6-9. Temperature Sensor Coefficient(1) PARAMETER(2) MIN TYP MAX UNIT TSLOPE Degrees C of temperature movement per measured ADC LSB change 0.18(3) (4) °C/LSB of the temperature sensor TOFFSET ADC output at 0°C of the temperature sensor 1750 LSB (1) The accuracy of the temperature sensor for sensing absolute temperature (temperature in degrees) is not specified. The primary use of the temperature sensor should be to compensate the internal oscillator for temperature drift (this operation is assured as per Table 5-5). (2) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be adjusted accordingly in external reference mode to the external reference voltage. (3) ADC temperature coeffieicient is accounted for in this specification (4) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values relative to an initial value. 76 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ac Rs ADCIN C 5 pF p C 1.6 pF h Switch Typical Values of the Input Circuit Components: Switch Resistance (R ): 3.4 k on W Sampling Capacitor (C ): 1.6 pF h Parasitic Capacitance (C ): 5 pF p Source Resistance (R ): 50 s W 28x DSP Source Signal 3.4 kW Ron ADCPWDN/ ADCBGPWD/ ADCREFPWD/ ADCENABLE Request for ADC Conversion td(PWD) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.1.2.3 ADC Power-Up Control Bit Timing Table 6-10. ADC Power-Up Delays PARAMETER(1) MIN MAX UNIT td(PWD) Delay time for the ADC to be stable after power up 1 ms (1) Timings maintain compatibility to the ADC module. The 2805x ADC supports driving all 3 bits at the same time td(PWD) ms before first conversion. Figure 6-5. ADC Conversion Timing Figure 6-6. ADC Input Impedance Model Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 77 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION SOC0 ADCCLK ADCRESULT 0 S/H Window Pulse to Core ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCINTFLG.ADCINTx SOC1 SOC2 0 2 9 15 22 24 37 Result 0 Latched ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 ADCRESULT 1 EOC0 Pulse EOC1 Pulse Conversion 0 13 ADC Clocks Minimum 7 ADCCLKs 6 ADCCLKs Conversion 1 13 ADC Clocks Minimum 7 ADCCLKs 2 ADCCLKs 1 ADCCLK Analog Input SOC1 Sample Window SOC0 Sample Window SOC2 Sample Window TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.3.1.2.4 ADC Sequential and Simultaneous Timings A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the converter. Figure 6-7. Timing Example for Sequential Mode / Late Interrupt Pulse 78 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Conversion 0 13 ADC Clocks Minimum 7 ADCCLKs SOC0 ADCCLK ADCRESULT 0 S/H Window Pulse to Core ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCINTFLG.ADCINTx SOC1 SOC2 9 15 22 24 37 6 ADCCLKs 0 2 Result 0 Latched Conversion 1 13 ADC Clocks Minimum 7 ADCCLKs ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 ADCRESULT 1 EOC0 Pulse EOC1 Pulse EOC2 Pulse 2 ADCCLKs Analog Input SOC1 Sample Window SOC0 Sample Window SOC2 Sample Window TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the converter. Figure 6-8. Timing Example for Sequential Mode / Early Interrupt Pulse Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 79 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Conversion 0 (A) 13 ADC Clocks Minimum 7 ADCCLKs SOC0 (A/B) ADCCLK ADCRESULT 0 S/H Window Pulse to Core ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCINTFLG .ADCINTx SOC2 (A/B) 9 22 24 37 19 ADCCLKs 0 2 Result 0 (A) Latched Conversion 0 (B) 13 ADC Clocks Minimum 7 ADCCLKs ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 ADCRESULT 1 Result 0 (B) Latched Conversion 1 (A) 13 ADC Clocks ADCRESULT 2 50 EOC0 Pulse EOC1 Pulse EOC2 Pulse 1 ADCCLK 2 ADCCLKs 2 ADCCLKs Analog Input B SOC0 Sample B Window SOC2 Sample B Window Analog Input A SOC0 Sample A Window SOC2 Sample A Window TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the converter. Figure 6-9. Timing Example for Simultaneous Mode / Late Interrupt Pulse 80 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ADCCLK 0 2 9 SOC0 Sample B Window Analog Input B Analog Input A SOC0 Sample A Window 37 50 SOC2 Sample B Window SOC2 Sample A Window 22 24 ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B) ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched ADCRESULT 1 Result 0 (B) Latched ADCRESULT 2 EOC0 Pulse EOC1 Pulse EOC2 Pulse Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks 2 ADCCLKs Minimum 7 ADCCLKs Conversion 1 (A) 13 ADC Clocks Conversion 0 (B) 13 ADC Clocks ADCINTFLG.ADCINTx 19 ADCCLKs TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the converter. Figure 6-10. Timing Example for Simultaneous Mode / Early Interrupt Pulse Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 81 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION 6.02 (SINAD 1.76) N - = TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.3.1.2.5 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. Differential Nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes. Zero Offset Zero error is the difference between the ideal input voltage and the actual input voltage that just causes a transition from an output code of zero to an output code of one. Gain Error The first code transition should occur at an analog value one-half LSB above negative full scale. The last transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Signal-to-Noise Ratio + Distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. 82 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.2 Analog Front End (AFE) 6.3.2.1 Analog Front End Device-Specific Information The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to- Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers (PGAs), and up to four digital filters. Figure 6-11 and Figure 6-12 show the AFE. The comparator output signal filtering is achieved using the Digital Filter present on selective input line and qualifies the output of the COMP/DAC subsystem (see Figure 6-13). The filtered or unfiltered output of the COMP/DAC subsystem can be configured to be an input to the Digital Compare submodule of the ePWM peripheral. Note: The Analog inputs are brought in through the AFE subsystem rather than through an AIO Mux, which is not present. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 83 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ADC VREFHI V /A0 REFOUT B7 PGA G~ = 3, 6, 11 _ + Cmp1 _ + Cmp1 V Buffered DAC Output COMPB7 REFOUT DFSS DAC5 6-bit DAC6 6-bit B7 VREFHI A0 PFCGND B0 A2 A4 B2 A1 PGA G~ = 3, 6, 11 M1GND _ + Cmp2 DAC1 6-bit COMPA1H DFSS _ + Cmp3 COMPA1L DFSS ADCINSWITCH A1 A3 PGA G~ = 3, 6, 11 M1GND Cmp4 COMPA3H DFSS _ + Cmp5 COMPA3L DFSS A3 B1 PGA G~ = 3, 6, 11 M1GND _ + Cmp6 COMPB1H DFSS _ + Cmp7 COMPB1L DFSS B1 DAC2 6-bit Temp Sensor ADCCTL1.TEMPCONV A5 A5 ADCCTL1.REFLOCONV B5 A7 B3 B5 VREFLO B0 A2 A4 B2 _ + ADCINSWITCH VREFLO A7 B3 A6 GAIN AMP G~ = 3 M2GND B4 GAIN AMP G~ = 3 M2GND B6 GAIN AMP G~ = 3 M2GND A6 B4 B6 Legend Cmp - Comparator DFSS - Comparator Trip/Digital Filter Subsystem Block GAIN AMP - Fixed Gain Amplifier PGA - Programmable Gain Amplifier TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-11. 28055, 28054, 28053, 28052, and 28051 Analog Front End (AFE) 84 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ADC VREFHI V /A0 REFOUT _ + Cmp1 V Buffered DAC Output REFOUT DAC6 6-bit VREFHI A0 B0 A2 A4 B2 A1 PGA G~ = 3, 6, 11 M1GND _ + Cmp2 DAC1 6-bit COMPA1H DFSS _ + Cmp3 COMPA1L DFSS ADCINSWITCH A1 A3 PGA G~ = 3, 6, 11 M1GND Cmp4 COMPA3H DFSS _ + Cmp5 COMPA3L DFSS A3 B1 PGA G~ = 3, 6, 11 M1GND _ + Cmp6 COMPB1H DFSS _ + Cmp7 COMPB1L DFSS B1 DAC2 6-bit Temp Sensor ADCCTL1.TEMPCONV A5 A5 ADCCTL1.REFLOCONV B5 A7 B3 B5 VREFLO B0 A2 A4 B2 _ + ADCINSWITCH VREFLO A7 B3 A6 GAIN AMP G~ = 3 M2GND B4 GAIN AMP G~ = 3 M2GND A6 B4 B6 GAIN AMP G~ = 3 M2GND B6 B7 GAIN AMP G~ = 3 PFCGND B7 Legend Cmp - Comparator DFSS - Comparator Trip/Digital Filter Subsystem Block GAIN AMP - Fixed Gain Amplifier PGA - Programmable Gain Amplifier TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 6-12. 28050 Analog Front End (AFE) Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 85 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ePWM 1-7 DCAH DCAL DCBH DCBL D C T R I P S E L GPIO MUX CTRIPOUTPOL SYSCLK Digital Filter CTRIPOUTBYP 1 0 CTRIPxxOUTEN CTRIPOUTxxSTS CTRIPOUTxxFLG CTRIPOUTLATEN 0 1 CTRIPFILCTRL REGISTER CTRIPBYP 0 1 COMPxxPOL COMPxxH 0 1 COMPxxPOL COMPxxL COMPxINPEN ENABLES CTRIPEN (to all ePWM modules) CTRIPxx0CTLREGISTER 0 1 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-13. Comparator Trip/Digital Filter Subsystem 86 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.2.2 Analog Front End Register Descriptions Table 6-11. DAC Control Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED DAC1CTL 0x6400 1 Yes DAC1 Control Register DAC2CTL 0x6401 1 Yes DAC2 Control Register DAC3CTL 0x6402 1 Yes DAC3 Control Register DAC4CTL 0x6403 1 Yes DAC4 Control Register DAC5CTL 0x6404 1 Yes DAC5 Control Register VREFOUTCTL 0x6405 1 Yes VREFOUT DAC Control Register Table 6-12. DAC, PGA, Comparator, and Filter Enable Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED DACEN 0x6410 1 Yes DAC Enables Register VREFOUTEN 0x6411 1 Yes VREFOUT Enable Register PGAEN 0x6412 1 Yes Programmable Gain Amplifier Enable Register COMPEN 0x6413 1 Yes Comparator Enable Register AMPM1_GAIN 0x6414 1 Yes Motor Unit 1 PGA Gain Controls Register AMPM2_GAIN 0x6415 1 Yes Motor Unit 2 PGA Gain Controls Register AMP_PFC_GAIN 0x6416 1 Yes PFC PGA Gain Controls Register Table 6-13. SWITCH Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED ADCINSWITCH 0x6421 1 Yes ADC Input-Select Switch Control Register Reserved 0x6422 – 7 Yes Reserved 0x6428 COMPHYSTCTL 0x6429 1 Yes Comparator Hysteresis Control Register Table 6-14. Digital Filter and Comparator Control Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED CTRIPA1ICTL 0x6430 1 Yes CTRIPA1 Filter Input and Function Control Register CTRIPA1FILCTL 0x6431 1 Yes CTRIPA1 Filter Parameters Register CTRIPA1FILCLKCTL 0x6432 1 Yes CTRIPA1 Filter Sample Clock Control Register Reserved 0x6433 1 Yes Reserved CTRIPA3ICTL 0x6434 1 Yes CTRIPA3 Filter Input and Function Control Register CTRIPA3FILCTL 0x6435 1 Yes CTRIPA3 Filter Parameters Register CTRIPA3FILCLKCTL 0x6436 1 Yes CTRIPA3 Filter Sample Clock Control Register Reserved 0x6437 1 Yes Reserved CTRIPB1ICTL 0x6438 1 Yes CTRIPB1 Filter Input and Function Control Register CTRIPB1FILCTL 0x6439 1 Yes CTRIPB1 Filter Parameters Register CTRIPB1FILCLKCTL 0x643A 1 Yes CTRIPB1 Filter Sample Clock Control Register Reserved 0x643B 1 Yes Reserved Reserved 0x643C 1 Yes Reserved CTRIPM1OCTL 0x643D 1 Yes CTRIPM1 CTRIP Filter Output Control Register CTRIPM1STS 0x643E 1 Yes CTRIPM1 CTRIPxx Outputs Status Register CTRIPM1FLGCLR 0x643F 1 Yes CTRIPM1 CTRIPxx Flag Clear Register Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 87 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-14. Digital Filter and Comparator Control Registers (continued) REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED Reserved 0x6440 – 16 Yes Reserved 0x644F CTRIPA6ICTL 0x6450 1 Yes CTRIPA6 Filter Input and Function Control Register CTRIPA6FILCTL 0x6451 1 Yes CTRIPA6 Filter Parameters Register CTRIPA6FILCLKCTL 0x6452 1 Yes CTRIPA6 Filter Sample Clock Control Register Reserved 0x6453 1 Yes Reserved CTRIPB4ICTL 0x6454 1 Yes CTRIPB4 Filter Input and Function Control Register CTRIPB4FILCTL 0x6455 1 Yes CTRIPB4 Filter Parameters Register CTRIPB4FILCLKCTL 0x6456 1 Yes CTRIPB4 Filter Sample Clock Control Register Reserved 0x6457 1 Yes Reserved CTRIPB6ICTL 0x6458 1 Yes CTRIPB6 Filter Input and Function Control Register CTRIPB6FILCTL 0x6459 1 Yes CTRIPB6 Filter Parameters Register CTRIPB6FILCLKCTL 0x645A 1 Yes CTRIPB6 Filter Sample Clock Control Register Reserved 0x645B 1 Yes Reserved Reserved 0x645C 1 Yes Reserved CTRIPM2OCTL 0x645D 1 Yes CTRIPM2 CTRIP Filter Output Control Register CTRIPM2STS 0x645E 1 Yes CTRIPM2 CTRIPxx Outputs Status Register CTRIPM2FLGCLR 0x645F 1 Yes CTRIPM2 CTRIPxx Flag Clear Register Reserved 0x6460 – 16 Yes Reserved 0x646F CTRIPB7ICTL 0x6470 1 Yes CTRIPB7 Filter Input and Function Control Register CTRIPB7FILCTL 0x6471 1 Yes CTRIPB7 Filter Parameters Register CTRIPB7FILCLKCTL 0x6472 1 Yes CTRIPB7 Filter Sample Clock Control Register Reserved 0x6473 – 9 Yes Reserved 0x647B Reserved 0x647C 1 Yes Reserved CTRIPPFCOCTL 0x647D 1 Yes CTRIPPFC CTRIPxx Outputs Status Register CTRIPPFCSTS 0x647E 1 Yes CTRIPPFC CTRIPxx Flag Clear Register CTRIPPFCFLGCLR 0x647F 1 Yes CTRIPPFC COMP Test Control Register Table 6-15. LOCK Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED LOCKCTRIP 0x64F0 1 Yes Lock Register for CTRIP Filters Register Reserved 0x64F1 1 Yes Reserved LOCKDAC 0x64F2 1 Yes Lock Register for DACs Register Reserved 0x64F3 1 Yes Reserved LOCKAMPCOMP 0x64F4 1 Yes Lock Register for Amplifiers and Comparators Register Reserved 0x64F5 1 Yes Reserved LOCKSWITCH 0x64F6 1 Yes Lock Register for Switches Register 88 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.2.3 Programmable Gain Amplifier Electrical Data/Timing Table 6-16. Op-Amp Linear Output and ADC Sampling Time Across Gain Settings MINIMUM INTERNAL RESISTOR RATIO EQUIVALENT GAIN FROM LINEAR OUTPUT RANGE ADC SAMPLING TIME INPUT TO OUTPUT OF OP-AMP TO ACHIEVE SETTLING ACCURACY 10 11 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23) 5 6 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23) 2 3 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23) Table 6-17. PGA Gain Stage: DC Accuracy Across Gain Settings COMPENSATED COMPENSATED INPUT INTERNAL RESISTOR RATIO EQUIVALENT GAIN FROM GAIN-ERROR DRIFT ACROSS OFFSET-ERROR ACROSS INPUT TO OUTPUT TEMPERATURE AND SUPPLY TEMPERATURE AND SUPPLY VARIATIONS VARIATIONS IN mV 10 11 < ±2.5% < ±8 mV 5 6 < ±1.5% < ±8 mV 2 3 < ±1.0% < ±8 mV 6.3.2.4 Comparator Block Electrical Data/Timing Table 6-18. Electrical Characteristics of the Comparator/DAC PARAMETER MIN TYP MAX UNITS Comparator Comparator Input Range VSSA – VDDA V Comparator response time to PWM Trip Zone (Async) 65 ns Comparator large step response time to PWM Trip Zone (Async) 95 ns Input Offset TBD mV Input Hysteresis(1) TBD mV DAC DAC Output Range VDDA / 26 – VDDA V DAC resolution 6 bits DAC Gain –1.5 % DAC Offset 10 mV Monotonic Yes INL 0.2 LSB (1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration, which results in an effective 100-kΩ feedback resistance between the output of the comparator and the non-inverting input of the comparator. There is an option to disable the hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for more information on this option if needed in your system. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 89 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.3.2.5 VREFOUT Buffered DAC Electrical Data Table 6-19. Electrical Characteristics of VREFOUT Buffered DAC PARAMETER MIN TYP MAX UNITS VREFOUT Programmable Range 6 56 LSB VREFOUT resolution 6 bits VREFOUT Gain –1.5 % VREFOUT Offset 10 mV Monotonic Yes INL ±0.2 LSB Load 3 kΩ 100 pF 90 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION (SPIBRR 1) LSPCLK Baud rate + = when SPIBRR = 3 to127 4 LSPCLK Baud rate = when SPIBRR = 0,1, 2 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.4 Serial Peripheral Interface (SPI) 6.4.1 Serial Peripheral Interface Device-Specific Information The device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI module features include: • Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO if the SPI module is not used. • Two operational modes: master and slave Baud rate: 125 different programmable rates. • Data word length: one to sixteen data bits • Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. • Simultaneous receive and transmit operation (transmit function can be disabled in software) • Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. • Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced feature: • 4-level transmit/receive FIFO • Delayed transmit control • Bi-directional 3-wire SPI mode support • Audio data receive support via SPISTE inversion Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 91 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION S SPICTL.0 SPI INT FLAG SPI INT ENA SPISTS.6 S Clock Polarity Talk LSPCLK SPI Bit Rate State Control Clock Phase Receiver Overrun Flag SPICTL.4 Overrun INT ENA SPICCR.3 - 0 SPIBRR.6 - 0 SPICCR.6 SPICTL.3 SPIDAT.15 - 0 SPICTL.1 M S M Master/Slave SPISTS.7 SPIDAT Data Register M S SPI Char SPICTL.2 SPISIMO SPISOMI SPICLK SW2 S M M S SW3 To CPU M SW1 RX FIFO _0 RX FIFO _1 ----- RX FIFO _3 TX FIFO Registers TX FIFO _0 TX FIFO _1 ----- TX FIFO _3 RX FIFO Registers 16 16 16 TX Interrupt Logic RX Interrupt Logic SPIINT SPITX SPIFFOVF FLAG SPIFFRX.15 TX FIFO Interrupt RX FIFO Interrupt SPIRXBUF SPITXBUF SPIFFTX.14 SPIFFENA SPISTE 16 3 2 1 0 6 5 4 3 2 1 0 TW TW TW SPIPRI.0 TRIWIRE SPIPRI.1 STEINV STEINV SPIRXBUF Buffer Register SPITXBUF Buffer Register TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-14 is a block diagram of the SPI in slave mode. A. SPISTE is driven low by the master for a slave device. Figure 6-14. SPI Module Block Diagram (Slave Mode) 92 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.4.2 Serial Peripheral Interface Register Descriptions The SPI port operation is configured and controlled by the registers listed in Table 6-20. Table 6-20. SPI-A Registers NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1) SPICCR 0x7040 1 No SPI-A Configuration Control Register SPICTL 0x7041 1 No SPI-A Operation Control Register SPISTS 0x7042 1 No SPI-A Status Register SPIBRR 0x7044 1 No SPI-A Baud Rate Register SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register SPIDAT 0x7049 1 No SPI-A Serial Data Register SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register SPIFFCT 0x704C 1 No SPI-A FIFO Control Register SPIPRI 0x704F 1 No SPI-A Priority Control Register (1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. 6.4.3 Serial Peripheral Interface Master Mode Electrical Data/Timing Table 6-21 lists the master mode timing (clock phase = 0) and Table 6-22 lists the timing (clock phase = 1). Figure 6-15 and Figure 6-16 show the timing waveforms. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 93 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD NO. SPIBRR = 0 OR 2 AND SPIBRR > 3 UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns 2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns (clock polarity = 0) tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) (clock polarity = 1) 3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns (clock polarity = 0) tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) (clock polarity = 1) 4 td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO 10 10 ns valid (clock polarity = 0) td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO 10 10 valid (clock polarity = 1) 5 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 ns SPICLK low (clock polarity = 0) tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 SPICLK high (clock polarity = 1) 8 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK 26 26 ns low (clock polarity = 0) tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK 26 26 high (clock polarity = 1) 9 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 ns SPICLK low (clock polarity = 0) tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 SPICLK high (clock polarity = 1) (1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1) (3) tc(LCO) = LSPCLK cycle time (4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. (5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). 94 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION 9 4 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid SPISTE (A) 1 2 3 5 8 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-15. SPI Master Mode External Timing (Clock Phase = 0) Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 95 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-22. SPI Master Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN SPI WHEN (SPIBRR + 1) IS ODD NO. OR SPIBRR = 0 OR 2 AND SPIBRR > 3 UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns 2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns (clock polarity = 0) tw(SPCL))M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO (clock polarity = 1) 3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns (clock polarity = 0) tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) (clock polarity = 1) 6 tsu(SIMO-SPCH)M Setup time, SPISIMO data valid 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns before SPICLK high (clock polarity = 0) tsu(SIMO-SPCL)M Setup time, SPISIMO data valid 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 before SPICLK low (clock polarity = 1) 7 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns SPICLK high (clock polarity = 0) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 SPICLK low (clock polarity = 1) 10 tsu(SOMI-SPCH)M Setup time, SPISOMI before 26 26 ns SPICLK high (clock polarity = 0) tsu(SOMI-SPCL)M Setup time, SPISOMI before 26 26 SPICLK low (clock polarity = 1) 11 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 ns SPICLK high (clock polarity = 0) tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 SPICLK low (clock polarity = 1) (1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. (4) tc(LCO) = LSPCLK cycle time (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 96 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Data Valid 11 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master in data must be valid Master out data Is valid 1 7 6 10 3 2 SPISTE(A) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-16. SPI Master Mode External Timing (Clock Phase = 1) Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 97 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION 20 15 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO data must be valid SPISOMI data Is valid 19 16 14 13 12 SPISTE(A) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.4.4 Serial Peripheral Interface Slave Mode Electrical Data/Timing Table 6-23 lists the slave mode external timing (clock phase = 0) and Table 6-24 (clock phase = 1). Figure 6-17 and Figure 6-18 show the timing waveforms. Table 6-23. SPI Slave Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 4tc(LCO) ns 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 15 td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 21 ns td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 21 16 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S ns tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S 19 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 26 ns tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 26 20 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 ns tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 (1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. (4) tc(LCO) = LSPCLK cycle time (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-17. SPI Slave Mode External Timing (Clock Phase = 0) 98 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Data Valid 22 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO data must be valid SPISOMI data is valid 21 12 18 17 14 13 SPISTE(A) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 8tc(LCO) ns 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC) S 14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC) S ns tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 17 tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S 18 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low 0.75tc(SPC)S ns (clock polarity = 1) tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high 0.75tc(SPC) S (clock polarity = 0) 21 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 26 ns tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 26 22 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high 0.5tc(SPC)S – 10 ns (clock polarity = 0) tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low 0.5tc(SPC)S – 10 (clock polarity = 1) (1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. (4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-18. SPI Slave Mode External Timing (Clock Phase = 1) Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 99 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION (BRR 1) * 8 LSPCLK Baud rate + = when BRR ¹ 0 16 LSPCLK Baud rate = when BRR = 0 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.5 Serial Communications Interface (SCI) 6.5.1 Serial Communications Interface Device-Specific Information The 2805x devices include three serial communications interface (SCI) modules (SCI-A, SCI-B, SCI-C). Each SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are doublebuffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register. Features of each SCI module include: • Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates: • Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits • Four error-detection flags: parity, overrun, framing, and break detection • Two wake-up multiprocessor modes: idle-line and address bit • Half- or full-duplex operation • Double-buffered receive and transmit functions • Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) • Separate enable bits for transmitter and receiver interrupts (except BRKDT) • NRZ (non-return-to-zero) format NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced features: • Auto baud-detect hardware logic • 4-level transmit/receive FIFO 100 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TX FIFO _0 LSPCLK WUT Frame Format and Mode Even/Odd Enable Parity SCI RX Interrupt select logic BRKDT RXRDY SCIRXST.6 SCICTL1.3 8 SCICTL2.1 RX/BK INT ENA SCIRXD SCIRXST.1 TXENA SCI TX Interrupt select logic TX EMPTY TXRDY SCICTL2.0 TX INT ENA SCITXD RXENA SCIRXD RXWAKE SCICTL1.6 RX ERR INT ENA TXWAKE SCITXD SCICCR.6 SCICCR.5 SCITXBUF.7-0 SCIHBAUD. 15 - 8 Baud Rate MSbyte Register SCILBAUD. 7 - 0 Transmitter-Data Buffer Register 8 SCICTL2.6 SCICTL2.7 Baud Rate LSbyte Register RXSHF Register TXSHF Register SCIRXST.5 1 TX FIFO _1 ----- TX FIFO _3 8 TX FIFO registers TX FIFO TX Interrupt Logic TXINT SCIFFTX.14 RX FIFO _3 SCIRXBUF.7-0 Receive Data Buffer register SCIRXBUF.7-0 ----- RX FIFO_1 RX FIFO _0 8 RX FIFO registers SCICTL1.0 RX Interrupt Logic RXINT RX FIFO SCIFFRX.15 RXFFOVF RX Error SCIRXST.7 RX Error FE OE PE SCIRXST.4 - 2 To CPU To CPU AutoBaud Detect logic SCICTL1.1 SCIFFENA Interrupts Interrupts TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 6-19 shows the SCI module block diagram. Figure 6-19. Serial Communications Interface (SCI) Module Block Diagram Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 101 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.5.2 Serial Communications Interface Register Descriptions The SCI port operation is configured and controlled by the registers listed in Table 6-25. Table 6-25. SCI-A Registers(1) NAME ADDRESS SIZE (x16) EALLOW DESCRIPTION PROTECTED SCICCRA 0x7050 1 No SCI-A Communications Control Register SCICTL1A 0x7051 1 No SCI-A Control Register 1 SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits SCICTL2A 0x7054 1 No SCI-A Control Register 2 SCIRXSTA 0x7055 1 No SCI-A Receive Status Register SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register SCIFFTXA(2) 0x705A 1 No SCI-A FIFO Transmit Register SCIFFRXA(2) 0x705B 1 No SCI-A FIFO Receive Register SCIFFCTA(2) 0x705C 1 No SCI-A FIFO Control Register SCIPRIA 0x705F 1 No SCI-A Priority Control Register (1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. (2) These registers are new registers for the FIFO mode. 102 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.6 Enhanced Controller Area Network (eCAN) 6.6.1 Enhanced Controller Area Network Device-Specific Information The CAN module (eCAN-A) has the following features: • Fully compliant with CAN protocol, version 2.0B • Supports data rates up to 1 Mbps • Thirty-two mailboxes, each with the following properties: – Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out • Low-power mode • Programmable wake-up on bus activity • Automatic reply to a remote request message • Automatic retransmission of a frame in case of loss of arbitration or error • 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16) • Self-test mode – Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit. NOTE For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 4.6875 kbps. The F2805x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 103 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Mailbox RAM (512 Bytes) 32-Message Mailbox of 4 x 32-Bit Words Memory Management Unit CPU Interface, Receive Control Unit, Timer Management Unit eCAN Memory (512 Bytes) Registers and Message Objects Control Message Controller 32 32 eCAN Protocol Kernel Receive Buffer Transmit Buffer Control Buffer Status Buffer Enhanced CAN Controller 32 eCAN0INT eCAN1INT Controls Address Data 32 SN65HVD23x 3.3-V CAN Transceiver CAN Bus TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-20. eCAN Block Diagram and Interface Circuit Table 6-26. 3.3-V eCAN Transceivers PART NUMBER SUPPLY LOW-POWER SLOPE VREF OTHER TVOLTAGE MODE CONTROL A SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C SN65HVD232 3.3 V None None None – –40°C to 85°C SN65HVD232Q 3.3 V None None None – –40°C to 125°C SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C SN65HVD234 3.3 V Standby and Sleep Adjustable None – –40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C ISO1050 3–5.5 V None None None Built-in Isolation –55°C to 105°C Low Prop Delay Thermal Shutdown Failsafe Operation Dominant Time-Out 104 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Mailbox Enable - CANME Mailbox Direction - CANMD Transmission Request Set - CANTRS Transmission Request Reset - CANTRR Transmission Acknowledge - CANTA Abort Acknowledge - CANAA Received Message Pending - CANRMP Received Message Lost - CANRML Remote Frame Pending - CANRFP Global Acceptance Mask - CANGAM Master Control - CANMC Bit-Timing Configuration - CANBTC Error and Status - CANES Transmit Error Counter - CANTEC Receive Error Counter - CANREC Global Interrupt Flag 0 - CANGIF0 Global Interrupt Mask - CANGIM Mailbox Interrupt Mask - CANMIM Mailbox Interrupt Level - CANMIL Overwrite Protection Control - CANOPC TX I/O Control - CANTIOC RX I/O Control - CANRIOC Time Stamp Counter - CANTSC Global Interrupt Flag 1 - CANGIF1 Time-Out Control - CANTOC Time-Out Status - CANTOS Reserved eCAN-A Control and Status Registers 61E8h-61E9h Message Identifier - MSGID Message Control - MSGCTRL Message Data Low - MDL Message Data High - MDH Message Mailbox (16 Bytes) Control and Status Registers 6000h 603Fh Local Acceptance Masks (LAM) (32 x 32-Bit RAM) 6040h 607Fh 6080h 60BFh 60C0h 60FFh eCAN-A Memory (512 Bytes) Message Object Time Stamps (MOTS) (32 x 32-Bit RAM) Message Object Time-Out (MOTO) (32 x 32-Bit RAM) 6100h-6107h Mailbox 0 6108h-610Fh Mailbox 1 6110h-6117h Mailbox 2 6118h-611Fh Mailbox 3 eCAN-A Memory RAM (512 Bytes) 6120h-6127h Mailbox 4 61E0h-61E7h Mailbox 28 61E8h-61EFh Mailbox 29 61F0h-61F7h Mailbox 30 61F8h-61FFh Mailbox 31 61EAh-61EBh 61ECh-61EDh 61EEh-61EFh TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 6-21. eCAN-A Memory Map NOTE If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled if the eCAN RAM (LAM, MOTS, MOTO, and mailbox RAM) is used as generalpurpose RAM. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 105 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.6.2 Enhanced Controller Area Network Register Descriptions The CAN registers listed in Table 6-27 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 6-27. CAN Register Map(1) REGISTER NAME eCAN-A SIZE (x32) DESCRIPTION ADDRESS CANME 0x6000 1 Mailbox enable CANMD 0x6002 1 Mailbox direction CANTRS 0x6004 1 Transmit request set CANTRR 0x6006 1 Transmit request reset CANTA 0x6008 1 Transmission acknowledge CANAA 0x600A 1 Abort acknowledge CANRMP 0x600C 1 Receive message pending CANRML 0x600E 1 Receive message lost CANRFP 0x6010 1 Remote frame pending CANGAM 0x6012 1 Global acceptance mask CANMC 0x6014 1 Master control CANBTC 0x6016 1 Bit-timing configuration CANES 0x6018 1 Error and status CANTEC 0x601A 1 Transmit error counter CANREC 0x601C 1 Receive error counter CANGIF0 0x601E 1 Global interrupt flag 0 CANGIM 0x6020 1 Global interrupt mask CANGIF1 0x6022 1 Global interrupt flag 1 CANMIM 0x6024 1 Mailbox interrupt mask CANMIL 0x6026 1 Mailbox interrupt level CANOPC 0x6028 1 Overwrite protection control CANTIOC 0x602A 1 TX I/O control CANRIOC 0x602C 1 RX I/O control CANTSC 0x602E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x6030 1 Time-out control (Reserved in SCC mode) CANTOS 0x6032 1 Time-out status (Reserved in SCC mode) (1) These registers are mapped to Peripheral Frame 1. 106 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.7 Inter-Integrated Circuit (I2C) 6.7.1 Inter-Integrated Circuit Device-Specific Information The device contains one I2C Serial Port. Figure 6-22 shows how the I2C peripheral module interfaces within the device. The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate) • One 4-word receive FIFO and one 4-word transmit FIFO • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave • An additional interrupt that can be used by the CPU when in FIFO mode • Module enable/disable capability • Free data format mode Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 107 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION I2CXSR I2CDXR I2CRSR I2CDRR Clock Synchronizer Prescaler Noise Filters Arbitrator I2C INT Peripheral Bus Interrupt to CPU/PIE SDA SCL Control/Status Registers CPU I2C Module TX FIFO RX FIFO FIFO Interrupt to CPU/PIE TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the SYSCLKOUT rate. B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off. Figure 6-22. I2C Peripheral Module Interfaces 6.7.2 Inter-Integrated Circuit Register Descriptions The registers in Table 6-28 configure and control the I2C port operation. Table 6-28. I2C-A Registers NAME ADDRESS EALLOW DESCRIPTION PROTECTED I2COAR 0x7900 No I2C own address register I2CIER 0x7901 No I2C interrupt enable register I2CSTR 0x7902 No I2C status register I2CCLKL 0x7903 No I2C clock low-time divider register I2CCLKH 0x7904 No I2C clock high-time divider register I2CCNT 0x7905 No I2C data count register I2CDRR 0x7906 No I2C data receive register I2CSAR 0x7907 No I2C slave address register I2CDXR 0x7908 No I2C data transmit register I2CMDR 0x7909 No I2C mode register I2CISRC 0x790A No I2C interrupt source register I2CPSC 0x790C No I2C prescaler register I2CFFTX 0x7920 No I2C FIFO transmit register I2CFFRX 0x7921 No I2C FIFO receive register I2CRSR – No I2C receive shift register (not accessible to the CPU) I2CXSR – No I2C transmit shift register (not accessible to the CPU) 108 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.7.3 Inter-Integrated Circuit Electrical Data/Timing Table 6-29. I2C Timing TEST CONDITIONS MIN MAX UNIT fSCL SCL clock frequency I2C clock module frequency is between 400 kHz 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately vil Low level input voltage 0.3 VDDIO V Vih High level input voltage 0.7 VDDIO V Vhys Input hysteresis 0.05 VDDIO V Vol Low level output voltage 3 mA sink current 0 0.4 V tLOW Low period of SCL clock I2C clock module frequency is between 1.3 μs 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately tHIGH High period of SCL clock I2C clock module frequency is between 0.6 μs 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately lI Input current with an input voltage –10 10 μA between 0.1 VDDIO and 0.9 VDDIO MAX Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 109 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.8 Enhanced Pulse Width Modulator (ePWM) 6.8.1 Enhanced Pulse Width Modulator Device-Specific Information The devices contain up to seven enhanced PWM Modules (ePWM1–ePWM7). Figure 6-23 shows a block diagram of multiple ePWM modules. Figure 6-24 shows the signal interconnections with the ePWM. See the Enhanced Pulse Width Modulator (ePWM) Module chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for more details. 110 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION EPWM1TZINT PIE EPWM1INT EPWM2TZINT EPWM2INT EPWMxTZINT EPWMxINT CTRIP Output Subsystem SOCA1 ADC SOCB1 SOCA2 SOCB2 SOCAx SOCBx EPWM1SYNCI EPWM2SYNCI EPWM1SYNCO EPWM2SYNCO EPWM1 Module EPWM2 Module EPWMxSYNCI EPWMx Module CTRIPxx TZ6 TZ6 TZ1 to TZ3 TZ5 CLOCKFAIL TZ4 EQEP1ERR EMUSTOP TZ5 CLOCKFAIL TZ4 EQEP1ERR EMUSTOP EPWM1ENCLK TBCLKSYNC EPWM2ENCLK TBCLKSYNC TZ5 TZ6 EPWMxENCLK TBCLKSYNC CLOCKFAIL TZ4 EQEP1ERR EMUSTOP EPWM1B C28x CPU System Control eQEP1 TZ1 to TZ3 TZ1 to TZ3 EPWM1SYNCO EPWM2B eCAPI EPWMxB EQEP1ERR EPWMxA EPWM2A EPWM1A G P I O M U X ADCSOCBO ADCSOCAO Peripheral Bus Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) SOCA1 SOCA2 SPCAx Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) SOCB1 SOCB2 SPCBx EPWMSYNCI TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 6-23. ePWM Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 111 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TBPRD Shadow (24) TBPRD Active (24) Counter Up/Down (16 Bit) TCBNT Active (16) TBCTL[PHSEN] CTR=PRD 16 Phase Control CTR=ZERO CTR_Dir CTR=ZERO CTR=CMPB Disabled TBCTL[SYNCOSEL] EPWMxSYNCO Time-Base (TB) TBPHS Active (24) Sync In/Out Select Mux CTR=PRD CTR=ZERO CTR=CMPA CTR=CMPB CTR_Dir DCAEVT1.soc (A) DCBEVT1.soc (A) Event Trigger and Interrupt (ET) EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxSOCA EPWMxSOCB ADC Action Qualifier (AQ) EPWMA Dead Band (DB) EPWMB PWM Chopper (PC) Trip Zone (TZ) EPWMxA EPWMxB CTR=ZERO EPWMxTZINT TZ1 to TZ3 EMUSTOP CLOCKFAIL EQEP1ERR DCAEVT1.force (A) DCAEVT2.force (A) DCBEVT1.force (A) DCBEVT2.force (A) CTR=CMPA 16 CTR=CMPB 16 CMPB Active (16) CMPB Shadow (16) CTR=PRD or ZERO DCAEVT1.inter DCBEVT1.inter DCAEVT2.inter DCBEVT2.inter EPWMxSYNCI TBCTL[SWFSYNC] (Software Forced Sync) DCAEVT1.sync DCBEVT1.sync CMPA Active (24) CMPA Shadow (24) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals. Figure 6-24. ePWM Sub-Modules Showing Critical Internal Signal Interconnections 112 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.8.2 Enhanced Pulse Width Modulator Register Descriptions Table 6-30 and Table 6-31 show the complete ePWM register set per module. Table 6-30. ePWM1–ePWM4 Control and Status Registers NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / DESCRIPTION #SHADOW TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register Reserved 0x6802 0x6842 0x6882 0x68C2 1 / 0 Reserved TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set Reserved 0x6806 0x6846 0x6886 0x68C6 1 / 1 Reserved CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register Reserved 0x6808 0x6848 0x6888 0x68C8 1 / 1 Reserved CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register(1) TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1 / 0 Trip Zone Digital Compare Register TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register(1) TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register(1) TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register (1) TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register(1) TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register(1) ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register (1) Registers that are EALLOW protected. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 113 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-30. ePWM1–ePWM4 Control and Status Registers (continued) NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / DESCRIPTION #SHADOW ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register Reserved 0x6820 0x6860 0x68A0 0x68E0 1 / 0 Reserved Reserved 0x6821 - - - 1 / 0 Reserved Reserved 0x6826 - - - 1 / 0 Reserved Reserved 0x6828 0x6868 0x68A8 0x68E8 1 / 0 Reserved Reserved 0x682A 0x686A 0x68AA 0x68EA 1 / W(2) Reserved TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W(2) Time Base Period Register Mirror Reserved 0x682C 0x686C 0x68AC 0x68EC 1 / W(2) Reserved CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W(2) Compare A Register Mirror DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1 / 0 Digital Compare Trip Select Register (1) DCACTL 0x6831 0x6871 0x68B1 0x68F1 1 / 0 Digital Compare A Control Register(1) DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1 / 0 Digital Compare B Control Register(1) DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1 / 0 Digital Compare Filter Control Register(1) DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1 / 0 Digital Compare Capture Control Register(3) DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1 / 1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1 / 0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1 / 0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1 / 0 Digital Compare Filter Window Counter Register DCCAP 0x6839 0x6879 0x68B9 0x68F9 1 / 1 Digital Compare Counter Capture Register (2) W = Write to shadow register (3) Registers that are EALLOW protected. 114 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 6-31. ePWM5–ePWM7 Control and Status Registers NAME ePWM5 ePWM6 ePWM7 SIZE (x16) / DESCRIPTION #SHADOW TBCTL 0x6900 0x6940 0x6980 1 / 0 Time Base Control Register TBSTS 0x6901 0x6941 0x6981 1 / 0 Time Base Status Register Reserved 0x6902 0x6942 0x6982 1 / 0 Reserved TBPHS 0x6903 0x6943 0x6983 1 / 0 Time Base Phase Register TBCTR 0x6904 0x6944 0x6984 1 / 0 Time Base Counter Register TBPRD 0x6905 0x6945 0x6985 1 / 1 Time Base Period Register Set Reserved 0x6906 0x6946 0x6986 1 / 1 Reserved CMPCTL 0x6907 0x6947 0x6987 1 / 0 Counter Compare Control Register Reserved 0x6908 0x6948 0x6988 1 / 1 Reserved CMPA 0x6909 0x6949 0x6989 1 / 1 Counter Compare A Register Set CMPB 0x690A 0x694A 0x698A 1 / 1 Counter Compare B Register Set AQCTLA 0x690B 0x694B 0x698B 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x690C 0x694C 0x698C 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x690D 0x694D 0x698D 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x690E 0x694E 0x698E 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x690F 0x694F 0x698F 1 / 1 Dead-Band Generator Control Register DBRED 0x6910 0x6950 0x6990 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6911 0x6951 0x6991 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6912 0x6952 0x6992 1 / 0 Trip Zone Select Register(1) TZDCSEL 0x6913 0x6953 0x6993 1 / 0 Trip Zone Digital Compare Register TZCTL 0x6914 0x6954 0x6994 1 / 0 Trip Zone Control Register(1) TZEINT 0x6915 0x6955 0x6995 1 / 0 Trip Zone Enable Interrupt Register(1) TZFLG 0x6916 0x6956 0x6996 1 / 0 Trip Zone Flag Register (1) TZCLR 0x6917 0x6957 0x6997 1 / 0 Trip Zone Clear Register(1) TZFRC 0x6918 0x6958 0x6998 1 / 0 Trip Zone Force Register(1) ETSEL 0x6919 0x6959 0x6999 1 / 0 Event Trigger Selection Register ETPS 0x691A 0x695A 0x699A 1 / 0 Event Trigger Prescale Register ETFLG 0x691B 0x695B 0x699B 1 / 0 Event Trigger Flag Register ETCLR 0x691C 0x695C 0x699C 1 / 0 Event Trigger Clear Register ETFRC 0x691D 0x695D 0x699D 1 / 0 Event Trigger Force Register PCCTL 0x691E 0x695E 0x699E 1 / 0 PWM Chopper Control Register Reserved 0x6920 0x6960 0x69A0 1 / 0 Reserved Reserved - - - 1 / 0 Reserved Reserved - - - 1 / 0 Reserved Reserved 0x6928 0x6968 0x69A8 1 / 0 Reserved Reserved 0x692A 0x696A 0x69AA 1 / W(2) Reserved TBPRDM 0x692B 0x696B 0x69AB 1 / W(2) Time Base Period Register Mirror Reserved 0x692C 0x696C 0x69AC 1 / W(2) Reserved CMPAM 0x692D 0x696D 0x69AD 1 / W(2) Compare A Register Mirror DCTRIPSEL 0x6930 0x6970 0x69B0 1 / 0 Digital Compare Trip Select Register (1) DCACTL 0x6931 0x6971 0x69B1 1 / 0 Digital Compare A Control Register(1) DCBCTL 0x6932 0x6972 0x69B2 1 / 0 Digital Compare B Control Register(1) DCFCTL 0x6933 0x6973 0x69B3 1 / 0 Digital Compare Filter Control Register(1) DCCAPCT 0x6934 0x6974 0x69B4 1 / 0 Digital Compare Capture Control Register(1) (1) Registers that are EALLOW protected. (2) W = Write to shadow register Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 115 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-31. ePWM5–ePWM7 Control and Status Registers (continued) NAME ePWM5 ePWM6 ePWM7 SIZE (x16) / DESCRIPTION #SHADOW DCFOFFSET 0x6935 0x6975 0x69B5 1 / 1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6936 0x6976 0x69B6 1 / 0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6937 0x6977 0x69B7 1 / 0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6938 0x6978 0x69B8 1 / 0 Digital Compare Filter Window Counter Register DCCAP 0x6939 0x6979 0x69B9 1 / 1 Digital Compare Counter Capture Register 6.8.3 Enhanced Pulse Width Modulator Electrical Data/Timing PWM refers to PWM outputs on ePWM1–7. Table 6-32 shows the PWM timing requirements and Table 6- 33, switching characteristics. Table 6-32. ePWM Timing Requirements(1) MIN MAX UNIT tw(SYCIN) Sync input pulse width Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. Table 6-33. ePWM Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tw(PWM) Pulse duration, PWMx output high/low 33.33 ns tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles td(PWM)tza Delay time, trip input active to PWM forced high no pin load 25 ns Delay time, trip input active to PWM forced low td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns 116 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION PWM (B) TZ (A) SYSCLK tw(TZ) td(TZ-PWM)HZ TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.8.3.1 Trip-Zone Input Timing Table 6-34. Trip-Zone Input Timing Requirements(1) MIN MAX UNIT tw(TZ) Pulse duration, TZx input low Asynchronous 2tc(TBCLK) cycles Synchronous 2tc(TBCLK) cycles With input qualifier 2tc(TBCLK) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6 B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 6-25. PWM Hi-Z Characteristics Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 117 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TSCTR (counter−32 bit) RST CAP1 (APRD active) LD CAP2 (ACMP active) LD CAP3 (APRD shadow) LD CAP4 (ACMP shadow) LD Continuous / Oneshot Capture Control LD1 LD2 LD3 LD4 32 32 PRD [0−31] CMP [0−31] CTR [0−31] eCAPx Interrupt Trigger and Flag control to PIE CTR=CMP 32 32 32 32 32 ACMP shadow Event Pre-scale CTRPHS (phase register−32 bit) SYNCOut SYNCIn Event qualifier Polarity select Polarity select Polarity select Polarity select CTR=PRD CTR_OVF 4 PWM compare logic CTR [0−31] PRD [0−31] CMP [0−31] CTR=CMP CTR=PRD OVF CTR_OVF APWM mode Delta−mode SYNC Capture events 4 CEVT[1:4] APRD shadow 32 32 MODE SELECT TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.9 Enhanced Capture Module (eCAP) 6.9.1 Enhanced Capture Module Device-Specific Information The device contains an enhanced capture module (eCAP1). Figure 6-26 shows a functional block diagram of a module. Figure 6-26. eCAP Functional Block Diagram The eCAP module is clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off. 118 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.9.2 Enhanced Capture Module Register Descriptions Table 6-35 shows the eCAP Control and Status Registers. Table 6-35. eCAP Control and Status Registers NAME eCAP1 SIZE (x16) EALLOW PROTECTED DESCRIPTION TSCTR 0x6A00 2 Time-Stamp Counter CTRPHS 0x6A02 2 Counter Phase Offset Value Register CAP1 0x6A04 2 Capture 1 Register CAP2 0x6A06 2 Capture 2 Register CAP3 0x6A08 2 Capture 3 Register CAP4 0x6A0A 2 Capture 4 Register Reserved 0x6A0C – 0x6A12 8 Reserved ECCTL1 0x6A14 1 Capture Control Register 1 ECCTL2 0x6A15 1 Capture Control Register 2 ECEINT 0x6A16 1 Capture Interrupt Enable Register ECFLG 0x6A17 1 Capture Interrupt Flag Register ECCLR 0x6A18 1 Capture Interrupt Clear Register ECFRC 0x6A19 1 Capture Interrupt Force Register Reserved 0x6A1A – 0x6A1F 6 Reserved 6.9.3 Enhanced Capture Module Electrical Data/Timing Table 6-36 shows the eCAP timing requirement and Table 6-37 shows the eCAP switching characteristics. Table 6-36. Enhanced Capture (eCAP) Timing Requirement(1) MIN MAX UNIT tw(CAP) Capture input pulse width Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. Table 6-37. eCAP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(APWM) Pulse duration, APWMx output high/low 20 ns Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 119 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION QWDTMR QWDPRD 16 UTIME QWDOG QUPRD QUTMR 32 UTOUT WDTOUT Quadrature Capture Unit (QCAP) QCPRDLAT QCTMRLAT 16 QFLG QEPSTS QEPCTL Registers Used by Multiple Units QCLK QDIR QI QS PHE PCSOUT Quadrature Decoder (QDU) QDECCTL 16 Position Counter/ Control Unit (PCCU) QPOSLAT QPOSSLAT 16 QPOSILAT EQEPxAIN EQEPxBIN EQEPxIIN EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE GPIO MUX EQEPxA/XCLK EQEPxB/XDIR EQEPxS EQEPxI QPOSCMP QEINT QFRC 32 QCLR QPOSCTL 32 16 QPOSCNT QPOSMAX QPOSINIT PIE EQEPxINT Enhanced QEP (eQEP) Peripheral System Control Registers QCTMR QCPRD 16 16 QCAPCTL EQEPxENCLK SYSCLKOUT To CPU Data Bus TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.10 Enhanced Quadrature Encoder Pulse (eQEP) 6.10.1 Enhanced Quadrature Encoder Pulse Device-Specific Information The device contains one enhanced quadrature encoder pulse (eQEP) module. Figure 6-27 shows the eQEP functional block diagram. Figure 6-27. eQEP Functional Block Diagram 120 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.10.2 Enhanced Quadrature Encoder Pulse Register Descriptions Table 6-38 shows the eQEP Control and Status Registers. Table 6-38. eQEP Control and Status Registers eQEP1 eQEP1 NAME ADDRESS SIZE(x16)/ REGISTER DESCRIPTION #SHADOW QPOSCNT 0x6B00 2/0 eQEP Position Counter QPOSINIT 0x6B02 2/0 eQEP Initialization Position Count QPOSMAX 0x6B04 2/0 eQEP Maximum Position Count QPOSCMP 0x6B06 2/1 eQEP Position-compare QPOSILAT 0x6B08 2/0 eQEP Index Position Latch QPOSSLAT 0x6B0A 2/0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 2/0 eQEP Position Latch QUTMR 0x6B0E 2/0 eQEP Unit Timer QUPRD 0x6B10 2/0 eQEP Unit Period Register QWDTMR 0x6B12 1/0 eQEP Watchdog Timer QWDPRD 0x6B13 1/0 eQEP Watchdog Period Register QDECCTL 0x6B14 1/0 eQEP Decoder Control Register QEPCTL 0x6B15 1/0 eQEP Control Register QCAPCTL 0x6B16 1/0 eQEP Capture Control Register QPOSCTL 0x6B17 1/0 eQEP Position-compare Control Register QEINT 0x6B18 1/0 eQEP Interrupt Enable Register QFLG 0x6B19 1/0 eQEP Interrupt Flag Register QCLR 0x6B1A 1/0 eQEP Interrupt Clear Register QFRC 0x6B1B 1/0 eQEP Interrupt Force Register QEPSTS 0x6B1C 1/0 eQEP Status Register QCTMR 0x6B1D 1/0 eQEP Capture Timer QCPRD 0x6B1E 1/0 eQEP Capture Period Register QCTMRLAT 0x6B1F 1/0 eQEP Capture Timer Latch QCPRDLAT 0x6B20 1/0 eQEP Capture Period Latch Reserved 0x6B21 – 31/0 0x6B3F Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 121 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.10.3 Enhanced Quadrature Encoder Pulse Electrical Data/Timing Table 6-39 shows the eQEP timing requirement and Table 6-40 shows the eQEP switching characteristics. Table 6-39. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements(1) TEST CONDITIONS MIN MAX UNIT tw(QEPP) QEP input period Synchronous 2tc(SCO) cycles With input qualifier 2[1tc(SCO) + tw(IQSW)] cycles tw(INDEXH) QEP Index Input High time Synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) +tw(IQSW) cycles tw(INDEXL) QEP Index Input Low time Synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(STROBH) QEP Strobe High time Synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(STROBL) QEP Strobe Input Low time Synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) +tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. Table 6-40. eQEP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SCO) cycles 122 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TRST 1 0 C28x Core TCK/GPIO38 TCK XCLKIN GPIO38_in GPIO38_out TDO GPIO37_out TDO/GPIO37 GPIO37_in 1 0 TMS TMS/GPIO36 GPIO36_out GPIO36_in 1 1 0 TDI TDI/GPIO35 GPIO35_out GPIO35_in 1 TRST TRST = 0: JTAG Disabled (GPIO Mode) = 1: JTAG Mode TRST TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.11 JTAG Port 6.11.1 JTAG Port Device-Specific Information On the 2805x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in Figure 6-28. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device during emulation/debug since this pin will be needed for the TCK function. NOTE In 2805x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should not prevent the emulator from driving (or being driven by) the JTAG pins for successful debug. Figure 6-28. JTAG/GPIO Multiplexing Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 123 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TRST TMS TDI TDO TCK VDDIO MCU EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET 13 14 2 1 3 7 11 9 6 inches or less PD GND GND GND GND GND 5 4 6 8 10 12 JTAG Header VDDIO TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.11.1.1 Emulator Connection Without Signal Buffering for the MCU Figure 6-29 shows the connection between the MCU and JTAG header for a single-processor configuration. If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-29 shows the simpler, no-buffering situation. For the pullup and pulldown resistor values, see Section 3.2. A. See Figure 6-28 for JTAG/GPIO multiplexing. Figure 6-29. Emulator Connection Without Signal Buffering for the MCU NOTE The 2805x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header on-board, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ (typical) resistor. 124 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.12 General-Purpose Input/Output (GPIO) 6.12.1 General-Purpose Input/Output Device-Specific Information The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. Table 6-41. GPIOA MUX(1) (2) DEFAULT AT RESET PRIMARY I/O PERIPHERAL PERIPHERAL PERIPHERAL FUNCTION SELECTION 1 SELECTION 2 SELECTION 3 GPAMUX1 REGISTER (GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11) BITS 1-0 GPIO0 EPWM1A (O) Reserved Reserved 3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O) 5-4 GPIO2 EPWM2A (O) Reserved Reserved 7-6 GPIO3 EPWM2B (O) SPISOMIA (I/O) COMP2OUT (O) 9-8 GPIO4 EPWM3A (O) Reserved Reserved 11-10 GPIO5 EPWM3B (O) SPISIMOA (I/O) ECAP1 (I/O) 13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O) 15-14 GPIO7 EPWM4B (O) SCIRXDA (I) Reserved 17-16 GPIO8 EPWM5A (O) Reserved ADCSOCAO (O) 19-18 GPIO9 EPWM5B (O) Reserved Reserved 21-20 GPIO10 EPWM6A (O) Reserved ADCSOCBO (O) 23-22 GPIO11 EPWM6B (O) Reserved Reserved 25-24 GPIO12 TZ1 (I) SCITXDA (O) Reserved 27-26 GPIO13 TZ2 (I) Reserved Reserved 29-28 GPIO14 TZ3 (I) Reserved Reserved 31-30 GPIO15 TZ1 (I) Reserved Reserved GPAMUX2 REGISTER (GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11) BITS 1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I) 3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I) 5-4 GPIO18 SPICLKA (I/O) Reserved XCLKOUT (O) 7-6 GPIO19/XCLKIN SPISTEA (I/O) Reserved ECAP1 (I/O) 9-8 GPIO20 EQEP1A (I) Reserved COMP1OUT (O) 11-10 GPIO21 EQEP1B (I) Reserved COMP2OUT (O) 13-12 GPIO22 EQEP1S (I/O) Reserved Reserved 15-14 GPIO23 EQEP1I (I/O) Reserved Reserved 17-16 GPIO24 ECAP1 (I/O) Reserved Reserved 19-18 GPIO25 Reserved Reserved Reserved 21-20 GPIO26 Reserved Reserved Reserved 23-22 GPIO27 Reserved Reserved Reserved 25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I) 27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I) 29-28 GPIO30 CANRXA (I) Reserved Reserved 31-30 GPIO31 CANTXA (O) Reserved Reserved (1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should the Reserved GPxMUX1/2 register setting be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion. (2) I = Input, O = Output, OD = Open Drain Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 125 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-42. GPIOB MUX(1) DEFAULT AT RESET PERIPHERAL PERIPHERAL PERIPHERAL PRIMARY I/O FUNCTION SELECTION 1 SELECTION 2 SELECTION 3 GPBMUX1 REGISTER BITS (GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11) 1-0 GPIO32 SDAA (I/OD) EPWMSYNCI (I) ADCSOCAO (O) 3-2 GPIO33 SCLA (I/OD) EPWMSYNCO (O) ADCSOCBO (O) 5-4 GPIO34 COMP2OUT (O) Reserved COMP3OUT (O) 7-6 GPIO35 (TDI) Reserved Reserved Reserved 9-8 GPIO36 (TMS) Reserved Reserved Reserved 11-10 GPIO37 (TDO) Reserved Reserved Reserved 13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved 15-14 GPIO39 Reserved Reserved Reserved 17-16 GPIO40 EPWM7A (O) Reserved Reserved 19-18 GPIO41 EPWM7B (O) Reserved Reserved 21-20 GPIO42 Reserved Reserved COMP1OUT (O) 23-22 GPIO43 Reserved Reserved COMP2OUT (O) 25-24 GPIO44 Reserved Reserved Reserved 27-26 Reserved Reserved Reserved Reserved 29-28 Reserved Reserved Reserved Reserved 31-30 Reserved Reserved Reserved Reserved (1) I = Input, O = Output, OD = Open Drain The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: • Synchronization to SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This mode is the default mode of all GPIO pins at reset and this mode simply synchronizes the input signal to the system clock (SYSCLKOUT). • Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change. • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. The sampling period specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 6-32 (for 6 sample mode). • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral). Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral. 126 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION GPxDAT (read) Input Qualification GPxMUX1/2 High Impedance Output Control GPIOx pin XRS 0 = Input, 1 = Output Low P ower Modes Block GPxDIR (latch) Peripheral 2 Input Peripheral 3 Input Peripheral 1 Output Peripheral 2 Output Peripheral 3 Output Peripheral 1 Output Enable Peripheral 2 Output Enable Peripheral 3 Output Enable 00 01 10 11 00 01 10 11 00 01 10 11 GPxCTRL Peripheral 1 Input GPxPUD N/C LPMCR0 Internal Pullup GPIOLMPSEL GPxQSEL1/2 GPxSET GPxDAT (latch) GPxCLEAR GPxTOGGLE = Default at Reset PIE External Interrupt MUX Asynchronous path Asynchronous path GPIOXINT1SEL GPIOXINT2SEL GPIOXINT3SEL TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected. B. GPxDAT latch/read are accessed at the same memory location. C. This diagram is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the Systems Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for pin-specific variations. Figure 6-30. GPIO Multiplexing Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 127 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.12.2 General-Purpose Input/Output Register Descriptions The device supports 42 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-43 shows the GPIO register mapping. Table 6-43. GPIO Registers NAME ADDRESS SIZE (x16) DESCRIPTION GPIO CONTROL REGISTERS (EALLOW PROTECTED) GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31) GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31) GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15) GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31) GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31) GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31) GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 44) GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 44) GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 44) GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 44) GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 44) Reserved 0x6FB6 2 Reserved Reserved 0x6FBA 2 Reserved GPIO DATA REGISTERS (NOT EALLOW PROTECTED) GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31) GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31) GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31) GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31) GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 44) GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 44) GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 44) GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 44) Reserved 0x6FD8 2 Reserved Reserved 0x6FDA 2 Reserved Reserved 0x6FDC 2 Reserved Reserved 0x6FDE 2 Reserved GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED) GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31) GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31) GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select Register (GPIO0 to 31) GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31) NOTE There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers occurs to when the action is valid. 128 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION GPIO tr(GPO) tf(GPO) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.12.3 General-Purpose Input/Output Electrical Data/Timing 6.12.3.1 GPIO - Output Timing Table 6-44. General-Purpose Output Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tr(GPO) Rise time, GPIO switching low to high All GPIOs 13(1) ns tf(GPO) Fall time, GPIO switching high to low All GPIOs 13(1) ns tfGPO Toggling frequency 15 MHz (1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-44 are applicable for a 40-pF load on I/O pins. Figure 6-31. General-Purpose Output Timing Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 129 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION GPIO Signal 1 Sampling Window Output From Qualifier 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 SYSCLKOUT QUALPRD = 1 (SYSCLKOUT/2) (A) GPxQSELn = 1,0 (6 samples) [(SYSCLKOUT cycle * 2 * QUALPRD) * 5 ] (C) Sampling Period determined by GPxCTRL[QUALPRD] (B) (D) tw(SP) tw(IQSW) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.12.3.2 GPIO - Input Timing Table 6-45. General-Purpose Input Timing Requirements MIN MAX UNIT QUALPRD = 0 1tc(SCO) cycles tw(SP) Sampling period QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles Synchronous mode 2tc(SCO) cycles tw(GPI) (2) Pulse duration, GPIO low/high With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO) cycles (1) "n" represents the number of qualification samples as defined by GPxQSELn register. (2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal. A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. The QUALPRD bit field value can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled). B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins. C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used. D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This condition would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13- SYSCLKOUT-wide pulse ensures reliable recognition. Figure 6-32. Sampling Mode 130 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION VDDIO VSS VSS 2 pF > 1 MS GPIOxn SYSCLK tw(GPI) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.12.3.3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT. Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0 Sampling frequency = SYSCLKOUT, if QUALPRD = 0 Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0 In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT. Sampling period = SYSCLKOUT cycle, if QUALPRD = 0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. The number of samples is determined by the value written to GPxQSELn register. Case 1: Qualification using 3 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0 Case 2: Qualification using 6 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0 Figure 6-33. General-Purpose Input Timing Figure 6-34. Input Resistance Model for a GPIO Pin With an Internal Pull-up Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 131 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION WAKE INT (A)(B) XCLKOUT Address/Data (internal) td(WAKE−IDLE) tw(WAKE−INT) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.12.3.4 Low-Power Mode Wakeup Timing Table 6-46 shows the timing requirements, Table 6-47 shows the switching characteristics, and Figure 6- 35 shows the timing diagram for IDLE mode. Table 6-46. IDLE Mode Timing Requirements(1) MIN MAX UNIT Without input qualifier 2tc(SCO) tw(WAKE-INT) Pulse duration, external wake-up signal cycles With input qualifier 5tc(SCO) + tw(IQSW) (1) For an explanation of the input qualifier parameters, see Table 6-45. Table 6-47. IDLE Mode Switching Characteristics(1) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT Delay time, external wake signal to program execution resume (2) cycles • Wake-up from Flash Without input qualifier 20tc(SCO) cycles – Flash module in active state With input qualifier 20tc(SCO) + tw(IQSW) td(WAKE-IDLE) • Wake-up from Flash Without input qualifier 1050tc(SCO) cycles – Flash module in sleep state With input qualifier 1050tc(SCO) + tw(IQSW) • Wake-up from SARAM Without input qualifier 20tc(SCO) cycles With input qualifier 20tc(SCO) + tw(IQSW) (1) For an explanation of the input qualifier parameters, see Table 6-45. (2) This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake-up) signal involves additional latency. A. WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-35. IDLE Entry and Exit Timing 132 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 6-48. STANDBY Mode Timing Requirements MIN MAX UNIT Pulse duration, external Without input qualification 3tc(OSCCLK) tw(WAKE-INT) wake-up signal cycles With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK) (1) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 6-49. STANDBY Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT t Delay time, IDLE instruction d(IDLE-XCOL) executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles Delay time, external wake signal to program execution cycles resume(1) • Wake up from flash Without input qualifier 100tc(SCO) cycles – Flash module in active state With input qualifier 100tc(SCO) + tw(WAKE-INT) td(WAKE-STBY) Without input qualifier 1125tc(SCO) • Wake up from flash cycles – Flash module in sleep state With input qualifier 1125tc(SCO) + tw(WAKE-INT) Without input qualifier 100tc(SCO) • Wake up from SARAM cycles With input qualifier 100tc(SCO) + tw(WAKE-INT) (1) This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up signal) involves additional latency. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 133 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION td(IDLE−XCOL) Wake-up Signal (H) X1/X2 or XCLKIN XCLKOUT Flushing Pipeline (A) Device Status STANDBY STANDBY Normal Execution (B) (G) (C) (D)(E) (F) tw(WAKE-INT) td(WAKE-STBY) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off: • 16 cycles, when DIVSEL = 00 or 01 • 32 cycles, when DIVSEL = 10 • 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. D. The external wake-up signal is driven active. E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. F. After a latency period, the STANDBY mode is exited. G. Normal execution resumes. The device will respond to the interrupt (if enabled). H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-36. STANDBY Entry and Exit Timing Diagram Table 6-50. HALT Mode Timing Requirements MIN MAX UNIT tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles Table 6-51. HALT Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles tp PLL lock-up time 1 ms Delay time, PLL lock to program execution resume • Wake up from flash 1125tc(SCO) cycles td(WAKE-HALT) – Flash module in sleep state • Wake up from SARAM 35tc(SCO) cycles 134 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION td(IDLE−XCOL) X1/X2 or XCLKIN XCLKOUT HALT HALT Wake-up Latency Flushing Pipeline td(WAKE−HALT Device Status PLL Lock-up Time Normal Execution tw(WAKE-GPIO) GPIOn (I) Oscillator Start-up Time (A) (G) (C) (D)(E) (F) (B) (H) ) tp TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off and the CLKIN to the core is stopped: • 16 cycles, when DIVSEL = 00 or 01 • 32 cycles, when DIVSEL = 10 • 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. Keeping INTOSC1, INTOSC2, and the watchdog alive in HALT mode is done by writing to the appropriate bits in the CLKCTL register. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized, which enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode. E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms. G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited. H. Normal operation resumes. I. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-37. HALT Wake-Up Using GPIOn Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 135 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 7 Device and Documentation Support 7.1 Device Support 7.1.1 Development Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of 2805x-based applications: Software Development Tools • Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator • Application algorithms • Sample applications code Hardware Development Tools • Development and evaluation boards • JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100 • Flash programming tools • Power supply • Documentation and cables For a complete listing of development-support tools for the processor platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 7.1.2 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes: TMX, TMP, or TMS (for example, TMX320F28055). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product 136 Device and Documentation Support Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION PREFIX TMX TMX = experimental device TMP = prototype device TMS = qualified device 320 DEVICE FAMILY 320 = TMS320 MCU Family F TECHNOLOGY F = Flash 28055 DEVICE 28055 28054 28053 28052 28051 28050 PN PACKAGE TYPE 80-Pin PN Low-Profile Quad Flatpack (LQFP) TEMPERATURE RANGE T −40°C to 105°C −40°C to 125°C T S = = TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PN) and temperature range (for example, T). Figure 7-1 provides a legend for reading the complete device name for any family member. For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 Piccolo MCU Silicon Errata (literature number SPRZ362). Figure 7-1. Device Nomenclature Copyright © 2012, Texas Instruments Incorporated Device and Documentation Support 137 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 7.2 Documentation Support Extensive documentation supports all of the TMS320™ MCU family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. The following documents can be downloaded from the TI website (www.ti.com): Data Manual and Errata SPRS797 TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 Piccolo Microcontrollers Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the 2805x devices. SPRZ362 TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 Piccolo MCU Silicon Errata describes known advisories on silicon and provides workarounds. Technical Reference Manual SPRUHE5 TMS320x2805x Piccolo Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the 2805x microcontrollers. CPU User's Guides SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference Guide also describes emulation features available on these DSPs. Peripheral Guides SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). Tools Guides SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core. 7.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 138 Device and Documentation Support Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 8 Mechanical Packaging and Orderable Information 8.1 Thermal Data for Package Table 8-1 shows the thermal data. See Section 2.9 for more information on thermal design considerations. Table 8-1. Thermal Model 80-Pin PN Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 49.9 38.3 36.7 34.4 ΨJT [°C/W] 0.8 1.18 1.34 1.62 ΨJB 21.6 20.7 20.5 20.1 θJC 14.2 θJB 21.9 8.2 Packaging Information The following packaging information and addendum reflect the most current data available for the designated devices. This data is subject to change without notice and without revision of this document. Copyright © 2012, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 139 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 PACKAGE OPTION ADDENDUM www.ti.com 1-Dec-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Samples (Requires Login) TMS320F28050PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28050PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28050PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28051PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28051PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28051PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28052PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28052PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28052PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28053PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28053PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28053PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28054MPNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI TMS320F28054PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28054PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28054PNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28055PNQ PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28055PNS PREVIEW LQFP PN 80 119 TBD Call TI Call TI TMS320F28055PNT ACTIVE LQFP PN 80 119 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMX320F28055PNT ACTIVE LQFP PN 80 1 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. PACKAGE OPTION ADDENDUM www.ti.com 1-Dec-2012 Addendum-Page 2 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 4040135 /B 11/96 0,17 0,27 0,13 NOM 40 21 0,25 0,45 0,75 0,05 MIN Seating Plane Gage Plane 60 41 61 80 20 SQ SQ 1 13,80 14,20 12,20 9,50 TYP 11,80 1,45 1,35 1,60 MAX 0,08 0,50 0,08 M 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated REF102 SBVS022A – SEPTEMBER 2000 – REVISED NOVEMBER 2003 www.ti.com FEATURES +10V ±0.0025V OUTPUT VERY LOW DRIFT: 2.5ppm/°C max EXCELLENT STABILITY: 5ppm/1000hr typ EXCELLENT LINE REGULATION: 1ppm/V max EXCELLENT LOAD REGULATION: 10ppm/mA max LOW NOISE: 5μVPP typ, 0.1Hz to 10Hz WIDE SUPPLY RANGE: 11.4VDC to 36VDC LOW QUIESCENT CURRENT: 1.4mA max PACKAGE OPTIONS: PLASTIC DIP, SO-8 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000-2003, Texas Instruments Incorporated 10V Precision Voltage Reference Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. APPLICATIONS PRECISION-CALIBRATED VOLTAGE STANDARD D/A AND A/D CONVERTER REFERENCE PRECISION CURRENT REFERENCE ACCURATE COMPARATOR THRESHOLD REFERENCE DIGITAL VOLTMETERS TEST EQUIPMENT PC-BASED INSTRUMENTATION DESCRIPTION The REF102 is a precision 10V voltage reference. The drift is laser-trimmed to 2.5ppm/°C max C-grade over the industrial temperature range. The REF102 achieves its precision without a heater. This results in low power, fast warm-up, excellent stability, and low noise. The output voltage is extremely insensitive to both line and load variations and can be externally adjusted with minimal effect on drift and stability. Single supply operation from 11.4V to 36V and excellent overall specifications make the REF102 an ideal choice for demanding instrumentation and system reference applications. – + A R2 R3 R4 R6 R1 R5 1 50kΩ 22kΩ 7kΩ 4kΩ 8kΩ DZ1 Noise Reduction Common VOUT Trim V+ 14kΩ 5 2 6 8 4 REF102 REF102 REF102 2 www.ti.com SBVS022A SPECIFIED MAX INITIAL MAX DRIFT PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT ERROR (mV) (PPM/°C) PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY REF102AU ±10 ±10 SO-8 D –25°C to +85°C REF102AU REF102AU Tube, 100 " ±10 ±10 SO-8 D " REF102AU/2K5 REF102AU/2K5 Tape and Reel, 2500 REF102AP ±10 ±10 DIP-8 P " REF102AP REF102AP Tube, 50 REF102BU ±5 ±5 SO-8 D " REF102BU REF102BU Tube, 100 " ±5 ±5 SO-8 D " REF102BU/2K5 REF102BU/2K5 Tape and Reel, 2500 REF102BP ±5 ±5 DIP-8 P " REF102BP REF102BP Tube, 50 REF102CU ±2.5 ±2.5 SO-8 D " REF102CU REF102CU Tube, 100 " ±2.5 ±2.5 SO-8 D " REF102CU/2K5 REF102CU/2K5 Tape and Reel, 2500 REF102CP ±2.5 ±2.5 DIP-8 P " REF102CP REF102CP Tube, 50 PIN CONFIGURATIONS Top View DIP, SO Input Voltage ...................................................................................... +40V Operating Temperature P, U ................................................................................. –25°C to +85°C Storage Temperature Range P, U ............................................................................... –40°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C (SO, 3s) ........................................................... +260°C Short-Circuit Protection to Common or V+ .............................. Continuous NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. 8 7 6 5 1 2 3 4 NC = Not Connected Noise Reduction NC VOUT Trim NC V+ Com NC REF102 3 SBVS022A www.ti.com ELECTRICAL CHARACTERISTICS At TA = +25°C and VS = +15V power supply, unless otherwise noted. REF102A REF102B REF102C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS OUTPUT VOLTAGE Initial TA = 25°C 9.99 10.01 9.995 10.005 9.9975 10.0025 V vs Temperature (1) 10 5 2.5 ppm/°C vs Supply (Line Regulation) VS = 11.4V to 36V 2 1 1 ppm/V vs Output Current (Load Regulation) IL = 0mA to +10mA 20 10 10 ppm/mA IL = 0mA to –5mA 40 20 20 ppm/mA vs Time TA = +25°C M Package 5 ✻ ✻ ppm/1000hr P, U Packages (2) 20 ✻ ppm/1000hr Trim Range (3) ±3 ✻ ✻ % Capacitive Load, max 1000 ✻ ✻ pF NOISE 0.1Hz to 10Hz 5 ✻ ✻ μVPP OUTPUT CURRENT +10, –5 ✻ ✻ mA INPUT VOLTAGE RANGE +11.4 +36 ✻ ✻ ✻ ✻ V QUIESCENT CURRENT IOUT = 0 +1.4 ✻ ✻ mA WARM-UP TIME (4) To 0.1% 15 ✻ ✻ μs TEMPERATURE RANGE Specification REF102A, B, C –25 +85 ✻ ✻ ✻ ✻ °C ✻ Specifications same as REF102A. NOTES: (1) The “box” method is used to specify output voltage drift vs temperature. See the Discussion of Performance section. (2) Typically 5ppm/1000hrs after 168hr powered stabilization. (3) Trimming the offset voltage affects drift slightly. See Installation and Operating Instructions for details. (4) With noise reduction pin floating. See Typical Characteristics for details. REF102 4 www.ti.com SBVS022A TYPICAL CHARACTERISTICS At TA = +25°C, VS = +15V, unless otherwise noted. POWER TURN-ON RESPONSE VOUT VIN Time (5μs/div) Power Turn-On POWER TURN-ON RESPONSE with 1μF CN VOUT VIN Time (10ms/div) Power Turn-On POWER SUPPLY REJECTION vs FREQUENCY 130 120 110 100 90 80 70 60 1 100 1k 10k Frequency (Hz) Power Supply Rejection (dB) LOAD REGULATION +1.5 +1.0 +0.5 0 −0.5 −1.0 −1.5 –5 0 +5 +10 Output Current (mA) Output Voltage Change (mV) RESPONSE TO THERMAL SHOCK 0 15 30 45 60 +600 +300 0 –300 –600 TA = +25°C REF102C Immersed in +85°C Fluorinert Bath Output Voltage Change (μV) Time (s) TA = +85°C QUIESCENT CURRENT vs TEMPERATURE 1.6 1.4 1.2 1.0 0.8 −50 −25 0 +25 +50 +75 +100 +125 Temperature (°C) Quiescent Current (mA) −75 REF102 5 SBVS022A www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +15V, unless otherwise noted. TYPICAL REF102 REFERENCE NOISE 6 4 2 0 −2 −4 −6 Low Frequency Noise (1s/div) (See Noise Test Circuit) Noise Voltage (μV) – + OPA227 DUT Noise Test Circuit. 100μF 15.8kΩ 20Ω 2kΩ 8kΩ 2μF Oscilloscope Gain = 100V/V f − 3 d B = 0.1Hz and 10Hz THEORY OF OPERATION Refer to the diagram on the first page of this data sheet. The 10V output is derived from a compensated buried zener diode DZ1, op amp A1, and resistor network R1 – R6. Approximately 8.2V is applied to the non-inverting input of A1 by DZ1. R1, R2, and R3 are laser-trimmed to produce an exact 10V output. The zener bias current is established from the regulated output voltage through R4. R5 allows user-trimming of the output voltage by providing for small external adjustment of the amplifier gain. Because the temperature coefficient (TCR) of of R5 closely matches the TCR of R1, R2 and R3 , the voltage trim has minimal effect on the reference drift. The output voltage noise of the REF102 is dominated by the noise of the zener diode. A capacitor can be connected between the Noise Reduction pin and ground to form a lowpass filter with R6 and roll off the high-frequency noise of the zener. DISCUSSION OF PERFORMANCE The REF102 is designed for applications requiring a precision voltage reference where both the initial value at room temperature and the drift over temperature are of importance to the user. Two basic methods of specifying voltage reference drift versus temperature are in common usage in the industry—the “butterfly method” and the “box method.” The REF102 is specified by the more commonly-used “box method.” The “box” is formed by the high and low specification temperatures and a diagonal, the slope of which is equal to the maximum specified drift. Since the shape of the actual drift curve is not known, the vertical position of the box is not known, either. It is, however, bounded by VUPPER BOUND and VLOWER BOUND (see Figure 1). Figure 1 uses the REF102CU as an example. It has a drift specification of 2.5ppm/°C maximum and a specification temperature range of –25°C to +85°C. The “box” height, V1 to V2, is 2.75mV. REF102CU VUPPER BOUND +10.00275 V1 VNOMINAL +10.0000 2.75mV Worst-case ΔVOUT for REF102CU V2 +9.99725 REF102CU VLOWER BOUND −25 0 +25 +50 +85 Output Voltage (V) Temperature (°C) FIGURE 1. REF102CU Output Voltage Drift. REF102 6 www.ti.com SBVS022A INSTALLATION AND OPERATING INSTRUCTIONS BASIC CIRCUIT CONNECTION Figure 2 shows the proper connection of the REF102. To achieve the specified performance, pay careful attention to layout. A low resistance star configuration will reduce voltage errors, noise pickup, and noise coupled from the power supply. Commons should be connected as indicated, being sure to minimize interconnection resistances. OPTIONAL OUTPUT VOLTAGE ADJUSTMENT Optional output voltage adjustment circuits are shown in Figures 3 and 4. Trimming the output voltage will change the voltage drift by approximately 0.008ppm/°C per mV of trimmed voltage. In the circuit in Figure 3, any mismatch in TCR between the two sections of the potentiometer will also affect drift, but the effect of the ΔTCR is reduced by a factor of five by the internal resistor divider. A high quality potentiometer, with good mechanical stability, such as a cermet, should be REF102 1μF Tantalum + RL 1 RL 2 RL 3 V+ (1) 2 (2) (1) (2) 4 6 NOTES: (1) Lead resistances here of up to a few ohms have negligible effect on performance. (2) A resistance of 0.1Ω in series with these leads will cause a 1mV error when the load current is at its maximum of 10mA. This results in a 0.01% error of 10V. FIGURE 2. REF102 Installation. REF102 1μF Tantalum + V+ 2 4 20k Output Voltage Adjust Minimum range (±300mV) and minimal degradation of drift. Ω +10V 5 VTRIM 6 VOUT FIGURE 3. REF102 Optional Output Voltage Adjust. REF102 V+ 2 4 20k Output Voltage Adjust Higher resolution, reduced range (typically ±25mV). Ω +10V 5 VTRIM 6 VOUT RS 1M Ω 1μF Tantalum + FIGURE 4. REF102 Optional Output Voltage, Fine Adjust. used. The circuit in Figure 3 has a minimum trim range of ±300mV. The circuit in Figure 4 has less range but provides higher resolution. The mismatch in TCR between RS and the internal resistors can introduce some slight drift. This effect is minimized if RS is kept significantly larger than the 50kΩ internal resistor. A TCR of 100ppm/°C is normally sufficient. REF102 7 SBVS022A www.ti.com OPTIONAL NOISE REDUCTION The high-frequency noise of the REF102 is dominated by the zener diode noise. This noise can be greatly reduced by connecting a capacitor between the Noise Reduction pin and ground. The capacitor forms a low-pass filter with R6 (refer to the figure on page 1) and attenuates the high-frequency noise generated by the zener. Figure 5 shows the effect of a 1μF noise reduction capacitor on the high-frequency noise of the REF102. R6 is typically 7kΩ so the filter has a –3dB frequency of about 22Hz. The result is a reduction in noise from about 800μVPP to under 200μVPP. If further noise reduction is required, use the circuit in Figure 14. APPLICATIONS INFORMATION High accuracy, extremely low drift, outstanding stability, and low cost make the REF102 an ideal choice for all instrumentation and system reference applications. Figures 6 through 14 show a variety of useful application circuits. 6 b) Precision –10V Reference. a) Resistor Biased –10V Reference RS IL 4 REF102 2 −10V Out See SBVA008 for more detail. V+ (1.4V to 26V) 1.4mA < < 5.4mA (5V −IL) RS 2 6 4 10V OPA227 R1 2kΩ C 1000pF 1 −10V Out −15V REF102 V+ (1.4V to 26V) FIGURE 6. –10V Reference Using a) Resistor or b) OPA227. NO CN CN = 1μF FIGURE 5. Effect of 1μF Noise Reduction Capacitor on Broadband Noise (f–3dB = 1MHz) REF102 8 www.ti.com SBVS022A FIGURE 7. +10V Reference With Output Current Boosted to: a) ±20mA, b) +100mA, and c) IL (TYP) +10mA, –5A. Ω – + OPA227 6 220 +10V IL 6 +10V IL 2N2905 6 +10V 4 IL REF102 V+ a) −20mA < IL < +20mA (OPA227 also improves transient immunity) b) −5mA < IL < +100mA c) IL (MAX) = IL (TYP) +10mA IL (MIN) = IL (TYP) −5mA VCC − 10V IL (TYP) R1 = 2 4 REF102 V+ 2 4 REF102 V+ 2 – + INA126 V x100 2 4 6 +15V −5V –15V 357 1/2W Ω 2 3 OPA227 – + 357 1/2W Ω 28mA 28.5mA +5V 350 Strain Gauge Bridge Ω 5 10 R 8 G OUT 6 REF102 V+ REF102 6 4 2 3 See SBVA007 for more details. 1 25kΩ 25kΩ 25kΩ 25kΩ INA105 5 6 +10V Out −10V Out 2 – + LOAD IOUT Can be connected to ground or −VS . V+ REF102 2 6 4 OPA277 R IOUT = , R ≥ 1kΩ See SBVA001 for more details and ISINK Circuit. 10V R FIGURE 8. Strain Gauge Conditioner for 350Ω Bridge. FIGURE 9. ±10V Reference. FIGURE 10. Positive Precision Current Source. REF102 9 SBVS022A www.ti.com 6 +30V 31.4V to 56V 2 4 6 2 6 2 4 +20V +10V REF102 4 REF102 REF102 NOTES: (1) REF102s can be stacked to obtain voltages in multiples of 10V. (2) The supply voltage should be between 10n + 1.4 and 10n + 26, where n is the number of REF102s. (3) Output current of each REF102 must not exceed its rated output current of +10, −5mA. This includes the current delivered to the lower REF102. – + 2 4 6 +5V Out INA105 2 5 1 3 6 –5V Out REF102 V+ – + 2 4 6 +10V +5V INA105 5 1 3 6 2 REF102 V+ Ω – + OPA227 6 2k +10V REF102 (2) 2 R 1k 1 4 VOUT 2 Ω C VREF 1 1μF C2 1μF R2 2kΩ VREF = (V01 + V02 … VOUT N) N eN = 5μVPP (f = 0.1Hz to 1MHz) See SBVA002 for more details. √N 2 3 Ω 6 2k REF102 (1) 2 4 VOUT 1 Ω 6 2k VOUT N V+ REF102 (N) 2 4 V+ V+ FIGURE 11. Stacked References. FIGURE 12. ±5V Reference. FIGURE 13. +5V and +10V Reference. FIGURE 14. Precision Voltage Reference with Extremely Low Noise. PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) REF102AM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI REF102AP ACTIVE PDIP P 8 50 TBD Call TI Level-NA-NA-NA REF102AU ACTIVE SOIC D 8 100 TBD CU NIPDAU Level-2-240C-1 YEAR REF102AU/2K5 ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR REF102BM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI REF102BP ACTIVE PDIP P 8 50 TBD Call TI Level-NA-NA-NA REF102BU ACTIVE SOIC D 8 100 TBD CU NIPDAU Level-2-240C-1 YEAR REF102CM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI REF102CP ACTIVE PDIP P 8 50 TBD Call TI Level-NA-NA-NA REF102CU ACTIVE SOIC D 8 100 TBD CU NIPDAU Level-2-240C-1 YEAR REF102RM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI REF102SM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2005 Addendum-Page 1 MECHANICAL DATA MMBC008 – MARCH 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 LMC (O–MBCY–W8) METAL CYLINDRICAL 4202483/A 03/01 4 3 2 1 8 7 6 5 0.335 (8,51) 0.500 (12,70) MIN 0.021 (0,53) 0.016 (0,41) 0.040 (1,02) 0.305 (7,75) 0.010 (0,25) 0.335 (8,51) 0.165 (4,19) 0.185 (4,70) 0.370 (9,40) 0.040 (1,02) MAX 0.105 (2,67) 0.095 (2,41) 0.140 (3,56) 0.160 (4,06) 0.095 (2,41) 0.105 (2,67) 0.028 (0,71) 0.034 (0,86) 0.045 (1,14) 0.029 (0,74) ø ø ø ø Seating Plane 0.200 (5,08) 45° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Leads in true position within 0.010 (0,25) R @ MMC at seating plane. D. Pin numbers shown for reference only. Numbers may not be marked on package. E. Falls within JEDEC MO-002/TO-99. MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 8 4 0.015 (0,38) Gage Plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM MAX 0.430 (10,92) 4040082/D 05/98 0.200 (5,08) MAX 0.125 (3,18) MIN 5 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 1 0.015 (0,38) 0.021 (0,53) Seating Plane 0.010 (0,25) M 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 Direct Upgrades to TL05x, TL07x, and TL08x BiFET Operational Amplifiers Greater Than 2× Bandwidth (10 MHz) and 3× Slew Rate (45 V/μs) Than TL08x On-Chip Offset Voltage Trimming for Improved DC Performance Wider Supply Rails Increase Dynamic Signal Range to ±19 V description The TLE208x series of JFET-input operational amplifiers more than double the bandwidth and triple the slew rate of the TL07x and TL08x families of BiFET operational amplifiers. The TLE208x also have wider supply-voltage rails, increasing the dynamic-signal range for BiFET circuits to ±19 V. On-chip zener trimming of offset voltage yields precision grades for greater accuracy in dc-coupled applications. The TLE208x are pin-compatible with lower performance BiFET operational amplifiers for ease in improving performance in existing designs. BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors, without sacrificing the output drive associated with bipolar amplifiers. This makes these amplifiers better suited for interfacing with high-impedance sensors or very low level ac signals. They also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption. Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to observe common-mode input-voltage limits and output voltage swing when operating from a single supply. DC biasing of the input signal is required and loads should be terminated to a virtual ground node at mid-supply. Texas Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from single supplies. The TLE208x are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems, Texas Instruments LinCMOS families of operational amplifiers (TLC- and TLV-prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to slew rate and bandwidth requirements and output loading. For BiFET circuits requiring low noise and/or tighter dc precision, the TLE207x offer the same ac response as the TLE208x with more stringent dc and noise specifications. PRODUCTION DATA information is current as of publication date. Copyright 2001, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2081 AVAILABLE OPTIONS PACKAGED DEVICES CHIP TA VIOmax AT 25°C SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) FORM (Y) 0°C to 70°C 3 mV TLE2081ACD TLE2081ACP — 6 mV TLE2081CD — — TLE2081CP TLE2081Y 40°C to 85°C 3 mV TLE2081AID TLE2081AIP –6 mV TLE2081ID — — TLE2081IP — 55°C to 125°C 3 mV TLE2081AMFK TLE2081AMJG –6 mV — TLE2081MFK TLE2081MJG — — † The D packages are available taped and reeled. Add R suffix to device type (e.g., TLE2081ACDR). ‡ Chip forms are tested at TA = 25°C only. TLE2082 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25°C SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) CHIP FORM (Y) 0°C to 70°C 4 mV TLE2082ACD TLE2082ACP 7 mV TLE2082CD — — TLE2082CP — 40°C to 85°C 4 mV TLE2082AID TLE2082AIP –TLE2082Y 7 mV TLE2082ID — — TLE2082IP 55°C to 125°C 4 mV TLE2082AMD TLE2082AMFK TLE2082AMJG TLE2082AMP –7 mV TLE2082MD TLE2082MFK TLE2082MJG TLE2082MP — ‡ The D packages are available taped and reeled. Add R suffix to device type (e.g., TLE2082ACDR). ‡ Chip forms are tested at TA = 25°C only. TLE2084 AVAILABLE OPTIONS PACKAGED DEVICES CHIP TA VIOmax AT 25°C SMALL OUTLINE (DW) CHIP CARRIER (FK) CERAMIC DIP (J) PLASTIC DIP (N) FORM (Y) 0°C to 70°C 4 mV TLE2084ACDW TLE2084ACN — 7 mV TLE2084CDW — — TLE2084CN TLE2084Y 55°C to 125°C 4 mV TLE2084AMFK TLE2084AMJ –7 mV — TLE2084MFK TLE2084MJ — — † The DW packages are available taped and reeled. Add R suffix to device type (e.g., TLE2084ACDWR). ‡ Chip forms are tested at TA = 25°C only. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 1 2 3 4 8 7 6 5 OFFSET N1 IN – IN + VCC– NC VCC+ OUT OFFSET N2 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 NC VCC+ NC OUT NC NC IN – NC IN + NC NC OFFSET N1 NC NC NC NC V NC OFFSET N2 NC CC – TLE2081 D, JG, OR P PACKAGE (TOP VIEW) TLE2081 FK PACKAGE (TOP VIEW) 1 2 3 4 8 7 6 5 1OUT 1IN– 1IN + VCC– VCC+ 2OUT 2IN– 2IN+ 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 NC 2OUT NC 2IN– NC NC 1IN– NC 1IN+ NC NC 1OUT NC NC NC NC V NC 2IN + CC – V CC + TLE2082 D, JG, OR P PACKAGE (TOP VIEW) TLE2082 FK PACKAGE (TOP VIEW) 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 4IN+ NC VCC– NC 3IN+ 1IN+ NC VCC+ NC 2IN+ TLE2084 FK PACKAGE (TOP VIEW) 1IN – 1OUT NC 3IN – 4IN – 2 IN – NC 3OUT 2OUT 4OUT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1OUT 1IN– 1IN+ VCC+ 2IN+ 2IN– 2OUT NC 4OUT 4IN– 4IN+ VCC– 3IN+ 3IN– 3OUT NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1OUT 1IN– 1IN+ VCC+ 2IN+ 2IN– 2OUT 4OUT 4IN– 4IN+ VCC– 3IN+ 3IN– 3OUT TLE2084 J OR N PACKAGE (TOP VIEW) TLE2084 DW PACKAGE (TOP VIEW) NC – No internal connection symbol + – OUT IN+ IN– TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2081Y chip information This chip, when properly assembled, displays characteristics similar to the TLE2081. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (4) IS INTERNALLY CONNECTED TO BACKSIDE OF THE CHIP. + – OUT IN+ IN– VCC+ (6) (3) (2) (5) (1) (7) (4) OFFSET N1 OFFSET N2 VCC– 58 85 (1) (2) (4) (5) (6) (7) (8) (3) TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLE2082Y chip information This chip, when properly assembled, displays characteristics similar to the TLE2082. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (4) IS INTERNALLY CONNECTED TO BACKSIDE OF THE CHIP. + – 1OUT 1IN+ 1IN– VCC+ (4) (6) (3) (2) (5) (1) (7) (8) – + 2OUT 2IN+ 2IN– VCC– 80 90 (1) (2) (3) (4) (5) (6) (7) (8) TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2084Y chip information This chip, when properly assembled, displays characteristics similar to the TLE2084. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (11) IS INTERNALLY CONNECTED TO BACKSIDE OF THE CHIP. + – 1OUT 1IN+ 1IN– VCC+ (11) (6) (3) (2) (5) (1) (7) (4) – + 2OUT 2IN+ 2IN– VCC– + – 3OUT 3IN+ 3IN– (13) (10) (9) (12) (8) (14) – + 4OUT 4IN+ 4IN– (2) (1) (14) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) 100 150 (3) TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 equivalent schematic (each channel) Q1 IN– IN+ Q2 D1 Q7 Q5 Q6 Q9 Q10 C2 R4 Q14 Q4 Q3 R1 Q8 R2 Q11 R3 C1 Q12 D2 Q13 Q15 Q16 Q19 Q20 Q17 R6 VCC– VCC+ R8 C3 Q18 R7 R5 C4 Q21 C5 R9 R10 Q22 Q26 Q27 Q31 R14 Q29 Q25 C6 Q30 R11 Q23 Q28 Q24 D3 OUT R13 R12 OFFSET N1 (see Note A) OFFSET N2 (see Note A) NOTE A: OFFSET N1 and OFFSET N2 are only availiable on the TLE2081x devices. ACTUAL DEVICE COMPONENT COUNT COMPONENT TLE2081 TLE2082 TLE2084 Transistors 33 57 114 Resistors 25 37 74 Diodes 8 5 10 Capacitors 6 11 22 TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V Supply voltage, VCC– (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –19 V Differential input voltage range, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC+ to VCC– Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC+ to VCC– Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80 mA Total current into VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA Total current out of VCC– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. 2. Differential voltages are at IN+ with respect to IN–. 3. The output can be shorted to either supply. Temperatures and/or supply voltages must be limited to ensure that the maximum dissipation rate is not exceeded. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW DW 1025 mW 8.2 mW/°C 656 mW 533 mW 205 mW FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW N 1150 mW 9.2 mW/°C 736 mW 598 mW 230 mW P 1000 mW 8.0 mW/°C 640 mW 344 mW 200 mW recommended operating conditions C SUFFIX I SUFFIX M SUFFIX UNIT MIN MAX MIN MAX MIN MAX Supply voltage, VCC± ±2.25 ±19 ±2.25 ±19 ±2.25 ±19 V Common mode input voltage VIC VCC± = ±5 V –0.9 5 –0.8 5 –0.8 5 Common-voltage, V VCC± = ±15 V –10.9 15 –10.8 15 –10.8 15 Operating free-air temperature, TA 0 70 –40 85 –55 125 °C TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLE2081C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2081C TLE2081AC TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.34 6 0.3 3 mV VIC = 0, VO = 0, Full range 8 5 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 3.2 29 3.2 29 μV/°C IIO Input offset current 25°C 5 100 5 100 nA VIC = 0, VO = 0, Full range 1.4 1.4 IIB Input bias current IC , O , See Figure 4 25°C 15 175 15 175 nA Full range 5 5 5 5 5 5 25°C to to to to VICR Common-mode input RS = 50 Ω –1 –1.9 –1 –1.9 V voltage range 5 5 Full range to g to –0.9 –0.9 IO = 200 μA 25°C 3.8 4.1 3.8 4.1 –Full range 3.7 3.7 VOM Maximum positive peak IO = 2 mA 25°C 3.5 3.9 3.5 3.9 VOM+ V output voltage swing –Full range 3.4 3.4 IO = 20 mA 25°C 1.5 2.3 1.5 2.3 –Full range 1.5 1.5 IO = 200 μA 25°C –3.5 –4.2 –3.5 –4.2 Full range –3.4 –3.4 VOM Maximum negative peak IO = 2 mA 25°C –3.7 –4.1 –3.7 –4.1 VOM– V g output voltage swing Full range –3.6 –3.6 IO = 20 mA 25°C –1.5 –2.4 –1.5 –2.4 Full range –1.5 –1.5 RL = 600 Ω 25°C 80 91 80 91 Full range 79 79 AVD Large-signal differential VO = ± 2 3 V RL = 2 kΩ 25°C 90 100 90 100 dB g g voltage amplification 2.3 Full range 89 89 RL = 10 kΩ 25°C 95 106 95 106 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, Common mode 25°C 11 11 IC pF , See Figure 5 Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 70 89 70 89 dB rejection ratio IC ICR , VO = 0, RS = 50 Ω Full range 68 68 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio(ΔVCC± /ΔVIO) CC± VO = 0, RS = 50 Ω Full range 80 80 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2081C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2081C TLE2081AC TA† UNIT MIN TYP MAX MIN TYP MAX ICC Supply current VO = 0 No load 25°C 1.35 1.6 2.2 1.35 1.6 2.2 0, mA Full range 2.2 2.2 IOS Short-circuit output VO = 0 VID = 1 V 25°C –35 –35 mA current VID = –1 V 45 45 † Full range is 0°C to 70°C. TLE2081C operating characteristics at specified free-air temperature, VCC± = ±5 V PARAMETER TEST CONDITIONS T † TLE2081C TLE2081AC TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 35 35 SR+ Positive slew rate VO(PP) = ±2.3 V, AVD 1 RL 2 kΩ Full range 23 23 V/μs = –1, = kΩ, CL = 100 pF, See Figure 1 25°C 38 38 SR– Negative slew rate F, Full range 23 23 V/μs t Settling time AVD = –1, 2-V step, To 10 mV 25°C 0.25 0.25 ts , μs RL = 1 kΩ, CL = 100 pF To 1 mV 0.4 0.4 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1 Hz to 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz THD + N Total harmonic distortion VO(PP) = 5 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 013% 0 013% plus noise = kHz, = kΩ, RS = 25 Ω 0.013% 0.013% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 9 4 9 4 MHz , L , CL = 25 pF, See Figure 2 9.4 9.4 BOM Maximum output-swing VO(PP) = 4 V, AVD = –1, 25°C 2 8 2 8 MHz g bandwidth O(, VD , RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ Phase margin at unity gain VI = 10 mV, RL = 2 kΩ, φm I 25°C 56° 56° , L , CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLE2081C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2081C TLE2081AC TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.49 6 0.47 3 mV VIC = 0, VO = 0, Full range 8 5 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 3.2 29 3.2 29 μV/°C IIO Input offset current 25°C 6 100 6 100 nA VIC = 0, VO = 0, Full range 1.4 1.4 IIB Input bias current IC , O , See Figure 4 25°C 20 175 20 175 nA Full range 5 5 15 15 15 15 25°C to to to to VICR Common-mode input RS = 50 Ω –11 –11.9 –11 –11.9 V voltage range 15 15 Full range to g to –10.9 –10.9 IO = 200 μA 25°C 13.8 14.1 13.8 14.1 –Full range 13.7 13.7 VOM Maximum positive peak IO = 2 mA 25°C 13.5 13.9 13.5 13.9 VOM+ V output voltage swing –Full range 13.4 13.4 IO = 20 mA 25°C 11.5 12.3 11.5 12.3 –Full range 11.5 11.5 IO = 200 μA 25°C –13.8 –14.2 –13.8 –14.2 Full range –13.7 –13.7 VOM Maximum negative peak IO = 2 mA 25°C –13.5 –14 –13.5 –14 VOM– V g output voltage swing Full range –13.4 –13.4 IO = 20 mA 25°C –11.5 –12.4 –11.5 –12.4 Full range –11.5 –11.5 RL = 600 Ω 25°C 80 96 80 96 Full range 79 79 AVD Large-signal differential VO = ± 10 V RL = 2 kΩ 25°C 90 109 90 109 dB g g voltage amplification Full range 89 89 RL = 10 kΩ 25°C 95 118 95 118 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, See Figure 5 Common mode 25°C 7.5 7.5 i pF Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 80 98 80 98 dB rejection ratio IC ICR , VO = 0, RS = 50 Ω Full range 79 79 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC± /ΔVIO) CC± VO = 0, RS = 50 Ω Full range 80 81 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2081C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2081C TLE2081AC TA† UNIT MIN TYP MAX MIN TYP MAX ICC Supply current VO = 0 No load 25°C 1.35 1.7 2.2 1.35 1.7 2.2 0, mA Full range 2.2 2.2 I Short-circuit output V 0 VID = 1 V 25°C –30 –45 –30 –45 IOS current VO = mA VID = –1 V 30 48 30 48 † Full range is 0°C to 70°C. TLE2081C operating characteristics at specified free-air temperature, VCC± = ±15 V PARAMETER TEST CONDITIONS T † TLE2081C TLE2081AC TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 30 40 30 40 SR+ Positive slew rate VO(PP) = 10 V, AVD = –1, RL 2 kΩ CL 100 pF Full range 27 27 V/μs = kΩ, = pF, See Figure 1 25°C 30 45 30 45 SR– Negative slew rate Full range 27 27 V/μs t Settling time AVD = –1, 10-V step, To 10 mV 25°C 0.4 0.4 ts , μs RL = 1 kΩ, CL = 100 pF To 1 mV 1.5 1.5 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak S See Figure 3 10 kHz 25°C equivalent input noise μV voltage f = 0.1 Hz to 10 Hz 0.6 0.6 I Equivalent input noise In VIC = 0 f = 10 kHz 25°C 2 8 2 8 fA/√Hz q current 0, 2.8 2.8 fA /√THD + N Total harmonic VO(PP) = 20 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 008% 0 008% distortion plus noise = kHz, = kΩ, RS = 25 Ω 0.008% 0.008% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 8 10 8 10 MHz , L , CL = 25 pF, See Figure 2 BOM Maximum output- VO(PP) = 20 V, AVD = –1, 25°C 478 637 478 637 kHz swing bandwidth O(, VD , RL = 2 kΩ, CL = 25 pF φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 57° 57° g y gain I L CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLE2081I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2081I TLE2081AI TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.34 6 0.3 3 mV VIC = 0, VO = 0, Full range 7.6 5.6 αVIO Temperature coefficient of input offset voltage RS = 50 Ω, Full range 3.2 29 3.2 29 μV/°C IIO Input offset current 25°C 5 100 5 100 pA VIC = 0, VO = 0, Full range 5 5 nA IIB Input bias current IC , O , See Figure 4 25°C 15 175 15 175 pA Full range 10 10 nA 5 5 5 5 25°C to to to to VICR Common-mode input RS = 50 Ω –1 –1.9 –1 –1.9 V voltage range 5 5 Full range to g to –0.8 –0.8 IO = 200 μA 25°C 3.8 4.1 3.8 4.1 –Full range 3.7 3.7 VOM Maximum positive peak IO = 2 mA 25°C 3.5 3.9 3.5 3.9 VOM+ V output voltage swing –Full range 3.4 3.4 IO = 20 mA 25°C 1.5 2.3 1.5 2.3 –Full range 1.5 1.5 IO = 200 μA 25°C –3.8 –4.2 –3.8 –4.2 Full range –3.7 –3.7 VOM Maximum negative peak IO = 2 mA 25°C –3.5 –4.1 –3.5 –4.1 VOM– V g output voltage swing Full range –3.4 –3.4 IO = 20 mA 25°C –1.5 –2.4 –1.5 –2.4 Full range –1.5 –1.5 RL = 600 Ω 25°C 80 91 80 91 Full range 79 79 AVD Large-signal differential VO = ± 2 3 V RL = 2 kΩ 25°C 90 100 90 100 dB g g voltage amplification 2.3 Full range 89 89 RL = 10 kΩ 25°C 95 106 95 106 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, See Figure 5 Common mode 25°C 11 11 i pF Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 70 89 70 89 dB rejection ratio IC ICR , VO = 0, RS = 50 Ω Full range 68 68 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC±/ΔVIO) CC± , VO = 0, RS = 50 Ω Full range 80 80 † Full range is –40°C to 85°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2081I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2081I TLE2081AI TA† UNIT MIN TYP MAX MIN TYP MAX ICC Supply current VO = 0 No load 25°C 1.35 1.6 2.2 1.35 1.6 2.2 0, mA Full range 2.2 2.2 IOS Short-circuit output VO = 0 VID = 1 V 25°C –35 –35 mA current VID = –1 V 45 45 † Full range is –40°C to 85°C. TLE2081I operating characteristics at specified free-air temperature, VCC± = ±5 V PARAMETER TEST CONDITIONS T † TLE2081I TLE2081AI TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 35 35 SR+ Positive slew rate VO(PP) = ±2.3 V, AVD 1 RL 2 kΩ Full range 22 22 V/μs = –1, = kΩ, CL = 100 pF, See Figure 1 25°C 38 38 SR– Negative slew rate F, Full range 22 22 V/μs t Settling time AVD = –1, 2-V step, To 10 mV 25°C 0.25 0.25 ts , μs RL = 1 kΩ, CL = 100 pF To 1 mV 0.4 0.4 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent S See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz THD + N Total harmonic distortion VO(PP) = 5 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 013% 0 013% plus noise = kHz, = kΩ, RS = 25 Ω 0.013% 0.013% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 9 4 9 4 MHz , L , CL = 25 pF, See Figure 2 9.4 9.4 BOM Maximum output-swing VO(PP) = 4 V, AVD = –1, 25°C 2 8 2 8 MHz g bandwidth O(, VD , RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ Phase margin at unity gain VI = 10 mV, RL = 2 kΩ, φm I 25°C 56° 56° , L , CL = 25 pF, See Figure 2 † Full range is –40°C to 85°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLE2081I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2081I TLE2081AI TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.49 6 0.47 3 mV VIC = 0, VO = 0, Full range 7.6 5.6 αVIO Temperature coefficient of input offset voltage RS = 50 Ω, Full range 3.2 29 3.2 29 μV/°C IIO Input offset current 25°C 6 100 6 100 pA VIC = 0, VO = 0, Full range 5 5 nA IIB Input bias current IC , O , See Figure 4 25°C 20 175 20 175 pA Full range 10 10 nA 15 15 15 15 25°C to to to to VICR Common-mode input RS = 50 Ω –11 –11.9 –11 –11.9 V voltage range 15 15 Full range to g to –10.8 –10.8 IO = 200 μA 25°C 13.8 14.1 13.8 14.1 –Full range 13.7 13.7 VOM Maximum positive peak IO = 2 mA 25°C 13.5 13.9 13.5 13.9 VOM+ V output voltage swing –Full range 13.4 13.4 IO = 20 mA 25°C 11.5 12.3 11.5 12.3 –Full range 11.5 11.5 IO = 200 μA 25°C –13.8 –14.2 –13.8 –14.2 Full range –13.7 –13.7 VOM Maximum negative peak IO = 2 mA 25°C –13.5 –14 –13.5 –14 VOM– V g output voltage swing Full range –13.4 –13.4 IO = 20 mA 25°C –11.5 –12.4 –11.5 –12.4 Full range –11.5 –11.5 RL = 600 Ω 25°C 80 96 80 96 Full range 79 79 AVD Large-signal differential VO = ± 10 V RL = 2 kΩ 25°C 90 109 90 109 dB g g voltage amplification Full range 89 89 RL = 10 kΩ 25°C 95 118 95 118 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, See Figure 5 Common mode 25°C 7.5 7.5 i pF Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, VO 0 25°C 80 98 80 98 dB rejection ratio = 0, RS = 50 Ω Full range 79 79 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC±/ΔVIO) CC± , VO = 0, RS = 50 Ω Full range 80 80 † Full range is –40°C to 85°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2081I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2081I TLE2081AI TA† UNIT MIN TYP MAX MIN TYP MAX ICC Supply current VO = 0 No load 25°C 1.35 1.7 2.2 1.35 1.7 2.2 0, mA Full range 2.2 2.2 I Short-circuit output V 0 VID = 1 V 25°C –30 –45 –30 –45 IOS current VO = mA VID = –1 V 30 48 30 48 † Full range is –40°C to 85°C. TLE2081I operating characteristics at specified free-air temperature, VCC± = ±15 V PARAMETER TEST CONDITIONS TA† TLE2081I TLE2081AI UNIT MIN TYP MAX MIN TYP MAX 25°C 30 40 30 40 SR+ Positive slew rate VO(PP) = ±10 V, AVD = –1 RL = 2 kΩ Full range 24 24 V/μs 1, kΩ, CL = 100 pF, See Figure 1 25°C 30 45 30 45 SR– Negative slew rate F, Full range 24 24 V/μs t Settling time AVD = –1, 10-V step, To 10 mV 25°C 0.4 0.4 ts R μs L = 1 kΩ, CL = 100 pF To 1 mV 1.5 1.5 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent See Figure 3 10 kHz 25°C input noise voltage μV f = 0.1 Hz to 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz THD + N Total harmonic distortion VO(PP) = 20 V, AVD = 10, plus noise f = 1 kHz, RL = 2 kΩ, 25°C 0 008% 0 008% RS = 25 Ω 0.008% 0.008% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I L 25°C 8 10 8 10 MHz CL = 25 pF, See Figure 2 BOM Maximum output-swing VO(PP) = 20 V, AVD = –1, 25°C 478 637 478 637 kHz g bandwidth O(VD RL = 2 kΩ, CL = 25 pF φm Phase margin at unity gain VI = 10 mV, RL = 2 kΩ, I L 25°C 57° 57° CL = 25 pF, See Figure 2 † Full range is –40°C to 85°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLE2081M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2081M TLE2081AM TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.34 6 0.3 3 mV VIC = 0, VO = 0, Full range 11.2 8.2 αVIO Temperature coefficient of input offset voltage RS = 50Ω Full range 3.2 29∗ 3.2 29∗ μV/°C IIO Input offset current 25°C 5 100 5 100 pA VIC = 0, VO = 0, Full range 20 20 nA IIB Input bias current IC , O , See Figure 4 25°C 15 175 15 175 pA Full range 65 65 nA 5 5 5 5 25°C to to to to VICR Common-mode input RS = 50 Ω –1 –1.9 –1 –1.9 V voltage range 5 5 Full range to g to –0.8 –0.8 IO = 200 μA 25°C 3.8 4.1 3.8 4.1 –Full range 3.6 3.6 VOM Maximum positive peak IO = 2 mA 25°C 3.5 3.9 3.5 3.9 VOM+ V output voltage swing –Full range 3.3 3.3 IO = 20 mA 25°C 1.5 2.3 1.5 2.3 –Full range 1.4 1.4 IO = 200 μA 25°C –3.8 –4.2 –3.8 –4.2 Full range –3.6 –3.6 VOM Maximum negative peak IO = 2 mA 25°C –3.5 –4.1 –3.5 –4.1 VOM– V g output voltage swing Full range –3.3 –3.3 IO = 20 mA 25°C –1.5 –2.4 –1.5 –2.4 Full range –1.4 –1.4 RL = 600 Ω 25°C 80 91 80 91 Full range 78 78 AVD Large-signal differential VO = ± 2 3 V RL = 2 kΩ 25°C 90 100 90 100 dB g g voltage amplification 2.3 Full range 88 88 RL = 10 kΩ 25°C 95 106 95 106 Full range 93 93 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, See Figure 5 Common mode 25°C 11 11 i pF Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 70 89 70 89 dB rejection ratio IC ICR , VO = 0, RS = 50 Ω Full range 68 68 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC±/ΔVIO) CC± VO = 0, RS = 50 Ω Full range 80 80 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2081M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2081M TLE2081AM TA† UNIT MIN TYP MAX MIN TYP MAX ICC Supply current VO = 0 No load 25°C 1.35 1.6 2.2 1.35 1.6 2.2 0, mA Full range 2.2 2.2 IOS Short-circuit output VO = 0 VID = 1 V 25°C –35 –35 mA current VID = –1 V 45 45 † Full range is –55°C to 125°C. TLE2081M operating characteristics at specified free-air temperature, VCC± = ±5 V PARAMETER TEST CONDITIONS T † TLE2081M TLE2081AM TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 35 35 SR+ Positive slew rate VO(PP) = ±2.3 V, AVD 1 RL 2 kΩ Full range 20∗ 20∗ V/μs = –1, = kΩ, CL = 100 pF, See Figure 1 25°C 38 38 SR– Negative slew rate F, Full range 20∗ 20∗ V/μs t Settling time AVD = –1, 2-V step, To 10 mV 25°C 0.25 0.25 ts , μs RL = 1 kΩ, CL = 100 pF To 1 mV 0.4 0.4 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak S See Figure 3 10 kHz 25°C equivalent input noise μV voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA /√Hz THD + N Total harmonic VO(PP) = 5 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 013% 0 013% distortion plus noise = kHz, = kΩ, RS = 25 Ω 0.013% 0.013% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 9 4 9 4 MHz , L , CL = 25 pF, See Figure 2 9.4 9.4 BOM Maximum output-swing VO(PP) = 4 V, AVD = –1, 25°C 2 8 2 8 MHz g bandwidth O(, VD , RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 56° 56° g y gain I L CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLE2081M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2081M TLE2081AM TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.49 6 0.47 3 mV VIC = 0, VO = 0, Full range 11.2 8.2 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 3.2 29∗ 3.2 29∗ μV/°C IIO Input offset current 25°C 6 100 6 100 pA VIC = 0, VO = 0, Full range 20 20 nA IIB Input bias current IC , O , See Figure 4 25°C 20 175 20 175 pA Full range 65 65 nA 15 15 15 15 25°C to to to to VICR Common-mode input RS = 50 Ω –11 –11.9 –11 –11.9 V voltage range 15 15 Full range to g to –10.8 –10.8 IO = 200 μA 25°C 13.8 14.1 13.8 14.1 –Full range 13.6 13.6 VOM Maximum positive peak IO = 2 mA 25°C 13.5 13.9 13.5 13.9 VOM+ V output voltage swing –Full range 13.3 13.3 IO = 20 mA 25°C 11.5 12.3 11.5 12.3 –Full range 11.4 11.4 IO = 200 μA 25°C –13.8 –14.2 –13.8 –14.2 Full range –13.6 –13.6 VOM Maximum negative peak IO = 2 mA 25°C –13.5 –14 –13.5 –14 VOM– V g output voltage swing Full range –13.3 –13.3 IO = 20 mA 25°C –11.5 –12.4 –11.5 –12.4 Full range –11.4 –11.4 RL = 600 Ω 25°C 80 96 80 96 Full range 78 78 AVD Large-signal differential VO = ± 10 V RL = 2 kΩ 25°C 90 109 90 109 dB g g voltage amplification Full range 88 88 RL = 10 kΩ 25°C 95 118 95 118 Full range 93 93 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, See Figure 5 Common mode 25°C 7.5 7.5 i pF Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 80 98 80 98 dB rejection ratio IC ICR , VO = 0, RS = 50 Ω Full range 78 78 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC± /ΔVIO) CC± VO = 0, RS = 50 Ω Full range 80 80 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2081M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted)(continued) PARAMETER TEST CONDITIONS T † TLE2081M TLE2081AM TA† UNIT MIN TYP MAX MIN TYP MAX ICC Supply current VO = 0 No load 25°C 1.35 1.7 2.2 1.35 1.7 2.2 0, mA Full range 2.2 2.2 I Short-circuit output V 0 VID = 1 V 25°C –30 –45 –30 –45 IOS current VO = mA VID = –1 V 30 48 30 48 † Full range is –55°C to 125°C. TLE2081M operating characteristics at specified free-air temperature, VCC± = ±15 V PARAMETER TEST CONDITIONS T † TLE2081M TLE2081AM TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 30 40 30 40 SR+ Positive slew rate VO(PP) = 10 V, AVD 1 RL 2 kΩ Full range 22 22 V/μs = –1, = kΩ, CL = 100 pF, See Figure 1 25°C 30 45 30 45 SR– Negative slew rate F, Full range 22 22 V/μs t Settling time AVD = –1, 10-V step, To 10 mV 25°C 0.4 0.4 ts , μs RL = 1 kΩ, CL = 100 pF To 1 mV 1.5 1.5 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak S See Figure 3 10 kHz 25°C equivalent input noise μV voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz THD + N Total harmonic distortion VO(PP) = 20 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 008% 0 008% plus noise = kHz, = kΩ, RS = 25 Ω 0.008% 0.008% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 8∗ 10 8∗ 10 MHz , L , CL = 25 pF, See Figure 2 BOM Maximum output-swing VO(PP) = 20 V, AVD = –1, 25°C 478∗ 637 478∗ 637 kHz g bandwidth O(, VD , RL = 2 kΩ, CL = 25 pF φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 57° 57° g y gain I L CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TLE2081Y electrical characteristics at VCC± = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS TLE2081Y UNIT MIN TYP MAX VIO Input offset voltage VIC = 0, VO = 0, RS = 50 Ω 0.49 6 mV IIO Input offset current VIC = 0 VO = 0 See Figure 4 6 100 pA IIB Input bias current 0, 0, 20 175 15 15 VICR Common-mode input voltage range RS = 50 Ω to ICR g g S to V –11 11.9 M i iti k IO = –200 μA 13.8 14.1 VOM+ Maximum positive peak output voltage swing IO = –2 mA 13.5 13.9 V out ut IO = –20 mA 11.5 12.3 M i ti k t t IO = 200 μA –13.8 –14.2 VOM– Maximum negative peak output IO = 2 mA –13.5 –14 V voltage swing IO = 20 mA –11.5 –12.4 L i l diff ti l lt RL = 600 Ω 80 96 AVD Large-signal differential voltage amplification VO = ± 10 V RL = 2 kΩ 90 109 dB am lification RL = 10 kΩ 95 118 ri Input resistance VIC = 0 1012 Ω ci Input capacitance VIC = 0 See Figure 5 Common mode 7.5 0, pF Differential 2.5 zo Open-loop output impedance f = 1 MHz 80 Ω CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω 80 98 dB kSVR Supply-voltage rejection ratio (ΔVCC± /ΔVIO) VCC±= ±5 V to ±15 V, VO = 0, RS = 50 Ω 82 99 dB ICC Supply current VO = 0, No load 1.35 1.7 2.2 mA I Short circuit output current V 0 VID = 1 V –30 –45 IOS Short-VO = mA VID = –1 V 30 48 TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2082C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2082C TLE2082AC TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.9 6 0.65 4 mV VIC = 0, VO = 0, Full range 8.1 5.1 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 2.3 25 2.3 25 μV/°C IIO Input offset current 25°C 5 100 5 100 pA VIC = 0, VO = 0, Full range 1.4 1.4 nA IIB Input bias current IC , O , See Figure 4 25°C 15 175 15 175 pA Full range 5 5 nA 5 5 5 5 25°C to to to to VICR Common-mode input RS = 50 Ω –1 –1.9 –1 –1.9 V voltage range 5 5 Full range to to –0.9 –0.9 IO = 200 μA 25°C 3.8 4.1 3.8 4.1 –Full range 3.7 3.7 VOM Maximum positive peak IO = 2 mA 25°C 3.5 3.9 3.5 3.9 VOM+ V output voltage swing –Full range 3.4 3.4 IO = 20 mA 25°C 1.5 2.3 1.5 2.3 –Full range 1.5 1.5 IO = 200 μA 25°C –3.8 –4.2 –3.8 –4.2 Full range –3.7 –3.7 VOM Maximum negative peak IO = 2 mA 25°C –3.5 –4.1 –3.5 –4.1 VOM– V g output voltage swing Full range –3.4 –3.4 IO = 20 mA 25°C –1.5 –2.4 –1.5 –2.4 Full range –1.5 –1.5 RL = 600 Ω 25°C 80 91 80 91 Full range 79 79 AVD Large-signal differential VO = ± 2 3 V RL = 2 kΩ 25°C 90 100 90 100 dB g g voltage amplification 2.3 Full range 89 89 RL = 10 kΩ 25°C 95 106 95 106 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input Common mode VIC = 0 See Figure 5 25°C 11 11 pF In ut capacitance Differential 0, 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common mode rejection ratio VIC = VICRmin, 25°C 70 89 70 89 Common-IC ICR dB , VO = 0, RS = 50 Ω Full range 68 68 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio(ΔVCC± /ΔVIO) CC± , VO = 0, RS = 50 Ω Full range 80 80 ICC Supply current VO = 0 No load 25°C 2.7 2.9 3.9 2.7 2.9 3.9 mA y (both channels) 0, Full range 3.9 3.9 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TLE2082C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T TLE2082C TLE2082AC TA UNIT MIN TYP MAX MIN TYP MAX Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB IOS Short circuit output current VO = 0 VID = 1 V 25°C –35 –35 Short-mA VID = –1 V 45 45 TLE2082C operating characteristics at specified free-air temperature, VCC± = ±5 V PARAMETER TEST CONDITIONS T † TLE2082C TLE2082AC TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 35 35 SR+ Positive slew rate VO(PP) = ±2.3 V, AVD = 1 RL = 2 kΩ Full range 22 22 V/μs –1, kΩ, = 100 pF, See Figure 1 25°C 38 38 SR– Negative slew rate CL F, Full range 22 22 V/μs t Settling time AVD = –1, 2-V step, To 10 mV 25°C 0.25 0.25 ts μs , RL = 1 kΩ, CL = 100 pF To 1 mV 0.4 0.4 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1Hz to 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz THD + N Total harmonic distortion VO(PP) = 5 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 013% 0 013% plus noise = kHz, = kΩ, RS = 25 Ω 0.013% 0.013% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 9 4 9 4 MHz , L , CL = 25 pF, See Figure 2 9.4 9.4 BOM Maximum output-swing VO(PP) = 4 V, AVD = –1, 25°C 2 8 2 8 MHz g bandwidth O(VD RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 56° 56° g y gain I L CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2082C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2082C TLE2082AC TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 1.1 7 0.7 4 mV VIC = 0, VO = 0, Full range 8.1 5.1 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 2.4 25 2.4 25 μV/°C IIO Input offset current 25°C 6 100 6 100 pA VIC = 0, VO = 0, Full range 1.4 1.4 nA IIB Input bias current IC , O , See Figure 4 25°C 20 175 20 175 pA Full range 5 5 nA 15 15 15 15 25°C to to to to VICR Common-mode input RS = 50 Ω –11 –11.9 –11 –11.9 V voltage range 15 15 Full range to to –10.9 –10.9 IO = 200 μA 25°C 13.8 14.1 13.8 14.1 –Full range 13.6 13.6 VOM Maximum positive peak IO = 2 mA 25°C 13.5 13.9 13.5 13.9 VOM+ V output voltage swing –Full range 13.4 13.4 IO = 20 mA 25°C 11.5 12.3 11.5 12.3 –Full range 11.5 11.5 IO = 200 μA 25°C –13.8 –14.2 –13.8 –14.2 Full range –13.7 –13.7 VOM Maximum negative peak IO = 2 mA 25°C –13.5 –14 –13.5 –14 VOM– V g output voltage swing Full range –13.4 –13.4 IO = 20 mA 25°C –11.5 –12.4 –11.5 –12.4 Full range –11.5 –11.5 RL = 600 Ω 25°C 80 96 80 96 Full range 79 79 AVD Large-signal differential VO = ± 10 V RL = 2 kΩ 25°C 90 109 90 109 dB g g voltage amplification Full range 89 89 RL = 10 kΩ 25°C 95 118 95 118 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance Common mode VIC = 0, See Figure 5 25°C 7.5 7.5 i ca acitance pF Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 80 98 80 98 dB rejection ratio IC ICR , VO = 0, RS = 50 Ω Full range 79 79 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC±/ΔVIO) CC± , VO = 0, RS = 50 Ω Full range 81 81 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TLE2082C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T TLE2082C TLE2082AC TA UNIT MIN TYP MAX MIN TYP MAX Supply current 25°C 2.7 3.1 3.9 2.7 3.1 3.9 ICC (both channels) VO = 0, No load Full range 3.9 3.9 mA Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB IOS Short circuit output current VO = 0 VID = 1 V 25°C –30 –45 –30 –45 Short-mA VID = –1 V 30 48 30 48 TLE2082C operating characteristics at specified free-air temperature, VCC± = ±15 V PARAMETER TEST CONDITIONS T † TLE2082C TLE2082AC TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 28 40 28 40 SR+ Positive slew rate VO(PP) = 10 V, AVD = –1, RL = 2 kΩ CL = 100 pF Full range 25 25 V/μs kΩ, pF, Figure 1 25°C 30 45 30 45 SR– Negative slew rate See Full range 25 25 V/μs t Settling time AVD = –1, 10-V step, To 10 mV 25°C 0.4 0.4 ts μs , RL = 1 kΩ, CL = 100 pF To 1 mV 1.5 1.5 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 V Peak-to-peak equivalent S , See Figure 3 10 kHz 25°C VN(PP) V Peak to eak input noise voltage f = 0.1 Hz to 0 6 0 6 μV 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz Total harmonic distortion VO(PP) = 20 V, AVD = 10, THD + N kHz kΩ 0 008% 0 008% plus noise f = 1 kHz, RL = 2 kΩ, RS = 25 Ω 25°C 0.008% 0.008% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 8 10 8 10 MHz , L , CL = 25 pF, See Figure 2 BOM Maximum output-swing VO(PP) = 20 V, AVD = –1, 25°C 478 637 478 637 kHz g bandwidth O(VD RL = 2 kΩ, CL = 25 pF φ Phase margin at VI = 10 mV, RL = 2 kΩ, φm 25°C 57° 57° g unity gain I , L , CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2082I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2082I TLE2082AI TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.9 7 0.65 4 mV VIC = 0, VO = 0, Full range 8.5 5.5 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 2.4 25 2.4 25 μV/°C IIO Input offset current 25°C 5 100 5 100 pA VIC = 0, VO = 0, Full range 5 5 nA IIB Input bias current IC , O , See Figure 4 25°C 15 175 15 175 pA Full range 10 10 nA 5 5 5 5 25°C to to to to VICR Common-mode input RS = 50 Ω –1 –1.9 –1 –1.9 V voltage range 5 5 Full range to to –0.8 –0.8 IO = 200 μA 25°C 3.8 4.1 3.8 4.1 –Full range 3.7 3.7 VOM Maximum positive peak IO = 2 mA 25°C 3.5 3.9 3.5 3.9 VOM+ V output voltage swing –Full range 3.4 3.4 IO = 20 mA 25°C 1.5 2.3 1.5 2.3 –Full range 1.5 1.5 IO = 200 μA 25°C –3.8 –4.2 –3.8 –4.2 Full range –3.7 –3.7 VOM Maximum negative peak IO = 2 mA 25°C –3.5 –4.1 –3.5 –4.1 VOM– V g output voltage swing Full range –3.4 –3.4 IO = 20 mA 25°C –1.5 –2.4 –1.5 –2.4 Full range –1.5 –1.5 RL = 600 Ω 25°C 80 91 80 91 Full range 79 79 AVD Large-signal differential VO = ± 2 3 V RL = 2 kΩ 25°C 90 100 90 100 dB g g voltage amplification 2.3 Full range 89 89 RL = 10 kΩ 25°C 95 106 95 106 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input Common mode VIC = 0, 25°C 11 11 pF In ut capacitance Differential IC , See Figure 5 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common mode rejection ratio VIC = VICRmin, 25°C 70 89 70 89 Common-IC ICR dB , VO = 0, RS = 50 Ω Full range 68 68 kSVR Supply-voltage rejection ratio VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j (ΔVCC±/ΔVIO) CC± , VO = 0, RS = 50 Ω Full range 80 80 ICC Supply current VO = 0 No load 25°C 2.7 2.9 3.9 2.7 2.9 3.9 mA y (both channels) 0, Full range 3.9 3.9 † Full range is –40°C to 85°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TLE2082I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T TLE2082I TLE2082AI TA UNIT MIN TYP MAX MIN TYP MAX Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB IOS Short circuit output current VO = 0 VID = 1 V 25°C –35 –35 Short-mA VID = –1 V 45 45 TLE2082I operating characteristics at specified free-air temperature, VCC± = ±5 V PARAMETER TEST CONDITIONS T † TLE2082I TLE2082AI TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 35 35 SR+ Positive slew rate VO(PP) = ±2.3 V, AVD = 1 RL = 2 kΩ Full range 20 20 V/μs –1, kΩ, = 100 pF, See Figure 1 25°C 38 38 SR– Negative slew rate CL F, Full range 20 20 V/μs t Settling time AVD = –1, 2-V step, To 10 mV 25°C 0.25 0.25 ts μs , RL = 1 kΩ, CL = 100 pF To 1 mV 0.4 0.4 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent S See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz THD + N Total harmonic distortion VO(PP) = 5 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 013% 0 013% plus noise = kHz, = kΩ, RS = 25 Ω 0.013% 0.013% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 9 4 9 4 MHz , L , CL = 25 pF, See Figure 2 9.4 9.4 BOM Maximum output-swing VO(PP) = 4 V, AVD = –1, 25°C 2 8 2 8 MHz g bandwidth O(VD RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 56° 56° g y gain I L CL = 25 pF, See Figure 2 † Full range is 40°C to 85°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2082I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2082I TLE2082AI TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 1.1 7 0.7 4 mV VIC = 0, VO = 0, Full range 8.5 5.5 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 2.4 25 2.4 25 μV/°C IIO Input offset current 25°C 6 100 6 100 pA VIC = 0, VO = 0, Full range 5 5 nA IIB Input bias current IC , O , See Figure 4 25°C 20 175 20 175 pA Full range 10 10 nA 15 15 15 15 25°C to to to to VICR Common-mode input RS = 50 Ω –11 –11.9 –11 –11.9 V voltage range 15 15 Full range to to –10.8 –10.8 IO = 200 μA 25°C 13.8 14.1 13.8 14.1 –Full range 13.7 13.7 VOM Maximum positive peak IO = 2 mA 25°C 13.5 13.9 13.5 13.9 VOM+ V output voltage swing –Full range 13.4 13.4 IO = 20 mA 25°C 11.5 12.3 11.5 12.3 –Full range 11.5 11.5 IO = 200 μA 25°C –13.8 –14.2 –13.8 –14.2 Full range –13.7 –13.7 VOM Maximum negative peak IO = 2 mA 25°C –13.5 –14 –13.5 –14 VOM– V g output voltage swing Full range –13.4 –13.4 IO = 20 mA 25°C –11.5 –12.4 –11.5 –12.4 Full range –11.5 –11.5 RL = 600 Ω 25°C 80 96 80 96 Full range 79 79 AVD Large-signal differential VO = ± 10 V RL = 2 kΩ 25°C 90 109 90 109 dB g g voltage amplification Full range 89 89 RL = 10 kΩ 25°C 95 118 95 118 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance Common mode VIC = 0, See Figure 5 25°C 7.5 7.5 i ca acitance pF Differential IC , g 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 80 98 80 98 dB rejection ratio IC ICR , VO = 0, RS = 50 Ω Full range 79 79 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC± /ΔVIO) CC± , VO = 0, RS = 50 Ω Full range 80 80 † Full range is –40°C to 85°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TLE2082I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T TLE2082I TLE2082AI TA UNIT MIN TYP MAX MIN TYP MAX Supply current 25°C 2.7 3.1 3.9 2.7 3.1 3.9 ICC (both channels) VO = 0, No load Full range 3.9 3.9 mA Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB IOS Short circuit output current VO = 0 VID = 1 V 25°C –30 –45 –30 –45 Short-mA VID = –1 V 30 48 30 48 TLE2082I operating characteristics at specified free-air temperature, VCC± = ±15 V PARAMETER TEST CONDITIONS T † TLE2082I TLE2082AI TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 28 40 28 40 SR+ Positive slew rate VO(PP) = 10 V, AVD = –1, RL = 2 kΩ CL = 100 pF Full range 22 22 V/μs kΩ, pF, Figure 1 25°C 30 45 30 45 SR– Negative slew rate See Full range 22 22 V/μs t Settling time AVD = –1, 10-V step, To 10 mV 25°C 0.4 0.4 ts μs , RL = 1 kΩ, CL = 100 pF To 1 mV 1.5 1.5 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent S See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz THD + N Total harmonic distortion VO(PP) = 20 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 008% 0 008% plus noise = kHz, = kΩ, RS = 25 Ω 0.008% 0.008% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 8 10 8 10 MHz , L , CL = 25 pF, See Figure 2 BOM Maximum output-swing VO(PP) = 20 V, AVD = –1, 25°C 478 637 478 637 kHz g bandwidth O(VD RL = 2 kΩ, CL = 25 pF φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 57° 57° g y gain I L CL = 25 pF, See Figure 2 † Full range is –40°C to 85°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2082M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2082M TLE2082AM TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 0.9 7 0.65 4 mV VIC = 0, VO = 0, Full range 9.5 6.5 αVIO Temperature coefficient of input offset voltage RS= 50Ω Full range 2.3 25∗ 2.3 25∗ μV/°C IIO Input offset current 25°C 5 100 5 100 pA VIC = 0, VO = 0, Full range 20 20 nA IIB Input bias current IC , O , See Figure 4 25°C 15 175 15 175 pA Full range 60 60 nA 5 5 5 5 25°C to to to to VICR Common-mode input RS = 50 Ω –1 –1.9 –1 –1.9 V voltage range 5 5 Full range to to –0.8 –0.8 IO = 200 μA 25°C 3.8 4.1 3.8 4.1 –Full range 3.6 3.6 VOM Maximum positive peak IO = 2 mA 25°C 3.5 3.9 3.5 3.9 VOM+ V output voltage swing –Full range 3.3 3.3 IO = 20 mA 25°C 1.5 2.3 1.5 2.3 –Full range 1.4 1.4 IO = 200 μA 25°C –3.8 –4.2 –3.8 –4.2 Full range –3.6 –3.6 VOM Maximum negative peak IO = 2 mA 25°C –3.5 –4.1 –3.5 –4.1 VOM– V g output voltage swing Full range –3.3 –3.3 IO = 20 mA 25°C –1.5 –2.4 –1.5 –2.4 Full range –1.4 –1.4 RL = 600 Ω 25°C 80 91 80 91 Full range 78 78 AVD Large-signal differential VO = ± 2 3 V RL = 2 kΩ 25°C 90 100 90 100 dB g g voltage amplification 2.3 Full range 88 88 RL = 10 kΩ 25°C 95 106 95 106 Full range 93 93 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capaci Common mode VIC = 0 See Figure 5 25°C 11 11 capaci- pF tance Differential 0, 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common mode rejection ratio VIC = VICRmin, 25°C 70 89 70 89 Common-IC ICR dB , VO = 0, RS = 50 Ω Full range 68 68 kSVR Supply-voltage rejection ratio VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j (ΔVCC± /ΔVIO) CC± , VO = 0, RS = 50 Ω Full range 80 80 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TLE2082M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2082M TLE2082AM TA† UNIT MIN TYP MAX MIN TYP MAX Supply current 25°C 2.7 2.9 3.6 2.7 2.9 3.6 ICC (both channels) VO = 0, No load Full range 3.6 3.6 mA Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB IOS Short circuit output current VO = 0 VID = 1 V 25°C –35 –35 Short-mA VID = –1 V 45 45 † Full range is –55°C to 125°C. TLE2082M operating characteristics at specified free-air temperature, VCC± = ±5 V PARAMETER TEST CONDITIONS T † TLE2082M TLE2082AM TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 35 35 SR+ Positive slew rate VO(PP) = ±2.3 V, 1 kΩ Full range 18∗ 18∗ V/μs AVD = –1, RL = 2 kΩ, CL = 100 pF, See Figure 1 25°C 38 38 SR– Negative slew rate F, Full range 18∗ 18∗ V/μs t Settling time AVD = –1, 2-V step, To 10 mV 25°C 0.25 0.25 ts μs , RL = 1 kΩ, CL = 100 pF To 1 mV 0.4 0.4 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent S See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz THD + N Total harmonic VO(PP) = 5 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 013% 0 013% distortion plus noise = kHz, = kΩ, RS = 25 Ω 0.013% 0.013% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 9 4 9 4 MHz , L , CL = 25 pF, See Figure 2 9.4 9.4 BOM Maximum output-swing VO(PP) = 4 V, AVD = –1, 25°C 2 8 2 8 MHz g bandwidth O(VD RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 56° 56° g y gain I L CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2082M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2082M TLE2082AM TA† UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C 1.1 7 0.7 4 mV VIC = 0, VO = 0, Full range 9.5 6.5 αVIO Temperature coefficient of input offset voltage RS= 50 Ω Full range 2.4 25∗ 2.4 25∗ μV/°C IIO Input offset current 25°C 6 100 6 100 pA VIC = 0, VO = 0, Full range 20 20 nA IIB Input bias current IC , O , See Figure 4 25°C 20 175 20 175 pA Full range 65 65 nA 15 15 15 15 25°C to to to to VICR Common-mode input RS = 50 Ω –11 –11.9 –11 –11.9 V voltage range 15 15 Full range to to –10.8 –10.8 IO = 200 μA 25°C 13.8 14.1 13.8 14.1 –Full range 13.6 13.6 VOM Maximum positive peak IO = 2 mA 25°C 13.5 13.9 13.5 13.9 VOM+ V output voltage swing –Full range 13.3 13.3 IO = 20 mA 25°C 11.5 12.3 11.5 12.3 –Full range 11.4 11.4 IO = 200 μA 25°C –13.8 –14.2 –13.8 –14.2 Full range –13.6 –13.6 VOM Maximum negative peak IO = 2 mA 25°C –13.5 –14 –13.5 –14 VOM– V g output voltage swing Full range –13.3 –13.3 IO = 20 mA 25°C –11.5 –12.4 –11.5 –12.4 Full range –11.4 –11.4 RL = 600 Ω 25°C 80 96 80 96 Full range 78 78 AVD Large-signal differential VO = ± 10 V RL = 2 kΩ 25°C 90 109 90 109 dB g g voltage amplification Full range 88 88 RL = 10 kΩ 25°C 95 118 95 118 Full range 93 93 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance Common mode VIC = 0, See Figure 5 25°C 7.5 7.5 i ca acitance pF Differential IC , g 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode rejection VIC = VICRmin, 25°C 80 98 80 98 dB j ratio IC ICR , VO = 0, RS = 50 Ω Full range 78 78 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC±/ΔVIO) CC± , VO = 0, RS = 50 Ω Full range 80 80 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 TLE2082M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2082M TLE2082AM TA† UNIT MIN TYP MAX MIN TYP MAX Supply current 25°C 2.7 3.1 3.6 2.7 3.1 3.6 ICC (both channels) VO = 0, No load Full range 3.6 3.6 mA Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB I Short-circuit output V 0 VID = 1 V 25°C –30 –45 –30 –45 IOS current VO = mA VID = –1 V 30 48 30 48 † Full range is –55°C to 125°C. TLE2082M operating characteristics at specified free-air temperature, VCC± = ±15 V PARAMETER TEST CONDITIONS T † TLE2082M TLE2082AM TA† UNIT MIN TYP MAX MIN TYP MAX 25°C 28 40 28 40 SR+ Positive slew rate VO(PP) = 10 V, AVD = –1, kΩ pF Full range 20 20 V/μs RL = 2 kΩ, CL = 100 pF, See Figure 1 25°C 30 45 30 45 SR– Negative slew rate Full range 20 20 V/μs t Settling time AVD = –1, 10-V step, To 10 mV 25°C 0.4 0.4 ts μs , RL = 1 kΩ, CL = 100 pF To 1 mV 1.5 1.5 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent S See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA/√Hz Total harmonic distortion VO(PP) = 20 V, AVD = 10, THD + N kHz kΩ 0 008% 0 008% plus noise f = 1 kHz, RL = 2 kΩ, RS = 25 Ω 25°C 0.008% 0.008% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 8∗ 10 8∗ 10 MHz , L , CL = 25 pF, See Figure 2 BOM Maximum output-swing VO(PP) = 20 V, AVD = –1, 25°C 478∗ 637 478∗ 637 kHz g bandwidth O(VD RL = 2 kΩ, CL = 25 pF φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 57° 57° g y gain I L CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2082Y electrical characteristics at VCC± = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS TLE2082Y UNIT MIN TYP MAX VIO Input offset voltage VIC = 0, VO = 0, RS = 50 Ω 1.1 6 mV IIO Input offset current VIC = 0 VO = 0 See Figure 4 6 100 pA IIB Input bias current 0, 0, 20 175 pA 15 15 VICR Common-mode input voltage range RS = 50 Ω to to V –11 11.9 IO = –200 μA 13.8 14.1 VOM+ Maximum positive peak output voltage swing IO = –2 mA 13.5 13.9 V IO = –20 mA 11.5 12.3 IO = 200 μA –13.8 –14.2 VOM– Maximum negative peak output voltage swing IO = 2 mA –13.5 –14 V IO = 20 mA –11.5 –12.4 RL = 600 Ω 80 96 AVD Large-signal differential voltage amplification VO = ± 10 V RL = 2 kΩ 90 109 dB RL = 10 kΩ 95 118 ri Input resistance VIC = 0 1012 Ω ci Input capacitance Common mode VO = 0 See Figure 5 7.5 pF Differential 0, 2.5 zo Open-loop output impedance f = 1 MHz 80 Ω CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω 80 98 dB kSVR Supply-voltage rejection ratio (ΔVCC± /ΔVIO) VCC± = ±5 V to ±15 V, VO = 0, RS = 50 Ω 82 99 dB ICC Supply current (both channels) VO = 0, No load 2.7 3.1 3.9 mA IOS Short circuit output current VO = 0 VID = 1 V –30 –45 Short-mA VID = –1 V 30 48 TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 TLE2084C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2084C TLE2084AC TA UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C –1.6 7 –0.5 4 mV VIC = 0, VO = 0, Full range 9.1 6.1 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 10.1 30 10.1 30 μV/°C IIO Input offset current 25°C 15 100 15 100 pA VIC = 0, VO = 0, Full range 1.4 1.4 nA IIB Input bias current IC O See Figure 4 25°C 20 175 20 175 pA Full range 5 5 nA 25°C 5 to 5 to 5 to 5 to VICR Common-mode input RS = 50 Ω –1 –1.9 –1 –1.9 voltage range V Full range 5 to 5 to –0.9 –0.9 IO = 200 μA 25°C 3.8 4.1 3.8 4.1 –Full range 3.7 3.7 VOM Maximum positive peak IO = 2 mA 25°C 3.5 3.9 3.5 3.9 VOM+ output voltage swing –V Full range 3.4 3.4 IO = 20 mA 25°C 1.5 2.3 1.5 2.3 –Full range 1.5 1.5 IO = 200 μA 25°C –3.8 –4.2 –3.8 –4.2 Full range –3.7 –3.7 VOM Maximum negative peak IO = 2 mA 25°C –3.5 –4.1 –3.5 –4.1 VOM– V g output voltage swing Full range –3.4 –3.4 IO = 20 mA 25°C –1.5 –2.4 –1.5 –2.4 Full range –1.5 –1.5 RL = 600 Ω 25°C 80 91 80 91 Full range 79 79 AVD Large-signal differential VO = ± 2 3 V RL = 2 kΩ 25°C 90 100 90 100 dB g g voltage amplification 2.3 Full range 89 89 RL = 10 kΩ 25°C 95 106 95 106 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, Common mode 25°C 11 11 IC pF See Figure 5 Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 70 89 70 89 rejection ratio dB IC ICR VO = 0, RS = 50 Ω Full range 68 68 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC± /ΔVIO) CC± VO = 0, RS = 50 Ω Full range 80 80 ICC Supply current VO = 0 No load 25°C 5.2 6.3 7.5 5.2 6.3 7.5 mA y ( four amplifiers ) 0, Full range 7.5 7.5 ax Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2084C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2084C TLE2084AC TA UNIT MIN TYP MAX MIN TYP MAX I Short-circuit output V 0 VID = 1 V 25°C –35 –35 IOS current VO = mA VID = –1 V 45 45 † Full range is 0°C to 70°C. TLE2084C operating characteristics at specified free-air temperature, VCC± = ±5 V PARAMETER TEST CONDITIONS T † TLE2084C TLE2084AC TA UNIT MIN TYP MAX MIN TYP MAX 25°C 35 35 SR+ Positive slew rate VO(PP) = ±2.3 V, 1 kΩ Full range 22 22 V/μs AVD = –1, RL = 2 kΩ, CL = 100 pF, See Figure 1 25°C 38 38 SR– Negative slew rate F, Full range 22 22 V/μs t Settling time AVD = –1, 2-V step, To 10 mV 25°C 0.25 0.25 ts R μs L = 1 kΩ, CL = 100 pF To 1 mV 0.4 0.4 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent See Figure 3 10 kHz 25°C input noise voltage μV f = 0.1Hz to 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA /√Hz THD + N Total harmonic distortion VO(PP) = 5 V, AVD = 10, f = 1 kHz RL = 2 kΩ 25°C 0 013% 0 013% plus noise kHz, kΩ, RS = 25 Ω 0.013% 0.013% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I L 25°C 9 4 9 4 MHz CL = 25 pF, See Figure 2 9.4 9.4 BOM Maximum output-swing VO(PP) = 4 V, AVD = –1, 25°C 2 8 2 8 MHz g bandwidth O(VD RL = 2 kΩ , CL = 25 pF 2.8 2.8 φm Phase margin at unity VI = 10 mV, RL = 2 kΩ, 25°C 56° 56° g y gain I L CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 TLE2084C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2084C TLE2084AC TA UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C –1.6 7 –0.5 4 mV VIC = 0, VO = 0, Full range 9.1 6.1 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 10.1 30 10.1 30 μV/°C IIO Input offset current 25°C 15 100 15 100 pA VIC = 0, VO = 0, Full range 1.4 1.4 nA IIB Input bias current IC O See Figure 4 25°C 25 175 25 175 pA Full range 5 5 nA 15 15 15 15 25°C to to to to VICR Common-mode input RS = 50 Ω –11 –11.9 –11 –11.9 voltage range V 15 15 Full range to to –10.9 –10.9 IO = 200 μA 25°C 13.8 14.1 13.8 14.1 –Full range 13.7 13.7 VOM Maximum positive peak IO = 2 mA 25°C 13.5 13.9 13.5 13.9 VOM+ output voltage swing –V Full range 13.4 13.4 IO = 20 mA 25°C 11.5 12.3 11.5 12.3 –Full range 11.5 11.5 IO = 200 μA 25°C –13.8 –14.2 –13.8 –14.2 M i ti Full range –13.7 –13.7 VOM Maximum negative peak output voltage IO = 2 mA 25°C –13.7 –14 –13.7 –14 VOM– eak out ut V swing Full range –13.6 –13.6 IO = 20 mA 25°C –11.5 –12.4 –11.5 –12.4 Full range –11.5 –11.5 RL = 600 Ω 25°C 80 96 80 96 Full range 79 79 AVD Large-signal differential VO = ± 10 V RL = 2 kΩ 25°C 90 109 90 109 dB g g voltage amplification Full range 89 89 RL = 10 kΩ 25°C 95 118 95 118 Full range 94 94 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, Common mode 25°C 7.5 7.5 IC pF See Figure 5 Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 80 98 80 98 rejection ratio dB IC ICR VO = 0, RS = 50 Ω Full range 79 79 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC±/ΔVIO) CC± VO = 0, RS = 50 Ω Full range 81 81 ICC Supply current VO = 0 No load 25°C 5.2 6.5 7.5 5.2 6.5 7.5 mA y ( four amplifiers ) 0, Full range 7.5 7.5 ax Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2084C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T † TLE2084C TLE2084AC TA UNIT MIN TYP MAX MIN TYP MAX I Short-circuit output V 0 VID = 1 V 25°C –30 –45 –30 –45 IOS current VO = mA VID = –1 V 30 48 30 48 † Full range is 0°C to 70°C. TLE2084C operating characteristics at specified free-air temperature, VCC± = ±15 V PARAMETER TEST CONDITIONS T † TLE2084C TLE2084AC TA UNIT MIN TYP MAX MIN TYP MAX 25°C 25 40 25 40 SR+ Positive slew rate VO(PP) = 10 V, AVD = –1, kΩ pF Full range 22 22 V/μs RL = 2 kΩ, CL = 100 pF, See Figure 1 25°C 30 45 30 45 SR– Negative slew rate Full range 25 25 V/μs t Settling time AVD = –1, 10-V step, To 10 mV 25°C 0.4 0.4 ts , μs RL = 1 kΩ, CL = 100 pF To 1 mV 1.5 1.5 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 V Peak-to-peak equivalent S , See Figure 3 10 kHz 25°C VN(PP) V Peak to eak input noise voltage f = 0.1 Hz to 0 6 0 6 μV 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA /√Hz THD + N Total harmonic distortion VO(PP) = 20 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 008% 0 008% plus noise = kHz, = kΩ, RS = 25 Ω 0.008% 0.008% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 8 10 8 10 MHz , L , CL = 25 pF, See Figure 2 BOM Maximum output-swing VO(PP) = 20 V, AVD = –1, 25°C 478 637 478 637 kHz g bandwidth O(, VD , RL = 2 kΩ, CL = 25 pF φ Phase margin at VI = 10 mV, RL = 2 kΩ, φm 25°C 57° 57° g unity gain I L CL = 25 pF, See Figure 2 † Full range is 0°C to 70°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 TLE2084M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2084M TLE2084AM TA UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C –1.6 7 –0.5 4 mV VIC = 0, VO = 0, Full range 12.5 9.5 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 10.1 30∗ 10.1 30∗ μV/°C IIO Input offset current 25°C 15 100 15 100 pA VIC = 0, VO = 0, Full range 20 20 nA IIB Input bias current IC O See Figure 4 25°C 20 175 20 175 pA Full range 65 65 nA 5 5 5 5 25°C to to to to VICR Common-mode input RS = 50 Ω –1 –1.9 –1 –1.9 voltage range V 5 5 Full range to to –0.8 –0.8 IO = 200 μA 25°C 3.8 4.1 3.8 4.1 –Full range 3.6 3.6 VOM Maximum positive peak IO = 2 mA 25°C 3.5 3.9 3.5 3.9 VOM+ output voltage swing –V Full range 3.3 3.3 IO = 20 mA 25°C 1.5 2.3 1.5 2.3 –Full range 1.4 1.4 IO = 200 μA 25°C –3.8 –4.2 –3.8 –4.2 M i ti Full range –3.6 –3.6 VOM Maximum negative peak output voltage IO = 2 mA 25°C –3.5 –4.1 –3.5 –4.1 VOM– eak out ut V swing Full range –3.3 –3.3 IO = 20 mA 25°C –1.5 –2.4 –1.5 –2.4 Full range –1.4 –1.4 RL = 600 Ω 25°C 80 91 80 91 Full range 78 78 AVD Large-signal differential VO = ± 2 3 V RL = 2 kΩ 25°C 90 100 90 100 dB g g voltage amplification 2.3 Full range 88 88 RL = 10 kΩ 25°C 95 106 95 106 Full range 93 93 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, Common mode 25°C 11 11 IC pF See Figure 5 Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 70 89 70 89 rejection ratio dB IC ICR VO = 0, RS = 50 Ω Full range 68 68 kSVR Supply-voltage rejec- VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j tion ratio (ΔVCC± /ΔVIO) CC± VO = 0, RS = 50 Ω Full range 80 80 ICC Supply current VO = 0 No load 25°C 5.2 6.3 7.5 5.2 6.3 7.5 mA y ( four amplifiers ) 0, Full range 7.5 7.5 ax Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2084M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T TLE2084M TLE2084AM TA UNIT MIN TYP MAX MIN TYP MAX I Short-circuit output V 0 VID = 1 V 25°C –35 –35 IOS current VO = mA VID = –1 V 45 45 TLE2084M operating characteristics at specified free-air temperature, VCC± = ±5 V PARAMETER TEST CONDITIONS T † TLE2084M TLE2084AM TA UNIT MIN TYP MAX MIN TYP MAX 25°C 35 35 SR+ Positive slew rate VO(PP) = ±2.3 V, AVD 1 RL 2 kΩ Full range 18∗ 18∗ V/μs = –1, = kΩ, CL = 100 pF, See Figure 1 25°C 38 38 SR– Negative slew rate F, Full range 18∗ 18∗ V/μs t Settling time AVD = –1, 2-V step, To 10 mV 25°C 0.25 0.25 ts , μs RL = 1 kΩ, CL = 100 pF To 1 mV 0.4 0.4 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent S See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 In Equivalent input noise current VIC = 0, f = 10 kHz 25°C 2.8 2.8 fA /√Hz THD + N Total harmonic distortion VO(PP) = 5 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 013% 0 013% plus noise = kHz, = kΩ, RS = 25 Ω 0.013% 0.013% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 9 4 9 4 MHz , L , CL = 25 pF, See Figure 2 9.4 9.4 BOM Maximum output-swing VO(PP) = 4 V, AVD = –1, 25°C 2 8 2 8 MHz g bandwidth O(, VD , RL = 2 kΩ , CL = 25 pF 2.8 2.8 φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 56° 56° g y gain I L CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 TLE2084M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T † TLE2084M TLE2084AM TA UNIT MIN TYP MAX MIN TYP MAX VIO Input offset voltage 25°C –1.6 7 –0.5 4 mV VIC = 0, VO = 0, Full range 12.5 7.5 αVIO Temperature coefficient of input offset voltage RS = 50 Ω Full range 10.1 30∗ 10.1 30∗ μV/°C IIO Input offset current 25°C 15 100 15 100 pA VIC = 0, VO = 0, Full range 20 20 nA IIB Input bias current IC O See Figure 4 25°C 25 175 25 175 pA Full range 65 65 nA 15 15 15 15 25°C to to to to VICR Common-mode input RS = 50 Ω –11 –11.9 –11 –11.9 voltage range V 15 15 Full range to to –10.8 –10.8 IO = 200 μA 25°C 13.8 14.1 13.8 14.1 –Full range 13.6 13.6 VOM Maximum positive peak IO = 2 mA 25°C 13.5 13.9 13.5 13.9 VOM+ output voltage swing –V Full range 13.3 13.3 IO = 20 mA 25°C 11.5 12.3 11.5 12.3 –Full range 11.4 11.4 IO = 200 μA 25°C –13.8 –14.2 –13.8 –14.2 Full range –13.6 –13.6 VOM Maximum negative peak IO = 2 mA 25°C –13.5 –14 –13.5 –14 VOM– V g output voltage swing Full range –13.3 –13.3 IO = 20 mA 25°C –11.5 –12.4 –11.5 –12.4 Full range –11.4 –11.4 RL = 600 Ω 25°C 80 96 80 96 Full range 78 78 AVD Large-signal differential VO = ± 10 V RL = 2 kΩ 25°C 90 109 90 109 dB g g voltage amplification Full range 88 88 RL = 10 kΩ 25°C 95 118 95 118 Full range 93 93 ri Input resistance VIC = 0 25°C 1012 1012 Ω ci Input capacitance VIC = 0, Common mode 25°C 7.5 7.5 IC pF See Figure 5 Differential 25°C 2.5 2.5 zo Open-loop output impedance f = 1 MHz 25°C 80 80 Ω CMRR Common-mode VIC = VICRmin, 25°C 80 98 80 98 rejection ratio dB IC ICR VO = 0, RS = 50 Ω Full range 78 78 kSVR Supply-voltage rejection VCC± = ±5 V to ±15 V, 25°C 82 99 82 99 dB y g j ratio (ΔVCC±/ΔVIO) CC± VO = 0, RS = 50 Ω Full range 80 80 ICC Supply current VO = 0 No load 25°C 5.2 6.5 7.5 5.2 6.5 7.5 mA y ( four amplifiers ) 0, Full range 7.5 7.5 ax Crosstalk attenuation VIC = 0, RL = 2 kΩ 25°C 120 120 dB ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2084M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS T TLE2084M TLE2084AM TA UNIT MIN TYP MAX MIN TYP MAX I Short-circuit output V 0 VID = 1 V 25°C –30 –45 –30 –45 IOS current VO = mA VID = –1 V 30 48 30 48 TLE2084M operating characteristics at specified free-air temperature, VCC± = ±15 V PARAMETER TEST CONDITIONS T † TLE2084M TLE2084AM TA UNIT MIN TYP MAX MIN TYP MAX 25°C 25 40 25 40 SR+ Positive slew rate VO(PP) = 10 V, AVD 1 RL 2 kΩ Full range 17 17 V/μs = –1, = kΩ, CL = 100 pF, See Figure 1 25°C 30 45 30 45 SR– Negative slew rate F, Full range 20 20 V/μs t Settling time AVD = –1, 10-V step, To 10 mV 25°C 0.4 0.4 ts , μs RL = 1 kΩ, CL = 100 pF To 1 mV 1.5 1.5 V Equivalent input noise f = 10 Hz 25°C 28 28 Vn nV/√Hz q voltage f = 10 kHz 11.6 11.6 RS = 20 Ω, f = 10 Hz to 6 6 VN(PP) Peak-to-peak equivalent S See Figure 3 10 kHz 25°C μV q input noise voltage f = 0.1 Hz to 0 6 0 6 10 Hz 0.6 0.6 I Equivalent input noise In VIC = 0 f = 10 kHz 25°C 2 8 2 8 fA/√Hz q current 0, 2.8 2.8 fA /√THD + N Total harmonic distortion VO(PP) = 20 V, AVD = 10, f 1 kHz RL 2 kΩ 25°C 0 008% 0 008% plus noise = kHz, = kΩ, RS = 25 Ω 0.008% 0.008% B1 Unity gain bandwidth VI = 10 mV, RL = 2 kΩ, Unity-I 25°C 8∗ 10 8∗ 10 MHz , L , CL = 25 pF, See Figure 2 BOM Maximum output-swing VO(PP) = 20 V, AVD = –1, 25°C 478∗ 637 478∗ 637 kHz g bandwidth O(, VD , RL = 2 kΩ, CL = 25 pF φ Phase margin at unity VI = 10 mV, RL = 2 kΩ, φm 25°C 57° 57° g y gain I , L , CL = 25 pF, See Figure 2 ∗On products compliant with MIL-PRF-38535, Class B, this parameter is not production tested. † Full range is –55°C to 125°C. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 TLE2084Y electrical characteristics at VCC± = ±15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TLE2084Y UNIT MIN TYP MAX VIO Input offset voltage VIC = 0, VO = 0, RS = 50 Ω 7 mV IIO Input offset current VIC = 0, VO = 0, 15 100 pA IIB Input bias current IC O See Figure 4 25 175 pA 15 15 VICR Common-mode input voltage range RS = 50 Ω to to V –11 11.9 IO = –200 μA 13.8 14.1 VOM+ Maximum positive peak output voltage swing IO = –2 mA 13.5 13.9 V IO = –20 mA 11.5 12.3 IO = 200 μA –13.8 –14.2 VOM– Maximum negative peak output voltage swing IO = 2 mA –13.5 –14 V IO = 20 mA –11.5 –12.4 RL = 600 Ω 80 96 AVD Large-signal differential voltage amplification VO = ± 10 V RL = 2 kΩ 90 109 dB RL = 10 kΩ 95 118 ri Input resistance VIC = 0 1012 Ω ci Input capacitance VIC = 0, Common mode 7.5 IC pF See Figure 5 Differential 2.5 zo Open-loop output impedance f = 1 MHz 80 Ω CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 Ω 80 98 dB kSVR Supply-voltage rejection ratio (ΔVCC± /ΔVIO) VCC± = ±5 V to ±15 V, VO = 0, RS = 50 Ω 82 99 dB ICC Supply current ( four amplifiers ) VO = 0, No load 5.2 6.5 7.5 mA IOS Short circuit output current VO = 0 VID = 1 V –30 –45 Short-mA VID = –1 V 30 48 TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION – + 2 kΩ 2 kΩ RL CL† VO VCC+ VCC+ VI – + 10 kΩ VO CL† 100Ω RL VCC+ VCC+ VI † Includes fixture capacitance † Includes fixture capacitance Figure 1. Slew-Rate Test Circuit Figure 2. Unity-Gain Bandwidth and Phase-Margin Test Circuit † Includes fixture capacitance – + – + 2 kΩ VCC+ VCC+ VO VO VCC– RS RS VCC– Ground Shield Picoammeters Figure 3. Noise-Voltage Test Circuit Figure 4. Input-Bias and Offset- Current Test Circuit – + VCC+ VO VCC– IN– IN+ Cic Cic Cid Figure 5. Internal Input Capacitance typical values Typical values presented in this data sheet represent the median (50% point) of device parametric performance. input bias and offset current At the picoampere bias-current level typical of the TLE208x and TLE208xA, accurate measurement of the bias becomes difficult. Not only does this measurement require a picoammeter, but test socket leakages can easily exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters with bias voltages applied but with no device in the socket. The device is then inserted in the socket and a second test is performed that measures both the socket leakage and the device input bias current. The two measurements are then subtracted algebraically to determine the bias current of the device. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 6, 7, 8 αVIO Input offset voltage temperature coefficient Distribution 9, 10, 11 IIO Input offset current vs Free-air temperature 12 – 15 IIB Input bias current vs Free-air temperature 12 – 15 vs Supply voltage 16 VICR Common-mode input voltage range vs Free-air temperature 17 VID Differential input voltage vs Output voltage 18, 19 vs Output current 20, 21 VOM+ Maximum positive peak output voltage vs Free-air temperature , OM+ g 24, 25 vs Supply voltage 26 vs Output current 22, 23 VOM– Maximum negative peak output voltage vs Free-air temperature , OM g g 24, 25 vs Supply voltage 26 VO(PP) Maximum peak-to-peak output voltage vs Frequency 27 VO Output voltage vs Settling time 28 AVD Large signal differential voltage amplification vs Load resistance 29 Large-vs Free-air temperature 30, 31 AVD Small-signal differential voltage amplification vs Frequency 32, 33 CMRR Common mode rejection ratio vs Frequency 34 Common-q y vs Free-air temperature 35 kSVR Supply voltage rejection ratio vs Frequency 36 Supply-q y vs Free-air temperature 37 vs Supply voltage 38, 39, 40 ICC Supply current y g vs Free-air temperature , , CC y 41, 42, 43 vs Differential input voltage 44 – 49 vs Supply voltage 50 IOS Short-circuit output current y g OS vs Elapsed time 51 vs Free-air temperature 52 vs Free-air temperature 53, 54 SR Slew rate vs Load resistance , 55 vs Differential input voltage 56 Vn Equivalent input noise voltage vs Frequency 57 V Input referred noise voltage vs Noise bandwidth frequency 58 Vn Input-q y Over a 10-second time interval 59 Third-octave spectral noise density vs Frequency bands 60 THD +N Total harmonic distortion plus noise vs Frequency 61, 62 B1 Unity-gain bandwidth vs Load capacitance 63 Gain bandwidth product vs Free-air temperature 64 Gain-vs Supply voltage 65 Gain margin vs Load capacitance 66 vs Free-air temperature 67 φm Phase margin vs Supply voltage 68 vs Load capacitance 69 Phase shift vs Frequency 32, 33 TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Table of Graphs (Continued) FIGURE Noninverting large-signal pulse response vs Time 70 Small-signal pulse response vs Time 71 zo Closed-loop output impedance vs Frequency 72 ax Crosstalk attenuation vs Frequency 73 Figure 6 15 12 6 3 0 27 9 – 4 – 2.4 – 0.8 0.8 Percentage of Units – % 21 18 24 DISTRIBUTION OF TLE2081 INPUT OFFSET VOLTAGE 30 2.4 4 VIO – Input Offset Voltage – mV VCC = ±15 V TA = 25°C P Package Figure 7 VIO – Input Offset Voltage – mV 10 8 4 2 0 18 6 – 4 – 2.4 – 0.8 0.8 Percentage of Units – % 14 12 16 DISTRIBUTION OF TLE2082 INPUT OFFSET VOLTAGE 20 2.4 4 600 Units Tested From One Wafer Lot VCC = ±15 V TA = 25°C P Package – 3.2 – 1.6 0 1.6 3.2 TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 TYPICAL CHARACTERISTICS Figure 8 VIO – Input Offset Voltage – mV 25 20 10 5 0 45 15 – 8 – 4.8 – 1.6 1.6 Percentage of Units – % 35 30 40 DISTRIBUTION OF TLE2084 INPUT OFFSET VOLTAGE 50 4.8 8 TA = 25°C N Package VCC± = ±15 V Figure 9 15 12 6 3 0 27 9 – 40 – 32 – 24 –16 – 8 0 8 Percentage of Amplifiers – % 21 18 24 DISTRIBUTION OF TLE2081 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 30 16 24 32 40 VCC = ±15 V TA = – 55 °C to 125°C P Package αVIO – Temperature Coefficient – μV/°C Figure 10 15 12 6 3 0 27 9 – 30 – 24 –18 –12 – 6 0 6 Percentage of Amplifiers – % 21 18 24 DISTRIBUTION OF TLE2082 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 30 12 18 24 30 310 Amplifiers VCC = ±15 V TA = – 55°C to 125°C αVIO – Temperature Coefficient – μV/°C P Package Figure 11 15 12 6 3 0 27 9 – 40 – 32 – 24 –16 – 8 0 8 Percentage of Amplifiers – % 21 18 24 DISTRIBUTION OF TLE2084 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 30 16 24 32 40 VCC± = ±15 V TA = – 55°C to 125°C N Package αVIO – Temperature Coefficient – μV/°C TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS† Figure 12 IIB and – Input Bias and Input Offset Currents – nA 0.01 0.001 25 45 100 65 85 105 125 0.1 1 10 IIO VCC± = ±5 V VIC = 0 VO = 0 IIB IIO –75 –55 –35 –15 –5 TA – Free-Air Temperature – °C TLE2081 AND TLE2082 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE Figure 13 and IIO – Input Bias and Offset Currents – nA 0.01 0.001 25 45 100 65 85 105 125 0.1 1 10 IIB IIO VCC± = ±5 V VIC = 0 VO = 0 IIB IIO –75 –55 –35 –15 –5 TA – Free-Air Temperature – °C TLE2084 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE Figure 14 25 45 65 85 105 125 0.01 0.001 100 0.1 1 10 VCC± = ±15 V VIC = 0 VO = 0 IIO IIB –75 –55 –35 –15 5 TA – Free-Air Temperature – °C IIIIBB and IIIIOO – Input Bias and Input Offset Currents – nA TLE2081 AND TLE2082 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE Figure 15 IIIIBB and IIOIO – Input Bias and Offset Currents – nA 25 45 65 85 105 125 0.01 0.001 100 0.1 1 10 VCC± = ±15 V VIC = 0 VO = 0 IIO IIB –75 –55 –35 –15 5 TA – Free-Air Temperature – °C TLE2084 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49 TYPICAL CHARACTERISTICS† Figure 16 104 103 102 100 101 106 – Input Bias Current – pA INPUT BIAS CURRENT vs TOTAL SUPPLY VOLTAGE 0 5 10 15 20 25 30 35 40 45 IIB TA = 25°C TA = –55°C 105 VICmin TA = 125°C VICmax = VCC+ VCC – Total Supply Voltage (referred to VCC–) – V Figure 17 VVIICC – Common-Mode Input Voltage Range – V 5 25 45 COMMON-MODE INPUT VOLTAGE RANGE vs FREE-AIR TEMPERATURE 65 85 105 125 RS = 50 Ω VCC+ + 0.5 VCC+ –0.5 VCC– + 3.5 VCC+ VCC– +3 VCC– + 2.5 VCC– +2 VICmin VICmax – 75 –55 –35 –15 TA – Free-Air Temperature – °C Figure 18 VVIIDD – Differential Input Voltage – uV – 5 – 4 – 3 – 2 – 10 0 1 DIFFERENTIAL INPUT VOLTAGE vs OUTPUT VOLTAGE 2 5 RL = 2 kΩ RL = 2 kΩ RL = 10 kΩ RL = 10 kΩ VCC± = ±5 V VIC = 0 RS = 50 Ω TA = 25°C RL = 600 Ω RL = 600 Ω – 100 – 200 – 300 – 400 100 200 400 300 0 3 4 VO – Output Voltage – V μV Figure 19 – 100 – 200 – 300 – 400 – 15 – 10 – 5 0 5 100 200 400 10 15 RL = 2 kΩ VCC± = ±15 V RL = 10 kΩ RL = 10 kΩ RL = 2 kΩ RL = 600 Ω RL = 600 Ω DIFFERENTIAL INPUT VOLTAGE vs OUTPUT VOLTAGE 300 0 VO – Output Voltage – V VVIIDD – Differential Input Voltage – uμVV VIC = 0 RS = 50 Ω TA = 25°C † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS† Figure 20 VOM – Maximum Positive Peak Output Voltage – V 7.5 6 3 1.5 0 13.5 4.5 0 – 5 –10 –15 – 20 – 25 – 30 10.5 9 12 15 – 35 – 40 – 45 – 50 VOM+ TA = 25°C TA = 125°C TA = 85°C IO – Output Current – mA VCC± = ±15 V TA = –55°C TLE2081 AND TLE2082 MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT Figure 21 VOM – Maximum Positive Peak Output Voltage – V 6 3 0 0 – 10 – 20 – 30 9 12 15 – 40 – 50 VOM+ TA = 25°C TA = 125°C TA = 85°C IO – Output Current – mA VCC± = ±15 V TLE2084 MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT Figure 22 – Maximum Negative Peak Output Voltage – V –7.5 – 6 – 3 –1.5 0 –13.5 – 4.5 0 5 10 15 20 25 30 –10.5 – 9 –12 –15 35 40 45 50 VOM – TA = 25°C TA = 125°C TA = –55°C VCC± = ±15 V TA = 85°C IO – Output Current – mA TLE2081 AND TLE2082 MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT Figure 23 – Maximum Negative Peak Output Voltage – V – 6 – 3 0 0 10 20 30 – 9 –12 –15 40 50 VOM – TA = 25°C TA = 125°C TA = –55°C VCC± = ±15 V TA = 85°C IO – Output Current – mA TLE2084 MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 TYPICAL CHARACTERISTICS† Figure 24 VOM – Maximum Peak Output Voltage – V 0 – 1 – 3 – 4 – 5 4 – 2 5 25 45 2 1 3 MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 5 65 85 105 125 VOM IO = –200 μA IO = –2 mA IO = –20 mA VCC± = ±5 V IO = 20 mA IO = 2 mA IO = 200 μA –75 –55 –35 –15 TA – Free-Air Temperature – °C Figure 25 12.5 12 11 10.5 10 14.5 11.5 5 25 45 | | – Maximum Peak Output Voltage – V 13.5 13 14 15 65 85 105 125 VOM MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE IO = –20 mA IO = 20 mA IO = 2 mA IO = –200 μA IO = 200 μA VCC± = ±15 V –75 –55 –35 –15 TA – Free-Air Temperature – °C IO = –2 mA Figure 26 VOM – Maximum Peak Output Voltage – V 0 – 5 –15 – 20 – 25 20 –10 0 2.5 5 7.5 10 12.5 15 10 5 15 MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE 25 17.5 20 22.5 25 VOM IO = –200 μA IO = –2 mA IO = –20 mA IO = 20 mA IO = 200 μA IO = 2 mA TA = 25°C |VCC±| – Supply Voltage – V Figure 27 PP) – Maximum Peak-to-Peak Output Voltage – V 20 5 0 30 10 25 100 k 1 M 10 M f – Frequency – Hz VO(PP) 15 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY TA = –55°C TA = 25°C, 125°C TA = 25°C, 125°C TA = –55°C VCC± = ±15 V RL = 2 kΩ VCC± = ±5 V † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS† Figure 28 0 0.5 1 1.5 2 – Output Voltage – V OUTPUT VOLTAGE vs SETTLING TIME VO VCC± = ±15 V RL = 1 kΩ CL = 100 pF AV = –1 TA = 25°C 1 mV 1 mV Rising Falling 10 mV 10 mV – 2.5 – 10 – 12.5 10 12.5 – 5 7.5 2.5 – 7.5 5 0 ts – Settling Time – μs Figure 29 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs LOAD RESISTANCE 115 110 100 95 90 125 105 0.1 1 10 100 120 VCC± = ±15 V VIC = 0 RS = 50 Ω TA = 25°C RL – Load Resistance – kΩ VCC± = ±5 V – Large-Signal Differential ÁÁ ÁÁ AVD Voltage Amplification – dB Figure 30 TA – Free-Air Temperature – °C 95 92 86 83 80 107 89 – 75 – 55 – 35 –15 5 25 45 101 98 104 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE 110 65 85 105 125 RL = 10 kΩ RL = 2 kΩ VCC± = ±5 V RL = 600 Ω VO = ±2.3 V – Large-Signal Differential ÁÁ ÁÁ AVD Voltage Amplification – dB Figure 31 – 55 – 35 –15 105 125 105 101 93 89 85 121 97 113 109 117 125 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE RL = 10 kΩ – 75 5 25 45 65 85 TA – Free-Air Temperature – °C RL = 600 Ω RL = 2 kΩ VCC± = ±15 V VO = ±10 V – Large-Signal Differential ÁÁ ÁÁ AVD Voltage Amplification – dB † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 TYPICAL CHARACTERISTICS 60 20 0 – 40 1 10 100 1 k 10 k 100 k 100 120 f – Frequency – Hz SMALL-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 140 1 M 10 M 100 M 80 40 Gain Phase Shift – 20 140° 120° 100° 80° 60° 40° 20° 0° Phase Shift 180° 160° VCC± = ±15 V RL = 2 kΩ CL = 100 pF TA = 25°C AVD – Small-Signal Differential Voltage Amplification – dB Figure 32 – 10 – 20 30 1 4 10 40 100 f – Frequency – MHz SMALL-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 20 10 0 CL = 100 pF CL = 25 pF VCC± = ± 15 V Phase Shift Gain 80° 120° 100° 140° 160° 180° Phase Shift CL = 100 pF CL = 25 pF VIC = 0 RC = 2 kΩ TA = 25°C AVD – Small-Signal Differential Voltage Amplification – dB Figure 33 TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS† Figure 34 10 100 1 k 10 k CMRR – Common-Mode Rejection Ratio – dB f – Frequency – Hz COMMON-MODE REJECTION RATIO vs FREQUENCY 100 k 1 M 10 M VCC± = ±15 V VCC± = ±5 V VIC = 0 VO = 0 RS = 50 Ω TA = 25°C 50 40 20 10 0 90 30 70 60 80 100 Figure 35 TA – Free-Air Temperature – °C 85 82 76 73 70 97 79 – 75 – 55 – 35 –15 5 25 45 CMRR – Common-Mode Rejection Ratio – dB 91 88 94 100 65 85 105 125 VO = 0 RS = 50 Ω VCC± = ±5 V VCC± = ±15 V COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE VIC = VICRmin Figure 36 kX SXVXRX – Supply-Voltage Rejection Ratio – dB SUPPLY-VOLTAGE REJECTION RATIO vs FREQUENCY 40 20 0 – 20 10 100 1 k 10 k 100 k 60 80 f – Frequency – Hz 100 1 M 10 M 120 kSVR+ kSVR– ΔVCC± = ±5 V to ±15 V VIC = 0 VO = 0 RS = 50 Ω TA = 25°C Figure 37 TA – Free-Air Temperature – °C 90 84 72 66 60 114 78 – 75 – 55 – 35 –15 5 25 45 102 96 108 120 65 85 105 125 SUPPLY-VOLTAGE REJECTION RATIO vs FREE-AIR TEMPERATURE kSVR+ kSVR– kX SXVXRX – Supply-Voltage Rejection Ratio – dB ΔVCC± = ±5 V to ±15 V VIC = 0 VO = 0 RS = 50 Ω † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55 TYPICAL CHARACTERISTICS† Figure 38 |VCC±| – Supply Voltage – V ICC – Supply Current – mA 2 1.6 0.8 0.4 0 3.6 1.2 0 2 4 6 8 10 12 2.8 2.4 3.2 4 14 16 18 20 ICC TA = 25°C TA = –55°C TA = 125°C VIC = 0 VO = 0 No Load TLE2081 SUPPLY CURRENT vs SUPPLY VOLTAGE Figure 39 |VCC±| – Supply Voltage – V ICC – Supply Current – mA 3 2.8 2.4 2.2 2 3.8 2.6 0 2.5 5 7.5 10 12.5 15 3.4 3.2 3.6 4 17.5 20 22.5 25 ICC TA = 25°C TA = –55°C TA = 125°C VIC = 0 VO = 0 No Load TLE2082 SUPPLY CURRENT vs SUPPLY VOLTAGE Figure 40 |VCC±| – Supply Voltage – V ICC – Supply Current – mA 4 2 0 0 2 4 6 8 10 12 6 8 10 14 16 18 20 ICC VIC = 0 VO = 0 No Load TA = –55°C TA = 25°C TA = 125°C TLE2084 SUPPLY CURRENT vs SUPPLY VOLTAGE Figure 41 TA – Free-Air Temperature – °C 2 1.6 0.8 0.4 0 3.6 1.2 – 75 – 55 – 35 – 15 5 25 45 ICC – Supply Current – mA 2.8 2.4 3.2 4 65 85 105 125 ICC VIC = 0 VO = 0 No Load VCC± = ±15 V VCC± = ±5 V TLE2081 SUPPLY CURRENT vs FREE-AIR TEMPERATURE † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS† Figure 42 TA – Free-Air Temperature – °C 3 2.9 2.7 2.6 2.5 3.4 2.8 – 75 – 55 – 35 –15 5 25 45 ICC – Supply Current – mA 3.2 3.1 3.3 3.5 65 85 105 125 ICC VIC = 0 VO = 0 No Load VCC± = ±15 V VCC± = ±5 V TLE2082 SUPPLY CURRENT vs FREE-AIR TEMPERATURE Figure 43 TA – Free-Air Temperature – °C 7 5 6 –75 – 55 – 35 –15 5 25 45 ICC – Supply Current – mA 8 9 10 65 85 105 125 ICC VIC = 0 VO = 0 No Load VCC± = ±15 V VCC± = ±5 V TLE2084 SUPPLY CURRENT vs FREE-AIR TEMPERATURE Figure 44 VID – Differential Input Voltage – V – Supply Current – mA – 0.5 – 0.25 0 0.25 0.5 0 6 8 10 12 ICC VCC+ = 5 V VCC– = 0 VIC = + 4.5 V TA = 25°C Open Loop No Load 4 2 TLE2081 SUPPLY CURRENT vs DIFFERENTIAL INPUT VOLTAGE Figure 45 VID – Differential Input Voltage – V – Supply Current – mA – 0.5 – 0.25 0 0.25 0.5 0 6 8 10 12 14 ICC VCC+ = 5 V VCC– = 0 VIC = 4.5 V TA = 25°C Open Loop No Load 4 2 TLE2082 SUPPLY CURRENT vs DIFFERENTIAL INPUT VOLTAGE † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 TYPICAL CHARACTERISTICS Figure 46 VID – Differential Input Voltage – V – Supply Current – mA – 0.5 – 0.25 0 0.25 0.5 0 6 8 10 12 14 ICC 4 2 VCC+ = 5 V VCC– = 0 VIC = 4.5 V TA = 25°C Open Loop No Load 16 18 20 TLE2084 SUPPLY CURRENT vs DIFFERENTIAL INPUT VOLTAGE Figure 47 VID – Differential Input Voltage – V 10 5 0 –1.5 – 0.9 – 0.3 0 1.5 – Supply Current – mA 15 20 25 ICC 13 8 3 18 23 0.3 0.9 VCC± = ±15 V VIC = 0 TA = 25°C Open Loop No Load TLE2081 SUPPLY CURRENT vs DIFFERENTIAL INPUT VOLTAGE Figure 48 VID – Differential Input Voltage – V 10 5 0 –1.5 –1 – 0.5 0 0.5 1 1.5 – Supply Current – mA 15 20 25 ICC VCC± = ±15 V VIC = 0 TA = 25°C Open Loop No Load TLE2082 SUPPLY CURRENT vs DIFFERENTIAL INPUT VOLTAGE Figure 49 VID – Differential Input Voltage – V 8 4 0 –1.5 – 0.3 0 0.9 1.2 1.5 – Supply Current – mA 12 16 20 ICC VCC± = ±15 V 28 24 32 36 40 –1.2 – 0.9 – 0.6 0.3 0.6 VIC = 0 TA = 25°C Open Loop No Load TLE2084 SUPPLY CURRENT vs DIFFERENTIAL INPUT VOLTAGE TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS† Figure 50 – Short-Circuit Output Current – mA 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 0 –12 – 36 – 48 – 60 48 – 24 24 12 36 SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE 60 IOS VO = 0 TA = 25°C VID = –1 V VID = 1 V |VCC±| – Supply Voltage – V Figure 51 IOS – Short-Circuit Output Current – mA 10 –10 – 20 – 50 0 60 120 30 40 t – Elapsed Time – s 50 180 20 0 SHORT-CIRCUIT OUTPUT CURRENT vs ELAPSED TIME VCC± = ±15 V VID = –1 V VID = 1 V – 30 – 40 VO = 0 TA = 25°C Figure 52 TA – Free-Air Temperature – °C IOS – Short-Circuit Output Current – mA 0 – 16 – 48 – 64 – 80 64 – 32 – 75 – 55 – 35 –15 5 25 45 32 16 48 SHORT-CIRCUIT OUTPUT CURRENT vs FREE-AIR TEMPERATURE 80 65 85 105 125 IOS VCC± = ±15 V VCC± = ±15 V VCC± = ±5 V VCC± = ±5 V VID = –1 V VID = 1 V VO = 0 Figure 53 TA – Free-Air Temperature – °C SR – Slew Rate – xs 35 33 29 27 25 43 31 – 75 – 55 – 35 –15 5 25 45 39 37 41 SLEW RATE vs FREE-AIR TEMPERATURE 45 65 85 105 125 V/μ s VCC± = ± 5 V RL = 2 kΩ CL = 100 pF SR– SR+ † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 TYPICAL CHARACTERISTICS† Figure 54 TA – Free-Air Temperature – °C 50 46 38 34 30 66 42 – 75 – 55 – 35 –15 5 25 45 SR – Slew Rate – 58 54 62 SLEW RATE vs FREE-AIR TEMPERATURE 70 65 85 105 125 V/μs VCC± = ±15 V RL = 2 kΩ CL = 100 pF SR– SR+ Figure 55 RL – Load Resistance – Ω 10 –10 0 – 20 – 50 50 – 30 100 1 k 10 k 100 k 30 20 40 SLEW RATE vs LOAD RESISTANCE VCC± = ±15 V VO± = ±10 V VCC± = ±5 V VO± = ±2.5 V Rising Edge Falling Edge – 40 SR – Slew Rate – V/μs AV = –1 CL = 100 pF TA = 25°C Figure 56 VID – Differential Input Voltage – V 50 0.1 0.4 1 4 10 SLEW RATE vs DIFFERENTIAL INPUT VOLTAGE VCC± = ±15 V VO± = ±10 V (10% – 90%) CL = 100 pF TA = 25°C Rising Edge Falling Edge 40 30 20 10 0 –10 – 20 – 30 – 40 – 50 SR – Slew Rate – V/μs AV = 1 AV = –1 AV = –1 AV = 1 Figure 57 – Equivalent Input Noise Voltage – 40 5 25 15 0 50 30 10 100 1 k 10 k 45 10 20 f – Frequency – Hz EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 35 Vn nV/ Hz VIC = 0 RS = 20 Ω TA = 25°C VCC± = ±15 V † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 58 0.01 1 10 100 1 k 10 k 100 k Noise Bandwidth Frequency – Hz 1 0.1 10 100 INPUT-REFERRED NOISE VOLTAGE vs NOISE BANDWIDTH FREQUENCY VCC± = ±15 V VIC = 0 RS = 20 Ω TA = 25°C Peak-to-Peak RMS VVnn – Input-Referred Noise Voltage – μV Figure 59 0.3 0 – 0.3 – 0.6 0 1 2 3 4 5 6 – Input-Referred Noise Voltage – 0.6 0.9 t – Time – s INPUT-REFERRED NOISE VOLTAGE OVER A 10-SECOND TIME INTERVAL 1.2 7 8 9 10 Vn μV VCC± = ±15 V f = 0.1 to 10 Hz TA = 25°C Figure 60 – 90 – 95 –100 –115 10 15 20 25 30 35 Third-Octave Spectral Noise Density – dB – 85 – 80 Frequency Bands THIRD-OCTAVE SPECTRAL NOISE DENSITY vs FREQUENCY BANDS – 75 40 45 VCC± = ±15 V Start Frequency: 12.5 Hz Stop Frequency: 20 kHz –105 –110 VIC = 0 TA = 25°C Figure 61 0.001 10 100 1 k 10 k 100 k THD + N – Total Harmonic Distortion + Noise – % 0.01 f – Frequency – Hz TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 0.1 1 VCC± = ±5 V VO(PP) = 5 V TA = 25°C Filter: 10-Hz to 500-kHz Band Pass AV = 100, RL = 600 Ω AV = 100, RL = 2 kΩ AV = 10, RL = 2 kΩ AV = 10, RL = 600 Ω TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61 TYPICAL CHARACTERISTICS† Figure 62 10 100 1 k 10 k 100 k f – Frequency – Hz 0.001 THD + N – Total Harmonic Distortion + Noise – % TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 0.01 0.1 1 Filter: 10-Hz to 500-kHz Band Pass VCC± = ±15 V VO(PP) = 20 V TA = 25°C AV = 100, RL = 600 Ω AV = 100, RL = 2 kΩ AV = 10, RL = 600 Ω AV = 10, RL = 2 kΩ Figure 63 BB11 – Unity-Gain Bandwidth – MHz 10 9 8 7 0 20 40 60 11 12 UNITY-GAIN BANDWIDTH vs LOAD CAPACITANCE 13 80 100 VCC± = ±15 V VIC = 0 VO = 0 RL = 2 kΩ TA = 25°C CL – Load Capacitance – pF Figure 64 TA – Free-Air Temperature – °C 10 9 8 7 – 75 – 55 – 35 – 15 5 25 45 Gain-Bandwidth Product – MHz 11 12 GAIN-BANDWIDTH PRODUCT vs FREE-AIR TEMPERATURE 13 65 85 105 125 f = 100 kHz VIC = 0 VO = 0 RL = 2 kΩ CL = 100 pF VCC± = ±15 V VCC± = ±5 V Figure 65 |VCC + | – Supply Voltage – V 10 9 8 7 0 5 10 15 Gain-Bandwidth Product – MHz 11 12 13 20 25 VCC ± f = 100 kHz VIC = 0 VO = 0 RL = 2 kΩ CL = 100 pF TA = 25°C GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS† Figure 66 Gain Margin – dB 6 4 2 0 0 20 40 60 8 GAIN MARGIN vs LOAD CAPACITANCE 10 80 100 VCC± = ±15 V VIC = 0 VO = 0 RL = 2 kΩ TA = 25°C CL – Load Capacitance – pF Figure 67 30° 20° 10° 0° 40° 50° 60° 70° 80° 90° xm – Phase Margin –75 – 55 – 35 –15 5 25 45 PHASE MARGIN vs FREE-AIR TEMPERATURE 65 85 105 φm VCC± = ±15 V VCC± = ±15 V VCC± = ±5 V VCC± = ±5 V 125 VIC = 0 VO = 0 CL = 25 pF CL = 100 pF TA – Free-Air Temperature – °C RL = 2 kΩ Figure 68 PHASE MARGIN vs SUPPLY VOLTAGE 0 4 8 12 16 20 VIC = 0 VO = 0 RL = 2 kΩ TA = 25°C 0° 10° 90° 80° 30° 20° 40° 50° 60° 70° CL = 25 pF CL = 100 pF |VCC±| – Supply Voltage – V xφmm – Phase Margin Figure 69 0° 10° 90° 80° VIC = 0 VO = 0 RL = 2 kΩ TA = 25°C VCC± = ±15 V VCC± = ±5 V PHASE MARGIN vs LOAD CAPACITANCE 30° 20° 40° 50° 60° 70° 0 20 40 60 80 100 CL – Load Capacitance – pF xφmm – Phase Margin † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 TYPICAL CHARACTERISTICS† Figure 70 – Output Voltage – V 0 – 5 – 10 – 15 0 1 5 10 NONINVERTING LARGE-SIGNAL PULSE RESPONSE 15 2 4 5 VO VCC± = ±15 V AV = 1 RL = 2 kΩ CL = 100 pF TA = 25°C, 125°C TA = 25°C, 125°C TA = –55°C 3 TA = –55°C t – Time – μs Figure 71 0 – 50 –100 0 0.4 0.8 VO – Output Voltage – mV 50 SMALL-SIGNAL PULSE RESPONSE 100 1.2 1.6 VCC± = ±15 V t – Time – μs AV = –1 RL = 2 kΩ CL = 100 pF TA = 25°C Figure 72 CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 0.001 10 100 1 k 10 k 100 k 1 M 10 M f – Frequency – Hz 1 0.1 10 100 AV = 100 AV = 10 AV = 1 VCC± = ±15 V 0.01 TA = 25°C zzoo – Closed-Loop Output Impedance – ΩX Figure 73 100 60 40 20 140 80 10 100 1 k 10 k 100 k – Crosstalk Attenuation – dB 120 f – Frequency – Hz ax VCC± = ±15 V VIC = 0 RL = 2 kΩ TA = 25°C TLE2082 AND TLE2084 CROSSTALK ATTENUATION vs FREQUENCY † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION input characteristics The TLE208x, TLE208xA, and TLE208xB are specified with a minimum and a maximum input voltage that if exceeded at either input could cause the device to malfunction. Because of the extremely high input impedance and resulting low bias current requirements, the TLE208x, TLE208xA, and TLE208xB are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias current requirements and cause degradation in system performance. It is good practice to include guard rings around inputs (see Figure 74). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input. VI R2 R1 VI R4 + – VO R3 VI + – VO VO + – R3 R4 R2 R1 Where Figure 74. Use of Guard Rings TLE2081 input offset voltage nulling The TLE2061 series offers external null pins that can be used to further reduce the input offset voltage. The circuit of Figure 75 can be connected as shown if the feature is desired. When external nulling is not needed, the null pins may be left unconnected. + – VCC– N2 N1 100 kΩ 5 kΩ IN– IN+ OUT Figure 75. Input Offset Voltage Nulling TLE208x, TLE208xA, TLE208xY EXCALIBUR HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS SLOS182B – FEBRUARY 1997 – REVISED JUNE 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using PSpice Parts model generation software. The Boyle macromodel (see Note 4) and subcircuit in Figure 58 were generated using the TLE208x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification NOTE 4: G.R. Boyle, B.M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). OUT + – + – + – + – + – + – + – – + VCC+ RP IN– 2 IN+ 1 VCC– RD1 11 J1 J2 10 RSS ISS 3 12 RD2 VE 54 DE DP VC DC C1 53 R2 6 9 EGND VB FB C2 GCM GA VLIM 8 5 RO1 RO2 HLIM 90 DLP 91 DLN 92 VLP VLN 99 7 4 .SUBCKT TLE208x 1 2 3 4 5 C1 11 12 2.2E–12 C2 6 7 10.00E–12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX DP 4 3 DX EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 FB 7 99 POLY (5) VB VC VE VLP VLN 0 + . . . . 5.607E6 –6E6 6E6 6E6 –6E6 GA 6 0 11 12 333.0E–6 GCM 0 6 10 99 7.43E–9 ISS 3 10 DC 400.0E–6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX RD1 4 11 3.003E3 RD2 4 12 3.003E3 R01 8 5 80 R02 7 99 80 RP 3 4 27.30E3 RSS 10 99 500.0E3 VB 9 0 DC 0 VC 3 53 DC 2.20 VE 54 4 DC 2.20 VLIM 7 8 DC 0 VLP 91 0 DC 45 VLN 0 92 DC 45 .MODEL DX D (IS=800.0E–18) .MODEL JX PJF (IS=15.00E–12 BETA=554.5E–6 + VTO=–.6) .ENDS R2 6 9 100.0E3 Figure 76. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. PACKAGE OPTION ADDENDUM www.ti.com 9-May-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLE2081ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 2081AC TLE2081ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 2081AC TLE2081ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 2081AC TLE2081ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 2081AC TLE2081ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLE2081AC TLE2081ACPE4 ACTIVE PDIP P 8 TBD Call TI Call TI -40 to 85 TLE2081AC TLE2081AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2081AI TLE2081AIDG4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 2081AI TLE2081AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLE2081AI TLE2081AIPE4 ACTIVE PDIP P 8 TBD Call TI Call TI -40 to 85 TLE2081AI TLE2081CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 2081C TLE2081CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 2081C TLE2081CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 2081C TLE2081CDRG4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70 2081C TLE2081CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLE2081CP TLE2081CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLE2081CP TLE2081ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2081I TLE2081IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2081I PACKAGE OPTION ADDENDUM www.ti.com 9-May-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLE2081IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2081I TLE2081IDRG4 ACTIVE SOIC D 8 TBD Call TI Call TI 2081I TLE2081IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2081IP TLE2081IPE4 ACTIVE PDIP P 8 TBD Call TI Call TI TLE2081IP TLE2082ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082AC TLE2082ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082AC TLE2082ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082AC TLE2082ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082AC TLE2082ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2082AC TLE2082ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2082AC TLE2082AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082AI TLE2082AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082AI TLE2082AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082AI TLE2082AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082AI TLE2082AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2082AI TLE2082AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2082AI TLE2082AMFKB NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 TLE2082 AMFKB TLE2082AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TLE2082 AMJGB TLE2082AMP OBSOLETE PDIP P 8 TBD Call TI Call TI -55 to 125 PACKAGE OPTION ADDENDUM www.ti.com 9-May-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLE2082CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082C TLE2082CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082C TLE2082CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082C TLE2082CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082C TLE2082CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2082CP TLE2082CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2082CP TLE2082ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082I TLE2082IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082I TLE2082IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082I TLE2082IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2082I TLE2082IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2082IP TLE2082IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2082IP TLE2082MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 TLE2082 MFKB TLE2082MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125 TLE2082MP OBSOLETE PDIP P 8 TBD Call TI Call TI -55 to 125 TLE2084ACDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLE2084AC TLE2084ACDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLE2084AC TLE2084ACN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2084ACN TLE2084ACNE4 ACTIVE PDIP N 14 TBD Call TI Call TI TLE2084ACN PACKAGE OPTION ADDENDUM www.ti.com 9-May-2014 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLE2084CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLE2084C TLE2084CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLE2084C TLE2084CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLE2084C TLE2084CDWRG4 ACTIVE SOIC DW 16 TBD Call TI Call TI TLE2084C TLE2084CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2084CN TLE2084CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLE2084CN TLE2084IDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLE2084I TLE2084IDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLE2084I TLE2084IDWR OBSOLETE SOIC DW 16 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. PACKAGE OPTION ADDENDUM www.ti.com 9-May-2014 Addendum-Page 5 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF TLE2082, TLE2082A, TLE2082AM, TLE2082M : • Catalog: TLE2082A, TLE2082 • Military: TLE2082M, TLE2082AM NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TLE2081ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2081CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2081IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2081IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2082AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2082AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLE2084CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLE2081ACDR SOIC D 8 2500 340.5 338.1 20.6 TLE2081CDR SOIC D 8 2500 340.5 338.1 20.6 TLE2081IDR SOIC D 8 2500 340.5 338.1 20.6 TLE2081IDR SOIC D 8 2500 367.0 367.0 35.0 TLE2082ACDR SOIC D 8 2500 340.5 338.1 20.6 TLE2082AIDR SOIC D 8 2500 367.0 367.0 35.0 TLE2082AIDR SOIC D 8 2500 340.5 338.1 20.6 TLE2082CDR SOIC D 8 2500 340.5 338.1 20.6 TLE2082IDR SOIC D 8 2500 340.5 338.1 20.6 TLE2084CDWR SOIC DW 16 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 5 4 0.065 (1,65) 0.045 (1,14) 8 1 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. 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The IL710 is the world's fastest digital isolator with a 110 Mbaud data rate. The symmetric magnetic coupling barrier provides a typical propagation delay of only 10 ns and a pulse width distortion of 2 ns achieving the best specifications of any isolator device. Typical transient immunity of 30 kV/μs is unsurpassed. The IL710 is ideally suited for isolating applications such as PROFIBUS, RS-485, RS422 and others. The IL710 is available in 8-pin PDIP and 8-pin SOIC packages and performance is specified over the temperature range of -40°C to +100°C without any derating. Isoloop® is a registered trademark of NVE Corporation * US Patent number 5,831,426; 6,300,617 and others IL710ISOLOOP® 2 NVE Corporation 11409 Valley View Road Eden Prairie, MN 55344-3617 USA Telephone: (952) 829-9217 Fax: (952) 829-9189 Internet: www.isoloop.com Recommended Operating Conditions Parameters Symbol Min. Max. Units Ambient Operating Temperature TA -40 100 oC Supply Voltage (3.3/5.0 V operation) VDD1,VDD2 3.0 5.5 Volts Supply Voltage (5.0 V operation) VDD1,VDD2 4.5 5.5 Volts Logic High Input Voltage VIH 2.4 VDD1 Volts Logic Low Input Voltage VIL 0 0.8 Volts Minimum Signal Rise and Fall Times tIR,tIF 1 μsec Absolute Maximum Ratings Parameters Symbol Min. Max. Units Storage Temperature TS -55 175 oC Ambient Operating Temperature(1) TA -55 125 oC Supply Voltage VDD1,VDD2 -0.5 7 Volts Input Voltage VI -0.5 VDD1+0.5 Volts Input Voltage VOE -0.5 VDD2+0.5 Volts Output Voltage VO -0.5 VDD2+0.5 Volts Output Current Drive IO 10 mA Lead Solder Temperature (10s) 280 oC ESD 2kV Human Body Model Insulation Specifications Parameter Condition Min. Typ. Max. Units Barrier Impedance >1014 ||3 Ω || pF Creepage Distance (External) 7.036 (PDIP) mm 4.026 (SOIC) Leakage Current 240 VRMS 0.2 μA 60Hz Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Capacitance (Input-Output)(5) CI-O 1.1 pF f= 1MHz Thermal Resistance (PDIP) θJCT 150 oC/W Thermocouple located at (SOIC) θJCT 240 oC/W center underside of package Package Power Dissipation PPD 150 mW Model Pollution Material Max Working Package Type Degree Group Voltage 8–PDIP 8–SOIC IL710-2 II III 300 VRMS IL710-3 II III 150 VRMS IEC61010-1 TUV Certificate Numbers: B 01 07 44230 001 (PDIP) B 01 07 44230 002 (SOIC) Classification as Table 1. UL 1577 Component Recognition program. File # E207481 Rated 2500Vrms for 1min. NVE Corporation 11409 Valley View Road Eden Prairie, MN 55344-3617 USA Telephone: (952) 829-9217 Fax: (952) 829-9189 Internet: www.isoloop.com Electrical Specifications Electrical Specifications are Tmin to Tmax unless otherwise stated. Parameter Symbol 3.3 Volt Specifications 5.0 Volt Specifications Units Test Conditions DC Specifications Min. Typ. Max. Min. Typ. Max. Input Quiescent Supply Current IDD1 8 10 10 15 μA Output Quiescent Supply Current IDD2 1.7 2 2.5 3 mA Logic Input Current II -10 10 -10 10 μA Logic High Output Voltage VOH VDD2-0.1 VDD2 VDD2-0.1 VDD2 V IO =-20 μA, VI =VIH 0.8*VDD2 VDD2-0.5 0.8*VDD2 VDD2-0.5 IO = -4 mA, VI =VIH Logic Low Output Voltage VOL 0 0.1 0 0.1 V IO = 20 μA, VI =VIL 0.5 0.8 0.5 0.8 IO = 4 mA, VI =VIL Switching Specifications Maximum Data Rate 100 110 100 110 MBd CL = 15 pF Pulse Width PW 10 10 ns Propagation Delay Input to Output (High to Low) tPHL 12 18 10 15 ns CL = 15 pF Propagation Delay Input to Output (Low to High) tPLH 12 18 10 15 ns CL = 15 pF Propagation Delay Enable to Output (High to High Impedance) tPHZ 3 5 3 5 ns CL = 15 pF Propagation Delay Enable to Output (Low to High Impedance) tPLZ 3 5 3 5 ns CL = 15 pF Propagation Delay Enable to Output (High Impedance to High) tPZH 3 5 3 5 ns CL = 15 pF Propagation Delay Enable to Output (High Impedance to Low) tPZL 3 5 3 5 ns CL = 15 pF Pulse Width Distortion(2) 2 3 2 3 Propagation Delay Skew(3) tPSK 4 6 4 6 ns CL = 15 pF Output Rise Time (10-90%) tR 2 4 1 3 ns CL = 15 pF Output Fall Time (10-90%) tF 2 4 1 3 ns CL = 15 pF Common Mode Transient |CMH| Immunity (Output Logic High or 20 30 20 30 kV/μs Vcm = 300V Logic Low) (4) |CML| IL710ISOLOOP® 3 Notes: 1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee performance. 2. PWD is defined as | tPHL - tPLH |. %PWD is equal to the PWD divided by the pulse width. 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25OC. 4. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common mode input voltage that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 5. Device is considered a two terminal device: pins 1-4 shorted and pins 5-8 shorted. IL710ISOLOOP® 4 NVE Corporation 11409 Valley View Road Eden Prairie, MN 55344-3617 USA Telephone: (952) 829-9217 Fax: (952) 829-9189 Internet: www.isoloop.com Application Notes: Dynamic Power Consumption Isoloop devices achieve their low power consumption from the manner by which they transmit data across the isolation barrier. By detecting the edge transitions of the input logic signal and converting these to narrow current pulses, a magnetic field is created around the GMR Wheatstone bridge. Depending on the direction of the magnetic field, the bridge causes the output comparator to switch following the input logic signal. Since the current pulses are narrow, about 2.5ns wide, the power consumption is independent of mark-to-space ratio and solely dependent on frequency. This has obvious advantages over optocouplers whose power consumption is heavily dependent on its on-state and frequency. The approximate power supply current per channel for IsoLoop® is: Power Supply Decoupling Both power supplies to these devices should be decoupled with low ESR 47 nF ceramic capacitors. For data rates in excess of 10MBd, use of ground planes for both GND1 and GND2 is highly recommended. Capacitors must be located as close as possible to the VDD Pins. Signal Status on Start-up and Shut Down To minimize power dissipation, the input signals are differentiated and then latched on the output side of the isolation barrier to reconstruct the signal. This could result in an ambiguous output state depending on power up, shutdown and power loss sequencing. Therefore, the designer should consider the inclusion of an initialization signal in his start-up circuit. Initialization consists of toggling the input either high then low or low then high, depending on the desired state. Electrostatic Discharge Sensitivity This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, NVE recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. Data Transmission Rates The reliability of a transmission system is directly related to the accuracy and quality of the transmitted digital information. For a digital system, those parameters which determine the limits of the data transmission are pulse width distortion and propagation delay skew. Propagation delay is the time taken for the signal to travel through the device. This is usually different when sending a low-to-high than when sending a high-to-low signal. This difference, or error, is called pulse width distortion (PWD) and is usually in ns. It may also be expressed as a percentage: This figure is almost three times better than for any available optocoupler with the same temperature range, and two times better than any optocoupler regardless of published temperature range. The IsoLoop® range of isolators surpasses the 10% maximum PWD recommended by PROFIBUS, and will run at almost 35 Mb before reaching the 10% limit. Propagation delay skew is the difference in time taken for two or more channels to propagate their signals. This becomes significant when clocking is involved since it is undesirable for the clock pulse to arrive before the data has settled. A short propagation delay skew is therefore critical, especially in high data rate parallel systems, to establish and maintain accuracy and repeatability. The IsoLoop® range of isolators all have a maximum propagation delay skew of 6 ns, which is five times better than any optocoupler. PWD% = Maximum Pulse Width Distortion (ns) x 100% Signal Pulse Width (ns) For example: For data rates of 12.5 Mb PWD% = 3 ns 80 ns x 100% = 3.75% IL710ISOLOOP® 5 NVE Corporation 11409 Valley View Road Eden Prairie, MN 55344-3617 USA Telephone: (952) 829-9217 Fax: (952) 829-9189 Internet: www.isoloop.com RS-485 Truth Table TXD RTS A B RXD 1 0 Z Z X 0 0 Z Z X 1 1 1 0 1 0 1 0 1 0 Isolated PROFIBUS / RS-485 Applications Reference 485 Drivers (Texas Instruments) 65ALS176 (-40°C to +85°C) 75ALS176 (0°C to +70°) VDD1 and VISO should be decoupled with 10 nF capacitors at IL710 supply pins IL710ISOLOOP® NVE Corporation 11409 Valley View Road Eden Prairie, MN 55344-3617 USA Telephone: (952) 829-9217 Fax: (952) 829-9189 Internet: www.isoloop.com 6 Truth Table VI VOE VO L L L H L H L H Z H H Z Legend tPLH Propagation Delay, Low to High tPHL Propagation Delay, High to Low tPW Minimum Pulse Width tPLZ Propagation Delay, Low to High Impedance tPZH Propagation Delay, High Impedance to High tPHZ Propagation Delay, High to High Impedance tPZL Propagation Delay, High Impedance to Low tR Rise Time tF Fall Time Timing Diagram IR Soldering Profile Pin Configuration Recommended profile shown. Maximum temperature allowed on any profile is 260° C. 7 NVE Corporation 11409 Valley View Road Eden Prairie, MN 55344-3617 USA Telephone: (952) 829-9217 Fax: (952) 829-9189 Internet: www.isoloop.com IL710-2 (8-Pin PDIP Package) IL710-3 (Small Outline SOIC-8 package) IL710ISOLOOP® Ordering Information: use the following format to order these devices IL 710 -2 B E TR7 Bulk Package Blank = Tube TR7 = 7’’ Tape and Reel TR13 = 13’’ Tape and Reel Lead Frame Material Blank = Tin-Lead Plating E = 100% Tin (Pb Free) Supply Voltage Blank = 3.3/5.0 VDC B = 5.0 VDC Package -2 = PDIP -3 = SOIC (0.15’’) Base Part Number 710 = 1 drive channel Product Family IL = Isolators Valid Part Numbers IL 710-2 IL 710-2E IL 710-2B IL 710-2BE IL 710-3 IL 710-3E IL 710-3B IL 710-3BE All IL710-3 products are available in TR7 or TR13 bulk package options. NVE Corporation 11409 Valley View Road Eden Prairie, Mn 55344-3617 USA Telephone: (952) 829-9217 Fax: (952) 829-9189 Internet: www.nve.com e-mail: isoinfo@nve.com About NVE NVE Corporation is a world leader in the practical commercialization of "spintronics," which many experts believe represents the next generation of microelectronics — the successor to the transistor. Unlike conventional electronics, which rely on electron charge, spintronics uses electron spin to store and transmit information. Spintronics devices are smaller, faster, and more accurate, compared to charge-based microelectronics. It is the spin of electrons that causes magnetism. NVE's products use proprietary spintronic materials called Giant Magnetoresistors (GMR). These materials are made of exotic alloys a few atoms thick, and provide very large signals (the "Giant" in "Giant Magnetoresistor"). NVE has the unique capability to combine leading edge GMR materials with integrated circuits to make high performance electronic components. We are pioneers in creating practical products using this revolutionary technology and introduced the world's first GMR products in 1994. We also license spintronics/Magnetic Random Access Memory (MRAM) designs to world-class memory manufacturers. Our products include: · Digital Signal Isolators · Isolated Bus Transceivers · Magnetic Field Sensors · Magnetic Field Gradient Sensors (Gradiometer) · Digital Magnetic Field Sensors. The information provided by NVE Corporation is believed to be accurate. However, no responsibility is assumed by NVE Corporation for its use, nor for any infringement of patents, nor rights or licenses granted to third parties, which may result from its use. No license is granted by implication, or otherwise, under any patent or patent rights of NVE Corporation. NVE Corporation does not authorize, nor warrant, any NVE Corporation product for use in life support devices or systems or other critical applications. The use of NVE Corporation’s products in such applications is understood to be entirely at the customer's own risk. Specifications shown are subject to change without notice. ISB-DS-001-IL710-G May 31, 2005 Features ➤ Fast charge and conditioning of nickel cadmium or nickel-metal hydride batteries ➤ Hysteretic PWM switch-mode current regulation or gated control of an external regulator ➤ Easily integrated into systems or used as a stand-alone charger ➤ Pre-charge qualification of temperature and voltage ➤ Configurable, direct LED outputs display battery and charge status ➤ Fast-charge termination by Δ temperature/ Δ time, peak volume detection, -ΔV, maximum voltage, maximum temperature, and maximum time ➤ Optional top-off charge and pulsed current maintenance charging ➤ Logic-level controlled low-power mode (< 5μA standby current) General Description The bq2004E and bq2004H Fast Charge ICs provide comprehensive fast charge control functions together with high-speed switching power control circuitry on a monolithic CMOS device. Integration of closed-loop current control circuitry allows the bq2004 to be the basis of a cost-effective solution for stand-alone and systemintegrated chargers for batteries of one or more cells. Switch-activated discharge-beforecharge allows bq2004E/H-based chargers to support battery conditioning and capacity determination. High-efficiency power conversion is accomplished using the bq2004E/H as a hysteretic PWM controller for switch-mode regulation of the charging current. The bq2004E/H may alternatively be used to gate an externally regulated charging current. Fast charge may begin on application of the charging supply, replacement of the battery, or switch depression. For safety, fast charge is inhibited unless/until the battery temperature and voltage are within configured limits. Temperature, voltage, and time are monitored throughout fast charge. Fast charge is terminated by any of the following: Rate of temperature rise (ΔT/Δt) Peak voltage detection (PVD) Negative delta voltage (-ΔV) Maximum voltage Maximum temperature Maximum time After fast charge, optional top-off and pulsed current maintenance phases with appropriate display mode selections are available. The bq2004H differs from the bq2004E only in that fast charge, hold-off, and top-off time units have been scaled up by a factor of two, and the bq2004H provides different display selections. Timing differences between the two ICs are illustrated in Table 1. Display differences are shown in Table 2. 1 Fast-Charge ICs bq2004E/H DCMD Discharge command DSEL Display select VSEL Voltage termination select TM1 Timer mode select 1 TM2 Timer mode select 2 TCO Temperature cutoff TS Temperature sense BAT Battery voltage 1 PN2004E01.eps 16-Pin Narrow DIP or Narrow SOIC 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 INH DIS MOD VCC VSS LED2 LED1 SNS DCMD DSEL VSEL TM1 TM2 TCO TS BAT SNS Sense resistor input LED1 Charge status output 1 LED2 Charge status output 2 VSS System ground VCC 5.0V ±10% power MOD Charge current control DIS Discharge control output INH Charge inhibit input Pin Connections SLUS081A - APRIL 2005 Pin Names Pin Descriptions DCMD Discharge-before-charge control input The DCMD input controls the conditions that enable discharge-before-charge. DCMD is pulled up internally. A negative-going pulse on DCMD initiates a discharge to endof- discharge voltage (EDV) on the BAT pin, followed by a new charge cycle start. Tying DCMD to ground enables automatic discharge-before-charge on every new charge cycle start. DSEL Display select input This three-state input configures the charge status display mode of the LED1 and LED2 outputs and can be used to disable top-off and pulsed-trickle. See Table 2. VSEL Voltage termination select input This three-state input controls the voltagetermination technique used by the bq2004E/H. When high, PVD is active. When floating, -ΔV is used. When pulled low, both PVD and -ΔV are disabled. TM1– TM2 Timer mode inputs TM1 and TM2 are three-state inputs that configure the fast charge safety timer, voltage termination hold-off time, “top-off ”, and trickle charge control. See Table 1. TCO Temperature cut-off threshold input Input to set maximum allowable battery temperature. If the potential between TS and SNS is less than the voltage at the TCO input, then fast charge or top-off charge is terminated. TS Temperature sense input Input, referenced to SNS, for an external thermister monitoring battery temperature. BAT Battery voltage input BAT is the battery voltage sense input, referenced to SNS. This is created by a highimpedance resistor-divider network connected between the positive and the negative terminals of the battery. SNS Charging current sense input SNS controls the switching of MOD based on an external sense resistor in the current path of the battery. SNS is the reference potential for both the TS and BAT pins. If SNS is connected to VSS, then MOD switches high at the beginning of charge and low at the end of charge. LED1– LED2 Charge status outputs Push-pull outputs indicating charging status. See Table 2. Vss Ground VCC VCC supply input 5.0V, ±10% power input. MOD Charge current control output MOD is a push-pull output that is used to control the charging current to the battery. MOD switches high to enable charging current to flow and low to inhibit charging current flow. DIS Discharge control output Push-pull output used to control an external transistor to discharge the battery before charging. INH Charge inhibit input When low, the bq2004E/H suspends all charge actions, drives all outputs to high impedance, and assumes a low-power operational state. When transitioning from low to high, a new charge cycle is started. 2 bq2004E/H Functional Description Figure 2 shows a block diagram and Figure 3 shows a state diagram of the bq2004E/H. Battery Voltage and Temperature Measurements Battery voltage and temperature are monitored for maximum allowable values. The voltage presented on the battery sense input, BAT, should represent a two-cell potential for the battery under charge. A resistor-divider ratio of: RB1 RB2 = N 2 - 1 is recommended to maintain the battery voltage within the valid range, where N is the number of cells, RB1 is the resistor connected to the positive battery terminal, and RB2 is the resistor connected to the negative battery terminal. See Figure 1. Note: This resistor-divider network input impedance to end-to-end should be at least 200kΩ and less than 1MΩ. A ground-referenced negative temperature coefficient thermistor placed in proximity to the battery may be used as a low-cost temperature-to-voltage transducer. The temperature sense voltage input at TS is developed using a resistor-thermistor network between VCC and VSS. See Figure 1. Both the BAT and TS inputs are referenced to SNS, so the signals used inside the IC are: VBAT - VSNS = VCELL and VTS - VSNS = VTEMP Discharge-Before-Charge The DCMD input is used to command discharge-beforecharge via the DIS output. Once activated, DIS becomes active (high) until VCELL falls below VEDV, at which time DIS goes low and a new fast charge cycle begins. The DCMD input is internally pulled up to VCC (its inactive state). Leaving the input unconnected, therefore, results in disabling discharge-before-charge. A negative going pulse on DCMD initiates discharge-before-charge at any time regardless of the current state of the bq2004. If DCMD is tied to VSS, discharge-before-charge will be the first step in all newly started charge cycles. Starting A Charge Cycle A new charge cycle is started by: 1. Application of VCC power. 2. VCELL falling through the maximum cell voltage, VMCV where: VMCV = 0.8 ∗ VCC ± 30mV 3. A transition on the INH input from low to high. If DCMD is tied low, a discharge-before-charge will be executed as the first step of the new charge cycle. Otherwise, pre-charge qualification testing will be the first step. The battery must be within the configured temperature and voltage limits before fast charging begins. The valid battery voltage range is VEDV < VBAT < VMCV where: VEDV = 0.4 ∗ VCC ± 30mV 3 bq2004E/H Fg2004a.eps NT C bq2004E/H VCC PACK + PACK - TS SNS RT1 RT2 RB2 bq2004E/H RB1 Negative Temperature Coefficient Thermister PACK+ PACKBAT SNS Figure 1. Voltage and Temperature Monitoring The valid temperature range is VHTF < VTEMP < VLTF, where: VLTF = 0.4 ∗ VCC ± 30mV VHTF = [(1/3 ∗ VLTF) + (2/3 ∗ VTCO)] ± 30mV VTCO is the voltage presented at the TCO input pin, and is configured by the user with a resistor divider between VCC and ground. The allowed range is 0.2 to 0.4 ∗ VCC. If the temperature of the battery is out of range, or the voltage is too low, the chip enters the charge pending state and waits for both conditions to fall within their allowed limits. During the charge-pending mode, the IC first applies a top-off charge to the battery. The top-off charge, at the rate of 1 8 of the fast charge, continues until the fast-charge conditions are met or the top-off time-out period is exceeded. The IC then trickle charges until the fast-charge conditions are met. There is no time limit on the charge pending state; the charger remains in this state as long as the voltage or temperature conditons are outside of the allowed limits. If the voltage is too high, the chip goes to the battery absent state and waits until a new charge cycle is started. Fast charge continues until termination by one or more of the six possible termination conditions: Delta temperature/delta time (ΔT/Δt) Peak voltage detection (PVD) Negative delta voltage (-ΔV) Maximum voltage Maximum temperature Maximum time PVD and -ΔV Termination The bq2004E/H samples the voltage at the BAT pin once every 34s. When -ΔV termination is selected, if VCELL is lower than any previously measured value by 12mV ±4mV (6mV/cell), fast charge is terminated. When PVD termination is selected, if VCELL is lower than any previously measured value by 6mV ±2mV (3mV/cell), fast charge is terminated. The PVD and -ΔV tests are valid in the range 0.4 ∗ VCC < VCELL < 0.8 ∗ VCC. 4 bq2004E/H BD200401.eps Timing Control OSC Display Control Charge Control State Machine Discharge Control MOD Control TCO Check LTF Check A/D EDV Check MCV Check DIS MOD INH VCC VSS BAT SNS TS TM1 TM2 TCO LED1 DCMD DVEN VTS - VSNS VBAT - VSNS LED2 DSEL PWR Control Figure 2. Block Diagram 5 VSEL Input Voltage Termination Low Disabled Float -ΔV High PVD Voltage Sampling Each sample is an average of voltage measurements. The IC takes 32 measurements in PVD mode and 16 measurements in -ΔV mode. The resulting sample periods (9.17ms and 18.18ms, respectively) filter out harmonics centered around 55Hz and 109Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%. Temperature and Voltage Termination Hold-off A hold-off period occurs at the start of fast charging. During the hold-off period, -ΔV and ΔT/Δt termination are disabled. The MOD pin is enabled at a duty cycle of 260μs active for every 1820μs inactive. This modulation results in an average rate 1/8th that of the fast charge rate. This avoids premature termination on the voltage spikes sometimes produced by older batteries when fast-charge current is first applied. Maximum voltage and maximum temperature terminations are not affected by the hold-off period. ΔT/Δt Termination The bq2004E/H samples at the voltage at the TS pin every 34s, and compares it to the value measured two samples earlier. If VTEMP has fallen 16mV ±4mV or more, fast charge is terminated. The ΔT/Δt termination test is valid only when VTCO < VTEMP < VLTF. Temperature Sampling Each sample is an average of 16 voltage measurements. The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%. Maximum Voltage, Temperature, and Time Anytime VCELL rises above VMCV, the LEDs go off and current flow into the battery ceases immediately. If VCELL then falls back below VMCV before tMCV = 1.5s ±0.5s, the chip transitions to the Charge Complete state (maximum voltage termination). If VCELL remains above VMCV at the expiration of tMCV, the bq2004E/H transitions to the Battery Absent state (battery removal). See Figure 3. Maximum temperature termination occurs anytime VTEMP falls below the temperature cutoff threshold VTCO. Charge will also be terminated if VTEMP rises above the low temperature fault threshold, VLTF, after fast charge begins. Corresponding Fast-Charge Rate TM1 TM2 Typical Fast-Charge Safety Time (min) Typical PVD, -ΔV Hold-Off Time (s) Top-Off Rate Pulse- Trickle Rate Pulse- Trickle Period (Hz) 2004E 2004H 2004E 2004H 2004E 2004H 2004E 2004H 2004E 2004H C/4 C/8 Low Low 325 650 137 273 Disabled Disabled Disabled C/2 C/4 Float Low 154 325 546 546 Disabled C/512 15 30 1C C/2 High Low 77 154 273 546 Disabled C/512 7.5 15 2C 1C Low Float 39 77 137 273 Disabled C/512 3.75 7.5 4C 2C Float Float 19 39 68 137 Disabled C/512 1.88 3.75 C/2 C/4 High Float 154 325 546 546 C/16 C/32 C/512 15 30 1C C/2 Low High 77 154 273 546 C/8 C/16 C/512 7.5 15 2C 1C Float High 39 77 137 273 C/4 C/18 C/512 3.75 7.5 4C 2C High High 19 39 68 137 C/2 C/4 C/512 1.88 3.75 Note: Typical conditions = 25°C, VCC = 5.0V. Table 1. Fast Charge Safety Time/Hold-Off/Top-Off Table bq2004E/H 6 bq2004E/H Mode 1 bq2004E Charge Action State LED1 LED2 DSEL = VSS Battery absent Low Low Fast charge pending or a discharge-before-charge in progress High High Fast charging Low High Fast charge complete, top-off, and/or trickle High Low Mode 1 bq2004H Charge Action State LED1 LED2 DSEL = VSS Battery absent Low Low Discharge-before-charge in progress High High Fast charge pending Low 1 8 second high 1 8 second low Fast charging Low High Fast charge complete, top-off, and/or trickle High Low Mode 2 bq2004E Charge Action State (See note) LED1 LED2 DSEL = Floating Battery absent Low Low Fast charge pending or discharge-before-charge in progress High High Fast charging Low High Fast charge complete, top-off, and/or trickle High Low Mode 2 bq2004H Charge Action State (See note) LED1 LED2 DSEL = Floating Battery absent Low Low Discharge-before-charge in progress High High Fast charge pending Low 1 8 second high 1 8 second low Fast charging Low High Fast charge complete, top-off, and/or trickle High Low Mode 3 bq2004E/H Charge Action State LED1 LED2 DSEL = VCC Battery absent Low Low Fast charge pending or discharge-before-charge in progress Low 1 8 second high 1 8 second low Fast charging Low High Fast charge complete, top-off, and/or trickle High Low Note: Pulse trickle is inhibited in Mode 2. Table 2. bq2004E/H LED Output Summary Maximum charge time is configured using the TM pin. Time settings are available for corresponding charge rates of C/4, C/2, 1C, and 2C. Maximum time-out termination is enforced on the fast-charge phase, then reset, and enforced again on the top-off phase, if selected. There is no time limit on the trickle-charge phase. Top-off Charge An optional top-off charge phase may be selected to follow fast charge termination for the C/2 through 4C rates. This phase may be necessary on NiMH or other battery chemistries that have a tendency to terminate charge prior to reaching full capacity. With top-off enabled, charging continues at a reduced rate after fast-charge termination for a period of time equal to 0.235∗ the fast-charge safety time (See Table 1.) During top-off, the MOD pin is enabled at a duty cycle of 260μs active for every 1820μs inactive. This modulation results in an average rate 1/8th that of the fast charge rate. Maximum voltage, time, and temperature are the only termination methods enabled during topoff. Pulse-Trickle Charge Pulse-trickle charging may be configured to follow the fast charge and optional top-off charge phases to compensate for self-discharge of the battery while it is idle in the charger. In the pulse-trickle mode, MOD is active for 260μs of a period specified by the settings of TM1 and TM2. See Table 1. The resulting trickle-charge rate is C/512. Both pulse trickle and top-off may be disabled by tying TM1 and TM2 to VSS or by selecting Mode 2 in the display. Charge Status Indication Charge status is indicated by the LED1 and LED2 outputs. The state of these outputs in the various charge cycle phases is given in Table 2 and illustrated in Figure 3. In all cases, if VCELL exceeds the voltage at the MCV pin, both LED1 and LED2 outputs are held low regardless of other conditions. Both can be used to directly drive an LED. Charge Current Control The bq2004E/H controls charge current through the MOD output pin. The current control circuitry is designed to support implementation of a constant-current switching regulator or to gate an externally regulated current source. When used in switch mode configuration, the nominal regulated current is: IREG = 0.225V/RSNS Charge current is monitored at the SNS input by the voltage drop across a sense resistor, RSNS, between the low side of the battery pack and ground. RSNS is sized to provide the desired fast charge current. If the voltage at the SNS pin is less than VSNSLO, the MOD output is switched high to pass charge current to the battery. When the SNS voltage is greater than VSNSHI, the MOD output is switched low—shutting off charging current to the battery. VSNSLO = 0.04 ∗ VCC ± 25mV VSNSHI = 0.05 ∗ VCC ± 25mV When used to gate an externally regulated current source, the SNS pin is connected to VSS, and no sense resisitor is required. 7 bq2004E/H 8 Charge Pending DCMD Tied to Ground? Falling Edge on DCMD Discharge- Before-Charge Top-Off and Pulse-Trickle Charge Pulse Trickle Charge Pulse Trickle Charge Pulse Trickle Charge Top-Off Charge Fast Charge Battery Voltage? Battery Temperature? Top-Off Selected? New Charge Cycle Started by Any One of: VCC Rising to Valid Level Battery Replacement (VCELL Falling through VMCV) Inhibit (INH) Released VEDV < VCELL < VMCV and VHTF < VTEMP < VLTF VHTF < VTEMP < VLTF VEDV < VCELL < VMCV VTEMP > VLTF or VTEMP < VHTF VCELL < VEDV VCELL < VEDV Yes Yes No No t > tMCV > VMCV VCELL > VMCV VCELL > VCELL VMCV > VCELL VMCV > VCELL VMCV VCELL < VMCV Charge Complete Battery Absent or 0.235 Maximum Time Out VTEMP < VTCO SD2004EH.eps > VCELL VMCV - V or T/ t or VTEMP < VTCO or Maximum Time Out Figure 3. Charge Algorithm State Diagram bq2004E/H 9 Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit Notes VCC VCC relative to VSS -0.3 +7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 +7.0 V TOPR Operating ambient temperature -20 +70 °C Commercial TSTG Storage temperature -55 +125 °C TSOLDER Soldering temperature - +260 °C 10 sec max. TBIAS Temperature under bias -40 +85 °C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Thresholds (TA = TOPR; VCC ±10%) Symbol Parameter Rating Tolerance Unit Notes VSNSHI High threshold at SNS resulting in MOD = Low 0.05 * VCC ±0.025 V VSNSLO Low threshold at SNS resulting in MOD = High 0.04 * VCC ±0.025 V VLTF Low-temperature fault 0.4 * VCC ±0.030 V VTEMP ≥ VLTF inhibits/ terminates charge VHTF High-temperature fault (1/3 * VLTF) + (2/3 * VTCO) ±0.030 V VTEMP ≤ VHTF inhibits charge VEDV End-of-discharge voltage 0.4 * VCC ±0.030 V VCELL < VEDV inhibits fast charge VMCV Maximum cell voltage 0.8 * VCC ±0.030 V VCELL > VMCV inhibits/ terminates charge VTHERM TS input change forΔT/Δt detection -16 ±4 mV VCC = 5V, TA = 25°C -ΔV BAT input change for -ΔV detection -12 ±4 mV VCC = 5V, TA = 25°C PVD BAT input change for PVD detection -6 ±2 mV VCC = 5V, TA = 25°C bq2004E/H 10 Recommended DC Operating Conditions (TA = TOPR) Symbol Condition Minimum Typical Maximum Unit Notes VCC Supply voltage 4.5 5.0 5.5 V VBAT Battery input 0 - VCC V VCELL BAT voltage potential 0 - VCC V VBAT - VSNS VTS Thermistor input 0 - VCC V VTEMP TS voltage potential 0 - VCC V VTS - VSNS VTCO Temperature cutoff 0.2 * VCC - 0.4 * VCC V Valid ΔT/Δt range VIH Logic input high 2.0 - - V DCMD, INH Logic input high VCC - 0.3 - - V TM1, TM2, DSEL, VSEL VIL Logic input low - - 0.8 V DCMD, INH Logic input low - - 0.3 V TM1, TM2, DSEL, VSEL VOH Logic output high VCC - 0.8 - - V DIS, MOD, LED1, LED2, IOH ≤ -10mA VOL Logic output low - - 0.8 V DIS, MOD, LED1, LED2, IOL ≤ 10mA ICC Supply current - 1 3 mA Outputs unloaded ISB Standby current - - 1 μA INH = VIL IOH DIS, LED1, LED2,MODsource -10 - - mA @VOH = VCC - 0.8V IOL DIS, LED1, LED2, MOD sink 10 - - mA @VOL = VSS + 0.8V IL Input leakage - - ±1 μA INH, BAT, V = VSS to VCC Input leakage 50 - 400 μA DCMD, V = VSS to VCC IIL Logic input low source - - 70 μA TM1, TM2, DSEL, VSEL, V = VSS to VSS + 0.3V IIH Logic input high source -70 - - μA TM1, TM2, DSEL, VSEL, V = VCC - 0.3V to VCC IIZ Tri-state -2 - 2 μA TM1, TM2, DSEL, and VSEL should be left disconnected (floating) for Z logic input state Note: All voltages relative to VSS except as noted. bq2004E/H 11 Impedance Symbol Parameter Minimum Typical Maximum Unit RBAT Battery input impedance 50 - - MΩ RTS TS input impedance 50 - - MΩ RTCO TCO input impedance 50 - - MΩ RSNS SNS input impedance 50 - - MΩ Timing (TA = 0 to +70°C; VCC ±10%) Symbol Parameter Minimum Typical Maximum Unit Notes tPW Pulse width for DCMD and INH pulse command 1 - - μs Pulse start for charge or discharge before charge dFCV Time base variation -16 - 16 % VCC = 4.75V to 5.25V fREG MOD output regulation frequency - - 300 kHz tMCV Maximum voltage termination time limit 1 - 2 s Time limit to distinguish battery removed from charge complete. Note: Typical is at TA = 25°C, VCC = 5.0V. bq2004E/H 12 bq2004E/H 16-Pin DIP Narrow (PN) 16-Pin PN (0.300" DIP) Dimension Inches Millimeters Min. Max. Min. Max. A 0.160 0.180 4.06 4.57 A1 0.015 0.040 0.38 1.02 B 0.015 0.022 0.38 0.56 B1 0.055 0.065 1.40 1.65 C 0.008 0.013 0.20 0.33 D 0.740 0.770 18.80 19.56 E 0.300 0.325 7.62 8.26 E1 0.230 0.280 5.84 7.11 e 0.300 0.370 7.62 9.40 G 0.090 0.110 2.29 2.79 L 0.115 0.150 2.92 3.81 S 0.020 0.040 0.51 1.02 13 bq2004E/H 16-Pin SOIC Narrow (SN) A A1 .004 C B e D E H L 16-Pin SN (0.150" SOIC) Dimension Inches Millimeters Min. Max. Min. Max. A 0.060 0.070 1.52 1.78 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.18 0.25 D 0.385 0.400 9.78 10.16 E 0.150 0.160 3.81 4.06 e 0.045 0.055 1.14 1.40 H 0.225 0.245 5.72 6.22 L 0.015 0.035 0.38 0.89 14 bq2004E/H Data Sheet Revision History Change No. Page No. Description Nature of Change 1 All Combined bq2004E and bq2004H, revised and expanded format of this data sheet Clarification 2 7 Separated bq2004E and bq2004H in Table 2, LED Output Summary Clarification 3 5 Description of charge-pending state Clarification 4 Note: Change 1 = Oct. 1997 B changes from Sept. 1996 (bq2004E), Feb. 1997 (bq2004H). Change 2 = Feb. 1998 C changes from Oct. 1997 B. Change 3 = Dec. 1998 D changes from Feb. 1998 C. Change 4 = June 1999 E changes from Dec. 1998 D. 5 9 Corrected VSNSLO tolerance Was: ±0.010 Is: ±0.025 Change 5 = Apr. 2005 F changes from June 1999 E. 15 bq2004E/H Ordering Information bq2004 Package Option: PN = 16-pin narrow plastic DIP SN = 16-pin narrow SOIC Device: E = bq2004E Fast-Charge IC H= bq2004H Fast-Charge IC TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant BQ2004ESNTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 BQ2004HSNTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ2004ESNTR SOIC D 16 2500 367.0 367.0 38.0 BQ2004HSNTR SOIC D 16 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated TSV6390, TSV6390A, TSV6391, TSV6391A Micropower (60 μA), wide bandwidth (2.4 MHz) CMOS op-amps Features ■ Low offset voltage: 500 μV max (A version) ■ Low power consumption: 60 μA typ at 5 V ■ Low supply voltage: 1.5 V – 5.5 V ■ Gain bandwidth product: 2.4 MHz typical ■ Stable in gain configuration (-3 or +4) ■ Low power shutdown mode: 5 nA typical ■ High output current: 63 mA at VCC= 5 V ■ Low input bias current: 1 pA typical ■ Rail-to-rail input and output ■ Extended temperature range: -40°C to +125°C ■ 4 kV human body model Applications ■ Battery-powered applications ■ Portable devices ■ Signal conditioning ■ Active filtering ■ Medical instrumentation Description The TSV6390 and TSV6391 devices are single operational amplifiers offering low voltage, low power operation and rail-to-rail input and output. With a very low input bias current and low offset voltage (500 μV maximum for the A version), the TSV6390 and TSV6391 are ideal for applications requiring precision. The devices can operate at power supplies ranging from 1.5 to 5.5 V, and are therefore ideal for battery-powered devices, extending battery life. When used with a gain (above -3 or +4), these products feature an excellent speed/power consumption ratio, offering a 2.4 MHz gain bandwidth product while consuming only 60 μA at a 5 V supply voltage. The TSV6390 comes with a shutdown function. Both the TSV6390 and TSV6391 have a high tolerance to ESD, sustaining 4 kV for the human body model. Additionally, they are offered in micropackages, SC70-6 and SOT23-6 for the TSV6390 and SC70-5 and SOT23-5 for the TSV6391. They are guaranteed for industrial temperature ranges from -40° C to +125° C. All these features combined make the TSV6390 and TSV6391 ideal for sensor interfaces, battery-supplied and portable applications, as well as active filtering. TSV6390ICT/ILT TSV6391ICT/ILT SC70-6/SOT23-6 SC70-5/SOT23-5 VCCIn+ In- Out 1 2 3 6 4 +_ 5 SHDN VCC+ VCCIn+ In- Out 1 2 3 5 4 +_ VCC+ www.st.com Contents TSV6390, TSV6390A, TSV6391, TSV6391A 2/22 Doc ID 17118 Rev 1 Contents 1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Shutdown function (TSV6390) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 Optimization of DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Driving resistive and capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 PCB layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.8 Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 SOT23-5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 SOT23-6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 SC70-5 (or SOT323-5) package mechanical data . . . . . . . . . . . . . . . . . . 17 4.4 SC70-6 (or SOT323-6) package mechanical data . . . . . . . . . . . . . . . . . . 18 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TSV6390, TSV6390A, TSV6391, TSV6391A Absolute maximum ratings and operating conditions Doc ID 17118 Rev 1 3/22 1 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings (AMR) Symbol Parameter Value Unit VCC Supply voltage(1) 1. All voltage values, except differential voltages, are with respect to network ground terminal. 6 V Vid Differential input voltage (2) 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. ±VCC V Vin Input voltage (3) 3. VCC-Vin must not exceed 6 V, Vin must not exceed 6 V. VCC- -0.2 to VCC+ +0.2 V Iin Input current (4) 4. Input current must be limited by a resistor in series with the inputs. 10 mA SHDN Shutdown voltage(3) VCC- -0.2 to VCC+ +0.2 V Tstg Storage temperature -65 to +150 °C Rthja Thermal resistance junction to ambient(5)(6) SC70-5 SOT23-5 SOT23-6 SC70-6 5. Short-circuits can cause excessive heating and destructive dissipation. 6. Rth are typical values. 205 250 240 232 °C/W Tj Maximum junction temperature 150 °C ESD HBM: human body model(7) 7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating. 4 kV MM: machine model(8) 8. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating. 300 V CDM: charged device model(9) 9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to the ground. 1.5 kV Latch-up immunity 200 mA Table 2. Operating conditions Symbol Parameter Value Unit VCC Supply voltage 1.5 to 5.5 V Vicm Common mode input voltage range VCC- -0.1 to VCC+ +0.1 V Toper Operating free air temperature range -40 to +125 °C Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A 4/22 Doc ID 17118 Rev 1 2 Electrical characteristics Table 3. Electrical characteristics at VCC+ = +1.8 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C and RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSV6390-TSV6391 TSV6390A-TSV6391A 3 0.5 mV Tmin < Top < Tmax TSV6390-TSV6391 TSV6390A-TSV6391A 4.5 2 DVio Input offset voltage drift 2 μV/°C Iio Input offset current (1) (Vout = VCC/2) 1 10 pA Tmin < Top < Tmax 1 100 Iib Input bias current(1) (Vout = VCC/2) 1 10 pA Tmin < Top < Tmax 1 100 CMR Common mode rejection ratio 20 log (ΔVic/ΔVio) 0 V to 1.8 V, Vout = 0.9 V 53 74 dB Tmin < Top < Tmax 51 Avd Large signal voltage gain RL= 10 kΩ, Vout = 0.5 V to 1.3 V 85 95 dB Tmin < Top < Tmax 80 VOH High level output voltage RL = 10 kΩ 35 5 mV Tmin < Top < Tmax 50 VOL Low level output voltage RL = 10 kΩ 4 35 mV Tmin < Top < Tmax 50 Iout Isink Vout = 1.8 V 6 12 mA Tmin < Top < Tmax 4 Isource Vout = 0 V 6 10 mA Tmin < Top < Tmax 4 ICC Supply current SHDN = VCC No load, Vout = VCC/2 40 50 60 μA Tmin < Top < Tmax 62 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2 MHz Gain Minimum gain for stability Phase margin = 60°, Rf = 10 kΩ, RL = 10 kΩ, CL = 20 pF +4 -3 V/V SR Slew rate RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to 1.3 V 0.7 V/μs en Equivalent input noise voltage f = 1 kHz f = 10 kHz 60 33 1. Guaranteed by design. nV Hz ----------- TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics Doc ID 17118 Rev 1 5/22 Table 4. Shutdown characteristics VCC = 1.8 V (TSV6390) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance ICC Supply current in shutdown mode (all operators) SHDN = VCC- 2.5 50 nA Tmin < Top < 85° C 200 nA Tmin < Top < 125° C 1.5 μA ton Amplifier turn-on time RL = 2 kΩ, Vout = VCC- to VCC - + 0.2 V 300 ns toff Amplifier turn-off time RL = 2 kΩ, Vout = VCC+ - 0.5 V to VCC+ - 0.7 V 20 ns VIH SHDN logic high 1.3 V VIL SHDN logic low 0.5 V IIH SHDN current high SHDN = VCC+ 10 pA IIL SHDN current low SHDN = VCC- 10 pA IOLeak Output leakage in shutdown mode SHDN = VCC- 50 pA Tmin < Top < Tmax 1 nA Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A 6/22 Doc ID 17118 Rev 1 Table 5. VCC+ = +3.3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSV6390-TSV6391 TSV6390A-TSV6391A 3 0.5 mV Tmin < Top < Tmax TSV6390-TSV6391 TSV6390A-TSV6391A 4.5 2 DVio Input offset voltage drift 2 μV/°C Iio Input offset current(1) 1 10 pA Tmin < Top < Tmax 1 100 Iib Input bias current(1) 1 10 pA Tmin < Top < Tmax 1 100 CMR Common mode rejection ratio 20 log (ΔVic/ΔVio) 0 V to 3.3 V, Vout = 1.65 V 57 79 dB Tmin < Top < Tmax 53 Avd Large signal voltage gain RL = 10 kΩ, Vout = 0.5 V to 2.8 V 88 98 dB Tmin < Top < Tmax 83 VOH High level output voltage RL = 10 kΩ 35 6 mV Tmin. < Top < Tmax 50 VOL Low level output voltage RL = 10 kΩ 7 35 mV Tmin < Top < Tmax 50 Iout Isink Vout = 3.3 V 23 45 mA Tmin < Top < Tmax 20 42 Isource Vout = 0 V 23 38 mA Tmin < Top < Tmax 20 ICC Supply current SHDN = VCC No load, Vout= VCC/2 43 55 64 μA Tmin < Top < Tmax 66 μA AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2.2 MHz Gain Minimum gain for stability Phase margin = 60°, Rf = 10 kΩ, RL = 10 kΩ, CL = 20 pF, +4 -3 V/V SR Slew rate RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to 2.8 V 0.9 V/μs en Equivalent input noise voltage f = 1 kHz 65 1. Guaranteed by design. nV Hz ----------- TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics Doc ID 17118 Rev 1 7/22 Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C and RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSV6390-TSV6391 TSV6390A-TSV6391A 3 0.5 mV Tmin < Top < Tmax TSV6390-TSV6391 TSV6390A-TSV6391A 4.5 2 mV DVio Input offset voltage drift 2 μV/°C Iio Input offset current(1) (Vout = VCC/2) 1 10 pA Tmin < Top < Tmax 1 100 Iib Input bias current(1) (Vout = VCC/2) 1 10 pA Tmin < Top < Tmax 1 100 CMR Common mode rejection ratio 20 log (ΔVic/ΔVio) 0 V to 5 V, Vout = 2.5 V 60 80 dB Tmin < Top < Tmax 55 SVR Supply voltage rejection ratio 20 log (ΔVCC/ΔVio) VCC = 1.8 to 5 V 75 93 dB Tmin < Top < Tmax 73 Avd Large signal voltage gain RL= 10 kΩ, Vout= 0.5 V to 4.5 V 89 98 dB Tmin < Top < Tmax 84 VOH High level output voltage RL = 10 kΩ 35 7 mV Tmin < Top < Tmax 50 VOL Low level output voltage RL = 10 kΩ 6 35 mV Tmin < Top < Tmax 50 Iout Isink Vout = 5 V 40 65 mA Tmin < Top < Tmax 35 Isource Vout = 0 V 40 72 mA Tmin < Top < Tmax 35 ICC Supply current SHDN = VCC No load, Vout=VCC/2 50 60 69 μA Tmin < Top < Tmax 72 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2.4 MHz Gain Minimum gain for stability Phase margin = 60°, Rf = 10 kΩ, RL = 10 kΩ, CL = 20 pF, +4 -3 V/V SR Slew rate RL = 10 kΩ, CL = 100 pF 1.1 V/μs Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A 8/22 Doc ID 17118 Rev 1 en Equivalent input noise voltage f = 1 kHz f = 10 kHz 60 33 THD+N Total harmonic distortion + noise Av = -10, fin = 1 kHz, R= 100 kΩ, Vicm = Vcc/2, Vin = 40 mVpp 0.11 % 1. Guaranteed by design. Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C and RL connected to VCC/2 (unless otherwise specified) (continued) Symbol Parameter Conditions Min. Typ. Max. Unit nV Hz ----------- Table 7. Shutdown characteristics VCC = 5 V (TSV6390) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance ICC Supply current in shutdown mode (all operators) SHDN = VCC- 5 50 nA Tmin < Top < 85° C 200 nA Tmin < Top < 125° C 1.5 μA ton Amplifier turn-on time RL = 2 kΩ, Vout = VCC- to VCC - + 0.2 V 300 ns toff Amplifier turn-off time RL = 2 Ω, Vout = VCC+ - 0.5 V to VCC+ - 0.7 V 30 ns VIH SHDN logic high 4.5 V VIL SHDN logic low 0.5 V IIH SHDN current high SHDN = VCC+ 10 pA IIL SHDN current low SHDN = VCC- 10 pA IOLeak Output leakage in shutdown mode SHDN = VCC- 50 pA Tmin < Top < Tmax 1 nA TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics Doc ID 17118 Rev 1 9/22 Figure 1. Supply current vs. supply voltage at Vicm = VCC/2 Figure 2. Output current vs. output voltage at VCC = 1.5 V Figure 3. Output current vs. output voltage at VCC = 5 V Figure 4. Peaking at closed loop gain = -10 10000 100000 1000000 0 5 10 15 20 VCC=5V VCC=1.5V Closed loop gain = -10 T=25 C,CLoad=100pF, Vicm=VCC/2, RLoad=2.2kΩ for Iout giving minimum stability on a typical part Gain (dB) Frequency (Hz) Figure 5. Peaking at closed loop gain = -3 at VCC = 1.5 V Figure 6. Peaking at closed loop gain = -3 at VCC = 5 V 10000 100000 1000000 0 2 4 6 8 10 12 14 RLoad=100kΩ RLoad T=25 C, V =2.2kΩ icm=VCC/2 ACL=-3, VCC=1.5V CLoad=33pF RLoad= 100kΩ connected to VCC/2 RLoad= 2.2kΩ for Iout giving minimum stability on a typical part Gain (dB) Frequency (Hz) 10000 100000 1000000 0 2 4 6 8 10 12 14 RLoad=2.2kΩ T=25 C, Vicm=VCC/2 ACL=-3, VCC=5V CLoad=33pF RLoad=100kΩ RLoad= 100kΩ connected to VCC/2 RLoad= 2.2kΩ for Iout giving minimum stability on a typical part Gain (dB) Frequency (Hz) Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A 10/22 Doc ID 17118 Rev 1 Figure 7. Positive slew rate vs. supply voltage Figure 8. Negative slew rate vs. supply voltage Figure 9. Distortion + noise vs. output voltage at VCC = 1.8 V Figure 10. Distortion + noise vs. output voltage at VCC = 5 V RLoad=2kΩ, CLoad=100pF, ACL=−10 Vin: from 0.5V to VCC+− 0.5V SR calculated from 10% to 90% Vicm=VCC/2 T=25°C T=125°C T=−40°C Slew rate (V/ s) Supply voltage (V) T=25°C RLoad=2kΩ, CLoad=100pF, ACL=−10 Vin: from VCC+−0.5V to 0.5V SR calculated from 10% to 90% Vicm=VCC/2 T=125°C T=−40°C Slew rate (V/ s) Supply voltage (V) Ω Ω THD + N (%) Output voltage (Vrms) Ω Ω THD + N (%) Ouput voltage (Vrms) Figure 11. Slew rate timing Figure 12. Noise vs. frequency at VCC = 5 V Vin Vout RLoad=2kΩ, CLoad=100pF, Vicm=VCC/2, ACL=−10 T=25°C, VCC=5V Amplitude (V) Time (μs) 10 100 1000 10000 10 100 Equivalent Input Voltage Noise (nV/VHz) Vcc=5V Tamb=25 C Vicm=4.5V Vicm=2.5V TSV6390, TSV6390A, TSV6391, TSV6391A Application information Doc ID 17118 Rev 1 11/22 3 Application information 3.1 Operating voltages The TSV6390 and TSV6391 can operate from 1.5 to 5.5 V. Their parameters are fully specified for 1.8, 3.3 and 5 V power supplies. However, the parameters are very stable in the full VCC range and several characterization curves show the TSV639x characteristics at 1.5 V. Additionally, the main specifications are guaranteed in extended temperature ranges from -40° C to +125° C. 3.2 Rail-to-rail input The TSV6390 and TSV6391 are built with two complementary PMOS and NMOS input differential pairs. The devices have a rail-to-rail input, and the input common mode range is extended from VCC- -0.1 V to VCC+ +0.1 V. The transition between the two pairs appears at VCC+ -0.7 V. In the transition region, the performance of CMRR, PSRR, Vio and THD is slightly degraded (as shown in Figure 13 and Figure 14 for Vio vs. Vicm). The devices are guaranteed without phase reversal. 3.3 Rail-to-rail output The operational amplifiers’ output levels can go close to the rails: 35 mV maximum above and below the rail when connected to a 10 kΩ resistive load to VCC/2. 3.4 Shutdown function (TSV6390) The operational amplifier is enabled when the SHDN pin is pulled high. To disable the amplifier, the SHDN must be pulled down to VCC-. When in shutdown mode, the amplifier’s output is in a high impedance state. The SHDN pin must never be left floating, but tied to VCC+ or VCC-. Figure 13. Input offset voltage vs input common mode at VCC = 1.5 V Figure 14. Input offset voltage vs input common mode at VCC = 5 V -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 Input Offset Voltage (mV) Input Common Mode Voltage (V) 0.0 1.0 2.0 3.0 4.0 5.0 -0.4 -0.2 0.0 0.2 0.4 Input Offset Voltage (mV) Input Common Mode Voltage (V) Application information TSV6390, TSV6390A, TSV6391, TSV6391A 12/22 Doc ID 17118 Rev 1 The turn-on and turn-off times are calculated for an output variation of ±200 mV (Figure 15 and Figure 16 show the test configurations). Figure 15. Test configuration for turn-on time (Vout pulled down) Figure 16. Test configuration for turn-off time (Vout pulled down) + VCC GND 2 KΩ + - DUT GND VCC - 0.5 V + VCC GND 2 KΩ + - DUT GND VCC - 0.5 V Figure 17. Turn-on time, VCC = 5 V, Vout pulled down, T = 25° C Figure 18. Turn-off time, VCC= 5 V, Vout pulled down, T = 25° C Shutdown pulse Vout Vcc = 5V T = 25°C Voltage (V) Time( s) Shutdown pulse Vout Vcc = 5V T = 25°C Output voltage (V) Time( s) TSV6390, TSV6390A, TSV6391, TSV6391A Application information Doc ID 17118 Rev 1 13/22 3.5 Optimization of DC and AC parameters These devices use an innovative approach to reduce the spread of the main DC and AC parameters. An internal adjustment achieves a very narrow spread of the current consumption (60 μA typical, min/max at ±17 %). Parameters linked to the current consumption value, such as GBP, SR and AVd, benefit from this narrow dispersion. 3.6 Driving resistive and capacitive loads These products are micropower, low-voltage operational amplifiers optimized to drive rather large resistive loads, above 2 kΩ. For lower resistive loads, the THD level may significantly increase. These operational amplifiers have a relatively low internal compensation capacitor, making them very fast while consuming very little. They are ideal when used in a non-inverting configuration or in an inverting configuration in the following conditions. ● IGainI ≥ 3 in an inverting configuration (CL = 20 pF, RL = 100 kΩ) or IgainI ≥ 10 (CL = 100 pF, RL = 100 kΩ) ● Gain ≥ +4 in a non-inverting configuration (CL = 20 pF, RL = 100 kΩ) or gain ≥ +11 (CL = 100 pF, RL= 100 kΩ) As these operational amplifiers are not unity gain stable, for a low closed-loop gain it is recommended to use the TSV62x (29 μA, 420 kHz) or TSV63x (60 μA, 880 kHz) which are unity gain stable. 3.7 PCB layouts For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins. 3.8 Macromodel An accurate macromodel of the TSV6390 and TSV6391 is available on STMicroelectronics’ web site at www.st.com. This model is a trade-off between accuracy and complexity (that is, time simulation) of the TSV639x operational amplifiers. It emulates the nominal performances of a typical device within the specified operating conditions mentioned in the datasheet. It also helps to validate a design approach and to select the right operational amplifier, but it does not replace on-board measurements. Table 8. Related products Part # Icc (μA) at 5 V GBP (MHz) SR (V/μs) Minimum gain for stability (CLoad = 100 pF) TSV620-1 29 0.42 0.14 1 TSV6290-1 29 1.3 0.5 +11 TSV630-1 60 0.88 0.34 1 TSV6390-1 60 2.4 1.1 +11 Package information TSV6390, TSV6390A, TSV6391, TSV6391A 14/22 Doc ID 17118 Rev 1 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. TSV6390, TSV6390A, TSV6391, TSV6391A Package information Doc ID 17118 Rev 1 15/22 4.1 SOT23-5 package mechanical data Figure 19. SOT23-5L package mechanical drawing Table 9. SOT23-5L package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.90 1.20 1.45 0.035 0.047 0.057 A1 0.15 0.006 A2 0.90 1.05 1.30 0.035 0.041 0.051 B 0.35 0.40 0.50 0.013 0.015 0.019 C 0.09 0.15 0.20 0.003 0.006 0.008 D 2.80 2.90 3.00 0.110 0.114 0.118 D1 1.90 0.075 e 0.95 0.037 E 2.60 2.80 3.00 0.102 0.110 0.118 F 1.50 1.60 1.75 0.059 0.063 0.069 L 0.10 0.35 0.60 0.004 0.013 0.023 K 0° 10° Package information TSV6390, TSV6390A, TSV6391, TSV6391A 16/22 Doc ID 17118 Rev 1 4.2 SOT23-6 package mechanical data Figure 20. SOT23-6L package mechanical drawing Table 10. SOT23-6L package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.90 1.45 0.035 0.057 A1 0.10 0.004 A2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.013 0.019 c 0.09 0.20 0.003 0.008 D 2.80 3.05 0.110 0.120 E 1.50 1.75 0.060 0.069 e 0.95 0.037 H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 ° 0 10° TSV6390, TSV6390A, TSV6391, TSV6391A Package information Doc ID 17118 Rev 1 17/22 4.3 SC70-5 (or SOT323-5) package mechanical data Figure 21. SC70-5 (or SOT323-5) package mechanical drawing Table 11. SC70-5 (or SOT323-5) package mechanical data Ref Dimensions Millimeters Inches Min Typ Max Min Typ Max A 0.80 1.10 0.315 0.043 A1 0.10 0.004 A2 0.80 0.90 1.00 0.315 0.035 0.039 b 0.15 0.30 0.006 0.012 c 0.10 0.22 0.004 0.009 D 1.80 2.00 2.20 0.071 0.079 0.087 E 1.80 2.10 2.40 0.071 0.083 0.094 E1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65 0.025 e1 1.30 0.051 L 0.26 0.36 0.46 0.010 0.014 0.018 < 0° 8° SEATING PLANE GAUGE PLANE DIMENSIONS IN MM SIDE VIEW TOP VIEW COPLANAR LEADS Package information TSV6390, TSV6390A, TSV6391, TSV6391A 18/22 Doc ID 17118 Rev 1 4.4 SC70-6 (or SOT323-6) package mechanical data Figure 22. SC70-6 (or SOT323-6) package mechanical drawing Table 12. SC70-6 (or SOT323-6) package mechanical data Ref Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.80 1.10 0.031 0.043 A1 0.10 0.004 A2 0.80 1.00 0.031 0.039 b 0.15 0.30 0.006 0.012 c 0.10 0.18 0.004 0.007 D 1.80 2.20 0.071 0.086 E 1.15 1.35 0.045 0.053 e 0.65 0.026 HE 1.80 2.40 0.071 0.094 L 0.10 0.40 0.004 0.016 Q1 0.10 0.40 0.004 0.016 TSV6390, TSV6390A, TSV6391, TSV6391A Package information Doc ID 17118 Rev 1 19/22 Figure 23. SC70-6 (or SOT323-6) package footprint Ordering information TSV6390, TSV6390A, TSV6391, TSV6391A 20/22 Doc ID 17118 Rev 1 5 Ordering information Table 13. Order codes Part number Temperature range Package Packing Marking TSV6390ILT -40°C to +125°C SOT23-6 Tape & reel K109 TSV6390ICT SC70-6 K19 TSV6390AILT SOT23-6 K142 TSV6390AICT SC70-6 K42 TSV6391ILT SOT23-5 K108 TSV6391ICT SC70-5 K20 TSV6391AILT SOT23-5 K141 TSV6391AICT SC70-5 K41 TSV6390, TSV6390A, TSV6391, TSV6391A Revision history Doc ID 17118 Rev 1 21/22 6 Revision history Table 14. Document revision history Date Revision Changes 09-Mar-2010 1 Initial release. TSV6390, TSV6390A, TSV6391, TSV6391A 22/22 Doc ID 17118 Rev 1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com General Description The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E +3.0V-powered EIA/TIA-232 and V.28/V.24 communications interface devices feature low power consumption, high data-rate capabilities, and enhanced electrostatic-discharge (ESD) protection. The enhanced ESD structure protects all transmitter outputs and receiver inputs to ±15kV using IEC 1000-4-2 Air-Gap Discharge, ±8kV using IEC 1000-4-2 Contact Discharge (±9kV for MAX3246E), and ±15kV using the Human Body Model. The logic and receiver I/O pins of the MAX3237E are protected to the above standards, while the transmitter output pins are protected to ±15kV using the Human Body Model. A proprietary low-dropout transmitter output stage delivers true RS-232 performance from a +3.0V to +5.5V power supply, using an internal dual charge pump. The charge pump requires only four small 0.1μF capacitors for operation from a +3.3V supply. Each device guarantees operation at data rates of 250kbps while maintaining RS-232 output levels. The MAX3237E guarantees operation at 250kbps in the normal operating mode and 1Mbps in the MegaBaud™ operating mode, while maintaining RS-232- compliant output levels. The MAX3222E/MAX3232E have two receivers and two transmitters. The MAX3222E features a 1μA shutdown mode that reduces power consumption in battery-powered portable systems. The MAX3222E receivers remain active in shutdown mode, allowing monitoring of external devices while consuming only 1μA of supply current. The MAX3222E and MAX3232E are pin, package, and functionally compatible with the industry-standard MAX242 and MAX232, respectively. The MAX3241E/MAX3246E are complete serial ports (three drivers/five receivers) designed for notebook and subnotebook computers. The MAX3237E (five drivers/ three receivers) is ideal for peripheral applications that require fast data transfer. These devices feature a shutdown mode in which all receivers remain active, while consuming only 1μA (MAX3241E/MAX3246E) or 10nA (MAX3237E). The MAX3222E, MAX3232E, and MAX3241E are available in space-saving SO, SSOP, TQFN and TSSOP packages. The MAX3237E is offered in an SSOP package. The MAX3246E is offered in the ultra-small 6 x 6 UCSP™ package. Applications Battery-Powered Equipment Printers Cell Phones Smart Phones Cell-Phone Data Cables xDSL Modems Notebook, Subnotebook, and Palmtop Computers Next-Generation Device Features ♦ For Space-Constrained Applications MAX3228E/MAX3229E: ±15kV ESD-Protected, +2.5V to +5.5V, RS-232 Transceivers in UCSP ♦ For Low-Voltage or Data Cable Applications MAX3380E/MAX3381E: +2.35V to +5.5V, 1μA, 2Tx/2Rx, RS-232 Transceivers with ±15kV ESD-Protected I/O and Logic Pins MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ________________________________________________________________ Maxim Integrated Products 1 19-1298; Rev 10; 1/06 _______________Ordering Information Ordering Information continued at end of data sheet. *Dice are tested at TA = +25°C, DC parameters only. **EP = Exposed paddle. Pin Configurations, Selector Guide, and Typical Operating Circuits appear at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PINPACKAGE PKG CODE MAX3222ECTP 0°C to +70°C 20 Thin QFNEP** (5mm x 5mm) T2055-5 MAX3222ECUP 0°C to +70°C 20 TSSOP — MAX3222ECAP 0°C to +70°C 20 SSOP — MAX3222ECWN 0°C to +70°C 18 Wide SO — MAX3222ECPN 0°C to +70°C 18 Plastic DIP — MAX3222EC/D 0°C to +70°C Dice* — MAX3222EETP -40°C to +85°C 20 Thin QFNEP** (5mm x 5mm) T2055-5 MAX3222EEUP -40°C to +85°C 20 TSSOP — MAX3222EEAP -40°C to +85°C 20 SSOP — MAX3222EEWN -40°C to +85°C 18 Wide SO — MAX3222EEPN -40°C to +85°C 18 Plastic DIP — MAX3232ECAE 0°C to +70°C 16 SSOP — MAX3232ECWE 0°C to +70°C 16 Wide SO — MAX3232ECPE 0°C to +70°C 16 Plastic DIP — MegaBaud and UCSP are trademarks of Maxim Integrated Products, Inc. †Covered by U.S. Patent numbers 4,636,930; 4,679,134; 4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and other patents pending. MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VCC to GND..............................................................-0.3V to +6V V+ to GND (Note 1) ..................................................-0.3V to +7V V- to GND (Note 1) ...................................................+0.3V to -7V V+ + |V-| (Note 1).................................................................+13V Input Voltages T_IN, EN, SHDN, MBAUD to GND ........................-0.3V to +6V R_IN to GND .....................................................................±25V Output Voltages T_OUT to GND...............................................................±13.2V R_OUT, R_OUTB (MAX3241E)................-0.3V to (VCC + 0.3V) Short-Circuit Duration, T_OUT to GND.......................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin SSOP (derate 7.14mW/°C above +70°C) ..........571mW 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .......754.7mW 16-Pin TQFN (derate 20.8mW/°C above +70°C) .....1666.7mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW 18-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW 18-Pin PDIP (derate 11.11mW/°C above +70°C)..........889mW 20-Pin TQFN (derate 21.3mW/°C above +70°C) ........1702mW 20-Pin TSSOP (derate 10.9mW/°C above +70°C) ........879mW 20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW 28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........762mW 28-Pin Wide SO (derate 12.50mW/°C above +70°C).............1W 28-Pin TSSOP (derate 12.8mW/°C above +70°C) ......1026mW 32-Lead Thin QFN (derate 33.3mW/°C above +70°C)..2666mW 6 x 6 UCSP (derate 12.6mW/°C above +70°C).............1010mW Operating Temperature Ranges MAX32_ _EC_ _ ...................................................0°C to +70°C MAX32_ _EE_ _.................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Bump Reflow Temperature (Note 2) Infrared, 15s..................................................................+200°C Vapor Phase, 20s..........................................................+215°C Note 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board-level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed. PARAMETER CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS (VCC = +3.3V or +5V, TA = +25°C) MAX3222E, MAX3232E, MAX3241E, MAX3246E 0.3 1 Supply Current SHDN = VCC, no load MAX3237E 0.5 2.0 mA SHDN = GND 1 10 μA Shutdown Supply Current SHDN = R_IN = GND, T_IN = GND or VCC (MAX3237E) 10 300 nA LOGIC INPUTS Input Logic Low T_IN, EN, SHDN, MBAUD 0.8 V VCC = +3.3V 2.0 Input Logic High T_IN, EN, SHDN, MBAUD VCC = +5.0V 2.4 V Transmitter Input Hysteresis 0.5 V T_IN, EN, SHDN MAX3222E, MAX3232E, MAX3241E, MAX3246E ±0.01 ±1 Input Leakage Current T_IN, SHDN, MBAUD MAX3237E (Note 5) 9 18 μA RECEIVER OUTPUTS Output Leakage Current R_OUT (MAX3222E/MAX3237E/MAX3241E/ MAX3246E), EN = VCC, receivers disabled ±0.05 ±10 μA Output-Voltage Low IOUT = 1.6mA (MAX3222E/MAX3232E/MAX3241E/ MAX3246E), IOUT = 1.0mA (MAX3237E) 0.4 V MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Output-Voltage High IOUT = -1.0mA VCC - 0.6 VCC - 0.1 V RECEIVER INPUTS Input Voltage Range -25 +25 V VCC = +3.3V 0.6 1.1 Input Threshold Low TA = +25°C VCC = +5.0V 0.8 1.5 V VCC = +3.3V 1.5 2.4 Input Threshold High TA = +25°C VCC = +5.0V 2.0 2.4 V Input Hysteresis 0.5 V Input Resistance TA = +25°C 3 5 7 kΩ TRANSMITTER OUTPUTS Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground (Note 6) ±5 ±5.4 V Output Resistance VCC = 0, transmitter output = ±2V 300 50k Ω Output Short-Circuit Current ±60 mA Output Leakage Current V C C = 0 or + 3.0V to + 5.5V , V OU T = ± 12V , tr ansm i tter s d i sab l ed ( M AX 3222E /M AX 3232E /M AX 3241E /M AX 3246E ) ±25 μA MOUSE DRIVABILITY (MAX3241E) Transmitter Output Voltage T1IN = T2IN = GND, T3IN = VCC, T3OUT loaded with 3kΩ to GND, T1OUT and T2OUT loaded with 2.5mA each ±5 V ESD PROTECTION Human Body Model ±15 IEC 1000-4-2 Air-Gap Discharge (except MAX3237E) ±15 IEC 1000-4-2 Contact Discharge (except MAX3237E) ±8 R_IN, T_OUT IEC 1000-4-2 Contact Discharge (MAX3246E only) ±9 kV Human Body Model ±15 IEC1000-4-2 Air-Gap Discharge ±15 T_IN, R_IN, R_OUT, EN, SHDN, MBAUD MAX3237E IEC1000-4-2 Contact Discharge ±8 kV MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 4 _______________________________________________________________________________________ TIMING CHARACTERISTICS—MAX3237E (VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) Note 3:MAX3222E/MAX3232E/MAX3241E: C1–C4 = 0.1μF tested at +3.3V ±10%; C1 = 0.047μF, C2, C3, C4 = 0.33μF tested at +5.0V ±10%. MAX3237E: C1–C4 = 0.1μF tested at +3.3V ±5%, C1–C4 = 0.22μF tested at +3.3V ±10%; C1 = 0.047μF, C2, C3, C4 = 0.33μF tested at +5.0V ±10%. MAX3246E; C1-C4 = 0.22μF tested at +3.3V ±10%; C1 = 0.22μF, C2, C3, C4 = 0.54μF tested at 5.0V ±10%. Note 4: MAX3246E devices are production tested at +25°C. All limits are guaranteed by design over the operating temperature range. Note 5: The MAX3237E logic inputs have an active positive feedback resistor. The input current goes to zero when the inputs are at the supply rails. Note 6: MAX3241EEUI is specified at TA = +25°C. Note 7: Transmitter skew is measured at the transmitter zero crosspoints. PARAMETER CONDITIONS MIN TYP MAX UNITS RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = GND 250 VCC = +3.0V to +4.5V, RL = 3kΩ, CL = 250pF, one transmitter switching, MBAUD = VCC Maximum Data Rate 1000 VCC = +4.5V to +5.5V, RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = VCC 1000 kbps tPHL 0.15 Receiver Propagation Delay R_IN to R_OUT, CL = 150pF tPLH 0.15 μs Receiver Output Enable Time Normal operation 2.6 μs Receiver Output Disable Time Normal operation 2.4 μs | tPHL - tPLH |, MBAUD = GND Transmitter Skew (Note 7) | tPHL - tPLH |, MBAUD = VCC 100 ns Receiver Skew | tPHL - tPLH | 50 ns CL = 150pF MBAUD = GND 6 30 to 1000pF MBAUD = VCC 24 150 VCC = +3.3V, RL = 3kΩ to 7kΩ, +3.0V to -3.0V or -3.0V to +3.0V, TA = +25°C CL = 150pF to 2500pF, MBAUD = GND 4 30 Transition-Region Slew Rate V/μs TIMING CHARACTERISTICS—MAX3222E/MAX3232E/MAX3241E/MAX3246E (VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TA = TMIN to TMAX (MAX3222E/MAX3232E/ MAX3241E) (Note 6) 250 Maximum Data Rate RL = 3kΩ, CL = 1000pF, one transmitter switching TA = + 25°C ( M AX 3246E ) 250 kbps tPHL 0.15 Receiver Propagation Delay tPLH Receiver input to receiver output, CL = 150pF 0.15 μs Receiver Output Enable Time Normal operation (except MAX3232E) 200 ns Receiver Output Disable Time Normal operation (except MAX3232E) 200 ns Transmitter Skew |tPHL - tPLH| (Note 7) 100 ns Receiver Skew |tPHL - tPLH| 50 ns Transition-Region Slew Rate V C C = + 3.3V , TA = + 25°C , RL = 3kΩ to 7kΩ , m easur ed fr om + 3.0V to - 3.0V or - 3.0V to + 3.0V , one tr ansm i tter sw i tchi ng CL = 150pF to 1000pF 6 30 V/μs MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers _______________________________________________________________________________________ 5 -6 -4 -2 0 2 4 6 0 MAX3237E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3237E toc07 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 500 1000 1500 2000 2500 3000 FOR DATA RATES UP TO 250kbps 1 TRANSMITTER AT 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ + CL 5 3 1 -1 -3 -5 VOUT+ VOUT- -6 -2 -4 2 0 4 6 -5 -3 1 -1 3 5 0 500 1000 1500 2000 2500 3000 MAX3246E toc07A LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) VOUTVOUT+ FOR DATA RATES UP TO 250kbps 1 TRANSMITTER 250kbps 4 TRANSMITTERS 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ + CL MAX3237E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3237E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3237E toc08 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 500 1000 1500 2000 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD, EACH OUTPUT 2Mbps 1.5Mbps 1Mbps 2Mbps 1Mbps 1.5Mbps __________________________________________Typical Operating Characteristics (VCC = +3.3V, 250kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ and CL, TA = +25°C, unless otherwise noted.) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 1000 2000 3000 4000 5000 MAX3241E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3237E to04 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1 TRANSMITTER AT 250kbps 2 TRANSMITTERS AT 15.6kbps VOUT+ VOUT- 0 30 20 10 40 50 60 0 1000 2000 3000 4000 5000 MAX3241E OPERATING SUPPLY CURRENT vs. LOAD CAPACITANCE MAX3237E toc06 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 250kbps 120kbps 20kbps 1 TRANSMITTER AT 250kbps 2 TRANSMITTERS AT 15.6kbps 0 4 2 8 6 12 10 14 0 1000 2000 3000 4000 5000 MAX3241E SLEW RATE vs. LOAD CAPACITANCE MAX3237E toc05 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 1000 2000 3000 4000 5000 MAX3222E/MAX3232E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3237E toc01 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) T1 TRANSMITTING AT 250kbps T2 TRANSMITTING AT 15.6kbps VOUT+ VOUT- 0 6 2 4 10 8 14 12 16 0 1000 2000 3000 4000 5000 MAX3222E/MAX3232E SLEW RATE vs. LOAD CAPACITANCE MAX3237E toc02 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) +SLEW FOR DATA RATES UP TO 250kbps -SLEW 0 25 20 15 5 10 35 30 40 45 0 1000 2000 3000 4000 5000 MAX3222E/MAX3232E OPERATING SUPPLY CURRENT vs. LOAD CAPACITANCE MAX3237E toc03 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 250kbps 120kbps 20kbps T1 TRANSMITTING AT 250kbps T2 TRANSMITTING AT 15.6kbps MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 6 _______________________________________________________________________________________ Typical Operating Characteristics (continued) (VCC = +3.3V, 250kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ and CL, TA = +25°C, unless otherwise noted.) 0 20 60 40 80 100 0 MAX3237E TRANSMITTER SKEW vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3237E toc12 LOAD CAPACITANCE (pF) 500 1000 1500 2000 TRANSMITTER SKEW (ns) |tPLH - tPHL| 1 TRANSMITTER AT 500kbps 4 TRANSMITTERS AT 1/16 DATA RATE ALL TRANSMITTERS LOADED WITH 3kΩ + CL -6 -2 -4 2 0 4 6 -3 -5 1 -1 3 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 MAX3237E toc13 SUPPLY VOLTAGE (V) TRANSMITTER OUTPUT VOLTAGE (V) VOUTVOUT+ 1 TRANSMITTER AT 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ +1000pF MAX3237E TRANSMITTER OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (MBAUD = GND) 0 10 20 30 40 50 2.0 MAX3237E SUPPLY CURRENT vs. SUPPLY VOLTAGE (MBAUD = GND) MAX3237E toc14 SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 2.5 3.0 3.5 4.0 4.5 5.0 1 TRANSMITTER AT 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ AND 1000pF MAX3246E TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3237E toc15 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 2000 3000 4000 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 -6 0 5000 1 TRANSMITTER AT 250kbps 2 TRANSMITTERS AT 15.6kbps VOUTVOUT+ 4 6 8 10 12 14 16 0 MAX3246E SLEW RATE vs. LOAD CAPACITANCE MAX3237E toc16 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 2000 3000 4000 5000 SR+ SR- 0 10 20 30 40 50 60 0 MAX3246E OPERATING SUPPLY CURRENT vs. LOAD CAPACITANCE MAX3237E toc17 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 2000 3000 4000 5000 1 TRANSMITTER AT 250kbps 2 TRANSMITTERS AT 15.6kbps 55 45 35 25 15 5 250kbps 120kbps 20kbps 0 2 4 6 8 10 12 0 MAX3237E SLEW RATE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3237E toc09 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 500 1000 1500 2000 2500 3000 SR+ SR- 1 TRANSMITTER AT 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ + CL 0 10 20 30 50 40 60 70 0 MAX3237E SLEW RATE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3237E toc10 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 500 1000 1500 2000 -SLEW, 1Mbps +SLEW, 1Mbps 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD EACH OUTPUT -SLEW, 2Mbps +SLEW, 2Mbps 0 10 20 30 40 50 0 MAX3237E SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA (MBAUD = GND) MAX3237E toc11 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 500 1000 1500 2000 2500 3000 250kbps 120kbps 20kbps 1 TRANSMITTER AT 20kbps, 120kbps, 250kbps 4 TRANSMITTERS AT 15.6kbps ALL TRANSMITTERS LOADED WITH 3kΩ + CL MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers _______________________________________________________________________________________ 7 *These pins have an active positive feedback resistor internal to the MAX3237E, allowing unused inputs to be left unconnected. Pin Description PIN MAX3222E MAX3232E MAX3241E TQFN SO/ DIP TSSOP/ SSOP TQFN SO/DIP/ SSOP/ 16-PIN TSSOP 20-PIN TSSOP MAX3237E SSOP/ SO QFN MAX3246E NAME FUNCTION 19 1 1 — — — 13* 23 22 B3 EN Receiver Enable. Active low. 1 2 2 16 1 2 28 28 28 F3 C1+ Positive Terminal of Voltage-Doubler Charge- Pump Capacitor 20 3 3 15 2 3 27 27 27 F1 V+ +5.5V Generated by the Charge Pump 2 4 4 1 3 4 25 24 23 F4 C1- Negative Terminal of Voltage-Doubler Charge- Pump Capacitor 3 5 5 2 4 5 1 1 29 E1 C2+ Positive Terminal of Inverting Charge-Pump Capacitor 4 6 6 3 5 6 3 2 30 D1 C2- Negative Terminal of Inverting Charge-Pump Capacitor 5 7 7 4 6 7 4 3 31 C1 V- -5.5V Generated by the Charge Pump 6, 15 8, 15 8, 17 5, 12 7, 14 8, 17 5, 6, 7, 10, 12 9, 10, 11 6, 7, 8 F6, E6, D6 T_OUT RS-232 Transmitter Outputs 7, 14 9, 14 9, 16 6, 11 8, 13 9, 16 8, 9, 11 4–8 1–5 A4, A5, A6, B6, C6 R_IN RS-232 Receiver Inputs 8, 13 10, 13 10, 15 7, 10 9, 12 12, 15 18, 20, 21 15–19 13, 14, 15, 17, 18 C2, B1, A1, A2, A3 R_OUT TTL/CMOS Receiver Outputs 10, 11 11, 12 12, 13 8, 9 10, 11 13, 14 17*, 19*, 22*, 23*, 24* 12, 13, 14 10, 11, 12 E3, E2, D2 T_IN TTL/CMOS Transmitter Inputs MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 8 _______________________________________________________________________________________ Pin Description (continued) PIN MAX3222E MAX3232E MAX3241E TQFN SO/ DIP TSSOP/ SSOP TQFN SO/DIP/ SSOP/ 16-PIN TSSOP 20-PIN TSSOP MAX3237E SSOP/ SO/ TSSOP QFN MAX3246E NAME FUNCTION 16 16 18 13 15 18 2 25 24 F5 GND Ground 17 17 19 14 16 19 26 26 26 F2 VCC +3.0V to +5.5V Supply Voltage 18 18 20 — — — 14* 22 21 B2 SHDN Shutdown Control. Active low. 9, 12 — 11, 14 — — 1, 10, 11, 20 — — 9, 16, 25, 32 C3, D3, B4, C4, D4, E4, B5, C5, D5, E5 N.C. No Connection. For MAX3246E, these locations are not populated with solder bumps. — — — — — — 15* — — — MBAUD MegaBaud Control Input. Connect to GND for normal operation; connect to VCC for 1Mbps transmission rates. — — — — — — 16 20, 21 19, 20 — R_OUTB Noninverting Complementary Receiver Outputs. Always active. EP — — EP — — — — EP — GND Exposed Paddle. Solder the exposed paddle to the ground alone or leave unconnected. MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers _______________________________________________________________________________________ 9 Detailed Description Dual Charge-Pump Voltage Converter The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246Es’ internal power supply consists of a regulated dual charge pump that provides output voltages of +5.5V (doubling charge pump) and -5.5V (inverting charge pump) over the +3.0V to +5.5V VCC range. The charge pump operates in discontinuous mode; if the output voltages are less than 5.5V, the charge pump is enabled, and if the output voltages exceed 5.5V, the charge pump is disabled. Each charge pump requires a flying capacitor (C1, C2) and a reservoir capacitor (C3, C4) to generate the V+ and V- supplies (Figure 1). RS-232 Transmitters The transmitters are inverting level translators that convert TTL/CMOS-logic levels to ±5V EIA/TIA-232-compliant levels. The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E transmitters guarantee a 250kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF, providing compatibility with PC-to-PC communication software (such as LapLink™). Transmitters can be paralleled to drive multiple receivers or mice. The MAX3222E/MAX3237E/MAX3241E/MAX3246E transmitters are disabled and the outputs are forced into a high-impedance state when the device is in shutdown mode (SHDN = GND). The MAX3222E/ MAX3232E/MAX3237E/MAX3241E/MAX3246E permit the outputs to be driven up to ±12V in shutdown. The MAX3222E/MAX3232E/MAX3241E/MAX3246E transmitter inputs do not have pullup resistors. Connect unused inputs to GND or VCC. The MAX3237E’s transmitter inputs have a 400kΩ active positive-feedback resistor, allowing unused inputs to be left unconnected. MAX3237E MegaBaud Operation For higher-speed serial communications, the MAX3237E features MegaBaud operation. In MegaBaud operating mode (MBAUD = VCC), the MAX3237E transmitters guarantee a 1Mbps data rate with worst-case loads of 3kΩ in parallel with 250pF for +3.0V < VCC < +4.5V. For +5V ±10% operation, the MAX3237E transmitters guarantee a 1Mbps data rate into worst-case loads of 3kΩ in parallel with 1000pF. RS-232 Receivers The receivers convert RS-232 signals to CMOS-logic output levels. The MAX3222E/MAX3237E/MAX3241E/ MAX3246E receivers have inverting three-state outputs. Drive EN high to place the receiver(s) into a highimpedance state. Receivers can be either active or inactive in shutdown (Table 1). MAX3222E MAX3232E MAX3237E MAX3241E MAX3246E 5kΩ R_ OUT R_ IN C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC T_ IN T_ OUT GND 7kΩ 150pF MAX3222E MAX3232E MAX3237E MAX3241E MAX3246E 5kΩ R_ OUT R_ IN C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC T_ IN T_ OUT GND 3kΩ 1000pF (2500pF, MAX3237E only) MINIMUM SLEW-RATE TEST CIRCUIT MAXIMUM SLEW-RATE TEST CIRCUIT Figure 1. Slew-Rate Test Circuits LapLink is a trademark of Traveling Software. MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 10 ______________________________________________________________________________________ The complementary outputs on the MAX3237E/ MAX3241E (R_OUTB) are always active, regardless of the state of EN or SHDN. This allows the device to be used for ring indicator applications without forward biasing other devices connected to the receiver outputs. This is ideal for systems where VCC drops to zero in shutdown to accommodate peripherals such as UARTs (Figure 2). MAX3222E/MAX3237E/MAX3241E/ MAX3246E Shutdown Mode Supply current falls to less than 1μA in shutdown mode (SHDN = low). The MAX3237E’s supply current falls to10nA (typ) when all receiver inputs are in the invalid range (-0.3V < R_IN < +0.3). When shut down, the device’s charge pumps are shut off, V+ is pulled down to VCC, V- is pulled to ground, and the transmitter outputs are disabled (high impedance). The time required to recover from shutdown is typically 100μs, as shown in Figure 3. Connect SHDN to VCC if shutdown mode is not used. SHDN has no effect on R_OUT or R_OUTB (MAX3237E/MAX3241E). ±15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated to protect against electrostatic discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX3222E/MAX3232E/MAX3237E/MAX3241E/MAX3246E have extra protection against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, Maxim’s E versions keep working without latchup, whereas competing RS-232 products can latch and must be powered down to remove latchup. Furthermore, the MAX3237E logic I/O pins also have ±15kV ESD protection. Protecting the logic I/O pins to ±15kV makes the MAX3237E ideal for data cable applications. T1OUT R1OUTB Tx 5kΩ UART VCC T1IN LOGIC TRANSITION DETECTOR R1OUT R1IN THREE-STATED EN = VCC SHDN = GND VCC TO μP Rx PREVIOUS RS-232 Tx UART PROTECTION DIODE PROTECTION DIODE SHDN = GND VCC VCC GND Rx 5kΩ a) OLDER RS-232: POWERED-DOWN UART DRAWS CURRENT FROM A ACTIVE RECEIVER OUTPUT IN SHUTDOWN. b) NEW MAX3237E/MAX3241E: EN SHUTS DOWN RECEIVER OUTPUTS B (EXCEPT FOR B OUTPUTS), SO NO CURRENT FLOWS TO UART IN SHUTDOWN. B B OUTPUTS INDICATE RECEIVER ACTIVITY DURING SHUTDOWN WITH EN HIGH. GND MAX3237E/MAX3241E Figure 2. Detection of RS-232 Activity when the UART and Interface are Shut Down; Comparison of MAX3237E/MAX3241E (b) with Previous Transceivers (a) 40μs/div SHDN T2OUT T1OUT 5V/div 0 2V/div 0 VCC = 3.3V C1–C4 = 0.1μF Figure 3. Transmitter Outputs Recovering from Shutdown or Powering Up MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 11 ESD protection can be tested in various ways; the transmitter outputs and receiver inputs for the MAX3222E/MAX3232E/MAX3241E/MAX3246E are characterized for protection to the following limits: • ±15kV using the Human Body Model • ±8kV using the Contact Discharge method specified in IEC 1000-4-2 • ±9kV (MAX3246E only) using the Contact Discharge method specified in IEC 1000-4-2 • ±15kV using the Air-Gap Discharge method specified in IEC 1000-4-2 CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR Cs 100pF RC 1MΩ RD 1500Ω HIGHVOLTAGE DC SOURCE DEVICEUNDERTEST Figure 4a. Human Body ESD Test Model IP 100% 90% 36.8% tRL TIME tDL CURRENT WAVEFORM PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) Ir 10% 0 0 AMPERES Figure 4b. Human Body Model Current Waveform CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR Cs 150pF RC 50MΩ to 100MΩ RD 330Ω HIGHVOLTAGE DC SOURCE DEVICEUNDERTEST Figure 5a. IEC 1000-4-2 ESD Test Model tr = 0.7ns to 1ns 30ns 60ns t 100% 90% 10% IPEAK I Figure 5b. IEC 1000-4-2 ESD Generator Current Waveform Table 1. MAX3222E/MAX3237E/MAX3241E/ MAX3246E Shutdown and Enable Control Truth Table SHDN EN T_OUT R_OUT R_OUTB (MAX3237E/ MAX3241E) 0 0 High impedance Active Active 0 1 High impedance High impedance Active 1 0 Active Active Active 1 1 Active High impedance Active MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 12 ______________________________________________________________________________________ For the MAX3237E, all logic and RS-232 I/O pins are characterized for protection to ±15kV per the Human Body Model. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 4a shows the Human Body Model, and Figure 4b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. IEC 1000-4-2 The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX3222E/ MAX3232E/MAX3237E/MAX3241E/MAX3246E help you design equipment that meets level 4 (the highest level) of IEC 1000-4-2, without the need for additional ESDprotection components. The major difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2, because series resistance is lower in the IEC 1000-4-2 model. Hence, the ESD withstand voltage measured to IEC 1000-4-2 is generally lower than that measured using the Human Body Model. Figure 5a shows the IEC 1000-4-2 model, and Figure 5b shows the current waveform for the ±8kV IEC 1000-4-2 level 4 ESD Contact Discharge test. The Air- Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized. Machine Model The Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. All pins require this protection during manufacturing, not just RS-232 inputs and outputs. Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports. Table 2. Required Minimum Capacitor Values -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 MAX3222E-fig06a LOAD CURRENT PER TRANSMITTER (mA) TRANSMITTER OUTPUT VOLTAGE (V) VOUT+ VOUTVOUT+ VCC VOUTVCC = 3.0V Figure 6a. MAX3241E Transmitter Output Voltage vs. Load Table 3. Logic-Family Compatibility with Current Per Transmitter Various Supply Voltages VCC (V) C1 (μF) C2, C3, C4 (μF) MAX3222E/MAX3232E/MAX3241E 3.0 to 3.6 0.1 0.1 4.5 to 5.5 0.047 0.33 3.0 to 5.5 0.1 0.47 MAX3237E/MAX3246E 3.0 to 3.6 0.22 0.22 3.15 to 3.6 0.1 0.1 4.5 to 5.5 0.047 0.33 3.0 to 5.5 0.22 1.0 SYSTEM POWER-SUPPLY VOLTAGE (V) VCC SUPPLY VOLTAGE (V) COMPATIBILITY 3.3 3.3 Compatible with all CMOS families 5 5 Compatible with all TTL and CMOS families 5 3.3 C om p ati b l e w i th AC T and H C T C M OS , and w i th AC , H C , or C D 4000 C M O S MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 13 Applications Information Capacitor Selection The capacitor type used for C1–C4 is not critical for proper operation; polarized or nonpolarized capacitors can be used. The charge pump requires 0.1μF capacitors for 3.3V operation. For other supply voltages, see Table 2 for required capacitor values. Do not use values smaller than those listed in Table 2. Increasing the capacitor values (e.g., by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without changing C1’s value. However, do not increase C1 without also increasing the values of C2, C3, C4, and CBYPASS to maintain the proper ratios (C1 to the other capacitors). When using the minimum required capacitor values, make sure the capacitor value does not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+ and V-. Power-Supply Decoupling In most circumstances, a 0.1μF VCC bypass capacitor is adequate. In applications sensitive to power-supply noise, use a capacitor of the same value as chargepump capacitor C1. Connect bypass capacitors as close to the IC as possible. Operation Down to 2.7V Transmitter outputs meet EIA/TIA-562 levels of ±3.7V with supply voltages as low as 2.7V. MAX3241E 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 VCC R4IN 7 6 R2IN 5 R1IN 4 SHDN 22 GND 25 12 T3IN 13 T2IN 14 T1IN 2 C2- 1 C2+ 24 C1- 28 C1+ T3OUT 11 +V COMPUTER SERIAL PORT +V -V GND Tx T2OUT 10 T1OUT 9 V- 3 V+ VCC 27 VCC C4 C1 C3 C2 CBYPASS VCC = +3.0V TO +5.5V 26 R3IN MOUSE Figure 6b. Mouse Driver Test Circuit MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 14 ______________________________________________________________________________________ Figure 7. Loopback Test Circuit 2μs/div T1IN T1OUT R1OUT 5V/div 5V/div V 5V/div CC = 3.3V C1–C4 = 0.1μF Figure 8. MAX3241E Loopback Test Result at 120kbps 2μs/div T1IN T1OUT R1OUT 5V/div 5V/div 5V/div VCC = 3.3V, C1–C4 = 0.1μF Figure 9. MAX3241E Loopback Test Result at 250kbps +5V 0 +5V 0 -5V +5V 0 T_IN T_OUT 5kΩ + 250pF R_OUT 400ns/div VCC = 3.3V C1–C4 = 0.1μF Figure 10. MAX3237E Loopback Test Result at 1000kbps (MBAUD = VCC) MAX3222E MAX3232E MAX3237E MAX3241E MAX3246E 5kΩ R_ OUT R_ IN C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC T_ IN T_ OUT GND 1000pF Transmitter Outputs Recovering from Shutdown Figure 3 shows two transmitter outputs recovering from shutdown mode. As they become active, the two transmitter outputs are shown going to opposite RS-232 levels (one transmitter input is high; the other is low). Each transmitter is loaded with 3kΩ in parallel with 2500pF. The transmitter outputs display no ringing or undesirable transients as they come out of shutdown. Note that the transmitters are enabled only when the magnitude of V- exceeds approximately -3.0V. Mouse Drivability The MAX3241E is designed to power serial mice while operating from low-voltage power supplies. It has been tested with leading mouse brands from manufacturers such as Microsoft and Logitech. The MAX3241E successfully drove all serial mice tested and met their current and voltage requirements. MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 15 Figure 6a shows the transmitter output voltages under increasing load current at +3.0V. Figure 6b shows a typical mouse connection using the MAX3241E. High Data Rates The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E maintain the RS-232 ±5V minimum transmitter output voltage even at high data rates. Figure 7 shows a transmitter loopback test circuit. Figure 8 shows a loopback test result at 120kbps, and Figure 9 shows the same test at 250kbps. For Figure 8, all transmitters were driven simultaneously at 120kbps into RS- 232 loads in parallel with 1000pF. For Figure 9, a single transmitter was driven at 250kbps, and all transmitters were loaded with an RS-232 receiver in parallel with 1000pF. The MAX3237E maintains the RS-232 ±5.0V minimum transmitter output voltage at data rates up to 1Mbps. Figure 10 shows a loopback test result at 1Mbps with MBAUD = VCC. For Figure 10, all transmitters were loaded with an RS-232 receiver in parallel with 250pF. Interconnection with 3V and 5V Logic The MAX3222E/MAX3232E/MAX3237E/MAX3241E/ MAX3246E can directly interface with various 5V logic families, including ACT and HCT CMOS. See Table 3 for more information on possible combinations of interconnections. UCSP Reliability The UCSP represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as the wafer-fabrication process primarily determines it. Mechanical stress performance is a greater consideration for a UCSP package. UCSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Table 4 shows the testing done to characterize the UCSP reliability performance. In conclusion, the UCSP is capable of performing reliably through environmental stresses as indicated by the results in the table. Additional usage data and recommendations are detailed in the UCSP application note, which can be found on Maxim’s website at www.maxim-ic.com. Table 4. Reliability Test Data TEST CONDITIONS DURATION FAILURES PER SAMPLE SIZE Temperature Cycle TA = -35°C to +85°C, TA = -40°C to +100°C 150 cycles, 900 cycles 0/10, 0/200 Operating Life TA = +70°C 240 hours 0/10 Moisture Resistance TA = +20°C to +60°C, 90% RH 240 hours 0/10 Low-Temperature Storage TA = -20°C 240 hours 0/10 Low-Temperature Operational TA = -10°C 24 hours 0/10 Solderability 8-hour steam age — 0/15 ESD ±15kV, Human Body Model — 0/5 High-Temperature Operating Life TJ = +150°C 168 hours 0/45 MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 16 ______________________________________________________________________________________ __________________________________________________________Pin Configurations 20 19 18 17 16 15 14 13 1 2 3 8 12 10 11 4 5 6 7 SHDN VCC GND C1- T1OUT V+ C1+ EN R1IN R1OUT T1IN T2IN T2OUT VC2- C2+ R2IN 9 R2OUT TSSOP/SSOP N.C. N.C. MAX3222E 20 19 18 17 16 15 14 13 1 2 3 8 12 10 11 4 5 6 7 N.C. VCC GND C1- T1OUT V+ C1+ N.C. R1IN R1OUT T2IN R2OUT T2OUT VC2- C2+ R2IN 9 N.C. TSSOP T1IN N.C. MAX3232E 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC GND T1OUT C2+ R1IN C1- V+ C1+ MAX3232E R1OUT T1IN T2IN R2IN R2OUT T2OUT VC2- SO/DIP/SSOP/TSSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC GND C1- EN R5OUT SHDN R1OUTB R2OUTB R1OUT R2OUT R3OUT R4OUT T1IN T2IN T3IN T3OUT T2OUT T1OUT R5IN R4IN R3IN R2IN R1IN VC2- C2+ SSOP/SO/TSSOP QFN MAX3241E TOP VIEW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC C1- T1IN T2IN MBAUD T3IN R1OUT R2OUT T4IN R3OUT T5IN R1OUTB SHDN EN T5OUT R3IN T4OUT R2IN R1IN T3OUT T2OUT T1OUT VC2- GND C2+ SSOP MAX3237E 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 SHDN VCC GND C1- T1OUT V+ C1+ EN R1IN R1OUT T1IN T2OUT T2IN VC2- C2+ R2IN 9 10 R2OUT SO/DIP MAX3222E 32 31 30 29 28 27 26 N.C. VC2- C2+ C1+ V+ VCC 25 N.C. 9 10 11 12 13 14 15 N.C. T3IN T2IN T1IN R5OUT R4OUT R3OUT N.C. 16 17 18 19 20 21 22 23 R2OUT R1OUT R2OUTB R1OUTB SHDN EN C1- 8 7 6 5 4 3 2 T3OUT T2OUT T1OUT R5IN R4IN R3IN R2IN MAX3241E R1IN 1 24 GND TOP VIEW MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 17 Pin Configurations (continued) 19 20 18 17 7 6 8 C1- C2- V- 9 C1+ R1IN N.C. T1IN T1OUT 1 2 SHDN 4 5 15 14 12 11 EN V+ EXPOSED PADDLE EXPOSED PADDLE N.C. R2OUT R2IN T2OUT MAX3222E C2+ R1OUT 3 13 VCC GND 16 10 T2IN TQFN TOP VIEW 15 16 14 13 6 5 7 C2+ V- 8 C1- R1IN T1IN T1OUT 1 2 VCC 4 12 11 9 V+ C1+ T2IN R2OUT R2IN T2OUT MAX3232E C2- R1OUT 3 10 GND TQFN TOP VIEW UCSP F2 F3 F4 F5 F6 E3 E6 D6 C6 B3 B6 A2 A3 A4 A5 A6 TOP VIEW (BUMPS ON BOTTOM) T1OUT VCC C1+ C1- GND R3IN R4OUT R5OUT R1IN R2IN R4IN R5IN T3OUT T2OUT B2: SHDN C2: R1OUT D2: T3IN E2: T2IN B3: EN E3: T1IN BUMPS B4, B5, C3, C4, C5, D3, D4, D5, E4, AND E5 NOT POPULATED E2 D2 C2 B2 F1 E1 D1 C1 B1 A1 V+ R3OUT R2OUT VC2- C2+ MAX3246E MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 18 ______________________________________________________________________________________ __________________________________________________Typical Operating Circuits 10 R2OUT 1 13 R1OUT R2IN 9 18 GND 16 RS-232 OUTPUTS TTL/CMOS INPUTS 11 T2IN 12 T1IN C2- 6 5 C2+ 4 C1- 2 C1+ R1IN 14 T2OUT 8 T1OUT 15 V- 7 V+ VCC 3 17 C1 0.1μF C2 0.1μF CBYPASS +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS 5kΩ EN 5kΩ SHDN C3* 0.1μF C4 0.1μF NOTE: PIN NUMBERS REFER TO SO/DIP PACKAGES. MAX3222E PINOUT REFERS TO SO/DIP PACKAGES. MAX3232E PINOUT REFERS TO TSSOP/SSOP/SO/DIP/ PACKAGES *C3 CAN BE RETURNED TO EITHER VCC OR GROUND. 9 R2OUT 12 R1OUT R2IN 8 GND 15 RS-232 OUTPUTS TTL/CMOS INPUTS 10 T2IN 11 T1IN C2- 5 4 C2+ 3 C1- 1 C1+ R1IN 13 T2OUT 7 T1OUT 14 V- 6 V+ VCC 2 C4 0.1μF 16 C1 0.1μF C2 0.1μF CBYPASS +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS C3* 0.1μF 5kΩ 5kΩ SEE TABLE 2 FOR CAPACITOR SELECTION. MAX3222E MAX3232E MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 19 _____________________________________Typical Operating Circuits (continued) 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB TTL/CMOS OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 *C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R4IN 7 R3IN 6 R2IN 5 R1IN 4 RS-232 INPUTS SHDN 22 GND 25 RS-232 OUTPUTS TTL/CMOS INPUTS 12 T3IN 13 T2IN 14 T1IN C2- 2 1 C2+ 24 C1- 28 C1+ T3OUT 11 T2OUT 10 T1OUT 9 V- 3 V+ VCC 27 C4 0.1μF C3* 0.1μF C1 0.1μF C2 0.1μF 26 +3.3V CBYPASS MAX3241E 13 EN 18 R3OUT 20 R2OUT 21 R1OUT 16 R1OUTB LOGIC OUTPUTS 5kΩ 5kΩ 5kΩ R3IN 11 R2IN 9 R1IN 8 RS-232 INPUTS GND 2 RS-232 OUTPUTS LOGIC INPUTS 22 T3IN 23 T2IN 24 T1IN C2- 3 1 C2+ 25 C1- 28 C1+ T3OUT 7 T2OUT 6 T1OUT 5 T1 T2 T3 R1 R2 R3 V- 4 V+ VCC 27 0.1μF 0.1μF 0.1μF 0.1μF 26 MBAUD 15 17 T5IN 19 T4IN T5OUT 12 T4OUT 10 SHDN 14 T4 T5 C3* CBYPASS +3.3V MAX3237E MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 20 ______________________________________________________________________________________ _____________________________________Typical Operating Circuits (continued) B3 EN A3 R5OUT A2 R4OUT A1 R3OUT B1 R2OUT C2 R1OUT TTL/CMOS OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN C6 *C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R4IN B6 R3IN A6 R2IN A5 R1IN A4 RS-232 INPUTS SHDN B2 GND F5 RS-232 OUTPUTS TTL/CMOS INPUTS D2 T3IN E2 T2IN E3 T1IN C2- D1 E1 C2+ F4 C1- F3 C1+ T3OUT D6 T2OUT E6 T1OUT F6 VC1 V+ VCC F1 C4 0.1μF C3* 0.1μF C1 0.1μF C2 0.1μF F2 +3.3V CBYPASS MAX3246E MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 21 Selector Guide PART NO. OF DRIVERS/ RECEIVERS LOW-POWER SHUTDOWN GUARANTEED DATA RATE (bps) MAX3222E 2/2 ✔ 250k MAX3232E 2/2 — 250k MAX3237E (Normal) 5/3 ✔ 250k MAX3237E (MegaBaud) 5/3 ✔ 1M MAX3241E 3/5 ✔ 250k MAX3246E 3/5 ✔ 250k ___________________Chip Information TRANSISTOR COUNT: MAX3222E/MAX3232E: 1129 MAX3237E: 2110 MAX3241E: 1335 MAX3246E: 842 PROCESS: BICMOS Ordering Information (continued) PART TEMP RANGE PINPACKAGE PKG CODE MAX3232ECTE 0°C to +70°C 16 Thin QFNEP** (5mm x 5mm) T1655-2 MAX3232ECUE 0°C to +70°C 16 TSSOP — MAX3232ECUP 0°C to +70°C 20 TSSOP — MAX3232EEAE -40°C to +85°C 16 SSOP — MAX3232EEWE -40°C to +85°C 16 Wide SO — MAX3232EEPE -40°C to +85°C 16 Plastic DIP — MAX3232EETE -40°C to +85°C 16 Thin QFNEP** (5mm x 5mm) T1655-2 MAX3232EEUE -40°C to +85°C 16 TSSOP — MAX3232EEUP -40°C to +85°C 20 TSSOP — MAX3237ECAI 0°C to +70°C 28 SSOP — MAX3237EEAI -40°C to +85°C 28 SSOP — MAX3241ECAI 0°C to +70°C 28 SSOP — MAX3241ECWI 0°C to +70°C 28 Wide SO — MAX3241ECUI 0°C to +70°C 28 TSSOP — MAX3241ECTJ 0°C to +70°C 32 Thin QFN — MAX3241EEAI -40°C to +85°C 28 SSOP — MAX3241EEWI -40°C to +85°C 28 Wide SO — MAX3241EEUI -40°C to +85°C 28 TSSOP — MAX3246ECBX-T 0°C to +70°C 6 x 6 UCSP† — MAX3246EEBX-T -40°C to +85°C 6 x 6 UCSP† — †Requires solder temperature profile described in the Absolute Maximum Ratings section. UCSP Reliability is integrally linked to the user’s assembly methods, circuit board material, and environment. Refer to the UCSP Reliability Notice in the UCSP Reliability section of this datasheet for more information. **EP = Exposed paddle. 24L QFN THIN.EPS PACKAGE OUTLINE, 21-0139 2 1 E 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm PACKAGE OUTLINE, 21-0139 2 2 E 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 22 ______________________________________________________________________________________ MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 23 TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 1 1 I Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers 24 ______________________________________________________________________________________ 36L,UCSP.EPS 21-0082 1 1 K PACKAGE OUTLINE, 6x6 UCSP Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ______________________________________________________________________________________ 25 SOICW.EPS PACKAGE OUTLINE, .300" SOIC 1 1 21-0042 B APPROVAL DOCUMENT CONTROL NO. REV. PROPRIETARY INFORMATION TITLE: TOP VIEW FRONT VIEW MAX 0.012 0.104 0.019 0.299 0.013 INCHES 0.291 0.009 E C DIM 0.014 0.004 B A1 MIN A 0.093 0.23 7.40 7.60 0.32 MILLIMETERS 0.10 0.35 2.35 MIN 0.49 0.30 MAX 2.65 L 0.016 0.050 0.40 1.27 D 0.496 0.512 D DIM MIN D INCHES MAX 12.60 13.00 MILLIMETERS MIN MAX 20 AC 0.447 0.463 11.35 11.75 18 AB 0.398 0.413 10.10 10.50 16 AA N MS013 SIDE VIEW H 0.394 0.419 10.00 10.65 e 0.050 1.27 D 0.598 0.614 15.20 15.60 24 AD D 0.697 0.713 17.70 18.10 28 AE E H N D e B A1 A 0∞-8∞ C L 1 VARIATIONS: Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SSOP.EPS PACKAGE OUTLINE, SSOP, 5.3 MM 1 1 21-0056 C APPROVAL DOCUMENT CONTROL NO. REV. PROPRIETARY INFORMATION TITLE: NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. H 7.90 L 0∞ 0.301 0.025 8∞ 0.311 0.037 0∞ 7.65 0.63 8∞ 0.95 MAX 5.38 MILLIMETERS B C D E e A1 DIM A SEE VARIATIONS 0.0256 BSC 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 INCHES MIN MAX 0.078 0.65 BSC 0.25 0.09 5.20 0.05 0.38 0.20 0.21 MIN 1.73 1.99 MILLIMETERS 6.07 6.07 10.07 8.07 7.07 INCHES D D D D D 0.239 0.239 0.397 0.317 0.278 MIN 0.249 0.249 0.407 0.328 0.289 MAX MIN 6.33 6.33 10.33 8.33 7.33 14L 16L 28L 24L 20L MAX N A D e A1 L C E H N 2 1 B 0.068 MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PDIPN.EPS Revision History Pages changed at Rev 10: 1–4, 9, 11, 21, 22, 26 PCB Keyswitches 4 - 23 4 RF RF short-travel keyswitches General data RF 15 (15 x 15 mm) and RF 19 (19 x 19 mm) with distinct key click, for use under an overlay or with RK 90 keycaps. Can be fully illuminated. Content RF 15 short-travel keyswitch 4 - 26 RF 15 short-travel keyswitch, non-illuminated 4 - 28 RF 15 short-travel keyswitch, fully illuminated with 2 LEDs 4 - 29 RF 15 short-travel keyswitch, 1 LED spot-illumination 4 - 30 RF 15 N short-travel keyswitch 4 - 32 RF 15 N short-travel keyswitch, non-illuminated 4 - 35 RF 15 R short-travel keyswitch 4 - 36 RF 15 R low short-travel keyswitch, non-illuminated 4 - 39 RF 15 R high short-travel keyswitch, non-illuminated 4 - 39 RF 15 R low short-travel keyswitch, 1 LED spot-illumination 4 - 40 RF 15 R high short-travel keyswitch, 1 LED spot-illumination 4 - 41 RF 15 H short-travel keyswitch 4 - 42 RF 15 H short-travel keyswitch, non-illuminated 4 - 44 RF 15 H short-travel keyswitch, fully illuminated 4 - 45 RF 15 signal indicator 4 - 46 RF 15 signal indicator, fully illuminated, 1 LED 4 - 48 RF 19 short-travel keyswitch 4 - 50 RF 19 short-travel keyswitch, non-illuminated 4 - 53 RF 19 short-travel keyswitch, fully illuminated with 2 LEDs 4 - 54 RF 19 short-travel keyswitch, 1 LED spot-illumination 4 - 55 RF 19 short-travel keyswitch, 1 NC + 1 NO 4 - 56 RF 19 short-travel keyswitch, non-illuminated 4 - 58 RF 19 H short-travel keyswitch 4 - 60 RF 19 H keyswitch, non-illuminated 4 - 62 RF 19 H short-travel keyswitch, fully illuminated 4 - 63 RF 19 signal indicator 4 - 64 RF 19 signal indicator, 1/2 x 1-module 4 - 66 RF 19 signal indicator, 1/2 x 2-module 4 - 66 RF 19 signal indicator, 1 x 1-module 4 - 67 RF 19 signal indicator, 1 x 2-module 4 - 67 4 - 24 PCB Keyswitches 4 RF RF short-travel keyswitches RF special accessories 4 - 68 Extension plunger for RF 15 N, round head 4 - 68 Extension plunger for RF 15 N, round head, with recess for LED 4 - 69 Keycap for RF 15, snap-on, for overall height 12.5 mm 4 - 69 Spacers, round 4 - 70 Spacers, triangular 4 - 71 LED spacer for RF 15 N 4 - 72 PCB Keyswitches 4 - 25 4 RF RF short-travel keyswitches Specifications LED 3 mm LED 2 mm LED Max. forward current lF: Current reduction from: T0 = 50 °C: Wavelength typ: Forward voltage UF/lF typ: Reverse voltage UR/lF typ: Ambient temperature, operating: (valid for 25 °C) 30 mA approx 0.5 mA/°C 635 nm 2 V/10 mA 5 V/100 μA min. - 20 °C . . . + 80 °C Red LED 30 mA approx 0.5 mA/°C 565 nm 2 V/10 mA 5 V/100 μA min. - 20 °C . . . + 80 °C Green LED 20 mA approx 0.2 mA/°C 586 nm 2 V/10 mA 5 V/100 μA min. - 20 °C . . . + 80 °C Yellow LED Max. forward current lF: Current reduction from: T0 = 50 °C: Wavelength typ: Forward voltage UF/lF typ: Reverse voltage UR/lF typ: Ambient temperature, operating: 20 mA approx 0.6 mA/°C 470 nm 2.7 V/10 mA 5V/100 μA min. - 20 °C . . . + 80 °C Blue LED 25 mA -- 3.6 V/20 mA - - 20 °C . . . + 80 °C White LED 30 mA - 510-545 nm 3.5 V/20 mA - -30 °C . . . + 100 °C Green LED superbright Max. forward current lF: Current reduction from: T0 = 50 °C: Light current fV/lF typ: Wavelength typ: Forward voltage UF/lF typ: Reverse voltage UR/lF typ: Ambient temperature, operating: (valid for 25 °C) 30 mA 0.5 mA/°C - 637 nm 1.8 V/20 mA 5 V/100 μA min. - 55 °C . . . + 100 °C Red LED 30 mA 0.5 mA/°C - 569 nm 2.1 V/10 mA 5 V/100 μA min. - 40 °C . . . + 100 °C Green LED 50 mA 0.8 mA/°C 250 mIm/20 mA 590 nm 1.9 V/20 mA 5 V/100 μA min. -40 °C . . . + 100 °C Yellow LED Max. forward current lF: Current reduction from: T0 = 50 °C: Light current fV/lF typ: Wavelength typ: Forward voltage UF/lF typ: Reverse voltage UR/lF typ: Ambient temperature, operating: 30 mA - - 464-485 nm 3.6 V/20 mA - 20 °C . . . + 80 °C Blue LED 30 mA approx 0.6 mA/°C - 635/565 nm 2 V/10 mA - - 20 °C . . . + 80 °C Multi-colour LED Rated power of series: PV = IF 2 x RV Calculating the series resistor: RV = Example for 5 Volt: RV = = 150 Ω (= standard value) UB - UF IF 5V - 2.0 V 0.02 A 4 - 26 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 short-travel keyswitch General data Low-profile keyboards with RF 15 components should be designed with a 19.05 mm grid. With this grid, frame webs remain free between the individual keys. The overlay can be glued onto these frame webs; we recommend area embossing over the keys for the overlays. Technical data General information Colour of lens see order block Recommended key grid 19.05 mm Dimensions Length 15 mm Width 15 mm Overall height 9.7 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination spot-/fully illuminated LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 27 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 View on component side, all hole diameters 1,1 +/- 0,1 mm Operation characteristic limits RF Keyswitch, non-illuminated Keyswitch, fully illuminated Keyswitch, spot-illuminated Force/Travel Diagram – Keyswitch RF 15 Circuit Diagram – Keyswitch RF 15 Dimensional Drawing RF 15 Hole Pattern RF 15 Hole Pattern – Front Panel Stock items are marked by bold printed order numbers. 4 - 28 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 short-travel keyswitch, non-illuminated Contact materials Illumination Colour of lens LED colour LED type Order no. Ag not illuminated transparent 3.14.100.006/0000 Au not illuminated transparent 3.14.100.001/0000 Technical data see page 4 - 26 Accessories: Keycap for RF 15, snap-on, for overall height 12.5 mm: 5.46.654.059/0227 For keycaps, refer to chapter accessories and system RK 90. If exchangeable legends are required, or if an overall height of 12.5 mm is required, a keycap can be mounted on the non-illuminated keys. The keycap legend is visible through a window in the overlay. You can change the legend by replacing the keycap. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 29 4 RF RF short-travel keyswitches RF 15 short-travel keyswitch, fully illuminated with 2 LEDs Illuminated area 10.8 x 10.8 mm Housing Actuator Lens Pict.: red Contact materials Illumination Colour of lens LED colour LED type Order no. Ag fully illuminated 2 LEDs red red 2 mm 3.14.200.021/0000 Ag fully illuminated 2 LEDs green green 2 mm 3.14.200.022/0000 Ag fully illuminated 2 LEDs yellow yellow 2 mm 3.14.200.023/0000 Ag fully illuminated 2 LEDs orange yellow 2 mm 3.14.200.024/0000 Ag fully illuminated 2 LEDs blue blue 2 mm 3.14.200.025/0000 Au fully illuminated 2 LEDs green green 2 mm 3.14.200.012/0000 Au fully illuminated 2 LEDs yellow yellow 2 mm 3.14.200.013/0000 Au fully illuminated 2 LEDs orange yellow 2 mm 3.14.200.014/0000 Au fully illuminated 2 LEDs blue blue 2 mm 3.14.200.015/0000 Technical data see page 4 - 26 For keycaps, refer to RK 90 system design. Technical data of LED see seperate page at the beginning of this chapter. Stock items are marked by bold printed order numbers. 4 - 30 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 short-travel keyswitch, 1 LED spot-illumination Pict.: red Contact materials Illumination Colour of lens LED colour LED type Order no. Ag spot illumination 1 LED opaque white blue 3 mm 3.14.100.040/0000 Ag spot illumination 1 LED transparent red 3 mm 3.14.100.041/0000 Ag spot illumination 1 LED transparent green 3 mm 3.14.100.042/0000 Ag spot illumination 1 LED transparent yellow 3 mm 3.14.100.043/0000 Au spot illumination 1 LED opaque white blue 3 mm 3.14.100.030/0000 Au spot illumination 1 LED transparent red 3 mm 3.14.100.031/0000 Au spot illumination 1 LED transparent green 3 mm 3.14.100.032/0000 Au spot illumination 1 LED transparent yellow 3 mm 3.14.100.033/0000 Technical data see page 4 - 26 Double-spot LED illumination available on request Technical data of LED see seperate page at the beginning of this chapter. 4 - 32 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 N short-travel keyswitch General data The RF 15N keyswitch provides a minimum overall height of 6.2 mm. The overall height can be varied by extension plungers which are inserted into the cross-like notches on the actuator tops. LEDs can only be arranged separately next to the keyswitches up to an overall height of 10 mm (i.e. without plunger or with small plunger). Keyswitches with overall heights of 12 mm or more can be provided with a maximum of 2 LEDs which are inserted into the recesses of the keyswitch housing. LEDs of keyswitches with overall heights of 12.5 mm or more should be placed onto LED spacers in order to obtain satisfactory illumination. Technical data General information Colour of lens see order block Recommended key grid 19.05 mm Dimensions Length 15 mm Width 15 mm Overall height 6.2 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination external 3 mm LED possible if height ‹ 12 mm Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 33 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 Operation characteristic limits RF Keyswitch, non illuminated Keyswitch, spot-illuminated Force/Travel Diagram – Keyswitch RF 15 N Circuit Diagram – Keyswitch RF 15 N Dimensional Drawings RF 15 N 4 - 34 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 N without plunger RF 15 N with plunger ø 10 mm, non-illuminated RF 15 N with plunger ø 10 mm, illuminated RF 15 N with plunger ø 15 mm, illuminated View on component side All hole diameters 1,1 +/- 0,1 mm PCB layout Keyswitch 1/400” grid Hole Pattern RF 15 N Hole Patterns – Front Panel RF 15 N Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 35 4 RF Description Photo Order no. Page Accessories RF 15 N short-travel keyswitch LED yellow, 3mm 1.90.690.103/0000 5 - 20 LED spacer for RF 15 N, Ø 5 mm, spacing length 2.2 mm, light grey, for use with overall height of 12.5 mm 5.30.109.010/0756 Extension plunger for RF 15 N, Ø 10 mm, overall height 22.5 mm 5.46.011.028/0710 Extension plunger for RF 15 N, Ø 15 mm, overall height 22.5 mm 5.46.017.028/0710 RF 15 N short-travel keyswitch, non-illuminated Contact materials Illumination Recommended key grid Overall height Order no. Au external 3 mm LED possible if height < 12 mm 19.05 mm 6.2 mm 3.14.100.601/0000 Ag external 3 mm LED possible if height < 12 mm 19.05 mm 6.2 mm 3.14.100.606/0000 Technical data see page 4 - 32 For keycaps, refer to RK 90 system design. Double-spot LED illumination available on request. 4 - 36 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 R short-travel keyswitch with 3 mm LED, green Pict.: with 2 mm LED, red General data The round actuator of the RF 15 R keyswitch requires round front panel cut-outs. These make it possible to use a narrow keyboard grid of only 15.24 mm with sufficiently large frame webs between the individual keys. We recommend area embossing over the actuators for the overlay. Technical data General information Recommended key grid 15.24 mm Dimensions Length 15 mm Width 15 mm Overall height 9,7/12,5 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination spot illumination LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 37 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 View on component side All hole diameters 1,1 +/- 0,1 mm PCB layout Keyswitch 1/400” grid Operation characteristic limits RF Keyswitch, non-illuminated Keyswitch, spot-illuminated Force/Travel Diagram – Keyswitch RF 15 R Circuit Diagram – Keyswitch RF 15 R Dimensional Drawing RF 15 R Hole Pattern RF 15 R 4 - 38 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 R, non-illuminated RF 15 R, illuminated Hole Pattern – Front Panel RF 15 R Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 39 4 RF RF short-travel keyswitches RF 15 R low short-travel keyswitch, non-illuminated Contact materials Overall height Illumination LED type LED colour Order no. Au 9.7 mm not illuminated 3.14.100.501/0000 Ag 9.7 mm not illuminated 3.14.100.506/0000 Technical data see page 4 - 36 RF 15 R high short-travel keyswitch, non-illuminated Contact materials Overall height Illumination LED type LED colour Order no. Au 12.5 mm not illuminated 3.14.100.801/0000 Ag 12.5 mm not illuminated 3.14.100.806/0000 Technical data see page 4 - 36 Stock items are marked by bold printed order numbers. 4 - 40 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 R low short-travel keyswitch, 1 LED spot-illumination Pict.: with 2 mm LED, red Contact materials Overall height Illumination LED type LED colour Order no. Au 9.7 mm spot illumination 1 LED 2 mm red 3.14.100.531/0000 Au 9.7 mm spot illumination 1 LED 2 mm green 3.14.100.532/0000 Au 9.7 mm spot illumination 1 LED 2 mm yellow 3.14.100.533/0000 Ag 9.7 mm spot illumination 1 LED 2 mm red 3.14.100.541/0000 Ag 9.7 mm spot illumination 1 LED 2 mm green 3.14.100.542/0000 Ag 9.7 mm spot illumination 1 LED 2 mm yellow 3.14.100.543/0000 Technical data see page 4 - 36 Versions with 2 LEDs available on request. Technical data of LED see seperate page at the beginning of this chapter. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 41 4 RF RF short-travel keyswitches RF 15 R high short-travel keyswitch, 1 LED spot-illumination Pict.: with 3 mm LED, green Contact materials Overall height Illumination LED type LED colour Order no. Au 12.5 mm spot illumination 1 LED 3 mm blue 3.14.100.830/0000 Au 12.5 mm spot illumination 1 LED 3 mm red 3.14.100.831/0000 Au 12.5 mm spot illumination 1 LED 3 mm green 3.14.100.832/0000 Au 12.5 mm spot illumination 1 LED 3 mm yellow 3.14.100.833/0000 Ag 12.5 mm spot illumination 1 LED 3 mm blue 3.14.100.840/0000 Ag 12.5 mm spot illumination 1 LED 3 mm red 3.14.100.841/0000 Ag 12.5 mm spot illumination 1 LED 3 mm green 3.14.100.842/0000 Ag 12.5 mm spot illumination 1 LED 3 mm yellow 3.14.100.843/0000 Technical data see page 4 - 36 Versions with 2 LEDs available on request. Technical data of LED see seperate page at the beginning of the chapter. 4 - 42 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 H short-travel keyswitch yellow General data Application notes: The RF 15 H key has an overall height of 12.5 mm and can be fully illuminated. When designing membrane keyboards, we recommend using a key grid of at least 19.05 mm and a 0.13 mm overlay with area embossing over the keys. You can use the O-ring (accessory) to block the key and use it as an indicator field or blank spaceholder. Technical data General information Colour of lens see order block Recommended key grid 20 mm Dimensions Length 15 mm Width 15 mm Overall height 12.5 mm Mechanical design Mounting soldering into PCB Terminals see order block Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination not illuminated / fully illuminated LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 43 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 No metal webs with 15.24 mm. View on component side. All hole diameters 1,1 +/- 0,1 mm. PCB layout Keyswitch 1/400” grid. Operation characteristic limits RF Keyswitch, non-illuminated Keyswitch, fully illuminated Force/Travel Diagram – Keyswitch RF 15 H Circuit Diagram – Keyswitch RF 15 H Dimensional Drawing Hole Pattern Hole Pattern – Front Panel Stock items are marked by bold printed order numbers. 4 - 44 PCB Keyswitches 4 RF RF short-travel keyswitches Description Photo Order no. Page Accessories RF 15 H short-travel keyswitch O-ring, black, for blocking the operating stroke 5.30.120.009/0100 5 - 27 RF 15 H short-travel keyswitch, non-illuminated overall height housing actuator lens illuminated area Contact materials Illumination Colour of lens LED colour LED type Order no. Au not illuminated white 3.14.100.702/0000 Ag not illuminated white 3.14.100.707/0000 Technical data see page 4 - 42 Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 45 4 RF RF short-travel keyswitches RF 15 H short-travel keyswitch, fully illuminated overall height housing actuator lens illuminated area Pict.: yellow Contact materials Illumination Colour of lens LED colour LED type Order no. Au fully illuminated 2 LEDs red red 2 mm 3.14.200.731/0000 Au fully illuminated 2 LEDs green green 2 mm 3.14.200.732/0000 Au fully illuminated 1 LED green green super bright 3 mm 3.14.200.736/0000 Au fully illuminated 2 LEDs yellow yellow 2 mm 3.14.200.733/0000 Au fully illuminated 1 LED white white 3 mm 3.14.200.735/0000 Au fully illuminated 2 LEDs orange yellow 2 mm 3.14.200.738/0000 Au fully illuminated 1 LED blue blue 3 mm 3.14.200.739/0000 Au fully illuminated 2 LEDs white multi colour 3 mm 3.14.100.734/0000 Ag fully illuminated 2 LEDs red red 2 mm 3.14.200.741/0000 Ag fully illuminated 2 LEDs green green 2 mm 3.14.200.742/0000 Ag fully illuminated 1 LED green green super bright 3 mm 3.14.200.746/0000 Ag fully illuminated 2 LEDs yellow yellow 2 mm 3.14.200.743/0000 Ag fully illuminated 1 LED white white 3 mm 3.14.200.745/0000 Ag fully illuminated 2 LEDs orange yellow 2 mm 3.14.200.748/0000 Ag fully illuminated 1 LED blue blue 3 mm 3.14.200.749/0000 Ag fully illuminated 2 LEDs white multi colour 3 mm 3.14.100.744/0000 Technical data see page 4 - 42 When using the keyswitches with multicolour LEDs the illumination colour can be varied from red to green by change of polarity. Due to the frequency of the polarity-changes the colours red, green, yellow as well as all secondary colours from these are possible. Technical data of LED see seperate page of the beginning of this chapter. 4 - 46 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 signal indicator Pict.: green Technical data General information Colour of lens see order block Recommended key grid 19.05 mm Dimensions Length 15 mm Width 15 mm Overall height 9.7 mm Mechanical design Mounting soldering into PCB Illumination fully illuminated 1 LED LED colour see order block LED type 2 mm Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 47 4 RF Dimensional Drawing Signal Indicator RF 15 Hole Pattern Hole Pattern – Front Panel No metal webs with 15.24 mm. View on component side. All hole diameters 1,1 +/- 0,1 mm. RF short-travel keyswitches Stock items are marked by bold printed order numbers. 4 - 48 PCB Keyswitches 4 RF RF short-travel keyswitches RF 15 signal indicator, fully illuminated, 1 LED Pict.: green Overall height Illumination Colour of lens LED colour LED type Order no. 9.7 mm fully illuminated 1 LED red red 2 mm 3.14.200.051/0000 9.7 mm fully illuminated 1 LED green green 2 mm 3.14.200.052/0000 9.7 mm fully illuminated 1 LED yellow yellow 2 mm 3.14.200.053/0000 9.7 mm fully illuminated 1 LED orange yellow 2 mm 3.14.200.054/0000 9.7 mm fully illuminated 1 LED blue blue 2 mm 3.14.200.055/0000 Technical data see page 4 - 46 For more information, see LEDs. Technical data of LED see seperate page of the beginning of this chapter. 4 - 50 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch General data Application notes: RF 19 keys offer a large actuation area. When designing low-profile keyboards with a grid of >= 23 mm, frame webs remain free between the individual keys. The overlay can be glued onto these frame webs; we recommend area embossing over the keys for the overlay. Technical data General information Colour of lens see order block Recommended key grid 23 mm Dimensions Length 19.05 mm Width 19.05 mm Overall height 9.7 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination spot-/fully illuminated LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 51 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 Operation characteristic limits RF Keyswitch, non-illuminated Keyswitch, fully illuminated Keyswitch, spot-illuminated Force/Travel Diagram – Keyswitch RF 19 Circuit Diagram – Keyswitch RF 19 Dimensional Drawing 4 - 52 PCB Keyswitches 4 RF RF short-travel keyswitches * The LED may be positioned either on the left-hand or right-hand side. Standard version: LED on left-hand side View on component side, all hole diameters 1,1 +/- 0,1 mm Hole Patterns RF 19 Hole Patterns – Front Panel RF 19 Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 53 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, non-illuminated Contact materials Illumination Colour of lens LED colour LED type Order no. Au not illuminated transparent 3.14.001.001/0000 Ag not illuminated transparent 3.14.001.006/0000 Technical data see page 4 - 50 Stock items are marked by bold printed order numbers. 4 - 54 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, fully illuminated with 2 LEDs Contact materials Illumination Colour of lens LED colour LED type Order no. Au fully illuminated 2 LEDs red red 2 mm 3.14.002.011/0000 Au fully illuminated 2 LEDs green green 2 mm 3.14.002.012/0000 Au fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.013/0000 Au fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.014/0000 Au fully illuminated 2 LEDs blue blue 2 mm 3.14.002.015/0000 Ag fully illuminated 2 LEDs red red 2 mm 3.14.002.021/0000 Ag fully illuminated 2 LEDs green green 2 mm 3.14.002.022/0000 Ag fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.023/0000 Ag fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.024/0000 Ag fully illuminated 2 LEDs blue blue 2 mm 3.14.002.025/0000 Technical data see page 4 - 50 Technical data of LED see seperate page of the beginning of this chapter. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 55 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, 1 LED spot-illumination Pict.: red Contact materials Illumination Colour of lens LED colour LED type Order no. Au spot illumination 1 LED opaque white blue 3 mm 3.14.001.030/0000 Au spot illumination 1 LED transparent red 3 mm 3.14.001.031/0000 Au spot illumination 1 LED transparent green 3 mm 3.14.001.032/0000 Au spot illumination 1 LED transparent yellow 3 mm 3.14.001.033/0000 Ag spot illumination 1 LED opaque white blue 3 mm 3.14.001.040/0000 Ag spot illumination 1 LED transparent red 3 mm 3.14.001.041/0000 Ag spot illumination 1 LED transparent green 3 mm 3.14.001.042/0000 Ag spot illumination 1 LED transparent yellow 3 mm 3.14.001.043/0000 Technical data see page 4 - 50 Versions with 2 LEDs available on request. Technical data of LED see seperate page of the beginning of this chapter. 4 - 56 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, 1 NC + 1 NO Technical data General information Recommended key grid 23 mm Dimensions Length 19.05 mm Width 19.05 mm Overall height 9.7 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system bridge contact Contact arrangement 1 NC + 1 NO Contact materials Au/Ag Illumination none Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0,02 V, Ag: 3 V V Rated voltage max. Au: 42 V, Ag: 50 V V Rated current min. Au: 0,01 mA, Ag: 0,1 mA mA Rated current max. Au: 100 mA, Ag: 250 mA mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 2 x 106 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 100000 Soldering time max. 5 sec. Soldering temperature max. 265 °C Flammability of materials UL 94 HB For keycaps, refer to RK 90. PCB Keyswitches 4 - 57 4 RF RF short-travel keyswitches Dimensional Drawing Hole Pattern Hole Pattern – Front Panel Circuit Diagram view on component side Stock items are marked by bold printed order numbers. 4 - 58 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 short-travel keyswitch, non-illuminated Contact materials Contact arrangement Illumination Colour of lens Order no. Au 1 NC + 1 NO not illuminated opaque white 1.16.000.991/0000 Ag 1 NC + 1 NO not illuminated opaque white 1.16.000.990/0000 Technical data see page 4 - 56 4 - 60 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 H short-travel keyswitch General data Application notes: The RF 19H key has an overall height of 12.5 mm and can be fully illuminated. When designing membrane keyboards, we recommend using a key grid of at least 23 mm and a 0.13 mm overlay with area embossing over the keys. You can use the O-ring (accessory) to block the key and use it as an indicator field or blank spaceholder. Technical data General information Colour of lens see order block Recommended key grid 24 mm Dimensions Length 19.05 mm Width 19.05 mm Overall height 12.5 mm Mechanical design Mounting soldering into PCB Terminals contacts tin-plated, fix contact Ag plated Contact system snap-action contact Contact arrangement 1 NO Contact materials Au/Ag Illumination spot-/fully illuminated LED colour see order block LED type see order block Mechanical characteristics Operating force max. 2 ... 3 N Operating travel 0.5 mm Switching travel 0.5 mm Robustness min. with through-plated PCB 100 N Electrical characteristics Rated voltage min. Au: 0.02 V, Ag: 3 V Rated voltage max. Au: 42 V, Ag: 50 V Rated current min. Au: 0,01 mA, Ag: 0,1 mA Rated current max. Au: 100 mA, Ag: 250 mA Rated power max. (ohmic load) Au: 2 W, Ag: 12.5 W Contact resistance when new max. 100 mΩ Contact resistance acc. to life max. 3 Ω Insulation resistance 109 Ω ESD strength (underneath overlay) 15 kV Bouncing time max. 5 ms Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Operating life min. 1,000,000 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 61 4 RF RF short-travel keyswitches F 1 = Max. operating force F 2 = Force at contact F 2 is max. 55% of F 1 Operation characteristic limits RF Keyswitch, non illuminated Keyswitch, fully illuminated Force/Travel Diagram – Keyswitch RF 19 H Circuit Diagram – Keyswitch RF 19 H Dimensional Drawing 4 - 62 PCB Keyswitches 4 RF Stock items are marked by bold printed order numbers. RF short-travel keyswitches Description Photo Order no. Page Accessories RF 19 H short-travel keyswitch O-ring, black, 17.0 x 1.5, for blocking RF 19H keys 5.30.125.003/0100 5 - 27 RF 19 H keyswitch, non-illuminated Contact materials Illumination Colour of lens LED colour LED type Order no. Au not illuminated white 3.14.001.501/0000 Ag not illuminated white 3.14.001.506/0000 Technical data see page 4 - 60 * The LED may be positioned either on the left-hand or right-hand side. Standard version: LED on left-hand side View on component side, all hole diameters 1,1 +/- 0,1 mm Hole Pattern RF 19 H Hole Pattern – Front Panel RF 19 H LED Keyswitch not illuminated Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 63 4 RF RF short-travel keyswitches RF 19 H short-travel keyswitch, fully illuminated Contact materials Illumination Colour of lens LED colour LED type Order no. Au fully illuminated 2 LEDs red red 2 mm 3.14.002.613/0000 Au fully illuminated 2 LEDs green green 2 mm 3.14.002.632/0000 Au fully illuminated 1 LED green green super bright 3 mm 3.14.002.633/0000 Au fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.653/0000 Au fully illuminated 1 LED white white 3 mm 3.14.002.684/0000 Au fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.673/0000 Au fully illuminated 2 LEDs white multi colour 3 mm 3.14.001.672/0000 Au fully illuminated 1 LED blue blue 3 mm 3.14.002.683/0000 Ag fully illuminated 2 LEDs red red 2 mm 3.14.002.623/0000 Ag fully illuminated 2 LEDs green green 2 mm 3.14.002.642/0000 Ag fully illuminated 1 LED green green super bright 3 mm 3.14.002.643/0000 Ag fully illuminated 1 LED blue blue super bright 3 mm 3.14.002.688/0000 Ag fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.663/0000 Ag fully illuminated 1 LED white white 3 mm 3.14.002.689/0000 Ag fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.678/0000 Ag fully illuminated 2 LEDs white multi colour 3 mm 3.14.001.682/0000 Technical data see page 4 - 60 When using the keyswitches with multicolour LEDs the illumination colour can be varied from red to green by change of polarity. Due to the frequency of the polarity-changes the colours red, green, yellow as well as all secondary colours from these are possible. Technical data of LED see seperate page of the beginning of this chapter. 4 - 64 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 signal indicator 1 x 2-module 0.5 x 2-module 1 x 1-module Pict.: 0.5 x 1-module Technical data General information Colour of lens see order block Recommended key grid 23/x mm Dimensions Length see order block Width see order block Overall height 9.15 mm Mechanical design Mounting soldering into PCB Illumination see order block LED colour see order block LED type see order block Other specifications Ambient temp. operating min. -25 °C Ambient temp. operating max. +70 °C Storage temperature min. -40 °C Storage temperature max. (product) +80 °C Storage temperature max. (in tube) +50 °C Resistance to constant environment according to IEC 600 68-2-3 and 2-30 Resistance at variable environment according to IEC 600 68-2-14 and 2-33 Soldering time max. 2,5 sec. Soldering temperature max. 250 °C Flammability of materials UL 94 HB PCB Keyswitches 4 - 65 4 RF RF short-travel keyswitches * The LED may be positioned either on the left-hand or right-hand side. Standard verstion: LED on left-hand side View on component side, all hole diameters 1,1 +/- 0,1 mm Front panel cut-out = outer keyswitch size + 1 mm Dimensional Drawing Signal Indicator RF 19 Hole Patterns RF 19 Stock items are marked by bold printed order numbers. 4 - 66 PCB Keyswitches 4 RF RF short-travel keyswitches RF 19 signal indicator, 1/2 x 1-module Housing Lens Illuminated area 16.4 x 7.8 mm Pict.: 0,5 x 1-module, yellow Illumination Colour of lens LED colour LED type Order no. fully illuminated 1 LED red red 2 mm 3.14.002.061/0000 fully illuminated 1 LED green green 2 mm 3.14.002.062/0000 fully illuminated 1 LED yellow yellow 2 mm 3.14.002.063/0000 fully illuminated 1 LED orange yellow 2 mm 3.14.002.064/0000 Technical data see page 4 - 64 For more information, see LEDs. RF 19 signal indicator, 1/2 x 2-module Pict.: 0,5 x 2-module, yellow Illumination Colour of lens LED colour LED type Order no. fully illuminated 3 LEDs red red 2 mm 3.14.002.908/0000 fully illuminated 3 LEDs green green 2 mm 3.14.002.909/0000 fully illuminated 3 LEDs yellow yellow 2 mm 3.14.002.910/0000 fully illuminated 3 LEDs orange yellow 2 mm 3.14.002.911/0000 Technical data see page 4 - 64 For more information, see LEDs. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 67 4 RF RF short-travel keyswitches RF 19 signal indicator, 1 x 1-module Pict.: 1 x 1-module, green Illumination Colour of lens LED colour LED type Order no. fully illuminated 2 LEDs red red 2 mm 3.14.002.051/0000 fully illuminated 2 LEDs green green 2 mm 3.14.002.052/0000 fully illuminated 2 LEDs yellow yellow 2 mm 3.14.002.053/0000 fully illuminated 2 LEDs orange yellow 2 mm 3.14.002.054/0000 fully illuminated 2 LEDs blue blue 2 mm 3.14.001.659/0000 Technical data see page 4 - 64 For more information, see LEDs. Suitable for RK 90 system design, illuminated for 2-module keycap. RF 19 signal indicator, 1 x 2-module Pict.: 1 x 2-module, red Illumination Colour of lens LED colour LED type Order no. fully illuminated 5 LEDs red red 2 mm 3.14.002.071/0000 fully illuminated 5 LEDs green green 2 mm 3.14.002.072/0000 fully illuminated 5 LEDs yellow yellow 2 mm 3.14.002.073/0000 fully illuminated 5 LEDs orange yellow 2 mm 3.14.002.074/0000 Technical data see page 4 - 64 For more information, see LEDs. Stock items are marked by bold printed order numbers. 4 - 68 PCB Keyswitches 4 RF RF short-travel keyswitches RF special accessories Pict.: light grey round and triangular versions Extension plunger for RF 15 N, round head Pict.: light grey Length Width Overall height Diameter Colour Order no. 9 mm 10 mm 5.46.011.036/0710 9.7 mm 10 mm 5.46.011.030/0710 12.5 mm 10 mm 5.46.011.037/0710 13 mm 10 mm 5.46.011.038/0710 22.5 mm 10 mm 5.46.011.028/0710 Length of plunger = Overall height - 4.25 mm. Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 69 4 RF RF short-travel keyswitches Extension plunger for RF 15 N, round head, with recess for LED Length Width Overall height Diameter Colour Order no. 9 mm 15 mm 5.46.017.036/0710 9.7 mm 15 mm 5.46.017.030/0710 12.5 mm 15 mm 5.46.017.037/0710 13 mm 15 mm 5.46.017.038/0710 22.5 mm 15 mm 5.46.017.028/0710 Keycap for RF 15, snap-on, for overall height 12.5 mm Length Width Overall height Diameter Colour Order no. 14.2 mm 14.2 mm 12.5 mm beige 5.46.654.059/0227 Stock items are marked by bold printed order numbers. 4 - 70 PCB Keyswitches 4 RF RF short-travel keyswitches Spacers, round Overlay Front panel Spacer PCB Length Width Overall height Diameter Colour Order no. 6.2 mm blue 5.30.759.251/0000 9.00 mm green 5.30.759.046/0000 3.50 mm blue transparent 5.30.759.023/0000 4 mm green 5.30.759.025/0000 4.25 mm blue 5.30.759.026/0000 4.50 mm red 5.30.759.027/0000 4.75 mm blue transparent 5.30.759.028/0000 5 mm black 5.30.759.029/0000 5.25 mm yellow orange transparent 5.30.759.030/0000 5.50 mm yellow 5.30.759.031/0000 5.75 mm green 5.30.759.032/0000 6 mm blue 5.30.759.033/0000 6.25 mm red 5.30.759.034/0000 6.50 mm blue transparent 5.30.759.035/0000 6.75 mm black 5.30.759.036/0000 7 mm yellow orange transparent 5.30.759.037/0000 7.25 mm yellow 5.30.759.038/0000 7.50 mm green 5.30.759.039/0000 7.75 mm blue 5.30.759.040/0000 8 mm red 5.30.759.041/0000 8.25 mm blue transparent 5.30.759.042/0000 10.00 mm black 5.30.759.043/0104 Stock items are marked by bold printed order numbers. PCB Keyswitches 4 - 71 4 RF RF short-travel keyswitches Spacers, triangular Countersink from height > 4 mm Overlay Front panel Spacer PCB Length Width Overall height Diameter Colour Order no. 6.2 mm blue 5.30.759.253/0000 2.50 mm blue 5.30.759.094/0000 2.75 mm red 5.30.759.095/0000 3 mm blue transparent 5.30.759.096/0000 3.25 mm black 5.30.759.097/0000 3.50 mm yellow orange transparent 5.30.759.098/0000 3.75 mm yellow 5.30.759.099/0000 4 mm green 5.30.759.100/0000 4.25 mm blue 5.30.759.101/0000 4.50 mm red 5.30.759.102/0000 4.75 mm blue transparent 5.30.759.103/0000 5 mm black 5.30.759.104/0000 5.25 mm yellow orange transparent 5.30.759.105/0000 5.50 mm yellow 5.30.759.106/0000 5.75 mm green 5.30.759.107/0000 6 mm blue 5.30.759.108/0000 6.25 mm red 5.30.759.109/0000 6.50 mm blue transparent 5.30.759.110/0000 6.75 mm black 5.30.759.111/0000 7 mm yellow orange transparent 5.30.759.112/0000 7.25 mm yellow 5.30.759.113/0000 7.50 mm green 5.30.759.114/0000 7.75 mm blue 5.30.759.115/0000 Stock items are marked by bold printed order numbers. 4 - 72 PCB Keyswitches 4 RF RF short-travel keyswitches Length Width Overall height Diameter Colour Order no. 8 mm red 5.30.759.116/0000 8.25 mm blue transparent 5.30.759.117/0000 10.00 mm black 5.30.759.124/0000 10.25 mm yellow orange transparent 5.30.759.125/0000 LED spacer for RF 15 N Pict.: light grey Length Characteristic 1 Width Overall height Order no. Characteristic 2 Diameter Colour 2.2 mm 12.5 mm 5 mm light grey 5.30.109.010/0756 12 mm 22.5 mm 5 mm black 5.30.109.019/0105 9 mm blue 5.30.759.254/0000 TL082 Wide Bandwidth Dual JFET Input Operational Amplifier General Description These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage (BI-FET II™ technology). They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The TL082 is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and most LM358 designs. These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Features n Internally trimmed offset voltage: 15 mV n Low input bias current: 50 pA n Low input noise voltage: 16nV/√Hz n Low input noise current: 0.01 pA/√Hz n Wide gain bandwidth: 4 MHz n High slew rate: 13 V/μs n Low supply current: 3.6 mA n High input impedance: 1012Ω n Low total harmonic distortion: ≤0.02% n Low 1/f noise corner: 50 Hz n Fast settling time to 0.01%: 2 μs Typical Connection 00835701 Connection Diagram DIP/SO Package (Top View) 00835703 Order Number TL082CM or TL082CP See NS Package Number M08A or N08E Simplified Schematic 00835702 BI-FET II™ is a trademark of National Semiconductor Corp. August 2000 TL082 Wide Bandwidth Dual JFET Input Operational Amplifier © 2004 National Semiconductor Corporation DS008357 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ±18V Power Dissipation (Note 2) Operating Temperature Range 0°C to +70°C Tj(MAX) 150°C Differential Input Voltage ±30V Input Voltage Range (Note 3) ±15V Output Short Circuit Duration Continuous Storage Temperature Range −65°C to +150°C Lead Temp. (Soldering, 10 seconds) 260°C ESD rating to be determined. Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. DC Electrical Characteristics (Note 5) Symbol Parameter Conditions TL082C Units Min Typ Max VOS Input Offset Voltage RS = 10 kΩ, TA = 25°C 5 15 mV Over Temperature 20 mV ΔVOS/ΔT Average TC of Input Offset RS = 10 kΩ 10 μV/°C Voltage IOS Input Offset Current Tj = 25°C, (Notes 5, 6) 25 200 pA Tj ≤ 70°C 4 nA IB Input Bias Current Tj = 25°C, (Notes 5, 6) 50 400 pA Tj ≤ 70°C 8 nA RIN Input Resistance Tj = 25°C 1012 Ω AVOL Large Signal Voltage Gain VS = ±15V, TA = 25°C 25 100 V/mV VO = ±10V, RL = 2 kΩ Over Temperature 15 V/mV VO Output Voltage Swing VS = ±15V, RL = 10 kΩ ±12 ±13.5 V VCM Input Common-Mode Voltage VS = ±15V ±11 +15 V Range −12 V CMRR Common-Mode Rejection Ratio RS ≤ 10 kΩ 70 100 dB PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB IS Supply Current 3.6 5.6 mA TL082 www.national.com 2 AC Electrical Characteristics (Note 5) Symbol Parameter Conditions TL082C Units Min Typ Max Amplifier to Amplifier Coupling TA = 25°C, f = 1Hz- −120 dB 20 kHz (Input Referred) SR Slew Rate VS = ±15V, TA = 25°C 8 13 V/μs GBW Gain Bandwidth Product VS = ±15V, TA = 25°C 4 MHz en Equivalent Input Noise Voltage TA = 25°C, RS = 100Ω, 25 nV/√Hz f = 1000 Hz in Equivalent Input Noise Current Tj = 25°C, f = 1000 Hz 0.01 pA/√Hz THD Total Harmonic Distortion AV = +10, RL = 10k, VO = 20 Vp − p, BW = 20 Hz−20 kHz <0.02 % Note 2: For operating at elevated temperature, the device must be derated based on a thermal resistance of 115°C/W junction to ambient for the N package. Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 4: The power dissipation limit, however, cannot be exceeded. Note 5: These specifications apply for VS = ±15V and 0°C ≤TA ≤ +70°C. VOS, IB and IOS are measured at VCM = 0. Note 6: The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, Tj. Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj = TA + θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = ±6V to ±15V. Typical Performance Characteristics Input Bias Current Input Bias Current 00835718 00835719 TL082 3 www.national.com Typical Performance Characteristics (Continued) Supply Current Positive Common-Mode Input Voltage Limit 00835720 00835721 Negative Common-Mode Input Voltage Limit Positive Current Limit 00835722 00835723 Negative Current Limit Voltage Swing 00835724 00835725 TL082 www.national.com 4 Typical Performance Characteristics (Continued) Output Voltage Swing Gain Bandwidth 00835726 00835727 Bode Plot Slew Rate 00835728 00835729 Distortion vs Frequency Undistorted Output Voltage Swing 00835730 00835731 TL082 5 www.national.com Typical Performance Characteristics (Continued) Open Loop Frequency Response Common-Mode Rejection Ratio 00835732 00835733 Power Supply Rejection Ratio Equivalent Input Noise Voltage 00835734 00835735 Open Loop Voltage Gain (V/V) Output Impedance 00835736 00835737 TL082 www.national.com 6 Typical Performance Characteristics (Continued) Inverter Setting Time 00835738 Pulse Response Small Signal Inverting 00835706 Small Signal Non-Inverting 00835707 Large Signal Inverting 00835708 Large Signal Non-Inverting 00835709 TL082 7 www.national.com Pulse Response (Continued) Current Limit (RL = 100Ω) 00835710 Application Hints These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±6V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kΩ load resistance to ±10V over the full temperature range of 0°C to +70°C. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. Because these amplifiers are JFET rather than MOSFET input op amps they do not require special handling. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. TL082 www.national.com 8 Detailed Schematic 00835711 Typical Applications Three-Band Active Tone Control 00835712 TL082 9 www.national.com Typical Applications (Continued) 00835713 • All potentiometers are linear taper • Use the LF347 Quad for stereo applications Note 8: All controls flat. Note 9: Bass and treble boost, mid flat. Note 10: Bass and treble cut, mid flat. Note 11: Mid boost, bass and treble flat. Note 12: Mid cut, bass and treble flat. Improved CMRR Instrumentation Amplifier 00835714 C and are separate isolated grounds Matching of R2’s, R4’s and R5’s control CMRR With AVT = 1400, resistor matching = 0.01%: CMRR = 136 dB • Very high input impedance • Super high CMRR TL082 www.national.com 10 Typical Applications (Continued) Fourth Order Low Pass Butterworth Filter 00835715 Fourth Order High Pass Butterworth Filter 00835716 TL082 11 www.national.com Typical Applications (Continued) Ohms to Volts Converter 00835717 TL082 www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted Order Number TL082CM NS Package M08A Order Number TL082CP NS Package N08E TL082 13 www.national.com Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com TL082 Wide Bandwidth Dual JFET Input Operational Amplifier UDG-02157 VIN VOUT 5 13 12 16 15 1 2 3 4 6 11 7 8 14 10 9 + - KFF RT BP5 SGND VIN BPN10 SW BP10 SYNC ILIM TPS40060PWP SS/SD VFB COMP HDRV LDRV PGND 8 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS40060, TPS40061 1FEATURES APPLICATIONS 2• Operating Input Voltage 10 V to 55 V • Networking Equipment • Input Voltage Feed-Forward Compensation • Telecom Equipment • < 1% Internal 0.7-V Reference • Base Stations • Programmable Fixed-Frequency, Up to 1-MHz • Servers Voltage Mode Controller • Internal Gate Drive Outputs for High-Side P- DESCRIPTION Channel and Synchronous N-Channel The TPS40060 and TPS40061 are high-voltage, wide MOSFETs input (10 V to 55 V) synchronous, step-down • 16-Pin PowerPAD™ Package (θ converters. JC = 2°C/W) • Thermal Shutdown This family of devices offers design flexibility with a variety of user programmable functions, including; • Externally Synchronizable soft-start, UVLO, operating frequency, voltage feed- • Programmable High-Side Sense Short Circuit forward, high-side current limit, and loop Protection compensation. These devices are also • Programmable Closed-Loop Soft-Start synchronizable to an external supply. • TPS40060 Source Only/TPS40061 Source/Sink The TPS40060 and TPS40061 incorporate MOSFET gate drivers for external P-channel high-side and Nchannel synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction. SIMPLIFIED APPLICATION DIAGRAM 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. THERMAL PAD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 KFF RT BP5 SYNC SGND SS/SD VFB COMP ILIM VIN HDRV BPN10 SW BP10 LDRV PGND PWP PACKAGE (1)(2) (TOP VIEW) TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA LOAD CURRENT PACKAGE(1) PART NUMBER SOURCE(2) Plastic HTSSOP (PWP) TPS40060PWP –40°C to 85°C SOURCE/SIN(2) Plastic HTSSOP (PWP) TPS40061PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40060PWPR). See the Application Information of the data sheet for PowerPAD drawing and layout information. (2) See Application Information section. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS40060 TPS40061 VIN 60 V VFB, SS/SD, SYNC –0.3 V to 6 V VIN Input voltage range SW –0.3 V to 60 V or VIN+5 V (whichever is less) SW. transient < 50 ns –2.5 V VOUT Output voltage range COMP, RT, KFF, SS –0.3 V to 6 V IIN Input current KFF 5 mA IOUT Output current RT 200 μA TJ Operating junction temperature range –40°C to 125°C Tstg Storage temperature –55°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VIN Input voltage 10 55 V TA Operating free-air temperature –40 85 °C (1) For more information on the PWP package, refer to TI Technical Brief (SLMA002). (2) PowerPAD™ heat slug must be connected to SGND (Pin 5), or electrically isolated from all other pins. 2 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VIN = 24 Vdc, RT = 165 kΩ, IKFF = 113 μA, fSW = 300 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range, VIN 10 55 V OPERATING CURRENT IDD Quiescent current Output drivers not switching 1.5 2.5 mA 5-V REFERENCE VBP5 Input voltage 4.5 5.0 5.5 V OSCILLATOR/RAMP GENERATOR(1) fOSC Frequency 270 300 330 kHz VRAMP PWM ramp voltage(2) 2 VIH High-level input voltage, SYNC 2 V VIL Low-level input voltage, SYNC 0.8 ISYNC Input current, SYNC 5 10 μA Pulse width, SYNC Pulse amplitude = 5 V 50 ns VRT RT voltage 2.32 2.50 2.68 V Maximum duty cycle VFB = 0 V, 100 kHz ≤ fSW≤ 1 MHz 85% 98% Minimum duty cycle VFB ≥ 0.75 V 0% VKFF Feed-forward voltage 3.35 3.50 3.65 V IKFF Feed-forward current operating range(2) 20 1100 μA SS/SD (SOFT START) ISS Soft-start source current 1.5 2.3 2.9 μA VSS Soft-start clamp voltage 3.1 3.7 4.0 V tDSCH Discharge time CSS = 220 pF 1.6 2.2 2.9 μs tSS Soft-start time CSS = 220 pF, 0 V ≤ VSS ≤ 1.6 V 120 155 235 SS/SD (SHUTDOWN) VSD Shutdown threshold voltage 90 130 160 VEN Device action threshold voltage 170 210 260 mV Hysteresis 80 10-V REFERENCE VBP10 Input voltage 9.0 9.7 10.7 V ERROR AMPLIFIER TA = 25°C 0.698 0.700 0.704 VFB Feedback regulation voltage 0°C ≤ TA ≤ 85°C 0.690 0.700 0.707 V 0.690 0.700 0.715 GBW Gain bandwidth 3 5 MHz AVOL Open loop gain 60 80 dB IOH High-level output source current VCOMP = 2.0 V, VFB = 0 V 1.5 4.0 mA IOL Low-level output sink current VCOMP = 2.0 V, VFB = 1 V 2.5 4.0 IBIAS Input bias current VFB = 0.7 V 100 300 nA VOH High-level output voltage IOH = 0.5 mA, VFB = 0 V 3.25 3.45 3.60 V VOL Low-level output voltage IOL = 0.5 mA, VFB = 1 V 0.050 0.215 0.350 (1) KFF current (IKFF) increases with SYNC frequency (fSYNC) and decreases with maximum duty cycle (DMAX). (2) Ensured by design. Not production tested. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 24 Vdc, RT = 165 kΩ, IKFF = 113 μA, fSW = 300 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT TA = 25°C 8.8 10.0 11.4 ISINK Current limit sink current 0°C ≤ TA ≤ 85°C 8.3 11.9 μA -40°C ≤ TA ≤ 0°C 7.5 11.5 VILIM = 23.7 V, VSW = (VILIM – 0.5 V) 330 500 tDELAY Propagation delay to output VILIM = 23.7 V, VSW = (VILIM – 2 V) 275 375 ns tON Switch leading-edge blanking pulse time(3) 100 tOFF Off time during a fault 7 cycles VOS Overcurrent comparator offset voltage -200 -60 50 mV OUTPUT DRIVER tHFALL High-side driver fall time(3) CHDRV = 2200 pF, (VIN – VBPN10) 48 96 tHRISE High-side driver rise time(3) CHDRV = 2200 pF, (VIN – VBPN10) 36 72 ns tLFALL Low-side driver fall time(3) CLDRV = 2200 pF, BP10 24 48 tLRISE Low-side driver rise time(3) CLDRV = 2200 pF, BP10 48 96 VOH High-level ouput voltage, HDRV IHDRV = 0.1 A , (VIN – VHDRV) 1.0 1.4 VOL Low-level ouput voltage, HDRV IHDRV = 0.1 A , (VHDRV – VBPN10) 0.75 V VOH High-level ouput voltage, LDRV ILDRV = 0.1 A, (VBP10 – VLDRV) 1.0 1.5 VOL Low-level ouput voltage, LDRV ILDRV = 0.1 A 0.5 Minimum controllable pulse width 100 150 ns BPN10 REGULATOR VBPN1 Output voltage Outputs off –7.5 –8.5 –9.5 V 0 RECTIFIER ZERO CURRENT COMPARATOR (TPS40060 ONLY) VSW Switch voltage LDRV output OFF –6 0 6 mV SW NODE ILEAK Leakage current(3) 1 μA THERMAL SHUTDOWN Shutdown temperature(3) 165 TSD °C Hysteresis(3) 25 UNDERVOLTAGE LOCKOUT VUVLO Undervoltage lockout threshold voltage, BP10 RKFF = 10 kΩ 6.25 6.5 7.5 Undervoltage lockout hysteresis 0.4 V VKFF KFF programmable threshold voltage RKFF = 82.5 kΩ 9 10 11 (3) Ensured by design. Not production tested. 4 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. 5-V reference. BP5 3 O This pin should be bypassed to ground with a 0.1-μF ceramic capacitor. This pin may be used with an external DC load of 1 mA or less. BP10 11 O 10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-μF ceramic capacitor. This pin may be used with an external DC load of 1 mA or less. BPN10 13 O Negative 8-V reference with respect to VIN. This voltage is used to provide gate drive for the high side P-channel MOSFET. This pin should be bypassed to VIN with a 0.1-μF capacitor Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the COMP 8 I VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve large signal transient response. HDRV 14 O Floating gate drive for the high-side P-channel MOSFET. This pin switches from VIN (MOSFET off) to BPN10 (MOSFET on). Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a ILIM 16 I voltage drop across an external resistor connected from this pin to VIN. The voltage on this pin is compared to the voltage drop (VIN -SW) across the high side MOSFET during conduction. KFF 1 I A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into this pin is internally divided and used to control the slope of the PWM ramp. LDRV 10 I Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET off). PGND 9 Power ground reference for the device. There should be a low-impedance connection from this point to the source of the power MOSFET. RT 2 I A resistor is connected from this pin to ground to set the internal oscillator ramp charging current and switching frequency. SGND 5 Signal ground reference for the device. Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 2.3 μA. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is approximately SS/SD 6 I 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V. The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive. The internal circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs cease switching and the output voltage (VOUT) decays while the internal circuitry remains active. SW 12 I This pin is connected to the switched node of the converter and used for overcurrent sensing. This pin is used for zero current sensing in the TPS40060. SYNC 4 I Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency. VFB 7 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V. VIN 15 I Supply voltage for the device. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS40060 TPS40061 1 2 7 + + 6 Ramp Generator Clock Oscillator 14 10 13 12 9 15 11 8 4 5 BP10 BP10 07VREF 7 7 16 3−bit up/down Fault Counter 7 7 7 07VREF 1V5REF 3V5REF Reference Voltages 7 Fault 7 Restart CLK 7 CLK BP5 7 3 BP5 7 7 Restart + 7 07VREF 7 7 Fault CL S Q R Q 7 CLK CL SW 7 SW S Q R Q 7 HDRV LDRV PGND BPN10 VIN BP10 SYNC RT KFF BP5 VFB SS/SD COMP ILIM SGND Zero Current Detector (TPS40060 Only) 10−V Regulator 7 1V5REF VIN 7 7 HDRV 7 HDRV 7 BPN10 7 + 0.85 V + N-Channel Driver P-Channel Driver UDG−02160 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com SIMPLIFIED BLOCK DIAGRAM 6 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 UDG-02131 RAMP COMP SW VIN VIN SW COMP RAMP VPEAK VVALLEY T2 tON1 > tON2 and d1 > d2 t tON2 ON1 d tON T T1 RT 1 fSW17.8210623 k TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 APPLICATION INFORMATION The TPS40060/61 family of parts allows the user to optimize the PWM controller to the specific application. The TPS40061 is the controller of choice for synchronous buck designs which will include most applications. It has two quadrant operation and will source or sink output current. This provides the best transient response. The TPS40060 operates in one quadrant and sources output current only, allowing for paralleling of converters and ensures that one converter does not sink current from another converter. This controller also emulates a standard buck converter at light loads where the inductor current goes discontinuous. At continuous output inductor currents the controller operates as a synchronous buck converter to optimize efficiency. SW NODE RESISTOR The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output current which flows during this dead time. This negative voltage could affect the operation of the controller, especially at low input voltages. Therefore, a 10-Ω resistor must be placed between the lower MOSFET drain and pin 12 (SW) of the controller as shown in Figure 14 as RSW. SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS40060 and TPS40061 have independent clock oscillator and ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by a single resistor (RT) to ground. The clock frequency is related to RT, in kΩ by Equation 1 and the relationship is charted in Figure 2. (1) PROGRAMMING THE RAMP GENERATOR CIRCUIT The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1). Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS40060 TPS40061 RKFF VIN (min)3.565.27RT1502 () 100 0 200 300 400 500 600 400 600 800 1000 700 200 800 FEED-FORWARD IMPEDANCE vs SWITCHING FREQUENCY RKFF - Feed-Forward Impedance - kW fSW - Switching Frequency - kHz VIN = 25 V VIN = 15 V VIN = 9 V RT - Timing Resistance - kW fSW - Switching Frequency - kHz TIMING RESISTANCE vs SWITCHING FREQUENCY 0 100 0 200 400 600 800 1000 200 300 400 500 600 RKFF VIN (min)3.565.27RT1502 () TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the minimum input voltage, VIN(min) through the following: where: • VIN is the desired start-up (UVLO) input voltage • RT is the timing resistor in kΩ (2) See the section on UVLO operation for further description. The curve showing the feedforward impedance required for a given switching frequency, fSW, at various input voltages is shown in Figure 3. For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltages. For more information on large duty cycle operation, refer to Application Note (SLUA310). Figure 2. Figure 3. UVLO OPERATION The TPS40060 and TPS40061 use both fixed and variable (user programmable) UVLO protection. The fixed UVLO monitors the BP10 and BP5 bypass voltages. The UVLO circuit holds the soft-start low until the BP5 and BP10 voltage rails have exceeded their thresholds and the input voltage has exceed the user programmable undervoltage threshold. The TPS40060 and TPS40061 use the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage condition exists if the device receives a clock pulse before the ramp has reached 90% of its full amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor can be referenced to the oscillator frequency as described in Equation 3: 8 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 10 15 0.5 0 1.0 1.5 2.0 2.5 3.0 20 25 30 35 40 45 50 45 VUVLO - Output Voltage - V VUVLO - Undervoltage Lockout Threshold - V UNDERVOLTAGE LOCKOUT vs HYSTERESIS UDG-02132 Clock PWM RAMP PowerGood VIN UVLO Threshold 1 2 3 4 5 6 7 1 2 1 2 3 4 5 6 7 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 where: • VIN is the desired start-up (UVLO) input voltage • RT is the timing resistor in kΩ (3) The variable UVLO function utilizes a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter the clock cycle a powergood signal is asserted, a soft-start initiated, and the upper and lower MOSFETs are turned off. Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp duration is longer than the clock cycle before an undervoltage condition is declared (See Figure 4). Figure 4. Undervoltage Lockout Operation Figure 5. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS40060 TPS40061 CSS 2.3 A 0.7 V tSTART (Farads) tSTART 2LCO (seconds) TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com The impedance of the input voltage can cause the input voltage, at the TPS4006x, to sag when the converter starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen to select the start-up voltage, the amount of hysteresis voltage is shown in Figure 5. PROGRAMMING SOFT START TPS4006x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on CSS minus 0.85 V, is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V VREF). The loop is closed on the lower of the (VCSS – 0.85 V) voltage or the internal reference voltage (0.7-V VREF). Once the (VCSS – 0.85 V) voltage rises above the internal reference voltage, regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-CO time constant as described in Equation 4. (4) There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the higher the input current required during start-up. This relationship is describe in more detail in the section titled, Programming the Current Limit, which follows. The soft-start capacitance, CSS, is described in Equation 5. For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO tripping. The soft-start time should be longer than the time that the VINsupply transitions between 6 V and 7 V. (5) 10 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 RILIM IOCRDS(on)[max] ISINK VOS ISINK () ( ) ( ) O O LIM LOAD START C V I I A t é ´ ù = ê ú + ë û TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 PROGRAMMING CURRENT LIMIT This device uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when the gate is driven low. The MOSFET voltage is compared to the voltage dropped across a resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 7 for typical overcurrent protection waveforms. The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at start-up (ILOAD). (6) The current limit programming resistor (RILIM) is calculated using Equation 7. Care must be taken in choosing the values used for VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level, the minimum value of ISINK and the maximum value of VOS must be used. where: • ISINK is the current into the ILIM pin and is nominally 8.3 μA, minimum • IOC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current • VOS is the overcurrent comparator offset and is 50 mV maximum (7) BP5, BP10 AND BPN10 INTERNAL VOLTAGE REGULATOR Start-up characteristics of the BP5, BP10 and BPN10 regulators are shown in Figure 7. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BPN10 and BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS40060 TPS40061 VBPx - Output Voltage - V VIN - Input Voltage - V INTERNAL REGULATOR OUTPUT VOLTAGE vs INPUT VOLTAGE 2 4 6 8 10 12 6 8 10 12 2 4 0 BP10 BP5 BPN10 UDG-02136 HDRV CLOCK VVIN-VSW SS 7 CURRENT LIMIT TRIPS (HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP) 7 SOFT-START CYCLES VILIM tBLANKING TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com Figure 6. Typical Current Limit Protection Waveforms Figure 7. CALCULATING THE BPN10 AND BP10V BYPASS CAPACITOR The BPN10 capacitance provides energy for the high-side driver. The BPN10 capacitor should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate charge of the high-side MOSFET and the amount of droop allowed on the bypass capacitor. The BPN10 capacitance is described in Equation 8. 12 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 L VINVOVO VINIfSW (H) KFF ( IN(min) ) ( T(dummy) ) R = V - 3.5V ´ 65.27 ´R +1502 W RT(dummy) 1 fSYNC17.8210623 k CBP10V QgSR V (F) CBPN10 Qg V (F) TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 (8) The 10-V reference pin, BP10V needs to provide energy for the synchronous MOSFET gate drive via the BP10V capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 9. (9) SYNCHRONIZING TO AN EXTERNAL SUPPLY The TPS4006x can be synchronized to an external clock through the SYNC pin. The SW node rises on the falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4006x to freely run at the frequency programmed by RT. Internally, the SYNC pin has a pull-down current between 5 μA and 10 μA. In order to synchronize the device to an external clock signal, the SYNC pin has to be overdriven from the external clock circuit. Normal logic gates or an external MOSFET with a pull-up resistor of 10 kΩ is adequate. Internally there is a delay of between approximately 50 ns and 100 ns from the time the SYNC pin is pulled low and the HDRV signal goes low to turn on the upper MOSFET. Additionally, there is some delay as the MOSFET gate charges to turn on the upper MOSFET, typically between 20 ns and 50 ns. The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a 'dummy' value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the design. where: • fSYNC is the synchronous frequency in kHz (10) Use the value of RT(dummy) to calculate the value for RKFF. where: • RT(dummy) is in kΩ (11) This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency. SELECTING THE INDUCTOR VALUE The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in Equation 12. where: • VO is the output voltage • ΔI is the peak-to-peak inductor current (12) Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: TPS40060 TPS40061 CO LIOH 2 IOL 2 Vf 2 Vi 2 (F) V2 Vf 2 Vi 2 Volts2 EC 12 CV2 (J) I2 IOH 2 IOL 2 (Amperes)2 EL 12 LI2 (J) V I ESR 1 8COfSW VPP TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com CALCULATING THE OUTPUT CAPACITANCE The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any output voltage deviation requirement during a load transient. The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output ripple is described in Equation 13. (13) The output ripple voltage is typically between 90% and 95% due to the ESR component. The output capacitance requirement typically increases in the presence of a load transient requirement. During a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess inductor energy (heavy-to-light load step) while maintaining the output voltage within acceptable limits. The amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the inductor. Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in Equation 14 and Equation 15. (14) where: where: • IOH is the output current under heavy load conditions • IOL is the output current under light load conditions (15) Energy in the capacitor is given by the following equation: (16) where: where: • Vf is the final peak capacitor voltage • Vi is the initial capacitor voltage (17) By substituting Equation 15 into Equation 14, substituting Equation 17 into Equation 16, setting Equation 14 equal to Equation 16 and solving for CO yields the following equation. (18) Loop Compensation Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40060 and TPS40061 use voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be included. The generic modulator gain is described in Figure 8. 14 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 fC fSW 4 (Hertz) BIAS O 0.7 R1 R V 0.7 ´ = W - fZ 1 2ESRCO (Hz) fLC 1 2LCO (Hz) ( ) ( ) IN min IN(min) MOD MOD dB RAMP RAMP V V A or A 20 log V V æ ö æ ö = ç ÷ = ´ ç ÷ ç ÷ ç ÷ è ø è ø D VO VIN VC VS or VO VC VIN VS TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 Duty cycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage, (19) With the voltage feedforward function, the ramp slope is proportional to the input voltage. Therefore, the moderator DC gain is independent of the change of input voltage. For the TPS40060 and TPS40061 the modulator dc gain is shown in Equation 20, with VIN(min) as the minimum input voltage required to cause the ramp excursion to reach the maximum ramp amplitude of VRAMP. (20) Calculate the Poles and Zeros For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole is located at the frequency calculated in Equation 21. (21) There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at the frequency calculated in Equation 22. (22) Calculate the value of RBIAS to set the output voltage, VO. (23) The maximum crossover frequency (0 dB loop gain) is set by Equation 24. (24) Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this frequency, the control to output gain has a –2 slope (-40 dB/decade), while the Type III topology has a +1 slope (20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 9 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated. A Type III topology, shown in Figure 10, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 11. The two zeros are used to compensate the L-CO double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier's gain roll-off used to roll-off the overall gain at higher frequencies. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: TPS40060 TPS40061 fC 1 2R1C2G (Hertz) fP1 1 2R2C2 (Hz) fP2 1 2R3C3 (Hz) fZ1 1 2R2C1 (Hz) fZ2 1 2R1C3 (Hz) RBIAS UDG−02189 + R1 R3 C3 C2 (optional) C1 R2 7 8 VREF COMP VFB VOUT GAIN 180° −90° −270° PHASE + 1 − 1 − 1 0 dB MODULATOR GAIN vs SWITCHING FREQUENCY ModulatorGain - dB fSW - Switching Frequency - Hz 100 1 k 10 k 100 k ESR Zero, + 1 LC Filter, - 2 AMOD = VIN(min) / VRAMP Resultant, - 1 VC PWM MODULATOR RELATIONSHIPS VS D = VC / VS TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com Figure 8. Figure 9. Figure 10. Type III Compensation of Configuration Figure 11. Type III Compensation Gain and Phase The poles and zeros for a type III network are described in Equation 25. (25) The value of R1 is somewhat arbitrary, but influences other component values. A value between 50kΩ and 100kΩ usually yields reasonable values. The unity gain frequency is described in Equation 26. where • G is the reciprocal of the modulator gain at fC (26) 16 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 PSW(fsw) VINIOUTtSWfSW (Watts) IRMS IOd AmperesRMS PCOND IRMS 2 RDS(on)1TCRTJ25OC (W) R2(MIN) VC (max) ISOURCE (min) () 3.45 V 2.0 mA 1.725 k AMOD(f) AMODfLC fC 2 and G 1 AMOD(f) TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 The modulator gain as a function of frequency at fC, is described in Equation 27. (27) Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current which must be considered when sizing R2. Too small a value does not allow the output to swing over its full range. (28) dv/dt INDUCED TURN-ON MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through currents. Therefore the SR MOSFET should be chosen so that the CGD capacitance is smaller than the CGS capacitance. A 2-Ω to 5-Ω resistor in the upper MOSFET gate lead shapes the turn-on and dv/dt of the SW node and helps reduce the induced turn-on. HIGH-SIDE MOSFET POWER DISSIPATION The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The high-side MOSFET conduction losses are defined by Equation 29. where: • TCR is the temperature coefficient of the MOSFET RDS(on) (29) The TCR varies depending on MOSFET technology and manufacturer but is typically ranges between 3500 ppm/°C and 1000 ppm/°C. The IRMS current for the high side MOSFET is described in Equation 30. (30) The switching losses for the high-side MOSFET are described in Equation 31. where: • IO is the DC output current • tSW is the switching rise time, typically < 20 ns • fSW is the switching frequency (31) Typical switching waveforms are shown in Figure 12. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TPS40060 TPS40061 PSR PDCPRRPCOND (W) PRR 0.5QRRVINfSW (W) PDC 2IOVFtDELAYfSW (W) IRMS IO1d ARMS PT PCONDPSW(fsw) (W) PT TJTA JA (W) UDG-02179 DI ANTI-CROSS CONDUCTION SYNCHRONOUS RECTIFIER ON BODY DIODE CONDUCTION BODY DIODE CONDUCTION HIGH SIDE ON ID1 ID2 IO SW 0 d 1-d TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com Figure 12. Inductor Current and SW Node Waveforms The maximum allowable power dissipation in the MOSFET is determined by the following equation. (32) where: (33) and ΘJA is the package thermal impedance. SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be found using Equation 29 and the RMS current through the synchronous rectifier MOSFET is described in Equation 34. (34) The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross conduction delay time. The body diode conduction losses are described by Equation 35. where: • VF is the body diode forward voltage • tDELAY is the delay time just before the SW node rises (35) The 2-multiplier is used because the body-diode conducts twice during each cycle (once on the rising edge and once on the falling edge) The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a reverse blocking state. The reverse recovery losses are described in Equation 36. where: • QRR is the reverse recovery charge of the body diode (36) The total synchronous rectifier MOSFET power dissipation is described in Equation 37. (37) 18 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 ( ) ( ) ( ) ( ) J A Q JA IN SW g T T I V f Hz 2 Q æ é - ù ö ç ê ú - ÷ ç êë q ´ úû ÷ = è ø ´ PT 2QgfSWIQVIN (W) PT 2PD VDR IQVIN (W) PD = Qg ´ VDR ´ fSW (W / driver) TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 TPS40060/TPS40061 POWER DISSIPATION The power dissipation in the TPS40060 and TPS40061 is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance, (refer to the second reference in the REFERENCES section) can be calculated from Equation 38. (38) And the total power dissipation in the device, assuming MOSFETs with similar gate charges for both the highside and synchronous rectifier is described in Equation 39. (39) or where: • IQ is the quiescent operating current (neglecting drivers) (40) The maximum power capability of the device's PowerPad package is dependent on the layout as well as air flow. The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow. ΘJA = 36.51°C/W The maximum allowable package power dissipation is related to ambient temperature by Equation 36. Substituting Equation 32 into Equation 40 and solving for fSW yields the maximum operating frequency for the TPS40060 and TPS40061. The result is: (41) Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com LAYOUT CONSIDERATIONS THE PowerPAD™ PACKAGE The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the dimensions of the circuit board pad are 5 mm x 3.4 mm. The dimensions of the package pad are shown in Figure 13. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally Enhanced Package (see REFERENCES section) for more information on the PowerPAD package. Figure 13. PowerPAD Dimensions MOSFET PACKAGING MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on proper layout and thermal management. The θJAspecified in the MOSFET data sheet refers to a given copper area and thickness. In most cases, a thermal impedance of 40°C/W requires one square inch of 2-ounce copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please refer to the selected MOSFET's data sheet for more information regarding proper mounting. GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS The device provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor. Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The SGND plane should only make a single point connection to the PGND plane. 20 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 Component placement should ensure that bypass capacitors (BP10, BP5, and BPN10) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BPN10, and the switch node (SW). Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: TPS40060 TPS40061 PSW(fsw) VINIOtSWfSW 55 V5 A20 ns130 kHz 0.715 W PCOND 1.220.12(10.007(15025)) 0.324 W IRMS IOd 50.0588 1.2 A I IO20.2 520.2 2.0 A fSW 0.0588 400 ns 147 kHz 1 TSW fSW VO(min) VIN(max) TON VO(min) VIN(max) tON TSW or dMIN VO(min) VIN(max) 0.0588 dMAX VO(max) VIN(min) 0.187 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com DESIGN EXAMPLE • Input voltage: 18 VDC to 55 VDC • Output voltage: 3.3 V ±2% • Output current: 5 A (maximum, steady-state), 7 A (surge, 10-ms duration, 10% duty cycle maximum) • Output ripple: 33 mVP-P at 5 A • Output load response: 0.3 V => 10% to 90% step load change • Operating temperature: –40°C to 85°C • fSW = 130 kHz 1. Calculate maximum and minimum duty cycles (42) 2. Select switching frequency The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater than 330 ns (see Electrical Characteristics table). Therefore (43) (44) Using 400 ns to provide margin, (45) Since the oscillator can vary by 10%, decrease fSW, by 10% fSW = 0.9 × 147 kHz = 130 kHz and therefore choose a frequency of 130 kHz. 3. Select ΔI In this case ΔI is chosen so that the converter enters discontinuous mode at 20% of nominal load. (46) 4. Calculate the high-side MOSFET power losses Power losses in the high-side MOSFET (Si9407AGY) at 55-VIN where switching losses dominate can be calculated from Equation 46 through Equation 49. (47) substituting Equation 47 into Equation 29 yields (48) and from Equation 31, the switching losses can be determined. (49) The MOSFET junction temperature can be found by substituting Equation 33 into Equation 32 22 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 RT 1 fSW17.82 E0623 k 408 k, use 412 k (55 3.3) 3.3 L 11.9 H 55 2 130 kHZ - ´ = = m ´ ´ J SR JA A ( ) T = P ´ q + T = 0.644 ´ 40 + 85 = 111°C SR RR COND DC P = P ´P ´P = 0.107 + 0.485 + 0.052 = 0.644 W PRR 0.5QRRVINfSW 0.530 nC55 V130 kHz 0.107 W DC O FD DELAY SW P = 2´I ´ V ´ t ´ f = 2´ 5 A ´ 0.8 V ´ 50 ns ´130 kHZ = 0.052 W ( ( )) 2 COND P = 4.85 ´ 0.011´ 1+ 0.007 150 - 25 = 0.485 W IRMS IO1d 510.0588 4.85 ARMS TJ PCONDPSWJATA (0.3240.715)4085 127OC TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 (50) 5. Calculate synchronous rectifier losses The synchronous rectifier MOSFET has two loss components, conduction, and diode reverse recovery losses. The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead time associated with the anti-cross conduction delay. The IRMS current through the synchronous rectifier from Equation 51 (51) The synchronous MOSFET conduction loss from Equation 29 is: (52) The body diode conduction loss from Equation 35 is: (53) The body diode reverse recovery loss from Equation 36 is: (54) The total power dissipated in the synchronous rectifier MOSFET from Equation 37 is: (55) The junction temperature of the synchronous rectifier at 85°C is: (56) In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode conduction and reverse recovery periods. 6. Calculate the Inductor Value The inductor value is calculated from Equation 12. (57) A standard inductor value of 10-μH is chosen. A Coev DXM1306-10RO or Panasonic ETQPF102HFA could be used. 7. Setting the switching frequency The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be derived from following Equation 58, with fSW in kHz. (58) 8. Programming the Ramp Generator Circuit The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also controls the input UVLO voltage. For an undervoltage level of 14.4V (20% below the 18 VIN(min)), RKFF is calculated in Equation 59. RKFF = (80%xVIN(min) – 3.5)(65.27 ×RT + 1502) Ω = 309 kΩ, use 301 kΩ (59) Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: TPS40060 TPS40061 fZ 1 20.012180 F 74 kHz fLC 1 2 10 H180 F 3.7 kHz AMOD(dB) = 20 ´log(9) = 19 dB MOD 18 A 9 2 = = RILIM 100.14 ISINK VOS ISINK 100.14 8.3 A (50 mV) 8.3 A 175 k 174 k ILIM 180 F3.3 1 m 7.0 7.6 A CSS 2.3 A 0.7 V 1 ms 3.28 nF 3300 pF 33 mV 2.0ESR 1 8180 F130 kHz 33 mV 2.0ESR 1 8127 F130 kHz CO 10 H5212 3.323.02 127 F TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com 9. Calculating the Output Capacitance (CO) In this example. the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1 A to 5 A step load. CO can be calculated using Equation 18. (60) Using Equation 13 calculate the ESR required to meet the output ripple requirements. (61) ESR = 8.9 mΩ In order to get the required ESR, the capacitance needs to be greater than the 127-μF calculated. For example, a single Panasonic SP capacitor, 180-μF with ESR of 12 mΩ can be used. Re-calculating the ESR required with the new value of 180-μF is shown in Equation 62. (62) ESR = 11.1 mΩ 10. Calculate the Soft-Start Capacitor (CSS) This design requires a soft-start time (tSTART) of 1 ms. CSS is calculated in Equation 63. (63) 11. Calculate the Current Limit Resistor (RILIM) The current limit set point depends on tSTART, VO, CO and ILOAD at start up as shown in Equation 7. (64) Set ILIM for 10.0 A minimum, then from Equation 7 (65) 12. Calculate Loop Compensation Values Calculate the DC modulator gain (AMOD) from Equation 20. (66) (67) Calculate the output poles and zeros from Equation 21 and Equation 22 of the L-C filter. (68) and (69) Select the close-loop 0 dB crossover frequency, fC. For this example fC = 10 kHz. Select the double zero location for the Type III compensation network at the output filter double pole at 3.7 kHz. Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7 kHz. 24 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 CBP10V QgSR V 57 nC 0.5 114 nF CBPN10 Qg V 30 nC 0.5 60 nF RBIAS 0.7 VR1 VO0.7 V 0.7 V100k 3.3 V0.7 V 26.9 k, choose 26.7 k Z1 1 1 f C1 4301pF, choose 3900 pF 2 R2 C1 2 10 k 3.7 kHz = \ = = p´ ´ p´ W´ P1 1 1 f R2 9.82 k , choose 10 k 2 R2 C2 2 220 pF 73.7 kHz = \ = = W W p´ ´ p´ ´ C 1 1 f C2 196 pF, choose 220 pF 2 R1 C2 G 2 100 k 0.81 10 kHz = \ = = p´ ´ ´ p´ W´ ´ P2 1 1 f R3 4.59 k , choose 4.64 k 2 R3 C3 2 470 pF 73.7 kHz = \ = = W W p´ ´ p´ ´ fZ2 1 2R1C3 C3 1 2100 k3.7 kHz 430 pF, choose 470 pF MOD(f ) 1 1 G 0.81 A 1.23 = = = 2 2 LC MOD(f ) MOD C f 3.7 kHz A A 9 1.23 f 10 kHz æ ö æ ö = ´ ç ÷ = ´ ç ÷ = è ø è ø TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 The amplifier gain at the crossover frequency of 10 kHz is determined by the reciprocal of the modulator gain AMOD at the crossover frequency from Equation 27. (70) And also from Equation 27. (71) Choose R1 = 100 kΩ The poles and zeros for a Type III network are described in Equation 25 and Equation 26. (72) (73) (74) (75) (76) Calculate the value of RBIAS from Equation 23 with R1 = 100 kΩ. (77) CALCULATING THE BPN10 AND BP10V BYPASS CAPACITANCE The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount of droop allowed on the bypass capacitor. The BPN10 capacitance, allowing for a 0.5-V droop on the BPN10 pin from Equation 8 is shown in Equation 78. (78) and the BP10V capacitance from Equation 9 is shown in Equation 79. (79) For this application, a 0.1-μF capacitor was used for the BPN10V and a 1.0-μF was used for the BP10V bypass capacitor. Figure 14 shows component selection for the 18-V through 55-V to 3.3-V at 5-A dc-to-dc converter specified in the design example. GATE DRIVE CONFIGURATION Due to the possibility of dv/dt induced turn-on from the fast MOSFET switching times, high VDS voltage and low gate threshold voltage of the Si4470, the design includes a 2-Ω in the gate lead of the upper MOSFET. The resistor can be used to shape the low-to-high transition of the Switch node and reduce the tendency of dv/dtinduced turn on. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: TPS40060 TPS40061 5 13 12 16 15 1 2 3 KFF RT BP5 SGND VIN BPN10 SW BP10 4 SYNC 11 ILIM TPS40060PWP 6 SS/SD 7 VFB 8 COMP HDRV 14 LDRV 10 PGND 9 + − + − PGND RILIM 174 kΩ 0.1 μF 2 Ω 10 μH Si4470 1.0 μF Si9407 CO 180 μF RT 412 kΩ RKFF 301 kΩ UDG−02161 0.1 μF CSS 3300 pF C1 3900 pF R2 10 kΩ R1 R3 100kΩ 4.64 kΩ C2 220 pF C3 470 pF RSW 10 Ω 30BQ060 RBIAS 26.7 kΩ VOUT VIN TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com Figure 14. Design Example, 48 V to 3.3 V at 5 A dc-to-dc Converter REFERENCES 1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2. 2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief: TI Literature No. SLMA002 26 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013 REVISION HISTORY Changes from Revision E (June 2006) to Revision F Page • Changed reference to Figure 13, PowerPad Dimensions, to Figure 14, Design Example, 48 V to 3.3 V at 5 A dc-todc Converter ......................................................................................................................................................................... 7 • Changed both (CSS – 0.85 V) voltages to (VCSS – 0.85 V) in Programming Soft Start ....................................................... 10 • Changed turn-on (IL) to start-up (ILOAD) in the third paragraph of Programming Current Limit section. ............................. 11 • Changed first instance of BPN10 to BP10 in respective section title. ................................................................................ 11 • Added high-side before MOSFET in the Calculating the BP10 and BP10V Bypass Capacitor section ............................. 12 • Changed HDRV signal goes high to ...goes low in the Synchronizing to an External Supply section ............................... 13 • Added equation definition for fSYNC to Equation 10 ............................................................................................................. 13 • Deleted k from KΩ at the end of equation Equation 11 ...................................................................................................... 13 • Added (dummy) to RT in Equation 11 definition ................................................................................................................. 13 • Changed sequence of equation substitutions from: Equation 14 into Equation 13, Equation 16 into Equation 15, Equation 13 equal to Equation 15, to: Equation 15 into Equation 14, Equation 17 into Equation 16, Equation 14 equal to Equation 16 ........................................................................................................................................................... 14 • Added generic before modulator gain in first paragraph of the Loop Compensation section ............................................ 14 • Deleted with VIN being the minimum input voltage required to cause the ramp excursion to cover the entire switching period. from first paragraph of the Loop Compensation section ........................................................................................ 14 • Deleted previous Equation 19, which was AMOD = VIN / VS or AMOD(db) = 20 × log (VIN / VS ) ............................................. 14 • Changed figure reference for modulator gain in the Loop Compensation from Figure 6 (Typical Current Limit Protection Waveforms) to Figure 8 (PWM MODULATOR RELATIONSHIPS) ................................................................... 14 • Added moderator DC gain and new Equation 20 to Loop Compensation section ............................................................. 15 • Changed VOUT to VOin sentence before and in Equation 23 .............................................................................................. 15 • Changed calculated in to set by in sentence before Equation 24 ...................................................................................... 15 • Changed VIN / VS to VIN(min) / VRAMP in the Modulator Gain vs Switching Frequency graph ............................................... 15 • Changed the TCR minimum value from 0.0035 to 3500 and the maximum from 0.010 to 10000 in the second paragraph of the High-Side MOSFET Power Dissipation section ...................................................................................... 17 • Changed VDD to VIN in Equation 41 .................................................................................................................................... 19 • Changed PowerPAD Dimensions to include x and y axis values ....................................................................................... 20 • Added high-side MOSFET to step four title ........................................................................................................................ 22 • Changed reference to substituting Equation 30 to Equation 47 ......................................................................................... 22 • Deleted IRMS 2 × RDS(ON) from synchronous MOSFET conduction equation ........................................................................ 23 • Changed synchronous MOSFET conduction equation equals value from 0.10 to 0.485 ................................................... 23 • Changed body diode conduction equation values: 100 ns to 50 ns and 0.104 W to 0.052 W ........................................... 23 • Changed power dissipation equation values: 0.1 to 0.485, 0.104 to 0.052, 0.311 W to 0.644 W ..................................... 23 • Changed junction temperature equation values: (0.311) to 0.644, 97°C to 111°C ............................................................ 23 • Changed Step 6 reference to Equation 11 to Equation 12 ................................................................................................. 23 • Changed inductor value equation in Step 6: replaced value of 48 with 55 and 11.8 with 11.9 .......................................... 23 • Changed RKFF equation values in Step 8:133.7 to 309 kΩ, 133 to 301 kΩ ........................................................................ 23 • Added 80%x before VIN(min) in RKFF equation in Step 8 ....................................................................................................... 23 • Changed first ESR value in Step 9 from 12.7 to 8.9 mΩ .................................................................................................... 24 • Changed second ESR value in Step 9 from 13.8 to 11.1 mΩ ............................................................................................ 24 • Changed DC modulator gain values in both equations: 10 to 18, 5 to 9; (5.0) to 9, 14 to 19 dB ...................................... 24 • Changed AMOD crossover frequency equation values: 5 to 9, 0.68 to 1.23 ..................................................................... 25 • Changed gain (G) equation values: 0.68 to 1.23, 1.46 to 0.81 .......................................................................................... 25 • Changed poles and zeros equation values: Equation 73, 73.3 to 73.7 kHZ, 4.62 to 4.59 kΩ; Equation 74, 3.29 to 0.81, 1.46 to 10 kHZ, 109 to 196 pF, 100 to 220 pF; Equation 75, 100 to 200 pF, 73.3 to 73.7 kHz, 21.7 to 9.82 kΩ, Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: TPS40060 TPS40061 TPS40060 TPS40061 SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com 21.5 to 10 kΩ; Equation 76, 21.5 to 10 kΩ, 2000 to 4301 pF, 1800 to 3900 pF ................................................................ 25 • Changed Design Example graphic to include new values from equation: 133 to 301 kΩ, 1800 to 3900 pF, 21.5 to 10 kΩ, 100 to 220 pF. Si9470 to Si9407 ................................................................................................................................. 25 • Added link references to hard-coded references throughout document ............................................................................. 26 28 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: TPS40060 TPS40061 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TPS40060PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060 TPS40060PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060 TPS40060PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060 TPS40060PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060 TPS40061PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061 TPS40061PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061 TPS40061PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061 TPS40061PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES025B January 2002–Revised May 2011 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Contents 1 Introduction ........................................................................................................................ 9 1.1 Features ...................................................................................................................... 9 1.2 Description ................................................................................................................. 10 1.3 Functional Block Diagram ................................................................................................ 11 1.4 Ordering Information ...................................................................................................... 11 1.5 Terminal Assignments—Normal Mode ................................................................................. 12 1.6 Terminal Assignments—External MCU Mode ......................................................................... 12 1.7 Terminal Functions ........................................................................................................ 13 1.8 Device Operation Modes ................................................................................................. 15 1.9 Terminal Assignments for Codec Port Interface Modes .............................................................. 15 2 Detailed Description .......................................................................................................... 16 2.1 Architectural Overview .................................................................................................... 16 2.1.1 Oscillator and PLL .............................................................................................. 16 2.1.2 Clock Generator and Sequencer Logic ...................................................................... 16 2.1.3 Adaptive Clock Generator (ACG) ............................................................................. 16 2.1.4 USB Transceiver ................................................................................................ 16 2.1.5 USB Serial Interface Engine (SIE) ........................................................................... 16 2.1.6 USB Buffer Manager (UBM) .................................................................................. 17 2.1.7 USB Frame Timer .............................................................................................. 17 2.1.8 USB Suspend and Resume Logic ............................................................................ 17 2.1.9 MCU Core ....................................................................................................... 17 2.1.10 MCU Memory ................................................................................................... 17 2.1.11 USB Endpoint Configuration Blocks and Buffer Space .................................................... 17 2.1.12 DMA Controller .................................................................................................. 17 2.1.13 Codec Port Interface ........................................................................................... 18 2.1.14 I2C Interface ..................................................................................................... 18 2.1.15 General-Purpose IO Ports (GPIO) ........................................................................... 18 2.1.16 Interrupt Logic ................................................................................................... 18 2.1.17 Reset Logic ...................................................................................................... 18 2.2 Device Operation .......................................................................................................... 19 2.2.1 Clock Generation ............................................................................................... 19 2.2.2 Boot Process .................................................................................................... 19 2.2.2.1 EEPROM Boot Process ........................................................................... 19 2.2.2.2 Host Boot Process ................................................................................. 19 2.2.2.3 EEPROM Data Organization ..................................................................... 20 2.2.2.4 I2C Serial EEPROM ................................................................................ 21 2.2.2.5 DFU Upgrade Process ............................................................................ 22 2.2.2.6 Download Error Recovery ........................................................................ 22 2.2.2.7 ROM Support Functions .......................................................................... 22 2.2.3 USB Enumeration .............................................................................................. 23 2.2.4 TAS1020B USB Reset Logic .................................................................................. 23 2.2.5 USB Suspend and Resume Modes .......................................................................... 24 2.2.5.1 USB Suspend Mode ............................................................................... 24 2.2.5.2 USB Resume Mode ................................................................................ 25 2.2.5.3 USB Remote Wake-Up Mode .................................................................... 25 2 Contents Copyright © 2002–2011, Texas Instruments Incorporated TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.6 Adaptive Clock Generator (ACG) ............................................................................. 26 2.2.6.1 Programmable Frequency Synthesizer ......................................................... 27 2.2.6.2 Capture Counter and Register ................................................................... 28 2.2.7 USB Transfers .................................................................................................. 29 2.2.7.1 Control Transfers ................................................................................... 29 2.2.7.2 Interrupt Transfers ................................................................................. 31 2.2.7.3 Bulk Transfers ...................................................................................... 32 2.2.7.4 Isochronous Transfers ............................................................................. 35 2.2.8 Microcontroller Unit ............................................................................................. 39 2.2.9 External MCU Mode Operation ............................................................................... 39 2.2.10 Interrupt Logic ................................................................................................... 39 2.2.11 General-Purpose I/O (GPIO) Ports ........................................................................... 45 2.2.11.1 Port 3 GPIO Bits ................................................................................... 47 2.2.11.2 Port 1 GPIO Bits ................................................................................... 48 2.2.11.3 Pullup Macro ........................................................................................ 48 2.2.12 DMA Controller .................................................................................................. 49 2.2.13 Codec Port Interface ........................................................................................... 49 2.2.13.1 General-Purpose Mode of Operation ............................................................ 50 2.2.13.2 Audio Codec (AC) '97 1.0 Mode of Operation ................................................. 57 2.2.13.3 Audio Codec (AC) '97 2.0 Mode of Operation ................................................. 58 2.2.13.4 Inter-IC Sound (I2S) Modes of Operation ....................................................... 59 2.2.13.5 AIC Mode of Operation ............................................................................ 61 2.2.13.6 Bulk Mode ........................................................................................... 61 2.2.14 I2C Interface ..................................................................................................... 62 2.2.14.1 Data Transfers ...................................................................................... 62 2.2.14.2 Single Byte Write ................................................................................... 63 2.2.14.3 Multiple Byte Write ................................................................................. 64 2.2.14.4 Single Byte Read ................................................................................... 64 2.2.14.5 Multiple Byte Read ................................................................................. 65 3 Electrical Specifications ..................................................................................................... 66 3.1 Absolute Maximum Ratings .............................................................................................. 66 3.2 Dissipation Ratings ........................................................................................................ 66 3.3 Recommended Operating Conditions .................................................................................. 66 3.4 Electrical Characteristics ................................................................................................. 66 3.5 Timing Characteristics .................................................................................................... 67 3.6 Clock and Control Signals ................................................................................................ 67 3.7 USB Signals When Sourced by TAS1020B ............................................................................ 67 3.8 Codec Port Interface Signals (AC ’97 Modes) ......................................................................... 68 3.9 Codec Port Interface Signals (I2S Modes) ............................................................................. 69 3.10 Codec Port Interface Signals (General-Purpose Mode) .............................................................. 69 3.11 I2C Interface Signals ...................................................................................................... 70 4 Application Information ...................................................................................................... 71 5 8K ROM ............................................................................................................................ 72 5.1 ROM Errata ................................................................................................................. 72 6 MCU Memory and Memory-Mapped Registers ....................................................................... 73 6.1 MCU Memory Space ...................................................................................................... 73 6.2 Internal Data Memory ..................................................................................................... 73 Copyright © 2002–2011, Texas Instruments Incorporated Contents 3 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.3 External MCU Mode Memory Space .................................................................................... 75 6.4 USB Endpoint Configuration Blocks and Data Buffer Space ........................................................ 76 6.4.1 USB Endpoint Configuration Blocks ......................................................................... 76 6.4.2 Data Buffer Space .............................................................................................. 76 6.4.3 USB OUT Endpoint Configuration Bytes .................................................................... 80 6.4.3.1 USB OUT Endpoint - Y Buffer Data Count Byte (OEPDCNTYx) ............................ 80 6.4.3.2 USB OUT Endpoint - Y Buffer Base Address Byte (OEPBBAYx) ........................... 80 6.4.3.3 USB OUT Endpoint - X Buffer Data Count Byte (OEPDCNTXx) ............................ 81 6.4.3.4 USB OUT Endpoint - X and Y Buffer Size Byte (OEPBSIZx) ................................ 81 6.4.3.5 USB OUT Endpoint - X Buffer Base Address Byte (OEPBBAXx) ........................... 81 6.4.3.6 USB OUT Endpoint - Configuration Byte (OEPCNFx) ........................................ 82 6.4.4 USB IN Endpoint Configuration Bytes ....................................................................... 83 6.4.4.1 USB IN Endpoint - Y Buffer Data Count Byte (IEPDCNTYx) ................................ 83 6.4.4.2 USB IN Endpoint - Y Buffer Base Address Byte (IEPBBAYx) ............................... 84 6.4.4.3 USB IN Endpoint - X Buffer Data Count Byte (IEPDCNTXx) ................................ 84 6.4.4.4 USB IN Endpoint - X and Y Buffer Size Byte (IEPBSIZx) .................................... 84 6.4.4.5 USB IN Endpoint - X Buffer Base Address Byte (IEPBBAXx) ............................... 85 6.4.4.6 USB IN Endpoint - Configuration Byte (IEPCNFx) ............................................ 85 6.4.5 USB Control Endpoint Setup Stage Data Packet Buffer .................................................. 86 6.5 Memory-Mapped Registers .............................................................................................. 87 6.5.1 USB Registers .................................................................................................. 89 6.5.1.1 USB Function Address Register (USBFADR - Address FFFFh) ............................ 89 6.5.1.2 USB Status Register (USBSTA - Address FFFEh) ............................................ 90 6.5.1.3 USB Interrupt Mask Register (USBIMSK - Address FFFDh) ................................. 91 6.5.1.4 USB Control Register (USBCTL - Address FFFCh) ........................................... 91 6.5.1.5 USB Frame Number Register (Low Byte) (USBFNL - Address FFFBh) .................... 92 6.5.1.6 USB Frame Number Register (High Byte) (USBFNH - Address FFFAh) ................... 92 6.5.2 DMA Registers .................................................................................................. 92 6.5.2.1 DMA Time Slot Assignment Register (Low Byte) (DMATSL1 - Address FFF0h) (DMATSL0 - Address FFEAh) .................................................................................. 92 6.5.2.2 DMA Time Slot Assignment Register (High Byte) (DMATSH1 - Address FFEFh) (DMATSH0 - Address FFE9h) ................................................................... 93 6.5.2.3 DMA Control Register (DMACTL1 - Address FFEEh) (DMACTL0 - Address FFE8h) .... 93 6.5.2.4 DMA Current Buffer Content Register (Low-Byte) (DMABCNT1L - Address FFF3h) (DMABCNT0L- Address FFEBh) ................................................................. 93 6.5.2.5 DMA Current Buffer Content Register (High Byte) (DMABCNT1H - Address FFF4h) (DMABCNT0H - Address FFECh) ............................................................... 94 6.5.2.6 DMA Bulk Packet Count Register (Low Byte) (DMABPCT0 - Address FFF2h) ........... 94 6.5.2.7 DMA Bulk Packet Count Register (High-byte) (DMABPCT1 - Address FFF1h) ........... 94 6.5.2.8 UBM Write Pointer (Low Byte) (Ch0WrPtrL - Address FFBCh) (Ch1WrPtrL - Address FFB8h) .............................................................................................. 94 6.5.2.9 UBM Write Pointer (High Byte) (Ch0WrPtrH - Address FFBBh) (Ch1WrPtrH - Address FFB7h) .............................................................................................. 95 6.5.2.10 DMA Read Pointer (Low Byte) (Ch0RdPtrL - Address FFBAh) (Ch1RdPtrL - Address FFB6h) .............................................................................................. 95 6.5.2.11 DMA Read Pointer (High Byte) (Ch0RdPtrH - Address FFB9h) (Ch1RdPtrH - Address FFB5h) .............................................................................................. 95 6.5.3 Adaptive Clock Generator Registers ......................................................................... 96 6.5.3.1 Adaptive Clock Generator1 Frequency Register (Byte 0) (ACG1FRQ0 - Address FFE7h) 4 Contents Copyright © 2002–2011, Texas Instruments Incorporated TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 ........................................................................................................ 96 6.5.3.2 Adaptive Clock Generator1 Frequency Register (Byte 1) (ACG1FRQ1 - Address FFE6h) ........................................................................................................ 96 6.5.3.3 Adaptive Clock Generator1 Frequency Register (Byte 2) (ACG1FRQ2 - Address FFE5h) ........................................................................................................ 96 6.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte) (ACGCAPL - Address FFE4h) .............................................................................................. 97 6.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte) (ACGCAPH - Address FFE3h) .............................................................................................. 97 6.5.3.6 Adaptive Clock Generator2 Frequency Register (Byte 0) (ACG2FRQ0 - Address FFF9h) ........................................................................................................ 97 6.5.3.7 Adaptive Clock Generator2 Frequency Register (Byte 1) (ACG2FRQ1 - Address FFF8h) ........................................................................................................ 97 6.5.3.8 Adaptive Clock Generator2 Frequency Register (Byte 2) (ACG2FRQ2 - Address FFF7h) ........................................................................................................ 98 6.5.3.9 Adaptive Clock Generator2 Divider Control Register (ACG2DCTL - Address FFF6h) ... 98 6.5.3.10 Adaptive Clock Generator1 Divider Control Register (ACG1DCTL - Address FFE2h) ... 98 6.5.3.11 Adaptive Clock Generator Control Register (ACGCTL - Address FFE1h) ................. 99 6.5.4 Codec Port Interface Registers .............................................................................. 100 6.5.4.1 Codec Port Interface Configuration Register 1 (CPTCNF1 - Address FFE0h) ........... 100 6.5.4.2 Codec Port Interface Configuration Register 2 (CPTCNF2 - Address FFDFh) .......... 101 6.5.4.3 Codec Port Interface Configuration Register 3 (CPTCNF3 - Address FFDEh) .......... 102 6.5.4.4 Codec Port Interface Configuration Register 4 (CPTCNF4 - Address FFDDh) .......... 103 6.5.4.5 Codec Port Interface Control and Status Register (CPTCTL - Address FFDCh) ........ 104 6.5.4.6 Codec Port Interface Address Register (CPTADR - Address FFDBh) .................... 105 6.5.4.7 Codec Port Interface Data Register (Low Byte) (CPTDATL - Address FFDAh) ......... 105 6.5.4.8 Codec Port Interface Data Register (High Byte) (CPTDATH - Address FFD9h) ......... 105 6.5.4.9 Codec Port Interface Valid Time Slots Register (Low Byte) (CPTVSLL - Address FFD8h) ....................................................................................................... 106 6.5.4.10 Codec Port Interface Valid Time Slots Register (High Byte) (CPTVSLH - Address FFD7h) ....................................................................................................... 106 6.5.4.11 Codec Port Receive Interface Configuration Register 2 (CPTRXCNF2 - Address FFD6h) ....................................................................................................... 107 6.5.4.12 Codec Port Receive Interface Configuration Register 3 (CPTRXCNF3 - Address FFD5h) ....................................................................................................... 108 6.5.4.13 Codec Port Receive Interface Configuration Register 4 (CPTRXCNF4 - Address FFD4h) ....................................................................................................... 109 6.5.5 P3 Mask Register ............................................................................................. 109 6.5.5.1 P3 Mask Register (P3MSK - Address FFCAh) ............................................... 109 6.5.6 I2C Interface Registers ....................................................................................... 110 6.5.6.1 I2C Interface Address Register (I2CADR - Address FFC3h) ............................... 110 6.5.6.2 I2C Interface Receive Data Register (I2CDATI - Address FFC2h) ......................... 110 6.5.6.3 I2C Interface Transmit Data Register (I2CDATO - Address FFC1h) ....................... 110 6.5.6.4 I2C Interface Control and Status Register (I2CCTL - Address FFC0h) ................... 111 6.5.7 Miscellaneous Registers ..................................................................................... 112 6.5.7.1 USB OUT endpoint Interrupt Register (OEPINT - Address FFB4h) ....................... 112 6.5.7.2 USB IN endpoint Interrupt Register (IEPINT - Address FFB3h) ........................... 112 6.5.7.3 Interrupt Vector Register (VECINT - Address FFB2h) ....................................... 113 6.5.7.4 Global Control Register (GLOBCTL - Address FFB1h) ..................................... 114 6.5.7.5 Memory Configuration Register (MEMCFG - Address FFB0h) ............................. 114 Copyright © 2002–2011, Texas Instruments Incorporated Contents 5 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com List of Figures 2-1 Adaptive Clock Generator Block Diagram .................................................................................... 27 2-2 TAS1020B Interrupt, Reset, Suspend, and Resume Logic ................................................................. 41 2-3 Activation of Setup Stage Transaction Overwrite Interrupt ................................................................. 43 2-4 GPIO Port 1 and Port 3 Functionality.......................................................................................... 46 2-5 Pull-Up Logic Symbol............................................................................................................ 48 2-6 Codec Port Interface Parameters − AC '97 1.0 .............................................................................. 53 2-7 Codec Port Interface Parameters − AIC ...................................................................................... 54 2-8 Codec Port Interface Parameters – I2S........................................................................................ 57 2-9 Byte Reversal Example ......................................................................................................... 57 2-10 Connection of the TAS1020B to an AC '97 Codec .......................................................................... 58 2-11 Connection of the TAS1020B to Multiple AC '97 Codecs................................................................... 59 2-12 Bit Transfer on the I2C Bus ..................................................................................................... 62 2-13 I2C START and STOP Conditions ............................................................................................. 63 2-14 TAS1020B Acknowledge on the I2C Bus...................................................................................... 63 2-15 Single Byte Write Transfer ...................................................................................................... 64 2-16 Multiple Byte Write Transfer .................................................................................................... 64 2-17 Single Byte Read Transfer ...................................................................................................... 64 2-18 Multiple Byte Read Transfer .................................................................................................... 65 3-1 External Interrupt Timing Waveform ........................................................................................... 67 3-2 USB Differential Driver Timing Waveform..................................................................................... 67 3-3 BIT_CLK and SYNC Timing Waveforms...................................................................................... 68 3-4 SYNC, SD_IN, and SD_OUT Timing Waveforms............................................................................ 68 3-5 I2S Mode Timing Waveforms ................................................................................................... 69 3-6 General-Purpose Mode Timing Waveforms .................................................................................. 69 3-7 SCL and SDA Timing Waveforms.............................................................................................. 70 3-8 Start and Stop Conditions Timing Waveforms................................................................................ 70 3-9 Acknowledge Timing Waveform................................................................................................ 70 4-1 Typical TAS1020B Device Connections....................................................................................... 71 6-1 Boot Loader Mode Memory Map............................................................................................... 75 6-2 Normal Operating Mode Memory Map ........................................................................................ 75 6-3 USB Endpoint Configuration Blocks and Buffer Space Memory Map..................................................... 77 6 List of Figures Copyright © 2002–2011, Texas Instruments Incorporated TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 List of Tables 1-1 Terminal Functions—Normal Mode ........................................................................................... 13 1-2 Terminal Functions—External MCU Mode ................................................................................... 14 1-3 Operating Mode After Reset .................................................................................................... 15 1-4 Terminal Assignments for Codec Port Interface Modes..................................................................... 15 2-1 EEPROM Header ................................................................................................................ 21 2-2 AGC Control Registers .......................................................................................................... 27 2-3 ACG Frequency Registers ...................................................................................................... 28 2-4 Electrical Characteristics of Pullup Resistors................................................................................. 48 2-5 Terminal Assignments for Codec Port Interface General-Purpose Mode................................................. 50 2-6 Terminal Assignments for Codec Port Interface AC '97 1.0 Mode 2 ...................................................... 57 2-7 Terminal Assignments for Codec Port Interface AC '97 2.0 Mode 3 ...................................................... 58 2-8 Terminal Assignments for Codec Port Interface I2S Mode 4 and Mode 5 ................................................ 59 2-9 SLOT Assignments for Codec Port Interface I2S Mode 4................................................................... 60 2-10 SLOT Assignments for Codec Port Interface I2S Mode 5................................................................... 60 2-11 Terminal Assignments for Codec Port Interface AIC Mode 1 .............................................................. 61 6-1 USB Endpoint Configuration Blocks Address Map .......................................................................... 77 6-2 USB Control Endpoint Setup Data Packet Buffer Address Map ........................................................... 86 6-3 Memory-Mapped Registers Address Map .................................................................................... 87 Copyright © 2002–2011, Texas Instruments Incorporated List of Tables 7 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 8 List of Tables Copyright © 2002–2011, Texas Instruments Incorporated TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 USB Streaming Controller Check for Samples: TAS1020B 1 Introduction 1.1 Features 1 • Universal Serial Bus (USB) • DMA Controller – USB specification version 1.1 compatible – Two DMA channels to support streaming – USB audio class specification 1.0 compatible USB audio data to/from the codec port – Integrated USB transceiver interface – Supports 12 Mb/s data rate (full speed) – Each channel can support a single USB – Supports suspend/resume and remote isochronous endpoint wake-up – In the I2S mode the device can support – Supports control, interrupt, bulk, and DAC/ADCs at different sampling frequencies isochronous data transfer type – A circular programmable FIFO used for – Supports up to a total of seven IN endpoints isochronous audio data streaming and seven OUT endpoints in addition to the • Codec Port Interface control endpoint – Configurable to support AC '97 1.x, AC '97 – Data transfer type, data buffer size, single or 2.x, AIC, or I2S serial interface formats double buffering is programmable for each – I2S modes can support a combination of one endpoint stereo DAC and/or two stereo ADCs – On-chip adaptive clock generator (ACG) – Can be configured as a general-purpose supports asynchronous, synchronous and serial interface adaptive synchronization modes for – Can support bulk data transfer using DMA isochronous endpoints for higher throughput – To support synchronization for streaming • I2C Interface USB audio data, the ACG can be used to – Master only interface generate the master clock for the codec – Does not support a multimaster bus • Micro-Controller Unit (MCU) environment – Standard 8052 8-bit core – Programmable to 100 kb/s or 400 kb/s data – 8K bytes of program memory ROM that transfer speeds contains a boot loader program and a library – Supports wait states to accommodate slow of commonly used USB functions slaves – 6016 bytes of program memory RAM which • General Characteristics is loaded by the boot loader program – High performance 48-pin TQFP Package – 256 bytes of internal data memory RAM – On-chip phase-locked loop (PLL) with – Two GPIO ports internal oscillator is used to generate – MCU handles all USB control, interrupt, and internal clocks from a 6 MHz crystal input bulk endpoint transfers – Reset output available which is asserted for both system and USB reset – External MCU mode supports application firmware development – 8K ROM with boot loader program and commonly used USB functions library – 3.3 V core and I/O buffers 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 1.2 Description The TAS1020B integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed specifically for applications that require isochronous data streaming. Applications include digital speakers, which require the streaming of digital audio data between the host PC and the speaker system via the USB connection. The TAS1020B device is fully compatible with the USB Specification Version 1.1 and the USB Audio Class 1.0 Specification. The TAS1020B uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU memory includes 8K bytes of program memory ROM that contains a boot loader program. At initialization, the boot loader program downloads the application program code to a 6,016-byte RAM from either the host PC or a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control, interrupt and bulk endpoint transactions. DMA channels are provided to handle isochronous endpoint transactions. The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In addition to the USB control endpoint, support is provided for up to seven IN endpoints and seven OUT endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint configuration blocks that reside in on-chip RAM. All USB data transfer types are supported. The TAS1020B device also includes a codec port interface (C-Port) that can be configured to support several industry standard serial interface protocols. These protocols include the audio codec (AC) '97 Revision 1.X, the AC '97 Revision 2.X and several inter-IC sound (I2S) modes. A direct memory access (DMA) controller with two channels is provided for streaming the USB isochronous data packets to/from the codec port interface. Each DMA channel can support one USB isochronous endpoint. An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB synchronization modes, which include asynchronous, synchronous and adaptive. Other on-chip MCU peripherals include an inter-IC control (I2C) serial interface, and two 8-bit general-purpose input/output (GPIO) ports. The TAS1020B device is implemented in a 3.3-V 0.25 μm CMOS technology. 10 Introduction Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B 8052 Core I2C Control 8K ROM 6016 Byte RAM USB Serial OSC PLL ACG Suspend /Resume Logic I2C Bus C−Port Port−3 Port−1 USB SOF 6 MHz Interface Engine CODEC Interface 1520 Byte SRAM UBM DMA Global Control/Status Registers TQFP Texas Instruments Package Type Peripheral Device Audio Solutions 48 pins PFB T AS 1020B PFB TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 1.3 Functional Block Diagram 1.4 Ordering Information Copyright © 2002–2011, Texas Instruments Incorporated Introduction 11 Submit Documentation Feedback Product Folder Link(s): TAS1020B 2 3 P1.1 P1.0 NC DVDD NC P3.5 P3.4 P3.3 DVSS P3.2/XINT P3.1 P3.0 24 23 22 21 20 19 18 17 16 15 14 13 4 37 38 39 40 41 42 43 44 45 46 47 48 CSCLK CDATO MCLKO1 MCLKO2 RESET VREN SDA SCL AVSS XTALO XTALI PLLFILI 5 6 7 8 P1.5 P1.4 P1.3 36 35 34 33 32 31 30 CDATI CSYNC CRESET CSCHNE DV TEST EXTEN RSTO MCLKI PUR DP DM MRESET 29 28 27 26 9 10 11 12 25 1 P1.2 P1.7 P1.6 DD PLLFILO AV DVSS DVDD DD DVSS TAS1020B 2 3 MCUAD1 MCUAD0 MCURD DVDD MCUWR MCUINTO MCUALE MCUA10 DVSS XINT MCUA9 MCUA8 24 23 22 21 20 19 18 17 16 15 14 13 4 37 38 39 40 41 42 43 44 45 46 47 48 CSCLK CDATO MCLKO1 MCLKO2 RESET VREN SDA SCL AVSS XTALO XTALI PLLFILI 5 6 7 8 MCUAD4 MCUAD3 36 35 34 33 32 31 30 CDATI CSYNC CRESET DV TEST EXTEN RSTO MCLKI PUR DP DM MRESET 29 28 27 26 9 10 11 12 25 1 MCUAD2 DD PLLFILO AV DVSS DVDD DD DVSS TAS1020B MCUAD5 MCUAD6 MCUAD7 CSCHNE TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 1.5 Terminal Assignments—Normal Mode PFB PACKAGE (Normal Mode) (TOP VIEW) 1.6 Terminal Assignments—External MCU Mode PFB PACKAGE (External Mode) (TOP VIEW) 12 Introduction Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 1.7 Terminal Functions Table 1-1. Terminal Functions—Normal Mode TERMINAL I/O DESCRIPTION NAME PIN TYPE NO. AVDD Power 2 3.3-V analog supply voltage AVSS Power 45 Analog ground CSCLK CMOS 37 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface used to clock the CSYNC, CDATO, CDATI, CRESET, AND CSCHNE signals. CSYNC CMOS 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port interface. CDATO CMOS 38 O Codec port interface serial data out CDATI CMOS 36 I Codec port interface serial data in CRESET CMOS 34 O Codec port interface reset output (see Table 1-4 for alternate uses) CSCHNE CMOS 32 I/O Codec port interface secondary channel enable (see Table 1-4 for alternate uses) DP CMOS 6 I/O USB differential pair data signal plus. DP is the positive signal of the bidirectional USB differential pair used to connect the TAS1020B device to the universal serial bus. DM CMOS 7 I/O USB differential pair data signal minus. DM is the negative signal of the bidirectional USB differential pair used to connect the TAS1020B device to the universal serial bus. DVDD Power 8, 21, 33 3.3-V digital supply voltage DVSS Power 4, 16, 28 Digital ground EXTEN CMOS 11 I External MCU mode enable: Input used to enable the device for the external MCU mode MCLKI CMOS 3 I Master clock input. An input that can be used as the master clock for the codec port interface or the source for MCLKO2. MCLKO1 CMOS 39 O Master clock output 1: The output of the ACG that can be used as the master clock for the codec port interface and the codec. MCLKO2 CMOS 40 O Master clock output 2: An output that can be used as the master clock for the codec port interface and the codec used in I2S modes for receive. This clock signal can also be used as a miscellaneous clock. MRESET CMOS 9 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state NC 20,22 Not used P1.[0:7] CMOS 23, 24, 25, I/O General-purpose I/O port [bits 0 through 7]: A bidirectional 8-bit I/O port with an internal 26, 27, 29, 100-μA active pullup 30, 31 P3.[0:5] CMOS 13, 14, 15, I/O General-purpose I/O port [bits 0 through 5]: A bidirectional I/O port with an internal 17, 18, 19 100-μA active pullup PLLFILI CMOS 48 I PLL loop filter input: Input to on-chip PLL from external filter components PLLFILO CMOS 1 O PLL loop filter output: Output from on-chip PLL to external filter components PUR CMOS 5 O USB data signal plus pullup resistor connect. PUR is used to connect the pullup resistor on the DP signal from a high-impedance state to 3.3 V. When the DP signal is connected to 3.3-V the host PC detects the connection of the TAS1020B device to the universal serial bus. RESET CMOS 41 O General-purpose active-low output which is memory mapped RSTO CMOS 12 O Reset output: An output that is active while the master reset input or the USB reset is active SCL CMOS 44 O I2C interface serial clock SDA CMOS 43 I/O I2C interface serial data TEST CMOS 10 I Test mode enable: Factory test mode VREN CMOS 42 O General-purpose active-low output which is memory mapped XINT CMOS 15 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU XTALI CMOS 47 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal XTALO CMOS 46 O Crystal Output: Output from the on-chip oscillator to an external 6-MHz crystal Copyright © 2002–2011, Texas Instruments Incorporated Introduction 13 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Table 1-2. Terminal Functions—External MCU Mode TERMINAL I/O DESCRIPTION NAME PIN TYPE NO. AVDD Power 2 - 3.3-V Analog supply voltage AVSS Power 45 - Analog ground CSCLK CMOS 37 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface used to clock the CSYNC, CDATO, CDATI, CRESET AND CSCHNE signals. CSYNC CMOS 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port interface. CDATO CMOS 38 O Codec port interface serial data output CDATI CMOS 36 I Codec port interface serial data input CRESET CMOS 34 O Codec port interface reset output (see Table 1-4 for alternate uses) CSCHNE CMOS 32 I/O Codec port interface secondary channel enable (see Table 1-4 for alternate uses) DP CMOS 6 I/O USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair used to connect the TAS1020B device to the universal serial bus. DM CMOS 7 I/O USB differential pair data signal minus. DM is the negative signal of the bidirectional USB differential pair used to connect the TAS1020B device to the universal serial bus. DVDD Power 8, 21, 33 - 3.3-V Digital supply voltage DVSS Power 4, 16, 28 - Digital ground EXTEN CMOS 11 I External MCU mode enable: Input used to enable the device for the external MCU mode. This signal uses a 3.3 V TTL/LVCMOS input buffer. MCLKI CMOS 3 I Master clock input: An input that can be used as the master clock for the codec port interface or the source for MCLKO2. MCLKO1 CMOS 39 O Master clock output 1: The output of the ACG that can be used as the master clock for the codec port interface and the codec. MCLKO2 CMOS 40 O Master clock output 2: An output that can be used as the master clock for the codec port interface and the codec. This clock signal can also be used as a miscellaneous clock. MRESET CMOS 9 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state. MCUAD [0:7] CMOS 23, 24, 25, I/O MCU multiplexed address/data: Multiplexed address bits[0:7]/data bits[0:7] for external 26, 27, 29, MCU access to the TAS1020B external data memory space. 30, 31 MCUA [8:10] CMOS 13, 14, 17 I/O MCU address bus: Multiplexed address bus bits[8:10] for external MCU access to the TAS1020B external data memory space. MCUALE CMOS 18 I MCU address latch enable: Address latch enable for external MCU access to the TAS1020B external data memory space. MCUINTO CMOS 19 O MCU interrupt output: Interrupt output to be used for external MCU INTO input signal. All internal TAS1020B interrupt sources are read together to generate this output signal. MCUWR CMOS 20 I MCU write strobe: Write strobe for external MCU write access to the TAS1020B external data memory space. MCURD CMOS 22 I MCU read strobe: Read strobe for external MCU read access to the TAS1020B external data memory space. PLLFILI CMOS 48 I PLL loop filter input: Input to on-chip PLL from external filter components. PLLFILO CMOS 1 O PLL loop filter output: Output to on-chip PLL from external filter components. PUR CMOS 5 O USB data signal plus pullup resistor connect. PUR is used to connect the pullup resistor on the DP signal to 3.3V from a high-impedance state. When the DP signal is connected in a 3.3-V state, the host PC should detect the connection of the TAS1020B device to the universal serial bus. RESET CMOS 41 O General-purpose active-low output which is memory mapped RSTO CMOS 12 O Reset output: An output that is active while the master reset input or the USB reset is active. SCL CMOS 44 O I2C interface serial clock SDA CMOS 43 I/O I2C interface serial data input/output TEST CMOS 10 I Test mode enable: Factory text mode 14 Introduction Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Table 1-2. Terminal Functions—External MCU Mode (continued) TERMINAL I/O DESCRIPTION NAME PIN TYPE NO. VREN CMOS 42 O General-purpose active-low output which is memory mapped. XINT CMOS 15 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU. XTALI CMOS 47 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal. XTALO CMOS 46 O Crystal output: Output from the on-chip oscillator to an external 6-MHz crystal. 1.8 Device Operation Modes The EXTEN and TEST pins define the mode that the TAS1020B is in after reset. Table 1-3. Operating Mode After Reset MODE EXTEN TEST Normal mode - internal MCU 0 0 External MCU mode 1 0 Factory test 0 1 Factory test 1 1 1.9 Terminal Assignments for Codec Port Interface Modes The codec port interface has five modes of operation that support AC '97, I2S, and AIC codecs. There is also a general-purpose mode that is not specific to a serial interface. The mode is programmed by writing to the mode select field of the codec port interface configuration register 1 (CPTCNF1). The codec port interface terminals CSYNC, CSCLK, CDATO, CDATI, CRESET, and CSCHNE take on functionality appropriate to the mode programmed as shown in the following table. Table 1-4. Terminal Assignments for Codec Port Interface Modes(1) (2) (3) TERMINAL GP AIC AC '97 v1.x AC '97 v2.x I2S I2S NO. NAME Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 35 CSYNC CSYNC I/O FS O SYNC O SYNC O LRCK O LRCK1 O 37 CSCLK CSCLK I/O SCLK O BIT_CLK I BIT_CLK I SCLK O SCLK1 O 38 CDATO CDATO O DOUT O SD_OUT O SD_OUT O SDOUT1 O SDOUT1 O 36 CDATI CDATI I DIN I SD_IN I SD_IN1 I SDIN1 I SDIN2 I 34 CRESET CRESET O RESET O RESET O RESET O CRESET O SCLK2 O 32 CSCHNE NC O FC O NC O SD_IN2 I SDIN2 I LRCK2 O (1) Signal names and I/O direction are with respect to the TAS1020B device. The signal names used for the TAS1020B terminals for the various codec port interface modes reflect the nomenclature used by the codec devices. (2) NC indicates no connection for the terminal in a particular mode. The TAS1020B device drives the signal as an output for these cases. (3) The CSYNC and CSCLK signals can be programmed as either an input or an output in the general-purpose mode. Copyright © 2002–2011, Texas Instruments Incorporated Introduction 15 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 2 Detailed Description 2.1 Architectural Overview 2.1.1 Oscillator and PLL Using an external 6-MHz crystal, the TAS1020B derives the fundamental 48-MHz internal clock signal using an on-chip oscillator and PLL. Using the PLL output, the other required clock signals are generated by the clock generator and adaptive clock generator. 2.1.2 Clock Generator and Sequencer Logic Utilizing the 48-MHz output from the PLL, the clock generator logic generates all internal clock signals, except for the codec port interface master clock (MCLK) and serial clock (CSCLK) signals. The TAS1020B internal clocks include the 48-MHz clock, a 24-MHz clock, and a 12-MHz clock. A 12 MHz USB clock is also generated. The USB clock is the same as the internal 12-MHz clock when the TAS1020B is transmitting data, but is derived from the data when the TAS1020B is receiving data. To derive the USB clock when receiving USB data, the TAS1020B utilizes an internal digital PLL (DPLL) driven from the 48-MHz clock. The sequencer logic controls the access to the SRAM used for the USB endpoint configuration blocks and the USB endpoint buffer space. The SRAM can be accessed by the MCU, the USB buffer manager (UBM), or the DMA channels. The sequencer controls the access to the memory using a round-robin fixed priority arbitration scheme. This means that the sequencer logic generates grant signals for the MCU, UBM, and DMA channels at a predetermined fixed frequency. 2.1.3 Adaptive Clock Generator (ACG) The adaptive clock generator is used to generate a master clock output signal (MCLKO) to be used by the codec port interface and the codec device. To synchronize data sent to or received from the codec to the USB frame rate, the MCLKO signal generated by the adaptive clock generator must be used. The synchronization of the MCLKO signal to the USB frame rate is achieved by the ACG, which, in turn, is controlled by a soft PLL, implemented in the MCU. One of the tasks performed by the ACG is to maintain count of the number of MCLKO clocks between USB Start of Frame (SOF) events. This count is monitored by the soft PLL in the MCU. Based on this count, the soft PLL outputs corrections to the ACG to adjust MCLKO to obtain the correct number of MCLKO clocks between USB SOF events. MCLKI, the master clock input, can also be selected to source the clocks used by the codec port interface. When MCLKI is selected, it is used to derive the TAS1020B-sourced versions of the clocks CSCLK and CSYNC. In this scenario, the codec device would also use the same master clock signal (MCLKI). 2.1.4 USB Transceiver The TAS1020B provides an integrated transceiver for the USB port. The transceiver includes a differential output driver, a differential input receiver, and two single ended input buffers. The transceiver connects to the USB DP and DM signal terminals. 2.1.5 USB Serial Interface Engine (SIE) The serial interface engine logic manages the USB packet protocol for packets being received and transmitted by the TAS1020B. For packets being received, the SIE decodes the packet identifier field (PID) to determine the type of packet being received and to ensure the PID is valid. The SIE then calculates the cycle redundancy check (CRC) of the received token and data packets and compares the value to the CRC contained in the packet to verify that the packet was not corrupted during transmission. For transmitted token and data packets, the SIE generates the CRC that is transmitted with the packet. The SIE also generates the synchronization field (SYNC) and the correct PID for all transmitted packets. Another major function of the SIE is the serial-to-parallel conversion of received data packets and the parallel-to-serial conversion of transmitted data packets. 16 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.1.6 USB Buffer Manager (UBM) The USB buffer manager provides the control logic that interfaces the SIE to the USB endpoint buffers. One of the major functions of the UBM is to decode the USB function address to determine if the host PC is addressing the TAS1020B device USB peripheral function. In addition, the endpoint address field and direction signal are decoded to determine which particular USB endpoint is being addressed. Based on the direction of the USB transaction and the endpoint number, the UBM will either write or read the data packet to or from the appropriate USB endpoint data buffer. 2.1.7 USB Frame Timer The USB frame timer logic receives the start of frame (SOF) packet from the host PC each USB frame. Each frame, the logic stores the 11-bit frame number value from the SOF packet in a register and asserts the internal SOF signal. The frame number register can be read by the MCU and the value can be used as a time stamp. For USB frames in which the SOF packet is corrupted or not received, the frame timer logic will generate a pseudo start of frame (PSOF) signal and increment the frame number register. 2.1.8 USB Suspend and Resume Logic The USB suspend and resume logic detects suspend and resume conditions on the USB. This logic also provides the internal signals used to control the TAS1020B device when these conditions occur. The capability to resume operation from a suspend condition with a locally generated remote wake-up event is also provided. 2.1.9 MCU Core The TAS1020B uses an 8-bit microcontroller core that is based on the industry standard 8052. The MCU is software compatible with the 8052, 8032, 80C52, 80C53, and 87C52 MCUs. The 8052 MCU is the processing core of the TAS1020B and handles all USB control, interrupt and bulk endpoint transfers. Bulk out end-point transfers can also be handled by one of the two DMA channels. 2.1.10 MCU Memory In accordance with the industry standard 8052, the TAS1020B MCU memory is organized into program memory, external data memory and internal data memory. A boot ROM program is used to download the application code to a 6K byte RAM that is mapped to the program memory space. The external data memory includes the USB endpoint configuration blocks, USB data buffers, and memory mapped registers. The total external data memory space available is 1.5K bytes. A total of 256 bytes are provided for the internal data memory. 2.1.11 USB Endpoint Configuration Blocks and Buffer Space The USB endpoint configuration blocks are used by the MCU to configure and operate the required USB endpoints for a particular application. In addition to the control end-point, the TAS1020B supports a total of seven IN endpoints and seven OUT endpoints. A set of six bytes is provided for each endpoint to specify the endpoint type, buffer address, buffer size, and data packet byte count. The USB endpoint buffer configuration blocks and buffer space provided totals 1440 bytes. The buffer space to be used by a particular endpoint is fully configurable by the MCU for a particular application. Therefore, the MCU can configure each buffer based on the total number of endpoints to be used, the maximum packet size to be used for each endpoint, and the selection of single or double buffering. 2.1.12 DMA Controller Two DMA channels are provided to support the streaming of data for USB isochronous IN endpoints, Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 17 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com isochronous OUT endpoints, and bulk OUT endpoints. Each DMA channel can support one USB isochronous IN endpoint, or one isochronous OUT endpoint, or one bulk OUT endpoint. The DMA channels are used to stream data between the USB endpoint data buffers and the codec port interface. The USB endpoint number and direction can be programmed for each DMA channel. Also, the codec port interface time slots to be serviced by each DMA channel can be programmed. 2.1.13 Codec Port Interface The TAS1020B provides a configurable full duplex bidirectional serial interface that can be used to connect to a codec or other external device types for streaming USB isochronous data. The interface can be configured to support several different industry standard protocols, including AC '97 1.x, AC '97 2.x, AIC, and I2S. The TAS1020B also has a general-purpose mode to support other protocols. 2.1.14 I2C Interface The I2C interface logic provides a two-wire serial interface that the 8052 MCU can use to access other ICs. The TAS1020B is an I2C master device only and supports single byte or multiple byte read and write operations. The interface can be programmed to operate at either 100 kbps or 400 kbps. In addition, the protocol supports 8-bit or 16-bit addressing for accessing the I2C slave device memory locations. The TAS1020B supports I2C wait states. This means slaves can assert wait state on the I2C bus by pulling the SCL line low. 2.1.15 General-Purpose IO Ports (GPIO) The TAS1020B provides two general-purpose IO ports that are controlled by the internal 8052 MCU. The two ports are port 1 and port 3. Port 1 provides true GPIO capability. Each bit of port 1 can be independently used as either an input or output, and consists of an output buffer, an input buffer, and a pullup resistor(4). Some of the bits of port 3 also provide true GPIO capability, but, in addition, some of the bits of port 3 also provide alternate input and output uses. An example of this is P3.2, which is used as the external interrupt (XINT) input to the TAS1020B. A detailed description of the alternate uses of some of the port 3 bits is presented in Section 2.2.11. The pullup resistors for port 1 and port 3 can be disabled by bits P1PUDIS and P3PUDIS respectively in the on-chip register GLOBCTL. In addition, any port 3 pin can be used to wake up the host PC from a low-power suspend mode. 2.1.16 Interrupt Logic The interrupt logic monitors the various conditions that can cause an interrupt and asserts the interrupt 0 (INTO) input on the 8052 MCU core accordingly. All of the TAS1020B internal interrupt sources and the external interrupt (XINT) input are ORed together to generate the INT0 signal. An interrupt vector register is used by the MCU to identify the interrupt source. 2.1.17 Reset Logic An external master reset (MRESET) input signal that is asynchronous to the internal clocks can be used to reset the TAS1020B logic. In addition to this master reset, the TAS1020B logic can also be reset by a USB reset from the host PC if bit FRSTE in the on-chip register USBCTL is set to 1. The TAS1020B also provides a reset output (RSTO) signal that can be used by external devices. This signal is asserted when either a master reset occurs or when a USB reset occurs and FRSTE is set to 1. (4) The pullup resistors are not implemented as true resistors, but rather as switchable current sources (see Section 2.2.11.3). 18 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2 Device Operation The operation of the TAS1020B is explained in the following sections. For additional information on USB, refer to the Universal Serial Bus Specification, Version 1.1. 2.2.1 Clock Generation The TAS1020B requires an external 6-MHz crystal with load capacitors and PLL loop filter components to derive all the clocks needed for both USB and codec operation. Figure 4-1 shows the connection of these components to the TAS1020B. Figure 4-1 also shows a ground shield residing on the top layer of the PCB and underneath the crystal and its load capacitors and the PLL components. The PLL is an analog PLL, and noise pickup in these components can translate to phase jitter at the output of the PLL, which in turn can translate to distortion at the codec. A ground shield is recommended to attenuate the digital noise components on the board as seen at the PLL. The AVSS and AVDD pins on the TAS1020B are used exclusively to power the analog PLL. To maintain isolation from the digital noise residing on a board, AVSS should be a separate ground plane that connects to the primary ground plane (DGND) at a single point via a ferrite bead. The ferrite bead should exhibit around 9 Ω of impedance at 100 MHz. AVDD should also be distinct from DVDD. A recommended architecture is to generate DVDD and AVDD from the same regulator line, with each derived from a RC filter in series with the regulator output. It is finally recommended that the ground shield for the crystal and its load capacitors and the PLL loop filter components be connected to AVSS at a single point via a ferrite bead of the same type as above. Using the low frequency 6-MHz crystal and generating the required higher frequency clocks internally in the TAS1020B is a major advantage with regard to EMI. 2.2.2 Boot Process The TAS1020B can boot from EEPROM or execute a host boot. Host boot will be used in the following circumstances: • No EEPROM is present. • An EEPROM is present, but does not contain a valid header. • An EEPROM is present, but is a device EEPROM (contains header information only). 2.2.2.1 EEPROM Boot Process If the target device has an application EEPROM (an EEPROM that contains both header and application data), and if the header portion of the EEPROM content is valid, the EEPROM application code is downloaded to on-chip RAM. During the download process, the RAM is mapped to data space, and the boot code that orchestrates the download is part of the on-chip firmware housed in on-chip ROM. Also, while the application code is being downloaded, the TAS1020B remains disconnected from the USB bus. When the download is complete, the firmware sets the ROM disable bit SDW. The setting of this bit maps the RAM from data space to program space, starting address 0x0000. Having set bit SDW, the firmware then branches to address 0x0000, which is the reset entry point for the application code. The application code is now running. The application code then switches on the PUR output. The PUR output pin is connected, through external circuitry (see Figure 4-1), to the positive (DP) line of the differential USB bus. Switching PUR on informs the host that a full speed (12 Mb/s) device is present on the bus. In the enumeration procedure that follows, the application code reports its run-time device descriptor set. Following enumeration, the device is actively running its application. 2.2.2.2 Host Boot Process The DFU code in the TAS1020B fully adheres to the USB Device Class Specification for DFU 1.0. In addition, the TAS1020B utilizes the communication protocols from the DFU specification to implement a host boot capability for those applications that do not have an EEPROM resource. In such cases, the Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 19 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com TAS1020B, at power-up, reports its DFU mode descriptor set rather than its run-time descriptor set and directly enters what the DFU specification terms the DFU Program Mode. The host processor must be cognizant of the fact that the device under enumeration does not have an EEPROM resource with valid code, and is already in the DFU mode awaiting a download per the DFU protocol. All of this capability is provided by the ROM-based code (firmware) that resides on the TAS1020B. Specifically, the host boot process addresses three cases—an EPROM is not present, an EEPROM is present but the data in the EEPROM is invalid, or an EEPROM is present but the EEPROM is a device EEPROM (contains only header data). In all three of these cases, the TAS1020B firmware comes up in the DFU Program Mode. A host boot ensues, but the final destination of the download depends on the status of the onboard EEPROM. a. If the firmware determines that no EEPROM is present (by noting, when addressing the EEPROM, the absence of an acknowledge from the EEPROM), a Vendor ID of 0xFFFF and a Product ID of 0xFFFE is reported during enumeration. The download that follows enumeration is written to the on-chip RAM. The download from the host must include a header (see Section 2.2.2.3.1), and the header overwrite bit in the header downloaded must be set to 0. (The header overwrite bit is used to instruct the TAS1020B firmware as to whether or not the header portion of the download is to be written into the EEPROM. Since, in this case, no EEPROM is present, this header overwrite bit must be set to 0). It is noted that the host must have prior knowledge that the target will initialize in the DFU program mode and will require a download of application code (and header) to RAM. b. If the firmware determines that an EEPROM is present (acknowledges are received from the EEPROM), but that the header data in the EEPROM is invalid, a Vendor ID of 0xFFFF and a Product ID of 0xFFFE is reported during enumeration. The download that follows enumeration is written to EEPROM. Since the EEPROM data was invalid, the host has to set the header overwrite bit in the header portion of the download to a 1 to ensure that the header is written to the EEPROM. It is noted that the host must have prior knowledge that the target does have an EEPROM, but that the data in the EEPROM is invalid. This could be a situation such as the initial download of the application on a production line. c. If the firmware determines that an EEPROM is present, that the header data in the EEPROM is valid, but that the header data in the EEPROM indicates that the EEPROM is a device EEPROM, the Vendor ID and Product ID settings in the EEPROM-resident header is reported during enumeration. In addition, the strings in the header, if applicable, are reported. The EEPROM download that follows enumeration will be written to the on-chip RAM facility. In addition to downloading the application code to RAM, an option also exists to download the header portion of the download image to the EEPROM. If the host does not wish to overwrite the valid header data in the EEPROM, it must set the header overwrite bit in its download header to a 0. It is noted that the host must have knowledge that the target contains an EEPROM, and that the EEPROM is a device EEPROM. 2.2.2.3 EEPROM Data Organization Two types of data can be stored in the EEPROM—header data, which contains USB device information, and application code. During boot, if no header or invalid header data is found in the EEPROM, paragraph (b) in Section 2.2.2.2 applies. During boot, if a valid header is found in the EEPROM, and the header indicates that the Data Type is an Application, then the application is loaded from the EEPROM and execution is passed to it. During boot, if a valid header is found in the EEPROM, and the header indicates that the Data Type is a Device, then paragraph (c) in Section 2.2.2.2 applies. 2.2.2.3.1 EEPROM Header Table 2-1 shows the format and information contained it the header data. As seen from Table 2-1, the header data begins at address 0x0000 in the EEPROM and precedes the application code. 20 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Table 2-1. EEPROM Header OFFSET TYPE SIZE VALUE 0 headerChksum 1 Header check sum—derived by adding the header data, excluding the header checksum, in bytes, and retaining the lower byte of the sum as the checksum. 1 HeaderSize 1 Size, in units of bytes, of the header including strings if applied 2 Signature 2 Signature: 0x1234 4 VendorID 2 USB Vendor ID 6 ProductID 2 USB Product ID 8 ProductVersion 1 Product version 9 FirmwareVersion 1 Firmware version USB attributes: Bit 0: If set to 1, the header includes all three strings: language, manufacture, and product strings, if set to 0, the header does not include any string. The strings, if present, must 10 UsbAttributes 1 conform to the USB string format per USB spec 1.0 or later. Bit 1 : Not used. Bit 2: If set to 1, the device can be self powered, if set to 0, cannot be self powered. Bit 3: If set to 1, the device can be bus powered, if set to 0, cannot be bus powered. Bits 4 through 7: Reserved 11 MaxPower 1 Maximum power the device needs in units of 2 mA. Device attributes: Bit 0: If set to 1, the CPU clock is 24 MHz, if set to 0, the CPU clock is 12 MHz. Bit 1: If set to 1, the download version of the header will be written into the EEPROM (download target has to be EEPROM). If the header is not to be overwritten, or if the target is 12 Attributes 1 RAM, this bit must be cleared to 0. Bit 2: Not used. Bit 3: If set to 1, the EEPROM can support a 400 kHz I2C bus, if set to 0, the EEPROM cannot support a 400-kHz I2C bus. Bits 4 through 7: Reserved 13 WPageSize 1 Maximum I2C write page size, in units of bytes This value defines if the device is an application EEPROM or a device EEPROM.0x01: 14 DataType 1 Application EEPROM—contains header and application code.0x02: Device EEPROM—contains only header. All other values are invalid. 15 RpageSize 1 Maximum I2C read page size, in units of bytes. If the value is zero, the whole payLoadSize is read in one I2C read setup. 16 payLoadSize 2 Size, in units of bytes, of the application, if using EEPROM as an application EEPROM, otherwise the value is 0. Language string in standard USB string format if applied. If this attribute is applied, the two xxxx Language string 4 attributes that follow must also be applied. If this attribute is not applied, the following two attributes cannot be applied. xxxx Manufacture ... Manufacture string in standard USB string format if applied. string xxxx Product string ... Product string in standard USB string format if applied. xxxx Application Code ... Application code if applied The header checksum is used by the firmware to detect the presence of a valid header in the EEPROM. The header size field supports future updates of the header. 2.2.2.3.2 Application Code Application code is stored as a binary image in the EEPROM following the header information. The binary image must always be mapped to MCU program space starting at address 0x0000, and must be stored in the EEPROM as a continuous linear block of data. 2.2.2.4 I2C Serial EEPROM The TAS1020B accesses the EEPROM via an I2C serial bus. Thus the EEPROM must be an I2C serial EEPROM. The ROM boot loader assumes the EEPROM device uses the full 7-bit I2C device address with the upper four bits of the address (control code) set to 1010 and the three least significant bits (chip select bits) set to 000. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 21 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 2.2.2.5 DFU Upgrade Process DFU compliance provides a host the capability of upgrading application code currently residing in a target's onboard EEPROM memory. The DFU upgrade process provided by the TAS1020B fully conforms to the requirements specified in USB Device Class Specification For DFU 1.0. The download must consist of both header and application code. The destination of the download must be defined by the on-chip application code (as opposed to the application code being downloaded). Under normal circumstances, the download destination would be EEPROM, but it is possible for the application code to specify on-chip RAM as the download destination. If the download destination is to be EEPROM, bit 1 of the Attribute field in the header data being downloaded determines whether or not the header data in the download image is to be written to the EEPROM. A bit value of 1 results in the header in the EEPROM being overwritten by the header content in the download image. It is important to note that if the application code targets RAM as the download destination, bit 1 in the Attribute field of the download image must be 0. 2.2.2.6 Download Error Recovery Safeguards are incorporated on the TAS1020B ROM to allow recovery from a host download that does not complete due to a loss of power. Before downloading the application code, the TAS1020B saves the value of the Data Type field in the EEPROM header and modifies the Data Type field to indicate that a download is in progress (0x03: Updating). After successful completion of the download, the TAS1020B restores the saved value in the Data Type field. If the download is terminated prior to successful completion, the Data Type field still indicates that a download is in progress. In the case of an unsuccessful download the TAS1020B reboots as a DFU device in DFU Program mode and uses the Vendor and Product ID from the EEPROM header as the vendor and product ID in its USB device descriptor. The download process consists of the following task flow. 1. Header portion of download is written to EEPROM, if applicable. 2. Header Data Type is retrieved and stored in RAM. 3. Header Data Type is overwritten with a value indicating that a download is in progress. 4. Application portion of download is written to EEPROM (or to RAM). 5. Header Data Type is overwritten with the previously recorded legal value. If the download should terminate during the downloading of the header to EEPROM, the header checksum results in the EEPROM being declared invalid on the next boot of the TAS1020B. If the download should terminate during the downloading of the application code, the Data Type field indicates that a download was in progress and the TAS1020B enters the DFU program mode on the next boot. If the TAS1020B remains powered when a premature termination of a download occurs, the TAS1020B remains in the DFU program mode. In this case, the host can again attempt a download; the TAS1020B does not have to be rebooted. 2.2.2.7 ROM Support Functions To conserve RAM memory resources on the TAS1020B, several USB-specific routines have been included in the firmware resident in the on-chip ROM. The inclusion of these routines frees the application code from having to implement USB-specific code. The tasks provided by the ROM code include: • A USB engine for handling USB control endpoint data transactions and states • USB protocol handlers to support USB Chapter 9 • USB protocol handlers to support USB HID Class • USB protocol handlers to support USB DFU Class 22 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 • USB protocol handlers to support the common features of USB Audio Class commands – Feature Unit: • Set/get volume control • Set/get mute control • Set/get bass control • Set/get treble control – Mixer unit: set/get input/output gain control – End point: set/get the audio streaming endpoint sampling frequency – For unsupported case, the ROM code passes the requests to the application code for processing (). See also Section 5. 2.2.3 USB Enumeration USB enumeration is accomplished by interaction between the host PC and the TAS1020B. As described in Section 2.2.2, the TAS1020B can identify itself as an application device by reporting its application Vendor ID and Product ID, or it can identify itself as a DFU device by reporting a Vendor ID of 0xFFFF and a Product ID of 0xFFFE. If the TAS1020B fails to detect the presence of an EEPROM, or if an EEPROM is present but does not contain a valid header, the Vendor ID of 0xFFFF and Product ID of 0xFFFE are reported. If an EEPROM is present, but contains only valid header data, the Vendor ID and Product ID settings in the EEPROM header are reported, but the TAS1020B firmware comes up as a DFU device in the DFU program mode. If an EEPROM is present, and contains both a valid header and application code, the TAS1020B comes up as an application specific device. For all cases where the TAS1020B comes up in the DFU program mode, once application code has been downloaded, the TAS1020B is reset by a host-issued USB reset. After this reset, the TAS1020B comes up as an application device. When the TAS1020B comes up as an application device, the ROM-resident boot loader retrieves the application code from the EEPROM, if the EEPROM is not a device EEPROM, and then runs the application code. It is the application code that connects the TAS1020B to the USB. During the enumeration that follows connection to the USB, the application code identifies the device as an application specific device and the host loads the appropriate host driver(s). The boot loader and application code both use the CONT, SDW and FRSTE bits to control the enumeration process. • The function connect (CONT) bit is set to a 1 by the MCU to connect the TAS1020B device to the USB. When this bit is set to a 1, the USB DP line pullup resistor (PUR) output signal is enabled. Enabling PUR pulls DP high via external circuitry (see Figure 4-1). (When the TAS1020B powers up, this bit is cleared to a 0 and the PUR output is in the high-impedance state.) This bit is not affected by subsequent USB resets. • The shadow the boot ROM (SDW) bit is set to 1 by the MCU to switch the MCU memory configuration from boot loader mode to normal operating mode. Once set to 1, this bit is not affected by subsequent USB resets. • The function reset enable (FRSTE) bit is set to a 1 by the MCU to enable the USB reset to reset all internal logic including the MCU. However, the shadow the ROM (SDW) and the USB function connect (CONT) bits are not reset. In addition, when the FRSTE bit is set, the reset output (RSTO) signal from the TAS1020B device is active whenever a USB reset occurs. This bit, once set, is not affected by subsequent USB resets. 2.2.4 TAS1020B USB Reset Logic There are two mechanisms provided by the TAS1020B—an external reset MRESET and a USB reset. The reset logic used in the TAS1020B is presented in Figure 2-2. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 23 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com MRESET is a global reset that results in all the TAS1020B logic and the 8052 MCU core being reset. This input to the TAS1020B is typically used to implement a power-on reset at the application of power, but it can also be used with reset pushbutton switches and external circuits to implement global resets at any time. MRESET is an asynchronous reset that must be active for a minimum time period of one microsecond. The TAS1020B can also detect a USB reset condition. When this reset occurs, the TAS1020B responds by setting the function reset (RSTR) bit in the USB status register (USBSTA). However, the extent to which the internal logic is reset depends on the setting of the function reset enable bit (FRSTE) in the USB control register (USBCTL). If the MCU has set FRSTE to 1, incoming USB resets are treated as global resets, with all TAS1020B logic and the 8052 MCU core being reset. However, the shadow the ROM (SDW) and the USB function connect (CONT) bits are not reset. Also, if the USB reset results in a global reset being issued, an interrupt to the 8052 MCU is not generated. But if the MCU has cleared FRSTE, incoming USB resets is treated as interrupts to the MCU (via INT0) if the corresponding function reset bit RSTR in the USB interrupt mask register USBMSK has been set by the MCU. If neither FRSTE or RSTR has been set by the MCU, USB resets have no effect on the TAS1020B, other than resetting the USB serial interface engine (SIE) and the USB buffer manager (UBM) in the TAS1020B. Regardless of the status of FRSTE and bit RSTR in the USB interrupt mask register USBMSK, the function reset bit RSTR in the USB status register USBSTA is always set whenever a USB reset condition is detected. If the USB reset results in the generation of a global reset, the global reset clears the function reset bit RSTR in USBSTA. If, instead, the USB reset results in an interrupt being generated, RSTR in register USBSTA is cleared when the MCU writes to the interrupt vector register VECINT while in the USB reset interrupt service routine (VECINT = 0x17). The TAS1020B has two reset outputs—RSTO and CRESET. RSTO is activated every time MRESET is active, and every time a USB reset occurs and bit FRSTE in the USB control register USBCTL is set. CRESET is typically used as a codec reset. Although labeled a reset line, it has no direct relationship to MRESET or detected USB resets. Instead, it is activated and deactivated when the on-chip 8052 MCU core writes a 0 and a 1, respectively, to the CRST bit in the codec port interface control and status register CPTCTL. 2.2.5 USB Suspend and Resume Modes The TAS1020B can recognize a suspend state. Figure 2-2 shows the logical implementation of the suspend and resume modes in the TAS1020B. The TAS1020B enters a suspend mode if a constant idle state (j state) is observed on the USB bus for a period of 5 ms. USB compliance also requires that a device enter a suspend state, drawing only suspend current from the bus, after no more than 10 ms of bus inactivity, The TAS1020B supports this requirement by creating a suspend interrupt to the on-chip MCU after a suspend condition has been present for 5 ms. Upon receiving this interrupt, the MCU firmware can then take the steps necessary to assure that the device enters a suspend state within the next 5 ms. There are two ways for the TAS1020B device to exit the suspend mode: 1) detection of USB resume signaling and 2) proactively performing a local remote wake-up event. 2.2.5.1 USB Suspend Mode When a suspend condition is detected on the USB, the suspend/resume logic sets the function suspend request bit (SUSR) in the USB status register, resulting in the generation of the function suspend request interrupt SUSR. To enter the low-power suspend state and disable all TAS1020B device clocks, the MCU firmware, upon receiving the SUSR interrupt, must set the idle mode bit (IDL), which is bit 0 in the MCU power control (PCON) register. Setting the IDL bit results in the TAS1020B suspending all internal clocks, including the clocks to the MCU. The MCU thus suspends instruction execution while in the idle mode. The MCU must not set the IDL bit while in the SUSR interrupt service routine (ISR), or while in any other ISR. As described in Section 2.2.5.3, it is intended that the receipt of an INT0 interrupt at the MCU result in exiting the suspend state. But if the MCU has suspended instruction execution while in an ISR, 24 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 subsequent INT0 activity is not recognized, as the MCU is still servicing an interrupt. For this reason then, it is necessary that IDL not be set while processing an ISR. (As described in Section 2.2.5.3, an external wake-up event will resume clocks within the TAS1020B. But even if the clocks to the MCU resume, if the MCU does not recognize INT0, the IDL bit remains set and thus the MCU core itself remains in the suspend state). The SUSR bit is cleared while in the SUSR ISR by writing to the interrupt vector register VECINT. While servicing the SUSR ISR, the VECINT output is 0x16 - the USB function suspend interrupt vector. As shown in Figure 2-2, the occurrence of a write to VECINT, while the USB function suspend interrupt vector is being output, results in clearing bit SUSR of the USB status register. (The data written to VECINT is of no consequence; the clearing action takes place upon decoding the write transaction to VECINT). 2.2.5.2 USB Resume Mode When the TAS1020B is in a suspend state, any non-idle signaling on the USB is detected by the suspend/resume logic and device operation resumes. When the resume signal is detected, the TAS1020B clocks are enabled and the function resume request bit (RESR) is set, resulting in the generation of the function resume request interrupt. The function resume request interrupt to the MCU automatically clears the idle mode bit IDL in the PCON register, and as a result the MCU exits the suspend state and becomes fully functional, with all internal clocks active. After the RETI from the ISR, the next instruction to be executed is the one following the instruction that set the IDL bit. The RESR bit is cleared while in the RESR ISR by writing to the interrupt vector register VECINT. 2.2.5.3 USB Remote Wake-Up Mode The TAS1020B device has the capability to remotely wake up the USB by generating resume signaling upstream, providing the host has granted permission to generate remote wake-ups via a SET_FEATURE DEVICE_REMOTE_WAKEUP control transaction. If remote wakeup capability has been granted, the MCU firmware, upon awakening from a suspend state, has to activate the remote wake-up request bit RWUP in the USB control register USBCTL. Activation of RWUP consists of the MCU firmware writing a 1 followed by a 0 to RWUP. This action creates a pulse, which results in the TAS1020B generating resume signaling upstream by driving a k state (non-idle) onto the USB bus. The USB specification requires that remote wake-up resume signaling not be generated until the suspend state has been active for at least 5 ms. In addition, the specification requires that the remote wake-up resume signaling be generated for at least 1ms but for no more than 15 ms. The 5 ms requirement is met by not entering the suspend mode until an idle state, or j state, is detected, uninterrupted, for 5 ms. The RWUP pulse results in driving a k state onto the USB bus for 1 to 2 ms, and thus the 15 ms requirement is also met. Moreover, if an application wishes to extend the duration of the k state on the USB bus, it need only extend the pulse width of RWUP. The resulting duration of the resume signaling is the duration of the RWUP pulse plus 1 to 2 ms. The condition that activates a remote wake-up is a transition from 1 to 0 on one of the P3 port bits whose corresponding mask bit has been set to zero. (When in the suspend mode, the XINT input is treated as port bit P3.2). As seen in Figure 2-2, the P3 mask register bits are gated with the P3 port input lines from the I/O port cells. The gated P3 port bits are then all ORed together and the output is ANDed with the suspend signal. The output of this logic drives the clock input of a flip-flop, and when the output of this logic transitions from 0 to 1, the flip-flop is set to 1. The setting of this flip-flop to 1 results in the TAS1020B exiting the suspend state and resuming all clocks, including those to the MCU core. The output of this flip-flop is also gated with bit XINTEN in the global control register GLOBCTL, and the output of this gate drives the INT0 interrupt logic. This means that a remote wake-up generates an INT0 interrupt to the MCU only if bit XINTEN has been set. Therefore, before entering a suspend state, the firmware must set XINTEN if remote wake-up capability is to be enabled. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 25 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com The wake-up interrupt is seen by the firmware as an XINT interrupt; that is, the interrupt vector register VECINT has an output value of 0x1F. If the XINT pin is to be used as an event marker during normal operation, and if one of the P3 port bits is to be used for a wake-up interrupt, the firmware must be able to distinguish between a wake-up interrupt and a normal XINT interrupt. One technique would be to examine the state of the IDL bit in the MCU power control register. If this bit is set, the interrupt event is a wake-up interrupt; otherwise, the interrupt is a normal XINT interrupt. If an XINT event should occur during a suspend mode, the event is ignored if the mask bit for P3.2 is set. (During a suspend mode the TAS1020B clocks are disabled, and thus an incoming XINT interrupt event does not propagate through the synchronization logic and activate the MCU INT0 input). 2.2.6 Adaptive Clock Generator (ACG) The adaptive clock generator is used to generate two programmable master clock output signals (MCLKO and MCLKO2) that can be used by the codec port interface and the codec device. Two separate and programmable frequency synthesizers provide the two master clocks. This allows the TAS1020B to support different record and playback rates for those devices that require separate master clocks to implement different rates. For isochronous transactions, the ACG can also support USB asynchronous, synchronous, and adaptive modes of operation. The ACG keeps count of the number of master clock events between USB SOF time marks, and the DCNTX/Y field of the endpoint register IEPDCNTX/Y keeps track of the number of samples received between USB SOF time marks. Synchronous isochronous operation can be accomplished by adjusting one of the two frequency synthesizers until the correct number of master clock events is obtained between USB SOF time marks. Similarly, monitoring the number of samples received between USB SOF events can accommodate adaptive isochronous operation. Here the frequency synthesizer is adjusted to obtain the proper codec output rate for the number of samples received. The TAS1020B can also accommodate asynchronous isochronous operation, and the input MCLKI is provided for this case. For asynchronous isochronous operation, the external clock pin MCLKI is used to derive the data and sync signal to the codec. However, the external clock that provides the input to pin MCLKI, instead of the master clock output (MCLKO or MCLKO2) from the ACG, must also source the codec's MCLK. A block diagram of the adaptive clock generator is shown in Figure 2-1. Each frequency synthesizer circuit generates a programmable clock with a frequency range of 12-25 MHz, and each frequency synthesizer output feeds a divide-by-M-circuit, which can be programmed to divide by 1 to 16. As a result, the frequency range of each master clock is 750 kHz to 25 MHz. Also, the duty cycle of each master clock is 50% for all programmable frequencies (after a possible short, or "runt", initial cycle). As indicated in Figure 2-1, multiplexers precede the master clocks MCLKO and MCLKO2. These multiplexers provide the option of using the output of either frequency synthesizer (after division by the divide-by-M circuit) or the MCLKI input (after division by the divide-by-I circuit) to source each master clock. Each master clock is also assigned its own divide circuit to generate its associated CSCLK. The C-port serial clock (CSCLK) is derived by setting the divide by B value in codec port interface configuration register CPTNCF4 [2:0] and the C-port serial clock 2 (CSCLK2) is derived by setting the divide by B2 value in codec port receive interface configuration register 4 CPTRXCNF4 [2:0]. In addition, although not shown in Figure 2-1, each master clock is assigned its own CSYNC generator, with the length and polarity of each CSYNC separately programmable. 26 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B 6 MHz PLL Frequency Synthesizer Oscillator MCLK0 Divide by M1 1 Frequency Synthesizer Divide by M2 2 Divide by I 4 4 3 ACG1DCTL[7:4] ACG2DCTL[7:4] ACG1DCTL[2:0] ACGCTL[4] ACGCTL[1] ACGCTL[3] ACGCTL[0] 16-Bit Counter ACGCTL[6] ACGCTL[7] MCLK02 ACGCAPH ACGCAPL SOF PSOF MCLKI Divide by B CPTCNF4 [2:0] CSCLK Divide by B2 CPTRXCNF4 [2:0] CSCLK2 TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Figure 2-1. Adaptive Clock Generator Block Diagram The ACG is controlled by the registers shown in Table 2-2. See Section 6.5.3 for details. Table 2-2. AGC Control Registers FUNCTIONAL REGISTER ACTUAL BYTE-WIDE REGISTERS 24-bit frequency register #1 ACG1FRQ2 ACG1FRQ1 ACG1FRQ0 16-bit capture register ACGCAPH ACGCAPL 8-bit synthesizer 1 divider control register ACG1DCTL 8-bit ACG control register ACGCTL 24-bit frequency register #2 ACG2FRQ2 ACG2FRQ1 ACG2FRQ0 8-bit synthesizer 2 divider control register ACG2DCTL The main functional modules of the ACG are described in the following sections. 2.2.6.1 Programmable Frequency Synthesizer The 24-bit ACG frequency register value is used to program the frequency synthesizer, and the value of the frequency register can be updated by the MCU while the ACG is running. The high resolution of each frequency value programmed allows the firmware to adjust the frequency value by +LSB or more to lock onto the USB start-of-frame (SOF) signal and achieve a synchronous mode of operation, a necessity for streaming audio applications. The 24-bit frequency register value is updated and used by the frequency synthesizer only when MCU writes to the ACGFRQ0 register. The proper way to update a frequency value then is to write the least significant byte (ACGFRQ0) last. The frequency resolution of the output master clock depends on the actual frequency being output. In general, the frequency resolution decreases with increasing output frequencies. The clock frequency of the MCLKO output signal is calculated by using the formula: For N ≥ 24 and N < 50, Frequency Synthesizer output frequency = 600/N MHz For N = 50, frequency = 12 MHz Where N is the value in the 24-bit frequency register (ACGFRQ). The value of N can range from 24 to 50. The six most significant bits of the 24-bit frequency register are used to represent the integer portion of N, and the remaining 18 bits of the frequency register are used to represent the fractional portion of N. An example is shown below. Alternatively, with ACGnFRQ considered to be a 24-bit unsigned value: ACGnFRQ = [600 000 000 / output (Hz)] × 218 Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 27 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Where output (Hz) is the output of Frequency Synthesizer n. Example Frequency Register Calculation Suppose the desired MCLKO frequency is 24.576 MHz. Using the above formula, N = 24.4140625 decimal. To determine the binary value to be written to the ACGFRQ register, separately convert the integer value (24) to 6-bit binary and the fractional value (4140625) to 18-bit binary. As a result, the 24-bit binary value is 011000.011010100000000000. The corresponding values to program into the ACGFRQ registers are: ACGFRQ2 = 01100001b = 61h ACGFRQ1 = 10101000b = A8h ACGFRQ0 = 00000000b = 00h Keep in mind that writing to register ACGFRQ0 loads the frequency synthesizer with the new 24-bit value in registers ACGFRQ2, ACGFRQ1, and ACGFRQ0. Example Frequency Resolution Calculation To illustrate the frequency resolution capabilities of the ACG, the next possible higher and lower frequencies for MCLKO can be calculated. To get the next possible higher frequency of MCLKO (24.57600384 MHz), decrease the value of N by 1 LSB. Thus, N = 011000.01 – 10100111 –11111111 binary. To get the next possible lower frequency of MCLKO (24.57599600 MHz), increase the value of N by 1 LSB. Thus, N = 011000.01 – 10101000 – 00000001 binary. For this example with a nominal MCLKO frequency of 24.576 MHz, the frequency resolution is approximately 4 Hz. Table 2-3 lists typically used frequencies and the corresponding ACG frequency register values. Table 2-3. ACG Frequency Registers SYNTHESIZED CLOCK ACG1FRQ2/ ACG1FRQ1/ ACG1FRQ0/ OUTPUT ACG2FRQ2 ACG2FRQ1 ACG2FRQ0 25 MHz 0x60 0 0 24.576 MHz 0x61 0×A8 0x0F 22.579 MHz 0x6A 0x4B 0x20 18.432 MHz 0x82 0x35 0x55 16.934 MHz 0x8D 0xBA 0x09 16.384 MHz 0x92 0x7C 0x00 12.288 MHz 0xC3 0x50 0x00 12 MHz 0xC8 0 0 2.2.6.2 Capture Counter and Register The capture counter and register circuit consists of a 16-bit free running counter which runs at the capture clock frequency. The capture clock source can be selected by programming bits MCLK01S0 and MCLK01S1 in the ACGCTL register. The options are the divided output of frequency synthesizer no. 1, the divided output of frequency synthesizer no. 2, or the divided input clock MCLKI. At each USB start-of-frame (SOF) event or pseudo-start-of-frame (PSOF) event, the capture counter value is stored into the 16-bit capture register. This value is valid until the next SOF or PSOF signal occurs (~1 ms). The MCU 28 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 can read the 16-bit capture register value by reading the ACGCAPH and ACGCAPL registers. Because the counter is a free running counter, and because the count range of the counter extends over several frames before rolling over and beginning the count anew, the capture count values obtained are correlated over several SOF cycles. This attribute is useful should a case ever arise when the MCU fails to read the capture counter after a SOF event, and thus skips an SOF cycle. As shown in Figure 2-1, there is only one capture counter and register, and its capture clock frequency is always the clock selection for MCLKO. This means that MCLKO2 cannot be synchronized to the incoming USB data stream. However, MCLKO2 is intended to support record capability for those cases where record and playback are conducted at different master clock frequencies. Synchronization to the USB bus for record is handled by the handshaking protocol established between the assigned DMA channel and the USB buffer manager (UBM) (see Section 2.2.7.4.1, heading Circular Buffer Operation for Isochronous IN Transactions for more detail). Thus it is not necessary that MCLKO2 itself be synchronized to the USB bus. 2.2.7 USB Transfers The TAS1020B device supports all USB data transfer types: control, bulk, interrupt, and isochronous. In accordance with the USB specification, endpoint zero is reserved for the control endpoint and is bidirectional. In addition to the control endpoint, the TAS1020B is capable of supporting up to 7 IN endpoints and 7 OUT endpoints. These additional endpoints can be configured as bulk, interrupt, or isochronous endpoints. 2.2.7.1 Control Transfers Control transfers are used for configuration, command, and status communication between the host PC and the TAS1020B device. Control transfers to the TAS1020B device use IN endpoint 0 and OUT endpoint 0. The three types of control transfers are control write, control write with no data stage, and control reads. 2.2.7.1.1 Control Write Transfer (Out Transfer) The host PC uses a control write transfer to write data to the USB function. A control write transfer always consists of a setup stage transaction and an IN status stage, and can optionally contain one or more data stage transactions between the setup and status transactions. If the data to be transferred can be contained in the two byte value field of the setup transaction data packet, no data stage transaction is required. If the control information requires the transfer of more than two bytes of data, a control write transfer with data stage transactions will be required. The steps followed for a control write transfer are: Initialization Stage 1. MCU initializes IN endpoint 0 and OUT endpoint 0 by programming the appropriate USB endpoint configuration blocks. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and clearing the NACK bit for both IN endpoint 0 and OUT endpoint 0. Setup Stage Transaction 1. The host PC sends a setup token followed by the setup data packet addressed to OUT endpoint 0. If the data is received without an error, the USB Buffer Manager (UBM) writes the data to the setup data packet buffer, sets the setup stage transaction (SETUP) bit to a 1 in the USB status register, returns an ACK handshake to the host PC, and asserts the setup stage transaction interrupt. Note that as long as the setup stage transaction (SETUP) bit is set to a 1, the UBM returns a NACK handshake for any data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values. 2. The MCU services the interrupt, reads the setup data packet from the buffer, and decodes the command. If the command is not supported or valid, the MCU should set the STALL bit in the OUT endpoint 0 configuration byte and the IN endpoint 0 configuration byte before clearing the setup stage transaction (SETUP) bit. This causes the device to return a STALL handshake for any data stage or status stage transactions. If the command decoded is supported, the MCU clears the interrupt, which Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 29 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com automatically clears the setup stage transaction bit. The MCU also sets the TOGGLE bit in the OUT endpoint 0 configuration byte to a 1. For control write transfers, the PID used by the host for the first OUT data packet is a DATA1 PID and the TOGGLE bit must match. Optional Data Stage Transaction 1. The host PC sends an out token packet followed by a data packet addressed to OUT endpoint 0. If the data packet is received without errors the UBM writes the data to the endpoint buffer, updates the data count value, toggles the TOGGLE bit, sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint interrupt. 2. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet, the MCU first must obtain the data count value. After reading the data packet, the MCU must clear the interrupt and clear the NACK bit to allow the reception of the next data packet from the host PC. 3. If the NACK bit is set to 1 when the in token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the in token packet is received, the UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, then no handshake is returned to the host PC. Status Stage Transaction 1. For IN endpoint 0, the MCU clears the data count value to zero, sets the TOGGLE bit to 1, and clears the NACK bit to 0 to enable the data packet to be sent to the host PC. Note that for a status stage transaction a null data packet with a DATA1 PID is sent to the host PC. 2. The host PC sends an IN token packet addressed to IN endpoint 0. After receiving the IN token, the UBM transmits the null data packet to the host PC. If the data packet is received without errors by the host PC, an ACK handshake is returned. Upon receiving the ACK handshake, the UBM toggles the TOGGLE bit, sets the NACK bit to 1, and asserts the endpoint interrupt. 3. If the NACK bit is set to 1 when the IN token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC then the UBM prepares to retransmit the same data packet again. 2.2.7.1.2 Control Read Transfer (In Transfer) The host PC uses a control read transfer to read data from the USB function. A control read transfer consists of a setup stage transaction, at least one in data stage transaction, and an out status stage transaction. The steps followed for a control read transfer are: Initialization Stage 1. MCU initializes IN endpoint 0 and OUT endpoint 0 by programming the appropriate USB endpoint configuration blocks. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and clearing the NACK bit for both IN endpoint 0 and OUT endpoint 0. Setup Stage Transaction 1. The host PC sends a setup token followed by the setup data packet addressed to OUT endpoint 0. If the data is received without an error, the UBM writes the data to the setup data packet buffer, sets the setup stage transaction (SETUP) bit to a 1 in the USB status register, returns an ACK handshake to the host PC, and asserts the setup stage transaction interrupt. Note that as long as the setup stage transaction (SETUP) bit is set to a 1, the UBM returns a NACK handshake for any data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values. 2. The MCU services the interrupt, reads the setup data packet from the buffer, and decodes the command. If the command is not supported or is not valid, the MCU sets the STALL bit in the OUT endpoint 0 configuration byte and the IN endpoint 0 configuration byte before clearing the setup stage transaction (SETUP) bit. This causes the device to return a STALL handshake for any data stage or 30 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 status stage transactions. If the command decoded is valid and is supported, the MCU clears the interrupt, which automatically clears the setup stage transaction bit. The MCU also sets the TOGGLE bit in the IN endpoint 0 configuration byte to a 1. For control read transfers, the PID used by the host for the first IN data packet is a DATA1 PID. Data Stage Transaction 1. The data packet to be sent to the host PC is written to the IN endpoint 0 buffer by the MCU. The MCU also updates the data count value then clears the IN endpoint 0 NACK bit to a 0 to enable the data packet to be sent to the host PC. 2. The host PC sends an IN token packet addressed to IN endpoint 0. After receiving the IN token, the UBM transmits the data packet to the host PC. If the data packet is received without an error by the host PC, then an ACK handshake is returned. The UBM then toggles the TOGGLE bit, sets the NACK bit to 1, and asserts the endpoint interrupt. 3. The MCU services the interrupt and prepares to send the next data packet to the host PC. 4. If the NACK bit is set to 1 when the IN token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC, then the UBM prepares to retransmit the same data packet again. 5. MCU continues to send data packets until all data has been sent to the host PC. Status Stage Transaction 1. For OUT endpoint 0, the MCU sets the TOGGLE bit to 1, then clears the NACK bit to a 0 to enable a data packet to be sent by the host PC. Note that for a status stage transaction a null data packet with the DATA1 PID is sent by the host PC. 2. The host PC sends an OUT token packet and the null data packet to OUT endpoint 0. If the data packet is received without an error the UBM updates the data count value, toggles to the TOGGLE bit, sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint interrupt. 3. The MCU services the interrupt. If the status transaction completed successfully, then the MCU clears the interrupt and clears the NACK bit. 4. If the NACK bit is set to 1 when the OUT token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the OUT token packet is received, the UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, no handshake is returned to the host PC. 2.2.7.2 Interrupt Transfers The TAS1020B supports interrupt data transfers both to and from the host PC. Devices that need to send or receive a small amount of data with a specified service period should use the interrupt transfer type. IN endpoints 1 through 7 and OUT endpoints 1 through 7 can all be configured as interrupt endpoints. 2.2.7.2.1 Interrupt Out Transaction The steps followed for an interrupt out transaction are: 1. MCU initializes one of the OUT endpoints as an out interrupt endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and clearing the NACK bit. 2. The host PC sends an OUT token packet followed by a data packet addressed to the OUT endpoint. If the data is received without an error then the UBM writes the data to the endpoint buffer, updates the data count value, toggles the toggle bit, sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint interrupt. 3. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet, the MCU must first obtain the data count value. After reading the data packet, the MCU clears the Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 31 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com interrupt and clears the NACK bit to allow the reception of the next data packet from the host PC. 4. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NACK handshake to the host PC. If the STALL bit is set to 1 when the data packet is received, the UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, no handshake is returned to the host PC. NOTE In double buffer mode for interrupt out transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM writes the data packet to the X buffer. If the toggle bit is a 1, the UBM writes the data packet to the Y buffer. When a data packet is received, the MCU determines which buffer contains the data packet by reading the toggle bit. However, when using double buffer mode, the possibility exists for data packets to be received and written to both the X and Y buffer before the MCU responds to the endpoint interrupt. In this case, simply use the toggle bit to determine which buffer contains the data packet does not work. Hence, in double buffer mode, the MCU reads the X buffer NACK bit, the Y buffer NACK bit, and the toggle bit to determine the status of the buffers. 2.2.7.2.2 Interrupt In Transaction The steps followed for an interrupt in transaction are: 1. MCU initializes one of the IN endpoints as an in interrupt endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and setting the NACK bit. 2. The data packet to be sent to the host PC is written to the buffer by the MCU. The MCU also updates the data count value and clears the NACK bit to 0 to enable the data packet to be sent to the host PC. 3. The host PC sends an IN token packet addressed to the IN endpoint. After receiving the IN token, the UBM transmits the data packet to the host PC. If the data packet is received without errors by the host PC, an ACK handshake is returned. The UBM then toggles the toggle bit, sets the NACK bit to a 1, and asserts the endpoint interrupt. 4. The MCU services the interrupt and prepares to send the next data packet to the host PC. 5. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NACK handshake to the host PC. If the STALL bit is set to a 1 when the IN token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC, then the UBM prepares to retransmit the same data packet. NOTE In double buffer mode for interrupt IN transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM reads the data packet from the X buffer. If the toggle bit is 1, the UBM reads the data packet from the Y buffer. 2.2.7.3 Bulk Transfers The TAS1020B supports bulk data transfers both to and from the host PC. Devices that need to send or receive a large amount of non time-critical data should use the bulk transfer type. IN endpoints 1 through 7 and OUT endpoints 1 through 7 can be configured as bulk endpoints. TAS1020B supports single and double buffering for bulk transfers. 2.2.7.3.1 Bulk Out Transaction Using MCU The steps for a bulk out transaction are as follows: 32 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 1. MCU initializes one of the OUT endpoints as an OUT bulk endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and clearing the NACK bit. 2. The host PC sends an OUT token packet followed by a data packet addressed to the OUT endpoint. If the data is received without an error, the UBM writes the data to the endpoint buffer, updates the data count value, toggles the toggle bit, sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint interrupt. 3. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet, the MCU must first retrieve the data count value. After reading the data packet, the MCU clears the interrupt and clears the NACK bit to allow the reception of the next data packet from the host PC. 4. If the NACK bit is set to 1 when the data packet is received, the UBM simply returns a NACK handshake to the host PC. If the STALL bit is set to 1 when the data packet is received, the UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, no handshake is returned to the host PC. NOTE In double buffer mode for bulk OUT transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM writes the data packet to the X buffer. If the toggle bit is a 1, the UBM writes the data packet to the Y buffer. When a data packet is received, the MCU determines which buffer contains the data packet by reading the toggle bit. However, when using double buffer mode, data packets may be received and written to both the X and Y buffer before the MCU responds to the endpoint interrupt. In this case, simply using the toggle bit to determine which buffer contains the data packet does not work. Hence, in double buffer mode, the MCU reads the X buffer NACK bit, the Y buffer NACK bit, and the toggle bit to determine the status of the buffers. 2.2.7.3.2 Bulk In Transaction Using MCU The steps followed for a bulk in transaction are: 1. MCU initializes one of the IN endpoints as an IN bulk endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint and setting the NACK bit. 2. The data packet to be sent to the host PC is written to the buffer by the MCU. The MCU also updates the data count value then clears the NACK bit to a 0 to enable the data packet to be sent to the host PC. 3. The host PC sends an IN token packet addressed to the IN endpoint. After receiving the IN token, the UBM transmits the data packet to the host PC. If the data packet is received without errors by the host PC, an ACK handshake is returned. The UBM then toggles the toggle bit, sets the NACK bit to a 1, and asserts the endpoint interrupt. 4. The MCU services the interrupt and prepares to send the next data packet to the host PC. 5. If the NACK bit is set to 1 when the in token packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC, the UBM prepares to retransmit the same data packet again. NOTE In double buffer mode for bulk IN transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM reads the data packet from the X buffer. If the toggle bit is a 1, the UBM reads the data packet from the Y buffer. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 33 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 2.2.7.3.3 Bulk Out Transaction Through DMA This transaction is used by mass storage class USB applications to move bulk data to an external device via the TAS1020B DMA resources. The difference between MCU-supported bulk transactions and DMA-supported bulk transactions lies in how the data in the assigned out endpoint buffer is distributed to its final destination. Two modes of DMA operation are possible. One mode is a software handshake mode utilizing synchronization communication between the MCU, the USB Buffer Manager (UBM), and an external device. The second mode is a direct exchange mode that bypasses communication with the MCU and directly outputs USB packets to an external device via the DMA resources. Higher bandwidth transactions can be achieved in the direct exchange mode. In both modes, the on-chip C-port is used to output the received bulk data to an external device. To implement DMA-supported transactions, the C-port must be programmed to operate in either a general-purpose (GP) mode or an Audio Codec '97 (AC97) mode. When in the general-purpose mode, SYNC is disabled when there is no valid data in the buffer to be output; in the AC97 mode, the time slot valid bits in the tag field are disabled when there is no valid data in the buffer to be output. Software Handshake Using MCU, UBM, and External Device Bulk data has the lowest priority of all transfers on the USB bus. But when there is little other activity on the USB bus, bulk transfers can achieve significant transfer rates. Bulk transfer rates then can fluctuate greatly, and for this reason it is sometimes necessary to monitor the transfer rate of bulk transfers in order to throttle back the transfer rate when the rate exceeds the bandwidth of the target device. The software handshake mode is provided to enable the implementation of just such a throttling of data. The following steps explain the operation of the software handshake mode. 1. The MCU initializes one of the OUT endpoints as a bulk OUT endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and clearing the NACK bit. 2. To configure a given DMA channel to process a given endpoint in a software handshake mode, the MCU must – Enable the handshake mode by setting the HSKEN bit in the DMA channel control register (DMACTL0 and DMACTL1) to 1. In this same register the MCU must also program the USB endpoint direction and endpoint number fields. – Program the DMA current buffer content register (DMABPCT0 and DMABPCT1) with the number of bulk out packets to be handled by the DMA process without MCU intervention once the MCU has invoked the DMA process. – Program the DMA channel time slot assignment register (DMATSH0 and DMATSH1) with the time slot assignments to be supported by the DMA channel and the number of bytes to be transferred for each supported time slot. 3. The MCU must also appropriately configure the C-port. (See Section 2.2.7.4 for more detail on initializing the C-port). Note that if the C-port is placed in mode 0 (general-purpose mode) the CPTBLK bit in the codec port interface configuration register 4 must be set to 1 to assure that SYNC is disabled when there is no valid data in the buffer to be output. 4. Data is now ready to be received. The UBM, after receiving the bulk out packet and placing it in the appropriate buffer, toggles the toggle bit if the double-buffer mode is set, sets the NACK bit to 1, stores the packet data count in the data count register, and issues an interrupt to the MCU. 5. If the external device indicates that it is ready to receive data, the MCU enables the DMA process by setting the DMAEN bit the DMA channel control register (DMACTL0 and DMACTL1). (Handshaking between the MCU and external device will have to have taken place earlier to determine the status of the external device). 6. Once enabled, the DMA engine proceeds to transfer the contents of the buffer(s) to the C-port for transmittal to the external device. Data availability in the buffer(s) is determined by examining the NACK flags - which are set to 1 when data has been received. For the double buffer case, the buffer to 34 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 be used to retrieve data for the C-port is determined by not only examining the NACK flags but also by monitoring the state of the toggle bit. The NACK bit is cleared by the DMA logic (as opposed to the MCU) each time an entire buffer content has been transferred to the C-port via DMA. 7. If the number of bulk out packets to be handled by the DMA process without MCU intervention is greater than one (the number can be as high as 64K packets), multiple buffer writes take place before the DMA process completes. Every time a data packet is written to a given buffer, the UBM generates the MCU endpoint interrupt. If the MCU wishes to remain autonomous to the DMA process, the MCU must mask off the MCU endpoint interrupt (by clearing the OEPIE bit in the USB out configuration register OEPCNFx) before enabling the DMA process. 8. When the DMA process completes, the DMA channel disables itself and issues a DMA0 or a DMA1 interrupt to the MCU. Upon receiving the interrupt, the MCU knows that DMABPCT packets have been sent out to the C-port. The MCU then enables the appropriate endpoint interrupt (if it had been previously masked off). The process is now complete. Direct Exchange Mode This mode offers the highest bandwidth for bulk OUT transactions. The process is almost identical to the software handshake mode, the only difference being that the Direct Exchange mode, once enabled, runs continuously until disabled; whereas the Software handshake mode only remains active for the processing of DMABPCT packets. The Direct Exchange mode is selected by clearing the bit HSKEN in the DMA channel control register (DMACTL0 and DMACTL1). When the MCU enables the DMA process, after appropriately setting up the endpoint configuration registers, the C-port configuration registers, and the DMA channel, the DMA process remains active until disabled by the MCU. While the DMA channel is active, received packets continue to be retrieved from the appropriate endpoint buffer and transferred to the C-port for transmission to the external device. 2.2.7.3.4 Bulk In Transaction Using DMA The TAS1020B does not support BULK IN using the DMA resources. 2.2.7.4 Isochronous Transfers The TAS1020B supports isochronous data transfers both to and from the host PC. Devices that need to send or receive data at a constant rate must use the isochronous transfer type rate if the bandwidth of the data exceeds the USB bandwidth allotted to interrupt type transactions. IN endpoints 1 through 7 and OUT endpoints 1 through 7 can all be configured as isochronous endpoints. Isochronous transfers must include the use of a DMA channel; MCU-supported isochronous transfers are not allowed. Since the TAS1020B has only two DMA channels, at any point in time only two isochronous transactions can be concurrently supported by the TAS1020B. To setup an isochronous IN or an isochronous OUT transaction, the MCU must initialize the appropriate IN or OUT USB endpoint configuration block. For isochronous transactions, this entails programming the buffer size and buffer base address, enabling the endpoint interrupt, setting the ISO bit (to flag that the endpoint is an isochronous endpoint), clearing the NACK bit, and enabling the endpoint. When the ISO bit is set, the hardware configures the buffer to be a single circular buffer (see Section 2.2.7.4.1), using the endpoint buffer size register I/OEPBSIZx and buffer base address register I/O EPBBAXx. The size of the circular buffer is the size specified in I/OEPSIZx. (This is not to be confused with the same value in I/OEPSIZx yielding two buffers of that size when the double buffer mode is selected for control, interrupt, and bulk transactions.) The TAS1020B DMA engine has two DMA channels. Each channel can be assigned to any IN or OUT endpoint that has been configured as an isochronous endpoint. (As previously discussed, DMA channels can also be assigned to bulk out endpoints). If an isochronous OUT endpoint receives data, the DMA channel assigned to the endpoint will retrieve the data from the endpoint buffer and transfer it to the C-port for outputting to the external device. If a DMA channel is assigned to an isochronous IN endpoint, the DMA channel transfers external device data received on the C-port to the IN endpoint buffer. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 35 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Each DMA channel can only implement data flow between endpoint buffers and the C-port. The configuration of each DMA channel includes a 14-bit field that defines which of the up to 14 time slots in the C-port audio frame the DMA channel supports. Both DMA channels could thus service OUT endpoints, or IN endpoints, with each DMA channel supporting different time slots in the audio frame. Each DMA channel also provides a current buffer count register (DMABCNT0/1). For isochronous OUT transactions, the count in the register represents the number of bytes being transferred from the OUT endpoint buffer to the C-port during the current USB frame. A new count is derived at each USB SOF event, and is the value of the write pointer address setting minus the read pointer address setting at the time of the USB SOF event. The MCU can read the content of this register. The steps required to service DMA-supported isochronous transfers are: 1. The MCU initializes an IN or OUT USB endpoint configuration block. This entails programming the buffer size and buffer base address, setting the ISO bit, setting the number of bytes per isochronous channel, clearing the NACK bit, and enabling the endpoint. Because the endpoint is configured as an isochronous endpoint, the buffer configuration parameters are used to implement a circular buffer rather than one or two linear buffers, and the size specified is the size of the single circular buffer. 2. The MCU configures the selected DMA channel. This entails: – Programming registers DMATSH0/1 and DMATSL0/1, which consists of assigning the time slots to be used and the number of bytes to be transferred per time slot. – Programming register DMACTL0/1, which consists of setting the USB endpoint direction, selecting the endpoint number, and setting the DMA channel enable bit DMAEN. 3. The MCU configures the C-port. This entails: – Programming register CPTCNF1, which consists of setting the number of time slots per audio frame and selecting the C-port interface mode (general purpose mode, AIC mode, etc.). – Programming register CPTCNF2, which consists of setting the length of time slot 0 (number of CSCLK serial clock cycles), setting the length of the remaining time slots (which are all the same in length), and setting the number of data bits per time slot. – Programming register CPTCNF3, which consists of: – Setting the state of DDLY. A 1 programs a one CSCLK clock delay on the data output and data input signals with reference to the leading edge of CSYNC. A 0 removes the delay. – Setting the state of TRSEN. A 1 sets the C-port output to the high-impedance state for those time slots that have no valid data. – Setting the state of CSCLKP. A 1 programs the C-port to be CSCLK falling edge active (CDATO and CSYNC transition on falling edge of CSCLK and DATI is sampled on rising edge of CSCLK). A 0 results in activity on the opposite edges of CSCLK. – Setting the state of CSYNCP. A 1 programs CSYNC to be active high. A 0 programs CSYNC to be active low. – Setting the state of CSYNCL. A 1 programs the length of CSYNC to be the same number of CSCLK cycles as time slot 0. A 0 programs CSYNC to be one CSCLK cycle in length. – Setting the state of BYOR. A 1 results in the DMA reversing the byte order in moving data to/from the endpoint buffer. – Setting the state of CSCLKD. A 1 sets the CSCLK port as an input port (TAS1020B receives CSCLK). A 0 sets the CSCLK port as an output port (TAS1020B sources CSCLK). – Setting the state of CSYNCD. A 1 sets the CSYNC port as an input port (TAS1020B receives CSYNC). A 0 sets the CSYNC port as an output port (TAS1020B sources CSYNC). – Programming register CPTCNF4, which consists of: – Specifying the 4-Bit field ATSL. This field defines which time slot is to be used for secondary communication (command/status) address and data. – Setting the state of CPTBLK. When DMA is to be used to transport USB bulk transfers to external devices via the C-port, the C-port must be placed in either a general-purpose mode or an AC '97 mode, and CPTBLK must be set to one. When the C-port is placed in the general-purpose mode, a state of 1 for CPTBLK results in CSYNC only being present when valid data is present in the current frame. When the C-port is placed in the AC '97 mode, a state 36 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 of 1 for CPTBLK results in CSYNC always being present, but the tag bits in time slot 0 being set to indicate the presence or absence of data. When CPTBLK is set to 0, CSYNC and CSCLK are free running once the C-port is enabled. – Specifying the 3-Bit field DIVB. This defines the divide ratio of MCLK to CSCLK. – Programming bits 4-7 of register CPTCTL to enable or disable the C-port transmit and receive interrupts. Bits 1-2 of register CPTCTL are used to select between primary and secondary codecs when using two codecs in the AC '97 mode. Bit 0 of register CPTCTL (CRST), when cleared to 0, is used to issue resets to external devices via the CRESET output pin. NOTE C-port registers CPTADR, CPTDATL, and CPTDATH are accessed during run time operation to set the address, the data, and the mode (receive (status) or command (write)) for secondary communications. Registers CPTVSLL and CPTVSLH are only used when the AC '97 mode is selected and are used to specify which time slots in the audio frame contain valid data. Registers CPTRXCNF2, CPTRXCNF3, and CPTRXCNF4 must be initialized when the C-port is used in the I2S mode (mode 5) to support an ADC and a DAC running at different frequencies. 2.2.7.4.1 Circular Memory Buffer Implementation A significant feature of DMA-supported isochronous transfers is the circular memory structure used to buffer the incoming data. In most applications, the C-port timing is derived from the USB frame rate using a soft-PLL provided in the TAS1020B firmware. However, the USB frame rate can vary within specified boundaries, and the output phase of the PLL can lag (or lead) the input during such variations. If a linear ping pong buffer implementation is used, tolerance must be built into switching between buffers to accommodate all possible magnitudes of variation in the relative timing between the input and output time references. A circular buffer topology greatly simplifies the implementation of the buffer as the need for decision points on when to switch buffers is eliminated. The circular buffer implementation used in TAS1020B utilizes the same endpoint start (I/OEPBBAXx) and size (I/OEPBSIZx) assignment used by the linear buffer implementation, and the size of the circular buffer is the size specified in I/OEPBSIZx. The circular buffer implementation does require the use of two additional registers - a read pointer and a write pointer. These two registers are controlled by hardware, but are made available to the MCU for debug purposes. Circular Buffer Operation for Isochronous OUT Transactions The operation of the circular buffer for isochronous OUT transactions is as follows. • Initially, the read and write pointers are set in hardware to the OUT endpoint start address. • As the first packet of isochronous data addressed to the endpoint is received, the UBM stores the data into the circular buffer and updates the value of the write pointer by a count of one for each byte written into the buffer. • As soon as the DMA channel detects that the read and write pointers are not the same value (data is available), the DMA channel could begin immediately retrieving data and outputting it to the C-port. However, the DMA channel waits until the next USB SOF is received. • Once the DMA channel has waited until the next SOF is received, the buffer contains a full packet of data. Upon receiving SOF, the DMA channel further waits until the start of the next C-port frame and then begins transferring the buffered data to the C-port, updating the read pointer by one count for each byte of data transferred. At the C-port the data is output to the external device in accordance with the timing requirements of the external device (8 frames for 8 kHz audio sampling, 48 frames for 48 kHz audio sampling, etc.). The DMA channel continues to retrieve data from the buffer and output it to the C-port, update the read pointer, and check the value of the write pointer. Should the DMA-controlled read pointer value ever equal the value of the UBM-controlled write pointer, the process goes on hold and awaits the next USB SOF, where the process again resumes. When the UBM completes writing a packet of data into the endpoint buffer, it loads the data count Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 37 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com value of that packer (number of data samples, not bytes) into field DCNTX/Y of register OEPDCNTX/Yx. The register chosen, OEPDCNTX or OEPDCNTY, is determined by the LSB of the frame count register USBFNL. An LSB value of 1 chooses OEPDCNTY; a value of 0 chooses OEPDCNTX. This count value does not play a role in implementing the data flow for isochronous out transactions, but is provided for and can be accessed by the MCU. As is discussed in the next section, the counts do play a role in implementing the data flow for isochronous in transactions. • The streaming of audio data via the DMA channel continues indefinitely until the DMA engine is halted by the MCU. Circular Buffer Operation for Isochronous IN Transactions For isochronous out transactions, the handshake implemented between the USB bus and the output device ensures that at each USB SOF event, the output has access to a complete USB frame of data. For isochronous in transactions, the mirror condition must be true: the handshake implemented between the USB bus and the input device must ensure that at each USB SOF event, the UBM has access to one or more complete frames of device data. Isochronous out transactions also ensure, by definition, that a complete USB frame of data is transmitted between USB SOF events. But the mirror condition here is not true, there may not be an integer number of device frames received between USB SOF events. If, at each USB SOF event, the UBM is to have access to one or more complete frames of data from the input device, the latest codec frame available to the UBM has to have completed prior to the USB SOF event. But it is not known when the last input device frame to complete prior to the USB SOF event occurs. Thus a timing mark must be set up to mark the worse case arrival time of the last complete input device frame prior to the USB SOF event. The slowest sampling rate supported for an input device is set at 8 kHz (8 kHz audio sampling). At 8 kHz, a frame arrives from the input device every 0.125 milliseconds, which is 1500 12 MHz USB clock periods. Thus a time mark can be set to occur 1500 clock periods before the next USB SOF event. When this time mark occurs, the DMA completes the current input device frame, if a frame is currently being received, and then sets a handshake flag. The DMA also updates the content of register IEPDCNTX/Y with the total number of samples collected since the previous handshake flag was set. When the USB SOF event occurs, the UBM looks at the flag to see if data is available. If data is available, the UBM refers to the count in the register to determine how much data is to be output on the next isochronous in transaction. To accommodate variations in the number of clocks at the output of the soft PLL, with respect to the incoming 12-MHz USB data rate, the time mark count is actually set to 1511, rather than 1500. The extra 11 clock periods assures that the last frame prior to the USB SOF event will have completed. The flag used is the NACK bit in the IEPDCNTX/Y register, and the data count is the 7-bit DCNTX/Y field in the same register. For isochronous in transactions, the register chosen, IEPDCNTX or IEPDCNTY, is also determined by the LSB of the frame count register USBFNL. But in the case of isochronous in transactions, an LSB value of 1 chooses IEPDCNTX and a value of 0 chooses IEPDCNTY. The selection logic for isochronous in transactions then is the reverse of that used for isochronous out transactions. The operation of the circular buffer for isochronous in transactions is as follows. • Initially, the read and write pointers are set in hardware to the IN endpoint start address. At the same time the NACK flags in the IEPDCNTX and IEPDCNTY registers are set to logic 1 and the DCNTX and DCNTY counts are cleared. • As the input device frames are received, they are stored in the circular buffer by the DMA engine. As each byte is stored in the buffer, the DMA engine updates the write pointer by one count, and also keeps count of the number of samples being stored. • When the time mark occurs, marking that there are 1511 USB clock periods remaining until the next USB SOF event occurs, the DMA engine awaits the completion of the current incoming input device frame (if one is currently being received). When the incoming input device frame completes, the DMA engine sets the NACK flag in IEPDCNTX/Y to logic 0 and loads the number of samples received into the DCNTX/Y field of IEPDCNTX/Y. 38 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 • At this time, the DMA engine zeroes its running count of data samples and awaits the next input device frame. For the DMA engine, the process repeats, and at the next time mark, the DMA engine sets the NACK flag in IEPDCNTX/Y to logic 0 and loads the number of samples received into the DCNTX/Y field of IEPDCNTXY. • At the same time that the DMA engine reinitializes itself to receive the next input device frame, the UBM has noted the clearing of the NACK flag in IEPDCNTX/Y. When this occurs, the UBM knows that one or more complete frames reside in the circular buffer, starting at the address pointed to by the read buffer, and that the integer number of frames comprise a total of DCNTX/Y samples. When the USB SOF event occurs, the UBM is thus prepared and can respond to the USB isochronous in transaction when it occurs. As the UBM retrieves data during the isochronous in transaction, it updates the read pointer by one count for each byte retrieved. When DCNTX/Y samples have been output, the NACK bit in IEPDCNTX/Y is set back to logic 1 and the isochronous transaction is terminated. The UBM now awaits the clearing of the NACK bit in IEPDCNTX/Y and the occurrence of the next USB SOF event, at which time the process repeats. The UBM now continues to alternate (ping pong) between the data count and NACK flag value in register IEPDCNTX and the data count and NACK flag value in register IEPDCNTY until the DMA process is terminated by the MCU. • If an isochronous in token is received when there is no new data to be output (the NACK flag bits in both IEPDCNTX and IEPDCNTY registers are at logic 1), the UBM will respond to the isochronous in request with a NULL packet. 2.2.8 Microcontroller Unit The TAS1020B chip contains an 8-bit microcontroller core for control and supervisory functions. The microcontroller core used is based on the industry standard 8052. It is software compatible (including instruction execution times) with the industry standard 8052AH and 8052BH discrete devices, having all their core features plus the additional features corresponding to standard 8052 / 8032 / 80C52BH / 80C32BH / 87C52 parts - except the ONCE mode and program lock are not supported. The MCU core has three 16-bit timer/counter units and a full-duplex serial port (UART). The timer/counter units and the UART are made available via the port 3 bits; thus some of the port 3 bits have dual functionality assignments in accordance with the 80C51 family of microcontrollers (see Section 2.2.11 for more detail on the dual functionality of port 3). 2.2.9 External MCU Mode Operation An external MCU mode of operation is provided for firmware development using an in-circuit emulator (ICE). The external MCU mode is selected by setting pin EXTEN on the TAS1020B high. When the external MCU mode is selected, the internal 8052 MCU core of the TAS1020B is disabled. Also in the external MCU mode, the GPIO ports are used for the external MCU data, address, and control signals. See Section 1.7, Terminal Functions - External MCU Mode, for details. When in the external mode of operation, the external MCU or ICE is able to access the memory mapped IO registers, the USB configuration blocks and the USB buffer space in the TAS1020B. Texas Instruments has developed a TAS1020B evaluation module (EVM) to allow customers to develop application firmware and to evaluate device performance. The EVM board provides a 40-pin dip socket for an ICE and headers to allow expansion of the system in a variety of ways. 2.2.10 Interrupt Logic The 8052 MCU core used in the TAS1020B supports the five standard 8052 MCU interrupt sources. These five standard MCU interrupt sources are timer 0, timer 1, serial port, external 1 (INT1), and external 0 (INT0).The timer 0, timer 1, and serial port interrupts are MCU-internal interrupts, but INT0 and INT1 are external to the MCU core. Figure 2-2 shows the associated interrupt circuitry external to the MCU core, but within the TAS1020B chip. INT0 is input into the MCU core via port 3 bit P3.2, and INT1 is input into the MCU core via port 3 bit P3.3. P3.3 can also be configured, under firmware control, to serve as a general-purpose IO (GPIO) port bit. But the input side of P3.2 must be dedicated to servicing the INT0 function, as all additional interrupt sources from within the TAS1020B device are ORed together to Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 39 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com generate the INT0 signal into port 3, bit P3.2. The other interrupt sources are: the eight USB IN endpoints, the eight USB OUT endpoints, USB function reset, USB function suspend, USB function resume, USB start-of-frame, USB pseudo start-of-frame, USB setup stage transaction, USB setup stage transaction over-write, codec port interface transmit data register empty, codec port interface receive data register full, I2C interface transmit data register empty, I2C interface receive data register full, DMA channel 0, DMA channel 1, and the external interrupt XINT. 40 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B DP DM USB Bus Suspend Counter En clk Decode > 5 ms Reset Reset Counter clk Decode > 2.5 us En Interrupt Vector Reg (VECINT) Logic Interrupts Decode /XINT Int WE D[0:7] NX2 NX1 MCU write to Interrupt Vector Register ”clears” current vector to next vector, or to 24h if no other interrupt pending RST IDL Power Control Register (PCON) USB Interrupt Mask Register (USBMSK) Internal Interrupts (After Masks Applied) Must be programmed to be low level triggered (ITO bit in MCU’s TCON control register = 0), as multiple internal TAS1020B events can occur concurrently . The internal hardware assures that each interrupt remains low until the MCU signals that the interrupt has been serviced. Function Suspend Request Interrupt Function Resume Request Interrupt P3MSK7 P3MSK2 P3MSK0 P3.7−IN P3.6−IN P3.5−IN P3.4−IN P3.3−IN P3.1−IN P3.0−IN P3.7−IN P3.2−IN P3.0−IN USB Reset Interrupt Suspend FRSTE USB Control Register (USBCTL) XINTEN 7 6 5 0 Global Control Register (GLOBCTL) RESR 0 4 5 6 7 Cl Cl Cl Decode Resume Int Decode Suspend Int Decode USB Reset Int USB Status Register (USBSTA) 0 4 5 6 7 0 3 4 5 7 8052 MCU CORE CRST 0 1 7 Suspend Global Reset Codec Port Interface Control and Status Register (CPTCTL) Clear USB Serial Interface Engine (SIE) and USB Buffer Manager (UBM) 7 1 0 PLL SubSystem Turn Off Turn On D Q CL ’1’ P3 Mask Register (P3MSK) 7 6 3 2 1 0 Synchronized XINT Remote ”Wake−Up Interrupt Suspend TAS1020B Clocks Q D Q D Q D Q D 24 MHz Clk Q D CL 24 MHz Clk Set Set Set Q D 48 MHz Clk MRESET RSTO CRESET XINT (P3.2−IN) SUSR RSTR RESR SUSR RSTR TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Figure 2-2. TAS1020B Interrupt, Reset, Suspend, and Resume Logic Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 41 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com The events that trigger the interrupt sources are: • USB OUT endpoint interrupts: these interrupts are issued by the USB Buffer Manager (UBM) whenever a complete data packet has been received and stored in an endpoint buffer. Each endpoint is assigned a dedicated OUT endpoint interrupt. For isochronous transactions, however, OUT endpoint interrupts are not issued. The firmware must clear OUT endpoint interrupts by writing to the interrupt vector register. • USB IN endpoint interrupts: these interrupts are issued by the USB buffer manager (UBM) whenever it receives an ACK handshake packet from the host PC indicating that a data packet sent by the UBM was received without error. Each endpoint is assigned a dedicated IN endpoint interrupt. For isochronous transactions, however, IN endpoint interrupts are not issued. The firmware must clear IN endpoint interrupts by writing to the interrupt vector register. • USB function reset interrupt: whenever the host PC issues a USB reset, the bit RSTR in the USB status register USBSTA is set. The setting of this bit causes all of the USB-related logic blocks in the TAS1020B to be reset. If the function reset enable (FRSTE) bit in the USB control register USBCTL is set, the setting of bit RSTR in the USB status register results in a global reset being issued - which resets the MCU core and activates the reset output RSTO. If bit FRSTE is not set, the setting of bit RSTR results in the USB function reset interrupt being issued. If a global reset is issued, it clears the USB status register USBSTA, and thus clears bit RSTR. If a USB function reset interrupt is issued, the interrupt and bit RSTR must be cleared in firmware by writing to the interrupt vector register. • USB function suspend interrupt: whenever the host PC keeps the USB bus in the idle or j state for more than 5 ms, bit SUSR in the USB status register USBSTA is set. This, in turn, results in the activation of the USB function suspend interrupt. The interrupt and bit SUSR must be cleared in firmware by writing to the interrupt vector register. • USB function resume interrupt: whenever a suspend state is active and the host PC resumes activity on the USB bus, bit RESR in the USB status register USBSTA is set. This, in turn, results in the activation of the USB function resume interrupt. The interrupt and bit RESR must be cleared in firmware by writing to the interrupt vector register. • USB start-of-frame interrupt: whenever the TAS1020B detects the reception of a start-of-frame (SOF) packet from the host PC, bit SOF in the USB status register USBSTA is set. This, in turn, results in the activation of the USB start-of-frame interrupt. The interrupt and bit SOF must be cleared in firmware by writing to the interrupt vector register. • USB pseudo start-of-frame interrupt: the TAS1020B employs a counter that runs between USB start-of-frame events, and is cleared upon every reception of a USB SOF event. This counter is included in the TAS1020B to generate pseudo start-of-frame interrupt in case the SOF packet on the USB bus is corrupted. This is done to maintain synchronization to the USB bus and maintain the fidelity any on going streaming audio application. If this count ever reaches a value representative of a time span longer than the 1 ms period of a USB frame, a USB SOF was not received. In such an event, bit PSOF in the USB status register USBSTA is set. This, in turn, results in the activation of the USB pseudo start-of-frame interrupt. The interrupt and bit PSOF must be cleared in firmware by writing to the interrupt vector register. • USB setup stage transaction interrupt: whenever a control transaction is initiated by the host PC, and the setup data packet following the setup token packet is received without error, bit SETUP in the USB status register USBSTA is set. This, in turn, results in the activation of the USB setup stage transaction interrupt. The interrupt and bit SETUP must be cleared in firmware by writing to the interrupt vector register. • USB setup stage transaction overwrite interrupt: the USB 1.1 specification states that should a setup transaction be received before a previously initiated control transaction is complete, the current control transaction must be aborted and the new transaction processed. The USB setup stage transaction interrupt addresses this requirement. The timing conditions under which this interrupt is issued are shown in Figure 2-3. In Figure 2-3, the host has sent two control transactions. Having received the setup data packet of the first transaction without error, the SETUP bit in the USB status register USBSTA is set and the USB setup stage transaction interrupt issued. While the MCU core is still processing the USB setup stage 42 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B SETUP TOKEN PACKET SETUP DATA PACKET ACK PACKET CONTROL TRANSACTION #1 CONTROL TRANSACTION #2 MCU CORE PROCESSING INTERRUPT USB Setup Stage Transaction Overwrite Interrupt USB Setup Stage Transaction Interrupt USB Bus Traffic SETUP Bit In USB Status Register STPOW Bit In USB Status Register SETUP TOKEN PACKET SETUP DATA PACKET ACK PACKET TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 transaction interrupt (as indicated by the set state of the SETUP bit, which the MCU does not clear until exiting the USB setup stage transaction interrupt service routine), the host issues another control transaction. Issuing another USB setup stage transaction interrupt would not be of value, as the MCU is still in the USB setup stage transaction interrupt service routine processing the first control transaction. Thus the USB setup stage transaction overwrite interrupt is used to indicate that a second control transaction has been received while still processing the first control transaction. If a setup data packet is received without error while the SETUP bit is set, the STPOW bit in the USB status register USBSTA is set and the USB setup stage transaction overwrite interrupt is issued. The interrupt and STPOW bit must be cleared in firmware by writing to the interrupt vector register. Figure 2-3. Activation of Setup Stage Transaction Overwrite Interrupt • Codec port interface transmit data register empty interrupt: codec port modes AC '97 and AIC, and the general-purpose codec port mode, all support secondary communication. Both secondary read and secondary write modes are supported. For the write mode (R/W bit in the codec port interface address register CPTADR cleared to logic 0), command/status can be sent to the codec port by the MCU for transmission to the codec. The codec hardware inserts the data into the proper time slot in the codec frame and transmit the data. The MCU writes the command/status data to the codec port interface data register CPTDATL (and register CPTDATH for 16-bit data). The data written by the MCU is not output until the address is written to the codec port interface address register CPTADR. Upon writing the address to CPTADR (and clearing bit R/W), the codec clears the transmit data register empty bit TXE in the codec port interface control and status register CPTCTL to logic 0. The clearing of this bit flags the hardware that new command/status data has been output. When the command/status data is taken by the codec, bit TXE is set to 1, and the codec port interface transmit data register empty interrupt is issued. The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear the TXE bit. • Codec port interface receive data register full interrupt: codec port modes AC '97 and AIC, and the general-purpose codec port mode, all support secondary communication. Both secondary read and secondary write modes are supported. For the read mode (R/W bit in the codec port interface address register CPTADR set to logic 1), command/status data received by the codec can be retrieved by the MCU. Upon receiving secondary command/status data, the codec hardware transfers the data to the codec port interface data register CPTDATL (and CPTDATH if 16-bit data is being transferred), sets the receive data register full bit RXF in codec port interface control and status register CPTCTL to logic 1, and issues the codec port interface receive data register full interrupt. When the MCU reads the command/status data, RXF is cleared to 0. The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear bit RXF. (Note that all secondary command/status receive transactions take two codec frames to complete. First the MCU writes the address of the command/status data to be read to CPTADR and sets the R/W bit in register CPTADR to logic 1. On the next codec frame, the address is sent to the codec. On the following codec frame, the requested data is output by the codec and received at the TAS1020B codec port.) Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 43 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com • I2C interface transmit data register empty interrupt: whenever the MCU writes to the I2C interface transmit data register I2CDATO, it results in the hardware clearing the transmit data register empty bit TXE in the I2C interface control and status register I2CCTL. When the data byte is output onto the I2C bus, the hardware sets TXE back to logic 1 and the I2C interface transmit data register empty interrupt is issued. The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear the TXE bit. • I2C interface receive data register full interrupt: whenever the I2C interface receive data register I2CDATI receives a byte of data off the I2C bus, the hardware sets the receive data register full bit RXF in the I2C interface control and status register I2CCTL and issues the I2C interface receive data register full interrupt. The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear the RXF bit. The RXF bit in the I2C interface control and status register I2CCTL is cleared whenever the MCU reads the contents of the I2C interface receive data register I2CDATI. • External interrupt XINT: this interrupt is provided to give a user the ability to issue interrupts from external sources. XINT is logic 0 active. The interrupt is sampled by synchronization logic internal to the TAS1020B, as shown in Figure 2-2. As Figure 2-2 shows, XINT must be remain in an active-low state for at least one period of the 24 MHz clock to assure that the interrupt is recognized. Also, XINT must transition to an inactive state (logic 1) and then transition back to the active state (logic 0) if another XINT interrupt is to be recognized. If XINT remains in the active low state, it does not result in issuing multiple XINT interrupts. The firmware must clear this interrupt by writing to the interrupt vector register. • DMA channel 0 interrupt: this interrupt becomes active only during bulk OUT transactions utilizing DMA channel 0 when the software handshake mode is selected (see Section 2.2.7.3.3). In this mode of operation the programmable variable DMABPCT - registers DMABPCT0 and DMABPCT1 - instructs DMA channel 0 as to how many bulk OUT packets it must handle before ceasing operation and issuing the DMA channel 0 interrupt. The firmware must clear this interrupt by writing to the interrupt vector register. • DMA channel 1 interrupt: this interrupt is identical in operation to the DMA channel 0 interrupt. Note that the same count variable DMABPCT is used for both DMA interrupts. In fact, as described in Section 2.2.12, only one of the two DMA channels can be active when supporting a bulk OUT transaction. - thus the need for only one count variable DMABPCT. The interrupts for the USB IN endpoints and USB OUT endpoints can be masked. An interrupt for a particular endpoint occurs at the end of a successful transaction to that endpoint. A status bit for each IN and OUT endpoint also exists. However, these status bits are read only, and therefore, these bits are intended to be used for diagnostic purposes only. After a successful transaction to an endpoint, both the interrupt and status bit for an endpoint are asserted until the interrupt is cleared by the MCU. The USB function reset, USB function suspend, USB function resume, USB start-of-frame, USB pseudo start-of- frame, USB setup stage transaction, and USB setup stage transaction over-write interrupts can all be masked. A status bit for each of these interrupts also exists. Refer to the USB interrupt mask register and the USB status register for more details. Note that the status bits for these interrupts are read only. For these interrupts, both the interrupt and status bit are asserted until the interrupt is cleared by the MCU. The codec port interface transmit data register empty, codec port interface receive data register full, I2C interface transmit data register empty, and I2C interface receive data register full interrupts can all be masked. A status bit for each of these interrupts also exists. Note that the status bits for these interrupts are read only. However, for these interrupts, the status bits are not cleared automatically when the interrupt is cleared by the MCU. Refer to the codec port interface control and status register CPTCTL and the I2C interface control and status register I2CCTL for more details. The external interrupt input (XINT) is logically ORed with the on-chip interrupt sources. An enable bit exists for this interrupt in the global control register GLOBCTL. This interrupt does not have a status bit. 44 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.11 General-Purpose I/O (GPIO) Ports Figure 2-4 shows the architecture of the MCU port bits in the TAS1020B. There are two GPIO ports visible to external devices - port 1 and port 3. In examining the functionality of these ports two interfaces must be examined - the I/O driver interface provided at the I/O pads of the TAS1020B and the interface provided at the M8052 MCU core. At each I/O pad servicing the GPIO ports, the individual data input (DI) and data output (DO) lines into the pads are combined into one bidirectional external line. Each I/O pad is also assigned a separate enable line EN. When EN is a logic 0 the output driver is enabled, and when EN is a logic 1 the input buffer is enabled. This implementation means that as an output the GPIO pin actively sinks current in the logic 0 state, but drives the logic 1 state through the 100-μa pullup. However, to obtain an acceptable rise time when the output transitions from a logic 0 to a logic 1, the EN signal remains active for two clock periods after the output data transitions from a logic 0 to a logic 1. For two clock periods then the output buffer actively drives the logic 1 output level before yielding to the 100 μa pullup. This implementation also means that to use a GPIO pin as an input, the DO line for that pin must be set to a logic 1 and the external source driving the pin must be able of sinking the 100 μa pullup when driving a logic 0. (Some port 3 bits also require that the alternate output data source be at logic 1 to use the pin as a GPIO input). The TAS1020B global control register has two bits - P1PUDIS and P3PUDIS - that control the enabling and disabling of the 100 μa pullups for port 1 and port 3 respectively. If firmware disables the 100-μA pullups in one of the ports - by setting P1PUDIS or P3PUDIS to logic 1 - then when a port bit is configured as an output, a logic 1 output will transition to a high-impedance state after the two clock delay period has expired. At power-up, and after a global reset, all GPIO pins are configured as input ports with all 100-μA pullups enabled(1). The MCU core implements each GPIO bit using three signals - DI, DO, and EN. For both port 1 and port 3, EN is derived from DO by ANDing DO with a two clock delayed version of DO. This provides a two-clock delay in transitioning EN from a logic 0 to a logic 1 after DO transitions from a logic 0 to a logic 1. It is this circuitry that results in the output buffer in the I/O pad actively driving a logic 1 output for two clock periods before yielding to the 100-μA pullup or transitioning to a high-impedance state. (1) At power-up, GPIO pins P3.0 and P3.1 can initialize as inputs, outputs driven high, or outputs driven low. After MRESET is high and clocks start, P3.0 and P3.1 become inputs. The user's firmware application can then reprogram them as desired. This behavior occurs only at power-up. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 45 Submit Documentation Feedback Product Folder Link(s): TAS1020B Mode 0 Tx Data Send Tx Clk Rx Data Tx Clk (mode 0) UART MCUDO Q MCU Data Out Alternate ADO Data Out MCU Read MCU Bus MCU MCUDI Data In ADI Alternate Data In EN DO DI P3.0 EN DO DI ADO MCUDO MCUDI ADI P3.1 EN DO DI ADO MCUDO MCUDI ADI P3.2 EN DO DI ADO MCUDO MCUDI ADI P3.3 EN DO DI ADO MCUDO MCUDI ADI P3.4 EN DO DI ADO MCUDO MCUDI ADI P3.5 EN DO DI ADO MCUDO MCUDI ADI P3.6 EN DO DI ADO MCUDO MCUDI ADI P3.7 Timer Logic Timer 0 Event Clk Timer 1 Event Clk Timer 1 Gate Q P1.3 Q P1.4 Q P1.5 Q P1.6 Q P1.7 Q P1.2 Q P1.1 Q P1.0 EN EN EN EN EN EN EN EN DO DI DO DI DO DI DO DI DO DI DO DI DO DI DO DI I/O Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 100 ua P3.1 UART Tx Data (Mode 0) TAS1020B Interrupt Logic On−Chip Interrupts P1PUDIS 0 GLOBCTL Reg Mux TAS1020B Read Pulse Mux TAS1020B Write Pulse Not Used Not Used EXTEN I/O Drivers M8052 MCU CORE TAS1020B P3.0 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua 100 ua Q D Q D MCU Clk Delay Delay Delay Delay Delay Delay Delay Delay D Q D Q MCU Clk UART Rx Data Delay Timer 2 Event Clk Timer 2 Ext. Trigger P3.2 (output only) / XINT UART Tx Data (Mode 0) UART Tx Clk (Mode 0) P3.3 / INT1 / Timer 1 Gate P3.4 / Timer 0 Event P3.5 / Timer 1 Event WR (output only, internal MCU mode only) WRD (input only, external MCU mode only) RD (output only, internal MCU mode only) RRD (input only, external MCU mode only) Not Used Not Used INT0 Not Used INT1 Not Used Not Used WR Not Used RD Not Used MCU Read VREN RESET MCU Read MCU Read MCU Read MCU Read MCU Read MCU Read MCU Read VREN Reset P3PUDIS 7 6 5 4 3 2 1 Tx Data (Mode 0) Tx Data (Mode 0) TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-4. GPIO Port 1 and Port 3 Functionality Also, as shown in Figure 2-4, both ports can service logical units internal to the MCU core, as well as service the memory-mapped discrete input and output lines assigned to each port. 46 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.11.1 Port 3 GPIO Bits As illustrated in Figure 2-4, alternative inputs on port 3 are routed directly from the DI input at the MCU core interface to their destination within the MCU core. It is also noted that when the port bit is used as an alternative input, the value of the input can still be read by the MCU. If the port bit is to be used as a general-purpose input, the firmware must make the proper settings so that the alternative logic unit that receives the general-purpose input does not erroneously respond to the input. Each alternative output on port 3 is ANDed with the memory-mapped latch (Special Function Register - SFR) assigned to that port bit, and the result is DO. This means that if the alternate output is to be used, the latch must be set to logic 1. Similarly, if the latch is to be the source for DO, the alternate output must be logic 1. (The MCU core assures that if the logical unit supplying the alternate output is not used, its default state is logic 1). 2.2.11.1.1 UART Alternative Functions Port 3 GPIO bits P3.0 and P3.1, in addition to being able to serve as general-purpose I/O bits, can also serve to implement UART functionality. The UART implemented offers four modes of operation. In mode 0, UART output data is output on port bit P3.0 and the transmit clock (MCU clock/12) is output on port bit P3.1. In modes 1, 2, and 3 UART receive data is input on P3.0 and UART transmit data is output on P3.1. Modes 1, 2, and 3 are then full duplex modes; serial data can be transmitted and received simultaneously. In all four UART modes, transmission is initiated by any instruction that accesses the MCU-core register SBUF. If this register is not written to, the alternate output lines for P3.0 and P3.1 are at their default logic 1 state. P3.0 and P3.1 can then be used as general-purpose outputs if no instructions access register SBUF. The REN bit in the MCU serial port control register SCON enables UART reception if set to logic 1. If REN is cleared to logic 0, using P3.0 as a general-purpose input does not result in erroneous behavior in the UART logic block. P3.1 has no alternative input function, and thus it can be used as a general-purpose input if the latch assigned to that bit is set to logic 1 and no instructions access register SBUF. (P3.0 also requires that its latch be set to logic 1 and that no instructions access register SBUF if it is to be used as a general-purpose input). 2.2.11.1.2 External Interrupts XINT and INT1 The MCU core provides ports for two external interrupts (external to the MCU core) - INT0 and INT1. INT0 is an alternate input for port 3 bit P3.2 and INT1 is an alternate input for port 3 bit P3.3. As seen from both Figure 2-2 and Figure 2-4, INT0 is used to service all TAS1020B internal interrupts as well as the external interrupt XINT. INT1 only services GPIO pin P3.3, and thus can be used as a dedicated interrupt line. Because INT0 services all internal interrupts, the input DI for P3.2 must be dedicated to its alternative input function INT0. Thus P3.2 cannot be used as a general-purpose input. However, if the external interrupt XINT is not required, P3.2 can be used as a general-purpose output. Port 3 bit P3.3 can be used as a general-purpose output, a general-purpose input, or as INT1. This bit can also serve as a gate for timer 1 (see Section 2.2.11.1.3). 2.2.11.1.3 Timer Alternative Functions The MCU core has three 16-bit timer/counter registers: timer 0, timer 1, and timer 2. In the timer mode, the timer/counter register is incremented every MCU machine cycle (MCU clock/12). In the counter mode, the timer/counter register is incremented in response to a falling edge (logic 1 to logic 0 transition) at its assigned port bit input - P3.4 for timer 0, P3.5 for timer 1, and P1.0 for timer 2. To qualify as an event clock in the counter mode, the external source must hold each logic state - logic 1 and logic 0 - for a period of time greater than 12 MCU clock periods. This means that the maximum count rate in the counter mode is MCU clock/24. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 47 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Timer 1 can be gated on and off under external control to facilitate pulse width measurements. The external control is brought in on port 3 bit P3.3, which is the same input that sources the alternate input function INT1. Thus P3.3 can be thought of as having two alternate input functions. The MCU core also provides gating for timer 0 via P3.2. However, the input DI for P3.2 must be dedicated to INT0 so that the internal TAS1020B interrupts can be serviced. As a result, gated timing is not allowed on timer 0. In addition to the external event clock on port 1 bit P1.0, timer 2 has an external trigger input on port 1 bit P1.1 which can be used to either capture the value in the counter when in the counter mode or reload the timer when in the timer mode. If the C/NT bit in the appropriate MCU special function register (SFR) for a given timer is cleared to enable a timer function, or if the timer/counter interrupt is masked off by clearing the appropriate ET bit in the MCU interrupt enable register IE, the corresponding port bit input providing the external event clock can be used as a general-purpose input. For the external trigger input for timer 2, it is necessary to clear bit EXEN2 in the MCU timer/counter 2 control register T2CON if this input is to be used as a general-purpose input. 2.2.11.1.4 MCU Read/Write Pulse Alternate Function The TAS1020B provides the capability of replacing the internal MCU core with an in-circuit emulator (ICE) for firmware development. When in the external MCU mode of operation (EXTEN = 1), port 3 bits P3.7 and P3.6 respectively are used to input the ICE-generated memory read and write pulses so that the ICE can access the memory-mapped resources internal to the TAS1020B (but not those resources internal to the MCU core itself). When in the internal MCU mode, P3.6 and P3.7 output the external memory write and read pulses respectively from the MCU core, and can be used as troubleshooting aids. P3.6 and P3.7 cannot be used as GPIO resources. 2.2.11.2 Port 1 GPIO Bits Port 1 has two bits that have alternate input functionality - P1.0 and P1.1. The alternate function serviced by these inputs is timer 2. P1.0 provides the external event clock for timer 2 and P1.1 provides the external trigger. These alternate functions and the conditions under which these two bits can be used as GPIO bits are discussed in Section 2.2.11.1.3. Port 1 provides no alternate output functionality. 2.2.11.3 Pullup Macro Figure 2-5 shows the equivalent circuit of the pullup "resistor" of the TAS1020B. For use with 3.3-V I/Os only. Figure 2-5. Pull-Up Logic Symbol Table 2-4. Electrical Characteristics of Pullup Resistors(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO Output current VO = 0 V –35.98 –90.67 –197.38 μA FI Input loading factor TAP 1.65 pF FI Input loading factor PWRDN 2.50 SL Cpd Equivalent power dissipation capacitance 0.04 pF (1) When PWRDN = H, the current source is turned off. 48 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.12 DMA Controller The TAS1020B provides two DMA channels for transferring data between the USB endpoint buffers and the codec port interface. The DMA channels are provided to support the streaming of data for USB isochronous or bulk OUT endpoints only. Each DMA channel can be programmed to service one isochronous endpoint. The endpoint number and direction are programmable using the DMA channel control register provided for each DMA channel. For the two AC '97 modes supported by the TAS1020B, one DMA channel can be assigned to support bulk OUT transactions and the second DMA channel assigned to support isochronous IN transactions. An example would be downloading an AC3 file for storage via a bulk OUT transaction while, at the same time, supporting an isochronous recording session. For all formats and protocols other than AC '97, however, if a DMA channel is assigned to support bulk OUT transactions, it can be the only DMA channel active. If, for example, DMA channel 0 is assigned to support bulk OUT transactions in the General Purpose mode, then DMA channel 1 cannot be assigned to support bulk OUT or isochronous transactions. Section 2.2.7.3.3 provides more detail on DMA-supported bulk OUT transactions. The codec port interface time slots to be serviced by a particular DMA channel must also be programmed. For example, an AC '97 mode stereo speaker application uses time slots 3 and 4 for audio playback. Therefore, the DMA channel used to move the audio data to the codec port interface must set time slot assignment bits 3 and 4 to a 1. Each DMA channel is capable of being programmed to transfer data for time slots 0 through 13 using the two DMA channel time slot assignment registers provided for each DMA channel. The number of bytes to be transferred for each time slot is also programmable. The number of bytes used must be set based on the desired audio data format. 2.2.13 Codec Port Interface The codec port interface is a configurable serial interface used to transfer data between the TAS1020B IC and a codec device. The serial protocol and formats supported include AC '97 1.0, AC '97 2.0, and several I2S modes. In addition, a general-purpose mode is provided that can be configured to various user defined serial interface formats. Configuration of the interface is accomplished using the four codec port interface configuration registers: CPTCNF1, CPTCNF2, CPTCNF3, and CPTCNF4. In I2S mode 5, CPTRXCNF2, CPTRXCNF3, and CPTRXCNF4 are used to configure the C-port in the receive direction. See Section 6.5.4 for more details on these registers. The serial interface is a time division multiplexed (TDM) time slot based scheme. The basic format of the serial interface is determined by setting the number of time slots per codec frame and the number of serial clock cycles (or bits) per time slot. The interface in all modes is bidirectional and full duplex. For all modes except the I2S modes, command/status data as well as audio data can be transferred via the serial interface. Transfer of the audio data packets between the USB endpoint data buffers and the codec port interface is controlled by the DMA channels. The source and/or the destination of the command/status address and data values is controlled by the MCU. The features of the codec port interface that can be configured are: • The mode of operation • The number of time slots per codec frame • The number of serial clock cycles for slot 0 • The number of serial clock cycles for all slots other than slot 0 • The number of data bits per audio data time slot • The time slots to be used for command/status address and data • The serial clock (CSCLK) frequency in relation to the codec master clock (MCLK) frequency • The source of the serial clock signal (internally generated or an input from the codec device) Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 49 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com • The source of the codec master clock signal used to generate the internal serial clock signal (internally generated by the ACG or an input to the TAS1020B device) • The polarity, duration, and direction of the codec frame sync signal • The relationship between the codec frame sync signal and the serial clock signal • The relationship between the codec frame sync signal and the serial data signals • The relationship between the serial clock signal and the serial data signals • The use of zero padding or a high-impedance state for unused time slots and/or bits • The byte ordering to be used 2.2.13.1 General-Purpose Mode of Operation In the general-purpose mode the codec port interface can be configured to various user-defined serial interface formats using the pin assignments shown in Table 2-5. This mode gives the user flexibility to configure the TAS1020B to connect to various codecs and DSPs that do not use a standard serial interface format. Table 2-5. Terminal Assignments for Codec Port Interface General-Purpose Mode TERMINAL GENERAL-PURPOSE MODE 0 NO. NAME 35 CSYNC CSYNC I/O 37 CSCLK CSCLK I/O 38 CDATO CDATA0 O 36 CDATI CDATA1 I 34 CRESET CRESET O 32 CSCHNE NC O Serial bus protocols AC '97, AIC, and I2S are specific settings of the programmable parameters offered in the general-purpose mode. The general-purpose mode then can be thought of as the primary mode of the codec interface port, with all other modes being special cases of the general-purpose mode. Figure 2-6, Figure 2-7, and Figure 2-8 show three general-purpose mode codec configuration examples. Figure 2-6 gives the settings required to implement AC '97 1.0, Figure 2-7 gives the settings required to implement AIC, and Figure 2-8 gives the settings required to implement I2S. In all three cases the parameters that define these modes are included in the figures. It should be noted the MODE bits in codec port interface configuration register 1 (CPTCNF1) can be used to specifically select either AC '97 1.0, AIC, or I2S. However, when using the specific mode selections, the firmware still must set all parameters in the codec port interface configuration registers. The MODE bits are used simply to implement mode-specific behavior not covered by the programmable parameters. An example of this would be setting, when in one of the two AC '97 modes, those time slot tag bits in the time slot 0 tag word that correspond to the time slots that have valid data. 50 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.1.1 Parameter Assignments - AC '97 1.0 In Figure 2-6, the codec port interface is configured for 13 time slots. The word size for time slot 0 is 16 bits, whereas the word size for all other time slots is 20 bits. Time slots 1 and 2 are used for secondary communication, and, in the example of figure 2-5, time slots 3, 4, 6, 7, 8, and 9 have valid audio data. The sync line CSYNC is programmed to be logic 1 active for the duration of time slot 0. CSYNC and CDATO are programmed to transition on the rising edge of CSCLK, which means that CDATI will be sampled on the falling edge of CSCLK. For the example of Figure 2-6, each audio data word is only 16 bits in length, and the 4 LSBs of the 20-bit data word slot are set to logic 0. Byte order reversal (BYOR) is not set, so the byte ordering of the data as received is preserved - both from the USB bus (OUT transactions) and from the external codec (IN transactions). To conform with AC '97 timing requirements, it is necessary that both transmit and receive data be delayed by one CSCLK clock period with respect to the rising edge of CSYNC. This is accomplished by setting DDLY to logic 1. Lastly, DIVB is programmed to set CSCLK to MSCLK/2. This allows MSCLK to be set at 24.576 MHz and source the oscillator input XTRL_IN on AC '97 compliant codecs. Figure 2-6 also points out that time slot assignments in AC '97 modes need not be the same for input data frames and output data frames. For output data frames (CDATO), the settings in bit fields VTSL(3:7) and VTSL(8:12) define which time slots have valid data. For input data frames (CDATI) the valid time slots are determined from the settings of the time slot valid tag bits in the 16-bit tag word received in time slot 0. The hardware uses these bit settings to extract the valid data from the input data frame and output it, via a DMA channel, to an endpoint buffer resource. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 51 Submit Documentation Feedback Product Folder Link(s): TAS1020B 0 Tag Rdy CSYNC CSCLK CDATO 0 DDLY = 1 CSCLK CDATO D15 0 CSCLKP = 0 CSYNCP = 1 CSYNCL = 1 Time Slot 0 Length = TSL0L = 10b (16 CSCLK Periods) Time Slot Length = TSLL = 011b (20 CSCLK Periods) Data Bits Per Time Slot = BPTSL = 001b (16) Number Of Time Slots = NTSL = 01100b (13) Mode = MODE = 010b (AC’97 1.0 Mode) BYOR = 0 Cmd Time Slot = ATSL = 0001b VTSL(3:7) = 11011b VTSL(8:12) = 11000b CSYNC CDATI CDATO Tag TRSEN = 0 MCLKO (XTL_IN) CSCLK DIVB = 001b Status Addr Cmd Addr 1 Status Data Cmd Data 2 PCM Left PCM Left 3 PCM Rt PCM Rt 4 0 . . . 0 5 PCM Mike PCM Cen 6 PCM L Surr 7 PCM R Surr 8 LFE 9 0 . . . 0 10 0 . . . 0 11 0 . . . 0 12 TS1 1 TS2 2 TS12 12 0 13 ID1 14 ID0 15 D14 1 D13 2 D0 15 0 16 0 17 0 18 0 19 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-6. Codec Port Interface Parameters − AC '97 1.0 52 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.1.2 Parameter Assignments - AIC Figure 2-7 shows the parametric settings for the AIC mode. In Figure 2-7, the codec port interface is configured for 16 time slots. The word size for all time slots, including time slot 0, is 16 bits. Time slot 0 is the only active audio time slot and time slot 8 is assigned to handle secondary communications. The sync line CSYNC is programmed to be logic 1 active for one CSCLK period. DDLY is set to logic 1, and thus transmit data (CDATO) and receive data (CDATI) are both delayed by one CSCLK period with respect to the rising edge of CSYNC. CSYNC and CDATO are programmed to transition on the rising edge of CSCLK, and consequently CDATI is sampled on the falling edge of CSCLK. Byte order reversal (BYOR) is not set, so the byte ordering of the data as received is preserved - both from the USB bus (OUT transactions) and from the external codec (IN transactions). The 3-state enable (TRSEN) is set, and thus CDATO goes to a high-impedance state during the outputting of non-valid time slots. Lastly, CSCLK is set to MSCLK/8. (This parameter selection is not part of the AIC standard.) AIC requires both input (CDATI) and output (CDATO) audio data reside in time slot 0 and secondary communication information reside in time slot 8. Thus, unlike AC '97, AIC does not require the use of the valid time slot tag bits VTSL as there is no tag word needed to identify which time slots are valid. A unique feature of AIC is the generation of a second CSYNC frame sync pulse within a given frame if a secondary transaction is taking place. If the MCU has not output data requesting a secondary transaction, the second frame sync pulse shown in Figure 2-7 is not generated. Thus without secondary communication there are 256 CSCLK periods between frame sync pulses, and with secondary communication there are 128 CSCLK periods between frame sync pulses. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 53 Submit Documentation Feedback Product Folder Link(s): TAS1020B D15 Data Bits / Time Slot = BPTSL = 001b (16) Time Slot 0 Length = TSL0L = 10b (16) CSYNCL = 0, CSYNCP = 1 CSCLKP = 0 DDLY = 1 BYOR = 0 Time Slot 0 Time Slot 1 Time Slot 7 Time Slot 8 Time Slot 9 Time Slot 14 Time Slot 15 FC CSYNC DAC Data Register W. Data CDATO /Register R. Addr ADC Data Register Read CDATI Data CSCLK CSYNC CDATO or CDATI MCLKO CSCLK DIVB = 111b 1 NOTE: DA = Device Address FC Number of Time Slots = NTSL = 01111b (16) TRSEN = 1 Cmd Time Slot = ATSL = 1000b (8) Mode = MODE = 001b (AIC Mode) D14 D13 D12 D2 D1 D0 DA2 Data Bits / Time Slot = BPTSL = 001b (16) Time Slot Length = TSLL = 001b (16) CSYNCL = 0, CSYNCP = 1 CSCLKP = 0 DDLY = 1 CSCLK CSYNC CDATO or CDATI FC DA1 DA0 RW D2 D1 D0 2 3 4 5 6 7 8 TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-7. Codec Port Interface Parameters − AIC 54 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.1.3 Parameter Assignments - I2S Figure 2-8 shows the parameter settings for I2S. I2S only uses two time slots. Time slot 0 is used for left channel audio data and time slot 1 is used for right channel audio data. Secondary communication is not allowed in I2S. The sync line CSYNC is programmed to be logic 0 active for the duration of time slot 0. CSYNC and CDATO are programmed to transition on the falling edge of CSCLK, which means that CDATI will be sampled on the rising edge of CSCLK. DDLY is set to logic 1, and thus transmit data (CDATO) and receive data (CDATI) are both delayed one CSCLK period with respect to the falling edge of CSYNC. The time slot length for both time slots is programmed to be 32 bits. I2S does allow the use of different word size lengths, and a word size length of 24 bits is selected for the example in Figure 2-8. Byte order reversal (BYOR) is not set, so the byte ordering of the data as received is preserved. CSCLK is set to MSCLK/4, which is a common ratio for I2S. For example, if 48 kHz audio sampling is used, CSCLK would be 64 × 48 kHz = 3.072 MHz. MCLK then would be 4 × 3.072 MHz 12.288 MHz, which is a standard master clock frequency used by I2S codecs for 48-kHz audio data. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 55 Submit Documentation Feedback Product Folder Link(s): TAS1020B 0 Time Slot 0 Time Slot 1 Time Slot 0 CSYNC CSCLK CDATO or CADTI DDLY = 1 CSYNCL = 1, CSYNCP = 0 CSCLKP = 1 BYOR = 0 TSL0L = 11b (32 CSCLK Periods) TSLL = 101b (32 CSCLK Periods) BPTSL = 100b (24) NTSL = 00001b (2) MCLKO CSCLK DIVB = 011b 0 L23 L22 L21 L20 L1 L0 0 0 0 0 0 0 R23 R22 R21 R20 0R1 R0 0 0 0 0 0 0 L23 L22 Mode = MODE = 100b or 101b (I2S) TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-8. Codec Port Interface Parameters – I2S 56 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.1.4 Byte Reversal Ordering For all data transactions managed under DMA control, the TAS1020B provides an option to reverse the ordering of the bytes within a data word as received. Byte order reversal, if selected, applies to both DMA channels. If, for example, one DMA channel is used to output audio to a codec and the second DMA channel is used to retrieve record data from a codec, byte reversal is applied to both audio streams. When re-ordering the bytes within an audio data word, both time slot length (TSLL/TSL0L) and data bits per time slot (BPTSL) must be taken into account. As an example consider Figure 2-9. In Figure 2-9 (a) 20-bit data in a 3-byte word is received either over the USB bus (OUT transaction) or from a codec (IN transaction). The byte order of the data as received is little endian, where the least significant byte is placed in the right-most byte position of the word. If BYOR = 1, byte reversal will be performed to yield an output that is big endian in byte order, where the least significant byte is placed in the left-most byte position of the word. However, in examining the byte-order reversed data in Figure 2-9 (b), it is noted that the two nibbles of the most significant byte are switched to prevent a gap in the serial data when output. The TAS1020B automatically performs this nibble reversal based on BPTSL being one nibble less than the time slot in length. a. Audio Word Received by TAS1020B 24 0 0 0 0 0 B19 B16 B15 B9 B8 B7 B1 B0 b. Received Audio Word After Byte Reversal 24 0 B7 B1 B0 B15 B9 B8 B19 B16 0 0 0 0 Figure 2-9. Byte Reversal Example 2.2.13.2 Audio Codec (AC) '97 1.0 Mode of Operation In AC '97 1.0 mode, the codec port interface can be configured as an AC link serial interface to the AC '97 codec device. Refer to the audio codec '97 specification revision 2.2 for additional information. The AC link serial interface is a time division multiplexed (TDM) slot based serial interface that is used to transfer both audio data and command/status data between the TAS1020B IC and the codec device. NO TAG shows the structure of the codec port interface signals for AC '97 1.0. Table 2-6. Terminal Assignments for Codec Port Interface AC '97 1.0 Mode 2 TERMINAL AC '97 VERSION 1.0 MODE 2 NO. NAME 35 CSYNC SYNC O 37 CSCLK BIT_CLK I 38 CDATO SDATA_OUT O 36 CDATI SDATA_IN I 34 CRESET RESET O 32 CSCHNE NC O In this mode, the codec port interface is configured as a bidirectional full duplex serial interface with a fixed rate of 48 kHz. Each 48-kHz frame is divided into 13 time slots, with the use of each time slot predefined by the audio codec AC '97 specification. Each time slot is 20 serial clock cycles in length except for time slot 0, which is only 16 serial clock cycles. The serial clock, which is referred to as the BIT_CLK for AC '97 modes, is set to 12.288 MHz. Based on the length of each slot, there is a total of 256 serial clock cycles per frame at a frequency of 12.288 MHz. As a result the frame frequency is 48 kHz. For the AC '97 modes, the BIT_CLK is input to the TAS1020B device from the codec. The BIT_CLK is Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 57 Submit Documentation Feedback Product Folder Link(s): TAS1020B MCLKO1 CSYNC CSCLK CDATO CDATI CRESET CSCHNE AC97CLK SYNC BIT_CLK SD_IN SD_OUT CRESET TAS1020B AC’97 IC TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com generated by the codec from the master clock (MCLK) input. The codec MCLK input, which can be generated by the TAS1020B device, must be a frequency of 24.576 MHz. The start of each 48-kHz frame is synchronized to the rising edge of the SYNC signal, which is an output of the TAS1020B device. The SYNC signal is driven high each frame for the duration of slot 0. See Figure 2-10 for details on connecting the TAS1020B to a codec device in this mode. Figure 2-10. Connection of the TAS1020B to an AC '97 Codec The AC link protocol defines slot 0 as a special slot called the tag slot and defines slots 1 through 12 as data slots. Slot 1 and slot 2 are used to transfer command and status information between the TAS1020B device and the codec. Slot 1 and slot 2 of the outgoing serial data stream are defined as the command address and command data slots, respectively. These slots are used for writing to the control registers in the codec. Slot 1 and slot 2 of the incoming serial data stream are defined as the status address and status data slots, respectively. These slots are used for reading from the control registers in the codec. Unused or reserved time slots and unused bit locations within a valid time slot are filled with zeros. Since each data time slot is 20 bits in length, the protocol supports 8-bit, 16-bit, 18-bit, or 20-bit data transfers. 2.2.13.3 Audio Codec (AC) '97 2.0 Mode of Operation The basic serial protocol for the AC '97 2.0 mode is the same as the AC '97 1.0 mode. The AC '97 2.0 mode, however, offers some additional features. In this mode, the TAS1020B provides support for multiple codec devices and also on-demand sampling. Table 2-7. Terminal Assignments for Codec Port Interface AC '97 2.0 Mode 3 TERMINAL AC '97 VERSION 2.0 MODE 3 NO. NAME 35 CSYNC SYNC O 37 CSCLK BIT_CLK I 38 CDATO SDATA_OUT O 36 CDATI SDATA_IN I 34 CRESET RESET O 32 CSCHNE SD_IN2 I The TAS1020B can connect directly to two AC '97 codecs. The interconnect for two codecs is shown in Figure 2-11. As noted in Figure 2-11, the support for two codecs only requires the use of one additional pin—CSCHNE (codec port interface secondary channel enable)—and this additional pin allows record transactions to consist of data from two codecs. The two serial data lines from the two codecs to the TAS1020B are ORed together inside the TAS1020B to form one final serial digital data stream. This means that the data output from each codec must reside in different time slots. This also explains why CSCHNE must be grounded when not used, as a floating input could result in unpredictable behavior and corrupt the serial data coming in on the other input pin, SDATA_IN1. AC '97 mode 2.0 also supports on-demand sampling. On-demand sampling is a codec-to-controller 58 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B Secondary MCLKO CSCHNE CRESET CDATI CDATO CSCLK CSYNC AC97CLK CRESET SDATA_OUT SDATA_IN BIT_CLK SYNC AC97CLK CRESET SDATA_OUT SDATA_IN BIT_CLK SYNC AC ’97 IC TAS1020B AC97 or MC97 Primary Serial Input Data TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 signaling protocol that is used to accommodate audio sampling rates that differ from the 48-kHz AC-link serial frame rate. An example would be streaming 44.1 kHz audio across the AC-link. The signaling protocol is implemented using the data request flags SLOTREQ[0-9] residing in SLOT1[2-11] of slot 1 of the AC '97 input frame. An active request (bit request flag = 0) results in data being sent to the codec on the next AC-link frame. The TAS1020B does not support on-demand sampling when used with two codecs. Only one codec using on-demand sampling can be supported by the TAS1020B. Figure 2-11. Connection of the TAS1020B to Multiple AC '97 Codecs 2.2.13.4 Inter-IC Sound (I2S) Modes of Operation The TAS1020B offers two I2S modes of operation, codec port interface mode 4 and codec port interface mode 5. The difference in the I2S modes is the number of serial data outputs and/or serial data inputs supported. For codec port interface mode 4, there is one serial data output (SDOUT1) and two serial data inputs (SDIN1, SDIN2). Hence, mode 4 can be used to connect the TAS1020B device to a codec with one stereo DAC and two ADCs. For codec port interface mode 5, one serial data output (SDOUT1) and one serial data input (SDIN2) are supported, but these data streams can be completely independent as each is assigned its separate sync pulse and bit clock. Mode 5 then can service applications that require different sampling rates for record and playback. Table 2-8 shows the TAS1020B codec terminal assignments and the respective signal names for each of the I2S modes. Figure 2-8 shows the signal waveforms for I2S. Table 2-8. Terminal Assignments for Codec Port Interface I2S Mode 4 and Mode 5 TERMINAL I2S I2S NO. NAME MODE 4 MODE 5 35 CSYNC LRCK O LRCK1 O 37 CSCLK SCLK O SCLK1 O 38 CDATO SDOUT1 O SDOUT1 O 36 CDATI SDIN1 I SDIN2 I 34 CRESET CRESET O SCLK2 O 32 CSCHNE SDIN2 I LRCK2 O Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 59 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com In all I2S modes, the codec port interface is configured as a bidirectional full duplex serial interface with two time slots per frame. The frame sync signal is the left/right clock (LRCK) signal. Time slot 0 is used for the left channel audio data, and time slot 1 is used for the right channel audio data. Both time slots must be set to 32 serial clock (SCLK) cycles in length giving an SCLK-to-LRCK ratio of 64. The serial clock frequency is based on the audio sample rate. For example, when using an audio sample rate (FS) of 48 kHz, the SCLK frequency must be set to 3.072 MHz (64×FS). (Note that the terms codec frame sync, audio sample rate (FS), and LRCK all refer to the same signal.) The LRCK signal has a 50% duty cycle. The LRCK signal is low for the left channel time slot and is high for the right channel time slot. In addition, the LRCK signal is synchronous to the falling edge of the SCLK. Serial data is shifted out on the falling edge of SCLK and shifted in on the rising edge of SCLK. Both for the left channel and the right channel, there is a one-SCLK cycle delay from the edge of LRCK before the most significant bit of the data is shifted out. For the I2S modes of the codec port interface, there is a 24-bit transmit and 24-bit receive shift register for each SDOUT and SDIN signal, respectively. As a result, the interface can actually support 16-bit, 18-bit, 20-bit or 24-bit transfers. The interface pads the unused bits automatically with zeros. The I2S protocol does not provide for command/status data transfers. Therefore, when using the TAS1020B device with a codec that uses an I2S serial interface for audio data transfers, the TAS1020B I2C serial interface can be used for codec command/status data transfers. 2.2.13.4.1 Mapping DMA Time Slots to Codec Port Interface Time Slots for I2S Modes The I2S serial data format uses two time slots (left channel—slot 0, and right channel—slot 1) for each serial data output or input. Because two serial data streams are input into the TAS1020B in I2S mode 4 operation, and since each input stream has its own unique slot 0 and slot 1 assignments associated with its data, the TAS1020B must contend with two slots arriving during time slot 0 and two slots arriving during time slot 1. Mapping is then required to transpose these multiple time slot occurrences to single, unique slot assignments for the DMA channel. Table 2-9 shows the mapping of the codec port interface time slots for each input to their corresponding DMA time slot assignments. As an example, suppose that codec port interface mode 4 is to be used with one serial data output and two serial data inputs. The DMA channel assigned to support the serial data output must have time slot assignment bits 0 and 1 set to 1. The DMA channel assigned to support the two serial data inputs must have time slot assignment bits 0, 1, 2, and 3 set to 1. Table 2-9. SLOT Assignments for Codec Port Interface I2S Mode 4 CODEC PORT INTERFACE DMA CHANNEL(S) SERIAL DATA TIME SLOT NUMBER TIME SLOT NUMBER LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL SDOUT1 0 1 0 1 SDIN1 0 1 0 2 SDIN2 0 1 1 3 Table 2-10. SLOT Assignments for Codec Port Interface I2S Mode 5 CODEC PORT INTERFACE DMA CHANNEL(S) SERIAL DATA TIME SLOT NUMBER TIME SLOT NUMBER LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL SDOUT1 0 1 0 1 SDIN2 0 1 0 1 60 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.13.5 AIC Mode of Operation AIC - audio interface circuit - is a standard adopted by Texas Instruments for interfacing digitized analog data to a TI DSP. The bus is specifically tailored to be compatible with the serial ports supplied with most TI DSP offerings. In later DSP offerings, these ports are referred to as McBSP ports. The AIC standard has four serial interface modes - pulse mode, SPI mode 0, SPI mode 1, and frame mode. The TAS1020B only supports the pulse mode of operation. (The pulse mode is so named because of the one CSCLK period duration of the sync signal). Three options exist for the pulse mode - master (frame sync is sourced by the codec), slave (frame sync is sourced by the TAS1020B), and continuous-transfer master (data is transmitted and received continuously, and frame sync is sourced by the codec). The TAS1020B directly supports the master and slave options. The continuous-transfer master mode option does not allow secondary communication. The AIC standard covers this case by specifying the use of a second data stream, synchronous with CSCLK, to directly program the internal registers of the codec. The TAS1020B has no means of outputting such a second data stream. The TAS1020B then can only support the continuous-transfer master mode option by the use of external logic, whereby the CDATO line can be multiplexed between the AIC data terminal and the direct configuration serial input terminal. Such a solution for implementing the continuous-transfer master mode option does introduce the restriction that audio data and control data cannot be transmitted concurrently. The AIC standard provides two options for requesting secondary communication - asserting an active-high logic level on a separate line (FC) or setting the LSB of the 16-bit data word high. The latter option is only available when the audio consists of 15-bit data words. The TAS1020B only supports the FC option. When the codec port interface is set to the AIC mode, the TAS1020B CSCHNE pin (pin 32) sources FC. Figure 2-7 shows the parameter settings for the AIC master or slave mode, and Section 2.2.13.1.2 provides detail on these settings. Table 2-11 shows the TAS1020B codec terminal assignments and the respective signal names for the AIC mode of operation. Table 2-11. Terminal Assignments for Codec Port Interface AIC Mode 1 TERMINAL AIC NO. NAME 35 CSYNC FS O 37 CSCLK SCLK O 38 CDATO DOUT O 36 CDATI DIN I 34 CRESET RESET O 32 CSCHNE FC O 2.2.13.6 Bulk Mode The TAS1020B supports bulk OUT data transactions through the codec port using one of the two available DMA channels, but the codec port needs to be configured in AC '97 or general-purpose mode to support bulk OUT transactions. AC '97 and the general-purpose mode are the only two modes of operation that support bulk OUT transactions, as these are the only two modes that have mechanisms in place to distinguish when valid data is or is not being output. AC '97 uses tag bits to indicate whether or not data is valid in any given time slot. In the general-purpose mode, no sync pulse is output if no valid data is available to be output. (In both AC '97 and the general-purpose mode, CPTBLK must be set to logic 1 if tag bits or the sync pulse, respectively, are to indicate the presence of valid data). See Section 2.2.7.3.3 for more detail on bulk OUT transactions using one of the two DMA channels. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 61 Submit Documentation Feedback Product Folder Link(s): TAS1020B Data Line Stable: Data Valid Change of Data Allowed SDA SCL TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 2.2.14 I2C Interface The TAS1020B has a bidirectional two-wire serial interface that can be used to access other ICs. This serial interface is compatible with the I2C (Inter IC) bus protocol and supports both 100-kbps and 400-kbps data transfer rates. The TAS1020B does not support all provisions of theI2C specification. The TAS1020B can only serve as a master device on the I2C bus, but as a master device, the TAS1020B does not support a multimaster bus environment (no bus arbitration), but can recognize wait state insertions on the bus. The I2C interface on the TAS1020B is provided to allow access to I2C slave devices, including EEPROMs and codecs. For example, if the application program code is stored in an EEPROM on the PCB, then the MCU downloads the code from the EEPROM to the TAS1020B on-chip RAM using the I2C interface. Another example is the control of a codec device that uses an I2S interface for audio data transfers and an I2C interface for control register read/write access. 2.2.14.1 Data Transfers The two-wire serial interface uses the serial clock signal, SCL, and the serial data signal, SDA. As stated above, the TAS1020B is a master only device, and therefore, the SCL signal is an output only. The SDA signal is a bidirectional signal that uses an open-drain output to allow the TAS1020B to be wire-ORed with other devices that use open-drain or open-collector outputs. All read and write data transfers on the serial bus are initiated by the TAS1020B. The TAS1020B is also responsible for generating the clock signal used for all data transfers. The data is transferred on the bus serially one bit at a time. However, the protocol requires that the address and data be transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The timing relationship between the SCL and SDA signals for each bit transferred on the bus is shown in Figure 2-12. As shown, the SDA signal must be stable while the SCL signal is high, which also means that the SDA signal can only change states while the SCL signal is low. Figure 2-12. Bit Transfer on the I2C Bus The timing relationship between the SCL and SDA signals for the start and stop conditions is shown in Figure 2-13. As shown, the start condition is defined as a high-to-low transition of the SDA signal while the SCL signal is high. Also as shown, the stop condition is defined as a low-to-high transition of the SDA signal while the SCL signal is high. 62 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B SDA SCL S Start Condition P Stop Condition S Start Condition MSB Acknowledge Not Acknowledge 9 Clock Pulse For Acknowledge 1 2 8 Data Output By Slave Device Data Output By TAS1020B SDA SDA } } SCL TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Figure 2-13. I2C START and STOP Conditions When the TAS1020B is the device receiving data information, the TAS1020B acknowledges each byte received by driving the SDA signal low during the acknowledge SCL period. During the acknowledge SCL period, the slave device must stop driving the SDA signal. If the TAS1020B is unable to receive a byte, the SDA signal is not driven low and is pulled high external to the TAS1020B device. Also, if the TAS1020B has received the last byte of data, it signals an end of transmission to the slave device by issuing a not acknowledge, rather than an acknowledge, following reception of the last byte. A high during the SCL period indicates a not-acknowledge to the slave device. The acknowledge timing is shown in Figure 2-14. Read and write data transfers by the TAS1020B device can be done using single byte or multiple byte data transfers. Therefore, the actual transfer type used depends on the protocol required by the I2C slave device being accessed. Figure 2-14. TAS1020B Acknowledge on the I2C Bus 2.2.14.2 Single Byte Write As shown is Figure 2-15, a single byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be a 0. After receiving the correct I2C device address and the read/write bit, the I2C slave device responds with an acknowledge bit. Next, the TAS1020B transmits the address byte or bytes corresponding to the I2C slave device internal memory address being accessed. After receiving the address byte, the I2C slave device again responds with an acknowledge bit. Next, the TAS1020B device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the I2C slave device again responds with an acknowledge bit. Finally, the TAS1020B device transmits a stop condition to complete the single byte data write transfer. Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 63 Submit Documentation Feedback Product Folder Link(s): TAS1020B A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I2C Device Address and Read/Write Bit Memory or Register Address Data Byte SDA D7 D6 D1 D0 ACK Stop Condition Acknowledge I2C Device Address and Read/Write Bit Memory or Register Address Last Data Byte A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 D6 D1 D0 ACK Start Condition Acknowledge Acknowledge Acknowledge SDA First Data Byte A6 A4 A3 Other Data Bytes A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I2C Device Address and Read/Write Bit Memory or Register Address Data Byte SDA D7 D6 D1 D0 ACK I2C Device Address and Read/Write Bit Repeat Start Condition Not Acknowledge A1 A1 R/W TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 2-15. Single Byte Write Transfer 2.2.14.3 Multiple Byte Write A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the TAS1020B device to the I2C slave device as shown in Figure 2-16. After receiving each data byte, the I2C slave device responds with an acknowledge bit. Figure 2-16. Multiple Byte Write Transfer 2.2.14.4 Single Byte Read As shown in Figure 2-17, a single byte data read transfer begins with the TAS1020B device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually performed. Initially, a write is performed to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit must be a 0. After receiving the I2C device address and the read/write bit, the I2C slave device responds with an acknowledge bit. Also, after sending the internal memory address byte or bytes, the TAS1020B device transmits another start condition followed by the I2C slave device address and the read/write bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the I2C device address and the read/write bit the I2C slave again responds with an acknowledge bit. Next, the I2C slave device transmits the data byte from the memory address being read. After receiving the data byte, the TAS1020B device transmits a not-acknowledge followed by a stop condition to complete the single byte data read transfer. Figure 2-17. Single Byte Read Transfer 64 Detailed Description Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B A6 A0 ACK Acknowledge I2C Device Address and Read/Write Bit A6 A0 R/W ACK A4 A0 ACK R/W D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge Last Data Byte SDA D7 D6 D1 D0 ACK First Data Byte Repeat Start Condition Not Acknowledge I2C Device Address and Read/Write Bit Memory or Register Address Other Data Bytes A7 A6 A7 TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 2.2.14.5 Multiple Byte Read A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the I2C slave device to the TAS1020B device as shown in Figure 2-18. Except for the last data byte, the TAS1020B device responds with an acknowledge bit after receiving each data byte. Figure 2-18. Multiple Byte Read Transfer Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 65 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 3 Electrical Specifications 3.1 Absolute Maximum Ratings(1) over operating temperature range (unless otherwise noted) DVDD Supply voltage range −0.5 to 3.6 V VI Input voltage range 3.3-V TTL/LVCMOS −0.5 V to DVDD + 0.5 V Continuous power dissipation See Section 3.2 TOp Operating free air temperature range 0°C to 70°C TStg Storage temperature range (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3.2 Dissipation Ratings PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C POWER RATING ABOVE TA = 25°C POWER RATING TQFP 0.923 W 10.256 mW/°C 0.461 W 3.3 Recommended Operating Conditions MIN NOM MAX UNIT DVDD Digital supply voltage 3 3.3 3.6 V AVDD Analog supply voltage 3 3.3 3.6 V VIH High-level input voltage CMOS inputs 0.7 DVDD V VIL Low-level input voltage CMOS inputs 0 0.2 DVDD V VI Input voltage CMOS inputs 0 DVDD V VO Output voltage CMOS inputs 0 DVDD V 3.4 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage, GPIO port bits P3 [0-7] IOH = - 4 mA DVDD-0.5 V VOL Low-level output voltage, GPIO port bits P3 [0-7] IOL = 4 mA 0.5 V VOH High-level output voltage, GPIO port bits P1 [0-7] IOH = - 8 mA DVDD-0.5 V VOL Low-level output voltage, GPIO port bits P1 [0-7] IOL = 8 mA 0.5 V IOZ High-impedance output current ± 20 μA Pullup disabled VI = VIL - 20 IIL Low-level input current μA Enabled -100 Pullup disabled VI = VIH 20 IIH High-level input current μA Enabled 20 CPU clock 12 MHz 45.9 mA Digital supply voltage DVDD (3.3 V) CPU clock 24 MHz 50.9 IDD Suspend(1) 196 μA Normal 14.7 mA Analog supply voltage AVDD (3.3 V) Suspend 24 nA (1) In this 196 μA measurement, the bulk of suspend current (190 μA) is delivered to the USB cable through PUR pin. The remaining 6 μA is consumed by the device. As described in section 7.2.3 of USB 1.1 specification, When computing suspend current, the current from VBus through the pullup and pulldown resistors must be included. 66 Electrical Specifications Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B tw(L) XINT tr , tf 90% 10% VO(CRS) VOH VOL DM DP TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 3.5 Timing Characteristics 3.6 Clock and Control Signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT Internal 0.75 25 fMCLKO1 Clock frequency, MCLKO1 CL = 50 pF(1) MHz MCLKI 0.625 25 Internal 0.75 25 fMCLKO2 Clock frequency, MCLKO2 CL = 50 pF(1) MHz MCLKI 0.625 25 fMCLKI Clock frequency, MCLKI See (1) 5 25 MHz tw(L) Pulse duration, XINT low CL = 50 pF 0.2 10 μs (1) Worst case duty cycle is 45/55. Figure 3-1. External Interrupt Timing Waveform 3.7 USB Signals When Sourced by TAS1020B over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tr Transition rise time for DP or DM 4 20 ns tf Transition fall time for DP or DM 4 20 ns tRFM Rise/fall time matching (tr / tf) × 100 90% 110% VO(CRS) Voltage output signal crossover 1.3 2 V Figure 3-2. USB Differential Driver Timing Waveform Copyright © 2002–2011, Texas Instruments Incorporated Electrical Specifications 67 Submit Documentation Feedback Product Folder Link(s): TAS1020B tw1(H) tw1(L) tcyc1 tw2(H) tw2(L) tcyc2 BIT_CLK SYNC tsu th BIT_CLK tpd1 SYNC, SD_OUT SD_IN TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 3.8 Codec Port Interface Signals (AC ’97 Modes) TA = 25°C, DVDD = 3.3 V, AVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fBIT_CLK Frequency, BIT_CLK See (1) 12.288 MHz tcyc1 Cycle time, BIT_CLK See (1) 81.4 ns tw1(H) Pulse duration, BIT_CLK high See (1) 36 40.7 45 ns tw1(L) Pulse duration, BIT_CLK low See (1) 36 40.7 45 ns fSYNC Frequency, SYNC CL = 50 pF 48 kHz tcyc2 Cycle time, SYNC CL = 50 pF 20.8 μs tw2(H) Pulse duration, SYNC high CL = 50 pF 1.3 μs tw2(L) Pulse duration, SYNC low CL = 50 pF 19.5 μs tpd1 Propagation delay time, BIT_CLK rising edge to SYNC, SD_OUT CL = 50 pF 15 ns tsu Setup time, SD_IN to BIT_CLK falling edge 10 ns th Hold time, SD_IN from BIT_CLK falling edge 10 ns (1) Worst case duty cycle is 45/55. Figure 3-3. BIT_CLK and SYNC Timing Waveforms Figure 3-4. SYNC, SD_IN, and SD_OUT Timing Waveforms 68 Electrical Specifications Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B tsu th SCLK LRCLK, SD_OUT SD_IN tpd tcyc tsu th CSCLK CSYNC, CDATO, CSCHNE, CRESET CDATI tpd tcyc TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 3.9 Codec Port Interface Signals (I2S Modes) over recommended operating conditions (unless otherwise noted) TEST CONDITIONS MIN MAX UNIT fSCLK Frequency, SCLK CL = 50 pF (32)FS (64)FS MHz tcyc Cycle time, SCLK CL = 50 pF(1) 1/(64)FS 1/(32)FS ns tpd Propagation delay, SCLK falling edge to LRCLK and SDOUT CL = 50 pF 15 ns tsu Setup time, SDIN to SCLK rising edge 10 ns th Hold time, SDIN from SCLK rising edge 10 ns (1) Worst case duty cycle is 45/55. Figure 3-5. I2S Mode Timing Waveforms 3.10 Codec Port Interface Signals (General-Purpose Mode) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT fCSCLK Frequency, CSCLK CL = 50 pF 0.125 25 MHz tcyc Cycle time, CSCLK CL = 50 pF(1) 0.040 8 μs tpd Propagation delay, CSCLK to CSYNC, CDATO, CSCHNE and CRESET CL = 50 pF 15 ns tsu Setup time, CDATI to CSCLK 10 ns th Hold time, CDATI from CSCLK 10 ns (1) The timing waveforms in Figure 3-6 show the CSYNC, CDATO, CSCHNE, and CRESET signals generated with the rising edge of the clock and the CDATI signal sampled with the falling edge of the clock. The edge of the clock used is programmable. However, the timing characteristics are the same regardless of which edge of the clock is used. Figure 3-6. General-Purpose Mode Timing Waveforms Copyright © 2002–2011, Texas Instruments Incorporated Electrical Specifications 69 Submit Documentation Feedback Product Folder Link(s): TAS1020B tw(H) tw(L) tr tf tsu1 tpd1 SCL SDA tsu2 th2 tsu3 tbuf SCL SDA Start Condition Stop Condition SCL 1 2 8 9 SDA OUT SDA IN TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 3.11 I2C Interface Signals over recommended operating conditions (unless otherwise noted) STANDARD FAST MODE PARAMETER MODE UNIT MIN MAX MIN MAX fSCL Frequency, SCL 0 100 0 400 kHz tw(H) Pulse duration, SCL high 4 0.6 μs tw(L) Pulse duration, SCL low 4.7 1.3 μs tr Rise time, SCL and SDA 1000 300 ns tf Fall time, SCL and SDA 300 300 ns tsu1 Setup time, SDA to SCL 250 100 ns tpd1 Propagation delay, SCL to SDA (5-kΩ pullup resistor) 300 500 300 500 ns tbuf Bus free time between stop and start condition 4.7 1.3 μs tsu2 Setup time, SCL to start condition 4.7 0.6 μs th2 Hold time, start condition to SCL 4 0.6 μs tsu3 Setup time, SCL to stop condition 4 0.6 μs CL Load capacitance for each bus line 400 400 pF Figure 3-7. SCL and SDA Timing Waveforms Figure 3-8. Start and Stop Conditions Timing Waveforms Figure 3-9. Acknowledge Timing Waveform 70 Electrical Specifications Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B 24C64 33 28 2 3 4 5 6 7 8 P1.4 P1.3 32 31 30 CDATI CSYNC TEST EXTEN MCLKI PUR DP DM 27 26 29 9 10 11 12 25 1 P1.2 PLLFILO DVSS DVSS TAS1020B P1.5 P1.6 P1.7 CSCHNE 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 PLLFILI XTALI XTALO SCL SDA MCLKO2 MCLKO1 CDATO P1.1 CSCLK P1.0 NC DVDD NC P3.5 P3.4 P3.3 P3.1 P3.0 3.3 VD 3.3 VD 1 μF 3.3 VD 10 k! VCC WP SCL SDA GND A2 3.09 k! 1000 pF 100 pF AGND 3.3 VA 27 pF XTAL 6 MHz 27 pF AGND MCLKO A1 A0 DGND DGND 3.3 VD 2 k! Top Layer Ground Shield Ferrite Bead 9 ! at 100 MHz 20 k! + C1 C5 35 36 34 C3 C2 2 k! C4 Voltage Regulator + 10 μF 16 V C1 0.1 μF C2 0.1 μF DGND C3 0.1 μF C4 0.1 μF 3.3 VD (To TAS1020B Device Only) 1.0 ! 1 μF 16 V + C5 0.1 μF AGND 3.3 VA (To TAS1020B Device Only) 3.3 V DGND 1.0 ! CRESET MRESET RSTO P3.2/XINT RESET VREN DVDD AVDD DVDD DVSS AVSS USB_CONN 27.4 W 27.4 W 15 kW 1.5 kW PN2222A (see Note E) Data– Data+ VCC GND VCC TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 4 Application Information A. If MCLKI and CSCHNE are not used, they must be connected to DGND. B. Capacitors C1, C2, C3, C4, and C5 are as shown to indicate they must be mounted as close to the pins as possible. C. NC on pins 20 and 22 means they must be left unconnected when running in normal mode. D. Crystal load capacitors are shown as 27 pF, but recommendations of crystal manufactures should be followed. E. Q1 and associated circuitry is required for USB back-voltage certification test. Figure 4-1. Typical TAS1020B Device Connections Copyright © 2002–2011, Texas Instruments Incorporated Application Information 71 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 5 8K ROM The 8K ROM is mask-programmed as part of the TAS1020B manufacturing process. The ROM program provides the boot behavior as discussed in Section 2.2.2. It also provides support functions for the user's application. Source for the ROM image is provided in the TAS1020B Firmware Development Kit (http://focus.ti.com/docs/toolsw/folders/print/tas1020fdk.html). 5.1 ROM Errata It is not possible for an application that uses the ROM support functions to stall an invalid control transaction that has a data stage. 72 8K ROM Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6 MCU Memory and Memory-Mapped Registers This section describes the TAS1020B MCU memory configurations and operation. In general, the MCU memory operation is the same as the industry standard 8052 MCU. 6.1 MCU Memory Space The TAS1020B MCU memory is organized into three individual spaces: program memory, external data memory, and internal data memory. All memory resources reside within the TAS1020B; the terms internal and external refer to memory resources internal to and external to the MCU core residing in the TAS1020B. The total address range for the program memory and the external data memory spaces is 64K bytes each. The total address range for the internal data memory is 256 bytes. The actual mapping of physical memory resources into these three individual spaces is dependent on which operating mode is active, boot loader mode or normal mode. The operating mode is determined by the setting of the SDW bit in the MCU memory configuration register. At power turnon, or after a master reset, the SDW bit is reset and the boot loader mode is active. In this mode, and 8K ROM resource within the TAS1020B is mapped to program space beginning at address 0000h. This same 8K ROM is also mapped to program space beginning at address 8000h. The TAS1020B uses the 8K boot ROM as the program memory when in the boot loader mode. The boot ROM program code downloads the application program code from a nonvolatile memory (EEPROM) on the peripheral PCB, and writes the code to a 6K RAM resource internal to the TAS1020B. In the boot loader mode, this 6K RAM resource is mapped to the external data memory space starting at address 0000h. (If a valid EEPROM resource is not available, the TAS1020B initializes in the DFU program mode and requires a download of application code to RAM—see Section 2.2.2.2). After downloading the application program code to the 6K RAM resource, the boot ROM enables the normal operating mode by setting the ROM disable (SDW) bit to enable program code execution from the 6K RAM instead of the boot ROM. In the normal operating mode, the boot ROM is still mapped to program memory space starting at address 8000h, but the 6K RAM resource is now mapped to program memory space beginning at address 0000h. Also, in the normal operating mode, the RAM resource becomes a read-only memory resource that cannot be written to. Refer to Figure 6-1 and Figure 6-2 for details. In the normal operating mode, the external data memory space contains the data buffers for the USB endpoints, the configuration blocks for the USB endpoints, the setup data packet buffer for the USB control endpoint, and memory-mapped registers. The data buffers for the USB endpoints, the configuration blocks for the USB endpoints and the setup data packet buffer for the USB control endpoints are all implemented in RAM, and this RAM resource is separate from the 6K RAM resource used to house the application code. The memory-mapped registers used for control and status registers are implemented in hardware with flip-flops. The data buffers for the USB endpoints total 1304 bytes, the configuration blocks for the USB endpoints total 128 bytes, the setup packet buffer for the USB control endpoint is 8 bytes, and the memory-mapped-register space is 80 bytes. The total external data memory space used for these blocks of memory then is 1520 bytes. 6.2 Internal Data Memory The internal data memory space is a total of 256 bytes of RAM, which includes the 128 bytes of special function registers (SFR) space. The internal data memory space is mapped in accordance with the industry standard 8052 MCU. The internal data memory space is mapped from 00h to FFh with the SFRs mapped from 80h to FFh. The lower 128 bytes are accessible with both direct and indirect addressing. However, the upper 128 bytes, which is the SFR space, is only accessible with direct addressing. Note that the internal data memory space is separate and distinct from the external data memory space, and although both spaces begin at address 0000h, there is no overlap. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 73 Submit Documentation Feedback Product Folder Link(s): TAS1020B Program Memory FFFFh 24K − Reserved A000h 9FFFh Boot ROM (8K) 24K − Reserved 2000h 1FFFh Boot ROM (8K) (Boot loader and library 0000h of USB functions) External Data Memory FFFFh Memory Mapped Registers (80 Bytes) FFB0h FFAFh USB End-Point Configuration Blocks and Buffer Space (1440 Bytes) FA10h FA0Fh 58,000 Bytes − Reserved 1780h 177Fh Code RAM (6016 Bytes) (Read/Write) (Loaded from EEPROM 0000h by boot loader) 8000h 7FFFh TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Figure 6-1. Boot Loader Mode Memory Map 74 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B Program Memory FFFFh 24K − Reserved A000h 9FFFh Boot ROM (8K) 26752 Bytes 0000h External Data Memory FFFFh Memory Mapped Registers (80 Bytes) FFB0h FFAFh USB End-Point Configuration Blocks and Buffer Space (1440 Bytes) FA10h FA0Fh 64016 Bytes − Reserved 1780h 177Fh Code RAM (6016 Bytes) 0000h 8000h 7FFFh (Read/Write) TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Figure 6-2. Normal Operating Mode Memory Map 6.3 External MCU Mode Memory Space When using an external MCU for firmware development, only the USB configuration blocks, the USB buffer space, and the memory-mapped registers are accessible by the external MCU. See Section 6.4 for details. In this mode, only address lines A0 to A10 are input to the TAS1020B device from the external MCU. Therefore, the USB buffer space and the memory-mapped registers in the external data memory space are not fully decoded since all sixteen address lines are not available. Hence, the USB buffer space and the memory-mapped registers are actually accessible at any 2K boundary within the total 64K external data memory space of the external MCU. As a result, when using the TAS1020B in the external MCU mode, nothing can be mapped to the external data memory space of the external MCU except the USB buffer space and the memory-mapped registers of the TAS1020B device. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 75 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.4 USB Endpoint Configuration Blocks and Data Buffer Space 6.4.1 USB Endpoint Configuration Blocks The USB endpoint configuration space contains 16 8-byte blocks that define configuration, buffer location, buffer size, and data count for the 16 (8 input and 8 output) USB endpoints. The MCU, UBM, and DMA all have access to these configuration blocks. Each of the 16 endpoints in the TAS1020B can be configured as a USB pipe endpoint by initializing the block configuration register assigned to each endpoint. The location of the endpoint X and Y data buffers for each endpoint is set by the value programmed into the X and Y buffer base address registers. Base addresses are octet (8-byte) aligned. The size of the X and Y buffers is set by initializing the buffer size register. The size of the X and Y buffers must be greater than or equal to the USB packet size associated with the endpoint. For Isochronous endpoints, the buffer size defines the size of the single circular buffer. For IN transactions, the X and Y data count registers assigned to each endpoint are set by the USB buffer manager (UBM) to register the size of the new data packet just received. For OUT transactions, the X and Y data count registers assigned to each endpoint are set by the DMA logic or the MCU to register the size of the data packet to be output. For control, interrupt, and bulk transactions, the data count is the number of samples per transaction. 6.4.2 Data Buffer Space The endpoint data buffer space (1304 bytes) provides rate buffering between the data traffic on the USB bus and data traffic to and from the codecs attached to the TAS1020B. Buffers are defined in this space by base address pointers and size descriptors in the USB endpoint configuration blocks. The MCU also has access to this space. In order to conserve RAM memory resources on the TAS1020B, several USB-specific routines have been included in the firmware resident in the on-chip ROM. These ROM support functions are detailed in Section 2.2.2.7. To provide temporary variable storage for these ROM support functions, locations FA10h through FA63h (84 bytes) of the 1304 bytes of data buffer space are reserved for use by the ROM support functions. This then leaves 1220 bytes for the endpoint buffer memories, which service applications up to 6 channels, 48 kHz sampling rate with 16 bits per sample or 4 channels, 48-kHz sampling rate with 24 bits per sample. (If the ROM support functions are not used, the entire block of 1304 bytes can be assigned to endpoint buffer memories.) The values entered into the X and Y buffer base address registers are offset addresses. The lower memory address (or Base address) of a given X (Y) buffer is determined by adding the value in the base address register (multiplied by 8) to the base address of the block of memory assigned to the X and Y buffers. For the TAS1020B, this base address is FA10h. However, the base address of the TUSB3200 members of the family of USB streaming audio controllers, of which the TAS1020B is also a member, is F800h. To maintain software compatibility between family members, the value entered into the base address register for the TAS1020B (as well as the other family members) must be the offset from the base address F800h. For example, assume the X buffer for IN endpoint 3 is to be established starting at address FA60h. For the TAS1020B, the offset of this address from the FA10h base address of the block of memory assigned to the X and Y buffers is 50h. Nevertheless, the value entered into the X buffer base address for IN endpoint 3 must be 4Ch, because F800h + 8 × 4Ch = FA60h. 76 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B External Data Memory Memory Mapped Registers (80 Bytes) Endpoint Configuration Blocks (128 Bytes) Setup Data Packet Buffer (8 Bytes) (see Note A) Endpoint Data Buffers (1220 Bytes) FFFFh FFB0h FFAFh FF30h FF2Fh FF28h FF27h FA10h DMA Access DMA Access MCU Access UBM Access FA64h FA63h ROM Support (84 Bytes) TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 A. See Section 6.4.5. Figure 6-3. USB Endpoint Configuration Blocks and Buffer Space Memory Map Table 6-1. USB Endpoint Configuration Blocks Address Map ADDRESS MNEMONIC NAME FFAFh OEPDCNTY0 OUT endpoint 0 - Y buffer data count byte FFAEh Reserved Reserved for future use FFADh OEPBBAY0 OUT endpoint 0 - Y buffer base address byte FFACh Reserved Reserved for future use FFABh OEPDCNTX0 OUT endpoint 0 - X buffer data count byte FFAAh OEPBSIZ0 OUT endpoint 0 - X and Y buffer size byte FFA9h OEPBBAX0 OUT endpoint 0 - X buffer base address byte FFA8h OEPCNF0 OUT endpoint 0 - configuration byte FFA7h OEPDCNTY1 OUT endpoint 1 - Y buffer data count byte FFA6h Reserved Reserved for future use FFA5h OEPBBAY1 OUT endpoint 1 - Y buffer base address byte FFA4h Reserved Reserved for future use FFA3h OEPDCNTX1 OUT endpoint 1 - X buffer data count byte FFA2h OEPBSIZ1 OUT endpoint 1 - X and Y buffer size byte FFA1h OEPBBAX1 OUT endpoint 1 - X buffer base address byte FFA0h OEPCNF1 OUT endpoint 1 - configuration byte FF9Fh OEPDCNTY2 OUT endpoint 2 - Y buffer data count byte FF9Eh Reserved Reserved for future use FF9Dh OEPBBAY2 OUT endpoint 2 - Y buffer base address byte FF9Ch Reserved Reserved for future use FF9Bh OEPDCNTX2 OUT endpoint 2 - X buffer data count byte FF9Ah OEPBSIZ2 OUT endpoint 2 - X and Y buffer size byte FF99h OEPBBAX2 OUT endpoint 2 - X buffer base address byte FF98h OEPCNF2 OUT endpoint 2 - configuration byte FF97h OEPDCNTY3 OUT endpoint 3 - Y buffer data count byte Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 77 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Table 6-1. USB Endpoint Configuration Blocks Address Map (continued) ADDRESS MNEMONIC NAME FF96h Reserved Reserved for future use FF95h OEPBBAY3 OUT endpoint 3 - Y buffer base address byte FF94h Reserved Reserved for future use FF93h OEPDCNTX3 OUT endpoint 3 - X buffer data count byte FF92h OEPBSIZ3 OUT endpoint 3 - X and Y buffer size byte FF91h OEPBBAX3 OUT endpoint 3 - X buffer base address byte FF90h OEPCNF3 OUT endpoint 3 - configuration byte FF8Fh OEPDCNTY4 OUT endpoint 4 - Y buffer data count byte FF8Eh Reserved Reserved for future use FF8Dh OEPBBAY4 OUT endpoint 4 - Y buffer base address byte FF8Ch Reserved Reserved for future use FF8Bh OEPDCNTX4 OUT endpoint 4 - X buffer data count byte FF8Ah OEPBSIZ4 OUT endpoint 4 - X and Y buffer size byte FF89h OEPBBAX4 OUT endpoint 4 - X buffer base address byte FF88h OEPCNF4 OUT endpoint 4 - configuration byte FF87h OEPDCNTY5 OUT endpoint 5 - Y buffer data count byte FF86h Reserved Reserved for future use FF85h OEPBBAY5 OUT endpoint 5 - Y buffer base address byte FF84h Reserved Reserved for future use FF83h OEPDCNTX5 OUT endpoint 5 - X buffer data count byte FF82h OEPBSIZ5 OUT endpoint 5 - X and Y buffer size byte FF81h OEPBBAX5 OUT endpoint 5 - X Buffer Base Address Byte FF80h OEPCNF5 OUT endpoint 5 - configuration byte FF7Fh OEPDCNTY6 OUT endpoint 6 - Y buffer data count byte FF7Eh Reserved Reserved for future use FF7Dh OEPBBAY6 OUT endpoint 6 - Y buffer base address byte FF7Ch Reserved Reserved for future use FF7Bh OEPDCNTX6 OUT endpoint 6 - X buffer data count byte FF7Ah OEPBSIZ6 OUT endpoint 6 - X and Y buffer size byte FF79h OEPBBAX6 OUT endpoint 6 - X buffer base address byte FF78h OEPCNF6 OUT endpoint 6 - configuration byte FF77h OEPDCNTY7 OUT endpoint 7 - Y buffer data count byte FF76h Reserved Reserved for future use FF75h OEPBBAY7 OUT endpoint 7 - Y buffer base address byte FF74h Reserved Reserved for future use FF73h OEPDCNTX7 OUT endpoint 7 - X buffer data count byte FF72h OEPBSIZ7 OUT endpoint 7 - X and Y buffer size byte FF71h OEPBBAX7 OUT endpoint 7 - X buffer base address byte FF70h OEPCNF7 OUT endpoint 7 - configuration byte FF6Fh IEPDCNTY0 IN endpoint 0 - Y buffer data count byte FF6Eh Reserved Reserved for future use FF6Dh IEPBBAY0 IN endpoint 0 - Y buffer base address byte FF6Ch Reserved Reserved for future use FF6Bh IEPDCNTX0 IN endpoint 0 - X buffer data count byte FF6Ah IEPBSIZ0 IN endpoint 0 - X and Y buffer size byte FF69h IEPBBAX0 IN endpoint 0 - X buffer base address byte FF68h IEPCNF0 IN endpoint 0 - configuration byte 78 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 Table 6-1. USB Endpoint Configuration Blocks Address Map (continued) ADDRESS MNEMONIC NAME FF67h IEPDCNTY1 IN endpoint 1 - Y buffer data count byte FF66h Reserved Reserved for future use FF65h IEPBBAY1 IN endpoint 1 - Y buffer base address byte FF64h Reserved Reserved for future use FF63h IEPDCNTX1 IN endpoint 1 - X buffer data count byte FF62h IEPBSIZ1 IN endpoint 1 - X and Y buffer size byte FF61h IEPBBAX1 IN endpoint 1 - X buffer base address byte FF60h IEPCNF1 IN endpoint 1 - configuration byte FF5Fh IEPDCNTY2 IN endpoint 2 - Y buffer data count byte FF5Eh Reserved Reserved for future use FF5Dh IEPBBAY2 IN endpoint 2 - Y buffer base address byte FF5Ch Reserved Reserved for future use FF5Bh IEPDCNTX2 IN endpoint 2 - X buffer data count byte FF5Ah IEPBSIZ2 IN endpoint 2 - X and Y buffer size byte FF59h IEPBBAX2 IN endpoint 2 - X buffer base address byte FF58h IEPCNF2 IN endpoint 2 - configuration byte FF57h IEPDCNTY3 IN endpoint 3 - Y buffer data count byte FF56h Reserved Reserved for future use FF55h IEPBBAY3 IN endpoint 3 - Y buffer base address byte FF54h Reserved Reserved for future use FF53h IEPDCNTX3 IN endpoint 3 - X buffer data count byte FF52h IEPBSIZ3 IN endpoint 3 - X and Y buffer size byte FF51h IEPBBAX3 IN endpoint 3 - X buffer base address byte FF50h IEPCNF3 IN endpoint 3 - configuration byte FF4Fh IEPDCNTY4 IN endpoint 4 - Y buffer data count byte FF4Eh Reserved Reserved for future use FF4Dh IEPBBAY4 IN endpoint 4 - Y buffer base address byte FF4Ch Reserved Reserved for future use FF4Bh IEPDCNTX4 IN endpoint 4 - X buffer data count byte FF4Ah IEPBSIZ4 IN endpoint 4 - X and Y buffer size byte FF49h IEPBBAX4 IN endpoint 4 - X buffer base address byte FF48h IEPCNF4 IN endpoint 4 - configuration byte FF47h IEPDCNTY5 IN endpoint 5 - Y buffer data count byte FF46h Reserved Reserved for future use FF45h IEPBBAY5 IN endpoint 5 - Y buffer base address byte FF44h Reserved Reserved for future use FF43h IEPDCNTX5 IN endpoint 5 - X buffer data count byte FF42h IEPBSIZ5 IN endpoint 5 - X and Y buffer size byte FF41h IEPBBAX5 IN endpoint 5 - X buffer base address byte FF40h IEPCNF5 IN endpoint 5 - configuration byte FF3Fh IEPDCNTY6 IN endpoint 6 - Y buffer data count byte FF3Eh Reserved Reserved for future use FF3Dh IEPBBAY6 IN endpoint 6 - Y buffer base address byte FF3Ch Reserved Reserved for future use FF3Bh IEPDCNTX6 IN endpoint 6 - X buffer data count byte FF3Ah IEPBSIZ6 IN endpoint 6 - X and Y buffer size byte FF39h IEPBBAX6 IN endpoint 6 - X buffer base address byte Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 79 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Table 6-1. USB Endpoint Configuration Blocks Address Map (continued) ADDRESS MNEMONIC NAME FF38h IEPCNF6 IN endpoint 6 - configuration byte FF37h IEPDCNTY7 IN endpoint 7 - Y buffer data count byte FF36h Reserved Reserved for future use FF35h IEPBBAY7 IN endpoint 7 - Y buffer base address byte FF34h Reserved Reserved for future use FF33h IEPDCNTX7 IN endpoint 7 - X buffer data count byte FF32h IEPBSIZ7 IN endpoint 7 - X and Y buffer size byte FF31h IEPBBAX7 IN endpoint 7 - X buffer base address byte FF30h IEPCNF7 IN endpoint 7 - configuration byte 6.4.3 USB OUT Endpoint Configuration Bytes This section describes the individual bytes in the USB endpoint configuration blocks for the OUT endpoints. A set of 8 bytes is used for the control and operation of each USB OUT endpoint. In addition to the USB control endpoint, the TAS1020B supports up to a total of seven OUT endpoints. 6.4.3.1 USB OUT Endpoint - Y Buffer Data Count Byte (OEPDCNTYx) The USB OUT endpoint Y buffer data count byte contains the 7-bit value used to specify the amount of data received in a data packet from the host PC. The no acknowledge status bit is also contained in this byte. Bit 7 6 5 4 3 2 1 0 Mnemonic NACK DCNTY6 DCNTY5 DCNTY4 DCNTY3 DCNTY2 DCNTY1 DCNTY0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB OUT transaction to this endpoint to indicate that the USB endpoint Y buffer contains a valid data packet and that the Y buffer data count value is valid. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the endpoint result in a NACK handshake response to the host PC. 7 NACK No acknowledge Also for control, interrupt, and bulk endpoints to enable this endpoint to receive another data packet from the host PC, this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to receiving the next data packet. However, the MCU or DMA must clear this bit before reading the data packet from the buffer. The Y buffer data count value is set by the UBM when a new data packet is written to the Y buffer for the OUT endpoint. The 7-bit value is set to the number of bytes in the data packet for control, interrupt or bulk endpoint transfers and is set to the number of 6:0 DCNTY(6:0) Y Buffer data count samples in the data packet for isochronous endpoint transfers. To determine the number of samples in the data packet for isochronous transfers, the bytes per sample value in the configuration byte is used. The data count value is read by the MCU or DMA to obtain the data packet size. 6.4.3.2 USB OUT Endpoint - Y Buffer Base Address Byte (OEPBBAYx) The USB OUT endpoint Y buffer base address byte contains the 8-bit value used to specify the base memory location for the Y data buffer for a particular USB OUT endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BBAY10 BBAY9 BBAY8 BBAY7 BBAY6 BBAY5 BBAY4 BBAY3 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The Y buffer base address value is set by the MCU to program the base address 7:0 BBAY(10:3) Y Buffer base address location in memory to be used for the Y data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the address. All 0s are used by the hardware for the three least significant bits. 80 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.4.3.3 USB OUT Endpoint - X Buffer Data Count Byte (OEPDCNTXx) The USB OUT endpoint X buffer data count byte contains the 7-bit value used to specify the amount of data received in a data packet from the host PC. The no acknowledge status bit is also contained in this byte. Bit 7 6 5 4 3 2 1 0 Mnemonic NACK DCNTX6 DCNTX5 DCNTX4 DCNTX3 DCNTX2 DCNTX1 DCNTX0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB OUT transaction to this endpoint to indicate that the USB endpoint X buffer contains a valid data packet and that the X buffer data count value is valid. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the endpoint result in a NACK handshake response to the host PC. 7 NACK No acknowledge Also for control, interrupt, and bulk endpoints to enable this endpoint to receive another data packet from the host PC, this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to receiving the next data packet. However, the MCU or DMA must clear this bit before reading the data packet from the buffer. The X buffer data count value is set by the UBM when a new data packet is written to the X buffer for the OUT endpoint. The 7-bit value is set to the number of bytes in the data packet for control, interrupt, or bulk endpoint transfers and is set to the number of 6:0 DCNTX(6:0) X Buffer data count samples in the data packet for isochronous endpoint transfers. To determine the number of samples in the data packet for isochronous transfers, the bytes per sample value in the configuration byte is used. The data count value is read by the MCU or DMA to obtain the data packet size. 6.4.3.4 USB OUT Endpoint - X and Y Buffer Size Byte (OEPBSIZx) The USB OUT endpoint X and Y buffer size byte contains the 8-bit value used to specify the size of the two data buffers to be used for this endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BSIZ7 BSIZ6 BSIZ5 BSIZ4 BSIZ3 BSIZ2 BSIZ1 BSIZ0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION For control, interrupt, and bulk transactions, the X and Y buffer size value is set by the MCU to program the size of the X and Y data packet buffers. Both buffers are 7:0 BSIZ(7:0) Buffer size programmed to the same size based on this value. This value is in 8-byte units. For example, a value of 18h results in the size of the X and Y buffers each being set to 192 bytes. For isochronous transactions, the buffer size sets the size of the single circular buffer. 6.4.3.5 USB OUT Endpoint - X Buffer Base Address Byte (OEPBBAXx) The USB OUT endpoint X buffer base address byte contains the 8-bit value used to specify the base memory location for the X data buffer for a particular USB OUT endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BBAX10 BBAX9 BBAX8 BBAX7 BBAX6 BBAX5 BBAX4 BBAX3 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The X buffer base address value is set by the MCU to program the base address 7:0 BBAX(10:3) X Buffer base address location in memory to be used for the X data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the address. All 0s are used by the hardware for the three least significant bits. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 81 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.4.3.6 USB OUT Endpoint - Configuration Byte (OEPCNFx) The USB OUT endpoint configuration byte contains the various bits used to configure and control the endpoint. Note that the bits in this byte take on different functionality based on the type of endpoint defined. The control, interrupt, and bulk endpoints function differently than the isochronous endpoints. 6.4.3.6.1 USB OUT Endpoint Configuration Byte Settings—Control, interrupt, or Bulk Transactions This section defines the functionality of the bits in the USB OUT endpoint configuration byte for control, interrupt, and bulk endpoints. Bit 7 6 5 4 3 2 1 0 Mnemonic OEPEN ISO TOGGLE DBUF STALL OEPIE — — Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION 7 OEPEN Endpoint enable The endpoint enable bit is set to 1 by the MCU to enable the OUT endpoint. The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a 6 ISO Isochronous endpoint particular OUT endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU to use a particular OUT endpoint for control, interrupt, or bulk transactions. The toggle bit is controlled by the UBM and is toggled at the end of a successful out 5 TOGGLE Toggle data stage transaction if a valid data packet is received and the data packet PID matches the expected PID. The double buffer mode bit is set to 1 by the MCU to enable the use of both the X and 4 DBUF Double buffer mode Y data packet buffers for USB transactions to a particular OUT endpoint. This bit must be cleared to a 0 by the MCU to use the single buffer mode. In the single buffer mode, only the X buffer is used. The stall bit is set to 1 by the MCU to stall endpoint transactions. When this bit is set, the hardware automatically returns a stall handshake to the host PC for any transaction received for the endpoint. An exception is the control endpoint setup stage transaction, which must always received. This requirement allows a 3 STALL Stall Clear_Feature_Stall request to be received from the host PC. Control endpoint data and status stage transactions however can be stalled. The stall bit is cleared to a 0 by the MCU if a Clear_Feature_Stall request or a USB reset is received from the host PC. For a control write transaction, if the amount of data received is greater than expected, the UBM sets the stall bit to a 1 to stall the endpoint. When the stall bit is set to a 1 by the UBM, the USB OUT endpoint 0 interrupt is generated. 2 OEPIE Interrupt enable The interrupt enable bit is set to a 1 by the MCU to enable the OUT endpoint interrupt. See Section 6.5.7.1 for details on the OUT endpoint interrupts. 1:0 — Reserved Reserved for future use 82 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.4.3.6.2 USB OUT Endpoint Configuration Byte Settings—Isochronous Transactions This section defines the functionality of the bits in the USB OUT endpoint configuration byte for isochronous endpoints. Bit 7 6 5 4 3 2 1 0 Mnemonic OEPEN ISO OVF BPS4 BPS3 BPS2 BPS1 BPS0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION 7 OEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the OUT endpoint. The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a 6 ISO Isochronous endpoint particular OUT endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU for a particular OUT endpoint to be used for control, interrupt, or bulk transactions. The overflow bit is set to a 1 by the UBM to indicate a buffer overflow condition has 5 OVF Overflow occurred. This bit is used for diagnostic purposes only and is not used for normal operation. This bit can only be cleared to a 0 by the MCU. The bytes per sample bits are used to define the number of bytes per isochronous data sample. In other words, the total number of bytes in an entire audio codec frame. 4:0 BPS(4:0) Bytes per sample For example, a PCM 16-bit stereo audio data sample consists of 4 bytes. There are two bytes of left channel data and two bytes of right channel data. For a four channel system using 16-bit data, the total number of bytes is 8, which is the isochronous data sample size.00h = 1 byte, 01h = 2 bytes, …, 1Fh = 32 bytes 6.4.4 USB IN Endpoint Configuration Bytes This section describes the individual bytes in the USB endpoint configuration blocks for the IN endpoints. A set of 8 bytes is used for the control and operation of each USB IN endpoint. In addition to the USB control endpoint, the TAS1020B supports up to a total of seven IN endpoints. 6.4.4.1 USB IN Endpoint - Y Buffer Data Count Byte (IEPDCNTYx) The USB IN endpoint Y buffer data count byte contains the 7-bit value used to specify the amount of data to be transmitted in a data packet to the host PC. The no acknowledge status bit is also contained in this byte. Bit 7 6 5 4 3 2 1 0 Mnemonic NACK DCNTY6 DCNTY5 DCNTY4 DCNTY3 DCNTY2 DCNTY1 DCNTY0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB IN transaction to this endpoint to indicate that the USB endpoint Y buffer is empty. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the endpoint result in a NACK handshake response to the 7 NACK No acknowledge host PC. Also for control, interrupt, and bulk endpoints to enable this endpoint to transmit another data packet to the Host PC, this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to sending the next data packet. However, the MCU or DMA must clear this bit after writing a data packet to the buffer. The Y buffer data count value is set by the MCU or DMA when a new data packet is written to the Y buffer for the IN endpoint. The 7-bit value is set to the number of bytes 6:0 DCNTY(6:0) Y Buffer data count in the data packet for control, interrupt, or bulk endpoint transfers and is set to the number of samples in the data packet for isochronous endpoint transfers. To determine the number of samples in the data packet for isochronous transfers, the bytes per sample value in the configuration byte is used. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 83 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.4.4.2 USB IN Endpoint - Y Buffer Base Address Byte (IEPBBAYx) The USB IN endpoint Y buffer base address byte contains the 8-bit value used to specify the base memory location for the Y data buffer for a particular USB IN endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BBAY10 BBAY9 BBAY8 BBAY7 BBAY6 BBAY5 BBAY4 BBAY3 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The Y buffer base address value is set by the MCU to program the base address 7:0 BBAY(10:3) Y Buffer base address location in memory to be used for the Y data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the address. All 0s are used by the hardware for the three least significant bits. 6.4.4.3 USB IN Endpoint - X Buffer Data Count Byte (IEPDCNTXx) The USB IN endpoint X buffer data count byte contains the 7-bit value used to specify the amount of data received in a data packet from the host PC. The no acknowledge status bit is also contained in this byte. Bit 7 6 5 4 3 2 1 0 Mnemonic NACK DCNTX6 DCNTX5 DCNTX4 DCNTX3 DCNTX2 DCNTX1 DCNTX0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The no acknowledge status bit is set to a 1 by the UBM at the end of a successful USB IN transaction to this endpoint to indicate that the USB endpoint X buffer is empty. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent transactions to the endpoint result in a NACK handshake response to the 7 NACK No acknowledge host PC. Also for control, interrupt, and bulk endpoints to enable this endpoint to transmit another data packet to the host PC, this bit must be cleared to a 0 by the MCU. For isochronous endpoints, a NACK handshake response to the host PC is not allowed. Therefore, the UBM ignores this bit in reference to sending the next data packet. However, the MCU or DMA must clear this bit after writing a data packet to the buffer. The X buffer data count value is set by the MCU or DMA when a new data packet is written to the X buffer for the IN endpoint. The 7-bit value is set to the number of bytes 6:0 DCNTX(6:0) X Buffer data count in the data packet for control, interrupt, or bulk endpoint transfers and is set to the number of samples in the data packet for isochronous endpoint transfers. To determine the number of samples in the data packet for isochronous transfers, the bytes per sample value in the configuration byte is used. 6.4.4.4 USB IN Endpoint - X and Y Buffer Size Byte (IEPBSIZx) The USB IN endpoint X and Y buffer size byte contains the 8-bit value used to specify the size of the two data buffers to be used for this endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BSIZ7 BSIZ6 BSIZ5 BSIZ4 BSIZ3 BSIZ2 BSIZ1 BSIZ0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION For control, interrupt, and bulk transactions, the X and Y buffer size value is set by the MCU to program the size of the X and Y data packet buffers. Both buffers are 7 BSIZ(7:0) Buffer size programmed to the same size based on this value. This value should be in 8 byte units. For example, a value of 18h results in the size of the X and Y buffers each being set to 192 bytes. For isochronous transactions, the buffer size sets the size of the single circular buffer. 84 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.4.4.5 USB IN Endpoint - X Buffer Base Address Byte (IEPBBAXx) The USB IN endpoint X buffer base address byte contains the 8-bit value used to specify the base memory location for the X data buffer for a particular USB IN endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic BBAX10 BBAX9 BBAX8 BBAX7 BBAX6 BBAX5 BBAX4 BBAX3 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION The X buffer base address value is set by the MCU to program the base address 7:0 BBAX(10:3) X Buffer base address location in memory to be used for the X data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the address. All 0s are used by the hardware for the three least significant bits. 6.4.4.6 USB IN Endpoint - Configuration Byte (IEPCNFx) The USB IN endpoint configuration byte contains the various bits used to configure and control the endpoint. Note that the bits in this byte take on different functionality based on the type of endpoint defined. Basically, the control, interrupt and bulk endpoints function differently than the isochronous endpoints. 6.4.4.6.1 USB IN Endpoint Configuration Byte Settings - Control, Interrupt or Bulk Transactions This section defines the functionality of the bits in the USB IN endpoint configuration byte for control, interrupt, and bulk endpoints. Bit 7 6 5 4 3 2 1 0 Mnemonic IEPEN ISO TOGGLE DBUF STALL IEPIE — — Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION 7 IEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the IN endpoint. This bit does not affect the reception of the control endpoint setup stage transaction. The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a 6 ISO Isochronous endpoint particular IN endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU to use a particular IN endpoint for control, interrupt, or bulk transactions. The toggle bit is controlled by the UBM and is toggled at the end of a successful in 5 TOGGLE Toggle data stage transaction if a valid data packet is transmitted. If this bit is a 0, a DATA0 PID is transmitted in the data packet to the host PC. If this bit is a 1, a DATA1 PID is transmitted in the data packet. The double buffer mode bit is set to a 1 by the MCU to enable the use of both the X 4 DBUF Double buffer mode and Y data packet buffers for USB transactions to a particular IN endpoint. This bit must be cleared to a 0 by the MCU to use the single buffer mode. In the single buffer mode, only the X buffer is used. The stall bit is set to a 1 by the MCU to stall endpoint transactions. When this bit is 3 STALL Stall set, the hardware automatically returns a stall handshake to the host PC for any transaction received for the endpoint. 2 IEPIE Interrupt enable The interrupt enable bit is set to a 1 by the MCU to enable the IN endpoint interrupt. See Section 6.5.7.2 for details on the IN endpoint interrupts. 1:0 — Reserved Reserved for future use. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 85 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.4.4.6.2 USB IN Endpoint Configuration Byte Settings - Isochronous Transactions This section defines the functionality of the bits in the USB IN endpoint configuration byte for isochronous endpoints. Bit 7 6 5 4 3 2 1 0 Mnemonic IEPEN ISO OVF BPS4 BPS3 BPS2 BPS1 BPS0 Type R/W R/W R/W R/W R/W R/W R/W R/W BIT MNEMONIC NAME DESCRIPTION 7 IEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the IN endpoint. The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a 6 ISO Isochronous endpoint particular IN endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU for a particular IN endpoint to be used for control, interrupt, or bulk transactions. The overflow bit is set to a 1 by the UBM to indicate a buffer overflow condition has 5 OVF Overflow occurred. This bit is used for diagnostic purposes only and is not used for normal operation. This bit can only be cleared to a 0 by the MCU. The bytes per sample bits are used to define the number of bytes per isochronous data sample. In other words, the total number of bytes in an entire audio codec frame. 4:0 BPS(4:0) Bytes per sample For example, a PCM 16-bit stereo audio data sample consists of 4 bytes. There are two bytes of left channel data and two bytes of right channel data. For a four channel system using 16-bit data, the total number of bytes is 8, which is the isochronous data sample size. 00h = 1 byte, 01h = 2 bytes, …, 1Fh = 32 bytes 6.4.5 USB Control Endpoint Setup Stage Data Packet Buffer The USB control endpoint setup stage data packet buffer is the buffer space used to store the 8-byte data packet received from the host PC during a control endpoint transfer setup stage transaction. Refer to Chapter 9 of the USB Specification for details on the data packet. Table 6-2. USB Control Endpoint Setup Data Packet Buffer Address Map ADDRESS NAME FF2Fh wLength - Number of bytes to transfer in the data stage FF2Eh wLength - Number of bytes to transfer in the data stage FF2Dh wIndex - Index or offset value FF2Ch wIndex - Index or offset value FF2Bh wValue - Value of a parameter specific to the request FF2Ah wValue - Value of a parameter specific to the request FF29h bRequest - Specifies the particular request FF28h bmRequestType - Identifies the characteristics of the request 86 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5 Memory-Mapped Registers The TAS1020B device provides a set of control and status registers to be used by the MCU to control the overall operation of the device. This section describes the memory-mapped registers. Table 6-3. Memory-Mapped Registers Address Map ADDRESS MNEMONIC NAME SECTION FFFFh USBFADR USB function address register Section 6.5.1.1 FFFEh USBSTA USB status register Section 6.5.1.2 FFFDh USBIMSK USB interrupt mask register Section 6.5.1.3 FFFCh USBCTL USB control register Section 6.5.1.4 FFFBh USBFNL USB frame number register (low-byte) Section 6.5.1.5 FFFAh USBFNH USB frame number register (high-byte) Section 6.5.1.6 FFF9h ACG2FRQ0 Adaptive clock generator2 frequency register (Byte 0) Section 6.5.3.6 FFF8h ACG2FRQ1 Adaptive clock generator2 frequency register (Byte 1) Section 6.5.3.7 FFF7h ACG2FRQ2 Adaptive clock generator2 frequency register (Byte 2) Section 6.5.3.8 FFF6h ACG2DCTL Adaptive clock generator2 divider control register Section 6.5.3.9 FFF5h Reserved Reserved for future use FFF4h DMABCNT1H DMA buffer content register (high-byte) (channel 1) Section 6.5.2.5 FFF3h DMABCNT1L DMA buffer content register (low-byte) (channel 1) Section 6.5.2.4 FFF2h DMABPCT0 DMA bulk packet count register (low-byte) Section 6.5.2.6 FFF1h DMABPCT1 DMA bulk packet count register (high-byte) Section 6.5.2.7 FFF0h DMATSL1 DMA time slot assignment register (low-byte) (channel 1) Section 6.5.2.1 FFEFh DMATSH1 DMA time slot assignment register (high-byte) (channel 1) Section 6.5.2.1 FFEEh DMACTL1 DMA control register (channel 1) Section 6.5.2.3 FFEDh Reserved Reserved for future use FFECh DMABCNT0H DMA current buffer content register (high-byte) (channel 0) Section 6.5.2.5 FFEBh DMABCNT0L DMA current buffer content register (low-byte) (channel 0) Section 6.5.2.4 FFEAh DMATSL0 DMA time slot assignment register (low-byte) (channel 0) Section 6.5.2.1 FFE9h DMATSH0 DMA time slot assignment register (high-byte) (channel 0) Section 6.5.2.2 FFE8h DMACTL0 DMA control register (channel 0) Section 6.5.2.3 FFE7h ACG1FRQ0 Adaptive clock generator1 frequency register (byte 0) Section 6.5.3.1 FFE6h ACG1FRQ1 Adaptive clock generator1 frequency register (byte 1) Section 6.5.3.2 FFE5h ACG1FRQ2 Adaptive clock generator1 frequency register (byte 2) Section 6.5.3.3 FFE4h ACGCAPL Adaptive clock generator1 MCLK capture register (low byte) Section 6.5.3.4 FFE3h ACGCAPH Adaptive clock generator1 MCLK capture register (high byte) Section 6.5.3.5 FFE2h ACG1DCTL Adaptive clock generator1 divider control register Section 6.5.3.10 FFE1h ACGCTL Adaptive clock generator control register Section 6.5.3.11 FFE0h CPTCNF1 Codec port interface configuration register 1 Section 6.5.4.1 FFDFh CPTCNF2 Codec port interface configuration register 2 Section 6.5.4.2 FFDEh CPTCNF3 Codec port interface configuration register 3 Section 6.5.4.3 FFDDh CPTCNF4 Codec port interface configuration register 4 Section 6.5.4.4 FFDCh CPTCTL Codec port interface control and status register Section 6.5.4.5 FFDBh CPTADR Codec port interface address register Section 6.5.4.6 FFDAh CPTDATL Codec port interface data register (low-byte) Section 6.5.4.7 FFD9h CPTDATH Codec port interface data register (high-byte) Section 6.5.4.8 FFD8h CPTVSLL Codec port interface valid slots register (low-byte) Section 6.5.4.9 FFD7h CPTVSLH Codec port interface valid slots register (high-byte) Section 6.5.4.10 FFD6h CPTRXCNF2 Codec port receive interface configuration register 2 Section 6.5.4.11 FFD5h CPTRXCNF3 Codec port receive interface configuration register 3 Section 6.5.4.12 Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 87 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com Table 6-3. Memory-Mapped Registers Address Map (continued) ADDRESS MNEMONIC NAME SECTION FFD4h CPTRXCNF4 Codec port receive interface configuration register 4 Section 6.5.4.13 FFD3h Reserved Reserved for future use FFD2h Reserved Reserved for future use FFD1h Reserved Reserved for future use FFD0h Reserved Reserved for future use FFCFh Reserved Reserved for future use FFCEh Reserved Reserved for future use FFCDh Reserved Reserved for future use FFCCh Reserved Reserved for future use FFCBh Reserved Reserved for future use FFCAh P3MSK Mask register for P3 Section 6.5.5.1 FFC9h Reserved Reserved for future use FFC8h Reserved Reserved for future use FFC7h Reserved Reserved for future use FFC6h Reserved Reserved for future use FFC5h Reserved Reserved for future use FFC4h Reserved Reserved for future use FFC3h I2CADR I2C interface address register Section 6.5.6.1 FFC2h I2CDATI I2C interface receive data register Section 6.5.6.2 FFC1h I2CDATO I2C interface transmit data register Section 6.5.6.3 FFC0h I2CCTL I2C interface control and status register Section 6.5.6.4 FFBFh Reserved Reserved for future use FFBEh Reserved Reserved for future use FFBDh Reserved Reserved for future use FFBCh Ch0WrPtrL UBM write pointer (low-byte) (8 bits) Section 6.5.2.8 FFBBh Ch0WrPtrH UBM write pointer (high-byte) (3 bits) Section 6.5.2.9 FFBAh Ch0RdPtrL DMA read pointer (low-byte) (8 bits) Section 6.5.2.10 FFB9h Ch0RdPtrH DMA read pointer (high-byte) (3 bits) Section 6.5.2.11 FFB8h Ch1WrPtrL UBM write pointer (low-byte) (8 bits) Section 6.5.2.8 FFB7h Ch1WrPtrH UBM write pointer (high-byte) (3 bits) Section 6.5.2.9 FFB6h Ch1RdPtrL DMA read pointer (low-byte) (8 bits) Section 6.5.2.10 FFB5h Ch1RdPtrH DMA read pointer (high-byte) (3 bits) Section 6.5.2.11 FFB4h OEPINT USB OUT endpoint interrupt register Section 6.5.7.1 FFB3h IEPINT USB IN endpoint interrupt register Section 6.5.7.2 FFB2h VECINT Interrupt vector register Section 6.5.7.3 FFB1h GLOBCTL Global control register Section 6.5.7.4 FFB0h MEMCFG Memory configuration register Section 6.5.7.5 88 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.1 USB Registers This section describes the memory-mapped registers used for control and operation of the USB functions. This section consists of six registers used for USB functions. 6.5.1.1 USB Function Address Register (USBFADR - Address FFFFh) The USB function address register contains the current setting of the USB device address assigned to the function by the host. After power-on reset or USB reset, the default address is 00h. During enumeration of the function by the host, the MCU should load the assigned address to this register when a USB Set_Address request is received by the control endpoint. Bit 7 6 5 4 3 2 1 0 Mnemonic — FA6 FA5 FA4 FA3 FA2 FA1 FA0 Type R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 — Reserved Reserved for future use 6:0 FA(6:0) Function address The function address bit values are set by the MCU to program the USB device address assigned by the host PC. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 89 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.1.2 USB Status Register (USBSTA - Address FFFEh) The USB status register contains various status bits used for USB operations. Bit 7 6 5 4 3 2 1 0 Mnemonic RSTR SUSR RESR SOF PSOF SETUP — STPOW Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The function reset bit is set to a 1 by hardware in response to the host PC initiating a USB reset to the function. When a USB reset occurs, all of the USB logic blocks, including the SIE, UBM, frame timer, and suspend/resume are automatically reset. The function reset enable (FRSTE) control bit in the USB control register, when set, 7 RSTR Function reset enables the USB reset to reset all remaining TAS1020B logic, except the shadow the ROM (SDW) and the USB function connect (CONT) bits. Also, when the FRSTE control bit is set to a 1, the reset output (RSTO) signal from the TAS1020B device is also active when a USB reset occurs. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The function suspend bit is set to a 1 by hardware when a USB suspend condition is 6 SUSR Function suspend detected by the suspend/resume logic. See Section 2.2.5 for details on the USB suspend and resume operation. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The function resume bit is set to a 1 by hardware when a USB resume condition is 5 RESR Function resume detected by the suspend/resume logic. See Section 2.2.5 for details on the USB suspend and resume operation. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The start-of-frame bit is set to a 1 by hardware when a new USB frame starts. This bit is set when the SOF packet from the host PC is detected, even if the TAS1020B 4 SOF Start-of-frame frame timer is not locked to the host PC frame timer. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The nominal SOF rate is 1 ms. The pseudo start-of-frame bit is set to a 1 by hardware when a USB pseudo SOF occurs. The pseudo SOF is an artificial SOF signal that is generated when the 3 PSOF Pseudo start-of-frame TAS1020B frame timer is not locked to the host PC frame timer. This bit is read only and is cleared when the MCU writes to the interrupt vector register. The nominal pseudo SOF rate is 1 ms. The setup stage transaction bit is set to a 1 by hardware when a successful control endpoint setup stage transaction is completed. Upon completion of the setup stage 2 SETUP Setup stage transaction transaction, the USB control endpoint setup stage data packet buffer should contain a new setup stage data packet. This bit is read-only and is cleared when the MCU writes to the interrupt vector register. 1 — Reserved Reserved for future use The setup stage transaction over-write bit is set to a 1 by hardware when the data in Setup stage transaction the USB control endpoint setup data packet buffer is over-written. This scenario 0 STPOW over-write occurs when the host PC prematurely terminates a USB control transfer by simply starting a new control transfer with a new setup stage transaction. This bit is read-only and is cleared when the MCU writes to the interrupt vector register. 90 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.1.3 USB Interrupt Mask Register (USBIMSK - Address FFFDh) The USB interrupt mask register contains the interrupt mask bits used to enable or disable the generation of interrupts based on the corresponding status bits. Bit 7 6 5 4 3 2 1 0 Mnemonic RSTR SUSR RESR SOF PSOF SETUP — STPOW Type R/W R/W R/W R/W R/W R/W R R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 RSTR Function reset The function reset interrupt mask bit is set to a 1 by the MCU to enable the USB function reset interrupt. 6 SUSR Function suspend The function suspend interrupt mask bit is set to a 1 by the MCU to enable the USB function suspend interrupt. 5 RESR Function resume The function resume interrupt mask bit is set to a 1 by the MCU to enable the USB function resume interrupt. 4 SOF Start-of-frame The start-of-frame interrupt mask bit is set to a 1 by the MCU to enable the USB start-of-frame interrupt. 3 PSOF Pseudo start-of-frame The pseudo start-of-frame interrupt mask bit is set to a 1 by the MCU to enable the USB pseudo start-of-frame interrupt. 2 SETUP Setup stage transaction The setup stage transaction interrupt mask bit is set to a 1 by the MCU to enable the USB setup stage transaction interrupt. 1 — Reserved Reserved for future use 0 STPOW Setup stage transaction The setup stage transaction over-write interrupt mask bit is set to a 1 by the MCU to over-write enable the USB setup stage transaction over-write interrupt. 6.5.1.4 USB Control Register (USBCTL - Address FFFCh) The USB control register contains various control bits used for USB operations. Bit 7 6 5 4 3 2 1 0 Mnemonic CONT FEN RWUP FRSTE — — — SDW_OK Type R/W R/W R/W R/W R R R R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The function connect bit is set to 1 by the MCU to connect the TAS1020B device to the USB. As a result of connecting to the USB, the host PC should enumerate the 7 CONT Function connect function. When this bit is set, the USB data plus pullup resistor (PUR) output signal is enabled, which connects the pullup on the PCB to the TAS1020B 3.3-V supply voltage. When this bit is cleared to 0, the PUR output is in the high-impedance state. This bit is not affected by a USB reset. The function enable bit is set to 1 by the MCU to enable the TAS1020B device to 6 FEN Function enable respond to USB transactions. If this bit is cleared to 0, the UBM ignores all USB transactions. This bit is cleared by a USB reset. The remote wake-up bit is set to 1 by the MCU to request the suspend/resume logic to 5 RWUP Remote wake-up generate resume signaling upstream on the USB. This bit is used to exit a USB low-power suspend state when a remote wake-up event occurs. After initiating the resume signaling by setting this bit, the MCU should clear this bit within 2.5 μs. The function reset enable bit is set to 1 by the MCU to enable the USB reset to reset all internal logic including the MCU. However, the shadow the ROM (SDW) and the 4 FRSTE Function reset enable USB function connect (CONT) bits will not be reset. When this bit is set, the reset output (RSTO) signal from the TAS1020B device is also active when a USB reset occurs. This bit is not affected by USB reset. 3 — Reserved Reserved for future use. 2 — Reserved Reserved for future use. 1 — Reserved Reserved for future use. This bit is used as a confirmation bit to prevent a user from spuriously clearing the 0 SDW_OK SDW bit confirm SDW bit in the MEMCFG register. This bit must be set to 1 before clearing the SDW bit to switch from normal mode to boot mode. This bit is not affected by USB reset. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 91 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.1.5 USB Frame Number Register (Low Byte) (USBFNL - Address FFFBh) The USB frame number register (low byte) contains the least significant byte of the 11-bit frame number value received from the host PC in the start-of-frame packet. Bit 7 6 5 4 3 2 1 0 Mnemonic FN7 FN6 FN5 FN4 FN3 FN2 FN1 FN0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The frame number bit values are updated by hardware each USB frame with the frame number field value received in the USB start-of-frame packet. The frame 7:0 FN(7:0) Frame number number can be used as a time stamp by the USB function. If the TAS1020B frame timer is not locked to the host PC frame timer, then the frame number is incremented from the previous value when a pseudo start-of-frame occurs. 6.5.1.6 USB Frame Number Register (High Byte) (USBFNH - Address FFFAh) The USB frame number register (high byte) contains the most significant 3 bits of the 11-bit frame number value received from the host PC in the start-of-frame packet. Bit 7 6 5 4 3 2 1 0 Mnemonic — — — — — FN10 FN9 FN8 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:3 — Reserved Reserved for future use. The frame number bit values are updated by hardware each USB frame with the frame number field value received in the USB start-of-frame packet. The frame 2:0 FN(10:8) Frame number number can be used as a time stamp by the USB function. If the TAS1020B frame timer is not locked to the host PC frame timer, then the frame number is incremented from the previous value when a pseudo start-of-frame occurs. 6.5.2 DMA Registers This section describes the memory-mapped registers used for the two DMA channels. Each DMA channel has a set of three registers. 6.5.2.1 DMA Time Slot Assignment Register (Low Byte) (DMATSL1 - Address FFF0h) (DMATSL0 - Address FFEAh) Bit 7 6 5 4 3 2 1 0 Mnemonic TSL7 TSL6 TSL5 TSL4 TSL3 TSL2 TSL1 TSL0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 TSL(7:0) Time slot assignment The DMA time slot assignment bits are set to 1 by the MCU to define the codec port interface time slots supported by this DMA channel. 92 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.2.2 DMA Time Slot Assignment Register (High Byte) (DMATSH1 - Address FFEFh) (DMATSH0 - Address FFE9h) Bit 7 6 5 4 3 2 1 0 Mnemonic BPTS1 BPTS0 TSL13 TSL12 TSL11 TSL10 TSL9 TSL8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The bytes per time slot bits are used to define the number of bytes to be transferred for each time slot supported by this DMA channel. 7:6 BPTS(1:0) Bytes per time slot 00b = 1 byte 01b = 2 bytes 10b = 3 bytes 11b = 4 bytes 5:0 TSL(13:8) Time slot assignment The DMA time slot assignment bits are set to 1 by the MCU to define the codec port interface time slots supported by this DMA channel. 6.5.2.3 DMA Control Register (DMACTL1 - Address FFEEh) (DMACTL0 - Address FFE8h) Bit 7 6 5 4 3 2 1 0 Mnemonic DMAEN HSKEN — — EPDIR EPNUM2 EPNUM1 EPNUM0 Type R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before 7 DMAEN DMA enable enabling the DMA channel, all other DMA channel configuration bits must be set to the desired value. This bit is relevant for BULK data transfer in the OUT direction through DMA. MCU must set this bit to a 1 to enable the handshake mode for the data transfer. If MCU sets this bit, MCU has to enable DMA for each received BULK OUT packet. DMA, 6 HSKEN Handshake enable once enabled, transfers the BULK OUT packet to the C-port, disables itself and generates an interrupt to the MCU. If MCU clears this bit, DMA handles the BULK OUT data transfer to the C-port without MCU intervention. For more details, see Section 2.2.7.3.3. 5 — Reserved Reserved for future use 4 — Reserved Reserved for future use The USB endpoint direction bit controls the direction of data transfer by this DMA 3 EPDIR USB endpoint direction channel. The MCU should set this bit to a 1 to configure this DMA channel to be used for a USB IN endpoint. The MCU must clear this bit to a 0 to configure this DMA channel to be used for a USB OUT endpoint. The USB endpoint number bits are set by the MCU to define the USB endpoint number supported by this DMA channel. Keep in mind that endpoint 0 is always used for the control endpoint, which is serviced by the MCU and not a DMA channel. 2:0 EPNUM(2:0) USB endpoint number 001b = Endpoint 1 010b = Endpoint 2 ⋮ 111b = Endpoint 7 000b = Illegal 6.5.2.4 DMA Current Buffer Content Register (Low-Byte) (DMABCNT1L - Address FFF3h) (DMABCNT0LAddress FFEBh) Bit 7 6 5 4 3 2 1 0 Mnemonic Size 7 Size 6 Size 5 Size 4 Size 3 Size 2 Size 1 Size 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register shows the buffer content (bytes) for an ISO OUT endpoint. This register 7:0 Size(7:0) Buffer content is updated every SOF and is stable for the following USB frame, during which the MCU can read it to implement USB audio synchronization. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 93 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.2.5 DMA Current Buffer Content Register (High Byte) (DMABCNT1H - Address FFF4h) (DMABCNT0H - Address FFECh) Bit 7 6 5 4 3 2 1 0 Mnemonic Size 15 Size 14 Size 13 Size 12 Size 11 Size 10 Size 9 Size 8 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register shows the buffer content (bytes) for an ISO OUT endpoint. This register 7:0 Size(15:8) Buffer content is updated every SOF and is stable for the following USB frame, during which the MCU can read it to implement USB audio synchronization. 6.5.2.6 DMA Bulk Packet Count Register (Low Byte) (DMABPCT0 - Address FFF2h) Bit 7 6 5 4 3 2 1 0 Mnemonic PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register shows the number of BULK OUT packets DMA has to handle in 7:0 PCNT (7:0) Bulk packet count handshake mode. MCU writes to this register before enabling the DMA to program the DMA to handle up to 64K BULK packets without MCU intervention. MCU can read this register anytime. 6.5.2.7 DMA Bulk Packet Count Register (High-byte) (DMABPCT1 - Address FFF1h) Bit 7 6 5 4 3 2 1 0 Mnemonic PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register shows the number of BULK OUT packets DMA has to handle in 7:0 PCNT (15:8) Bulk packet count handshake mode. MCU writes to this register before enabling the DMA to program the DMA to handle up to 64K BULK packets without MCU intervention. MCU can read this register anytime. 6.5.2.8 UBM Write Pointer (Low Byte) (Ch0WrPtrL - Address FFBCh) (Ch1WrPtrL - Address FFB8h) Bit 7 6 5 4 3 2 1 0 Mnemonic WRPTR7 WRPTR6 WRPTR5 WRPTR4 WRPTR3 WRPTR2 WRPTR1 WRPTR0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register contains 8 LSB bits of 11-bit UBM write pointer of the isochronous OUT 7:0 WRPTR(7:0) UBM write pointer endpoint buffer. MCU can read this register anytime. This 11-bit UBM write pointer WRPTR can be used in conjunction with the corresponding 11-bit CHn DMA RDPTR to estimate the amount of data in the isochronous OUT endpoint buffer. 94 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.2.9 UBM Write Pointer (High Byte) (Ch0WrPtrH - Address FFBBh) (Ch1WrPtrH - Address FFB7h) Bit 7 6 5 4 3 2 1 0 Mnemonic — — — — — WRPTR10 WRPTR9 WRPTR8 Type — — — — — R R R Default — — — — — 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register contains 3 MSB bits of 11-bit UBM write pointer of the isochronous OUT 2:0 WRPTR(10:8) UBM write pointer endpoint buffer. MCU can read this register anytime. This 11-bit UBM write pointer WRPTR can be used in conjunction with the corresponding 11-bit CHn DMA RDPTR to estimate the amount of data in the isochronous OUT endpoint buffer. 7:3 — Reserved Reserved for future use 6.5.2.10 DMA Read Pointer (Low Byte) (Ch0RdPtrL - Address FFBAh) (Ch1RdPtrL - Address FFB6h) Bit 7 6 5 4 3 2 1 0 Mnemonic RDPTR7 RDPTR6 RDPTR5 RDPTR4 RDPTR3 RDPTR2 RDPTR1 RDPTR0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register contains 8 LSB bits of 11-bit DMA channel n (n can be 0 or 1) read pointer of the Isochronous OUT endpoint buffer. MCU can read this register anytime. 7:0 RDPTR(7:0) DMA read pointer This 11-bit CHn DMA read pointer RDPTR can be used in conjunction with the corresponding 11-bit UBM write pointer WRPTR to estimate the amount of data in the isochronous OUT endpoint buffer. 6.5.2.11 DMA Read Pointer (High Byte) (Ch0RdPtrH - Address FFB9h) (Ch1RdPtrH - Address FFB5h) Bit 7 6 5 4 3 2 1 0 Mnemonic — — — — — WRPTR10 WRPTR9 WRPTR8 Type — — — — — R R R Default — — — — — 0 0 0 BIT MNEMONIC NAME DESCRIPTION This register contains 3 MSB bits of 11-bit channel n (n can be 0 or 1) read pointer of the Isochronous OUT endpoint buffer. MCU can read this register anytime. This 11-bit 2:0 RDPTR(10:8) DMA read pointer CHn DMA RDPTR can be used in conjunction with the corresponding 11-bit UBM write pointer WRPTR to estimate the amount of data in the isochronous OUT endpoint buffer. 7:3 — Reserved Reserved for future use Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 95 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.3 Adaptive Clock Generator Registers This section describes the memory-mapped registers used for two adaptive clock generators for their controls and operations. 6.5.3.1 Adaptive Clock Generator1 Frequency Register (Byte 0) (ACG1FRQ0 - Address FFE7h) The adaptive clock generator frequency register (byte 0) contains the least significant byte of the 24-bit ACG frequency value. The adaptive clock generator frequency registers, ACG1FRQ0, ACG1FRQ1, and ACG1FRQ2, contain the 24-bit value used to program the ACG1 frequency synthesizer. The 24-bit value of these three registers can be used to determine the codec master clock output (MCLKO) signal frequency. The output of the ACG2 frequency synthesizer can also be used to source MCLK0. See Section 2.2.6 for the operation details of the adaptive clock generator including instructions for programming the 24-bit ACG frequency value. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ7 FRQ6 FRQ5 FRQ4 FRQ3 FRQ2 FRQ1 FRQ0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(7:0) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer. 6.5.3.2 Adaptive Clock Generator1 Frequency Register (Byte 1) (ACG1FRQ1 - Address FFE6h) The adaptive clock generator frequency register (byte 1) contains the middle byte of the 24-bit ACG 1 frequency value. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ15 FRQ14 FRQ13 FRQ12 FRQ11 FRQ10 FRQ9 FRQ8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(15:8) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer. 6.5.3.3 Adaptive Clock Generator1 Frequency Register (Byte 2) (ACG1FRQ2 - Address FFE5h) The adaptive clock generator frequency register (byte 2) contains the most significant byte of the 24-bit ACG frequency value. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ23 FRQ22 FRQ21 FRQ20 FRQ19 FRQ18 FRQ17 FRQ16 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(23:16) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer. 96 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte) (ACGCAPL - Address FFE4h) The adaptive clock generator MCLK capture register (low byte) contains the least significant byte of the 16-bit codec master clock (MCLK) signal cycle count that is captured each time a USB start of frame (SOF) occurs. The value of a16-bit free running counter, which is clocked with the MCLK signal, is captured at the beginning of each USB frame. The source of the MCLK signal used to clock the 16-bit timer can be selected to be either the MCLKO signal or the MCLKO2 signal. See Section 2.2.6 for the operation details of the adaptive clock generator. Bit 7 6 5 4 3 2 1 0 Mnemonic CAP7 CAP6 CAP5 CAP4 CAP3 CAP2 CAP1 CAP0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 CAP(7:0) ACG MCLK capture The ACG MCLK capture bit values are updated by hardware each time a USB start of frame occurs. This register contains the least significant byte of the 16-bit value. 6.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte) (ACGCAPH - Address FFE3h) The adaptive clock generator MCLK capture register (high byte) contains the most significant byte of the 16-bit codec master clock (MCLK) signal cycle count that is captured each time a USB start of frame (SOF) occurs. Bit 7 6 5 4 3 2 1 0 Mnemonic CAP15 CAP14 CAP13 CAP12 CAP11 CAP10 CAP9 CAP8 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 CAP(15:8) ACG MCLK capture The ACG MCLK capture bit values are updated by hardware each time a USB start of frame occurs. This register contains the most significant byte of the 16-bit value. 6.5.3.6 Adaptive Clock Generator2 Frequency Register (Byte 0) (ACG2FRQ0 - Address FFF9h) The adaptive clock generator control registers ACG2FRQ0, ACG2FRQ1, and ACG2FRQ2, contain the 24-bit value used to program the ACG2 frequency synthesizer. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ7 FRQ6 FRQ5 FRQ4 FRQ3 FRQ2 FRQ1 FRQ0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(7:0) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer. 6.5.3.7 Adaptive Clock Generator2 Frequency Register (Byte 1) (ACG2FRQ1 - Address FFF8h) Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ15 FRQ14 FRQ13 FRQ12 FRQ11 FRQ10 FRQ9 FRQ8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(15:8) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 97 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.3.8 Adaptive Clock Generator2 Frequency Register (Byte 2) (ACG2FRQ2 - Address FFF7h) Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ23 FRQ22 FRQ21 FRQ20 FRQ19 FRQ18 FRQ17 FRQ16 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(23:16) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer. 6.5.3.9 Adaptive Clock Generator2 Divider Control Register (ACG2DCTL - Address FFF6h) Bit 7 6 5 4 3 2 1 0 Mnemonic DIVM3 DIVM2 DIVM1 DIVM0 - - - - Type R/W R/W R/W R/W R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The divide by M control bits are set by the MCU to program the ACG2 frequency divider. 7:4 DIVM(3:0) Divide by M value 0000b = divide by 1 0001b = divide by 2 ⋮ 1111b = divide by 16 3:0 - Reserved Reserved for future use 6.5.3.10 Adaptive Clock Generator1 Divider Control Register (ACG1DCTL - Address FFE2h) Bit 7 6 5 4 3 2 1 0 Mnemonic DIVM3 DIVM2 DIVM1 DIVM0 - DIVI2 DIVI1 DIVI0 Type R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The divide by M control bits are set by the MCU to program the ACG1 frequency divider. 7:4 DIVM(3:0) Divide by M value 0000b = divide by 1 0001b = divide by 2 ⋮ 1111b = divide by 16 3 - Reserved Reserved for future use The divide by I control bits are set by the MCU to program the MCLKI divider. 000b = divide by 1 2:0 DIVI(2:0) Divide by I value 001b = divide by 2 ⋮ 111b = divide by 8 98 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.3.11 Adaptive Clock Generator Control Register (ACGCTL - Address FFE1h) Bit 7 6 5 4 3 2 1 0 Mnemonic MCLKO2EN MCLKO1EN - MCLKO1S1 MCLKO1S0 DIVEN MCLKO2S1 MCLKO2S0 Type R/W R/W R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION This bit is set to 1 by the MCU to enable the MCLKO2 signal to be an output from the 7 MCLKO2EN MCLKO2 output enable TAS1020B device. If the MCLKO2 signal is not being used, then the MCU can clear this bit to 0 to set the output to logic 0. This bit is set to 1 by the MCU to enable the MCLKO1 signal to be an output from the 6 MCLKO1EN MCLKO1 output enable TAS1020B device. If the MCLKO1 signal is not being used, then the MCU can clear this bit to 0 to set the output to logic 0. 5 - Reserved Reserved for future use This bit in conjunction with MCLKO1S0, selects the source for MCLKO1. See the ACG block diagram (Figure 2-1). MCLKO1S1 MCLKO1S0 MCLKO1 4 MCLKO1S1 MCLKO1 clock select 0 0 acg_clk (after ÷M) x 1 mclki (after ÷I) 1 0 acg2_clk(after ÷M) 3 MCLKO1S0 MCLKO1 clock select See the description above. 2 DIVEN Divider enable The divider enable bit is set to 1 by the MCU to enable the divide-by-I and divide-by-M circuits. This bit in conjunction with MCLKO2S0, selects the MCLKO2. See the ACG block diagram (Figure 2-1). MCLKO2S1 MCLKO2S0 MCLKO2 1 MCLKO2S1 MCLKO2 clock select 0 0 acg_clk (after ÷M) x 1 mclki (after ÷I) 1 0 acg2_clk(after ÷M) 0 MCLKO2S0 MCLKO2 clock select See the description above. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 99 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4 Codec Port Interface Registers This section describes the memory-mapped registers used for the codec port interface control and operation. The codec port interface has a set of ten registers. Note that the four codec port interface configuration registers can only be written to by the MCU if the codec port enable bit (CPTEN) in the global control register is a 0 - the codec port is disabled. 6.5.4.1 Codec Port Interface Configuration Register 1 (CPTCNF1 - Address FFE0h) The codec port interface configuration register 1 is used to store various control bits for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic NTSL4 NTSL3 NTSL2 NTSL1 NTSL0 MODE2 MODE1 MODE0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The number of time slots bits are set by the MCU to program the number of time slots per audio frame. 7:3 NTSL(4:0) Number of time slots 00000b = Illegal 00001b = 2 time slots per frame ⋮ 01101 = 14 time slots per frame The mode select bits are set by the MCU to program the codec port interface mode of operation. In addition to selecting the desired mode of operation, the MCU must also program the other configuration registers to obtain the correct serial interface format. 000b = mode 0 - General-purpose mode 001b = mode 1 - AIC mode 2:0 MODE(2:0) Mode select 010b = mode 2 - AC ’97 1.x mode 011b = mode 3 - AC ’97 2.x mode 100b = mode 4 - I2S mode - 1 OUT and 2 IN at same frequency 101b = mode 5 - I2S mode - 1 OUT and 1 IN at different frequencies 110b = Reserved 111b = Reserved 100 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.2 Codec Port Interface Configuration Register 2 (CPTCNF2 - Address FFDFh) The codec port interface configuration register 2 is used to store various control bits for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic TSL0L1 TSL0L0 BPTSL2 BPTSL1 BPTSL0 TSLL2 TSLL1 TSLL0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The time slot 0 Length bits are set by the MCU to program the number of serial clock (CSCLK) cycles for time slot 0. 7:6 TSL0L(1:0) Time slot 0 length 00b = CSCLK cycles for time slot 0 same as other time slots 01b = 8 CSCLK cycles for time slot 0 10b = 16 CSCLK cycles for time slot 0 11b = 32 CSCLK cycles for time slot 0 The data bits per time slot bits are set by the MCU to program the number of data bits per audio time slot. Note that this value in not used for the secondary communication address and data time slots. 000b = 8 data bits per time slot 001b = 16 data bits per time slot 5:3 BPTSL(2:0) Data bits per time slot 010b = 18 data bits per time slot 011b = 20 data bits per time slot 100b = 24 data bits per time slot 101b = 32 data bits per time slot 110b = reserved 111b = reserved The time slot length bits are set by the MCU to program the number of serial clock (CSCLK) cycles for all time slots except time slot 0. 000b = 8 CSCLK cycles per time slot 001b = 16 CSCLK cycles per time slot 2:0 TSLL(2:0) Time slot length 010b = 18 CSCLK cycles per time slot 011b = 20 CSCLK cycles per time slot 100b = 24 CSCLK cycles per time slot 101b = 32 CSCLK cycles per time slot 110b = reserved 111b = reserved Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 101 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4.3 Codec Port Interface Configuration Register 3 (CPTCNF3 - Address FFDEh) The codec port interface configuration register 3 is used to store various control bits for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic DDLY TRSEN CSCLKP CSYNCP CSYNCL BYOR CSCLKD CSYNCD Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 1 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The data delay bit is set to a 1 by the MCU to program a one CSCLK cycle delay of 7 DDLY Data delay the serial data output and input signals in reference to the leading edge of the CSYNC signal. The MCU must clear this bit to a 0 for no delay between these signals. The 3-state enable bit is set to a 1 by the MCU to program the hardware to set the serial data output signal to the high-impedance state for the time slots during the 6 TRSEN 3-State enable audio frame that are not valid. The MCU must clear this bit to a 0 to program the hardware to use zero-padding for the serial data output signal for time slots during the audio frame that are not valid. The CSCLK polarity bit is used by the MCU to program the clock edge used for the codec port interface frame sync (CSYNC) output signal, codec port interface serial data output (CDATO) signal and codec port interface serial data Input (CDATI) signal. When this bit is set to a 1, the CSYNC signal is generated with the negative edge of the codec port interface serial clock (CSCLK) signal. Also, when this bit is set to a 1, 5 CSCLKP CSCLK polarity the CDATO signal is generated with the negative edge of the CSCLK signal and the CDATI signal is sampled with the positive edge of the CSCLK signal. When this bit is cleared to a 0, the CSYNC signal is generated with the positive edge of the CSCLK signal. Also, when this bit is cleared to a 0, the CDATO signal is generated with the positive edge of the CSCLK signal and the CDATI signal is sampled with the negative edge of the CSCLK signal. The CSYNC polarity bit is set to a 1 by the MCU to program the polarity of the codec 4 CSYNCP CSYNC polarity port interface frame sync (CSYNC) output signal to be active high. The MCU must clear this bit to a 0 to program the polarity of the CSYNC output signal to be active low. The CSYNC length bit is set to a 1 by the MCU to program the length of the codec 3 CSYNCL CSYNC length port interface frame sync (CSYNC) output signal to be the same number of CSCLK cycles as time slot 0. The MCU must clear this bit to a 0 to program the length of the CSYNC output signal to be one CSCLK cycle. The byte order bit is used by the MCU to program the byte order for the data moved by the DMA between the USB endpoint buffer and the codec port interface. When this 2 BYOR Byte order bit is set to a 1, the byte order of each audio sample is reversed when the data is moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the byte order of the each audio sample is unchanged. The CSCLK direction bit is set to a 1 by the MCU to program the direction of the codec port interface serial clock (CSCLK) signal as an input to the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the CSCLK signal as an 1 CSCLKD CSCLK direction output from the TAS1020B device. This bit can optionally be set to 1 to select 'Input' only when General Purpose Mode 1 has been selected. The CSYNC direction bit is set to a 1 by the MCU to program the direction of the codec port interface frame sync (CSYNC) signal as an input to the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the CSYNC signal as an 0 CSYNCD CSYNC direction output from the TAS1020B device. This bit can optionally be set to 1 to select 'Input' only when General Purpose Mode 1 has been selected. 102 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.4 Codec Port Interface Configuration Register 4 (CPTCNF4 - Address FFDDh) The codec port interface configuration register 4 is used to store various control bits for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic ATSL3 ATSL2 ATSL1 ATSL0 CPTBLK DIVB2 DIVB1 DIVB0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The command/status address/data time slot bits are set by the MCU to program the time slots to be used for the secondary communication address and data values. For the AC ’97 modes of operation, this value must be set to 0001b which results in time slot 1 being used for the address and time slot 2 being used for the data. For the AIC Command/status and general-purpose modes of operation, the same time slot is used for both address 7:4 ATSL(3:0) address/data time slot and data. For the AIC mode of operation this value must be set to 0111b which results in time slot 7 being used for both the address and data. 0000b = time slot 0 0001b = time slot 1 ⋮ 1111b = time slot 15 This bit is used when C-port is in Mode 0. If this bit is cleared to 0, the C-port 3 CptBlk C-port bulk mode sync/clocks are free running once C-port is enabled. If this bit is set to 1, DMA controls the C-port sync/clocks. The sync/clocks are active only when valid data is present in a codec frame. The divide by B control bits are set by the MCU to program the divide ratio used to derive CSCLK from MCLKO. 000b = CSCLK output disabled 001b = divide by 2 2:0 DIVB(2:0) Divide by B value 010b = divide by 3 011b = divide by 4 100b = divide by 5 101b = divide by 6 110b = divide by 7 111b = divide by 8 Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 103 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4.5 Codec Port Interface Control and Status Register (CPTCTL - Address FFDCh) The codec port interface control and status register contains various control and status bits used for the codec port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic RXF RXIE TXE TXIE — CID1 CID0 CRST Type R R/W R R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The receive data register full bit is set to a 1 by hardware when a new data value has been received into the receive data register from the codec device. This bit is read 7 RXF Receive data register full only and is cleared to a 0 by hardware when the MCU reads the new value from the receive data register. Note that when the MCU writes to the interrupt vector register, the codec port interface receive data register full interrupt is cleared but this status bit is not cleared at that time. 6 RXIE Receive interrupt enable The receive interrupt enable bit is set to a 1 by the MCU to enable the C-port receive data register full interrupt. The transmit data register empty bit is set to a 1 by hardware when the data value in the transmit data register has been sent to the codec device. This bit is read only and 5 TXE Transmit data register is cleared to a 0 by hardware when a new data byte is written to the transmit data empty register by the MCU. Note that when the MCU writes to the interrupt vector register, the codec port interface transmit data register empty interrupt is cleared but this status bit is not cleared at that time. 4 TXIE Transmit interrupt The transmit interrupt enable bit is set to a 1 by the MCU to enable the codec port enable interface transmit data register empty interrupt. 3 — Reserved Reserved for future use The codec ID bits are used by the MCU to select between the primary codec device and the secondary codec device for secondary communication in the AC ’97 modes of 2:1 CID(1:0) Codec ID operation. When the bits are cleared to 00, the primary codec device is selected. When the bits are set to 01, 10 or 11, the secondary codec device is selected. Note that when only a primary codec device is connected to the TAS1020B, the bits remain cleared to 00. The codec reset bit is used by the MCU to control the codec port interface reset (CRESET) output signal from the TAS1020B device. When this bit is set to a 1, the CRESET signal is a high. When this bit is cleared to a 0, the CRESET signal is active 0 CRST Codec reset low. At power up this bit is cleared to a 0, which means the CRESET output signal is active low and remains active low until the MCU sets this bit to a 1. In I2S mode 5, this signal is not available because the CRESET pin becomes SCLK2, which is used to input data from a codec. 104 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.6 Codec Port Interface Address Register (CPTADR - Address FFDBh) The codec port interface address register contains the read/write control bit and address bits used for secondary communication between the TAS1020B MCU and the codec device. For write transactions to the codec, the 8-bit value in this register is sent to the codec in the designated time slot and appropriate bit locations. Note that for the different modes of operation, the number of address bits and the bit location of the read/write bit is different. For example, the AC ’97 modes require 7 address bits and the bit location of the read/write bit to be the most significant bit. The AIC mode only requires 4 address bits and the bit location of the read/write bit to be bit 13 of the 16-bits in the time slot. The MCU must load the read/write and address bits to the correct bit locations within this register for the different modes of operation. Shown below are the read/write control bit and address bits for the AC ’97 mode of operation. Bit 7 6 5 4 3 2 1 0 Mnemonic R/W A6 A5 A4 A3 A2 A1 A0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The command/status read/write control bit value is set by the MCU to program the 7 R/W Command/status type of secondary communication transaction to be done. This bit must be set to a 1 read/write control by the MCU for a read transaction and cleared to a 0 by the MCU for a write transaction. The command/status address value is set by the MCU to program the codec device 6:0 A(6:0) Command/status control/status register address to be accessed during the read or write transaction. address The command/status address value is updated by hardware with the control/status register address value received from the codec device for read transactions. 6.5.4.7 Codec Port Interface Data Register (Low Byte) (CPTDATL - Address FFDAh) The codec port interface data register (low byte) contains the least significant byte of the 16-bit command or status data value used for secondary communication between the TAS1020B MCU and the codec device. Note that for general-purpose mode or AIC mode only an 8-bit data value is used for secondary communication. Bit 7 6 5 4 3 2 1 0 Mnemonic D7 D6 D5 D4 D3 D2 D1 D0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The command/status data value is set by the MCU with the command data to be 7:0 D(7:0) Command/status data transmitted to the codec device for write transactions. The command/status data value is updated by hardware with the status data received from the codec device for read transactions. 6.5.4.8 Codec Port Interface Data Register (High Byte) (CPTDATH - Address FFD9h) The codec port interface data register (high byte) contains the most significant byte of the 16-bit command or status data value used for secondary communication between the TAS1020B MCU and the codec device. This register is not used for general-purpose mode or AIC mode since these modes only support an 8-bit data value for secondary communication. Bit 7 6 5 4 3 2 1 0 Mnemonic D15 D14 D13 D12 D11 D10 D9 D8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The command/status data value is set by the MCU with the command data to be 7:0 D(15:8) Command/status data transmitted to the codec device for write transactions. The command/status data value is updated by hardware with the status data received from the codec device for read transactions. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 105 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4.9 Codec Port Interface Valid Time Slots Register (Low Byte) (CPTVSLL - Address FFD8h) The codec port interface valid time slots register (low byte) contains the control bits used to specify which time slots in the audio frame contain valid data. This register is only used in the AC ’97 modes of operation. Bit 7 6 5 4 3 2 1 0 Mnemonic VTSL8 VTSL9 VTSL10 VTSL11 VTSL12 — — — Type R/W R/W R/W R/W R/W R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The valid time slot bits are set to a 1 by the MCU to define which time slots in the 7:3 VTSL(8:12) Valid time slot audio frame contain valid data. The MCU must clear to a 0 the bits corresponding to time slots that do not contain valid data. Note that bits 7 to 3 of this register correspond to time slots 8 to 12. 2:0 — Reserved Reserved for future use 6.5.4.10 Codec Port Interface Valid Time Slots Register (High Byte) (CPTVSLH - Address FFD7h) The codec port interface valid time slots register (high byte) contains the control bits used to specify which time slots in the audio frame contain valid data. In addition the valid frame, primary codec ready and secondary codec ready bits are contained in this register. This register is only used in the AC ’97 modes of operation. Bit 7 6 5 4 3 2 1 0 Mnemonic VF PCRDY SCRDY VTSL3 VTSL4 VTSL5 VTSL6 VTSL7 Type R/W R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The valid frame bit is set to a 1 by the MCU to indicate that the current audio frame 7 VF Valid frame contains at least one time slot with valid data. The MCU must clear this bit to a 0 to indicate that the current audio frame does not contain any time slots with valid data. The primary codec ready bit is updated by hardware each audio frame based on the 6 PCRDY Primary codec ready value of bit 15 in time slot 0 of the incoming serial data from the primary codec. This bit is set to a 1 to indicate the primary codec is ready for operation. The secondary codec ready bit is updated by hardware each audio frame based on 5 SCRDY Secondary codec ready the value of bit 15 in time slot 0 of the incoming serial data from the secondary codec. This bit is set to a 1 to indicate the secondary codec is ready for operation. Note that this bit is only used if a secondary codec is connected to the TAS1020B device. The valid time slot bits are set to a 1 by the MCU to define which time slots in the 4:0 VTSL(3:7) Valid time slot audio frame contain valid data. The MCU must clear to a 0 the bits corresponding to time slots that do not contain valid data. Note that bits 4 to 0 of this register correspond to time slots 3 to 7. 106 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.11 Codec Port Receive Interface Configuration Register 2 (CPTRXCNF2 - Address FFD6h) The codec port receive interface configuration register2 is only used in I2S Mode 5. Bit 7 6 5 4 3 2 1 0 Mnemonic - - BPTSL2 BPTSL1 BPTSL0 TSLL2 TSLL1 TSLL0 Type R R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:6 — Reserved Reserved for future use The data bits per time slot bits are set by the MCU to program the number of data bits per audio time slot. Note that this value in not used for the secondary communication address and data time slots. 000b = 8 data bits per time slot 001b = 16 data bits per time slot 5:3 BPTSL(2:0) Data bits per time slot. 010b = 18 data bits per time slot 011b = 20 data bits per time slot 100b = 24 data bits per time slot 101b = 32 data bits per time slot 110b = reserved 111b = reserved The time slot length bits are set by the MCU to program the number of serial clock (SCLK2) cycles for all time slots. 000b = 8 SCLK2 cycles per time slot 001b = 16 SCLK2 cycles per time slot 2:0 TSLL(2:0) Time slot length 010b = 18 SCLK2 cycles per time slot 011b = 20 SCLK2 cycles per time slot 100b = 24 SCLK2 cycles per time slot 101b = 32 SCLK2 cycles per time slot 110b = reserved 111b= reserved Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 107 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.4.12 Codec Port Receive Interface Configuration Register 3 (CPTRXCNF3 - Address FFD5h) The codec port receive interface configuration register3 is only used in I2S Mode 5. Bit 7 6 5 4 3 2 1 0 Mnemonic DDLY TRSEN CSCLKP CSYNCP CSYNCL BYOR CSCLKD CSYNCD Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 1 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The data delay bit is set to 1 by the MCU to program a one SCLK2 cycle delay of the 7 DDLY Data delay serial data output and input signals in reference to the leading edge of the LRCK2 signal. The MCU must clear this bit to a 0 for no delay between these signals. The 3-state enable bit is set to a 1 by the MCU to program the hardware to set the serial data output signal to the high-impedance state for time slots during the audio 6 TRSEN 3-state enable frame that are not valid. The MCU must clear this bit to a 0 to program the hardware to use zero-padding for the serial data output signal for time slots during the audio frame that are not valid. The CSCLKP polarity bit is used by the MCU to program the clock edge used for the codec port interface frame sync (LRCK2) output signal and codec port interface serial data input (CDAT1) signal. When this bit is set to a 1, the LRCK2 signal is generated 5 CSCLKP CSCLK polarity with the negative edge of the codec port interface serial clock (SCLK2) signal. Also, when this bit is set a 1, the CDATI signal is sampled with the positive edge of the SCLK2 signal. When this bit is cleared to 0, the LRCK2 signal is generated with the positive edge of SCLK2 and the CDATI signal is sampled with the negative edge of the SCLK2 signal. The CSYNCP polarity bit is set to a 1 by the MCU to program the polarity of the codec 4 CSYNCP CSYNC polarity port interface frame sync (LRCK2) output signal to be active high. The MCU must clear this bit to a 0 to program the polarity of the LRCK2 output signal to be active low. The CSYNCL polarity bit is set to a 1 by the MCU to program the length of the codec 3 CSYNCL CSYNC length port interface frame sync (LRCK2) output signal to be the same number of SCLK2 cycles as time slot 0. The MCU must clear this bit to a 0 to program the length of the LRCK2 output signal to be one SCLK2 cycle. The byte order bit is used by the MCU to program the byte order for the data moved by the DMA between the USB endpoint buffer and the codec port interface. When this 2 BYOR Byte order bit is set to a 1, the byte order of each audio sample is reversed when the data is moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the byte order of the each audio sample is unchanged. The SCLK2 direction bit is set to a 1 by the MCU to program the direction of the codec 1 CSCLKD CSCLK direction port interface serial clock (SCLK2) signal as an input of the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the CSCLK signal as an output from the TAS1020B device. The SCLK2 direction bit is set to a 1 by the MCU to program the direction of the codec 0 CSYNCD CSYNC direction port interface frame sync (LRCK2) signal as an input of the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the LRCK2 signal as an output from the TAS1020B device. 108 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.4.13 Codec Port Receive Interface Configuration Register 4 (CPTRXCNF4 - Address FFD4h) The codec port receive interface configuration register 4 is only used in I2S Mode 5. Bit 7 6 5 4 3 2 1 0 Mnemonic - - - - - DIVB22 DIVB21 DIVB20 Type R R R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:3 — Reserved Reserved for future use The divide by B2 control bits are set by the MCU to program the divide ratio used to derive SCLK2 from MCLKO2. 000b = SCLK2 output disabled 001b = divide by 2 2:0 DIVB2(2:0) Divide by B2 value 010b = divide by 3 011b = divide by 4 100b = divide by 5 101b = divide by 6 110b = divide by 7 111b = divide by 8 6.5.5 P3 Mask Register Mask register for P3 to enable the wake-up function for these pins when the device is in low-power mode. 6.5.5.1 P3 Mask Register (P3MSK - Address FFCAh) Bit 7 6 5 4 3 2 1 0 Mnemonic P3MSK7 P3MSK6 P3MSK5 P3MSK4 P3MSK3 P3MSK2 P3MSK1 P3MSK0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 P3MSK(7:0) 0 = Unmasked 1 = Masked Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 109 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.6 I2C Interface Registers This section describes the memory-mapped registers used for the I2C Interface control and operation. The I2C interface has a set of four registers. See Section 2.2.14 for the operation details of the I2C interface. 6.5.6.1 I2C Interface Address Register (I2CADR - Address FFC3h) The I2C interface address register contains the 7-bit I2C slave device address and the read/write transaction control bit. Bit 7 6 5 4 3 2 1 0 Mnemonic A6 A5 A4 A3 A2 A1 A0 RW Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The address bit values are set by the MCU to program the 7-bit I2C slave address of the device to be accessed. Each I2 7:1 A(6:0) Address C slave device must have a unique address on the I2C bus. This address is used to identify the device on the bus to be accessed and is not the internal memory address to be accessed within the device. The read/write control bit value is set by the MCU to program the type of I2C 0 RW Read/write control transaction to be done. This bit must be set to a 1 by the MCU for a read transaction and cleared to a 0 by the MCU for a write transaction. 6.5.6.2 I2C Interface Receive Data Register (I2CDATI - Address FFC2h) The I2C interface receive data register contains the most recent data byte received from the slave device. Bit 7 6 5 4 3 2 1 0 Mnemonic RXD7 RXD6 RXD5 RDXD4 RXD3 RXD2 RXD1 RXD0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 RXD(7:0) Receive data The receive data byte value is updated by hardware for each data byte received from the I2C slave device. 6.5.6.3 I2C Interface Transmit Data Register (I2CDATO - Address FFC1h) The I2C interface transmit data register contains the next address or data byte to be transmitted to the slave device in accordance with the protocol. Note that for both read and write transactions, the internal register or memory address of the slave device being accessed must be transmitted to the slave device. Bit 7 6 5 4 3 2 1 0 Mnemonic TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 Type W W W W W W W W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 TXD(7:0) Transmit data The transmit data byte value is set by the MCU for each address or data byte to be transmitted to the I2C slave device. 110 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.6.4 I2C Interface Control and Status Register (I2CCTL - Address FFC0h) The I2C interface control and status register contains various control and status bits used for the I2C interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic RXF RXIE ERR FRQ TXE TXIE STPRD STPWR Type R R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The receive data register full bit is set to a 1 by hardware when a new data byte has been received into the receive data register from the slave device. This bit is read only 7 RXF Receive data register full and is cleared to a 0 by hardware when the MCU reads the new byte from the receive data register. Note that when the MCU writes to the interrupt vector register, the I2C receive data register full interrupt is cleared but this status bit is not cleared at that time. 6 RXIE Receive interrupt enable The receive interrupt enable bit is set to a 1 by the MCU to enable the I2C receive data register full interrupt. 5 ERR Error condition The error condition bit is set to a 1 by hardware when the slave device does not respond. This bit is read/write and can only be cleared by the MCU. The frequency select bit is used by the MCU to program the I2C serial clock (SCL) 4 FRQ Frequency select output signal frequency. A value of 0 sets the SCL frequency to 100 kHz and a value of 1 sets the SCL frequency to 400 kHz. The transmit data register empty bit is set to a 1 by hardware when the data byte in the transmit data register has been sent to the slave device. This bit is read only and 3 TXE Transmit data register is cleared to a 0 by hardware when a new data byte is written to the transmit data empty register by the MCU. Note that when the MCU writes to the interrupt vector register, the I2C transmit data register empty interrupt is cleared but this status bit is not cleared at that time. 2 TXIE Transmit interrupt The transmit interrupt enable bit is set to a 1 by the MCU to enable the I2C transmit enable data register empty interrupt. The stop read transaction bit is set to a 1 by the MCU to enable the hardware to 1 STPRD Stop - read transaction generate a stop condition on the I2C bus after the next data byte from the slave device is received into the receive data register. The MCU must clear this bit to a 0 after the read transaction has concluded. The stop write transaction bit is set to a 1 by the MCU to enable the hardware to 0 STPWR Stop - write transaction generate a stop condition on the I2C bus after the data byte in the transmit data register is sent to the slave device. The MCU must clear this bit to a 0 after the write transaction has concluded. Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 111 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.7 Miscellaneous Registers This section describes the memory-mapped registers used for the control and operation of miscellaneous functions in the TAS1020B device. The registers include the USB OUT endpoint interrupt register, the USB IN endpoint interrupt register, the interrupt vector register, the global control register, and the memory configuration register. 6.5.7.1 USB OUT endpoint Interrupt Register (OEPINT - Address FFB4h) The USB OUT endpoint interrupt register contains the interrupt pending status bits for the USB OUT endpoints. These bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for diagnostic purposes only. Bit 7 6 5 4 3 2 1 0 Mnemonic OEPI7 OEPI6 OEPI5 OEPI4 OEPI3 OEPI2 OEPI1 OEPI0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The OUT endpoint interrupt status bit for a particular USB OUT endpoint is set to a 1 by the UBM when a successful completion of a transaction occurs to that OUT 7:0 OEPI(7:0) OUT endpoint interrupt endpoint. When a bit is set, an interrupt to the MCU is generated and the corresponding interrupt vector results. The status bit is cleared when the MCU writes to the interrupt vector register. These bits do not apply to isochronous OUT endpoints. 6.5.7.2 USB IN endpoint Interrupt Register (IEPINT - Address FFB3h) The USB IN endpoint interrupt register contains the interrupt pending status bits for the USB IN endpoints. These bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for diagnostic purposes only. Bit 7 6 5 4 3 2 1 0 Mnemonic IEPI7 IEPI6 IEPI5 IEPI4 IEPI3 IEPI2 IEPI1 IEPI0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The IN endpoint interrupt status bit for a particular USB IN endpoint is set to a 1 by the UBM when a successful completion of a transaction occurs to that IN endpoint. When 7:0 IEPI(7:0) IN endpoint interrupt a bit is set, an interrupt to the MCU is generated and the corresponding interrupt vector results. The status bit is cleared when the MCU writes to the interrupt vector register. These bits do not apply to isochronous IN endpoints. 112 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011 6.5.7.3 Interrupt Vector Register (VECINT - Address FFB2h) The interrupt vector register contains a 6-bit vector value that identifies the interrupt source for the INT0 input to the MCU. All of the TAS1020B internal interrupt sources and the external interrupt input to the device are ORed together to generate the internal INT0 signal to the MCU. When there is not an interrupt pending, the interrupt vector value is set to 24h. To clear any interrupt and update the interrupt vector value to the next pending interrupt, the MCU should simply write any value to this register. The interrupt priority is fixed in order, ranging from vector value 1Fh with the highest priority to vector value 00h with the lowest priority. An exception to this priority is the control endpoint EP0 which has top priority. Bit 7 6 5 4 3 2 1 0 Mnemonic — — IVEC5 IVEC4 IVEC3 IVEC2 IVEC1 IVEC0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 — Reserved Reserved for future use 6 — Reserved Reserved for future use 00h = USB OUT endpoint 0 10h = USB setup stage transaction 01h = USB OUT endpoint 1 over-write 02h = USB OUT endpoint 2 11h = Reserved 03h = USB OUT endpoint 3 12h = USB setup stage transaction 04h = USB OUT endpoint 4 13h = USB pseudo start-of-frame 05h = USB OUT endpoint 5 14h = USB start-of-frame 06h = USB OUT endpoint 6 15h = USB function resume 07h = USB OUT endpoint 7 16h = USB function suspend 5:0 IVEC(5:0) Interrupt vector 08h = USB IN endpoint 0 17h = USB function reset 09h = USB IN endpoint 1 18h = C-port receive data register full 0Ah = USB IN endpoint 2 19h = C-port transmit data register empty 0Bh = USB IN endpoint 3 1Ah = Reserved 0Ch = USB IN endpoint 4 1Bh = Reserved 0Dh = USB IN endpoint 5 1Ch = I2C receive data register full 0Eh = USB IN endpoint 6 1Dh = I2C transmit data register empty 0Fh = USB IN endpoint 7 1Eh = Reserved1Fh = External interrupt input 20h = DMA Ch.0 interrupt 24h = No interrupt pending 21h = DMA Ch.1 interrupt 25h - 3Fh = Reserved 22h - 23h = Reserved Copyright © 2002–2011, Texas Instruments Incorporated MCU Memory and Memory-Mapped Registers 113 Submit Documentation Feedback Product Folder Link(s): TAS1020B TAS1020B SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com 6.5.7.4 Global Control Register (GLOBCTL - Address FFB1h) The global control register contains various global control bits for the TAS1020B device. Bit 7 6 5 4 3 2 1 0 Mnemonic MCUCLK XINTEN P1PUDIS VREN RESET LPWR P3PUDIS CPTEN Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION The MCU clock select bit is used by the MCU to program the clock frequency to be used for the MCU operation. 7 MCUCLK MCU clock select 0b = 12 MHz 1b = 24 MHz POR (Power On Reset) value is 0 (12 MHz). Setting this bit to 1 will change MCU clock frequency to 24 MHz. But, once set, this bit can only be cleared by master reset. 6 XINTEN External interrupt enable The external interrupt enable bit is set to a 1 by the MCU to enable the use of the external interrupt input to the TAS1020B device. 5 P1PUDIS Pullup resistor disable If set to 1, disables on-chip pullup resistors on P1 GPIO pins. 4 VREN VREN Memory-mapped GPIO pin 3 RESET RESET Memory-mapped GPIO pin The low power mode disable bit is used by the MCU to put the TAS1020B into a 2 LPWR Low power mode semi-low power state. When this bit is cleared to a 0, all USB functional blocks are powered down. For normal operation, the MCU must set this bit to a 1. 1 P3PUDIS Pullup resistor disable If set to 1, disables on-chip pullup resistors on P3 GPIO pins. The codec port enable bit is set to a 1 by the MCU to enable the operation of the 0 CPTEN Codec port enable codec port interface. Note that the codec port interface configuration registers must be fully programmed before this bit is set by the MCU. 6.5.7.5 Memory Configuration Register (MEMCFG - Address FFB0h) The memory configuration register contains various bits pertaining to the memory configuration of the TAS1020B device. Bit 7 6 5 4 3 2 1 0 Mnemonic MEMTYP CODESZ1 CODESZ0 REV3 REV2 REV1 REV0 SDW Type R R R R R R R R/W Default 1 0 1 0 0 0 1 0 BIT MNEMONIC NAME DESCRIPTION The code memory type bit identifies if the type of memory used for the application 7 MEMTYP Code memory type program code space is ROM or RAM. For the TAS1020B, an 8K byte RAM is used and this bit is tied to 1. The code space size bits identify the size of the application program code memory space. For the TAS1020B, an 8K byte RAM is used and these bits are tied to 01b. 6:5 CODESZ(1:0) Code space size 00b = 4K bytes 01b = 8K bytes 10b = 16K bytes 11b = 32K bytes The IC revision bits identify the revision of the IC. 0000b = Rev. - 4:1 REV(3:0) IC revision 0001b = Rev. A ⋮ 1111b = Rev. F The shadow the boot ROM bit is set to a 1 by the MCU to switch the MCU memory 0 SDW Shadow the boot ROM configuration from boot loader mode to normal operating mode. This must occur after completion of the download of the application program code by the boot ROM. See the SDW protection bit in USBCTL register. 114 MCU Memory and Memory-Mapped Registers Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS1020B PACKAGE OPTION ADDENDUM www.ti.com 23-Nov-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TAS1020BPFB NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS1020BPFBG4 NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS1020BPFBR NRND TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TAS1020BPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TAS1020BPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS1020BPFBR TQFP PFB 48 1000 336.6 336.6 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Individual Switch Controls Extremely Low Input Current Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information These triple 2-channel CMOS analog multiplexers/demultiplexers are designed for 2-V to 5.5-V VCC operation. The ’LV4053A devices handle both analog and digital signals. Each channel permits signals with amplitudes up to 5.5 V (peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74LV4053AN SN74LV4053AN QFN − RGY Reel of 1000 SN74LV4053ARGYR LW053A SOIC D Tube of 40 SN74LV4053AD − LV4053A Reel of 2500 SN74LV4053ADR 40°C to 85°C SOP − NS Reel of 2000 SN74LV4053ANSR 74LV4053A −SSOP − DB Reel of 2000 SN74LV4053ADBR LW053A Tube of 90 SN74LV4053APW TSSOP − PW Reel of 2000 SN74LV4053APWR LW053A Reel of 250 SN74LV4053APWT TVSOP − DGV Reel of 2000 SN74LV4053ADGVR LW053A 55°C to 125°C CDIP − J Tube of 25 SNJ54LV4053AJ SNJ54LV4053AJ −CFP − W Tube of 150 SNJ54LV4053AW SNJ54LV4053AW † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright © 2005, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 2Y1 2Y0 3Y1 3-COM 3Y0 INH GND GND VCC 2-COM 1-COM 1Y1 1Y0 A B C SN54LV4053A . . . J OR W PACKAGE SN74LV4053A . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) SN74LV4053A . . . RGY PACKAGE (TOP VIEW) 1 16 8 9 2 3 4 5 6 7 15 14 13 12 11 10 2-COM 1-COM 1Y1 1Y0 A B 2Y0 3Y1 3-COM 3Y0 INH GND 2Y1 C V GND CC SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS ON CHANNELS INH C B A L L L L 1Y0, 2Y0, 3Y0 L L L H 1Y1, 2Y0, 3Y0 L L H L 1Y0, 2Y1, 3Y0 L L H H 1Y1, 2Y1, 3Y0 L H L L 1Y0, 2Y0, 3Y1 L H L H 1Y1, 2Y0, 3Y1 L H H L 1Y0, 2Y1, 3Y1 L H H H 1Y1, 2Y1, 3Y1 H X X X None logic diagram (positive logic) 1Y0 1Y1 2Y0 2Y1 3Y0 1-COM INH B A 3-COM 3Y1 2-COM C 11 10 9 6 15 14 12 13 2 1 5 3 4 SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA I/O diode current, IIOK (VIO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 5) SN54LV4053A SN74LV4053A UNIT MIN MAX MIN MAX VCC Supply voltage 2‡ 5.5 2‡ 5.5 V VCC = 2 V 1.5 1.5 V High level input voltage control inputs VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VIH High-voltage, V VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VCC = 2 V 0.5 0.5 V Low level input voltage control inputs VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VIL Low-voltage, V VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3 VI Control input voltage 0 5.5 0 5.5 V VIO Input/output voltage 0 VCC 0 VCC V VCC = 2.3 V to 2.7 V 200 200 Δt/Δv Input transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V VCC = 4.5 V to 5.5 V 20 20 TA Operating free-air temperature −55 125 −40 85 °C ‡ With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST V TA = 25°C SN54LV4053A SN74LV4053A UNIT CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX IT = 2 mA, 2.3 V 41 180 225 225 ron On-state T , VI = VCC or GND, VINH = VIL on 3 V 30 150 190 190 Ω switch resistance (see Figure 1) 4.5 V 23 75 100 100 IT = 2 mA, 2.3 V 139 500 600 600 ron(p) Peak on-state resistance on VI = VCC to GND, 3 V 63 180 225 225 Ω VINH = VIL 4.5 V 35 100 125 125 Difference in IT = 2 mA, 2.3 V 2 30 40 40 Δron on-state resistance on VI = VCC to GND, 3 V 1.6 20 30 30 Ω between switches VINH = VIL 4.5 V 1.3 15 20 20 II Control input current VI = 5.5 V or GND 0 to 5.5 V ±0.1 ±1 ±1 μA IS(off) Off-state switch leakage current VI = VCC and VO = GND, or VI = GND and VO = VCC, VINH = VIH (see Figure 2) 5.5 V ±0.1 ±1 ±1 μA IS(on) On-state switch leakage current VI = VCC or GND, VINH = VIH (see Figure 3) 5.5 V ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 5.5 V 20 20 μA CIC Control input capacitance 2 pF CIS Common terminal capacitance 8.2 pF COS Switch terminal capacitance 5.6 pF CF Feedthrough capacitance 0.5 pF switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 15 pF (see Figure 4) 2.5 10 16 16 ns tPZH tPZL Enable delay time INH COM or Yn CL = 15 pF (see Figure 5) 7.6 18 23 23 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 15 pF (see Figure 5) 7.7 18 23 23 ns tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 50 pF (see Figure 4) 4.4 12 18 18 ns tPZH tPZL Enable delay time INH COM or Yn CL = 50 pF (see Figure 5) 8.8 28 35 35 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 50 pF (see Figure 5) 11.7 28 35 35 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 15 pF (see Figure 4) 1.6 6 10 10 ns tPZH tPZL Enable delay time INH COM or Yn CL = 15 pF (see Figure 5) 5.3 12 15 15 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 15 pF (see Figure 5) 6.1 12 15 15 ns tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 50 pF (see Figure 4) 2.9 9 12 12 ns tPZH tPZL Enable delay time INH COM or Yn CL = 50 pF (see Figure 5) 6.1 20 25 25 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 50 pF (see Figure 5) 8.9 20 25 25 ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) PARAMETER FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 15 pF (see Figure 4) 0.9 4 7 7 ns tPZH tPZL Enable delay time INH COM or Yn CL = 15 pF (see Figure 5) 3.8 8 10 10 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 15 pF (see Figure 5) 4.6 8 10 10 ns tPLH tPHL Propagation delay time COM or Yn Yn or COM CL = 50 pF (see Figure 4) 1.8 6 8 8 ns tPZH tPZL Enable delay time INH COM or Yn CL = 50 pF (see Figure 5) 4.3 14 18 18 ns tPHZ tPLZ Disable delay time INH COM or Yn CL = 50 pF (see Figure 5) 6.3 14 18 18 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 analog switch characteristics PARAMETER FROM TO TEST CONDITIONS V TA = 25°C UNIT (INPUT) (OUTPUT) VCC TYP CL = 50 pF, 2.3 V 30 Frequency response COM or Yn Yn or COM L p , RL = 600 Ω, fi = 1 MHz (sine wave) 3 V 35 MHz (switch on) fin (see Note 6 and Figure 6) 4.5 V 50 CL = 50 pF, 2.3 V −45 Crosstalk COM or Yn Yn or COM p , RL = 600 Ω, fin = 1 MHz (sine wave) 3 V −45 dB (between any switches) (see Note 7 and Figure 7) 4.5 V −45 CL = 50 pF, 2.3 V 20 Crosstalk (control input to signal output) INH COM or Yn p , RL = 600 Ω, fin = 1 MHz (square wave) 3 V 35 mV (see Figure 8) 4.5 V 65 CL = 50 pF, 2.3 V −45 Feedthrough attenuation COM or Yn Yn or COM p , RL = 600 Ω, fin = 1 MHz 3 V −45 dB (switch off) (see Note 7 and Figure 9) 4.5 V −45 CL = 50 pF, RL = 10 kΩ VI = 2 Vp-p 2.3 V 0.1 Sine-wave distortion COM or Yn Yn or COM kΩ, fin = 1 kHz ( i ) VI = 2.5 Vp-p 3 V 0.1 % sine wave) (see Figure 10) VI = 4 Vp-p 4.5 V 0.1 NOTES: 6. Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB. 7. Adjust fin voltage to obtain 0-dBm input. operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz 5.3 pF PARAMETER MEASUREMENT INFORMATION VCC VI = VCC or GND VINH = VIL 2 mA VO ron VI – VO 2 10–3 VI − VO VCC GND (ON) V Figure 1. On-State Resistance Test Circuit SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PARAMETER MEASUREMENT INFORMATION VINH = VIH VI VO Condition 1: VI = 0, VO = VCC Condition 2: VI = VCC, VO = 0 A VCC VCC GND (OFF) Figure 2. Off-State Switch Leakage-Current Test Circuit VCC VINH = VIL VI Open VCC GND A (ON) VI = VCC or GND Figure 3. On-State Switch Leakage-Current Test Circuit VCC VINH = VIL Input Output 50 Ω CL VCC GND (ON) Figure 4. Propagation Delay Time, Signal Input to Signal Output SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION CL VCC VO TEST CIRCUIT VOLTAGE WAVEFORMS 1 kΩ S1 S2 tPLZ/tPZL tPHZ/tPZH GND VCC TEST S1 S2 VCC GND VINH 50 Ω 50% VOL + 0.3 V tPZH tPHZ 50% 50% 50% tPZL 50% VCC VO 50% 0 V VOL VINH (tPZL, tPZH) (tPLZ, tPHZ) VCC VO 0 V VOL VINH VCC 0 V VOH VCC 0 V ≈0 V VOH VOH − 0.3 V ≈0 V ≈VCC ≈VCC GND VCC VI tPLZ Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output VO RL CL VCC 50 Ω fin VINH = GND 0.1 μF VCC GND (ON) NOTE A: fin is a sine wave. VCC/2 Figure 6. Frequency Response (Switch On) SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION VO1 RL CL VCC 50 Ω fin VCC/2 VINH = GND 0.1 μF VO2 VCC VCC/2 VINH = VCC 600 Ω VCC GND (ON) VCC GND (OFF) 600 Ω RL CL fin Figure 7. Crosstalk Between Any Two Switches VO VCC VCC GND RL CL VCC/2 VCC/2 50 Ω VINH 600 Ω Figure 8. Crosstalk Between Control Input and Switch Output VO RL CL VCC VCC/2 VINH = VCC 0.1 μF fin VCC/2 50 Ω 600 Ω VCC GND (OFF) Figure 9. Feedthrough Attenuation (Switch Off) SN54LV4053A, SN74LV4053A TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS430K − MAY 1999 − REVISED APRIL 2005 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VO RL CL VCC VCC/2 VINH = GND 10 μF fin VCC GND (ON) 600 Ω 10 μF Figure 10. Sine-Wave Distortion PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LV4053AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053ADBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A SN74LV4053AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74LV4053AN SN74LV4053ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74LV4053AN SN74LV4053ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 74LV4053A SN74LV4053APW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A SN74LV4053APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LV4053ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LW053A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN74LV4053A : PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 3 • Automotive: SN74LV4053A-Q1 • Enhanced Product: SN74LV4053A-EP NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74LV4053ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV4053ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV4053ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4053ADR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4053ADRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4053ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV4053APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4053APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4053APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4053APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4053ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV4053ADBR SSOP DB 16 2000 367.0 367.0 38.0 SN74LV4053ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV4053ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV4053ADR SOIC D 16 2500 364.0 364.0 27.0 SN74LV4053ADRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74LV4053ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV4053APWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV4053APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV4053APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV4053APWT TSSOP PW 16 250 367.0 367.0 35.0 SN74LV4053ARGYR VQFN RGY 16 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 14 3,70 3,50 4,90 5,10 20 DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 1 12 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 16 24 38 4,90 3,70 5,10 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 56 9,60 9,80 48 0,08 0,40 0,07 M 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. 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It allows you to program, debug, and analyze your applications using its unique streaming trace technology. ULINKpro, together with MDK-ARM, provides extended on-the-fly debug capabilities for Cortex-M devices. You are able to control the processor, set breakpoints, and read/write memory contents, all while the processor is running at full speed. High-Speed data and instruction trace are streamed directly to your PC enabling you to analyze detailed program behaviour. Features Supports ARM7, ARM9, Cortex-M0, Cortex-M1, Cortex-M3, and Cortex-M4 devices JTAG support for ARM7, ARM9, and Cortex-M Serial Wire Debug (SWD) support for Cortex-M Serial Wire Viewer (SWV) Data and Event Trace for Cortex-M up to 100Mbit/s (Manchester mode) Instruction Trace (ETM) for Cortex-M3 and Cortex-M4 up to 800Mbit/s Unique Streaming Trace direct to your PC, provides unlimited trace buffer JTAG Clock Speed up to 50MHz Supports Cortex-M devices running at up to 200MHz High-Speed Memory Read/Write up to 1MBytes/sec Seamless integration with the Keil μVision IDE & Debugger Wide target voltage range: 1.2V - 3.3V, 5V tolerant Support for 5V only devices using optional 5V Adapter Optional Isolation Adapter provides electrical isolation from the target system USB 2.0 High-Speed connection USB powered (no power supply required) Target Connectors 10-pin (0.05") - Cortex Debug Connector 20-pin (0.10") - ARM Standard JTAG Connector 20-pin (0.05") - Cortex Debug+ETM Connector The unique streaming trace capabilities of ULINKpro delivers sophisticated analysis features such as: Complete Code Coverage information about your program's execution ensures thorough application testing and verification Performance Analysis using the Execution Profiler and Performance Analyzer enable you to identify program bottlenecks, optimize your application, and to isolate problems Streaming instruction trace requires the target device to have ETM (Embedded Trace Macrocell) www.element14.com www.farnell.com www.newark.com Page <1> V1.0 30/07/13 Raspberry PI Heat Sink Kit The Farnell Raspberry PI heat sink kit will ensure your Raspberry PI remains cool with no need for Fans. They will also help extend the life of your Raspberry PI and thereby reduce hardware failures. The heat sink kit comprises of 3 high quality Pressfin heat sinks which are designed to fit the 3 main heat sources on the Raspberry PI. Included in the kit is a 30mm × 30mm piece of thermal adhesive tape to securely fix the heat sinks in place and to ensure a good thermal transfer bond. Dimensions : Millimetres Important Notice : This data sheet and its contents (the “Information”) belong to the members of the Premier Farnell group of companies (the “Group”) or are licensed to it. No licence is granted for the use of it other than for information purposes in connection with the products to which it relates. No licence of any intellectual property rights is granted. The Information is subject to change without notice and replaces all data sheets previously supplied. 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Part Number Table Description Part Number Raspberry PI Heat Sink Kit 2319947 Raspberry Pi Power Supply UK version Features: Built specifically for use with Raspberry Pi Class II design 5vdc 1A output via Micro USB Energy efficienct to ErP stage 2 ĞƐĐƌŝƉƟŽŶ͗ This 5vdc 1A UK Micro USB power supply is manufactured specifically for use with the Raspberry Pi device. It offers a highly efficient output ŵĞĞƟŶŐ ůĂƚĞƐƚ ƌW ƐƚĂŐĞ Ϯ ƌĞƋƵŝƌĞŵĞŶƚƐ ĂŶĚ ŝƐ ƐĂĨĞƚLJ ĂƉƉƌŽǀ ĞĚ͘ dŚŝƐ unit has a fixed UK pin and a 1.8 metre output cable and features ƐŚŽƌƚ ĐŝƌĐƵŝƚ ĂŶĚ Žǀ Ğƌ ĐƵƌƌĞŶƚ ƉƌŽƚĞĐƟŽŶ ĂƐ ƐƚĂŶĚĂƌĚ͘ dŚŝƐ ZĂƐƉďĞƌƌLJ Pi power supply has M.T.B.F of 50K hours at 25 degrees C. Part Number PW03060 Output 5vdc 1A maximum Current Min. 0.01A WŽǁ Ğƌ ;ǁ ĂƩ ƐͿ 5W Line Reg +/-5% at rated load dŽƚĂů K ƵƚƉƵƚ ZĞŐƵůĂƟŽŶ +/-5 % at 0—100% load Ripple & Noise (mV p-p) 200mV P-P WƌŽƚĞĐƟŽŶƐ Over Current and Short Circuit Case Size 54 x 50 x 42mm Weight (approx.) 70g DC Cord 1.8 Metres DC Plug Micro USB Rated Input Voltage 100-240Vac Full Input Voltage Range 90-264Vac Rated Frequency 50-60Hz Full Frequency Range 47-63Hz Efficiency 68.17% Leakage Current shall not exceed 0.25mA Input Power 7.72W max Input Current (RMS Max.) 0.18A max Hi-Pot Spec 3000Vac 10mA 1 min. (I.P. to O.P.) E Ž ůŽĂĚ ƉŽǁ Ğƌ ĐŽŶƐƵŵƉƟŽŶ 0.3W max K ƉĞƌĂƟŶŐ dĞŵƉĞƌĂƚƵƌĞ 0 to 40 degrees C Storage Temperature -20 to 80 degrees C K ƉĞƌĂƟŶŐ , ƵŵŝĚŝƚLJ 10% to 90% Safety Approvals BS EN60950-1 / CE marked EMC Standards EN55022:2006+A1:2007 / EN6100-3-2 / EN6100-3-3 Pb-free Yes RoHS Compliant MTBF 50K Hours at 25 degrees C See mechanical drawing and DC cable drawing on page 2. Full spec sheet on this PSU is available on request. Premier Farnell Ltd accepts ŶŽ ƌĞƐƉŽŶƐŝďŝůŝƚLJ ĨŽƌ ƚLJƉŽŐƌĂƉŚŝĐĂů ĞƌƌŽƌƐ ŝŶ ƚŚĞ ƉƌŽĚƵĐƟŽŶ ŽĨ ƚŚŝƐ ůĞĂŇĞƚ͘ WƌŽĚƵĐƚ ƐƉĞĐŝĮ ĐĂƟŽŶƐ ĂƌĞ ƐƵďũĞĐƚ ƚŽ ĐŚĂŶŐĞ ǁ ŝƚŚŽƵƚ ŶŽƟĐĞ Raspberry Pi Power Supply UK version Mechanical drawing: Output connector Keyboard, Mouse and Cable Bundles for the Raspberry Pi Kit Contents: HDMI Bundle DVI Bundle RPI-CABLE+ACC/HDMI RPI-CABLE+ACC/DVI Mini QWERTY Keyboard Optical USB Mouse 3.5mm Stereo Jack Plug Cable – 2m Stereo Phono (RCA) to 3.5mm Stereo Jack Plug Cable – 1.8m Cat5e Patch Cable, RJ45 Plug to RJ45 Plug – 3m High Speed HDMI Cable – 2m HDMI to DVI Cable – 2m LM3S6952 Microcontroller DATA SHEET DS-LM3S6952-1972 Copyright © 2007 Luminary Micro, Inc. PRELIMINARY Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 108 Wild Basin, Suite 350 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com 2 November 30, 2007 Preliminary Table of Contents About This Document .................................................................................................................... 20 Audience .............................................................................................................................................. 20 About This Manual ................................................................................................................................ 20 Related Documents ............................................................................................................................... 20 Documentation Conventions .................................................................................................................. 20 1 Architectural Overview ...................................................................................................... 22 1.1 Product Features ...................................................................................................................... 22 1.2 Target Applications .................................................................................................................... 28 1.3 High-Level Block Diagram ......................................................................................................... 29 1.4 Functional Overview .................................................................................................................. 29 1.4.1 ARM Cortex™-M3 ..................................................................................................................... 30 1.4.2 Motor Control Peripherals .......................................................................................................... 30 1.4.3 Analog Peripherals .................................................................................................................... 31 1.4.4 Serial Communications Peripherals ............................................................................................ 32 1.4.5 System Peripherals ................................................................................................................... 33 1.4.6 Memory Peripherals .................................................................................................................. 34 1.4.7 Additional Features ................................................................................................................... 35 1.4.8 Hardware Details ...................................................................................................................... 35 2 ARM Cortex-M3 Processor Core ...................................................................................... 37 2.1 Block Diagram .......................................................................................................................... 38 2.2 Functional Description ............................................................................................................... 38 2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 38 2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 39 2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 39 2.2.4 ROM Table ............................................................................................................................... 39 2.2.5 Memory Protection Unit (MPU) ................................................................................................... 39 2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 39 3 Memory Map ....................................................................................................................... 43 4 Interrupts ............................................................................................................................ 45 5 JTAG Interface .................................................................................................................... 48 5.1 Block Diagram .......................................................................................................................... 49 5.2 Functional Description ............................................................................................................... 49 5.2.1 JTAG Interface Pins .................................................................................................................. 50 5.2.2 JTAG TAP Controller ................................................................................................................. 51 5.2.3 Shift Registers .......................................................................................................................... 52 5.2.4 Operational Considerations ........................................................................................................ 52 5.3 Initialization and Configuration ................................................................................................... 55 5.4 Register Descriptions ................................................................................................................ 55 5.4.1 Instruction Register (IR) ............................................................................................................. 55 5.4.2 Data Registers .......................................................................................................................... 57 6 System Control ................................................................................................................... 59 6.1 Functional Description ............................................................................................................... 59 6.1.1 Device Identification .................................................................................................................. 59 6.1.2 Reset Control ............................................................................................................................ 59 November 30, 2007 3 Preliminary LM3S6952 Microcontroller 6.1.3 Power Control ........................................................................................................................... 62 6.1.4 Clock Control ............................................................................................................................ 62 6.1.5 System Control ......................................................................................................................... 64 6.2 Initialization and Configuration ................................................................................................... 65 6.3 Register Map ............................................................................................................................ 65 6.4 Register Descriptions ................................................................................................................ 66 7 Hibernation Module .......................................................................................................... 120 7.1 Block Diagram ........................................................................................................................ 121 7.2 Functional Description ............................................................................................................. 121 7.2.1 Register Access Timing ........................................................................................................... 121 7.2.2 Clock Source .......................................................................................................................... 122 7.2.3 Battery Management ............................................................................................................... 122 7.2.4 Real-Time Clock ...................................................................................................................... 122 7.2.5 Non-Volatile Memory ............................................................................................................... 123 7.2.6 Power Control ......................................................................................................................... 123 7.2.7 Interrupts and Status ............................................................................................................... 123 7.3 Initialization and Configuration ................................................................................................. 124 7.3.1 Initialization ............................................................................................................................. 124 7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 124 7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 124 7.3.4 External Wake-Up from Hibernation .......................................................................................... 125 7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 125 7.4 Register Map .......................................................................................................................... 125 7.5 Register Descriptions .............................................................................................................. 126 8 Internal Memory ............................................................................................................... 139 8.1 Block Diagram ........................................................................................................................ 139 8.2 Functional Description ............................................................................................................. 139 8.2.1 SRAM Memory ........................................................................................................................ 139 8.2.2 Flash Memory ......................................................................................................................... 140 8.3 Flash Memory Initialization and Configuration ........................................................................... 141 8.3.1 Flash Programming ................................................................................................................. 141 8.3.2 Nonvolatile Register Programming ........................................................................................... 142 8.4 Register Map .......................................................................................................................... 142 8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 143 8.6 Flash Register Descriptions (System Control Offset) .................................................................. 150 9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 163 9.1 Functional Description ............................................................................................................. 163 9.1.1 Data Control ........................................................................................................................... 164 9.1.2 Interrupt Control ...................................................................................................................... 165 9.1.3 Mode Control .......................................................................................................................... 166 9.1.4 Commit Control ....................................................................................................................... 166 9.1.5 Pad Control ............................................................................................................................. 166 9.1.6 Identification ........................................................................................................................... 166 9.2 Initialization and Configuration ................................................................................................. 166 9.3 Register Map .......................................................................................................................... 168 9.4 Register Descriptions .............................................................................................................. 169 4 November 30, 2007 Preliminary Table of Contents 10 General-Purpose Timers ................................................................................................. 204 10.1 Block Diagram ........................................................................................................................ 204 10.2 Functional Description ............................................................................................................. 205 10.2.1 GPTM Reset Conditions .......................................................................................................... 205 10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206 10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207 10.3 Initialization and Configuration ................................................................................................. 211 10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211 10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212 10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212 10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213 10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213 10.3.6 16-Bit PWM Mode ................................................................................................................... 214 10.4 Register Map .......................................................................................................................... 214 10.5 Register Descriptions .............................................................................................................. 215 11 Watchdog Timer ............................................................................................................... 240 11.1 Block Diagram ........................................................................................................................ 240 11.2 Functional Description ............................................................................................................. 240 11.3 Initialization and Configuration ................................................................................................. 241 11.4 Register Map .......................................................................................................................... 241 11.5 Register Descriptions .............................................................................................................. 242 12 Analog-to-Digital Converter (ADC) ................................................................................. 263 12.1 Block Diagram ........................................................................................................................ 264 12.2 Functional Description ............................................................................................................. 264 12.2.1 Sample Sequencers ................................................................................................................ 264 12.2.2 Module Control ........................................................................................................................ 265 12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266 12.2.4 Analog-to-Digital Converter ...................................................................................................... 266 12.2.5 Test Modes ............................................................................................................................. 266 12.2.6 Internal Temperature Sensor .................................................................................................... 266 12.3 Initialization and Configuration ................................................................................................. 267 12.3.1 Module Initialization ................................................................................................................. 267 12.3.2 Sample Sequencer Configuration ............................................................................................. 267 12.4 Register Map .......................................................................................................................... 268 12.5 Register Descriptions .............................................................................................................. 269 13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296 13.1 Block Diagram ........................................................................................................................ 297 13.2 Functional Description ............................................................................................................. 297 13.2.1 Transmit/Receive Logic ........................................................................................................... 297 13.2.2 Baud-Rate Generation ............................................................................................................. 298 13.2.3 Data Transmission .................................................................................................................. 299 13.2.4 Serial IR (SIR) ......................................................................................................................... 299 13.2.5 FIFO Operation ....................................................................................................................... 300 13.2.6 Interrupts ................................................................................................................................ 300 13.2.7 Loopback Operation ................................................................................................................ 301 13.2.8 IrDA SIR block ........................................................................................................................ 301 13.3 Initialization and Configuration ................................................................................................. 301 13.4 Register Map .......................................................................................................................... 302 November 30, 2007 5 Preliminary LM3S6952 Microcontroller 13.5 Register Descriptions .............................................................................................................. 303 14 Synchronous Serial Interface (SSI) ................................................................................ 337 14.1 Block Diagram ........................................................................................................................ 337 14.2 Functional Description ............................................................................................................. 337 14.2.1 Bit Rate Generation ................................................................................................................. 338 14.2.2 FIFO Operation ....................................................................................................................... 338 14.2.3 Interrupts ................................................................................................................................ 338 14.2.4 Frame Formats ....................................................................................................................... 339 14.3 Initialization and Configuration ................................................................................................. 346 14.4 Register Map .......................................................................................................................... 347 14.5 Register Descriptions .............................................................................................................. 348 15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374 15.1 Block Diagram ........................................................................................................................ 374 15.2 Functional Description ............................................................................................................. 374 15.2.1 I2C Bus Functional Overview .................................................................................................... 375 15.2.2 Available Speed Modes ........................................................................................................... 377 15.2.3 Interrupts ................................................................................................................................ 378 15.2.4 Loopback Operation ................................................................................................................ 378 15.2.5 Command Sequence Flow Charts ............................................................................................ 379 15.3 Initialization and Configuration ................................................................................................. 385 15.4 I2C Register Map ..................................................................................................................... 386 15.5 Register Descriptions (I2C Master) ........................................................................................... 387 15.6 Register Descriptions (I2C Slave) ............................................................................................. 400 16 Ethernet Controller .......................................................................................................... 409 16.1 Block Diagram ........................................................................................................................ 410 16.2 Functional Description ............................................................................................................. 410 16.2.1 Internal MII Operation .............................................................................................................. 410 16.2.2 PHY Configuration/Operation ................................................................................................... 411 16.2.3 MAC Configuration/Operation .................................................................................................. 412 16.2.4 Interrupts ................................................................................................................................ 414 16.3 Initialization and Configuration ................................................................................................. 415 16.4 Ethernet Register Map ............................................................................................................. 415 16.5 Ethernet MAC Register Descriptions ......................................................................................... 417 16.6 MII Management Register Descriptions ..................................................................................... 434 17 Analog Comparators ....................................................................................................... 453 17.1 Block Diagram ........................................................................................................................ 454 17.2 Functional Description ............................................................................................................. 454 17.2.1 Internal Reference Programming .............................................................................................. 456 17.3 Initialization and Configuration ................................................................................................. 457 17.4 Register Map .......................................................................................................................... 457 17.5 Register Descriptions .............................................................................................................. 458 18 Pulse Width Modulator (PWM) ........................................................................................ 466 18.1 Block Diagram ........................................................................................................................ 466 18.2 Functional Description ............................................................................................................. 466 18.2.1 PWM Timer ............................................................................................................................. 466 18.2.2 PWM Comparators .................................................................................................................. 467 18.2.3 PWM Signal Generator ............................................................................................................ 468 6 November 30, 2007 Preliminary Table of Contents 18.2.4 Dead-Band Generator ............................................................................................................. 469 18.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 469 18.2.6 Synchronization Methods ......................................................................................................... 469 18.2.7 Fault Conditions ...................................................................................................................... 470 18.2.8 Output Control Block ............................................................................................................... 470 18.3 Initialization and Configuration ................................................................................................. 470 18.4 Register Map .......................................................................................................................... 471 18.5 Register Descriptions .............................................................................................................. 472 19 Quadrature Encoder Interface (QEI) ............................................................................... 501 19.1 Block Diagram ........................................................................................................................ 501 19.2 Functional Description ............................................................................................................. 502 19.3 Initialization and Configuration ................................................................................................. 504 19.4 Register Map .......................................................................................................................... 504 19.5 Register Descriptions .............................................................................................................. 505 20 Pin Diagram ...................................................................................................................... 518 21 Signal Tables .................................................................................................................... 519 22 Operating Characteristics ............................................................................................... 533 23 Electrical Characteristics ................................................................................................ 534 23.1 DC Characteristics .................................................................................................................. 534 23.1.1 Maximum Ratings ................................................................................................................... 534 23.1.2 Recommended DC Operating Conditions .................................................................................. 534 23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 535 23.1.4 Power Specifications ............................................................................................................... 535 23.1.5 Flash Memory Characteristics .................................................................................................. 537 23.2 AC Characteristics ................................................................................................................... 537 23.2.1 Load Conditions ...................................................................................................................... 537 23.2.2 Clocks .................................................................................................................................... 537 23.2.3 Analog-to-Digital Converter ...................................................................................................... 538 23.2.4 Analog Comparator ................................................................................................................. 539 23.2.5 I2C ......................................................................................................................................... 539 23.2.6 Ethernet Controller .................................................................................................................. 540 23.2.7 Hibernation Module ................................................................................................................. 543 23.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 543 23.2.9 JTAG and Boundary Scan ........................................................................................................ 545 23.2.10 General-Purpose I/O ............................................................................................................... 546 23.2.11 Reset ..................................................................................................................................... 547 24 Package Information ........................................................................................................ 549 A Serial Flash Loader .......................................................................................................... 551 A.1 Serial Flash Loader ................................................................................................................. 551 A.2 Interfaces ............................................................................................................................... 551 A.2.1 UART ..................................................................................................................................... 551 A.2.2 SSI ......................................................................................................................................... 551 A.3 Packet Handling ...................................................................................................................... 552 A.3.1 Packet Format ........................................................................................................................ 552 A.3.2 Sending Packets ..................................................................................................................... 552 A.3.3 Receiving Packets ................................................................................................................... 552 November 30, 2007 7 Preliminary LM3S6952 Microcontroller A.4 Commands ............................................................................................................................. 553 A.4.1 COMMAND_PING (0X20) ........................................................................................................ 553 A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 553 A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 553 A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 554 A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 554 A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 554 B Register Quick Reference ............................................................................................... 556 C Ordering and Contact Information ................................................................................. 575 C.1 Ordering Information ................................................................................................................ 575 C.2 Kits ......................................................................................................................................... 575 C.3 Company Information .............................................................................................................. 575 C.4 Support Information ................................................................................................................. 576 8 November 30, 2007 Preliminary Table of Contents List of Figures Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram ............................................................... 29 Figure 2-1. CPU Block Diagram ......................................................................................................... 38 Figure 2-2. TPIU Block Diagram ........................................................................................................ 39 Figure 5-1. JTAG Module Block Diagram ............................................................................................ 49 Figure 5-2. Test Access Port State Machine ....................................................................................... 52 Figure 5-3. IDCODE Register Format ................................................................................................. 57 Figure 5-4. BYPASS Register Format ................................................................................................ 58 Figure 5-5. Boundary Scan Register Format ....................................................................................... 58 Figure 6-1. External Circuitry to Extend Reset .................................................................................... 60 Figure 7-1. Hibernation Module Block Diagram ................................................................................. 121 Figure 8-1. Flash Block Diagram ...................................................................................................... 139 Figure 9-1. GPIO Port Block Diagram ............................................................................................... 164 Figure 9-2. GPIODATA Write Example ............................................................................................. 165 Figure 9-3. GPIODATA Read Example ............................................................................................. 165 Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205 Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209 Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210 Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211 Figure 11-1. WDT Module Block Diagram .......................................................................................... 240 Figure 12-1. ADC Module Block Diagram ........................................................................................... 264 Figure 12-2. Internal Temperature Sensor Characteristic ..................................................................... 267 Figure 13-1. UART Module Block Diagram ......................................................................................... 297 Figure 13-2. UART Character Frame ................................................................................................. 298 Figure 13-3. IrDA Data Modulation ..................................................................................................... 300 Figure 14-1. SSI Module Block Diagram ............................................................................................. 337 Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 339 Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340 Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341 Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341 Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342 Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343 Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343 Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344 Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345 Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346 Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346 Figure 15-1. I2C Block Diagram ......................................................................................................... 374 Figure 15-2. I2C Bus Configuration .................................................................................................... 375 Figure 15-3. START and STOP Conditions ......................................................................................... 375 Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376 Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376 Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376 Figure 15-7. Master Single SEND ...................................................................................................... 379 Figure 15-8. Master Single RECEIVE ................................................................................................. 380 Figure 15-9. Master Burst SEND ....................................................................................................... 381 November 30, 2007 9 Preliminary LM3S6952 Microcontroller Figure 15-10. Master Burst RECEIVE .................................................................................................. 382 Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383 Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384 Figure 15-13. Slave Command Sequence ............................................................................................ 385 Figure 16-1. Ethernet Controller Block Diagram .................................................................................. 410 Figure 16-2. Ethernet Controller ......................................................................................................... 410 Figure 16-3. Ethernet Frame ............................................................................................................. 412 Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 454 Figure 17-2. Structure of Comparator Unit .......................................................................................... 455 Figure 17-3. Comparator Internal Reference Structure ........................................................................ 456 Figure 18-1. PWM Module Block Diagram .......................................................................................... 466 Figure 18-2. PWM Count-Down Mode ................................................................................................ 467 Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 468 Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 468 Figure 18-5. PWM Dead-Band Generator ........................................................................................... 469 Figure 19-1. QEI Block Diagram ........................................................................................................ 501 Figure 19-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 503 Figure 20-1. Pin Connection Diagram ................................................................................................ 518 Figure 23-1. Load Conditions ............................................................................................................ 537 Figure 23-2. I2C Timing ..................................................................................................................... 540 Figure 23-3. External XTLP Oscillator Characteristics ......................................................................... 542 Figure 23-4. Hibernation Module Timing ............................................................................................. 543 Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 544 Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 544 Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 545 Figure 23-8. JTAG Test Clock Input Timing ......................................................................................... 546 Figure 23-9. JTAG Test Access Port (TAP) Timing .............................................................................. 546 Figure 23-10. JTAG TRST Timing ........................................................................................................ 546 Figure 23-11. External Reset Timing (RST) .......................................................................................... 547 Figure 23-12. Power-On Reset Timing ................................................................................................. 548 Figure 23-13. Brown-Out Reset Timing ................................................................................................ 548 Figure 23-14. Software Reset Timing ................................................................................................... 548 Figure 23-15. Watchdog Reset Timing ................................................................................................. 548 Figure 24-1. 100-Pin LQFP Package .................................................................................................. 549 10 November 30, 2007 Preliminary Table of Contents List of Tables Table 1. Documentation Conventions ............................................................................................ 20 Table 3-1. Memory Map ................................................................................................................... 43 Table 4-1. Exception Types .............................................................................................................. 45 Table 4-2. Interrupts ........................................................................................................................ 46 Table 5-1. JTAG Port Pins Reset State ............................................................................................. 50 Table 5-2. JTAG Instruction Register Commands ............................................................................... 55 Table 6-1. System Control Register Map ........................................................................................... 65 Table 7-1. Hibernation Module Register Map ................................................................................... 125 Table 8-1. Flash Protection Policy Combinations ............................................................................. 141 Table 8-2. Flash Resident Registers ............................................................................................... 142 Table 8-3. Flash Register Map ........................................................................................................ 142 Table 9-1. GPIO Pad Configuration Examples ................................................................................. 167 Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 167 Table 9-3. GPIO Register Map ....................................................................................................... 168 Table 10-1. Available CCP Pins ........................................................................................................ 205 Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208 Table 10-3. Timers Register Map ...................................................................................................... 214 Table 11-1. Watchdog Timer Register Map ........................................................................................ 241 Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264 Table 12-2. ADC Register Map ......................................................................................................... 268 Table 13-1. UART Register Map ....................................................................................................... 302 Table 14-1. SSI Register Map .......................................................................................................... 347 Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 377 Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386
